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TARGET_NUCLEO_H743ZI/TOOLCHAIN_ARM_MICRO/stm32h7xx_hal_spi.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	172:65be27845400	1	/**
AnnaBridge	172:65be27845400	2	******************************************************************************
AnnaBridge	172:65be27845400	3	* @file stm32h7xx_hal_spi.h
AnnaBridge	172:65be27845400	4	* @author MCD Application Team
AnnaBridge	172:65be27845400	5	* @brief Header file of SPI HAL module.
AnnaBridge	172:65be27845400	6	******************************************************************************
AnnaBridge	172:65be27845400	7	* @attention
AnnaBridge	172:65be27845400	8	*
AnnaBridge	172:65be27845400	9	* <h2><center>© Copyright (c) 2017 STMicroelectronics.
AnnaBridge	172:65be27845400	10	* All rights reserved.</center></h2>
AnnaBridge	172:65be27845400	11	*
AnnaBridge	172:65be27845400	12	* This software component is licensed by ST under BSD 3-Clause license,
AnnaBridge	172:65be27845400	13	* the "License"; You may not use this file except in compliance with the
AnnaBridge	172:65be27845400	14	* License. You may obtain a copy of the License at:
AnnaBridge	172:65be27845400	15	* opensource.org/licenses/BSD-3-Clause
AnnaBridge	172:65be27845400	16	*
AnnaBridge	172:65be27845400	17	******************************************************************************
AnnaBridge	172:65be27845400	18	*/
AnnaBridge	172:65be27845400	19
AnnaBridge	172:65be27845400	20	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	172:65be27845400	21	#ifndef STM32H7xx_HAL_SPI_H
AnnaBridge	172:65be27845400	22	#define STM32H7xx_HAL_SPI_H
AnnaBridge	172:65be27845400	23
AnnaBridge	172:65be27845400	24	#ifdef __cplusplus
AnnaBridge	172:65be27845400	25	extern "C" {
AnnaBridge	172:65be27845400	26	#endif
AnnaBridge	172:65be27845400	27
AnnaBridge	172:65be27845400	28	/* Includes ------------------------------------------------------------------*/
AnnaBridge	172:65be27845400	29	#include "stm32h7xx_hal_def.h"
AnnaBridge	172:65be27845400	30
AnnaBridge	172:65be27845400	31	/** @addtogroup STM32H7xx_HAL_Driver
AnnaBridge	172:65be27845400	32	* @{
AnnaBridge	172:65be27845400	33	*/
AnnaBridge	172:65be27845400	34
AnnaBridge	172:65be27845400	35	/** @addtogroup SPI
AnnaBridge	172:65be27845400	36	* @{
AnnaBridge	172:65be27845400	37	*/
AnnaBridge	172:65be27845400	38
AnnaBridge	172:65be27845400	39	/* Exported types ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	40	/** @defgroup SPI_Exported_Types SPI Exported Types
AnnaBridge	172:65be27845400	41	* @{
AnnaBridge	172:65be27845400	42	*/
AnnaBridge	172:65be27845400	43
AnnaBridge	172:65be27845400	44	/**
AnnaBridge	172:65be27845400	45	* @brief SPI Configuration Structure definition
AnnaBridge	172:65be27845400	46	*/
AnnaBridge	172:65be27845400	47	typedef struct
AnnaBridge	172:65be27845400	48	{
AnnaBridge	172:65be27845400	49	uint32_t Mode; /*!< Specifies the SPI operating mode.
AnnaBridge	172:65be27845400	50	This parameter can be a value of @ref SPI_Mode */
AnnaBridge	172:65be27845400	51
AnnaBridge	172:65be27845400	52	uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
AnnaBridge	172:65be27845400	53	This parameter can be a value of @ref SPI_Direction */
AnnaBridge	172:65be27845400	54
AnnaBridge	172:65be27845400	55	uint32_t DataSize; /*!< Specifies the SPI data size.
AnnaBridge	172:65be27845400	56	This parameter can be a value of @ref SPI_Data_Size */
AnnaBridge	172:65be27845400	57
AnnaBridge	172:65be27845400	58	uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
AnnaBridge	172:65be27845400	59	This parameter can be a value of @ref SPI_Clock_Polarity */
AnnaBridge	172:65be27845400	60
AnnaBridge	172:65be27845400	61	uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
AnnaBridge	172:65be27845400	62	This parameter can be a value of @ref SPI_Clock_Phase */
AnnaBridge	172:65be27845400	63
AnnaBridge	172:65be27845400	64	uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
AnnaBridge	172:65be27845400	65	hardware (NSS pin) or by software using the SSI bit.
AnnaBridge	172:65be27845400	66	This parameter can be a value of @ref SPI_Slave_Select_Management */
AnnaBridge	172:65be27845400	67
AnnaBridge	172:65be27845400	68	uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
AnnaBridge	172:65be27845400	69	used to configure the transmit and receive SCK clock.
AnnaBridge	172:65be27845400	70	This parameter can be a value of @ref SPI_BaudRate_Prescaler
AnnaBridge	172:65be27845400	71	@note The communication clock is derived from the master
AnnaBridge	172:65be27845400	72	clock. The slave clock does not need to be set. */
AnnaBridge	172:65be27845400	73
AnnaBridge	172:65be27845400	74	uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
AnnaBridge	172:65be27845400	75	This parameter can be a value of @ref SPI_MSB_LSB_Transmission */
AnnaBridge	172:65be27845400	76
AnnaBridge	172:65be27845400	77	uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
AnnaBridge	172:65be27845400	78	This parameter can be a value of @ref SPI_TI_Mode */
AnnaBridge	172:65be27845400	79
AnnaBridge	172:65be27845400	80	uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
AnnaBridge	172:65be27845400	81	This parameter can be a value of @ref SPI_CRC_Calculation */
AnnaBridge	172:65be27845400	82
AnnaBridge	172:65be27845400	83	uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
AnnaBridge	172:65be27845400	84	This parameter must be an odd number between Min_Data = 0 and Max_Data = 65535 */
AnnaBridge	172:65be27845400	85
AnnaBridge	172:65be27845400	86	uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
AnnaBridge	172:65be27845400	87	This parameter can be a value of @ref SPI_CRC_length */
AnnaBridge	172:65be27845400	88
AnnaBridge	172:65be27845400	89	uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
AnnaBridge	172:65be27845400	90	This parameter can be a value of @ref SPI_NSSP_Mode
AnnaBridge	172:65be27845400	91	This mode is activated by the SSOM bit in the SPIx_CR2 register and
AnnaBridge	172:65be27845400	92	it takes effect only if the SPI interface is configured as Motorola SPI
AnnaBridge	172:65be27845400	93	master (FRF=0). */
AnnaBridge	172:65be27845400	94
AnnaBridge	172:65be27845400	95	uint32_t NSSPolarity; /*!< Specifies which level of SS input/output external signal (present on SS pin) is
AnnaBridge	172:65be27845400	96	considered as active one.
AnnaBridge	172:65be27845400	97	This parameter can be a value of @ref SPI_NSS_Polarity */
AnnaBridge	172:65be27845400	98
AnnaBridge	172:65be27845400	99	uint32_t FifoThreshold; /*!< Specifies the FIFO threshold level.
AnnaBridge	172:65be27845400	100	This parameter can be a value of @ref SPI_Fifo_Threshold */
AnnaBridge	172:65be27845400	101
AnnaBridge	172:65be27845400	102	uint32_t TxCRCInitializationPattern; /*!< Specifies the transmitter CRC initialization Pattern used for the CRC calculation.
AnnaBridge	172:65be27845400	103	This parameter can be a value of @ref SPI_CRC_Calculation_Initialization_Pattern */
AnnaBridge	172:65be27845400	104
AnnaBridge	172:65be27845400	105	uint32_t RxCRCInitializationPattern; /*!< Specifies the receiver CRC initialization Pattern used for the CRC calculation.
AnnaBridge	172:65be27845400	106	This parameter can be a value of @ref SPI_CRC_Calculation_Initialization_Pattern */
AnnaBridge	172:65be27845400	107
AnnaBridge	172:65be27845400	108	uint32_t MasterSSIdleness; /*!< Specifies an extra delay, expressed in number of SPI clock cycle periods, inserted
AnnaBridge	172:65be27845400	109	additionally between active edge of SS and first data transaction start in master mode.
AnnaBridge	172:65be27845400	110	This parameter can be a value of @ref SPI_Master_SS_Idleness */
AnnaBridge	172:65be27845400	111
AnnaBridge	172:65be27845400	112	uint32_t MasterInterDataIdleness; /*!< Specifies minimum time delay (expressed in SPI clock cycles periods) inserted between
AnnaBridge	172:65be27845400	113	two consecutive data frames in master mode
AnnaBridge	172:65be27845400	114	This parameter can be a value of @ref SPI_Master_InterData_Idleness */
AnnaBridge	172:65be27845400	115
AnnaBridge	172:65be27845400	116	uint32_t MasterReceiverAutoSusp; /*!< Control continuous SPI transfer in master receiver mode and automatic management
AnnaBridge	172:65be27845400	117	in order to avoid overrun condition.
AnnaBridge	172:65be27845400	118	This parameter can be a value of @ref SPI_Master_RX_AutoSuspend*/
AnnaBridge	172:65be27845400	119
AnnaBridge	172:65be27845400	120	uint32_t MasterKeepIOState; /*!< Control of Alternate function GPIOs state
AnnaBridge	172:65be27845400	121	This parameter can be a value of @ref SPI_Master_Keep_IO_State */
AnnaBridge	172:65be27845400	122
AnnaBridge	172:65be27845400	123	uint32_t IOSwap; /*!< Invert MISO/MOSI alternate functions
AnnaBridge	172:65be27845400	124	This parameter can be a value of @ref SPI_IO_Swap */
AnnaBridge	172:65be27845400	125
AnnaBridge	172:65be27845400	126	} SPI_InitTypeDef;
AnnaBridge	172:65be27845400	127
AnnaBridge	172:65be27845400	128	/**
AnnaBridge	172:65be27845400	129	* @brief HAL SPI State structure definition
AnnaBridge	172:65be27845400	130	*/
AnnaBridge	172:65be27845400	131	typedef enum
AnnaBridge	172:65be27845400	132	{
AnnaBridge	172:65be27845400	133	HAL_SPI_STATE_RESET = 0x00UL, /!< Peripheral not Initialized /
AnnaBridge	172:65be27845400	134	HAL_SPI_STATE_READY = 0x01UL, /!< Peripheral Initialized and ready for use /
AnnaBridge	172:65be27845400	135	HAL_SPI_STATE_BUSY = 0x02UL, /!< an internal process is ongoing /
AnnaBridge	172:65be27845400	136	HAL_SPI_STATE_BUSY_TX = 0x03UL, /!< Data Transmission process is ongoing /
AnnaBridge	172:65be27845400	137	HAL_SPI_STATE_BUSY_RX = 0x04UL, /!< Data Reception process is ongoing /
AnnaBridge	172:65be27845400	138	HAL_SPI_STATE_BUSY_TX_RX = 0x05UL, /!< Data Transmission and Reception process is ongoing /
AnnaBridge	172:65be27845400	139	HAL_SPI_STATE_ERROR = 0x06UL, /!< SPI error state /
AnnaBridge	172:65be27845400	140	HAL_SPI_STATE_ABORT = 0x07UL /!< SPI abort is ongoing /
AnnaBridge	172:65be27845400	141	} HAL_SPI_StateTypeDef;
AnnaBridge	172:65be27845400	142
AnnaBridge	172:65be27845400	143	#if defined(USE_SPI_RELOAD_TRANSFER)
AnnaBridge	172:65be27845400	144	/**
AnnaBridge	172:65be27845400	145	* @brief SPI Reload Structure definition
AnnaBridge	172:65be27845400	146	*/
AnnaBridge	172:65be27845400	147	typedef struct
AnnaBridge	172:65be27845400	148	{
AnnaBridge	172:65be27845400	149	uint8_t pTxBuffPtr; /!< Pointer to SPI Tx transfer Buffer */
AnnaBridge	172:65be27845400	150
AnnaBridge	172:65be27845400	151	uint16_t TxXferSize; /!< SPI Tx Transfer size to reload /
AnnaBridge	172:65be27845400	152
AnnaBridge	172:65be27845400	153	uint8_t pRxBuffPtr; /!< Pointer to SPI Rx transfer Buffer */
AnnaBridge	172:65be27845400	154
AnnaBridge	172:65be27845400	155	uint16_t RxXferSize; /!< SPI Rx Transfer size to reload /
AnnaBridge	172:65be27845400	156
AnnaBridge	172:65be27845400	157	uint32_t Requested; /!< SPI reload request /
AnnaBridge	172:65be27845400	158
AnnaBridge	172:65be27845400	159	} SPI_ReloadTypeDef;
AnnaBridge	172:65be27845400	160	#endif /* USE_HSPI_RELOAD_TRANSFER */
AnnaBridge	172:65be27845400	161
AnnaBridge	172:65be27845400	162	/**
AnnaBridge	172:65be27845400	163	* @brief SPI handle Structure definition
AnnaBridge	172:65be27845400	164	*/
AnnaBridge	172:65be27845400	165	typedef struct __SPI_HandleTypeDef
AnnaBridge	172:65be27845400	166	{
AnnaBridge	172:65be27845400	167	SPI_TypeDef Instance; /!< SPI registers base address */
AnnaBridge	172:65be27845400	168
AnnaBridge	172:65be27845400	169	SPI_InitTypeDef Init; /!< SPI communication parameters /
AnnaBridge	172:65be27845400	170
AnnaBridge	172:65be27845400	171	uint8_t pTxBuffPtr; /!< Pointer to SPI Tx transfer Buffer */
AnnaBridge	172:65be27845400	172
AnnaBridge	172:65be27845400	173	uint16_t TxXferSize; /!< SPI Tx Transfer size /
AnnaBridge	172:65be27845400	174
AnnaBridge	172:65be27845400	175	__IO uint16_t TxXferCount; /!< SPI Tx Transfer Counter /
AnnaBridge	172:65be27845400	176
AnnaBridge	172:65be27845400	177	uint8_t pRxBuffPtr; /!< Pointer to SPI Rx transfer Buffer */
AnnaBridge	172:65be27845400	178
AnnaBridge	172:65be27845400	179	uint16_t RxXferSize; /!< SPI Rx Transfer size /
AnnaBridge	172:65be27845400	180
AnnaBridge	172:65be27845400	181	__IO uint16_t RxXferCount; /!< SPI Rx Transfer Counter /
AnnaBridge	172:65be27845400	182
AnnaBridge	172:65be27845400	183	uint32_t CRCSize; /!< SPI CRC size used for the transfer /
AnnaBridge	172:65be27845400	184
AnnaBridge	172:65be27845400	185	void (RxISR)(struct __SPI_HandleTypeDef hspi); /!< function pointer on Rx ISR /
AnnaBridge	172:65be27845400	186
AnnaBridge	172:65be27845400	187	void (TxISR)(struct __SPI_HandleTypeDef hspi); /!< function pointer on Tx ISR /
AnnaBridge	172:65be27845400	188
AnnaBridge	172:65be27845400	189	DMA_HandleTypeDef hdmatx; /!< SPI Tx DMA Handle parameters */
AnnaBridge	172:65be27845400	190
AnnaBridge	172:65be27845400	191	DMA_HandleTypeDef hdmarx; /!< SPI Rx DMA Handle parameters */
AnnaBridge	172:65be27845400	192
AnnaBridge	172:65be27845400	193	HAL_LockTypeDef Lock; /!< Locking object /
AnnaBridge	172:65be27845400	194
AnnaBridge	172:65be27845400	195	__IO HAL_SPI_StateTypeDef State; /!< SPI communication state /
AnnaBridge	172:65be27845400	196
AnnaBridge	172:65be27845400	197	__IO uint32_t ErrorCode; /!< SPI Error code /
AnnaBridge	172:65be27845400	198
AnnaBridge	172:65be27845400	199	#if defined(USE_SPI_RELOAD_TRANSFER)
AnnaBridge	172:65be27845400	200
AnnaBridge	172:65be27845400	201	SPI_ReloadTypeDef Reload; /!< SPI reload parameters /
AnnaBridge	172:65be27845400	202
AnnaBridge	172:65be27845400	203	#endif /* USE_HSPI_RELOAD_TRANSFER */
AnnaBridge	172:65be27845400	204
AnnaBridge	172:65be27845400	205	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
AnnaBridge	172:65be27845400	206	void (* TxCpltCallback)(struct __SPI_HandleTypeDef hspi); /!< SPI Tx Completed callback */
AnnaBridge	172:65be27845400	207	void (* RxCpltCallback)(struct __SPI_HandleTypeDef hspi); /!< SPI Rx Completed callback */
AnnaBridge	172:65be27845400	208	void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef hspi); /!< SPI TxRx Completed callback */
AnnaBridge	172:65be27845400	209	void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef hspi); /!< SPI Tx Half Completed callback */
AnnaBridge	172:65be27845400	210	void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef hspi); /!< SPI Rx Half Completed callback */
AnnaBridge	172:65be27845400	211	void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef hspi); /!< SPI TxRx Half Completed callback */
AnnaBridge	172:65be27845400	212	void (* ErrorCallback)(struct __SPI_HandleTypeDef hspi); /!< SPI Error callback */
AnnaBridge	172:65be27845400	213	void (* AbortCpltCallback)(struct __SPI_HandleTypeDef hspi); /!< SPI Abort callback */
AnnaBridge	172:65be27845400	214	void (* MspInitCallback)(struct __SPI_HandleTypeDef hspi); /!< SPI Msp Init callback */
AnnaBridge	172:65be27845400	215	void (* MspDeInitCallback)(struct __SPI_HandleTypeDef hspi); /!< SPI Msp DeInit callback */
AnnaBridge	172:65be27845400	216
AnnaBridge	172:65be27845400	217	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
AnnaBridge	172:65be27845400	218	} SPI_HandleTypeDef;
AnnaBridge	172:65be27845400	219
AnnaBridge	172:65be27845400	220	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
AnnaBridge	172:65be27845400	221	/**
AnnaBridge	172:65be27845400	222	* @brief HAL SPI Callback ID enumeration definition
AnnaBridge	172:65be27845400	223	*/
AnnaBridge	172:65be27845400	224	typedef enum
AnnaBridge	172:65be27845400	225	{
AnnaBridge	172:65be27845400	226	HAL_SPI_TX_COMPLETE_CB_ID = 0x00UL, /!< SPI Tx Completed callback ID /
AnnaBridge	172:65be27845400	227	HAL_SPI_RX_COMPLETE_CB_ID = 0x01UL, /!< SPI Rx Completed callback ID /
AnnaBridge	172:65be27845400	228	HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02UL, /!< SPI TxRx Completed callback ID /
AnnaBridge	172:65be27845400	229	HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03UL, /!< SPI Tx Half Completed callback ID /
AnnaBridge	172:65be27845400	230	HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04UL, /!< SPI Rx Half Completed callback ID /
AnnaBridge	172:65be27845400	231	HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05UL, /!< SPI TxRx Half Completed callback ID /
AnnaBridge	172:65be27845400	232	HAL_SPI_ERROR_CB_ID = 0x06UL, /!< SPI Error callback ID /
AnnaBridge	172:65be27845400	233	HAL_SPI_ABORT_CB_ID = 0x07UL, /!< SPI Abort callback ID /
AnnaBridge	172:65be27845400	234	HAL_SPI_MSPINIT_CB_ID = 0x08UL, /!< SPI Msp Init callback ID /
AnnaBridge	172:65be27845400	235	HAL_SPI_MSPDEINIT_CB_ID = 0x09UL /!< SPI Msp DeInit callback ID /
AnnaBridge	172:65be27845400	236
AnnaBridge	172:65be27845400	237	} HAL_SPI_CallbackIDTypeDef;
AnnaBridge	172:65be27845400	238
AnnaBridge	172:65be27845400	239	/**
AnnaBridge	172:65be27845400	240	* @brief HAL SPI Callback pointer definition
AnnaBridge	172:65be27845400	241	*/
AnnaBridge	172:65be27845400	242	typedef void (pSPI_CallbackTypeDef)(SPI_HandleTypeDef hspi); /!< pointer to an SPI callback function /
AnnaBridge	172:65be27845400	243
AnnaBridge	172:65be27845400	244	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
AnnaBridge	172:65be27845400	245	/**
AnnaBridge	172:65be27845400	246	* @}
AnnaBridge	172:65be27845400	247	*/
AnnaBridge	172:65be27845400	248
AnnaBridge	172:65be27845400	249	/* Exported constants --------------------------------------------------------*/
AnnaBridge	172:65be27845400	250
AnnaBridge	172:65be27845400	251	/** @defgroup SPI_Exported_Constants SPI Exported Constants
AnnaBridge	172:65be27845400	252	* @{
AnnaBridge	172:65be27845400	253	*/
AnnaBridge	172:65be27845400	254
AnnaBridge	172:65be27845400	255	/** @defgroup SPI_FIFO_Type SPI FIFO Type
AnnaBridge	172:65be27845400	256	* @{
AnnaBridge	172:65be27845400	257	*/
AnnaBridge	172:65be27845400	258	#define SPI_LOWEND_FIFO_SIZE 8UL
AnnaBridge	172:65be27845400	259	#define SPI_HIGHEND_FIFO_SIZE 16UL
AnnaBridge	172:65be27845400	260	/**
AnnaBridge	172:65be27845400	261	* @}
AnnaBridge	172:65be27845400	262	*/
AnnaBridge	172:65be27845400	263
AnnaBridge	172:65be27845400	264	/** @defgroup SPI_Error_Code SPI Error Codes
AnnaBridge	172:65be27845400	265	* @{
AnnaBridge	172:65be27845400	266	*/
AnnaBridge	172:65be27845400	267	#define HAL_SPI_ERROR_NONE (0x00000000UL) /!< No error /
AnnaBridge	172:65be27845400	268	#define HAL_SPI_ERROR_MODF (0x00000001UL) /!< MODF error /
AnnaBridge	172:65be27845400	269	#define HAL_SPI_ERROR_CRC (0x00000002UL) /!< CRC error /
AnnaBridge	172:65be27845400	270	#define HAL_SPI_ERROR_OVR (0x00000004UL) /!< OVR error /
AnnaBridge	172:65be27845400	271	#define HAL_SPI_ERROR_FRE (0x00000008UL) /!< FRE error /
AnnaBridge	172:65be27845400	272	#define HAL_SPI_ERROR_DMA (0x00000010UL) /!< DMA transfer error /
AnnaBridge	172:65be27845400	273	#define HAL_SPI_ERROR_FLAG (0x00000020UL) /!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag /
AnnaBridge	172:65be27845400	274	#define HAL_SPI_ERROR_ABORT (0x00000040UL) /!< Error during SPI Abort procedure /
AnnaBridge	172:65be27845400	275	#define HAL_SPI_ERROR_UDR (0x00000080UL) /!< Underrun error /
AnnaBridge	172:65be27845400	276	#define HAL_SPI_ERROR_TIMEOUT (0x00000100UL) /!< Timeout error /
AnnaBridge	172:65be27845400	277	#define HAL_SPI_ERROR_UNKNOW (0x00000200UL) /!< Unknow error /
AnnaBridge	172:65be27845400	278	#define HAL_SPI_ERROR_NOT_SUPPORTED (0x00000400UL) /!< Requested operation not supported /
AnnaBridge	172:65be27845400	279	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
AnnaBridge	172:65be27845400	280	#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000800UL) /!< Invalid Callback error /
AnnaBridge	172:65be27845400	281	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
AnnaBridge	172:65be27845400	282	/**
AnnaBridge	172:65be27845400	283	* @}
AnnaBridge	172:65be27845400	284	*/
AnnaBridge	172:65be27845400	285
AnnaBridge	172:65be27845400	286	/** @defgroup SPI_Mode SPI Mode
AnnaBridge	172:65be27845400	287	* @{
AnnaBridge	172:65be27845400	288	*/
AnnaBridge	172:65be27845400	289	#define SPI_MODE_SLAVE (0x00000000UL)
AnnaBridge	172:65be27845400	290	#define SPI_MODE_MASTER SPI_CFG2_MASTER
AnnaBridge	172:65be27845400	291	/**
AnnaBridge	172:65be27845400	292	* @}
AnnaBridge	172:65be27845400	293	*/
AnnaBridge	172:65be27845400	294
AnnaBridge	172:65be27845400	295	/** @defgroup SPI_Direction SPI Direction Mode
AnnaBridge	172:65be27845400	296	* @{
AnnaBridge	172:65be27845400	297	*/
AnnaBridge	172:65be27845400	298	#define SPI_DIRECTION_2LINES (0x00000000UL)
AnnaBridge	172:65be27845400	299	#define SPI_DIRECTION_2LINES_TXONLY SPI_CFG2_COMM_0
AnnaBridge	172:65be27845400	300	#define SPI_DIRECTION_2LINES_RXONLY SPI_CFG2_COMM_1
AnnaBridge	172:65be27845400	301	#define SPI_DIRECTION_1LINE SPI_CFG2_COMM
AnnaBridge	172:65be27845400	302	/**
AnnaBridge	172:65be27845400	303	* @}
AnnaBridge	172:65be27845400	304	*/
AnnaBridge	172:65be27845400	305
AnnaBridge	172:65be27845400	306	/** @defgroup SPI_Data_Size SPI Data Size
AnnaBridge	172:65be27845400	307	* @{
AnnaBridge	172:65be27845400	308	*/
AnnaBridge	172:65be27845400	309	#define SPI_DATASIZE_4BIT (0x00000003UL)
AnnaBridge	172:65be27845400	310	#define SPI_DATASIZE_5BIT (0x00000004UL)
AnnaBridge	172:65be27845400	311	#define SPI_DATASIZE_6BIT (0x00000005UL)
AnnaBridge	172:65be27845400	312	#define SPI_DATASIZE_7BIT (0x00000006UL)
AnnaBridge	172:65be27845400	313	#define SPI_DATASIZE_8BIT (0x00000007UL)
AnnaBridge	172:65be27845400	314	#define SPI_DATASIZE_9BIT (0x00000008UL)
AnnaBridge	172:65be27845400	315	#define SPI_DATASIZE_10BIT (0x00000009UL)
AnnaBridge	172:65be27845400	316	#define SPI_DATASIZE_11BIT (0x0000000AUL)
AnnaBridge	172:65be27845400	317	#define SPI_DATASIZE_12BIT (0x0000000BUL)
AnnaBridge	172:65be27845400	318	#define SPI_DATASIZE_13BIT (0x0000000CUL)
AnnaBridge	172:65be27845400	319	#define SPI_DATASIZE_14BIT (0x0000000DUL)
AnnaBridge	172:65be27845400	320	#define SPI_DATASIZE_15BIT (0x0000000EUL)
AnnaBridge	172:65be27845400	321	#define SPI_DATASIZE_16BIT (0x0000000FUL)
AnnaBridge	172:65be27845400	322	#define SPI_DATASIZE_17BIT (0x00000010UL)
AnnaBridge	172:65be27845400	323	#define SPI_DATASIZE_18BIT (0x00000011UL)
AnnaBridge	172:65be27845400	324	#define SPI_DATASIZE_19BIT (0x00000012UL)
AnnaBridge	172:65be27845400	325	#define SPI_DATASIZE_20BIT (0x00000013UL)
AnnaBridge	172:65be27845400	326	#define SPI_DATASIZE_21BIT (0x00000014UL)
AnnaBridge	172:65be27845400	327	#define SPI_DATASIZE_22BIT (0x00000015UL)
AnnaBridge	172:65be27845400	328	#define SPI_DATASIZE_23BIT (0x00000016UL)
AnnaBridge	172:65be27845400	329	#define SPI_DATASIZE_24BIT (0x00000017UL)
AnnaBridge	172:65be27845400	330	#define SPI_DATASIZE_25BIT (0x00000018UL)
AnnaBridge	172:65be27845400	331	#define SPI_DATASIZE_26BIT (0x00000019UL)
AnnaBridge	172:65be27845400	332	#define SPI_DATASIZE_27BIT (0x0000001AUL)
AnnaBridge	172:65be27845400	333	#define SPI_DATASIZE_28BIT (0x0000001BUL)
AnnaBridge	172:65be27845400	334	#define SPI_DATASIZE_29BIT (0x0000001CUL)
AnnaBridge	172:65be27845400	335	#define SPI_DATASIZE_30BIT (0x0000001DUL)
AnnaBridge	172:65be27845400	336	#define SPI_DATASIZE_31BIT (0x0000001EUL)
AnnaBridge	172:65be27845400	337	#define SPI_DATASIZE_32BIT (0x0000001FUL)
AnnaBridge	172:65be27845400	338	/**
AnnaBridge	172:65be27845400	339	* @}
AnnaBridge	172:65be27845400	340	*/
AnnaBridge	172:65be27845400	341
AnnaBridge	172:65be27845400	342	/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
AnnaBridge	172:65be27845400	343	* @{
AnnaBridge	172:65be27845400	344	*/
AnnaBridge	172:65be27845400	345	#define SPI_POLARITY_LOW (0x00000000UL)
AnnaBridge	172:65be27845400	346	#define SPI_POLARITY_HIGH SPI_CFG2_CPOL
AnnaBridge	172:65be27845400	347	/**
AnnaBridge	172:65be27845400	348	* @}
AnnaBridge	172:65be27845400	349	*/
AnnaBridge	172:65be27845400	350
AnnaBridge	172:65be27845400	351	/** @defgroup SPI_Clock_Phase SPI Clock Phase
AnnaBridge	172:65be27845400	352	* @{
AnnaBridge	172:65be27845400	353	*/
AnnaBridge	172:65be27845400	354	#define SPI_PHASE_1EDGE (0x00000000UL)
AnnaBridge	172:65be27845400	355	#define SPI_PHASE_2EDGE SPI_CFG2_CPHA
AnnaBridge	172:65be27845400	356	/**
AnnaBridge	172:65be27845400	357	* @}
AnnaBridge	172:65be27845400	358	*/
AnnaBridge	172:65be27845400	359
AnnaBridge	172:65be27845400	360	/** @defgroup SPI_Slave_Select_Management SPI Slave Select Management
AnnaBridge	172:65be27845400	361	* @{
AnnaBridge	172:65be27845400	362	*/
AnnaBridge	172:65be27845400	363	#define SPI_NSS_SOFT SPI_CFG2_SSM
AnnaBridge	172:65be27845400	364	#define SPI_NSS_HARD_INPUT (0x00000000UL)
AnnaBridge	172:65be27845400	365	#define SPI_NSS_HARD_OUTPUT SPI_CFG2_SSOE
AnnaBridge	172:65be27845400	366	/**
AnnaBridge	172:65be27845400	367	* @}
AnnaBridge	172:65be27845400	368	*/
AnnaBridge	172:65be27845400	369
AnnaBridge	172:65be27845400	370	/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
AnnaBridge	172:65be27845400	371	* @{
AnnaBridge	172:65be27845400	372	*/
AnnaBridge	172:65be27845400	373	#define SPI_NSS_PULSE_DISABLE (0x00000000UL)
AnnaBridge	172:65be27845400	374	#define SPI_NSS_PULSE_ENABLE SPI_CFG2_SSOM
AnnaBridge	172:65be27845400	375	/**
AnnaBridge	172:65be27845400	376	* @}
AnnaBridge	172:65be27845400	377	*/
AnnaBridge	172:65be27845400	378
AnnaBridge	172:65be27845400	379	/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
AnnaBridge	172:65be27845400	380	* @{
AnnaBridge	172:65be27845400	381	*/
AnnaBridge	172:65be27845400	382	#define SPI_BAUDRATEPRESCALER_2 (0x00000000UL)
AnnaBridge	172:65be27845400	383	#define SPI_BAUDRATEPRESCALER_4 (0x10000000UL)
AnnaBridge	172:65be27845400	384	#define SPI_BAUDRATEPRESCALER_8 (0x20000000UL)
AnnaBridge	172:65be27845400	385	#define SPI_BAUDRATEPRESCALER_16 (0x30000000UL)
AnnaBridge	172:65be27845400	386	#define SPI_BAUDRATEPRESCALER_32 (0x40000000UL)
AnnaBridge	172:65be27845400	387	#define SPI_BAUDRATEPRESCALER_64 (0x50000000UL)
AnnaBridge	172:65be27845400	388	#define SPI_BAUDRATEPRESCALER_128 (0x60000000UL)
AnnaBridge	172:65be27845400	389	#define SPI_BAUDRATEPRESCALER_256 (0x70000000UL)
AnnaBridge	172:65be27845400	390	/**
AnnaBridge	172:65be27845400	391	* @}
AnnaBridge	172:65be27845400	392	*/
AnnaBridge	172:65be27845400	393
AnnaBridge	172:65be27845400	394	/** @defgroup SPI_MSB_LSB_Transmission SPI MSB LSB Transmission
AnnaBridge	172:65be27845400	395	* @{
AnnaBridge	172:65be27845400	396	*/
AnnaBridge	172:65be27845400	397	#define SPI_FIRSTBIT_MSB (0x00000000UL)
AnnaBridge	172:65be27845400	398	#define SPI_FIRSTBIT_LSB SPI_CFG2_LSBFRST
AnnaBridge	172:65be27845400	399	/**
AnnaBridge	172:65be27845400	400	* @}
AnnaBridge	172:65be27845400	401	*/
AnnaBridge	172:65be27845400	402
AnnaBridge	172:65be27845400	403	/** @defgroup SPI_TI_Mode SPI TI Mode
AnnaBridge	172:65be27845400	404	* @{
AnnaBridge	172:65be27845400	405	*/
AnnaBridge	172:65be27845400	406	#define SPI_TIMODE_DISABLE (0x00000000UL)
AnnaBridge	172:65be27845400	407	#define SPI_TIMODE_ENABLE SPI_CFG2_SP_0
AnnaBridge	172:65be27845400	408	/**
AnnaBridge	172:65be27845400	409	* @}
AnnaBridge	172:65be27845400	410	*/
AnnaBridge	172:65be27845400	411
AnnaBridge	172:65be27845400	412	/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
AnnaBridge	172:65be27845400	413	* @{
AnnaBridge	172:65be27845400	414	*/
AnnaBridge	172:65be27845400	415	#define SPI_CRCCALCULATION_DISABLE (0x00000000UL)
AnnaBridge	172:65be27845400	416	#define SPI_CRCCALCULATION_ENABLE SPI_CFG1_CRCEN
AnnaBridge	172:65be27845400	417	/**
AnnaBridge	172:65be27845400	418	* @}
AnnaBridge	172:65be27845400	419	*/
AnnaBridge	172:65be27845400	420
AnnaBridge	172:65be27845400	421	/** @defgroup SPI_CRC_length SPI CRC Length
AnnaBridge	172:65be27845400	422	* @{
AnnaBridge	172:65be27845400	423	*/
AnnaBridge	172:65be27845400	424	#define SPI_CRC_LENGTH_DATASIZE (0x00000000UL)
AnnaBridge	172:65be27845400	425	#define SPI_CRC_LENGTH_4BIT (0x00030000UL)
AnnaBridge	172:65be27845400	426	#define SPI_CRC_LENGTH_5BIT (0x00040000UL)
AnnaBridge	172:65be27845400	427	#define SPI_CRC_LENGTH_6BIT (0x00050000UL)
AnnaBridge	172:65be27845400	428	#define SPI_CRC_LENGTH_7BIT (0x00060000UL)
AnnaBridge	172:65be27845400	429	#define SPI_CRC_LENGTH_8BIT (0x00070000UL)
AnnaBridge	172:65be27845400	430	#define SPI_CRC_LENGTH_9BIT (0x00080000UL)
AnnaBridge	172:65be27845400	431	#define SPI_CRC_LENGTH_10BIT (0x00090000UL)
AnnaBridge	172:65be27845400	432	#define SPI_CRC_LENGTH_11BIT (0x000A0000UL)
AnnaBridge	172:65be27845400	433	#define SPI_CRC_LENGTH_12BIT (0x000B0000UL)
AnnaBridge	172:65be27845400	434	#define SPI_CRC_LENGTH_13BIT (0x000C0000UL)
AnnaBridge	172:65be27845400	435	#define SPI_CRC_LENGTH_14BIT (0x000D0000UL)
AnnaBridge	172:65be27845400	436	#define SPI_CRC_LENGTH_15BIT (0x000E0000UL)
AnnaBridge	172:65be27845400	437	#define SPI_CRC_LENGTH_16BIT (0x000F0000UL)
AnnaBridge	172:65be27845400	438	#define SPI_CRC_LENGTH_17BIT (0x00100000UL)
AnnaBridge	172:65be27845400	439	#define SPI_CRC_LENGTH_18BIT (0x00110000UL)
AnnaBridge	172:65be27845400	440	#define SPI_CRC_LENGTH_19BIT (0x00120000UL)
AnnaBridge	172:65be27845400	441	#define SPI_CRC_LENGTH_20BIT (0x00130000UL)
AnnaBridge	172:65be27845400	442	#define SPI_CRC_LENGTH_21BIT (0x00140000UL)
AnnaBridge	172:65be27845400	443	#define SPI_CRC_LENGTH_22BIT (0x00150000UL)
AnnaBridge	172:65be27845400	444	#define SPI_CRC_LENGTH_23BIT (0x00160000UL)
AnnaBridge	172:65be27845400	445	#define SPI_CRC_LENGTH_24BIT (0x00170000UL)
AnnaBridge	172:65be27845400	446	#define SPI_CRC_LENGTH_25BIT (0x00180000UL)
AnnaBridge	172:65be27845400	447	#define SPI_CRC_LENGTH_26BIT (0x00190000UL)
AnnaBridge	172:65be27845400	448	#define SPI_CRC_LENGTH_27BIT (0x001A0000UL)
AnnaBridge	172:65be27845400	449	#define SPI_CRC_LENGTH_28BIT (0x001B0000UL)
AnnaBridge	172:65be27845400	450	#define SPI_CRC_LENGTH_29BIT (0x001C0000UL)
AnnaBridge	172:65be27845400	451	#define SPI_CRC_LENGTH_30BIT (0x001D0000UL)
AnnaBridge	172:65be27845400	452	#define SPI_CRC_LENGTH_31BIT (0x001E0000UL)
AnnaBridge	172:65be27845400	453	#define SPI_CRC_LENGTH_32BIT (0x001F0000UL)
AnnaBridge	172:65be27845400	454	/**
AnnaBridge	172:65be27845400	455	* @}
AnnaBridge	172:65be27845400	456	*/
AnnaBridge	172:65be27845400	457
AnnaBridge	172:65be27845400	458	/** @defgroup SPI_Fifo_Threshold SPI Fifo Threshold
AnnaBridge	172:65be27845400	459	* @{
AnnaBridge	172:65be27845400	460	*/
AnnaBridge	172:65be27845400	461	#define SPI_FIFO_THRESHOLD_01DATA (0x00000000UL)
AnnaBridge	172:65be27845400	462	#define SPI_FIFO_THRESHOLD_02DATA (0x00000020UL)
AnnaBridge	172:65be27845400	463	#define SPI_FIFO_THRESHOLD_03DATA (0x00000040UL)
AnnaBridge	172:65be27845400	464	#define SPI_FIFO_THRESHOLD_04DATA (0x00000060UL)
AnnaBridge	172:65be27845400	465	#define SPI_FIFO_THRESHOLD_05DATA (0x00000080UL)
AnnaBridge	172:65be27845400	466	#define SPI_FIFO_THRESHOLD_06DATA (0x000000A0UL)
AnnaBridge	172:65be27845400	467	#define SPI_FIFO_THRESHOLD_07DATA (0x000000C0UL)
AnnaBridge	172:65be27845400	468	#define SPI_FIFO_THRESHOLD_08DATA (0x000000E0UL)
AnnaBridge	172:65be27845400	469	#define SPI_FIFO_THRESHOLD_09DATA (0x00000100UL)
AnnaBridge	172:65be27845400	470	#define SPI_FIFO_THRESHOLD_10DATA (0x00000120UL)
AnnaBridge	172:65be27845400	471	#define SPI_FIFO_THRESHOLD_11DATA (0x00000140UL)
AnnaBridge	172:65be27845400	472	#define SPI_FIFO_THRESHOLD_12DATA (0x00000160UL)
AnnaBridge	172:65be27845400	473	#define SPI_FIFO_THRESHOLD_13DATA (0x00000180UL)
AnnaBridge	172:65be27845400	474	#define SPI_FIFO_THRESHOLD_14DATA (0x000001A0UL)
AnnaBridge	172:65be27845400	475	#define SPI_FIFO_THRESHOLD_15DATA (0x000001C0UL)
AnnaBridge	172:65be27845400	476	#define SPI_FIFO_THRESHOLD_16DATA (0x000001E0UL)
AnnaBridge	172:65be27845400	477	/**
AnnaBridge	172:65be27845400	478	* @}
AnnaBridge	172:65be27845400	479	*/
AnnaBridge	172:65be27845400	480
AnnaBridge	172:65be27845400	481	/** @defgroup SPI_CRC_Calculation_Initialization_Pattern SPI CRC Calculation Initialization Pattern
AnnaBridge	172:65be27845400	482	* @{
AnnaBridge	172:65be27845400	483	*/
AnnaBridge	172:65be27845400	484	#define SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN (0x00000000UL)
AnnaBridge	172:65be27845400	485	#define SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN (0x00000001UL)
AnnaBridge	172:65be27845400	486	/**
AnnaBridge	172:65be27845400	487	* @}
AnnaBridge	172:65be27845400	488	*/
AnnaBridge	172:65be27845400	489
AnnaBridge	172:65be27845400	490	/** @defgroup SPI_NSS_Polarity SPI NSS Polarity
AnnaBridge	172:65be27845400	491	* @{
AnnaBridge	172:65be27845400	492	*/
AnnaBridge	172:65be27845400	493	#define SPI_NSS_POLARITY_LOW (0x00000000UL)
AnnaBridge	172:65be27845400	494	#define SPI_NSS_POLARITY_HIGH SPI_CFG2_SSIOP
AnnaBridge	172:65be27845400	495	/**
AnnaBridge	172:65be27845400	496	* @}
AnnaBridge	172:65be27845400	497	*/
AnnaBridge	172:65be27845400	498
AnnaBridge	172:65be27845400	499	/** @defgroup SPI_Master_Keep_IO_State Keep IO State
AnnaBridge	172:65be27845400	500	* @{
AnnaBridge	172:65be27845400	501	*/
AnnaBridge	172:65be27845400	502	#define SPI_MASTER_KEEP_IO_STATE_DISABLE (0x00000000UL)
AnnaBridge	172:65be27845400	503	#define SPI_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR
AnnaBridge	172:65be27845400	504	/**
AnnaBridge	172:65be27845400	505	* @}
AnnaBridge	172:65be27845400	506	*/
AnnaBridge	172:65be27845400	507
AnnaBridge	172:65be27845400	508	/** @defgroup SPI_IO_Swap Control SPI IO Swap
AnnaBridge	172:65be27845400	509	* @{
AnnaBridge	172:65be27845400	510	*/
AnnaBridge	172:65be27845400	511	#define SPI_IO_SWAP_DISABLE (0x00000000UL)
AnnaBridge	172:65be27845400	512	#define SPI_IO_SWAP_ENABLE SPI_CFG2_IOSWP
AnnaBridge	172:65be27845400	513	/**
AnnaBridge	172:65be27845400	514	* @}
AnnaBridge	172:65be27845400	515	*/
AnnaBridge	172:65be27845400	516
AnnaBridge	172:65be27845400	517	/** @defgroup SPI_Master_SS_Idleness SPI Master SS Idleness
AnnaBridge	172:65be27845400	518	* @{
AnnaBridge	172:65be27845400	519	*/
AnnaBridge	172:65be27845400	520	#define SPI_MASTER_SS_IDLENESS_00CYCLE (0x00000000UL)
AnnaBridge	172:65be27845400	521	#define SPI_MASTER_SS_IDLENESS_01CYCLE (0x00000001UL)
AnnaBridge	172:65be27845400	522	#define SPI_MASTER_SS_IDLENESS_02CYCLE (0x00000002UL)
AnnaBridge	172:65be27845400	523	#define SPI_MASTER_SS_IDLENESS_03CYCLE (0x00000003UL)
AnnaBridge	172:65be27845400	524	#define SPI_MASTER_SS_IDLENESS_04CYCLE (0x00000004UL)
AnnaBridge	172:65be27845400	525	#define SPI_MASTER_SS_IDLENESS_05CYCLE (0x00000005UL)
AnnaBridge	172:65be27845400	526	#define SPI_MASTER_SS_IDLENESS_06CYCLE (0x00000006UL)
AnnaBridge	172:65be27845400	527	#define SPI_MASTER_SS_IDLENESS_07CYCLE (0x00000007UL)
AnnaBridge	172:65be27845400	528	#define SPI_MASTER_SS_IDLENESS_08CYCLE (0x00000008UL)
AnnaBridge	172:65be27845400	529	#define SPI_MASTER_SS_IDLENESS_09CYCLE (0x00000009UL)
AnnaBridge	172:65be27845400	530	#define SPI_MASTER_SS_IDLENESS_10CYCLE (0x0000000AUL)
AnnaBridge	172:65be27845400	531	#define SPI_MASTER_SS_IDLENESS_11CYCLE (0x0000000BUL)
AnnaBridge	172:65be27845400	532	#define SPI_MASTER_SS_IDLENESS_12CYCLE (0x0000000CUL)
AnnaBridge	172:65be27845400	533	#define SPI_MASTER_SS_IDLENESS_13CYCLE (0x0000000DUL)
AnnaBridge	172:65be27845400	534	#define SPI_MASTER_SS_IDLENESS_14CYCLE (0x0000000EUL)
AnnaBridge	172:65be27845400	535	#define SPI_MASTER_SS_IDLENESS_15CYCLE (0x0000000FUL)
AnnaBridge	172:65be27845400	536	/**
AnnaBridge	172:65be27845400	537	* @}
AnnaBridge	172:65be27845400	538	*/
AnnaBridge	172:65be27845400	539
AnnaBridge	172:65be27845400	540	/** @defgroup SPI_Master_InterData_Idleness SPI Master Inter-Data Idleness
AnnaBridge	172:65be27845400	541	* @{
AnnaBridge	172:65be27845400	542	*/
AnnaBridge	172:65be27845400	543	#define SPI_MASTER_INTERDATA_IDLENESS_00CYCLE (0x00000000UL)
AnnaBridge	172:65be27845400	544	#define SPI_MASTER_INTERDATA_IDLENESS_01CYCLE (0x00000010UL)
AnnaBridge	172:65be27845400	545	#define SPI_MASTER_INTERDATA_IDLENESS_02CYCLE (0x00000020UL)
AnnaBridge	172:65be27845400	546	#define SPI_MASTER_INTERDATA_IDLENESS_03CYCLE (0x00000030UL)
AnnaBridge	172:65be27845400	547	#define SPI_MASTER_INTERDATA_IDLENESS_04CYCLE (0x00000040UL)
AnnaBridge	172:65be27845400	548	#define SPI_MASTER_INTERDATA_IDLENESS_05CYCLE (0x00000050UL)
AnnaBridge	172:65be27845400	549	#define SPI_MASTER_INTERDATA_IDLENESS_06CYCLE (0x00000060UL)
AnnaBridge	172:65be27845400	550	#define SPI_MASTER_INTERDATA_IDLENESS_07CYCLE (0x00000070UL)
AnnaBridge	172:65be27845400	551	#define SPI_MASTER_INTERDATA_IDLENESS_08CYCLE (0x00000080UL)
AnnaBridge	172:65be27845400	552	#define SPI_MASTER_INTERDATA_IDLENESS_09CYCLE (0x00000090UL)
AnnaBridge	172:65be27845400	553	#define SPI_MASTER_INTERDATA_IDLENESS_10CYCLE (0x000000A0UL)
AnnaBridge	172:65be27845400	554	#define SPI_MASTER_INTERDATA_IDLENESS_11CYCLE (0x000000B0UL)
AnnaBridge	172:65be27845400	555	#define SPI_MASTER_INTERDATA_IDLENESS_12CYCLE (0x000000C0UL)
AnnaBridge	172:65be27845400	556	#define SPI_MASTER_INTERDATA_IDLENESS_13CYCLE (0x000000D0UL)
AnnaBridge	172:65be27845400	557	#define SPI_MASTER_INTERDATA_IDLENESS_14CYCLE (0x000000E0UL)
AnnaBridge	172:65be27845400	558	#define SPI_MASTER_INTERDATA_IDLENESS_15CYCLE (0x000000F0UL)
AnnaBridge	172:65be27845400	559	/**
AnnaBridge	172:65be27845400	560	* @}
AnnaBridge	172:65be27845400	561	*/
AnnaBridge	172:65be27845400	562
AnnaBridge	172:65be27845400	563	/** @defgroup SPI_Master_RX_AutoSuspend SPI Master Receiver AutoSuspend
AnnaBridge	172:65be27845400	564	* @{
AnnaBridge	172:65be27845400	565	*/
AnnaBridge	172:65be27845400	566	#define SPI_MASTER_RX_AUTOSUSP_DISABLE (0x00000000UL)
AnnaBridge	172:65be27845400	567	#define SPI_MASTER_RX_AUTOSUSP_ENABLE SPI_CR1_MASRX
AnnaBridge	172:65be27845400	568	/**
AnnaBridge	172:65be27845400	569	* @}
AnnaBridge	172:65be27845400	570	*/
AnnaBridge	172:65be27845400	571
AnnaBridge	172:65be27845400	572	/** @defgroup SPI_Underrun_Detection SPI Underrun Detection
AnnaBridge	172:65be27845400	573	* @{
AnnaBridge	172:65be27845400	574	*/
AnnaBridge	172:65be27845400	575	#define SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME (0x00000000UL)
AnnaBridge	172:65be27845400	576	#define SPI_UNDERRUN_DETECT_END_DATA_FRAME SPI_CFG1_UDRDET_0
AnnaBridge	172:65be27845400	577	#define SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS SPI_CFG1_UDRDET_1
AnnaBridge	172:65be27845400	578	/**
AnnaBridge	172:65be27845400	579	* @}
AnnaBridge	172:65be27845400	580	*/
AnnaBridge	172:65be27845400	581
AnnaBridge	172:65be27845400	582	/** @defgroup SPI_Underrun_Behaviour SPI Underrun Behavior
AnnaBridge	172:65be27845400	583	* @{
AnnaBridge	172:65be27845400	584	*/
AnnaBridge	172:65be27845400	585	#define SPI_UNDERRUN_BEHAV_REGISTER_PATTERN (0x00000000UL)
AnnaBridge	172:65be27845400	586	#define SPI_UNDERRUN_BEHAV_LAST_RECEIVED SPI_CFG1_UDRCFG_0
AnnaBridge	172:65be27845400	587	#define SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED SPI_CFG1_UDRCFG_1
AnnaBridge	172:65be27845400	588	/**
AnnaBridge	172:65be27845400	589	* @}
AnnaBridge	172:65be27845400	590	*/
AnnaBridge	172:65be27845400	591
AnnaBridge	172:65be27845400	592	/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
AnnaBridge	172:65be27845400	593	* @{
AnnaBridge	172:65be27845400	594	*/
AnnaBridge	172:65be27845400	595	#define SPI_IT_RXP SPI_IER_RXPIE
AnnaBridge	172:65be27845400	596	#define SPI_IT_TXP SPI_IER_TXPIE
AnnaBridge	172:65be27845400	597	#define SPI_IT_DXP SPI_IER_DXPIE
AnnaBridge	172:65be27845400	598	#define SPI_IT_EOT SPI_IER_EOTIE
AnnaBridge	172:65be27845400	599	#define SPI_IT_TXTF SPI_IER_TXTFIE
AnnaBridge	172:65be27845400	600	#define SPI_IT_UDR SPI_IER_UDRIE
AnnaBridge	172:65be27845400	601	#define SPI_IT_OVR SPI_IER_OVRIE
AnnaBridge	172:65be27845400	602	#define SPI_IT_CRCERR SPI_IER_CRCEIE
AnnaBridge	172:65be27845400	603	#define SPI_IT_FRE SPI_IER_TIFREIE
AnnaBridge	172:65be27845400	604	#define SPI_IT_MODF SPI_IER_MODFIE
AnnaBridge	172:65be27845400	605	#define SPI_IT_TSERF SPI_IER_TSERFIE
AnnaBridge	172:65be27845400	606	#define SPI_IT_ERR (SPI_IT_UDR \| SPI_IT_OVR \| SPI_IT_FRE \| SPI_IT_MODF \| SPI_IT_CRCERR)
AnnaBridge	172:65be27845400	607	/**
AnnaBridge	172:65be27845400	608	* @}
AnnaBridge	172:65be27845400	609	*/
AnnaBridge	172:65be27845400	610
AnnaBridge	172:65be27845400	611	/** @defgroup SPI_Flags_definition SPI Flags Definition
AnnaBridge	172:65be27845400	612	* @{
AnnaBridge	172:65be27845400	613	*/
AnnaBridge	172:65be27845400	614	#define SPI_FLAG_RXP SPI_SR_RXP /* SPI status flag : Rx-Packet available flag */
AnnaBridge	172:65be27845400	615	#define SPI_FLAG_TXP SPI_SR_TXP /* SPI status flag : Tx-Packet space available flag */
AnnaBridge	172:65be27845400	616	#define SPI_FLAG_DXP SPI_SR_DXP /* SPI status flag : Duplex Packet flag */
AnnaBridge	172:65be27845400	617	#define SPI_FLAG_EOT SPI_SR_EOT /* SPI status flag : End of transfer flag */
AnnaBridge	172:65be27845400	618	#define SPI_FLAG_TXTF SPI_SR_TXTF /* SPI status flag : Transmission Transfer Filled flag */
AnnaBridge	172:65be27845400	619	#define SPI_FLAG_UDR SPI_SR_UDR /* SPI Error flag : Underrun flag */
AnnaBridge	172:65be27845400	620	#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag : Overrun flag */
AnnaBridge	172:65be27845400	621	#define SPI_FLAG_CRCERR SPI_SR_CRCE /* SPI Error flag : CRC error flag */
AnnaBridge	172:65be27845400	622	#define SPI_FLAG_FRE SPI_SR_TIFRE /* SPI Error flag : TI mode frame format error flag */
AnnaBridge	172:65be27845400	623	#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag : Mode fault flag */
AnnaBridge	172:65be27845400	624	#define SPI_FLAG_TSERF SPI_SR_TSERF /* SPI status flag : Additional number of data reloaded flag */
AnnaBridge	172:65be27845400	625	#define SPI_FLAG_SUSP SPI_SR_SUSP /* SPI status flag : Transfer suspend complete flag */
AnnaBridge	172:65be27845400	626	#define SPI_FLAG_TXC SPI_SR_TXC /* SPI status flag : TxFIFO transmission complete flag */
AnnaBridge	172:65be27845400	627	#define SPI_FLAG_FRLVL SPI_SR_RXPLVL /* SPI status flag : Fifo reception level flag */
AnnaBridge	172:65be27845400	628	#define SPI_FLAG_RXWNE SPI_SR_RXWNE /* SPI status flag : RxFIFO word not empty flag */
AnnaBridge	172:65be27845400	629	/**
AnnaBridge	172:65be27845400	630	* @}
AnnaBridge	172:65be27845400	631	*/
AnnaBridge	172:65be27845400	632
AnnaBridge	172:65be27845400	633	/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
AnnaBridge	172:65be27845400	634	* @{
AnnaBridge	172:65be27845400	635	*/
AnnaBridge	172:65be27845400	636	#define SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packets available in the RxFIFO */
AnnaBridge	172:65be27845400	637	#define SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0)
AnnaBridge	172:65be27845400	638	#define SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1)
AnnaBridge	172:65be27845400	639	#define SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 \| SPI_SR_RXPLVL_0)
AnnaBridge	172:65be27845400	640	/**
AnnaBridge	172:65be27845400	641	* @}
AnnaBridge	172:65be27845400	642	*/
AnnaBridge	172:65be27845400	643
AnnaBridge	172:65be27845400	644	/**
AnnaBridge	172:65be27845400	645	* @}
AnnaBridge	172:65be27845400	646	*/
AnnaBridge	172:65be27845400	647
AnnaBridge	172:65be27845400	648	/* Exported macros -----------------------------------------------------------*/
AnnaBridge	172:65be27845400	649	/** @defgroup SPI_Exported_Macros SPI Exported Macros
AnnaBridge	172:65be27845400	650	* @{
AnnaBridge	172:65be27845400	651	*/
AnnaBridge	172:65be27845400	652
AnnaBridge	172:65be27845400	653	/** @brief Reset SPI handle state.
AnnaBridge	172:65be27845400	654	* @param __HANDLE__: specifies the SPI Handle.
AnnaBridge	172:65be27845400	655	* This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
AnnaBridge	172:65be27845400	656	* @retval None
AnnaBridge	172:65be27845400	657	*/
AnnaBridge	172:65be27845400	658	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
AnnaBridge	172:65be27845400	659	#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \
AnnaBridge	172:65be27845400	660	(__HANDLE__)->State = HAL_SPI_STATE_RESET; \
AnnaBridge	172:65be27845400	661	(__HANDLE__)->MspInitCallback = NULL; \
AnnaBridge	172:65be27845400	662	(__HANDLE__)->MspDeInitCallback = NULL; \
AnnaBridge	172:65be27845400	663	} while(0)
AnnaBridge	172:65be27845400	664	#else
AnnaBridge	172:65be27845400	665	#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
AnnaBridge	172:65be27845400	666	#endif
AnnaBridge	172:65be27845400	667
AnnaBridge	172:65be27845400	668	/** @brief Enable the specified SPI interrupts.
AnnaBridge	172:65be27845400	669	* @param __HANDLE__: specifies the SPI Handle.
AnnaBridge	172:65be27845400	670	* This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
AnnaBridge	172:65be27845400	671	* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
AnnaBridge	172:65be27845400	672	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	673	* @arg SPI_IT_RXP : Rx-Packet available interrupt
AnnaBridge	172:65be27845400	674	* @arg SPI_IT_TXP : Tx-Packet space available interrupt
AnnaBridge	172:65be27845400	675	* @arg SPI_IT_DXP : Duplex Packet interrupt
AnnaBridge	172:65be27845400	676	* @arg SPI_IT_EOT : End of transfer interrupt
AnnaBridge	172:65be27845400	677	* @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt
AnnaBridge	172:65be27845400	678	* @arg SPI_IT_UDR : Underrun interrupt
AnnaBridge	172:65be27845400	679	* @arg SPI_IT_OVR : Overrun interrupt
AnnaBridge	172:65be27845400	680	* @arg SPI_IT_CRCERR : CRC error interrupt
AnnaBridge	172:65be27845400	681	* @arg SPI_IT_FRE : TI mode frame format error interrupt
AnnaBridge	172:65be27845400	682	* @arg SPI_IT_MODF : Mode fault interrupt
AnnaBridge	172:65be27845400	683	* @arg SPI_IT_TSERF : Additional number of data reloaded interrupt
AnnaBridge	172:65be27845400	684	* @arg SPI_IT_ERR : Error interrupt
AnnaBridge	172:65be27845400	685	* @retval None
AnnaBridge	172:65be27845400	686	*/
AnnaBridge	172:65be27845400	687	#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER \|= (__INTERRUPT__))
AnnaBridge	172:65be27845400	688
AnnaBridge	172:65be27845400	689	/** @brief Disable the specified SPI interrupts.
AnnaBridge	172:65be27845400	690	* @param __HANDLE__: specifies the SPI Handle.
AnnaBridge	172:65be27845400	691	* This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
AnnaBridge	172:65be27845400	692	* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
AnnaBridge	172:65be27845400	693	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	694	* @arg SPI_IT_RXP : Rx-Packet available interrupt
AnnaBridge	172:65be27845400	695	* @arg SPI_IT_TXP : Tx-Packet space available interrupt
AnnaBridge	172:65be27845400	696	* @arg SPI_IT_DXP : Duplex Packet interrupt
AnnaBridge	172:65be27845400	697	* @arg SPI_IT_EOT : End of transfer interrupt
AnnaBridge	172:65be27845400	698	* @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt
AnnaBridge	172:65be27845400	699	* @arg SPI_IT_UDR : Underrun interrupt
AnnaBridge	172:65be27845400	700	* @arg SPI_IT_OVR : Overrun interrupt
AnnaBridge	172:65be27845400	701	* @arg SPI_IT_CRCERR : CRC error interrupt
AnnaBridge	172:65be27845400	702	* @arg SPI_IT_FRE : TI mode frame format error interrupt
AnnaBridge	172:65be27845400	703	* @arg SPI_IT_MODF : Mode fault interrupt
AnnaBridge	172:65be27845400	704	* @arg SPI_IT_TSERF : Additional number of data reloaded interrupt
AnnaBridge	172:65be27845400	705	* @arg SPI_IT_ERR : Error interrupt
AnnaBridge	172:65be27845400	706	* @retval None
AnnaBridge	172:65be27845400	707	*/
AnnaBridge	172:65be27845400	708	#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
AnnaBridge	172:65be27845400	709
AnnaBridge	172:65be27845400	710	/** @brief Check whether the specified SPI interrupt source is enabled or not.
AnnaBridge	172:65be27845400	711	* @param __HANDLE__: specifies the SPI Handle.
AnnaBridge	172:65be27845400	712	* This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
AnnaBridge	172:65be27845400	713	* @param __INTERRUPT__: specifies the SPI interrupt source to check.
AnnaBridge	172:65be27845400	714	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	715	* @arg SPI_IT_RXP : Rx-Packet available interrupt
AnnaBridge	172:65be27845400	716	* @arg SPI_IT_TXP : Tx-Packet space available interrupt
AnnaBridge	172:65be27845400	717	* @arg SPI_IT_DXP : Duplex Packet interrupt
AnnaBridge	172:65be27845400	718	* @arg SPI_IT_EOT : End of transfer interrupt
AnnaBridge	172:65be27845400	719	* @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt
AnnaBridge	172:65be27845400	720	* @arg SPI_IT_UDR : Underrun interrupt
AnnaBridge	172:65be27845400	721	* @arg SPI_IT_OVR : Overrun interrupt
AnnaBridge	172:65be27845400	722	* @arg SPI_IT_CRCERR : CRC error interrupt
AnnaBridge	172:65be27845400	723	* @arg SPI_IT_FRE : TI mode frame format error interrupt
AnnaBridge	172:65be27845400	724	* @arg SPI_IT_MODF : Mode fault interrupt
AnnaBridge	172:65be27845400	725	* @arg SPI_IT_TSERF : Additional number of data reloaded interrupt
AnnaBridge	172:65be27845400	726	* @arg SPI_IT_ERR : Error interrupt
AnnaBridge	172:65be27845400	727	* @retval The new state of __IT__ (TRUE or FALSE).
AnnaBridge	172:65be27845400	728	*/
AnnaBridge	172:65be27845400	729	#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
AnnaBridge	172:65be27845400	730
AnnaBridge	172:65be27845400	731	/** @brief Check whether the specified SPI flag is set or not.
AnnaBridge	172:65be27845400	732	* @param __HANDLE__: specifies the SPI Handle.
AnnaBridge	172:65be27845400	733	* This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
AnnaBridge	172:65be27845400	734	* @param __FLAG__: specifies the flag to check.
AnnaBridge	172:65be27845400	735	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	736	* @arg SPI_FLAG_RXP : Rx-Packet available flag
AnnaBridge	172:65be27845400	737	* @arg SPI_FLAG_TXP : Tx-Packet space available flag
AnnaBridge	172:65be27845400	738	* @arg SPI_FLAG_DXP : Duplex Packet flag
AnnaBridge	172:65be27845400	739	* @arg SPI_FLAG_EOT : End of transfer flag
AnnaBridge	172:65be27845400	740	* @arg SPI_FLAG_TXTF : Transmission Transfer Filled flag
AnnaBridge	172:65be27845400	741	* @arg SPI_FLAG_UDR : Underrun flag
AnnaBridge	172:65be27845400	742	* @arg SPI_FLAG_OVR : Overrun flag
AnnaBridge	172:65be27845400	743	* @arg SPI_FLAG_CRCERR : CRC error flag
AnnaBridge	172:65be27845400	744	* @arg SPI_FLAG_FRE : TI mode frame format error flag
AnnaBridge	172:65be27845400	745	* @arg SPI_FLAG_MODF : Mode fault flag
AnnaBridge	172:65be27845400	746	* @arg SPI_FLAG_TSERF : Additional number of data reloaded flag
AnnaBridge	172:65be27845400	747	* @arg SPI_FLAG_SUSP : Transfer suspend complete flag
AnnaBridge	172:65be27845400	748	* @arg SPI_FLAG_TXC : TxFIFO transmission complete flag
AnnaBridge	172:65be27845400	749	* @arg SPI_FLAG_FRLVL : Fifo reception level flag
AnnaBridge	172:65be27845400	750	* @arg SPI_FLAG_RXWNE : RxFIFO word not empty flag
AnnaBridge	172:65be27845400	751	* @retval The new state of __FLAG__ (TRUE or FALSE).
AnnaBridge	172:65be27845400	752	*/
AnnaBridge	172:65be27845400	753	#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
AnnaBridge	172:65be27845400	754
AnnaBridge	172:65be27845400	755	/** @brief Clear the SPI CRCERR pending flag.
AnnaBridge	172:65be27845400	756	* @param __HANDLE__: specifies the SPI Handle.
AnnaBridge	172:65be27845400	757	* @retval None
AnnaBridge	172:65be27845400	758	*/
AnnaBridge	172:65be27845400	759	#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_CRCEC)
AnnaBridge	172:65be27845400	760
AnnaBridge	172:65be27845400	761	/** @brief Clear the SPI MODF pending flag.
AnnaBridge	172:65be27845400	762	* @param __HANDLE__: specifies the SPI Handle.
AnnaBridge	172:65be27845400	763	* @retval None
AnnaBridge	172:65be27845400	764	*/
AnnaBridge	172:65be27845400	765	#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , (uint32_t)(SPI_IFCR_MODFC));
AnnaBridge	172:65be27845400	766
AnnaBridge	172:65be27845400	767	/** @brief Clear the SPI OVR pending flag.
AnnaBridge	172:65be27845400	768	* @param __HANDLE__: specifies the SPI Handle.
AnnaBridge	172:65be27845400	769	* @retval None
AnnaBridge	172:65be27845400	770	*/
AnnaBridge	172:65be27845400	771	#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)
AnnaBridge	172:65be27845400	772
AnnaBridge	172:65be27845400	773	/** @brief Clear the SPI FRE pending flag.
AnnaBridge	172:65be27845400	774	* @param __HANDLE__: specifies the SPI Handle.
AnnaBridge	172:65be27845400	775	* @retval None
AnnaBridge	172:65be27845400	776	*/
AnnaBridge	172:65be27845400	777	#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)
AnnaBridge	172:65be27845400	778
AnnaBridge	172:65be27845400	779	/** @brief Clear the SPI UDR pending flag.
AnnaBridge	172:65be27845400	780	* @param __HANDLE__: specifies the SPI Handle.
AnnaBridge	172:65be27845400	781	* @retval None
AnnaBridge	172:65be27845400	782	*/
AnnaBridge	172:65be27845400	783	#define __HAL_SPI_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)
AnnaBridge	172:65be27845400	784
AnnaBridge	172:65be27845400	785	/** @brief Clear the SPI EOT pending flag.
AnnaBridge	172:65be27845400	786	* @param __HANDLE__: specifies the SPI Handle.
AnnaBridge	172:65be27845400	787	* @retval None
AnnaBridge	172:65be27845400	788	*/
AnnaBridge	172:65be27845400	789	#define __HAL_SPI_CLEAR_EOTFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_EOTC)
AnnaBridge	172:65be27845400	790
AnnaBridge	172:65be27845400	791	/** @brief Clear the SPI UDR pending flag.
AnnaBridge	172:65be27845400	792	* @param __HANDLE__: specifies the SPI Handle.
AnnaBridge	172:65be27845400	793	* @retval None
AnnaBridge	172:65be27845400	794	*/
AnnaBridge	172:65be27845400	795	#define __HAL_SPI_CLEAR_TXTFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TXTFC)
AnnaBridge	172:65be27845400	796
AnnaBridge	172:65be27845400	797	/** @brief Clear the SPI SUSP pending flag.
AnnaBridge	172:65be27845400	798	* @param __HANDLE__: specifies the SPI Handle.
AnnaBridge	172:65be27845400	799	* @retval None
AnnaBridge	172:65be27845400	800	*/
AnnaBridge	172:65be27845400	801	#define __HAL_SPI_CLEAR_SUSPFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_SUSPC)
AnnaBridge	172:65be27845400	802
AnnaBridge	172:65be27845400	803	/** @brief Clear the SPI TSERF pending flag.
AnnaBridge	172:65be27845400	804	* @param __HANDLE__: specifies the SPI Handle.
AnnaBridge	172:65be27845400	805	* @retval None
AnnaBridge	172:65be27845400	806	*/
AnnaBridge	172:65be27845400	807	#define __HAL_SPI_CLEAR_TSERFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TSERFC)
AnnaBridge	172:65be27845400	808
AnnaBridge	172:65be27845400	809	/** @brief Enable the SPI peripheral.
AnnaBridge	172:65be27845400	810	* @param __HANDLE__: specifies the SPI Handle.
AnnaBridge	172:65be27845400	811	* @retval None
AnnaBridge	172:65be27845400	812	*/
AnnaBridge	172:65be27845400	813	#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)
AnnaBridge	172:65be27845400	814
AnnaBridge	172:65be27845400	815	/** @brief Disable the SPI peripheral.
AnnaBridge	172:65be27845400	816	* @param __HANDLE__: specifies the SPI Handle.
AnnaBridge	172:65be27845400	817	* @retval None
AnnaBridge	172:65be27845400	818	*/
AnnaBridge	172:65be27845400	819	#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)
AnnaBridge	172:65be27845400	820	/**
AnnaBridge	172:65be27845400	821	* @}
AnnaBridge	172:65be27845400	822	*/
AnnaBridge	172:65be27845400	823
AnnaBridge	172:65be27845400	824
AnnaBridge	172:65be27845400	825	/* Include SPI HAL Extension module */
AnnaBridge	172:65be27845400	826	#include "stm32h7xx_hal_spi_ex.h"
AnnaBridge	172:65be27845400	827
AnnaBridge	172:65be27845400	828
AnnaBridge	172:65be27845400	829	/* Exported functions --------------------------------------------------------*/
AnnaBridge	172:65be27845400	830	/** @addtogroup SPI_Exported_Functions
AnnaBridge	172:65be27845400	831	* @{
AnnaBridge	172:65be27845400	832	*/
AnnaBridge	172:65be27845400	833
AnnaBridge	172:65be27845400	834	/** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
AnnaBridge	172:65be27845400	835	* @{
AnnaBridge	172:65be27845400	836	*/
AnnaBridge	172:65be27845400	837	/* Initialization/de-initialization functions ********************************/
AnnaBridge	172:65be27845400	838	HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
AnnaBridge	172:65be27845400	839	HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
AnnaBridge	172:65be27845400	840	void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
AnnaBridge	172:65be27845400	841	void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
AnnaBridge	172:65be27845400	842
AnnaBridge	172:65be27845400	843	/* Callbacks Register/UnRegister functions ***********************************/
AnnaBridge	172:65be27845400	844	#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
AnnaBridge	172:65be27845400	845	HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback);
AnnaBridge	172:65be27845400	846	HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
AnnaBridge	172:65be27845400	847	#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
AnnaBridge	172:65be27845400	848	/**
AnnaBridge	172:65be27845400	849	* @}
AnnaBridge	172:65be27845400	850	*/
AnnaBridge	172:65be27845400	851
AnnaBridge	172:65be27845400	852	/** @addtogroup SPI_Exported_Functions_Group2 IO operation functions
AnnaBridge	172:65be27845400	853	* @{
AnnaBridge	172:65be27845400	854	*/
AnnaBridge	172:65be27845400	855	/* I/O operation functions ***************************************************/
AnnaBridge	172:65be27845400	856	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout);
AnnaBridge	172:65be27845400	857	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout);
AnnaBridge	172:65be27845400	858	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size,
AnnaBridge	172:65be27845400	859	uint32_t Timeout);
AnnaBridge	172:65be27845400	860	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size);
AnnaBridge	172:65be27845400	861	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size);
AnnaBridge	172:65be27845400	862	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size);
AnnaBridge	172:65be27845400	863
AnnaBridge	172:65be27845400	864	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size);
AnnaBridge	172:65be27845400	865	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size);
AnnaBridge	172:65be27845400	866	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size);
AnnaBridge	172:65be27845400	867
AnnaBridge	172:65be27845400	868	#if defined(USE_SPI_RELOAD_TRANSFER)
AnnaBridge	172:65be27845400	869	HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size);
AnnaBridge	172:65be27845400	870	HAL_StatusTypeDef HAL_SPI_Reload_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size);
AnnaBridge	172:65be27845400	871	HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size);
AnnaBridge	172:65be27845400	872	#endif /* USE_HSPI_RELOAD_TRANSFER */
AnnaBridge	172:65be27845400	873
AnnaBridge	172:65be27845400	874	HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
AnnaBridge	172:65be27845400	875	HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
AnnaBridge	172:65be27845400	876	HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
AnnaBridge	172:65be27845400	877
AnnaBridge	172:65be27845400	878	/* Transfer Abort functions */
AnnaBridge	172:65be27845400	879	HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
AnnaBridge	172:65be27845400	880	HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
AnnaBridge	172:65be27845400	881
AnnaBridge	172:65be27845400	882	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
AnnaBridge	172:65be27845400	883	void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
AnnaBridge	172:65be27845400	884	void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
AnnaBridge	172:65be27845400	885	void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
AnnaBridge	172:65be27845400	886	void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
AnnaBridge	172:65be27845400	887	void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
AnnaBridge	172:65be27845400	888	void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
AnnaBridge	172:65be27845400	889	void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
AnnaBridge	172:65be27845400	890	void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
AnnaBridge	172:65be27845400	891	/**
AnnaBridge	172:65be27845400	892	* @}
AnnaBridge	172:65be27845400	893	*/
AnnaBridge	172:65be27845400	894
AnnaBridge	172:65be27845400	895	/** @addtogroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
AnnaBridge	172:65be27845400	896	* @{
AnnaBridge	172:65be27845400	897	*/
AnnaBridge	172:65be27845400	898
AnnaBridge	172:65be27845400	899	/* Peripheral State and Error functions ***************************************/
AnnaBridge	172:65be27845400	900	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
AnnaBridge	172:65be27845400	901	uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
AnnaBridge	172:65be27845400	902	/**
AnnaBridge	172:65be27845400	903	* @}
AnnaBridge	172:65be27845400	904	*/
AnnaBridge	172:65be27845400	905
AnnaBridge	172:65be27845400	906	/**
AnnaBridge	172:65be27845400	907	* @}
AnnaBridge	172:65be27845400	908	*/
AnnaBridge	172:65be27845400	909
AnnaBridge	172:65be27845400	910	/* Private macros ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	911	/** @defgroup SPI_Private_Macros SPI Private Macros
AnnaBridge	172:65be27845400	912	* @{
AnnaBridge	172:65be27845400	913	*/
AnnaBridge	172:65be27845400	914
AnnaBridge	172:65be27845400	915	/** @brief Set the SPI transmit-only mode.
AnnaBridge	172:65be27845400	916	* @param __HANDLE__: specifies the SPI Handle.
AnnaBridge	172:65be27845400	917	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
AnnaBridge	172:65be27845400	918	* @retval None
AnnaBridge	172:65be27845400	919	*/
AnnaBridge	172:65be27845400	920	#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_HDDIR)
AnnaBridge	172:65be27845400	921
AnnaBridge	172:65be27845400	922	/** @brief Set the SPI receive-only mode.
AnnaBridge	172:65be27845400	923	* @param __HANDLE__: specifies the SPI Handle.
AnnaBridge	172:65be27845400	924	* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
AnnaBridge	172:65be27845400	925	* @retval None
AnnaBridge	172:65be27845400	926	*/
AnnaBridge	172:65be27845400	927	#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 ,SPI_CR1_HDDIR)
AnnaBridge	172:65be27845400	928
AnnaBridge	172:65be27845400	929	#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) \|\| \
AnnaBridge	172:65be27845400	930	((MODE) == SPI_MODE_MASTER))
AnnaBridge	172:65be27845400	931
AnnaBridge	172:65be27845400	932	#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) \|\| \
AnnaBridge	172:65be27845400	933	((MODE) == SPI_DIRECTION_2LINES_RXONLY) \|\| \
AnnaBridge	172:65be27845400	934	((MODE) == SPI_DIRECTION_1LINE) \|\| \
AnnaBridge	172:65be27845400	935	((MODE) == SPI_DIRECTION_2LINES_TXONLY))
AnnaBridge	172:65be27845400	936
AnnaBridge	172:65be27845400	937	#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
AnnaBridge	172:65be27845400	938
AnnaBridge	172:65be27845400	939	#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(MODE) ( \
AnnaBridge	172:65be27845400	940	((MODE) == SPI_DIRECTION_2LINES)\|\| \
AnnaBridge	172:65be27845400	941	((MODE) == SPI_DIRECTION_1LINE) \|\| \
AnnaBridge	172:65be27845400	942	((MODE) == SPI_DIRECTION_2LINES_TXONLY))
AnnaBridge	172:65be27845400	943
AnnaBridge	172:65be27845400	944	#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(MODE) ( \
AnnaBridge	172:65be27845400	945	((MODE) == SPI_DIRECTION_2LINES)\|\| \
AnnaBridge	172:65be27845400	946	((MODE) == SPI_DIRECTION_1LINE) \|\| \
AnnaBridge	172:65be27845400	947	((MODE) == SPI_DIRECTION_2LINES_RXONLY))
AnnaBridge	172:65be27845400	948
AnnaBridge	172:65be27845400	949	#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_32BIT) \|\| \
AnnaBridge	172:65be27845400	950	((DATASIZE) == SPI_DATASIZE_31BIT) \|\| \
AnnaBridge	172:65be27845400	951	((DATASIZE) == SPI_DATASIZE_30BIT) \|\| \
AnnaBridge	172:65be27845400	952	((DATASIZE) == SPI_DATASIZE_29BIT) \|\| \
AnnaBridge	172:65be27845400	953	((DATASIZE) == SPI_DATASIZE_28BIT) \|\| \
AnnaBridge	172:65be27845400	954	((DATASIZE) == SPI_DATASIZE_27BIT) \|\| \
AnnaBridge	172:65be27845400	955	((DATASIZE) == SPI_DATASIZE_26BIT) \|\| \
AnnaBridge	172:65be27845400	956	((DATASIZE) == SPI_DATASIZE_25BIT) \|\| \
AnnaBridge	172:65be27845400	957	((DATASIZE) == SPI_DATASIZE_24BIT) \|\| \
AnnaBridge	172:65be27845400	958	((DATASIZE) == SPI_DATASIZE_23BIT) \|\| \
AnnaBridge	172:65be27845400	959	((DATASIZE) == SPI_DATASIZE_22BIT) \|\| \
AnnaBridge	172:65be27845400	960	((DATASIZE) == SPI_DATASIZE_21BIT) \|\| \
AnnaBridge	172:65be27845400	961	((DATASIZE) == SPI_DATASIZE_20BIT) \|\| \
AnnaBridge	172:65be27845400	962	((DATASIZE) == SPI_DATASIZE_22BIT) \|\| \
AnnaBridge	172:65be27845400	963	((DATASIZE) == SPI_DATASIZE_19BIT) \|\| \
AnnaBridge	172:65be27845400	964	((DATASIZE) == SPI_DATASIZE_18BIT) \|\| \
AnnaBridge	172:65be27845400	965	((DATASIZE) == SPI_DATASIZE_17BIT) \|\| \
AnnaBridge	172:65be27845400	966	((DATASIZE) == SPI_DATASIZE_16BIT) \|\| \
AnnaBridge	172:65be27845400	967	((DATASIZE) == SPI_DATASIZE_15BIT) \|\| \
AnnaBridge	172:65be27845400	968	((DATASIZE) == SPI_DATASIZE_14BIT) \|\| \
AnnaBridge	172:65be27845400	969	((DATASIZE) == SPI_DATASIZE_13BIT) \|\| \
AnnaBridge	172:65be27845400	970	((DATASIZE) == SPI_DATASIZE_12BIT) \|\| \
AnnaBridge	172:65be27845400	971	((DATASIZE) == SPI_DATASIZE_11BIT) \|\| \
AnnaBridge	172:65be27845400	972	((DATASIZE) == SPI_DATASIZE_10BIT) \|\| \
AnnaBridge	172:65be27845400	973	((DATASIZE) == SPI_DATASIZE_9BIT) \|\| \
AnnaBridge	172:65be27845400	974	((DATASIZE) == SPI_DATASIZE_8BIT) \|\| \
AnnaBridge	172:65be27845400	975	((DATASIZE) == SPI_DATASIZE_7BIT) \|\| \
AnnaBridge	172:65be27845400	976	((DATASIZE) == SPI_DATASIZE_6BIT) \|\| \
AnnaBridge	172:65be27845400	977	((DATASIZE) == SPI_DATASIZE_5BIT) \|\| \
AnnaBridge	172:65be27845400	978	((DATASIZE) == SPI_DATASIZE_4BIT))
AnnaBridge	172:65be27845400	979
AnnaBridge	172:65be27845400	980	#define IS_SPI_FIFOTHRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_FIFO_THRESHOLD_01DATA) \|\| \
AnnaBridge	172:65be27845400	981	((THRESHOLD) == SPI_FIFO_THRESHOLD_02DATA) \|\| \
AnnaBridge	172:65be27845400	982	((THRESHOLD) == SPI_FIFO_THRESHOLD_03DATA) \|\| \
AnnaBridge	172:65be27845400	983	((THRESHOLD) == SPI_FIFO_THRESHOLD_04DATA) \|\| \
AnnaBridge	172:65be27845400	984	((THRESHOLD) == SPI_FIFO_THRESHOLD_05DATA) \|\| \
AnnaBridge	172:65be27845400	985	((THRESHOLD) == SPI_FIFO_THRESHOLD_06DATA) \|\| \
AnnaBridge	172:65be27845400	986	((THRESHOLD) == SPI_FIFO_THRESHOLD_07DATA) \|\| \
AnnaBridge	172:65be27845400	987	((THRESHOLD) == SPI_FIFO_THRESHOLD_08DATA) \|\| \
AnnaBridge	172:65be27845400	988	((THRESHOLD) == SPI_FIFO_THRESHOLD_09DATA) \|\| \
AnnaBridge	172:65be27845400	989	((THRESHOLD) == SPI_FIFO_THRESHOLD_10DATA) \|\| \
AnnaBridge	172:65be27845400	990	((THRESHOLD) == SPI_FIFO_THRESHOLD_11DATA) \|\| \
AnnaBridge	172:65be27845400	991	((THRESHOLD) == SPI_FIFO_THRESHOLD_12DATA) \|\| \
AnnaBridge	172:65be27845400	992	((THRESHOLD) == SPI_FIFO_THRESHOLD_13DATA) \|\| \
AnnaBridge	172:65be27845400	993	((THRESHOLD) == SPI_FIFO_THRESHOLD_14DATA) \|\| \
AnnaBridge	172:65be27845400	994	((THRESHOLD) == SPI_FIFO_THRESHOLD_15DATA) \|\| \
AnnaBridge	172:65be27845400	995	((THRESHOLD) == SPI_FIFO_THRESHOLD_16DATA))
AnnaBridge	172:65be27845400	996
AnnaBridge	172:65be27845400	997	#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) \|\| \
AnnaBridge	172:65be27845400	998	((CPOL) == SPI_POLARITY_HIGH))
AnnaBridge	172:65be27845400	999
AnnaBridge	172:65be27845400	1000	#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) \|\| \
AnnaBridge	172:65be27845400	1001	((CPHA) == SPI_PHASE_2EDGE))
AnnaBridge	172:65be27845400	1002
AnnaBridge	172:65be27845400	1003	#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) \|\| \
AnnaBridge	172:65be27845400	1004	((NSS) == SPI_NSS_HARD_INPUT) \|\| \
AnnaBridge	172:65be27845400	1005	((NSS) == SPI_NSS_HARD_OUTPUT))
AnnaBridge	172:65be27845400	1006
AnnaBridge	172:65be27845400	1007	#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) \|\| \
AnnaBridge	172:65be27845400	1008	((NSSP) == SPI_NSS_PULSE_DISABLE))
AnnaBridge	172:65be27845400	1009
AnnaBridge	172:65be27845400	1010	#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) \|\| \
AnnaBridge	172:65be27845400	1011	((PRESCALER) == SPI_BAUDRATEPRESCALER_4) \|\| \
AnnaBridge	172:65be27845400	1012	((PRESCALER) == SPI_BAUDRATEPRESCALER_8) \|\| \
AnnaBridge	172:65be27845400	1013	((PRESCALER) == SPI_BAUDRATEPRESCALER_16) \|\| \
AnnaBridge	172:65be27845400	1014	((PRESCALER) == SPI_BAUDRATEPRESCALER_32) \|\| \
AnnaBridge	172:65be27845400	1015	((PRESCALER) == SPI_BAUDRATEPRESCALER_64) \|\| \
AnnaBridge	172:65be27845400	1016	((PRESCALER) == SPI_BAUDRATEPRESCALER_128) \|\| \
AnnaBridge	172:65be27845400	1017	((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
AnnaBridge	172:65be27845400	1018
AnnaBridge	172:65be27845400	1019	#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) \|\| \
AnnaBridge	172:65be27845400	1020	((BIT) == SPI_FIRSTBIT_LSB))
AnnaBridge	172:65be27845400	1021
AnnaBridge	172:65be27845400	1022	#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) \|\| \
AnnaBridge	172:65be27845400	1023	((MODE) == SPI_TIMODE_ENABLE))
AnnaBridge	172:65be27845400	1024
AnnaBridge	172:65be27845400	1025	#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) \|\| \
AnnaBridge	172:65be27845400	1026	((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
AnnaBridge	172:65be27845400	1027
AnnaBridge	172:65be27845400	1028	#define IS_SPI_CRC_INITIALIZATION_PATTERN(PATTERN) (((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN) \|\| \
AnnaBridge	172:65be27845400	1029	((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN))
AnnaBridge	172:65be27845400	1030
AnnaBridge	172:65be27845400	1031	#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) \|\| \
AnnaBridge	172:65be27845400	1032	((LENGTH) == SPI_CRC_LENGTH_32BIT) \|\| \
AnnaBridge	172:65be27845400	1033	((LENGTH) == SPI_CRC_LENGTH_31BIT) \|\| \
AnnaBridge	172:65be27845400	1034	((LENGTH) == SPI_CRC_LENGTH_30BIT) \|\| \
AnnaBridge	172:65be27845400	1035	((LENGTH) == SPI_CRC_LENGTH_29BIT) \|\| \
AnnaBridge	172:65be27845400	1036	((LENGTH) == SPI_CRC_LENGTH_28BIT) \|\| \
AnnaBridge	172:65be27845400	1037	((LENGTH) == SPI_CRC_LENGTH_27BIT) \|\| \
AnnaBridge	172:65be27845400	1038	((LENGTH) == SPI_CRC_LENGTH_26BIT) \|\| \
AnnaBridge	172:65be27845400	1039	((LENGTH) == SPI_CRC_LENGTH_25BIT) \|\| \
AnnaBridge	172:65be27845400	1040	((LENGTH) == SPI_CRC_LENGTH_24BIT) \|\| \
AnnaBridge	172:65be27845400	1041	((LENGTH) == SPI_CRC_LENGTH_23BIT) \|\| \
AnnaBridge	172:65be27845400	1042	((LENGTH) == SPI_CRC_LENGTH_22BIT) \|\| \
AnnaBridge	172:65be27845400	1043	((LENGTH) == SPI_CRC_LENGTH_21BIT) \|\| \
AnnaBridge	172:65be27845400	1044	((LENGTH) == SPI_CRC_LENGTH_20BIT) \|\| \
AnnaBridge	172:65be27845400	1045	((LENGTH) == SPI_CRC_LENGTH_19BIT) \|\| \
AnnaBridge	172:65be27845400	1046	((LENGTH) == SPI_CRC_LENGTH_18BIT) \|\| \
AnnaBridge	172:65be27845400	1047	((LENGTH) == SPI_CRC_LENGTH_17BIT) \|\| \
AnnaBridge	172:65be27845400	1048	((LENGTH) == SPI_CRC_LENGTH_16BIT) \|\| \
AnnaBridge	172:65be27845400	1049	((LENGTH) == SPI_CRC_LENGTH_15BIT) \|\| \
AnnaBridge	172:65be27845400	1050	((LENGTH) == SPI_CRC_LENGTH_14BIT) \|\| \
AnnaBridge	172:65be27845400	1051	((LENGTH) == SPI_CRC_LENGTH_13BIT) \|\| \
AnnaBridge	172:65be27845400	1052	((LENGTH) == SPI_CRC_LENGTH_12BIT) \|\| \
AnnaBridge	172:65be27845400	1053	((LENGTH) == SPI_CRC_LENGTH_11BIT) \|\| \
AnnaBridge	172:65be27845400	1054	((LENGTH) == SPI_CRC_LENGTH_10BIT) \|\| \
AnnaBridge	172:65be27845400	1055	((LENGTH) == SPI_CRC_LENGTH_9BIT) \|\| \
AnnaBridge	172:65be27845400	1056	((LENGTH) == SPI_CRC_LENGTH_8BIT) \|\| \
AnnaBridge	172:65be27845400	1057	((LENGTH) == SPI_CRC_LENGTH_7BIT) \|\| \
AnnaBridge	172:65be27845400	1058	((LENGTH) == SPI_CRC_LENGTH_6BIT) \|\| \
AnnaBridge	172:65be27845400	1059	((LENGTH) == SPI_CRC_LENGTH_5BIT) \|\| \
AnnaBridge	172:65be27845400	1060	((LENGTH) == SPI_CRC_LENGTH_4BIT))
AnnaBridge	172:65be27845400	1061
AnnaBridge	172:65be27845400	1062	#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFFFFFF))
AnnaBridge	172:65be27845400	1063
AnnaBridge	172:65be27845400	1064	#define IS_SPI_UNDERRUN_DETECTION(MODE) (((MODE) == SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME) \|\| \
AnnaBridge	172:65be27845400	1065	((MODE) == SPI_UNDERRUN_DETECT_END_DATA_FRAME) \|\| \
AnnaBridge	172:65be27845400	1066	((MODE) == SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS))
AnnaBridge	172:65be27845400	1067
AnnaBridge	172:65be27845400	1068	#define IS_SPI_UNDERRUN_BEHAVIOUR(MODE) (((MODE) == SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) \|\| \
AnnaBridge	172:65be27845400	1069	((MODE) == SPI_UNDERRUN_BEHAV_LAST_RECEIVED) \|\| \
AnnaBridge	172:65be27845400	1070	((MODE) == SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED))
AnnaBridge	172:65be27845400	1071	/**
AnnaBridge	172:65be27845400	1072	* @}
AnnaBridge	172:65be27845400	1073	*/
AnnaBridge	172:65be27845400	1074
AnnaBridge	172:65be27845400	1075	/**
AnnaBridge	172:65be27845400	1076	* @}
AnnaBridge	172:65be27845400	1077	*/
AnnaBridge	172:65be27845400	1078
AnnaBridge	172:65be27845400	1079	/**
AnnaBridge	172:65be27845400	1080	* @}
AnnaBridge	172:65be27845400	1081	*/
AnnaBridge	172:65be27845400	1082
AnnaBridge	172:65be27845400	1083	#ifdef __cplusplus
AnnaBridge	172:65be27845400	1084	}
AnnaBridge	172:65be27845400	1085	#endif
AnnaBridge	172:65be27845400	1086
AnnaBridge	172:65be27845400	1087	#endif /* STM32H7xx_HAL_SPI_H */
AnnaBridge	172:65be27845400	1088
AnnaBridge	172:65be27845400	1089	/**
AnnaBridge	172:65be27845400	1090	* @}
AnnaBridge	172:65be27845400	1091	*/
AnnaBridge	172:65be27845400	1092	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/