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TARGET_NUCLEO_H743ZI/TOOLCHAIN_ARM_MICRO/stm32h7xx_hal_rcc_ex.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	172:65be27845400	1	/**
AnnaBridge	172:65be27845400	2	******************************************************************************
AnnaBridge	172:65be27845400	3	* @file stm32h7xx_hal_rcc_ex.h
AnnaBridge	172:65be27845400	4	* @author MCD Application Team
AnnaBridge	172:65be27845400	5	* @brief Header file of RCC HAL Extension module.
AnnaBridge	172:65be27845400	6	******************************************************************************
AnnaBridge	172:65be27845400	7	* @attention
AnnaBridge	172:65be27845400	8	*
AnnaBridge	172:65be27845400	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
AnnaBridge	172:65be27845400	10	* All rights reserved.</center></h2>
AnnaBridge	172:65be27845400	11	*
AnnaBridge	172:65be27845400	12	* This software component is licensed by ST under BSD 3-Clause license,
AnnaBridge	172:65be27845400	13	* the "License"; You may not use this file except in compliance with the
AnnaBridge	172:65be27845400	14	* License. You may obtain a copy of the License at:
AnnaBridge	172:65be27845400	15	* opensource.org/licenses/BSD-3-Clause
AnnaBridge	172:65be27845400	16	*
AnnaBridge	172:65be27845400	17	******************************************************************************
AnnaBridge	172:65be27845400	18	*/
AnnaBridge	172:65be27845400	19
AnnaBridge	172:65be27845400	20	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	172:65be27845400	21	#ifndef STM32H7xx_HAL_RCC_EX_H
AnnaBridge	172:65be27845400	22	#define STM32H7xx_HAL_RCC_EX_H
AnnaBridge	172:65be27845400	23
AnnaBridge	172:65be27845400	24	#ifdef __cplusplus
AnnaBridge	172:65be27845400	25	extern "C" {
AnnaBridge	172:65be27845400	26	#endif
AnnaBridge	172:65be27845400	27
AnnaBridge	172:65be27845400	28	/* Includes ------------------------------------------------------------------*/
AnnaBridge	172:65be27845400	29	#include "stm32h7xx_hal_def.h"
AnnaBridge	172:65be27845400	30
AnnaBridge	172:65be27845400	31	/** @addtogroup STM32H7xx_HAL_Driver
AnnaBridge	172:65be27845400	32	* @{
AnnaBridge	172:65be27845400	33	*/
AnnaBridge	172:65be27845400	34
AnnaBridge	172:65be27845400	35	/** @addtogroup RCCEx
AnnaBridge	172:65be27845400	36	* @{
AnnaBridge	172:65be27845400	37	*/
AnnaBridge	172:65be27845400	38
AnnaBridge	172:65be27845400	39	/* Exported types ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	40	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
AnnaBridge	172:65be27845400	41	* @{
AnnaBridge	172:65be27845400	42	*/
AnnaBridge	172:65be27845400	43
AnnaBridge	172:65be27845400	44	/**
AnnaBridge	172:65be27845400	45	* @brief PLL2 Clock structure definition
AnnaBridge	172:65be27845400	46	*/
AnnaBridge	172:65be27845400	47	typedef struct
AnnaBridge	172:65be27845400	48	{
AnnaBridge	172:65be27845400	49
AnnaBridge	172:65be27845400	50	uint32_t PLL2M; /*!< PLL2M: Division factor for PLL2 VCO input clock.
AnnaBridge	172:65be27845400	51	This parameter must be a number between Min_Data = 1 and Max_Data = 63 */
AnnaBridge	172:65be27845400	52
AnnaBridge	172:65be27845400	53	uint32_t PLL2N; /*!< PLL2N: Multiplication factor for PLL2 VCO output clock.
AnnaBridge	172:65be27845400	54	This parameter must be a number between Min_Data = 4 and Max_Data = 512 */
AnnaBridge	172:65be27845400	55
AnnaBridge	172:65be27845400	56	uint32_t PLL2P; /*!< PLL2P: Division factor for system clock.
AnnaBridge	172:65be27845400	57	This parameter must be a number between Min_Data = 2 and Max_Data = 128
AnnaBridge	172:65be27845400	58	odd division factors are not allowed */
AnnaBridge	172:65be27845400	59
AnnaBridge	172:65be27845400	60	uint32_t PLL2Q; /*!< PLL2Q: Division factor for peripheral clocks.
AnnaBridge	172:65be27845400	61	This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
AnnaBridge	172:65be27845400	62
AnnaBridge	172:65be27845400	63	uint32_t PLL2R; /*!< PLL2R: Division factor for peripheral clocks.
AnnaBridge	172:65be27845400	64	This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
AnnaBridge	172:65be27845400	65	uint32_t PLL2RGE; /*!<PLL2RGE: PLL2 clock Input range
AnnaBridge	172:65be27845400	66	This parameter must be a value of @ref RCC_PLL2_VCI_Range */
AnnaBridge	172:65be27845400	67	uint32_t PLL2VCOSEL; /*!<PLL2VCOSEL: PLL2 clock Output range
AnnaBridge	172:65be27845400	68	This parameter must be a value of @ref RCC_PLL2_VCO_Range */
AnnaBridge	172:65be27845400	69
AnnaBridge	172:65be27845400	70	uint32_t PLL2FRACN; /*!<PLL2FRACN: Specifies Fractional Part Of The Multiplication Factor for
AnnaBridge	172:65be27845400	71	PLL2 VCO It should be a value between 0 and 8191 */
AnnaBridge	172:65be27845400	72	}RCC_PLL2InitTypeDef;
AnnaBridge	172:65be27845400	73
AnnaBridge	172:65be27845400	74
AnnaBridge	172:65be27845400	75	/**
AnnaBridge	172:65be27845400	76	* @brief PLL3 Clock structure definition
AnnaBridge	172:65be27845400	77	*/
AnnaBridge	172:65be27845400	78	typedef struct
AnnaBridge	172:65be27845400	79	{
AnnaBridge	172:65be27845400	80
AnnaBridge	172:65be27845400	81	uint32_t PLL3M; /*!< PLL3M: Division factor for PLL3 VCO input clock.
AnnaBridge	172:65be27845400	82	This parameter must be a number between Min_Data = 1 and Max_Data = 63 */
AnnaBridge	172:65be27845400	83
AnnaBridge	172:65be27845400	84	uint32_t PLL3N; /*!< PLL3N: Multiplication factor for PLL3 VCO output clock.
AnnaBridge	172:65be27845400	85	This parameter must be a number between Min_Data = 4 and Max_Data = 512 */
AnnaBridge	172:65be27845400	86
AnnaBridge	172:65be27845400	87	uint32_t PLL3P; /*!< PLL3P: Division factor for system clock.
AnnaBridge	172:65be27845400	88	This parameter must be a number between Min_Data = 2 and Max_Data = 128
AnnaBridge	172:65be27845400	89	odd division factors are not allowed */
AnnaBridge	172:65be27845400	90
AnnaBridge	172:65be27845400	91	uint32_t PLL3Q; /*!< PLL3Q: Division factor for peripheral clocks.
AnnaBridge	172:65be27845400	92	This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
AnnaBridge	172:65be27845400	93
AnnaBridge	172:65be27845400	94	uint32_t PLL3R; /*!< PLL3R: Division factor for peripheral clocks.
AnnaBridge	172:65be27845400	95	This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
AnnaBridge	172:65be27845400	96	uint32_t PLL3RGE; /*!<PLL3RGE: PLL3 clock Input range
AnnaBridge	172:65be27845400	97	This parameter must be a value of @ref RCC_PLL3_VCI_Range */
AnnaBridge	172:65be27845400	98	uint32_t PLL3VCOSEL; /*!<PLL3VCOSEL: PLL3 clock Output range
AnnaBridge	172:65be27845400	99	This parameter must be a value of @ref RCC_PLL3_VCO_Range */
AnnaBridge	172:65be27845400	100
AnnaBridge	172:65be27845400	101	uint32_t PLL3FRACN; /*!<PLL3FRACN: Specifies Fractional Part Of The Multiplication Factor for
AnnaBridge	172:65be27845400	102	PLL3 VCO It should be a value between 0 and 8191 */
AnnaBridge	172:65be27845400	103	}RCC_PLL3InitTypeDef;
AnnaBridge	172:65be27845400	104
AnnaBridge	172:65be27845400	105	/**
AnnaBridge	172:65be27845400	106	* @brief RCC PLL1 Clocks structure definition
AnnaBridge	172:65be27845400	107	*/
AnnaBridge	172:65be27845400	108	typedef struct
AnnaBridge	172:65be27845400	109	{
AnnaBridge	172:65be27845400	110	uint32_t PLL1_P_Frequency;
AnnaBridge	172:65be27845400	111	uint32_t PLL1_Q_Frequency;
AnnaBridge	172:65be27845400	112	uint32_t PLL1_R_Frequency;
AnnaBridge	172:65be27845400	113	}PLL1_ClocksTypeDef;
AnnaBridge	172:65be27845400	114
AnnaBridge	172:65be27845400	115	/**
AnnaBridge	172:65be27845400	116	* @brief RCC PLL2 Clocks structure definition
AnnaBridge	172:65be27845400	117	*/
AnnaBridge	172:65be27845400	118	typedef struct
AnnaBridge	172:65be27845400	119	{
AnnaBridge	172:65be27845400	120	uint32_t PLL2_P_Frequency;
AnnaBridge	172:65be27845400	121	uint32_t PLL2_Q_Frequency;
AnnaBridge	172:65be27845400	122	uint32_t PLL2_R_Frequency;
AnnaBridge	172:65be27845400	123	}PLL2_ClocksTypeDef;
AnnaBridge	172:65be27845400	124
AnnaBridge	172:65be27845400	125	/**
AnnaBridge	172:65be27845400	126	* @brief RCC PLL3 Clocks structure definition
AnnaBridge	172:65be27845400	127	*/
AnnaBridge	172:65be27845400	128	typedef struct
AnnaBridge	172:65be27845400	129	{
AnnaBridge	172:65be27845400	130	uint32_t PLL3_P_Frequency;
AnnaBridge	172:65be27845400	131	uint32_t PLL3_Q_Frequency;
AnnaBridge	172:65be27845400	132	uint32_t PLL3_R_Frequency;
AnnaBridge	172:65be27845400	133	}PLL3_ClocksTypeDef;
AnnaBridge	172:65be27845400	134
AnnaBridge	172:65be27845400	135
AnnaBridge	172:65be27845400	136	/**
AnnaBridge	172:65be27845400	137	* @brief RCC extended clocks structure definition
AnnaBridge	172:65be27845400	138	*/
AnnaBridge	172:65be27845400	139	typedef struct
AnnaBridge	172:65be27845400	140	{
AnnaBridge	172:65be27845400	141	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	172:65be27845400	142	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	172:65be27845400	143
AnnaBridge	172:65be27845400	144	RCC_PLL2InitTypeDef PLL2; /*!< PLL2structure parameters.
AnnaBridge	172:65be27845400	145	This parameter will be used only when PLL2 is selected as kernel clock Source for some peripherals */
AnnaBridge	172:65be27845400	146
AnnaBridge	172:65be27845400	147	RCC_PLL3InitTypeDef PLL3; /*!< PLL3 structure parameters.
AnnaBridge	172:65be27845400	148	This parameter will be used only when PLL2 is selected as kernel clock Source for some peripherals */
AnnaBridge	172:65be27845400	149
AnnaBridge	172:65be27845400	150	uint32_t FmcClockSelection; /*!< Specifies FMC clock source
AnnaBridge	172:65be27845400	151	This parameter can be a value of @ref RCCEx_FMC_Clock_Source */
AnnaBridge	172:65be27845400	152
AnnaBridge	172:65be27845400	153	uint32_t QspiClockSelection; /*!< Specifies QSPI clock source
AnnaBridge	172:65be27845400	154	This parameter can be a value of @ref RCCEx_QSPI_Clock_Source */
AnnaBridge	172:65be27845400	155
AnnaBridge	172:65be27845400	156	uint32_t SdmmcClockSelection; /*!< Specifies SDMMC clock source
AnnaBridge	172:65be27845400	157	This parameter can be a value of @ref RCCEx_SDMMC_Clock_Source */
AnnaBridge	172:65be27845400	158
AnnaBridge	172:65be27845400	159	uint32_t CkperClockSelection; /*!< Specifies CKPER clock source
AnnaBridge	172:65be27845400	160	This parameter can be a value of @ref RCCEx_CLKP_Clock_Source */
AnnaBridge	172:65be27845400	161
AnnaBridge	172:65be27845400	162	uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source
AnnaBridge	172:65be27845400	163	This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
AnnaBridge	172:65be27845400	164
AnnaBridge	172:65be27845400	165	uint32_t Sai23ClockSelection; /*!< Specifies SAI2/3 clock source
AnnaBridge	172:65be27845400	166	This parameter can be a value of @ref RCCEx_SAI23_Clock_Source */
AnnaBridge	172:65be27845400	167
AnnaBridge	172:65be27845400	168	uint32_t Spi123ClockSelection; /*!< Specifies SPI1/2/3 clock source
AnnaBridge	172:65be27845400	169	This parameter can be a value of @ref RCCEx_SPI123_Clock_Source */
AnnaBridge	172:65be27845400	170
AnnaBridge	172:65be27845400	171	uint32_t Spi45ClockSelection; /*!< Specifies SPI4/5 clock source
AnnaBridge	172:65be27845400	172	This parameter can be a value of @ref RCCEx_SPI45_Clock_Source */
AnnaBridge	172:65be27845400	173
AnnaBridge	172:65be27845400	174	uint32_t SpdifrxClockSelection; /*!< Specifies SPDIFRX Clock clock source
AnnaBridge	172:65be27845400	175	This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */
AnnaBridge	172:65be27845400	176
AnnaBridge	172:65be27845400	177	uint32_t Dfsdm1ClockSelection; /*!< Specifies DFSDM1 Clock clock source
AnnaBridge	172:65be27845400	178	This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source */
AnnaBridge	172:65be27845400	179	#if defined(FDCAN1) \|\| defined(FDCAN2)
AnnaBridge	172:65be27845400	180	uint32_t FdcanClockSelection; /*!< Specifies FDCAN Clock clock source
AnnaBridge	172:65be27845400	181	This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source */
AnnaBridge	172:65be27845400	182	#endif /FDCAN1 \|\| FDCAN2/
AnnaBridge	172:65be27845400	183
AnnaBridge	172:65be27845400	184	uint32_t Swpmi1ClockSelection; /*!< Specifies SWPMI1 Clock clock source
AnnaBridge	172:65be27845400	185	This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source */
AnnaBridge	172:65be27845400	186
AnnaBridge	172:65be27845400	187	uint32_t Usart234578ClockSelection; /*!< Specifies USART2/3/4/5/7/8 clock source
AnnaBridge	172:65be27845400	188	This parameter can be a value of @ref RCCEx_USART234578_Clock_Source */
AnnaBridge	172:65be27845400	189
AnnaBridge	172:65be27845400	190	uint32_t Usart16ClockSelection; /*!< Specifies USART1/6 clock source
AnnaBridge	172:65be27845400	191	This parameter can be a value of @ref RCCEx_USART16_Clock_Source */
AnnaBridge	172:65be27845400	192
AnnaBridge	172:65be27845400	193	uint32_t RngClockSelection; /*!< Specifies RNG clock source
AnnaBridge	172:65be27845400	194	This parameter can be a value of @ref RCCEx_RNG_Clock_Source */
AnnaBridge	172:65be27845400	195
AnnaBridge	172:65be27845400	196	uint32_t I2c123ClockSelection; /*!< Specifies I2C1/2/3 clock source
AnnaBridge	172:65be27845400	197	This parameter can be a value of @ref RCCEx_I2C123_Clock_Source */
AnnaBridge	172:65be27845400	198
AnnaBridge	172:65be27845400	199	uint32_t UsbClockSelection; /*!< Specifies USB clock source
AnnaBridge	172:65be27845400	200	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
AnnaBridge	172:65be27845400	201
AnnaBridge	172:65be27845400	202	uint32_t CecClockSelection; /*!< Specifies CEC clock source
AnnaBridge	172:65be27845400	203	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
AnnaBridge	172:65be27845400	204
AnnaBridge	172:65be27845400	205	uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source
AnnaBridge	172:65be27845400	206	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
AnnaBridge	172:65be27845400	207
AnnaBridge	172:65be27845400	208	uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source
AnnaBridge	172:65be27845400	209	This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
AnnaBridge	172:65be27845400	210
AnnaBridge	172:65be27845400	211	uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source
AnnaBridge	172:65be27845400	212	This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */
AnnaBridge	172:65be27845400	213
AnnaBridge	172:65be27845400	214	uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source
AnnaBridge	172:65be27845400	215	This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */
AnnaBridge	172:65be27845400	216
AnnaBridge	172:65be27845400	217	uint32_t Lptim345ClockSelection; /*!< Specifies LPTIM3/4/5 clock source
AnnaBridge	172:65be27845400	218	This parameter can be a value of @ref RCCEx_LPTIM345_Clock_Source */
AnnaBridge	172:65be27845400	219
AnnaBridge	172:65be27845400	220	uint32_t AdcClockSelection; /*!< Specifies ADC interface clock source
AnnaBridge	172:65be27845400	221	This parameter can be a value of @ref RCCEx_ADC_Clock_Source */
AnnaBridge	172:65be27845400	222
AnnaBridge	172:65be27845400	223	uint32_t Sai4AClockSelection; /*!< Specifies SAI4A clock source
AnnaBridge	172:65be27845400	224	This parameter can be a value of @ref RCCEx_SAI4A_Clock_Source */
AnnaBridge	172:65be27845400	225
AnnaBridge	172:65be27845400	226	uint32_t Sai4BClockSelection; /*!< Specifies SAI4B clock source
AnnaBridge	172:65be27845400	227	This parameter can be a value of @ref RCCEx_SAI4B_Clock_Source */
AnnaBridge	172:65be27845400	228
AnnaBridge	172:65be27845400	229	uint32_t Spi6ClockSelection; /*!< Specifies SPI6 clock source
AnnaBridge	172:65be27845400	230	This parameter can be a value of @ref RCCEx_SPI6_Clock_Source */
AnnaBridge	172:65be27845400	231
AnnaBridge	172:65be27845400	232	uint32_t RTCClockSelection; /*!< Specifies RTC Clock clock source
AnnaBridge	172:65be27845400	233	This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge	172:65be27845400	234
AnnaBridge	172:65be27845400	235	uint32_t Hrtim1ClockSelection; /*!< Specifies HRTIM1 Clock clock source
AnnaBridge	172:65be27845400	236	This parameter can be a value of @ref RCCEx_HRTIM1_Clock_Source */
AnnaBridge	172:65be27845400	237	uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
AnnaBridge	172:65be27845400	238	This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */
AnnaBridge	172:65be27845400	239	}RCC_PeriphCLKInitTypeDef;
AnnaBridge	172:65be27845400	240
AnnaBridge	172:65be27845400	241
AnnaBridge	172:65be27845400	242	/**
AnnaBridge	172:65be27845400	243	* @brief RCC_CRS Init structure definition
AnnaBridge	172:65be27845400	244	*/
AnnaBridge	172:65be27845400	245	typedef struct
AnnaBridge	172:65be27845400	246	{
AnnaBridge	172:65be27845400	247	uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
AnnaBridge	172:65be27845400	248	This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
AnnaBridge	172:65be27845400	249
AnnaBridge	172:65be27845400	250	uint32_t Source; /*!< Specifies the SYNC signal source.
AnnaBridge	172:65be27845400	251	This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
AnnaBridge	172:65be27845400	252
AnnaBridge	172:65be27845400	253	uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
AnnaBridge	172:65be27845400	254	This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
AnnaBridge	172:65be27845400	255
AnnaBridge	172:65be27845400	256	uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
AnnaBridge	172:65be27845400	257	It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)
AnnaBridge	172:65be27845400	258	This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
AnnaBridge	172:65be27845400	259
AnnaBridge	172:65be27845400	260	uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
AnnaBridge	172:65be27845400	261	This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
AnnaBridge	172:65be27845400	262
AnnaBridge	172:65be27845400	263	uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
AnnaBridge	172:65be27845400	264	This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
AnnaBridge	172:65be27845400	265
AnnaBridge	172:65be27845400	266	}RCC_CRSInitTypeDef;
AnnaBridge	172:65be27845400	267
AnnaBridge	172:65be27845400	268	/**
AnnaBridge	172:65be27845400	269	* @brief RCC_CRS Synchronization structure definition
AnnaBridge	172:65be27845400	270	*/
AnnaBridge	172:65be27845400	271	typedef struct
AnnaBridge	172:65be27845400	272	{
AnnaBridge	172:65be27845400	273	uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
AnnaBridge	172:65be27845400	274	This parameter must be a number between 0 and 0xFFFF */
AnnaBridge	172:65be27845400	275
AnnaBridge	172:65be27845400	276	uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
AnnaBridge	172:65be27845400	277	This parameter must be a number between 0 and 0x3F */
AnnaBridge	172:65be27845400	278
AnnaBridge	172:65be27845400	279	uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
AnnaBridge	172:65be27845400	280	value latched in the time of the last SYNC event.
AnnaBridge	172:65be27845400	281	This parameter must be a number between 0 and 0xFFFF */
AnnaBridge	172:65be27845400	282
AnnaBridge	172:65be27845400	283	uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
AnnaBridge	172:65be27845400	284	frequency error counter latched in the time of the last SYNC event.
AnnaBridge	172:65be27845400	285	It shows whether the actual frequency is below or above the target.
AnnaBridge	172:65be27845400	286	This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
AnnaBridge	172:65be27845400	287
AnnaBridge	172:65be27845400	288	}RCC_CRSSynchroInfoTypeDef;
AnnaBridge	172:65be27845400	289
AnnaBridge	172:65be27845400	290	/**
AnnaBridge	172:65be27845400	291	* @}
AnnaBridge	172:65be27845400	292	*/
AnnaBridge	172:65be27845400	293
AnnaBridge	172:65be27845400	294
AnnaBridge	172:65be27845400	295	/* Exported constants --------------------------------------------------------*/
AnnaBridge	172:65be27845400	296	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
AnnaBridge	172:65be27845400	297	* @{
AnnaBridge	172:65be27845400	298	*/
AnnaBridge	172:65be27845400	299
AnnaBridge	172:65be27845400	300	/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
AnnaBridge	172:65be27845400	301	* @{
AnnaBridge	172:65be27845400	302	*/
AnnaBridge	172:65be27845400	303
AnnaBridge	172:65be27845400	304	#define RCC_PERIPHCLK_USART16 (0x00000001U)
AnnaBridge	172:65be27845400	305	#define RCC_PERIPHCLK_USART1 RCC_PERIPHCLK_USART16
AnnaBridge	172:65be27845400	306	#define RCC_PERIPHCLK_USART6 RCC_PERIPHCLK_USART16
AnnaBridge	172:65be27845400	307	#define RCC_PERIPHCLK_USART234578 (0x00000002U)
AnnaBridge	172:65be27845400	308	#define RCC_PERIPHCLK_USART2 RCC_PERIPHCLK_USART234578
AnnaBridge	172:65be27845400	309	#define RCC_PERIPHCLK_USART3 RCC_PERIPHCLK_USART234578
AnnaBridge	172:65be27845400	310	#define RCC_PERIPHCLK_UART4 RCC_PERIPHCLK_USART234578
AnnaBridge	172:65be27845400	311	#define RCC_PERIPHCLK_UART5 RCC_PERIPHCLK_USART234578
AnnaBridge	172:65be27845400	312	#define RCC_PERIPHCLK_UART7 RCC_PERIPHCLK_USART234578
AnnaBridge	172:65be27845400	313	#define RCC_PERIPHCLK_UART8 RCC_PERIPHCLK_USART234578
AnnaBridge	172:65be27845400	314	#define RCC_PERIPHCLK_LPUART1 (0x00000004U)
AnnaBridge	172:65be27845400	315	#define RCC_PERIPHCLK_I2C123 (0x00000008U)
AnnaBridge	172:65be27845400	316	#define RCC_PERIPHCLK_I2C1 RCC_PERIPHCLK_I2C123
AnnaBridge	172:65be27845400	317	#define RCC_PERIPHCLK_I2C2 RCC_PERIPHCLK_I2C123
AnnaBridge	172:65be27845400	318	#define RCC_PERIPHCLK_I2C3 RCC_PERIPHCLK_I2C123
AnnaBridge	172:65be27845400	319	#define RCC_PERIPHCLK_I2C4 (0x00000010U)
AnnaBridge	172:65be27845400	320	#define RCC_PERIPHCLK_LPTIM1 (0x00000020U)
AnnaBridge	172:65be27845400	321	#define RCC_PERIPHCLK_LPTIM2 (0x00000040U)
AnnaBridge	172:65be27845400	322	#define RCC_PERIPHCLK_LPTIM345 (0x00000080U)
AnnaBridge	172:65be27845400	323	#define RCC_PERIPHCLK_LPTIM3 RCC_PERIPHCLK_LPTIM345
AnnaBridge	172:65be27845400	324	#define RCC_PERIPHCLK_LPTIM4 RCC_PERIPHCLK_LPTIM345
AnnaBridge	172:65be27845400	325	#define RCC_PERIPHCLK_LPTIM5 RCC_PERIPHCLK_LPTIM345
AnnaBridge	172:65be27845400	326	#define RCC_PERIPHCLK_SAI1 (0x00000100U)
AnnaBridge	172:65be27845400	327	#define RCC_PERIPHCLK_SAI23 (0x00000200U)
AnnaBridge	172:65be27845400	328	#define RCC_PERIPHCLK_SAI2 RCC_PERIPHCLK_SAI23
AnnaBridge	172:65be27845400	329	#define RCC_PERIPHCLK_SAI3 RCC_PERIPHCLK_SAI23
AnnaBridge	172:65be27845400	330	#define RCC_PERIPHCLK_SAI4A (0x00000400U)
AnnaBridge	172:65be27845400	331	#define RCC_PERIPHCLK_SAI4B (0x00000800U)
AnnaBridge	172:65be27845400	332	#define RCC_PERIPHCLK_SPI123 (0x00001000U)
AnnaBridge	172:65be27845400	333	#define RCC_PERIPHCLK_SPI1 RCC_PERIPHCLK_SPI123
AnnaBridge	172:65be27845400	334	#define RCC_PERIPHCLK_SPI2 RCC_PERIPHCLK_SPI123
AnnaBridge	172:65be27845400	335	#define RCC_PERIPHCLK_SPI3 RCC_PERIPHCLK_SPI123
AnnaBridge	172:65be27845400	336	#define RCC_PERIPHCLK_SPI45 (0x00002000U)
AnnaBridge	172:65be27845400	337	#define RCC_PERIPHCLK_SPI4 RCC_PERIPHCLK_SPI45
AnnaBridge	172:65be27845400	338	#define RCC_PERIPHCLK_SPI5 RCC_PERIPHCLK_SPI45
AnnaBridge	172:65be27845400	339	#define RCC_PERIPHCLK_SPI6 (0x00004000U)
AnnaBridge	172:65be27845400	340	#define RCC_PERIPHCLK_FDCAN (0x00008000U)
AnnaBridge	172:65be27845400	341	#define RCC_PERIPHCLK_SDMMC (0x00010000U)
AnnaBridge	172:65be27845400	342	#define RCC_PERIPHCLK_RNG (0x00020000U)
AnnaBridge	172:65be27845400	343	#define RCC_PERIPHCLK_USB (0x00040000U)
AnnaBridge	172:65be27845400	344	#define RCC_PERIPHCLK_ADC (0x00080000U)
AnnaBridge	172:65be27845400	345	#define RCC_PERIPHCLK_SWPMI1 (0x00100000U)
AnnaBridge	172:65be27845400	346	#define RCC_PERIPHCLK_DFSDM1 (0x00200000U)
AnnaBridge	172:65be27845400	347	#define RCC_PERIPHCLK_RTC (0x00400000U)
AnnaBridge	172:65be27845400	348	#define RCC_PERIPHCLK_CEC (0x00800000U)
AnnaBridge	172:65be27845400	349	#define RCC_PERIPHCLK_FMC (0x01000000U)
AnnaBridge	172:65be27845400	350	#define RCC_PERIPHCLK_QSPI (0x02000000U)
AnnaBridge	172:65be27845400	351	#define RCC_PERIPHCLK_SPDIFRX (0x08000000U)
AnnaBridge	172:65be27845400	352	#define RCC_PERIPHCLK_HRTIM1 (0x10000000U)
AnnaBridge	172:65be27845400	353	#define RCC_PERIPHCLK_LTDC (0x20000000U)
AnnaBridge	172:65be27845400	354	#define RCC_PERIPHCLK_TIM (0x40000000U)
AnnaBridge	172:65be27845400	355	#define RCC_PERIPHCLK_CKPER (0x80000000U)
AnnaBridge	172:65be27845400	356
AnnaBridge	172:65be27845400	357	/**
AnnaBridge	172:65be27845400	358	* @}
AnnaBridge	172:65be27845400	359	*/
AnnaBridge	172:65be27845400	360
AnnaBridge	172:65be27845400	361
AnnaBridge	172:65be27845400	362	/** @defgroup RCC_PLL2_Clock_Output RCC PLL2 Clock Output
AnnaBridge	172:65be27845400	363	* @{
AnnaBridge	172:65be27845400	364	*/
AnnaBridge	172:65be27845400	365	#define RCC_PLL2_DIVP RCC_PLLCFGR_DIVP2EN
AnnaBridge	172:65be27845400	366	#define RCC_PLL2_DIVQ RCC_PLLCFGR_DIVQ2EN
AnnaBridge	172:65be27845400	367	#define RCC_PLL2_DIVR RCC_PLLCFGR_DIVR2EN
AnnaBridge	172:65be27845400	368
AnnaBridge	172:65be27845400	369	/**
AnnaBridge	172:65be27845400	370	* @}
AnnaBridge	172:65be27845400	371	*/
AnnaBridge	172:65be27845400	372
AnnaBridge	172:65be27845400	373	/** @defgroup RCC_PLL3_Clock_Output RCC PLL3 Clock Output
AnnaBridge	172:65be27845400	374	* @{
AnnaBridge	172:65be27845400	375	*/
AnnaBridge	172:65be27845400	376	#define RCC_PLL3_DIVP RCC_PLLCFGR_DIVP3EN
AnnaBridge	172:65be27845400	377	#define RCC_PLL3_DIVQ RCC_PLLCFGR_DIVQ3EN
AnnaBridge	172:65be27845400	378	#define RCC_PLL3_DIVR RCC_PLLCFGR_DIVR3EN
AnnaBridge	172:65be27845400	379
AnnaBridge	172:65be27845400	380	/**
AnnaBridge	172:65be27845400	381	* @}
AnnaBridge	172:65be27845400	382	*/
AnnaBridge	172:65be27845400	383
AnnaBridge	172:65be27845400	384	/** @defgroup RCC_PLL2_VCI_Range RCC PLL2 VCI Range
AnnaBridge	172:65be27845400	385	* @{
AnnaBridge	172:65be27845400	386	*/
AnnaBridge	172:65be27845400	387	#define RCC_PLL2VCIRANGE_0 RCC_PLLCFGR_PLL2RGE_0
AnnaBridge	172:65be27845400	388	#define RCC_PLL2VCIRANGE_1 RCC_PLLCFGR_PLL2RGE_1
AnnaBridge	172:65be27845400	389	#define RCC_PLL2VCIRANGE_2 RCC_PLLCFGR_PLL2RGE_2
AnnaBridge	172:65be27845400	390	#define RCC_PLL2VCIRANGE_3 RCC_PLLCFGR_PLL2RGE_3
AnnaBridge	172:65be27845400	391
AnnaBridge	172:65be27845400	392	/**
AnnaBridge	172:65be27845400	393	* @}
AnnaBridge	172:65be27845400	394	*/
AnnaBridge	172:65be27845400	395
AnnaBridge	172:65be27845400	396
AnnaBridge	172:65be27845400	397	/** @defgroup RCC_PLL2_VCO_Range RCC PLL2 VCO Range
AnnaBridge	172:65be27845400	398	* @{
AnnaBridge	172:65be27845400	399	*/
AnnaBridge	172:65be27845400	400	#define RCC_PLL2VCOWIDE (0x00000000U)
AnnaBridge	172:65be27845400	401	#define RCC_PLL2VCOMEDIUM RCC_PLLCFGR_PLL2VCOSEL
AnnaBridge	172:65be27845400	402
AnnaBridge	172:65be27845400	403	/**
AnnaBridge	172:65be27845400	404	* @}
AnnaBridge	172:65be27845400	405	*/
AnnaBridge	172:65be27845400	406
AnnaBridge	172:65be27845400	407	/** @defgroup RCC_PLL3_VCI_Range RCC PLL3 VCI Range
AnnaBridge	172:65be27845400	408	* @{
AnnaBridge	172:65be27845400	409	*/
AnnaBridge	172:65be27845400	410	#define RCC_PLL3VCIRANGE_0 RCC_PLLCFGR_PLL3RGE_0
AnnaBridge	172:65be27845400	411	#define RCC_PLL3VCIRANGE_1 RCC_PLLCFGR_PLL3RGE_1
AnnaBridge	172:65be27845400	412	#define RCC_PLL3VCIRANGE_2 RCC_PLLCFGR_PLL3RGE_2
AnnaBridge	172:65be27845400	413	#define RCC_PLL3VCIRANGE_3 RCC_PLLCFGR_PLL3RGE_3
AnnaBridge	172:65be27845400	414
AnnaBridge	172:65be27845400	415	/**
AnnaBridge	172:65be27845400	416	* @}
AnnaBridge	172:65be27845400	417	*/
AnnaBridge	172:65be27845400	418
AnnaBridge	172:65be27845400	419
AnnaBridge	172:65be27845400	420	/** @defgroup RCC_PLL3_VCO_Range RCC PLL3 VCO Range
AnnaBridge	172:65be27845400	421	* @{
AnnaBridge	172:65be27845400	422	*/
AnnaBridge	172:65be27845400	423	#define RCC_PLL3VCOWIDE (0x00000000U)
AnnaBridge	172:65be27845400	424	#define RCC_PLL3VCOMEDIUM RCC_PLLCFGR_PLL3VCOSEL
AnnaBridge	172:65be27845400	425
AnnaBridge	172:65be27845400	426	/**
AnnaBridge	172:65be27845400	427	* @}
AnnaBridge	172:65be27845400	428	*/
AnnaBridge	172:65be27845400	429
AnnaBridge	172:65be27845400	430	/** @defgroup RCCEx_USART16_Clock_Source RCCEx USART1/6 Clock Source
AnnaBridge	172:65be27845400	431	* @{
AnnaBridge	172:65be27845400	432	*/
AnnaBridge	172:65be27845400	433	#define RCC_USART16CLKSOURCE_D2PCLK2 (0x00000000U)
AnnaBridge	172:65be27845400	434	#define RCC_USART16CLKSOURCE_PLL2 RCC_D2CCIP2R_USART16SEL_0
AnnaBridge	172:65be27845400	435	#define RCC_USART16CLKSOURCE_PLL3 RCC_D2CCIP2R_USART16SEL_1
AnnaBridge	172:65be27845400	436	#define RCC_USART16CLKSOURCE_HSI (RCC_D2CCIP2R_USART16SEL_0 \| RCC_D2CCIP2R_USART16SEL_1)
AnnaBridge	172:65be27845400	437	#define RCC_USART16CLKSOURCE_CSI RCC_D2CCIP2R_USART16SEL_2
AnnaBridge	172:65be27845400	438	#define RCC_USART16CLKSOURCE_LSE (RCC_D2CCIP2R_USART16SEL_0 \| RCC_D2CCIP2R_USART16SEL_2)
AnnaBridge	172:65be27845400	439	/**
AnnaBridge	172:65be27845400	440	* @}
AnnaBridge	172:65be27845400	441	*/
AnnaBridge	172:65be27845400	442
AnnaBridge	172:65be27845400	443	/** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source
AnnaBridge	172:65be27845400	444	* @{
AnnaBridge	172:65be27845400	445	*/
AnnaBridge	172:65be27845400	446	#define RCC_USART1CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2
AnnaBridge	172:65be27845400	447	#define RCC_USART1CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2
AnnaBridge	172:65be27845400	448	#define RCC_USART1CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3
AnnaBridge	172:65be27845400	449	#define RCC_USART1CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI
AnnaBridge	172:65be27845400	450	#define RCC_USART1CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI
AnnaBridge	172:65be27845400	451	#define RCC_USART1CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE
AnnaBridge	172:65be27845400	452	/**
AnnaBridge	172:65be27845400	453	* @}
AnnaBridge	172:65be27845400	454	*/
AnnaBridge	172:65be27845400	455
AnnaBridge	172:65be27845400	456	/** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source
AnnaBridge	172:65be27845400	457	* @{
AnnaBridge	172:65be27845400	458	*/
AnnaBridge	172:65be27845400	459	#define RCC_USART6CLKSOURCE_D2PCLK2 RCC_USART16CLKSOURCE_D2PCLK2
AnnaBridge	172:65be27845400	460	#define RCC_USART6CLKSOURCE_PLL2 RCC_USART16CLKSOURCE_PLL2
AnnaBridge	172:65be27845400	461	#define RCC_USART6CLKSOURCE_PLL3 RCC_USART16CLKSOURCE_PLL3
AnnaBridge	172:65be27845400	462	#define RCC_USART6CLKSOURCE_HSI RCC_USART16CLKSOURCE_HSI
AnnaBridge	172:65be27845400	463	#define RCC_USART6CLKSOURCE_CSI RCC_USART16CLKSOURCE_CSI
AnnaBridge	172:65be27845400	464	#define RCC_USART6CLKSOURCE_LSE RCC_USART16CLKSOURCE_LSE
AnnaBridge	172:65be27845400	465
AnnaBridge	172:65be27845400	466	/**
AnnaBridge	172:65be27845400	467	* @}
AnnaBridge	172:65be27845400	468	*/
AnnaBridge	172:65be27845400	469
AnnaBridge	172:65be27845400	470	/** @defgroup RCCEx_USART234578_Clock_Source RCCEx USART2/3/4/5/7/8 Clock Source
AnnaBridge	172:65be27845400	471	* @{
AnnaBridge	172:65be27845400	472	*/
AnnaBridge	172:65be27845400	473	#define RCC_USART234578CLKSOURCE_D2PCLK1 (0x00000000U)
AnnaBridge	172:65be27845400	474	#define RCC_USART234578CLKSOURCE_PLL2 RCC_D2CCIP2R_USART28SEL_0
AnnaBridge	172:65be27845400	475	#define RCC_USART234578CLKSOURCE_PLL3 RCC_D2CCIP2R_USART28SEL_1
AnnaBridge	172:65be27845400	476	#define RCC_USART234578CLKSOURCE_HSI (RCC_D2CCIP2R_USART28SEL_0 \| RCC_D2CCIP2R_USART28SEL_1)
AnnaBridge	172:65be27845400	477	#define RCC_USART234578CLKSOURCE_CSI RCC_D2CCIP2R_USART28SEL_2
AnnaBridge	172:65be27845400	478	#define RCC_USART234578CLKSOURCE_LSE (RCC_D2CCIP2R_USART28SEL_0 \| RCC_D2CCIP2R_USART28SEL_2)
AnnaBridge	172:65be27845400	479
AnnaBridge	172:65be27845400	480	/**
AnnaBridge	172:65be27845400	481	* @}
AnnaBridge	172:65be27845400	482	*/
AnnaBridge	172:65be27845400	483
AnnaBridge	172:65be27845400	484	/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
AnnaBridge	172:65be27845400	485	* @{
AnnaBridge	172:65be27845400	486	*/
AnnaBridge	172:65be27845400	487	#define RCC_USART2CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
AnnaBridge	172:65be27845400	488	#define RCC_USART2CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
AnnaBridge	172:65be27845400	489	#define RCC_USART2CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
AnnaBridge	172:65be27845400	490	#define RCC_USART2CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
AnnaBridge	172:65be27845400	491	#define RCC_USART2CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
AnnaBridge	172:65be27845400	492	#define RCC_USART2CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
AnnaBridge	172:65be27845400	493
AnnaBridge	172:65be27845400	494	/**
AnnaBridge	172:65be27845400	495	* @}
AnnaBridge	172:65be27845400	496	*/
AnnaBridge	172:65be27845400	497
AnnaBridge	172:65be27845400	498	/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
AnnaBridge	172:65be27845400	499	* @{
AnnaBridge	172:65be27845400	500	*/
AnnaBridge	172:65be27845400	501	#define RCC_USART3CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
AnnaBridge	172:65be27845400	502	#define RCC_USART3CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
AnnaBridge	172:65be27845400	503	#define RCC_USART3CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
AnnaBridge	172:65be27845400	504	#define RCC_USART3CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
AnnaBridge	172:65be27845400	505	#define RCC_USART3CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
AnnaBridge	172:65be27845400	506	#define RCC_USART3CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
AnnaBridge	172:65be27845400	507
AnnaBridge	172:65be27845400	508	/**
AnnaBridge	172:65be27845400	509	* @}
AnnaBridge	172:65be27845400	510	*/
AnnaBridge	172:65be27845400	511
AnnaBridge	172:65be27845400	512	/** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source
AnnaBridge	172:65be27845400	513	* @{
AnnaBridge	172:65be27845400	514	*/
AnnaBridge	172:65be27845400	515	#define RCC_UART4CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
AnnaBridge	172:65be27845400	516	#define RCC_UART4CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
AnnaBridge	172:65be27845400	517	#define RCC_UART4CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
AnnaBridge	172:65be27845400	518	#define RCC_UART4CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
AnnaBridge	172:65be27845400	519	#define RCC_UART4CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
AnnaBridge	172:65be27845400	520	#define RCC_UART4CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
AnnaBridge	172:65be27845400	521
AnnaBridge	172:65be27845400	522	/**
AnnaBridge	172:65be27845400	523	* @}
AnnaBridge	172:65be27845400	524	*/
AnnaBridge	172:65be27845400	525
AnnaBridge	172:65be27845400	526	/** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source
AnnaBridge	172:65be27845400	527	* @{
AnnaBridge	172:65be27845400	528	*/
AnnaBridge	172:65be27845400	529	#define RCC_UART5CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
AnnaBridge	172:65be27845400	530	#define RCC_UART5CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
AnnaBridge	172:65be27845400	531	#define RCC_UART5CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
AnnaBridge	172:65be27845400	532	#define RCC_UART5CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
AnnaBridge	172:65be27845400	533	#define RCC_UART5CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
AnnaBridge	172:65be27845400	534	#define RCC_UART5CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
AnnaBridge	172:65be27845400	535
AnnaBridge	172:65be27845400	536	/**
AnnaBridge	172:65be27845400	537	* @}
AnnaBridge	172:65be27845400	538	*/
AnnaBridge	172:65be27845400	539
AnnaBridge	172:65be27845400	540	/** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source
AnnaBridge	172:65be27845400	541	* @{
AnnaBridge	172:65be27845400	542	*/
AnnaBridge	172:65be27845400	543	#define RCC_UART7CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
AnnaBridge	172:65be27845400	544	#define RCC_UART7CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
AnnaBridge	172:65be27845400	545	#define RCC_UART7CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
AnnaBridge	172:65be27845400	546	#define RCC_UART7CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
AnnaBridge	172:65be27845400	547	#define RCC_UART7CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
AnnaBridge	172:65be27845400	548	#define RCC_UART7CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
AnnaBridge	172:65be27845400	549
AnnaBridge	172:65be27845400	550	/**
AnnaBridge	172:65be27845400	551	* @}
AnnaBridge	172:65be27845400	552	*/
AnnaBridge	172:65be27845400	553
AnnaBridge	172:65be27845400	554	/** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source
AnnaBridge	172:65be27845400	555	* @{
AnnaBridge	172:65be27845400	556	*/
AnnaBridge	172:65be27845400	557	#define RCC_UART8CLKSOURCE_D2PCLK1 RCC_USART234578CLKSOURCE_D2PCLK1
AnnaBridge	172:65be27845400	558	#define RCC_UART8CLKSOURCE_PLL2 RCC_USART234578CLKSOURCE_PLL2
AnnaBridge	172:65be27845400	559	#define RCC_UART8CLKSOURCE_PLL3 RCC_USART234578CLKSOURCE_PLL3
AnnaBridge	172:65be27845400	560	#define RCC_UART8CLKSOURCE_HSI RCC_USART234578CLKSOURCE_HSI
AnnaBridge	172:65be27845400	561	#define RCC_UART8CLKSOURCE_CSI RCC_USART234578CLKSOURCE_CSI
AnnaBridge	172:65be27845400	562	#define RCC_UART8CLKSOURCE_LSE RCC_USART234578CLKSOURCE_LSE
AnnaBridge	172:65be27845400	563
AnnaBridge	172:65be27845400	564	/**
AnnaBridge	172:65be27845400	565	* @}
AnnaBridge	172:65be27845400	566	*/
AnnaBridge	172:65be27845400	567
AnnaBridge	172:65be27845400	568	/** @defgroup RCCEx_LPUART1_Clock_Source RCCEx LPUART1 Clock Source
AnnaBridge	172:65be27845400	569	* @{
AnnaBridge	172:65be27845400	570	*/
AnnaBridge	172:65be27845400	571	#define RCC_LPUART1CLKSOURCE_D3PCLK1 (0x00000000U)
AnnaBridge	172:65be27845400	572	#define RCC_LPUART1CLKSOURCE_PLL2 RCC_D3CCIPR_LPUART1SEL_0
AnnaBridge	172:65be27845400	573	#define RCC_LPUART1CLKSOURCE_PLL3 RCC_D3CCIPR_LPUART1SEL_1
AnnaBridge	172:65be27845400	574	#define RCC_LPUART1CLKSOURCE_HSI (RCC_D3CCIPR_LPUART1SEL_0 \| RCC_D3CCIPR_LPUART1SEL_1)
AnnaBridge	172:65be27845400	575	#define RCC_LPUART1CLKSOURCE_CSI RCC_D3CCIPR_LPUART1SEL_2
AnnaBridge	172:65be27845400	576	#define RCC_LPUART1CLKSOURCE_LSE (RCC_D3CCIPR_LPUART1SEL_2 \| RCC_D3CCIPR_LPUART1SEL_0)
AnnaBridge	172:65be27845400	577
AnnaBridge	172:65be27845400	578	/**
AnnaBridge	172:65be27845400	579	* @}
AnnaBridge	172:65be27845400	580	*/
AnnaBridge	172:65be27845400	581
AnnaBridge	172:65be27845400	582	/** @defgroup RCCEx_I2C123_Clock_Source RCCEx I2C1/2/3 Clock Source
AnnaBridge	172:65be27845400	583	* @{
AnnaBridge	172:65be27845400	584	*/
AnnaBridge	172:65be27845400	585	#define RCC_I2C123CLKSOURCE_D2PCLK1 (0x00000000U)
AnnaBridge	172:65be27845400	586	#define RCC_I2C123CLKSOURCE_PLL3 RCC_D2CCIP2R_I2C123SEL_0
AnnaBridge	172:65be27845400	587	#define RCC_I2C123CLKSOURCE_HSI RCC_D2CCIP2R_I2C123SEL_1
AnnaBridge	172:65be27845400	588	#define RCC_I2C123CLKSOURCE_CSI (RCC_D2CCIP2R_I2C123SEL_0 \| RCC_D2CCIP2R_I2C123SEL_1)
AnnaBridge	172:65be27845400	589
AnnaBridge	172:65be27845400	590	/**
AnnaBridge	172:65be27845400	591	* @}
AnnaBridge	172:65be27845400	592	*/
AnnaBridge	172:65be27845400	593
AnnaBridge	172:65be27845400	594	/** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source
AnnaBridge	172:65be27845400	595	* @{
AnnaBridge	172:65be27845400	596	*/
AnnaBridge	172:65be27845400	597	#define RCC_I2C1CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1
AnnaBridge	172:65be27845400	598	#define RCC_I2C1CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3
AnnaBridge	172:65be27845400	599	#define RCC_I2C1CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI
AnnaBridge	172:65be27845400	600	#define RCC_I2C1CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI
AnnaBridge	172:65be27845400	601
AnnaBridge	172:65be27845400	602
AnnaBridge	172:65be27845400	603	/**
AnnaBridge	172:65be27845400	604	* @}
AnnaBridge	172:65be27845400	605	*/
AnnaBridge	172:65be27845400	606
AnnaBridge	172:65be27845400	607	/** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source
AnnaBridge	172:65be27845400	608	* @{
AnnaBridge	172:65be27845400	609	*/
AnnaBridge	172:65be27845400	610	#define RCC_I2C2CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1
AnnaBridge	172:65be27845400	611	#define RCC_I2C2CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3
AnnaBridge	172:65be27845400	612	#define RCC_I2C2CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI
AnnaBridge	172:65be27845400	613	#define RCC_I2C2CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI
AnnaBridge	172:65be27845400	614
AnnaBridge	172:65be27845400	615	/**
AnnaBridge	172:65be27845400	616	* @}
AnnaBridge	172:65be27845400	617	*/
AnnaBridge	172:65be27845400	618
AnnaBridge	172:65be27845400	619	/** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source
AnnaBridge	172:65be27845400	620	* @{
AnnaBridge	172:65be27845400	621	*/
AnnaBridge	172:65be27845400	622	#define RCC_I2C3CLKSOURCE_D2PCLK1 RCC_I2C123CLKSOURCE_D2PCLK1
AnnaBridge	172:65be27845400	623	#define RCC_I2C3CLKSOURCE_PLL3 RCC_I2C123CLKSOURCE_PLL3
AnnaBridge	172:65be27845400	624	#define RCC_I2C3CLKSOURCE_HSI RCC_I2C123CLKSOURCE_HSI
AnnaBridge	172:65be27845400	625	#define RCC_I2C3CLKSOURCE_CSI RCC_I2C123CLKSOURCE_CSI
AnnaBridge	172:65be27845400	626
AnnaBridge	172:65be27845400	627	/**
AnnaBridge	172:65be27845400	628	* @}
AnnaBridge	172:65be27845400	629	*/
AnnaBridge	172:65be27845400	630
AnnaBridge	172:65be27845400	631	/** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source
AnnaBridge	172:65be27845400	632	* @{
AnnaBridge	172:65be27845400	633	*/
AnnaBridge	172:65be27845400	634	#define RCC_I2C4CLKSOURCE_D3PCLK1 (0x00000000U)
AnnaBridge	172:65be27845400	635	#define RCC_I2C4CLKSOURCE_PLL3 RCC_D3CCIPR_I2C4SEL_0
AnnaBridge	172:65be27845400	636	#define RCC_I2C4CLKSOURCE_HSI RCC_D3CCIPR_I2C4SEL_1
AnnaBridge	172:65be27845400	637	#define RCC_I2C4CLKSOURCE_CSI (RCC_D3CCIPR_I2C4SEL_0 \| RCC_D3CCIPR_I2C4SEL_1)
AnnaBridge	172:65be27845400	638
AnnaBridge	172:65be27845400	639
AnnaBridge	172:65be27845400	640	/**
AnnaBridge	172:65be27845400	641	* @}
AnnaBridge	172:65be27845400	642	*/
AnnaBridge	172:65be27845400	643
AnnaBridge	172:65be27845400	644	/** @defgroup RCCEx_RNG_Clock_Source RCCEx RNG Clock Source
AnnaBridge	172:65be27845400	645	* @{
AnnaBridge	172:65be27845400	646	*/
AnnaBridge	172:65be27845400	647	#define RCC_RNGCLKSOURCE_HSI48 (0x00000000U)
AnnaBridge	172:65be27845400	648	#define RCC_RNGCLKSOURCE_PLL RCC_D2CCIP2R_RNGSEL_0
AnnaBridge	172:65be27845400	649	#define RCC_RNGCLKSOURCE_LSE RCC_D2CCIP2R_RNGSEL_1
AnnaBridge	172:65be27845400	650	#define RCC_RNGCLKSOURCE_LSI RCC_D2CCIP2R_RNGSEL
AnnaBridge	172:65be27845400	651
AnnaBridge	172:65be27845400	652
AnnaBridge	172:65be27845400	653	/**
AnnaBridge	172:65be27845400	654	* @}
AnnaBridge	172:65be27845400	655	*/
AnnaBridge	172:65be27845400	656
AnnaBridge	172:65be27845400	657	/** @defgroup RCCEx_HRTIM1_Clock_Source RCC Extended HRTIM1 Clock Source
AnnaBridge	172:65be27845400	658	* @{
AnnaBridge	172:65be27845400	659	*/
AnnaBridge	172:65be27845400	660	#define RCC_HRTIM1CLK_TIMCLK (0x00000000U)
AnnaBridge	172:65be27845400	661	#define RCC_HRTIM1CLK_CPUCLK RCC_CFGR_HRTIMSEL
AnnaBridge	172:65be27845400	662
AnnaBridge	172:65be27845400	663	/**
AnnaBridge	172:65be27845400	664	* @}
AnnaBridge	172:65be27845400	665	*/
AnnaBridge	172:65be27845400	666
AnnaBridge	172:65be27845400	667	/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
AnnaBridge	172:65be27845400	668	* @{
AnnaBridge	172:65be27845400	669	*/
AnnaBridge	172:65be27845400	670	#define RCC_USBCLKSOURCE_PLL RCC_D2CCIP2R_USBSEL_0
AnnaBridge	172:65be27845400	671	#define RCC_USBCLKSOURCE_PLL3 RCC_D2CCIP2R_USBSEL_1
AnnaBridge	172:65be27845400	672	#define RCC_USBCLKSOURCE_HSI48 RCC_D2CCIP2R_USBSEL
AnnaBridge	172:65be27845400	673
AnnaBridge	172:65be27845400	674	/**
AnnaBridge	172:65be27845400	675	* @}
AnnaBridge	172:65be27845400	676	*/
AnnaBridge	172:65be27845400	677
AnnaBridge	172:65be27845400	678	/** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source
AnnaBridge	172:65be27845400	679	* @{
AnnaBridge	172:65be27845400	680	*/
AnnaBridge	172:65be27845400	681	#define RCC_SAI1CLKSOURCE_PLL (0x00000000U)
AnnaBridge	172:65be27845400	682	#define RCC_SAI1CLKSOURCE_PLL2 RCC_D2CCIP1R_SAI1SEL_0
AnnaBridge	172:65be27845400	683	#define RCC_SAI1CLKSOURCE_PLL3 RCC_D2CCIP1R_SAI1SEL_1
AnnaBridge	172:65be27845400	684	#define RCC_SAI1CLKSOURCE_PIN (RCC_D2CCIP1R_SAI1SEL_0 \| RCC_D2CCIP1R_SAI1SEL_1)
AnnaBridge	172:65be27845400	685	#define RCC_SAI1CLKSOURCE_CLKP RCC_D2CCIP1R_SAI1SEL_2
AnnaBridge	172:65be27845400	686
AnnaBridge	172:65be27845400	687	/**
AnnaBridge	172:65be27845400	688	* @}
AnnaBridge	172:65be27845400	689	*/
AnnaBridge	172:65be27845400	690
AnnaBridge	172:65be27845400	691
AnnaBridge	172:65be27845400	692
AnnaBridge	172:65be27845400	693	/** @defgroup RCCEx_SAI23_Clock_Source SAI2/3 Clock Source
AnnaBridge	172:65be27845400	694	* @{
AnnaBridge	172:65be27845400	695	*/
AnnaBridge	172:65be27845400	696	#define RCC_SAI23CLKSOURCE_PLL (0x00000000U)
AnnaBridge	172:65be27845400	697	#define RCC_SAI23CLKSOURCE_PLL2 RCC_D2CCIP1R_SAI23SEL_0
AnnaBridge	172:65be27845400	698	#define RCC_SAI23CLKSOURCE_PLL3 RCC_D2CCIP1R_SAI23SEL_1
AnnaBridge	172:65be27845400	699	#define RCC_SAI23CLKSOURCE_PIN (RCC_D2CCIP1R_SAI23SEL_0 \| RCC_D2CCIP1R_SAI23SEL_1)
AnnaBridge	172:65be27845400	700	#define RCC_SAI23CLKSOURCE_CLKP RCC_D2CCIP1R_SAI23SEL_2
AnnaBridge	172:65be27845400	701
AnnaBridge	172:65be27845400	702	/**
AnnaBridge	172:65be27845400	703	* @}
AnnaBridge	172:65be27845400	704	*/
AnnaBridge	172:65be27845400	705
AnnaBridge	172:65be27845400	706	/** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source
AnnaBridge	172:65be27845400	707	* @{
AnnaBridge	172:65be27845400	708	*/
AnnaBridge	172:65be27845400	709	#define RCC_SAI2CLKSOURCE_PLL RCC_SAI23CLKSOURCE_PLL
AnnaBridge	172:65be27845400	710	#define RCC_SAI2CLKSOURCE_PLL2 RCC_SAI23CLKSOURCE_PLL2
AnnaBridge	172:65be27845400	711	#define RCC_SAI2CLKSOURCE_PLL3 RCC_SAI23CLKSOURCE_PLL3
AnnaBridge	172:65be27845400	712	#define RCC_SAI2CLKSOURCE_PIN RCC_SAI23CLKSOURCE_PIN
AnnaBridge	172:65be27845400	713	#define RCC_SAI2CLKSOURCE_CLKP RCC_SAI23CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	714
AnnaBridge	172:65be27845400	715	/**
AnnaBridge	172:65be27845400	716	* @}
AnnaBridge	172:65be27845400	717	*/
AnnaBridge	172:65be27845400	718
AnnaBridge	172:65be27845400	719	/** @defgroup RCCEx_SAI3_Clock_Source SAI3 Clock Source
AnnaBridge	172:65be27845400	720	* @{
AnnaBridge	172:65be27845400	721	*/
AnnaBridge	172:65be27845400	722	#define RCC_SAI3CLKSOURCE_PLL RCC_SAI23CLKSOURCE_PLL
AnnaBridge	172:65be27845400	723	#define RCC_SAI3CLKSOURCE_PLL2 RCC_SAI23CLKSOURCE_PLL2
AnnaBridge	172:65be27845400	724	#define RCC_SAI3CLKSOURCE_PLL3 RCC_SAI23CLKSOURCE_PLL3
AnnaBridge	172:65be27845400	725	#define RCC_SAI3CLKSOURCE_PIN RCC_SAI23CLKSOURCE_PIN
AnnaBridge	172:65be27845400	726	#define RCC_SAI3CLKSOURCE_CLKP RCC_SAI23CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	727
AnnaBridge	172:65be27845400	728	/**
AnnaBridge	172:65be27845400	729	* @}
AnnaBridge	172:65be27845400	730	*/
AnnaBridge	172:65be27845400	731
AnnaBridge	172:65be27845400	732	/** @defgroup RCCEx_SPI123_Clock_Source SPI1/2/3 Clock Source
AnnaBridge	172:65be27845400	733	* @{
AnnaBridge	172:65be27845400	734	*/
AnnaBridge	172:65be27845400	735	#define RCC_SPI123CLKSOURCE_PLL (0x00000000U)
AnnaBridge	172:65be27845400	736	#define RCC_SPI123CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI123SEL_0
AnnaBridge	172:65be27845400	737	#define RCC_SPI123CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI123SEL_1
AnnaBridge	172:65be27845400	738	#define RCC_SPI123CLKSOURCE_PIN (RCC_D2CCIP1R_SPI123SEL_0 \| RCC_D2CCIP1R_SPI123SEL_1)
AnnaBridge	172:65be27845400	739	#define RCC_SPI123CLKSOURCE_CLKP RCC_D2CCIP1R_SPI123SEL_2
AnnaBridge	172:65be27845400	740
AnnaBridge	172:65be27845400	741	/**
AnnaBridge	172:65be27845400	742	* @}
AnnaBridge	172:65be27845400	743	*/
AnnaBridge	172:65be27845400	744
AnnaBridge	172:65be27845400	745	/** @defgroup RCCEx_SPI1_Clock_Source SPI1 Clock Source
AnnaBridge	172:65be27845400	746	* @{
AnnaBridge	172:65be27845400	747	*/
AnnaBridge	172:65be27845400	748	#define RCC_SPI1CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL
AnnaBridge	172:65be27845400	749	#define RCC_SPI1CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2
AnnaBridge	172:65be27845400	750	#define RCC_SPI1CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3
AnnaBridge	172:65be27845400	751	#define RCC_SPI1CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN
AnnaBridge	172:65be27845400	752	#define RCC_SPI1CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	753
AnnaBridge	172:65be27845400	754	/**
AnnaBridge	172:65be27845400	755	* @}
AnnaBridge	172:65be27845400	756	*/
AnnaBridge	172:65be27845400	757
AnnaBridge	172:65be27845400	758	/** @defgroup RCCEx_SPI2_Clock_Source SPI2 Clock Source
AnnaBridge	172:65be27845400	759	* @{
AnnaBridge	172:65be27845400	760	*/
AnnaBridge	172:65be27845400	761	#define RCC_SPI2CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL
AnnaBridge	172:65be27845400	762	#define RCC_SPI2CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2
AnnaBridge	172:65be27845400	763	#define RCC_SPI2CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3
AnnaBridge	172:65be27845400	764	#define RCC_SPI2CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN
AnnaBridge	172:65be27845400	765	#define RCC_SPI2CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	766
AnnaBridge	172:65be27845400	767	/**
AnnaBridge	172:65be27845400	768	* @}
AnnaBridge	172:65be27845400	769	*/
AnnaBridge	172:65be27845400	770
AnnaBridge	172:65be27845400	771	/** @defgroup RCCEx_SPI3_Clock_Source SPI3 Clock Source
AnnaBridge	172:65be27845400	772	* @{
AnnaBridge	172:65be27845400	773	*/
AnnaBridge	172:65be27845400	774	#define RCC_SPI3CLKSOURCE_PLL RCC_SPI123CLKSOURCE_PLL
AnnaBridge	172:65be27845400	775	#define RCC_SPI3CLKSOURCE_PLL2 RCC_SPI123CLKSOURCE_PLL2
AnnaBridge	172:65be27845400	776	#define RCC_SPI3CLKSOURCE_PLL3 RCC_SPI123CLKSOURCE_PLL3
AnnaBridge	172:65be27845400	777	#define RCC_SPI3CLKSOURCE_PIN RCC_SPI123CLKSOURCE_PIN
AnnaBridge	172:65be27845400	778	#define RCC_SPI3CLKSOURCE_CLKP RCC_SPI123CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	779
AnnaBridge	172:65be27845400	780	/**
AnnaBridge	172:65be27845400	781	* @}
AnnaBridge	172:65be27845400	782	*/
AnnaBridge	172:65be27845400	783
AnnaBridge	172:65be27845400	784	/** @defgroup RCCEx_SPI45_Clock_Source SPI4/5 Clock Source
AnnaBridge	172:65be27845400	785	* @{
AnnaBridge	172:65be27845400	786	*/
AnnaBridge	172:65be27845400	787	#define RCC_SPI45CLKSOURCE_D2PCLK1 (0x00000000U)
AnnaBridge	172:65be27845400	788	#define RCC_SPI45CLKSOURCE_PLL2 RCC_D2CCIP1R_SPI45SEL_0
AnnaBridge	172:65be27845400	789	#define RCC_SPI45CLKSOURCE_PLL3 RCC_D2CCIP1R_SPI45SEL_1
AnnaBridge	172:65be27845400	790	#define RCC_SPI45CLKSOURCE_HSI (RCC_D2CCIP1R_SPI45SEL_0 \| RCC_D2CCIP1R_SPI45SEL_1)
AnnaBridge	172:65be27845400	791	#define RCC_SPI45CLKSOURCE_CSI RCC_D2CCIP1R_SPI45SEL_2
AnnaBridge	172:65be27845400	792	#define RCC_SPI45CLKSOURCE_HSE (RCC_D2CCIP1R_SPI45SEL_0 \| RCC_D2CCIP1R_SPI45SEL_2)
AnnaBridge	172:65be27845400	793
AnnaBridge	172:65be27845400	794	/**
AnnaBridge	172:65be27845400	795	* @}
AnnaBridge	172:65be27845400	796	*/
AnnaBridge	172:65be27845400	797
AnnaBridge	172:65be27845400	798	/** @defgroup RCCEx_SPI4_Clock_Source SPI4 Clock Source
AnnaBridge	172:65be27845400	799	* @{
AnnaBridge	172:65be27845400	800	*/
AnnaBridge	172:65be27845400	801	#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK1
AnnaBridge	172:65be27845400	802	#define RCC_SPI4CLKSOURCE_PLL2 RCC_SPI45CLKSOURCE_PLL2
AnnaBridge	172:65be27845400	803	#define RCC_SPI4CLKSOURCE_PLL3 RCC_SPI45CLKSOURCE_PLL3
AnnaBridge	172:65be27845400	804	#define RCC_SPI4CLKSOURCE_HSI RCC_SPI45CLKSOURCE_HSI
AnnaBridge	172:65be27845400	805	#define RCC_SPI4CLKSOURCE_CSI RCC_SPI45CLKSOURCE_CSI
AnnaBridge	172:65be27845400	806	#define RCC_SPI4CLKSOURCE_HSE RCC_SPI45CLKSOURCE_HSE
AnnaBridge	172:65be27845400	807
AnnaBridge	172:65be27845400	808	/**
AnnaBridge	172:65be27845400	809	* @}
AnnaBridge	172:65be27845400	810	*/
AnnaBridge	172:65be27845400	811
AnnaBridge	172:65be27845400	812	/** @defgroup RCCEx_SPI5_Clock_Source SPI5 Clock Source
AnnaBridge	172:65be27845400	813	* @{
AnnaBridge	172:65be27845400	814	*/
AnnaBridge	172:65be27845400	815	#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK1
AnnaBridge	172:65be27845400	816	#define RCC_SPI5CLKSOURCE_PLL2 RCC_SPI45CLKSOURCE_PLL2
AnnaBridge	172:65be27845400	817	#define RCC_SPI5CLKSOURCE_PLL3 RCC_SPI45CLKSOURCE_PLL3
AnnaBridge	172:65be27845400	818	#define RCC_SPI5CLKSOURCE_HSI RCC_SPI45CLKSOURCE_HSI
AnnaBridge	172:65be27845400	819	#define RCC_SPI5CLKSOURCE_CSI RCC_SPI45CLKSOURCE_CSI
AnnaBridge	172:65be27845400	820	#define RCC_SPI5CLKSOURCE_HSE RCC_SPI45CLKSOURCE_HSE
AnnaBridge	172:65be27845400	821
AnnaBridge	172:65be27845400	822	/**
AnnaBridge	172:65be27845400	823	* @}
AnnaBridge	172:65be27845400	824	*/
AnnaBridge	172:65be27845400	825
AnnaBridge	172:65be27845400	826	/** @defgroup RCCEx_SPI6_Clock_Source SPI6 Clock Source
AnnaBridge	172:65be27845400	827	* @{
AnnaBridge	172:65be27845400	828	*/
AnnaBridge	172:65be27845400	829	#define RCC_SPI6CLKSOURCE_D3PCLK1 (0x00000000U)
AnnaBridge	172:65be27845400	830	#define RCC_SPI6CLKSOURCE_PLL2 RCC_D3CCIPR_SPI6SEL_0
AnnaBridge	172:65be27845400	831	#define RCC_SPI6CLKSOURCE_PLL3 RCC_D3CCIPR_SPI6SEL_1
AnnaBridge	172:65be27845400	832	#define RCC_SPI6CLKSOURCE_HSI (RCC_D3CCIPR_SPI6SEL_0 \| RCC_D3CCIPR_SPI6SEL_1)
AnnaBridge	172:65be27845400	833	#define RCC_SPI6CLKSOURCE_CSI RCC_D3CCIPR_SPI6SEL_2
AnnaBridge	172:65be27845400	834	#define RCC_SPI6CLKSOURCE_HSE (RCC_D3CCIPR_SPI6SEL_0 \| RCC_D3CCIPR_SPI6SEL_2)
AnnaBridge	172:65be27845400	835
AnnaBridge	172:65be27845400	836
AnnaBridge	172:65be27845400	837	/**
AnnaBridge	172:65be27845400	838	* @}
AnnaBridge	172:65be27845400	839	*/
AnnaBridge	172:65be27845400	840
AnnaBridge	172:65be27845400	841
AnnaBridge	172:65be27845400	842	/** @defgroup RCCEx_SAI4A_Clock_Source SAI4A Clock Source
AnnaBridge	172:65be27845400	843	* @{
AnnaBridge	172:65be27845400	844	*/
AnnaBridge	172:65be27845400	845	#define RCC_SAI4ACLKSOURCE_PLL (0x00000000U)
AnnaBridge	172:65be27845400	846	#define RCC_SAI4ACLKSOURCE_PLL2 RCC_D3CCIPR_SAI4ASEL_0
AnnaBridge	172:65be27845400	847	#define RCC_SAI4ACLKSOURCE_PLL3 RCC_D3CCIPR_SAI4ASEL_1
AnnaBridge	172:65be27845400	848	#define RCC_SAI4ACLKSOURCE_PIN (RCC_D3CCIPR_SAI4ASEL_0 \| RCC_D3CCIPR_SAI4ASEL_1)
AnnaBridge	172:65be27845400	849	#define RCC_SAI4ACLKSOURCE_CLKP RCC_D3CCIPR_SAI4ASEL_2
AnnaBridge	172:65be27845400	850
AnnaBridge	172:65be27845400	851
AnnaBridge	172:65be27845400	852	/**
AnnaBridge	172:65be27845400	853	* @}
AnnaBridge	172:65be27845400	854	*/
AnnaBridge	172:65be27845400	855
AnnaBridge	172:65be27845400	856
AnnaBridge	172:65be27845400	857	/** @defgroup RCCEx_SAI4B_Clock_Source SAI4B Clock Source
AnnaBridge	172:65be27845400	858	* @{
AnnaBridge	172:65be27845400	859	*/
AnnaBridge	172:65be27845400	860	#define RCC_SAI4BCLKSOURCE_PLL (0x00000000U)
AnnaBridge	172:65be27845400	861	#define RCC_SAI4BCLKSOURCE_PLL2 RCC_D3CCIPR_SAI4BSEL_0
AnnaBridge	172:65be27845400	862	#define RCC_SAI4BCLKSOURCE_PLL3 RCC_D3CCIPR_SAI4BSEL_1
AnnaBridge	172:65be27845400	863	#define RCC_SAI4BCLKSOURCE_PIN (RCC_D3CCIPR_SAI4BSEL_0 \| RCC_D3CCIPR_SAI4BSEL_1)
AnnaBridge	172:65be27845400	864	#define RCC_SAI4BCLKSOURCE_CLKP RCC_D3CCIPR_SAI4BSEL_2
AnnaBridge	172:65be27845400	865
AnnaBridge	172:65be27845400	866	/**
AnnaBridge	172:65be27845400	867	* @}
AnnaBridge	172:65be27845400	868	*/
AnnaBridge	172:65be27845400	869
AnnaBridge	172:65be27845400	870
AnnaBridge	172:65be27845400	871	/** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source
AnnaBridge	172:65be27845400	872	* @{
AnnaBridge	172:65be27845400	873	*/
AnnaBridge	172:65be27845400	874	#define RCC_LPTIM1CLKSOURCE_D2PCLK1 (0x00000000U)
AnnaBridge	172:65be27845400	875	#define RCC_LPTIM1CLKSOURCE_PLL2 RCC_D2CCIP2R_LPTIM1SEL_0
AnnaBridge	172:65be27845400	876	#define RCC_LPTIM1CLKSOURCE_PLL3 RCC_D2CCIP2R_LPTIM1SEL_1
AnnaBridge	172:65be27845400	877	#define RCC_LPTIM1CLKSOURCE_LSE (RCC_D2CCIP2R_LPTIM1SEL_0 \| RCC_D2CCIP2R_LPTIM1SEL_1)
AnnaBridge	172:65be27845400	878	#define RCC_LPTIM1CLKSOURCE_LSI RCC_D2CCIP2R_LPTIM1SEL_2
AnnaBridge	172:65be27845400	879	#define RCC_LPTIM1CLKSOURCE_CLKP (RCC_D2CCIP2R_LPTIM1SEL_0 \| RCC_D2CCIP2R_LPTIM1SEL_2)
AnnaBridge	172:65be27845400	880
AnnaBridge	172:65be27845400	881
AnnaBridge	172:65be27845400	882	/**
AnnaBridge	172:65be27845400	883	* @}
AnnaBridge	172:65be27845400	884	*/
AnnaBridge	172:65be27845400	885
AnnaBridge	172:65be27845400	886	/** @defgroup RCCEx_LPTIM2_Clock_Source RCCEx LPTIM2 Clock Source
AnnaBridge	172:65be27845400	887	* @{
AnnaBridge	172:65be27845400	888	*/
AnnaBridge	172:65be27845400	889	#define RCC_LPTIM2CLKSOURCE_D3PCLK1 (0x00000000U)
AnnaBridge	172:65be27845400	890	#define RCC_LPTIM2CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM2SEL_0
AnnaBridge	172:65be27845400	891	#define RCC_LPTIM2CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM2SEL_1
AnnaBridge	172:65be27845400	892	#define RCC_LPTIM2CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM2SEL_0 \| RCC_D3CCIPR_LPTIM2SEL_1)
AnnaBridge	172:65be27845400	893	#define RCC_LPTIM2CLKSOURCE_LSI RCC_D3CCIPR_LPTIM2SEL_2
AnnaBridge	172:65be27845400	894	#define RCC_LPTIM2CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM2SEL_0 \| RCC_D3CCIPR_LPTIM2SEL_2)
AnnaBridge	172:65be27845400	895
AnnaBridge	172:65be27845400	896	/**
AnnaBridge	172:65be27845400	897	* @}
AnnaBridge	172:65be27845400	898	*/
AnnaBridge	172:65be27845400	899
AnnaBridge	172:65be27845400	900	/** @defgroup RCCEx_LPTIM345_Clock_Source RCCEx LPTIM3/4/5 Clock Source
AnnaBridge	172:65be27845400	901	* @{
AnnaBridge	172:65be27845400	902	*/
AnnaBridge	172:65be27845400	903	#define RCC_LPTIM345CLKSOURCE_D3PCLK1 (0x00000000U)
AnnaBridge	172:65be27845400	904	#define RCC_LPTIM345CLKSOURCE_PLL2 RCC_D3CCIPR_LPTIM345SEL_0
AnnaBridge	172:65be27845400	905	#define RCC_LPTIM345CLKSOURCE_PLL3 RCC_D3CCIPR_LPTIM345SEL_1
AnnaBridge	172:65be27845400	906	#define RCC_LPTIM345CLKSOURCE_LSE (RCC_D3CCIPR_LPTIM345SEL_0 \| RCC_D3CCIPR_LPTIM345SEL_1)
AnnaBridge	172:65be27845400	907	#define RCC_LPTIM345CLKSOURCE_LSI RCC_D3CCIPR_LPTIM345SEL_2
AnnaBridge	172:65be27845400	908	#define RCC_LPTIM345CLKSOURCE_CLKP (RCC_D3CCIPR_LPTIM345SEL_0 \| RCC_D3CCIPR_LPTIM345SEL_2)
AnnaBridge	172:65be27845400	909
AnnaBridge	172:65be27845400	910	/**
AnnaBridge	172:65be27845400	911	* @}
AnnaBridge	172:65be27845400	912	*/
AnnaBridge	172:65be27845400	913
AnnaBridge	172:65be27845400	914	/** @defgroup RCCEx_LPTIM3_Clock_Source RCCEx LPTIM3 Clock Source
AnnaBridge	172:65be27845400	915	* @{
AnnaBridge	172:65be27845400	916	*/
AnnaBridge	172:65be27845400	917	#define RCC_LPTIM3CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1
AnnaBridge	172:65be27845400	918	#define RCC_LPTIM3CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2
AnnaBridge	172:65be27845400	919	#define RCC_LPTIM3CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3
AnnaBridge	172:65be27845400	920	#define RCC_LPTIM3CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE
AnnaBridge	172:65be27845400	921	#define RCC_LPTIM3CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI
AnnaBridge	172:65be27845400	922	#define RCC_LPTIM3CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	923
AnnaBridge	172:65be27845400	924	/**
AnnaBridge	172:65be27845400	925	* @}
AnnaBridge	172:65be27845400	926	*/
AnnaBridge	172:65be27845400	927
AnnaBridge	172:65be27845400	928	/** @defgroup RCCEx_LPTIM4_Clock_Source RCCEx LPTIM4 Clock Source
AnnaBridge	172:65be27845400	929	* @{
AnnaBridge	172:65be27845400	930	*/
AnnaBridge	172:65be27845400	931	#define RCC_LPTIM4CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1
AnnaBridge	172:65be27845400	932	#define RCC_LPTIM4CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2
AnnaBridge	172:65be27845400	933	#define RCC_LPTIM4CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3
AnnaBridge	172:65be27845400	934	#define RCC_LPTIM4CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE
AnnaBridge	172:65be27845400	935	#define RCC_LPTIM4CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI
AnnaBridge	172:65be27845400	936	#define RCC_LPTIM4CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	937
AnnaBridge	172:65be27845400	938	/**
AnnaBridge	172:65be27845400	939	* @}
AnnaBridge	172:65be27845400	940	*/
AnnaBridge	172:65be27845400	941
AnnaBridge	172:65be27845400	942	/** @defgroup RCCEx_LPTIM5_Clock_Source RCCEx LPTIM5 Clock Source
AnnaBridge	172:65be27845400	943	* @{
AnnaBridge	172:65be27845400	944	*/
AnnaBridge	172:65be27845400	945	#define RCC_LPTIM5CLKSOURCE_D3PCLK1 RCC_LPTIM345CLKSOURCE_D3PCLK1
AnnaBridge	172:65be27845400	946	#define RCC_LPTIM5CLKSOURCE_PLL2 RCC_LPTIM345CLKSOURCE_PLL2
AnnaBridge	172:65be27845400	947	#define RCC_LPTIM5CLKSOURCE_PLL3 RCC_LPTIM345CLKSOURCE_PLL3
AnnaBridge	172:65be27845400	948	#define RCC_LPTIM5CLKSOURCE_LSE RCC_LPTIM345CLKSOURCE_LSE
AnnaBridge	172:65be27845400	949	#define RCC_LPTIM5CLKSOURCE_LSI RCC_LPTIM345CLKSOURCE_LSI
AnnaBridge	172:65be27845400	950	#define RCC_LPTIM5CLKSOURCE_CLKP RCC_LPTIM345CLKSOURCE_CLKP
AnnaBridge	172:65be27845400	951
AnnaBridge	172:65be27845400	952	/**
AnnaBridge	172:65be27845400	953	* @}
AnnaBridge	172:65be27845400	954	*/
AnnaBridge	172:65be27845400	955
AnnaBridge	172:65be27845400	956	/** @defgroup RCCEx_QSPI_Clock_Source RCCEx QSPI Clock Source
AnnaBridge	172:65be27845400	957	* @{
AnnaBridge	172:65be27845400	958	*/
AnnaBridge	172:65be27845400	959	#define RCC_QSPICLKSOURCE_D1HCLK (0x00000000U)
AnnaBridge	172:65be27845400	960	#define RCC_QSPICLKSOURCE_PLL RCC_D1CCIPR_QSPISEL_0
AnnaBridge	172:65be27845400	961	#define RCC_QSPICLKSOURCE_PLL2 RCC_D1CCIPR_QSPISEL_1
AnnaBridge	172:65be27845400	962	#define RCC_QSPICLKSOURCE_CLKP RCC_D1CCIPR_QSPISEL
AnnaBridge	172:65be27845400	963
AnnaBridge	172:65be27845400	964
AnnaBridge	172:65be27845400	965
AnnaBridge	172:65be27845400	966	/**
AnnaBridge	172:65be27845400	967	* @}
AnnaBridge	172:65be27845400	968	*/
AnnaBridge	172:65be27845400	969
AnnaBridge	172:65be27845400	970	/** @defgroup RCCEx_FMC_Clock_Source RCCEx FMC Clock Source
AnnaBridge	172:65be27845400	971	* @{
AnnaBridge	172:65be27845400	972	*/
AnnaBridge	172:65be27845400	973	#define RCC_FMCCLKSOURCE_D1HCLK (0x00000000U)
AnnaBridge	172:65be27845400	974	#define RCC_FMCCLKSOURCE_PLL RCC_D1CCIPR_FMCSEL_0
AnnaBridge	172:65be27845400	975	#define RCC_FMCCLKSOURCE_PLL2 RCC_D1CCIPR_FMCSEL_1
AnnaBridge	172:65be27845400	976	#define RCC_FMCCLKSOURCE_CLKP RCC_D1CCIPR_FMCSEL
AnnaBridge	172:65be27845400	977
AnnaBridge	172:65be27845400	978	/**
AnnaBridge	172:65be27845400	979	* @}
AnnaBridge	172:65be27845400	980	*/
AnnaBridge	172:65be27845400	981
AnnaBridge	172:65be27845400	982	#if defined(FDCAN1) \|\| defined(FDCAN2)
AnnaBridge	172:65be27845400	983	/** @defgroup RCCEx_FDCAN_Clock_Source RCCEx FDCAN Clock Source
AnnaBridge	172:65be27845400	984	* @{
AnnaBridge	172:65be27845400	985	*/
AnnaBridge	172:65be27845400	986
AnnaBridge	172:65be27845400	987	#define RCC_FDCANCLKSOURCE_HSE (0x00000000U)
AnnaBridge	172:65be27845400	988	#define RCC_FDCANCLKSOURCE_PLL RCC_D2CCIP1R_FDCANSEL_0
AnnaBridge	172:65be27845400	989	#define RCC_FDCANCLKSOURCE_PLL2 RCC_D2CCIP1R_FDCANSEL_1
AnnaBridge	172:65be27845400	990
AnnaBridge	172:65be27845400	991	/**
AnnaBridge	172:65be27845400	992	* @}
AnnaBridge	172:65be27845400	993	*/
AnnaBridge	172:65be27845400	994	#endif /FDCAN1 \|\| FDCAN2/
AnnaBridge	172:65be27845400	995
AnnaBridge	172:65be27845400	996
AnnaBridge	172:65be27845400	997	/** @defgroup RCCEx_SDMMC_Clock_Source RCCEx SDMMC Clock Source
AnnaBridge	172:65be27845400	998	* @{
AnnaBridge	172:65be27845400	999	*/
AnnaBridge	172:65be27845400	1000
AnnaBridge	172:65be27845400	1001	#define RCC_SDMMCCLKSOURCE_PLL (0x00000000U)
AnnaBridge	172:65be27845400	1002	#define RCC_SDMMCCLKSOURCE_PLL2 RCC_D1CCIPR_SDMMCSEL
AnnaBridge	172:65be27845400	1003
AnnaBridge	172:65be27845400	1004	/**
AnnaBridge	172:65be27845400	1005	* @}
AnnaBridge	172:65be27845400	1006	*/
AnnaBridge	172:65be27845400	1007
AnnaBridge	172:65be27845400	1008
AnnaBridge	172:65be27845400	1009	/** @defgroup RCCEx_ADC_Clock_Source RCCEx ADC Clock Source
AnnaBridge	172:65be27845400	1010	* @{
AnnaBridge	172:65be27845400	1011	*/
AnnaBridge	172:65be27845400	1012	#define RCC_ADCCLKSOURCE_PLL2 (0x00000000U)
AnnaBridge	172:65be27845400	1013	#define RCC_ADCCLKSOURCE_PLL3 RCC_D3CCIPR_ADCSEL_0
AnnaBridge	172:65be27845400	1014	#define RCC_ADCCLKSOURCE_CLKP RCC_D3CCIPR_ADCSEL_1
AnnaBridge	172:65be27845400	1015
AnnaBridge	172:65be27845400	1016	/**
AnnaBridge	172:65be27845400	1017	* @}
AnnaBridge	172:65be27845400	1018	*/
AnnaBridge	172:65be27845400	1019
AnnaBridge	172:65be27845400	1020
AnnaBridge	172:65be27845400	1021
AnnaBridge	172:65be27845400	1022
AnnaBridge	172:65be27845400	1023
AnnaBridge	172:65be27845400	1024	/** @defgroup RCCEx_SWPMI1_Clock_Source RCCEx SWPMI1 Clock Source
AnnaBridge	172:65be27845400	1025	* @{
AnnaBridge	172:65be27845400	1026	*/
AnnaBridge	172:65be27845400	1027	#define RCC_SWPMI1CLKSOURCE_D2PCLK1 (0x00000000U)
AnnaBridge	172:65be27845400	1028	#define RCC_SWPMI1CLKSOURCE_HSI RCC_D2CCIP1R_SWPSEL
AnnaBridge	172:65be27845400	1029
AnnaBridge	172:65be27845400	1030	/**
AnnaBridge	172:65be27845400	1031	* @}
AnnaBridge	172:65be27845400	1032	*/
AnnaBridge	172:65be27845400	1033
AnnaBridge	172:65be27845400	1034	/** @defgroup RCCEx_DFSDM1_Clock_Source RCCEx DFSDM1 Clock Source
AnnaBridge	172:65be27845400	1035	* @{
AnnaBridge	172:65be27845400	1036	*/
AnnaBridge	172:65be27845400	1037	#define RCC_DFSDM1CLKSOURCE_D2PCLK1 (0x00000000U)
AnnaBridge	172:65be27845400	1038	#define RCC_DFSDM1CLKSOURCE_SYS RCC_D2CCIP1R_DFSDM1SEL
AnnaBridge	172:65be27845400	1039
AnnaBridge	172:65be27845400	1040
AnnaBridge	172:65be27845400	1041	/**
AnnaBridge	172:65be27845400	1042	* @}
AnnaBridge	172:65be27845400	1043	*/
AnnaBridge	172:65be27845400	1044
AnnaBridge	172:65be27845400	1045	/** @defgroup RCCEx_SPDIFRX_Clock_Source RCCEx SPDIFRX Clock Source
AnnaBridge	172:65be27845400	1046	* @{
AnnaBridge	172:65be27845400	1047	*/
AnnaBridge	172:65be27845400	1048	#define RCC_SPDIFRXCLKSOURCE_PLL (0x00000000U)
AnnaBridge	172:65be27845400	1049	#define RCC_SPDIFRXCLKSOURCE_PLL2 RCC_D2CCIP1R_SPDIFSEL_0
AnnaBridge	172:65be27845400	1050	#define RCC_SPDIFRXCLKSOURCE_PLL3 RCC_D2CCIP1R_SPDIFSEL_1
AnnaBridge	172:65be27845400	1051	#define RCC_SPDIFRXCLKSOURCE_HSI RCC_D2CCIP1R_SPDIFSEL
AnnaBridge	172:65be27845400	1052
AnnaBridge	172:65be27845400	1053	/**
AnnaBridge	172:65be27845400	1054	* @}
AnnaBridge	172:65be27845400	1055	*/
AnnaBridge	172:65be27845400	1056
AnnaBridge	172:65be27845400	1057	/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
AnnaBridge	172:65be27845400	1058	* @{
AnnaBridge	172:65be27845400	1059	*/
AnnaBridge	172:65be27845400	1060	#define RCC_CECCLKSOURCE_LSE (0x00000000U)
AnnaBridge	172:65be27845400	1061	#define RCC_CECCLKSOURCE_LSI RCC_D2CCIP2R_CECSEL_0
AnnaBridge	172:65be27845400	1062	#define RCC_CECCLKSOURCE_CSI RCC_D2CCIP2R_CECSEL_1
AnnaBridge	172:65be27845400	1063
AnnaBridge	172:65be27845400	1064	/**
AnnaBridge	172:65be27845400	1065	* @}
AnnaBridge	172:65be27845400	1066	*/
AnnaBridge	172:65be27845400	1067
AnnaBridge	172:65be27845400	1068
AnnaBridge	172:65be27845400	1069	/** @defgroup RCCEx_CLKP_Clock_Source RCCEx CLKP Clock Source
AnnaBridge	172:65be27845400	1070	* @{
AnnaBridge	172:65be27845400	1071	*/
AnnaBridge	172:65be27845400	1072	#define RCC_CLKPSOURCE_HSI (0x00000000U)
AnnaBridge	172:65be27845400	1073	#define RCC_CLKPSOURCE_CSI RCC_D1CCIPR_CKPERSEL_0
AnnaBridge	172:65be27845400	1074	#define RCC_CLKPSOURCE_HSE RCC_D1CCIPR_CKPERSEL_1
AnnaBridge	172:65be27845400	1075
AnnaBridge	172:65be27845400	1076	/**
AnnaBridge	172:65be27845400	1077	* @}
AnnaBridge	172:65be27845400	1078	*/
AnnaBridge	172:65be27845400	1079
AnnaBridge	172:65be27845400	1080	/** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection
AnnaBridge	172:65be27845400	1081	* @{
AnnaBridge	172:65be27845400	1082	*/
AnnaBridge	172:65be27845400	1083	#define RCC_TIMPRES_DESACTIVATED (0x00000000U)
AnnaBridge	172:65be27845400	1084	#define RCC_TIMPRES_ACTIVATED RCC_CFGR_TIMPRE
AnnaBridge	172:65be27845400	1085
AnnaBridge	172:65be27845400	1086	/**
AnnaBridge	172:65be27845400	1087	* @}
AnnaBridge	172:65be27845400	1088	*/
AnnaBridge	172:65be27845400	1089
AnnaBridge	172:65be27845400	1090
AnnaBridge	172:65be27845400	1091	/** @defgroup RCCEx_RCC_WWDGx RCCEx RCC WWDGx
AnnaBridge	172:65be27845400	1092	* @{
AnnaBridge	172:65be27845400	1093	*/
AnnaBridge	172:65be27845400	1094	#define RCC_WWDG1 RCC_GCR_WW1RSC
AnnaBridge	172:65be27845400	1095
AnnaBridge	172:65be27845400	1096	/**
AnnaBridge	172:65be27845400	1097	* @}
AnnaBridge	172:65be27845400	1098	*/
AnnaBridge	172:65be27845400	1099
AnnaBridge	172:65be27845400	1100	/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
AnnaBridge	172:65be27845400	1101	* @{
AnnaBridge	172:65be27845400	1102	*/
AnnaBridge	172:65be27845400	1103	#define RCC_CRS_NONE (0x00000000U)
AnnaBridge	172:65be27845400	1104	#define RCC_CRS_TIMEOUT (0x00000001U)
AnnaBridge	172:65be27845400	1105	#define RCC_CRS_SYNCOK (0x00000002U)
AnnaBridge	172:65be27845400	1106	#define RCC_CRS_SYNCWARN (0x00000004U)
AnnaBridge	172:65be27845400	1107	#define RCC_CRS_SYNCERR (0x00000008U)
AnnaBridge	172:65be27845400	1108	#define RCC_CRS_SYNCMISS (0x00000010U)
AnnaBridge	172:65be27845400	1109	#define RCC_CRS_TRIMOVF (0x00000020U)
AnnaBridge	172:65be27845400	1110	/**
AnnaBridge	172:65be27845400	1111	* @}
AnnaBridge	172:65be27845400	1112	*/
AnnaBridge	172:65be27845400	1113
AnnaBridge	172:65be27845400	1114	/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
AnnaBridge	172:65be27845400	1115	* @{
AnnaBridge	172:65be27845400	1116	*/
AnnaBridge	172:65be27845400	1117	#define RCC_CRS_SYNC_SOURCE_USB2 (0x00000000U) /!< Synchro Signal source USB2 SOF /
AnnaBridge	172:65be27845400	1118	#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /!< Synchro Signal source LSE /
AnnaBridge	172:65be27845400	1119	#define RCC_CRS_SYNC_SOURCE_USB1 CRS_CFGR_SYNCSRC_1 /!< Synchro Signal source USB1 SOF (default) /
AnnaBridge	172:65be27845400	1120
AnnaBridge	172:65be27845400	1121
AnnaBridge	172:65be27845400	1122
AnnaBridge	172:65be27845400	1123	/**
AnnaBridge	172:65be27845400	1124	* @}
AnnaBridge	172:65be27845400	1125	*/
AnnaBridge	172:65be27845400	1126
AnnaBridge	172:65be27845400	1127	/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
AnnaBridge	172:65be27845400	1128	* @{
AnnaBridge	172:65be27845400	1129	*/
AnnaBridge	172:65be27845400	1130	#define RCC_CRS_SYNC_DIV1 (0x00000000U) /!< Synchro Signal not divided (default) /
AnnaBridge	172:65be27845400	1131	#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /!< Synchro Signal divided by 2 /
AnnaBridge	172:65be27845400	1132	#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /!< Synchro Signal divided by 4 /
AnnaBridge	172:65be27845400	1133	#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 8 /
AnnaBridge	172:65be27845400	1134	#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /!< Synchro Signal divided by 16 /
AnnaBridge	172:65be27845400	1135	#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 32 /
AnnaBridge	172:65be27845400	1136	#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_1) /!< Synchro Signal divided by 64 /
AnnaBridge	172:65be27845400	1137	#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /!< Synchro Signal divided by 128 /
AnnaBridge	172:65be27845400	1138	/**
AnnaBridge	172:65be27845400	1139	* @}
AnnaBridge	172:65be27845400	1140	*/
AnnaBridge	172:65be27845400	1141
AnnaBridge	172:65be27845400	1142	/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
AnnaBridge	172:65be27845400	1143	* @{
AnnaBridge	172:65be27845400	1144	*/
AnnaBridge	172:65be27845400	1145	#define RCC_CRS_SYNC_POLARITY_RISING (0x00000000U) /!< Synchro Active on rising edge (default) /
AnnaBridge	172:65be27845400	1146	#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /!< Synchro Active on falling edge /
AnnaBridge	172:65be27845400	1147	/**
AnnaBridge	172:65be27845400	1148	* @}
AnnaBridge	172:65be27845400	1149	*/
AnnaBridge	172:65be27845400	1150
AnnaBridge	172:65be27845400	1151	/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
AnnaBridge	172:65be27845400	1152	* @{
AnnaBridge	172:65be27845400	1153	*/
AnnaBridge	172:65be27845400	1154	#define RCC_CRS_RELOADVALUE_DEFAULT (0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds
AnnaBridge	172:65be27845400	1155	to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
AnnaBridge	172:65be27845400	1156	/**
AnnaBridge	172:65be27845400	1157	* @}
AnnaBridge	172:65be27845400	1158	*/
AnnaBridge	172:65be27845400	1159
AnnaBridge	172:65be27845400	1160	/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
AnnaBridge	172:65be27845400	1161	* @{
AnnaBridge	172:65be27845400	1162	*/
AnnaBridge	172:65be27845400	1163	#define RCC_CRS_ERRORLIMIT_DEFAULT (0x00000022U) /!< Default Frequency error limit /
AnnaBridge	172:65be27845400	1164	/**
AnnaBridge	172:65be27845400	1165	* @}
AnnaBridge	172:65be27845400	1166	*/
AnnaBridge	172:65be27845400	1167
AnnaBridge	172:65be27845400	1168	/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
AnnaBridge	172:65be27845400	1169	* @{
AnnaBridge	172:65be27845400	1170	*/
AnnaBridge	172:65be27845400	1171	#define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
AnnaBridge	172:65be27845400	1172	The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
AnnaBridge	172:65be27845400	1173	corresponds to a higher output frequency */
AnnaBridge	172:65be27845400	1174	/**
AnnaBridge	172:65be27845400	1175	* @}
AnnaBridge	172:65be27845400	1176	*/
AnnaBridge	172:65be27845400	1177
AnnaBridge	172:65be27845400	1178	/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
AnnaBridge	172:65be27845400	1179	* @{
AnnaBridge	172:65be27845400	1180	*/
AnnaBridge	172:65be27845400	1181	#define RCC_CRS_FREQERRORDIR_UP (0x00000000U) /!< Upcounting direction, the actual frequency is above the target /
AnnaBridge	172:65be27845400	1182	#define RCC_CRS_FREQERRORDIR_DOWN (CRS_ISR_FEDIR) /!< Downcounting direction, the actual frequency is below the target /
AnnaBridge	172:65be27845400	1183	/**
AnnaBridge	172:65be27845400	1184	* @}
AnnaBridge	172:65be27845400	1185	*/
AnnaBridge	172:65be27845400	1186
AnnaBridge	172:65be27845400	1187	/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
AnnaBridge	172:65be27845400	1188	* @{
AnnaBridge	172:65be27845400	1189	*/
AnnaBridge	172:65be27845400	1190	#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /!< SYNC event OK /
AnnaBridge	172:65be27845400	1191	#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /!< SYNC warning /
AnnaBridge	172:65be27845400	1192	#define RCC_CRS_IT_ERR CRS_CR_ERRIE /!< Error /
AnnaBridge	172:65be27845400	1193	#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /!< Expected SYNC /
AnnaBridge	172:65be27845400	1194	#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /!< SYNC error /
AnnaBridge	172:65be27845400	1195	#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /!< SYNC missed /
AnnaBridge	172:65be27845400	1196	#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /!< Trimming overflow or underflow /
AnnaBridge	172:65be27845400	1197
AnnaBridge	172:65be27845400	1198	/**
AnnaBridge	172:65be27845400	1199	* @}
AnnaBridge	172:65be27845400	1200	*/
AnnaBridge	172:65be27845400	1201
AnnaBridge	172:65be27845400	1202	/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
AnnaBridge	172:65be27845400	1203	* @{
AnnaBridge	172:65be27845400	1204	*/
AnnaBridge	172:65be27845400	1205	#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /!< SYNC event OK flag /
AnnaBridge	172:65be27845400	1206	#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /!< SYNC warning flag /
AnnaBridge	172:65be27845400	1207	#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /!< Error flag /
AnnaBridge	172:65be27845400	1208	#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /!< Expected SYNC flag /
AnnaBridge	172:65be27845400	1209	#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
AnnaBridge	172:65be27845400	1210	#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
AnnaBridge	172:65be27845400	1211	#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
AnnaBridge	172:65be27845400	1212
AnnaBridge	172:65be27845400	1213	/**
AnnaBridge	172:65be27845400	1214	* @}
AnnaBridge	172:65be27845400	1215	*/
AnnaBridge	172:65be27845400	1216
AnnaBridge	172:65be27845400	1217	/**
AnnaBridge	172:65be27845400	1218	* @}
AnnaBridge	172:65be27845400	1219	*/
AnnaBridge	172:65be27845400	1220
AnnaBridge	172:65be27845400	1221
AnnaBridge	172:65be27845400	1222
AnnaBridge	172:65be27845400	1223	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	1224	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
AnnaBridge	172:65be27845400	1225	* @{
AnnaBridge	172:65be27845400	1226	*/
AnnaBridge	172:65be27845400	1227
AnnaBridge	172:65be27845400	1228	/** @brief Macros to enable or disable PLL2.
AnnaBridge	172:65be27845400	1229	* @note After enabling PLL2, the application software should wait on
AnnaBridge	172:65be27845400	1230	* PLL2RDY flag to be set indicating that PLL2 clock is stable and can
AnnaBridge	172:65be27845400	1231	* be used as kernel clock source.
AnnaBridge	172:65be27845400	1232	* @note PLL2 is disabled by hardware when entering STOP and STANDBY modes.
AnnaBridge	172:65be27845400	1233	*/
AnnaBridge	172:65be27845400	1234	#define __HAL_RCC_PLL2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL2ON)
AnnaBridge	172:65be27845400	1235	#define __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON)
AnnaBridge	172:65be27845400	1236
AnnaBridge	172:65be27845400	1237	/**
AnnaBridge	172:65be27845400	1238	* @brief Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK)
AnnaBridge	172:65be27845400	1239	* @note Enabling/disabling those Clocks can be done only when the PLL2 is disabled,
AnnaBridge	172:65be27845400	1240	* This is mainly used to save Power.
AnnaBridge	172:65be27845400	1241	* @param __RCC_PLL2ClockOut__: Specifies the PLL2 clock to be outputted
AnnaBridge	172:65be27845400	1242	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1243	* @arg RCC_PLL2_DIVP: This clock is used to generate system clock (up to 400MHZ)
AnnaBridge	172:65be27845400	1244	* @arg RCC_PLL2_DIVQ: This clock is used to generate peripherals clock (up to 400MHZ)
AnnaBridge	172:65be27845400	1245	* @arg RCC_PLL2_DIVR: This clock is used to generate peripherals clock (up to 400MHZ)
AnnaBridge	172:65be27845400	1246	* @retval None
AnnaBridge	172:65be27845400	1247	*/
AnnaBridge	172:65be27845400	1248	#define __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
AnnaBridge	172:65be27845400	1249
AnnaBridge	172:65be27845400	1250	#define __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
AnnaBridge	172:65be27845400	1251
AnnaBridge	172:65be27845400	1252	/**
AnnaBridge	172:65be27845400	1253	* @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO
AnnaBridge	172:65be27845400	1254	* @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL2
AnnaBridge	172:65be27845400	1255	* @retval None
AnnaBridge	172:65be27845400	1256	*/
AnnaBridge	172:65be27845400	1257	#define __HAL_RCC_PLL2FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
AnnaBridge	172:65be27845400	1258
AnnaBridge	172:65be27845400	1259	#define __HAL_RCC_PLL2FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
AnnaBridge	172:65be27845400	1260
AnnaBridge	172:65be27845400	1261	/**
AnnaBridge	172:65be27845400	1262	* @brief Macro to configures the PLL2 multiplication and division factors.
AnnaBridge	172:65be27845400	1263	* @note This function must be used only when PLL2 is disabled.
AnnaBridge	172:65be27845400	1264	*
AnnaBridge	172:65be27845400	1265	* @param __PLL2M__: specifies the division factor for PLL2 VCO input clock
AnnaBridge	172:65be27845400	1266	* This parameter must be a number between 1 and 63.
AnnaBridge	172:65be27845400	1267	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
AnnaBridge	172:65be27845400	1268	* frequency ranges from 1 to 16 MHz.
AnnaBridge	172:65be27845400	1269	*
AnnaBridge	172:65be27845400	1270	* @param __PLL2N__: specifies the multiplication factor for PLL2 VCO output clock
AnnaBridge	172:65be27845400	1271	* This parameter must be a number between 4 and 512.
AnnaBridge	172:65be27845400	1272	* @note You have to set the PLL2N parameter correctly to ensure that the VCO
AnnaBridge	172:65be27845400	1273	* output frequency is between 150 and 420 MHz (when in medium VCO range) or
AnnaBridge	172:65be27845400	1274	* between 192 and 836 MHZ (when in wide VCO range)
AnnaBridge	172:65be27845400	1275	*
AnnaBridge	172:65be27845400	1276	* @param __PLL2P__: specifies the division factor for peripheral kernel clocks
AnnaBridge	172:65be27845400	1277	* This parameter must be a number between 2 and 128 (where odd numbers not allowed)
AnnaBridge	172:65be27845400	1278	*
AnnaBridge	172:65be27845400	1279	* @param __PLL2Q__: specifies the division factor for peripheral kernel clocks
AnnaBridge	172:65be27845400	1280	* This parameter must be a number between 1 and 128
AnnaBridge	172:65be27845400	1281	*
AnnaBridge	172:65be27845400	1282	* @param __PLL2R__: specifies the division factor for peripheral kernel clocks
AnnaBridge	172:65be27845400	1283	* This parameter must be a number between 1 and 128
AnnaBridge	172:65be27845400	1284	*
AnnaBridge	172:65be27845400	1285	* @retval None
AnnaBridge	172:65be27845400	1286	*/
AnnaBridge	172:65be27845400	1287
AnnaBridge	172:65be27845400	1288
AnnaBridge	172:65be27845400	1289	#define __HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__,__PLL2R__ ) \
AnnaBridge	172:65be27845400	1290	do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM2) , ( (__PLL2M__) <<12U)); \
AnnaBridge	172:65be27845400	1291	WRITE_REG (RCC->PLL2DIVR , ( (((__PLL2N__) - 1U ) & RCC_PLL2DIVR_N2) \| ((((__PLL2P__) -1U ) << 9U) & RCC_PLL2DIVR_P2) \| \
AnnaBridge	172:65be27845400	1292	((((__PLL2Q__) -1U) << 16U) & RCC_PLL2DIVR_Q2) \| ((((__PLL2R__)- 1U) << 24U) & RCC_PLL2DIVR_R2))); \
AnnaBridge	172:65be27845400	1293	} while(0)
AnnaBridge	172:65be27845400	1294	/**
AnnaBridge	172:65be27845400	1295	* @brief Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor
AnnaBridge	172:65be27845400	1296	*
AnnaBridge	172:65be27845400	1297	* @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO
AnnaBridge	172:65be27845400	1298	*
AnnaBridge	172:65be27845400	1299	* @param __RCC_PLL2FRACN__: Specifies Fractional Part Of The Multiplication factor for PLL2 VCO
AnnaBridge	172:65be27845400	1300	* It should be a value between 0 and 8191
AnnaBridge	172:65be27845400	1301	* @note Warning: the software has to set correctly these bits to insure that the VCO
AnnaBridge	172:65be27845400	1302	* output frequency is between its valid frequency range, which is:
AnnaBridge	172:65be27845400	1303	* 192 to 836 MHz if PLL2VCOSEL = 0
AnnaBridge	172:65be27845400	1304	* 150 to 420 MHz if PLL2VCOSEL = 1.
AnnaBridge	172:65be27845400	1305	*
AnnaBridge	172:65be27845400	1306	*
AnnaBridge	172:65be27845400	1307	* @retval None
AnnaBridge	172:65be27845400	1308	*/
AnnaBridge	172:65be27845400	1309	#define __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__) MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,(uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos)
AnnaBridge	172:65be27845400	1310
AnnaBridge	172:65be27845400	1311	/** @brief Macro to select the PLL2 reference frequency range.
AnnaBridge	172:65be27845400	1312	* @param __RCC_PLL2VCIRange__: specifies the PLL2 input frequency range
AnnaBridge	172:65be27845400	1313	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1314	* @arg RCC_PLL2VCIRANGE_0: Range frequency is between 1 and 2 MHz
AnnaBridge	172:65be27845400	1315	* @arg RCC_PLL2VCIRANGE_1: Range frequency is between 2 and 4 MHz
AnnaBridge	172:65be27845400	1316	* @arg RCC_PLL2VCIRANGE_2: Range frequency is between 4 and 8 MHz
AnnaBridge	172:65be27845400	1317	* @arg RCC_PLL2VCIRANGE_3: Range frequency is between 8 and 16 MHz
AnnaBridge	172:65be27845400	1318	* @retval None
AnnaBridge	172:65be27845400	1319	*/
AnnaBridge	172:65be27845400	1320	#define __HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__) \
AnnaBridge	172:65be27845400	1321	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__))
AnnaBridge	172:65be27845400	1322
AnnaBridge	172:65be27845400	1323
AnnaBridge	172:65be27845400	1324	/** @brief Macro to select the PLL2 reference frequency range.
AnnaBridge	172:65be27845400	1325	* @param __RCC_PLL2VCORange__: Specifies the PLL2 input frequency range
AnnaBridge	172:65be27845400	1326	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1327	* @arg RCC_PLL2VCOWIDE: Range frequency is between 192 and 836 MHz
AnnaBridge	172:65be27845400	1328	* @arg RCC_PLL2VCOMEDIUM: Range frequency is between 150 and 420 MHz
AnnaBridge	172:65be27845400	1329	* @retval None
AnnaBridge	172:65be27845400	1330	*/
AnnaBridge	172:65be27845400	1331	#define __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) \
AnnaBridge	172:65be27845400	1332	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__))
AnnaBridge	172:65be27845400	1333
AnnaBridge	172:65be27845400	1334	/** @brief Macros to enable or disable the main PLL3.
AnnaBridge	172:65be27845400	1335	* @note After enabling PLL3, the application software should wait on
AnnaBridge	172:65be27845400	1336	* PLL3RDY flag to be set indicating that PLL3 clock is stable and can
AnnaBridge	172:65be27845400	1337	* be used as kernel clock source.
AnnaBridge	172:65be27845400	1338	* @note PLL3 is disabled by hardware when entering STOP and STANDBY modes.
AnnaBridge	172:65be27845400	1339	*/
AnnaBridge	172:65be27845400	1340	#define __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL3ON)
AnnaBridge	172:65be27845400	1341	#define __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON)
AnnaBridge	172:65be27845400	1342
AnnaBridge	172:65be27845400	1343	/**
AnnaBridge	172:65be27845400	1344	* @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO
AnnaBridge	172:65be27845400	1345	* @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL3
AnnaBridge	172:65be27845400	1346	* @retval None
AnnaBridge	172:65be27845400	1347	*/
AnnaBridge	172:65be27845400	1348	#define __HAL_RCC_PLL3FRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
AnnaBridge	172:65be27845400	1349
AnnaBridge	172:65be27845400	1350	#define __HAL_RCC_PLL3FRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
AnnaBridge	172:65be27845400	1351
AnnaBridge	172:65be27845400	1352	/**
AnnaBridge	172:65be27845400	1353	* @brief Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK)
AnnaBridge	172:65be27845400	1354	* @note Enabling/disabling those Clocks can be done only when the PLL3 is disabled,
AnnaBridge	172:65be27845400	1355	* This is mainly used to save Power.
AnnaBridge	172:65be27845400	1356	* @param __RCC_PLL3ClockOut__: specifies the PLL3 clock to be outputted
AnnaBridge	172:65be27845400	1357	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1358	* @arg RCC_PLL3_DIVP: This clock is used to generate system clock (up to 400MHZ)
AnnaBridge	172:65be27845400	1359	* @arg RCC_PLL3_DIVQ: This clock is used to generate peripherals clock (up to 400MHZ)
AnnaBridge	172:65be27845400	1360	* @arg RCC_PLL3_DIVR: This clock is used to generate peripherals clock (up to 400MHZ)
AnnaBridge	172:65be27845400	1361	* @retval None
AnnaBridge	172:65be27845400	1362	*/
AnnaBridge	172:65be27845400	1363	#define __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
AnnaBridge	172:65be27845400	1364
AnnaBridge	172:65be27845400	1365	#define __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
AnnaBridge	172:65be27845400	1366
AnnaBridge	172:65be27845400	1367	/**
AnnaBridge	172:65be27845400	1368	* @brief Macro to configures the PLL3 multiplication and division factors.
AnnaBridge	172:65be27845400	1369	* @note This function must be used only when PLL3 is disabled.
AnnaBridge	172:65be27845400	1370	*
AnnaBridge	172:65be27845400	1371	* @param __PLL3M__: specifies the division factor for PLL3 VCO input clock
AnnaBridge	172:65be27845400	1372	* This parameter must be a number between 1 and 63.
AnnaBridge	172:65be27845400	1373	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
AnnaBridge	172:65be27845400	1374	* frequency ranges from 1 to 16 MHz.
AnnaBridge	172:65be27845400	1375	*
AnnaBridge	172:65be27845400	1376	* @param __PLL3N__: specifies the multiplication factor for PLL3 VCO output clock
AnnaBridge	172:65be27845400	1377	* This parameter must be a number between 4 and 512.
AnnaBridge	172:65be27845400	1378	* @note You have to set the PLL3N parameter correctly to ensure that the VCO
AnnaBridge	172:65be27845400	1379	* output frequency is between 150 and 420 MHz (when in medium VCO range) or
AnnaBridge	172:65be27845400	1380	* between 192 and 836 MHZ (when in wide VCO range)
AnnaBridge	172:65be27845400	1381	*
AnnaBridge	172:65be27845400	1382	* @param __PLL3P__: specifies the division factor for peripheral kernel clocks
AnnaBridge	172:65be27845400	1383	* This parameter must be a number between 2 and 128 (where odd numbers not allowed)
AnnaBridge	172:65be27845400	1384	*
AnnaBridge	172:65be27845400	1385	* @param __PLL3Q__: specifies the division factor for peripheral kernel clocks
AnnaBridge	172:65be27845400	1386	* This parameter must be a number between 1 and 128
AnnaBridge	172:65be27845400	1387	*
AnnaBridge	172:65be27845400	1388	* @param __PLL3R__: specifies the division factor for peripheral kernel clocks
AnnaBridge	172:65be27845400	1389	* This parameter must be a number between 1 and 128
AnnaBridge	172:65be27845400	1390	*
AnnaBridge	172:65be27845400	1391	* @retval None
AnnaBridge	172:65be27845400	1392	*/
AnnaBridge	172:65be27845400	1393
AnnaBridge	172:65be27845400	1394	#define __HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__,__PLL3R__ ) \
AnnaBridge	172:65be27845400	1395	do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM3) , ( (__PLL3M__) <<20U)); \
AnnaBridge	172:65be27845400	1396	WRITE_REG (RCC->PLL3DIVR , ( (((__PLL3N__) - 1U ) & RCC_PLL3DIVR_N3) \| ((((__PLL3P__) -1U ) << 9U) & RCC_PLL3DIVR_P3) \| \
AnnaBridge	172:65be27845400	1397	((((__PLL3Q__) -1U) << 16U) & RCC_PLL3DIVR_Q3) \| ((((__PLL3R__) - 1U) << 24U) & RCC_PLL3DIVR_R3))); \
AnnaBridge	172:65be27845400	1398	} while(0)
AnnaBridge	172:65be27845400	1399
AnnaBridge	172:65be27845400	1400
AnnaBridge	172:65be27845400	1401
AnnaBridge	172:65be27845400	1402	/**
AnnaBridge	172:65be27845400	1403	* @brief Macro to configures PLL3 clock Fractional Part of The Multiplication Factor
AnnaBridge	172:65be27845400	1404	*
AnnaBridge	172:65be27845400	1405	* @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO
AnnaBridge	172:65be27845400	1406	*
AnnaBridge	172:65be27845400	1407	* @param __RCC_PLL3FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL3 VCO
AnnaBridge	172:65be27845400	1408	* It should be a value between 0 and 8191
AnnaBridge	172:65be27845400	1409	* @note Warning: the software has to set correctly these bits to insure that the VCO
AnnaBridge	172:65be27845400	1410	* output frequency is between its valid frequency range, which is:
AnnaBridge	172:65be27845400	1411	* 192 to 836 MHz if PLL3VCOSEL = 0
AnnaBridge	172:65be27845400	1412	* 150 to 420 MHz if PLL3VCOSEL = 1.
AnnaBridge	172:65be27845400	1413	*
AnnaBridge	172:65be27845400	1414	*
AnnaBridge	172:65be27845400	1415	* @retval None
AnnaBridge	172:65be27845400	1416	*/
AnnaBridge	172:65be27845400	1417	#define __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos)
AnnaBridge	172:65be27845400	1418
AnnaBridge	172:65be27845400	1419	/** @brief Macro to select the PLL3 reference frequency range.
AnnaBridge	172:65be27845400	1420	* @param __RCC_PLL3VCIRange__: specifies the PLL1 input frequency range
AnnaBridge	172:65be27845400	1421	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1422	* @arg RCC_PLL3VCIRANGE_0: Range frequency is between 1 and 2 MHz
AnnaBridge	172:65be27845400	1423	* @arg RCC_PLL3VCIRANGE_1: Range frequency is between 2 and 4 MHz
AnnaBridge	172:65be27845400	1424	* @arg RCC_PLL3VCIRANGE_2: Range frequency is between 4 and 8 MHz
AnnaBridge	172:65be27845400	1425	* @arg RCC_PLL3VCIRANGE_3: Range frequency is between 8 and 16 MHz
AnnaBridge	172:65be27845400	1426	* @retval None
AnnaBridge	172:65be27845400	1427	*/
AnnaBridge	172:65be27845400	1428	#define __HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__) \
AnnaBridge	172:65be27845400	1429	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__))
AnnaBridge	172:65be27845400	1430
AnnaBridge	172:65be27845400	1431
AnnaBridge	172:65be27845400	1432	/** @brief Macro to select the PLL3 reference frequency range.
AnnaBridge	172:65be27845400	1433	* @param __RCC_PLL3VCORange__: specifies the PLL1 input frequency range
AnnaBridge	172:65be27845400	1434	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1435	* @arg RCC_PLL3VCOWIDE: Range frequency is between 192 and 836 MHz
AnnaBridge	172:65be27845400	1436	* @arg RCC_PLL3VCOMEDIUM: Range frequency is between 150 and 420 MHz
AnnaBridge	172:65be27845400	1437	* @retval None
AnnaBridge	172:65be27845400	1438	*/
AnnaBridge	172:65be27845400	1439	#define __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) \
AnnaBridge	172:65be27845400	1440	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__))
AnnaBridge	172:65be27845400	1441	/**
AnnaBridge	172:65be27845400	1442	* @brief Macro to Configure the SAI1 clock source.
AnnaBridge	172:65be27845400	1443	* @param __RCC_SAI1CLKSource__: defines the SAI1 clock source. This clock is derived
AnnaBridge	172:65be27845400	1444	* from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
AnnaBridge	172:65be27845400	1445	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1446	* @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL
AnnaBridge	172:65be27845400	1447	* @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2
AnnaBridge	172:65be27845400	1448	* @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3
AnnaBridge	172:65be27845400	1449	* @arg RCC_SAI1CLKSOURCE_OSC: SAI1 clock = OSC
AnnaBridge	172:65be27845400	1450	* @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock
AnnaBridge	172:65be27845400	1451	* @retval None
AnnaBridge	172:65be27845400	1452	*/
AnnaBridge	172:65be27845400	1453	#define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\
AnnaBridge	172:65be27845400	1454	MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))
AnnaBridge	172:65be27845400	1455
AnnaBridge	172:65be27845400	1456	/** @brief Macro to get the SAI1 clock source.
AnnaBridge	172:65be27845400	1457	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1458	* @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL
AnnaBridge	172:65be27845400	1459	* @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2
AnnaBridge	172:65be27845400	1460	* @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3
AnnaBridge	172:65be27845400	1461	* @arg RCC_SAI1CLKSOURCE_CLKP: SAI1 clock = CLKP
AnnaBridge	172:65be27845400	1462	* @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock
AnnaBridge	172:65be27845400	1463	*/
AnnaBridge	172:65be27845400	1464	#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL)))
AnnaBridge	172:65be27845400	1465
AnnaBridge	172:65be27845400	1466	/**
AnnaBridge	172:65be27845400	1467	* @brief Macro to Configure the SPDIFRX clock source.
AnnaBridge	172:65be27845400	1468	* @param __RCC_SPDIFCLKSource__: defines the SPDIFRX clock source. This clock is derived
AnnaBridge	172:65be27845400	1469	* from system PLL, PLL2, PLL3, or internal OSC clock
AnnaBridge	172:65be27845400	1470	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1471	* @arg RCC_SPDIFRXCLKSOURCE_PLL: SPDIFRX clock = PLL
AnnaBridge	172:65be27845400	1472	* @arg RCC_SPDIFRXCLKSOURCE_PLL2: SPDIFRX clock = PLL2
AnnaBridge	172:65be27845400	1473	* @arg RCC_SPDIFRXCLKSOURCE_PLL3: SPDIFRX clock = PLL3
AnnaBridge	172:65be27845400	1474	* @arg RCC_SPDIFRXCLKSOURCE_HSI: SPDIFRX clock = HSI
AnnaBridge	172:65be27845400	1475	* @retval None
AnnaBridge	172:65be27845400	1476	*/
AnnaBridge	172:65be27845400	1477	#define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\
AnnaBridge	172:65be27845400	1478	MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))
AnnaBridge	172:65be27845400	1479	/**
AnnaBridge	172:65be27845400	1480	* @brief Macro to get the SPDIFRX clock source.
AnnaBridge	172:65be27845400	1481	* @retval None
AnnaBridge	172:65be27845400	1482	*/
AnnaBridge	172:65be27845400	1483	#define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL)))
AnnaBridge	172:65be27845400	1484
AnnaBridge	172:65be27845400	1485	/**
AnnaBridge	172:65be27845400	1486	* @brief Macro to Configure the SAI2/3 clock source.
AnnaBridge	172:65be27845400	1487	* @param __RCC_SAI23CLKSource__: defines the SAI2/3 clock source. This clock is derived
AnnaBridge	172:65be27845400	1488	* from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
AnnaBridge	172:65be27845400	1489	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1490	* @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL
AnnaBridge	172:65be27845400	1491	* @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2
AnnaBridge	172:65be27845400	1492	* @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3
AnnaBridge	172:65be27845400	1493	* @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock = CLKP
AnnaBridge	172:65be27845400	1494	* @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock
AnnaBridge	172:65be27845400	1495	* @retval None
AnnaBridge	172:65be27845400	1496	*/
AnnaBridge	172:65be27845400	1497	#define __HAL_RCC_SAI23_CONFIG(__RCC_SAI23CLKSource__ )\
AnnaBridge	172:65be27845400	1498	MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI23CLKSource__))
AnnaBridge	172:65be27845400	1499
AnnaBridge	172:65be27845400	1500	/** @brief Macro to get the SAI2/3 clock source.
AnnaBridge	172:65be27845400	1501	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1502	* @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL
AnnaBridge	172:65be27845400	1503	* @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2
AnnaBridge	172:65be27845400	1504	* @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3
AnnaBridge	172:65be27845400	1505	* @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock = CLKP
AnnaBridge	172:65be27845400	1506	* @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock
AnnaBridge	172:65be27845400	1507	*/
AnnaBridge	172:65be27845400	1508	#define __HAL_RCC_GET_SAI23_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL)))
AnnaBridge	172:65be27845400	1509
AnnaBridge	172:65be27845400	1510	/**
AnnaBridge	172:65be27845400	1511	* @brief Macro to Configure the SAI2 clock source.
AnnaBridge	172:65be27845400	1512	* @param __RCC_SAI2CLKSource__: defines the SAI2 clock source. This clock is derived
AnnaBridge	172:65be27845400	1513	* from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
AnnaBridge	172:65be27845400	1514	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1515	* @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL
AnnaBridge	172:65be27845400	1516	* @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2
AnnaBridge	172:65be27845400	1517	* @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3
AnnaBridge	172:65be27845400	1518	* @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock = CLKP
AnnaBridge	172:65be27845400	1519	* @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock
AnnaBridge	172:65be27845400	1520	* @retval None
AnnaBridge	172:65be27845400	1521	*/
AnnaBridge	172:65be27845400	1522	#define __HAL_RCC_SAI2_CONFIG(__RCC_SAI2CLKSource__ )\
AnnaBridge	172:65be27845400	1523	MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI2CLKSource__))
AnnaBridge	172:65be27845400	1524
AnnaBridge	172:65be27845400	1525	/** @brief Macro to get the SAI2 clock source.
AnnaBridge	172:65be27845400	1526	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1527	* @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL
AnnaBridge	172:65be27845400	1528	* @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2
AnnaBridge	172:65be27845400	1529	* @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3
AnnaBridge	172:65be27845400	1530	* @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock = CLKP
AnnaBridge	172:65be27845400	1531	* @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock
AnnaBridge	172:65be27845400	1532	*/
AnnaBridge	172:65be27845400	1533	#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL)))
AnnaBridge	172:65be27845400	1534
AnnaBridge	172:65be27845400	1535	/**
AnnaBridge	172:65be27845400	1536	* @brief Macro to Configure the SAI3 clock source.
AnnaBridge	172:65be27845400	1537	* @param __RCC_SAI3CLKSource__: defines the SAI3 clock source. This clock is derived
AnnaBridge	172:65be27845400	1538	* from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
AnnaBridge	172:65be27845400	1539	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1540	* @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL
AnnaBridge	172:65be27845400	1541	* @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2
AnnaBridge	172:65be27845400	1542	* @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3
AnnaBridge	172:65be27845400	1543	* @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock = CLKP
AnnaBridge	172:65be27845400	1544	* @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock
AnnaBridge	172:65be27845400	1545	* @retval None
AnnaBridge	172:65be27845400	1546	*/
AnnaBridge	172:65be27845400	1547	#define __HAL_RCC_SAI3_CONFIG(__RCC_SAI3CLKSource__ )\
AnnaBridge	172:65be27845400	1548	MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI3CLKSource__))
AnnaBridge	172:65be27845400	1549
AnnaBridge	172:65be27845400	1550	/** @brief Macro to get the SAI3 clock source.
AnnaBridge	172:65be27845400	1551	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1552	* @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL
AnnaBridge	172:65be27845400	1553	* @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2
AnnaBridge	172:65be27845400	1554	* @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3
AnnaBridge	172:65be27845400	1555	* @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock = CLKP
AnnaBridge	172:65be27845400	1556	* @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock
AnnaBridge	172:65be27845400	1557	*/
AnnaBridge	172:65be27845400	1558	#define __HAL_RCC_GET_SAI3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL)))
AnnaBridge	172:65be27845400	1559
AnnaBridge	172:65be27845400	1560	/**
AnnaBridge	172:65be27845400	1561	* @brief Macro to Configure the SAI4A clock source.
AnnaBridge	172:65be27845400	1562	* @param __RCC_SAI4ACLKSource__: defines the SAI4A clock source. This clock is derived
AnnaBridge	172:65be27845400	1563	* from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
AnnaBridge	172:65be27845400	1564	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1565	* @arg RCC_SAI4ACLKSOURCE_PLL: SAI4A clock = PLL
AnnaBridge	172:65be27845400	1566	* @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4A clock = PLL2
AnnaBridge	172:65be27845400	1567	* @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4A clock = PLL3
AnnaBridge	172:65be27845400	1568	* @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4A clock = CLKP
AnnaBridge	172:65be27845400	1569	* @arg RCC_SAI4ACLKSOURCE_PIN: SAI4A clock = External Clock
AnnaBridge	172:65be27845400	1570	* @retval None
AnnaBridge	172:65be27845400	1571	*/
AnnaBridge	172:65be27845400	1572	#define __HAL_RCC_SAI4A_CONFIG(__RCC_SAI4ACLKSource__ )\
AnnaBridge	172:65be27845400	1573	MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL, (__RCC_SAI4ACLKSource__))
AnnaBridge	172:65be27845400	1574
AnnaBridge	172:65be27845400	1575	/** @brief Macro to get the SAI4A clock source.
AnnaBridge	172:65be27845400	1576	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1577	* @arg RCC_SAI4ACLKSOURCE_PLL: SAI4B clock = PLL
AnnaBridge	172:65be27845400	1578	* @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4B clock = PLL2
AnnaBridge	172:65be27845400	1579	* @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4B clock = PLL3
AnnaBridge	172:65be27845400	1580	* @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4B clock = CLKP
AnnaBridge	172:65be27845400	1581	* @arg RCC_SAI4ACLKSOURCE_PIN: SAI4B clock = External Clock
AnnaBridge	172:65be27845400	1582	*/
AnnaBridge	172:65be27845400	1583	#define __HAL_RCC_GET_SAI4A_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL)))
AnnaBridge	172:65be27845400	1584
AnnaBridge	172:65be27845400	1585	/**
AnnaBridge	172:65be27845400	1586	* @brief Macro to Configure the SAI4B clock source.
AnnaBridge	172:65be27845400	1587	* @param __RCC_SAI4BCLKSource__: defines the SAI4B clock source. This clock is derived
AnnaBridge	172:65be27845400	1588	* from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
AnnaBridge	172:65be27845400	1589	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1590	* @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL
AnnaBridge	172:65be27845400	1591	* @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2
AnnaBridge	172:65be27845400	1592	* @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3
AnnaBridge	172:65be27845400	1593	* @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock = CLKP
AnnaBridge	172:65be27845400	1594	* @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock
AnnaBridge	172:65be27845400	1595	* @retval None
AnnaBridge	172:65be27845400	1596	*/
AnnaBridge	172:65be27845400	1597	#define __HAL_RCC_SAI4B_CONFIG(__RCC_SAI4BCLKSource__ )\
AnnaBridge	172:65be27845400	1598	MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL, (__RCC_SAI4BCLKSource__))
AnnaBridge	172:65be27845400	1599
AnnaBridge	172:65be27845400	1600	/** @brief Macro to get the SAI4B clock source.
AnnaBridge	172:65be27845400	1601	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1602	* @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL
AnnaBridge	172:65be27845400	1603	* @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2
AnnaBridge	172:65be27845400	1604	* @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3
AnnaBridge	172:65be27845400	1605	* @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock = CLKP
AnnaBridge	172:65be27845400	1606	* @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock
AnnaBridge	172:65be27845400	1607	*/
AnnaBridge	172:65be27845400	1608	#define __HAL_RCC_GET_SAI4B_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL)))
AnnaBridge	172:65be27845400	1609
AnnaBridge	172:65be27845400	1610	/** @brief macro to configure the I2C1/2/3 clock (I2C123CLK).
AnnaBridge	172:65be27845400	1611	*
AnnaBridge	172:65be27845400	1612	* @param __I2C123CLKSource__: specifies the I2C1/2/3 clock source.
AnnaBridge	172:65be27845400	1613	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1614	* @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3 clock
AnnaBridge	172:65be27845400	1615	* @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3 clock
AnnaBridge	172:65be27845400	1616	* @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3 clock
AnnaBridge	172:65be27845400	1617	* @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3 clock
AnnaBridge	172:65be27845400	1618	*/
AnnaBridge	172:65be27845400	1619	#define __HAL_RCC_I2C123_CONFIG(__I2C123CLKSource__) \
AnnaBridge	172:65be27845400	1620	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C123CLKSource__))
AnnaBridge	172:65be27845400	1621
AnnaBridge	172:65be27845400	1622	/** @brief macro to get the I2C1/2/3 clock source.
AnnaBridge	172:65be27845400	1623	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1624	* @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3 clock
AnnaBridge	172:65be27845400	1625	* @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3 clock
AnnaBridge	172:65be27845400	1626	* @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3 clock
AnnaBridge	172:65be27845400	1627	* @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3 clock
AnnaBridge	172:65be27845400	1628	*/
AnnaBridge	172:65be27845400	1629	#define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))
AnnaBridge	172:65be27845400	1630
AnnaBridge	172:65be27845400	1631	/** @brief macro to configure the I2C1 clock (I2C1CLK).
AnnaBridge	172:65be27845400	1632	*
AnnaBridge	172:65be27845400	1633	* @param __I2C1CLKSource__: specifies the I2C1 clock source.
AnnaBridge	172:65be27845400	1634	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1635	* @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock
AnnaBridge	172:65be27845400	1636	* @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock
AnnaBridge	172:65be27845400	1637	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
AnnaBridge	172:65be27845400	1638	* @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock
AnnaBridge	172:65be27845400	1639	*/
AnnaBridge	172:65be27845400	1640	#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \
AnnaBridge	172:65be27845400	1641	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C1CLKSource__))
AnnaBridge	172:65be27845400	1642
AnnaBridge	172:65be27845400	1643	/** @brief macro to get the I2C1 clock source.
AnnaBridge	172:65be27845400	1644	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1645	* @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock
AnnaBridge	172:65be27845400	1646	* @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock
AnnaBridge	172:65be27845400	1647	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
AnnaBridge	172:65be27845400	1648	* @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock
AnnaBridge	172:65be27845400	1649	*/
AnnaBridge	172:65be27845400	1650	#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))
AnnaBridge	172:65be27845400	1651
AnnaBridge	172:65be27845400	1652	/** @brief macro to configure the I2C2 clock (I2C2CLK).
AnnaBridge	172:65be27845400	1653	*
AnnaBridge	172:65be27845400	1654	* @param __I2C2CLKSource__: specifies the I2C2 clock source.
AnnaBridge	172:65be27845400	1655	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1656	* @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock
AnnaBridge	172:65be27845400	1657	* @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock
AnnaBridge	172:65be27845400	1658	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
AnnaBridge	172:65be27845400	1659	* @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock
AnnaBridge	172:65be27845400	1660	*/
AnnaBridge	172:65be27845400	1661	#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
AnnaBridge	172:65be27845400	1662	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C2CLKSource__))
AnnaBridge	172:65be27845400	1663
AnnaBridge	172:65be27845400	1664	/** @brief macro to get the I2C2 clock source.
AnnaBridge	172:65be27845400	1665	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1666	* @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock
AnnaBridge	172:65be27845400	1667	* @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock
AnnaBridge	172:65be27845400	1668	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
AnnaBridge	172:65be27845400	1669	* @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock
AnnaBridge	172:65be27845400	1670	*/
AnnaBridge	172:65be27845400	1671	#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))
AnnaBridge	172:65be27845400	1672
AnnaBridge	172:65be27845400	1673	/** @brief macro to configure the I2C3 clock (I2C3CLK).
AnnaBridge	172:65be27845400	1674	*
AnnaBridge	172:65be27845400	1675	* @param __I2C3CLKSource__: specifies the I2C3 clock source.
AnnaBridge	172:65be27845400	1676	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1677	* @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock
AnnaBridge	172:65be27845400	1678	* @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock
AnnaBridge	172:65be27845400	1679	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
AnnaBridge	172:65be27845400	1680	* @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock
AnnaBridge	172:65be27845400	1681	*/
AnnaBridge	172:65be27845400	1682	#define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
AnnaBridge	172:65be27845400	1683	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C3CLKSource__))
AnnaBridge	172:65be27845400	1684
AnnaBridge	172:65be27845400	1685	/** @brief macro to get the I2C3 clock source.
AnnaBridge	172:65be27845400	1686	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1687	* @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock
AnnaBridge	172:65be27845400	1688	* @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock
AnnaBridge	172:65be27845400	1689	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
AnnaBridge	172:65be27845400	1690	* @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock
AnnaBridge	172:65be27845400	1691	*/
AnnaBridge	172:65be27845400	1692	#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))
AnnaBridge	172:65be27845400	1693
AnnaBridge	172:65be27845400	1694	/** @brief macro to configure the I2C4 clock (I2C4CLK).
AnnaBridge	172:65be27845400	1695	*
AnnaBridge	172:65be27845400	1696	* @param __I2C4CLKSource__: specifies the I2C4 clock source.
AnnaBridge	172:65be27845400	1697	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1698	* @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock
AnnaBridge	172:65be27845400	1699	* @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock
AnnaBridge	172:65be27845400	1700	* @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
AnnaBridge	172:65be27845400	1701	* @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock
AnnaBridge	172:65be27845400	1702	*/
AnnaBridge	172:65be27845400	1703	#define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \
AnnaBridge	172:65be27845400	1704	MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))
AnnaBridge	172:65be27845400	1705
AnnaBridge	172:65be27845400	1706	/** @brief macro to get the I2C4 clock source.
AnnaBridge	172:65be27845400	1707	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1708	* @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock
AnnaBridge	172:65be27845400	1709	* @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock
AnnaBridge	172:65be27845400	1710	* @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
AnnaBridge	172:65be27845400	1711	* @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock
AnnaBridge	172:65be27845400	1712	*/
AnnaBridge	172:65be27845400	1713	#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL)))
AnnaBridge	172:65be27845400	1714
AnnaBridge	172:65be27845400	1715	/** @brief macro to configure the USART1/6 clock (USART16CLK).
AnnaBridge	172:65be27845400	1716	*
AnnaBridge	172:65be27845400	1717	* @param __USART16CLKSource__: specifies the USART1/6 clock source.
AnnaBridge	172:65be27845400	1718	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1719	* @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6 clock
AnnaBridge	172:65be27845400	1720	* @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6 clock
AnnaBridge	172:65be27845400	1721	* @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6 clock
AnnaBridge	172:65be27845400	1722	* @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6 clock
AnnaBridge	172:65be27845400	1723	* @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6 clock
AnnaBridge	172:65be27845400	1724	* @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6 clock
AnnaBridge	172:65be27845400	1725	*/
AnnaBridge	172:65be27845400	1726	#define __HAL_RCC_USART16_CONFIG(__USART16CLKSource__) \
AnnaBridge	172:65be27845400	1727	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART16CLKSource__))
AnnaBridge	172:65be27845400	1728
AnnaBridge	172:65be27845400	1729	/** @brief macro to get the USART1/6 clock source.
AnnaBridge	172:65be27845400	1730	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1731	* @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6 clock
AnnaBridge	172:65be27845400	1732	* @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6 clock
AnnaBridge	172:65be27845400	1733	* @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6 clock
AnnaBridge	172:65be27845400	1734	* @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6 clock
AnnaBridge	172:65be27845400	1735	* @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6 clock
AnnaBridge	172:65be27845400	1736	* @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6 clock
AnnaBridge	172:65be27845400	1737	*/
AnnaBridge	172:65be27845400	1738	#define __HAL_RCC_GET_USART16_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL)))
AnnaBridge	172:65be27845400	1739
AnnaBridge	172:65be27845400	1740	/** @brief macro to configure the USART234578 clock (USART234578CLK).
AnnaBridge	172:65be27845400	1741	*
AnnaBridge	172:65be27845400	1742	* @param __USART234578CLKSource__: specifies the USART2/3/4/5/7/8 clock source.
AnnaBridge	172:65be27845400	1743	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1744	* @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock
AnnaBridge	172:65be27845400	1745	* @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock
AnnaBridge	172:65be27845400	1746	* @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock
AnnaBridge	172:65be27845400	1747	* @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock
AnnaBridge	172:65be27845400	1748	* @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock
AnnaBridge	172:65be27845400	1749	* @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock
AnnaBridge	172:65be27845400	1750	*/
AnnaBridge	172:65be27845400	1751	#define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \
AnnaBridge	172:65be27845400	1752	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART234578CLKSource__))
AnnaBridge	172:65be27845400	1753
AnnaBridge	172:65be27845400	1754	/** @brief macro to get the USART2/3/4/5/7/8 clock source.
AnnaBridge	172:65be27845400	1755	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1756	* @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock
AnnaBridge	172:65be27845400	1757	* @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock
AnnaBridge	172:65be27845400	1758	* @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock
AnnaBridge	172:65be27845400	1759	* @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock
AnnaBridge	172:65be27845400	1760	* @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock
AnnaBridge	172:65be27845400	1761	* @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock
AnnaBridge	172:65be27845400	1762	*/
AnnaBridge	172:65be27845400	1763	#define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
AnnaBridge	172:65be27845400	1764
AnnaBridge	172:65be27845400	1765	/** @brief macro to configure the USART1 clock (USART1CLK).
AnnaBridge	172:65be27845400	1766	*
AnnaBridge	172:65be27845400	1767	* @param __USART1CLKSource__: specifies the USART1 clock source.
AnnaBridge	172:65be27845400	1768	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1769	* @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock
AnnaBridge	172:65be27845400	1770	* @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock
AnnaBridge	172:65be27845400	1771	* @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock
AnnaBridge	172:65be27845400	1772	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
AnnaBridge	172:65be27845400	1773	* @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock
AnnaBridge	172:65be27845400	1774	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
AnnaBridge	172:65be27845400	1775	*/
AnnaBridge	172:65be27845400	1776	#define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \
AnnaBridge	172:65be27845400	1777	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART1CLKSource__))
AnnaBridge	172:65be27845400	1778
AnnaBridge	172:65be27845400	1779	/** @brief macro to get the USART1 clock source.
AnnaBridge	172:65be27845400	1780	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1781	* @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock
AnnaBridge	172:65be27845400	1782	* @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock
AnnaBridge	172:65be27845400	1783	* @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock
AnnaBridge	172:65be27845400	1784	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
AnnaBridge	172:65be27845400	1785	* @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock
AnnaBridge	172:65be27845400	1786	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
AnnaBridge	172:65be27845400	1787	*/
AnnaBridge	172:65be27845400	1788	#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL)))
AnnaBridge	172:65be27845400	1789
AnnaBridge	172:65be27845400	1790	/** @brief macro to configure the USART2 clock (USART2CLK).
AnnaBridge	172:65be27845400	1791	*
AnnaBridge	172:65be27845400	1792	* @param __USART2CLKSource__: specifies the USART2 clock source.
AnnaBridge	172:65be27845400	1793	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1794	* @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock
AnnaBridge	172:65be27845400	1795	* @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock
AnnaBridge	172:65be27845400	1796	* @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock
AnnaBridge	172:65be27845400	1797	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
AnnaBridge	172:65be27845400	1798	* @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock
AnnaBridge	172:65be27845400	1799	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
AnnaBridge	172:65be27845400	1800	*/
AnnaBridge	172:65be27845400	1801	#define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \
AnnaBridge	172:65be27845400	1802	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART2CLKSource__))
AnnaBridge	172:65be27845400	1803
AnnaBridge	172:65be27845400	1804	/** @brief macro to get the USART2 clock source.
AnnaBridge	172:65be27845400	1805	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1806	* @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock
AnnaBridge	172:65be27845400	1807	* @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock
AnnaBridge	172:65be27845400	1808	* @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock
AnnaBridge	172:65be27845400	1809	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
AnnaBridge	172:65be27845400	1810	* @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock
AnnaBridge	172:65be27845400	1811	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
AnnaBridge	172:65be27845400	1812	*/
AnnaBridge	172:65be27845400	1813	#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
AnnaBridge	172:65be27845400	1814
AnnaBridge	172:65be27845400	1815	/** @brief macro to configure the USART3 clock (USART3CLK).
AnnaBridge	172:65be27845400	1816	*
AnnaBridge	172:65be27845400	1817	* @param __USART3CLKSource__: specifies the USART3 clock source.
AnnaBridge	172:65be27845400	1818	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1819	* @arg RCC_USART3CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock
AnnaBridge	172:65be27845400	1820	* @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock
AnnaBridge	172:65be27845400	1821	* @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock
AnnaBridge	172:65be27845400	1822	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
AnnaBridge	172:65be27845400	1823	* @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock
AnnaBridge	172:65be27845400	1824	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
AnnaBridge	172:65be27845400	1825	*/
AnnaBridge	172:65be27845400	1826	#define __HAL_RCC_USART3_CONFIG(__USART3CLKSource__) \
AnnaBridge	172:65be27845400	1827	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART3CLKSource__))
AnnaBridge	172:65be27845400	1828
AnnaBridge	172:65be27845400	1829	/** @brief macro to get the USART3 clock source.
AnnaBridge	172:65be27845400	1830	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1831	* @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock
AnnaBridge	172:65be27845400	1832	* @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock
AnnaBridge	172:65be27845400	1833	* @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock
AnnaBridge	172:65be27845400	1834	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
AnnaBridge	172:65be27845400	1835	* @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock
AnnaBridge	172:65be27845400	1836	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
AnnaBridge	172:65be27845400	1837	*/
AnnaBridge	172:65be27845400	1838	#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
AnnaBridge	172:65be27845400	1839
AnnaBridge	172:65be27845400	1840	/** @brief macro to configure the UART4 clock (UART4CLK).
AnnaBridge	172:65be27845400	1841	*
AnnaBridge	172:65be27845400	1842	* @param __UART4CLKSource__: specifies the UART4 clock source.
AnnaBridge	172:65be27845400	1843	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1844	* @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock
AnnaBridge	172:65be27845400	1845	* @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock
AnnaBridge	172:65be27845400	1846	* @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock
AnnaBridge	172:65be27845400	1847	* @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
AnnaBridge	172:65be27845400	1848	* @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock
AnnaBridge	172:65be27845400	1849	* @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
AnnaBridge	172:65be27845400	1850	*/
AnnaBridge	172:65be27845400	1851	#define __HAL_RCC_UART4_CONFIG(__UART4CLKSource__) \
AnnaBridge	172:65be27845400	1852	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART4CLKSource__))
AnnaBridge	172:65be27845400	1853
AnnaBridge	172:65be27845400	1854	/** @brief macro to get the UART4 clock source.
AnnaBridge	172:65be27845400	1855	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1856	* @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock
AnnaBridge	172:65be27845400	1857	* @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock
AnnaBridge	172:65be27845400	1858	* @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock
AnnaBridge	172:65be27845400	1859	* @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
AnnaBridge	172:65be27845400	1860	* @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock
AnnaBridge	172:65be27845400	1861	* @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
AnnaBridge	172:65be27845400	1862	*/
AnnaBridge	172:65be27845400	1863	#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
AnnaBridge	172:65be27845400	1864
AnnaBridge	172:65be27845400	1865	/** @brief macro to configure the UART5 clock (UART5CLK).
AnnaBridge	172:65be27845400	1866	*
AnnaBridge	172:65be27845400	1867	* @param __UART5CLKSource__: specifies the UART5 clock source.
AnnaBridge	172:65be27845400	1868	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1869	* @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock
AnnaBridge	172:65be27845400	1870	* @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock
AnnaBridge	172:65be27845400	1871	* @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock
AnnaBridge	172:65be27845400	1872	* @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
AnnaBridge	172:65be27845400	1873	* @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock
AnnaBridge	172:65be27845400	1874	* @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
AnnaBridge	172:65be27845400	1875	*/
AnnaBridge	172:65be27845400	1876	#define __HAL_RCC_UART5_CONFIG(__UART5CLKSource__) \
AnnaBridge	172:65be27845400	1877	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART5CLKSource__))
AnnaBridge	172:65be27845400	1878
AnnaBridge	172:65be27845400	1879	/** @brief macro to get the UART5 clock source.
AnnaBridge	172:65be27845400	1880	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1881	* @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock
AnnaBridge	172:65be27845400	1882	* @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock
AnnaBridge	172:65be27845400	1883	* @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock
AnnaBridge	172:65be27845400	1884	* @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
AnnaBridge	172:65be27845400	1885	* @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock
AnnaBridge	172:65be27845400	1886	* @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
AnnaBridge	172:65be27845400	1887	*/
AnnaBridge	172:65be27845400	1888	#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
AnnaBridge	172:65be27845400	1889
AnnaBridge	172:65be27845400	1890	/** @brief macro to configure the USART6 clock (USART6CLK).
AnnaBridge	172:65be27845400	1891	*
AnnaBridge	172:65be27845400	1892	* @param __USART6CLKSource__: specifies the USART6 clock source.
AnnaBridge	172:65be27845400	1893	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1894	* @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock
AnnaBridge	172:65be27845400	1895	* @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock
AnnaBridge	172:65be27845400	1896	* @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock
AnnaBridge	172:65be27845400	1897	* @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
AnnaBridge	172:65be27845400	1898	* @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock
AnnaBridge	172:65be27845400	1899	* @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
AnnaBridge	172:65be27845400	1900	*/
AnnaBridge	172:65be27845400	1901	#define __HAL_RCC_USART6_CONFIG(__USART6CLKSource__) \
AnnaBridge	172:65be27845400	1902	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART6CLKSource__))
AnnaBridge	172:65be27845400	1903
AnnaBridge	172:65be27845400	1904	/** @brief macro to get the USART6 clock source.
AnnaBridge	172:65be27845400	1905	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1906	* @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock
AnnaBridge	172:65be27845400	1907	* @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock
AnnaBridge	172:65be27845400	1908	* @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock
AnnaBridge	172:65be27845400	1909	* @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
AnnaBridge	172:65be27845400	1910	* @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock
AnnaBridge	172:65be27845400	1911	* @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
AnnaBridge	172:65be27845400	1912	*/
AnnaBridge	172:65be27845400	1913	#define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL)))
AnnaBridge	172:65be27845400	1914
AnnaBridge	172:65be27845400	1915	/** @brief macro to configure the UART5 clock (UART7CLK).
AnnaBridge	172:65be27845400	1916	*
AnnaBridge	172:65be27845400	1917	* @param __UART7CLKSource__: specifies the UART7 clock source.
AnnaBridge	172:65be27845400	1918	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1919	* @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock
AnnaBridge	172:65be27845400	1920	* @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock
AnnaBridge	172:65be27845400	1921	* @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock
AnnaBridge	172:65be27845400	1922	* @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
AnnaBridge	172:65be27845400	1923	* @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock
AnnaBridge	172:65be27845400	1924	* @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
AnnaBridge	172:65be27845400	1925	*/
AnnaBridge	172:65be27845400	1926	#define __HAL_RCC_UART7_CONFIG(__UART7CLKSource__) \
AnnaBridge	172:65be27845400	1927	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART7CLKSource__))
AnnaBridge	172:65be27845400	1928
AnnaBridge	172:65be27845400	1929	/** @brief macro to get the UART7 clock source.
AnnaBridge	172:65be27845400	1930	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1931	* @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock
AnnaBridge	172:65be27845400	1932	* @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock
AnnaBridge	172:65be27845400	1933	* @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock
AnnaBridge	172:65be27845400	1934	* @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
AnnaBridge	172:65be27845400	1935	* @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock
AnnaBridge	172:65be27845400	1936	* @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
AnnaBridge	172:65be27845400	1937	*/
AnnaBridge	172:65be27845400	1938	#define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
AnnaBridge	172:65be27845400	1939
AnnaBridge	172:65be27845400	1940	/** @brief macro to configure the UART8 clock (UART8CLK).
AnnaBridge	172:65be27845400	1941	*
AnnaBridge	172:65be27845400	1942	* @param __UART8CLKSource__: specifies the UART8 clock source.
AnnaBridge	172:65be27845400	1943	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1944	* @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock
AnnaBridge	172:65be27845400	1945	* @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock
AnnaBridge	172:65be27845400	1946	* @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock
AnnaBridge	172:65be27845400	1947	* @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
AnnaBridge	172:65be27845400	1948	* @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock
AnnaBridge	172:65be27845400	1949	* @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
AnnaBridge	172:65be27845400	1950	*/
AnnaBridge	172:65be27845400	1951	#define __HAL_RCC_UART8_CONFIG(__UART8CLKSource__) \
AnnaBridge	172:65be27845400	1952	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__UART8CLKSource__))
AnnaBridge	172:65be27845400	1953
AnnaBridge	172:65be27845400	1954	/** @brief macro to get the UART8 clock source.
AnnaBridge	172:65be27845400	1955	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1956	* @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock
AnnaBridge	172:65be27845400	1957	* @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock
AnnaBridge	172:65be27845400	1958	* @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock
AnnaBridge	172:65be27845400	1959	* @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
AnnaBridge	172:65be27845400	1960	* @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock
AnnaBridge	172:65be27845400	1961	* @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
AnnaBridge	172:65be27845400	1962	*/
AnnaBridge	172:65be27845400	1963	#define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))
AnnaBridge	172:65be27845400	1964
AnnaBridge	172:65be27845400	1965	/** @brief macro to configure the LPUART1 clock (LPUART1CLK).
AnnaBridge	172:65be27845400	1966	*
AnnaBridge	172:65be27845400	1967	* @param __LPUART1CLKSource__: specifies the LPUART1 clock source.
AnnaBridge	172:65be27845400	1968	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	1969	* @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock
AnnaBridge	172:65be27845400	1970	* @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock
AnnaBridge	172:65be27845400	1971	* @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock
AnnaBridge	172:65be27845400	1972	* @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
AnnaBridge	172:65be27845400	1973	* @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock
AnnaBridge	172:65be27845400	1974	* @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
AnnaBridge	172:65be27845400	1975	*/
AnnaBridge	172:65be27845400	1976	#define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \
AnnaBridge	172:65be27845400	1977	MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))
AnnaBridge	172:65be27845400	1978
AnnaBridge	172:65be27845400	1979	/** @brief macro to get the LPUART1 clock source.
AnnaBridge	172:65be27845400	1980	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1981	* @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock
AnnaBridge	172:65be27845400	1982	* @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock
AnnaBridge	172:65be27845400	1983	* @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock
AnnaBridge	172:65be27845400	1984	* @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
AnnaBridge	172:65be27845400	1985	* @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock
AnnaBridge	172:65be27845400	1986	* @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
AnnaBridge	172:65be27845400	1987	*/
AnnaBridge	172:65be27845400	1988	#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL)))
AnnaBridge	172:65be27845400	1989
AnnaBridge	172:65be27845400	1990	/** @brief macro to get the LPTIM1 clock source.
AnnaBridge	172:65be27845400	1991	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	1992	* @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock
AnnaBridge	172:65be27845400	1993	* @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock
AnnaBridge	172:65be27845400	1994	* @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock
AnnaBridge	172:65be27845400	1995	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
AnnaBridge	172:65be27845400	1996	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock
AnnaBridge	172:65be27845400	1997	* @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock
AnnaBridge	172:65be27845400	1998	*/
AnnaBridge	172:65be27845400	1999	#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \
AnnaBridge	172:65be27845400	2000	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))
AnnaBridge	172:65be27845400	2001
AnnaBridge	172:65be27845400	2002
AnnaBridge	172:65be27845400	2003	/** @brief macro to get the LPTIM1 clock source.
AnnaBridge	172:65be27845400	2004	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	2005	* @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock
AnnaBridge	172:65be27845400	2006	* @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock
AnnaBridge	172:65be27845400	2007	* @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock
AnnaBridge	172:65be27845400	2008	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
AnnaBridge	172:65be27845400	2009	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock
AnnaBridge	172:65be27845400	2010	* @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock
AnnaBridge	172:65be27845400	2011	*/
AnnaBridge	172:65be27845400	2012	#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL)))
AnnaBridge	172:65be27845400	2013
AnnaBridge	172:65be27845400	2014	/** @brief macro to get the LPTIM2 clock source.
AnnaBridge	172:65be27845400	2015	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	2016	* @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock
AnnaBridge	172:65be27845400	2017	* @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock
AnnaBridge	172:65be27845400	2018	* @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock
AnnaBridge	172:65be27845400	2019	* @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock
AnnaBridge	172:65be27845400	2020	* @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock
AnnaBridge	172:65be27845400	2021	* @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock
AnnaBridge	172:65be27845400	2022	*/
AnnaBridge	172:65be27845400	2023	#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \
AnnaBridge	172:65be27845400	2024	MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))
AnnaBridge	172:65be27845400	2025
AnnaBridge	172:65be27845400	2026
AnnaBridge	172:65be27845400	2027	/** @brief macro to get the LPTIM2 clock source.
AnnaBridge	172:65be27845400	2028	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	2029	* @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock
AnnaBridge	172:65be27845400	2030	* @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock
AnnaBridge	172:65be27845400	2031	* @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock
AnnaBridge	172:65be27845400	2032	* @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock
AnnaBridge	172:65be27845400	2033	* @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock
AnnaBridge	172:65be27845400	2034	* @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock
AnnaBridge	172:65be27845400	2035	*/
AnnaBridge	172:65be27845400	2036	#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL)))
AnnaBridge	172:65be27845400	2037
AnnaBridge	172:65be27845400	2038	/** @brief macro to get the LPTIM3/4/5 clock source.
AnnaBridge	172:65be27845400	2039	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	2040	* @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock
AnnaBridge	172:65be27845400	2041	* @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock
AnnaBridge	172:65be27845400	2042	* @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock
AnnaBridge	172:65be27845400	2043	* @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock
AnnaBridge	172:65be27845400	2044	* @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock
AnnaBridge	172:65be27845400	2045	* @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock
AnnaBridge	172:65be27845400	2046	*/
AnnaBridge	172:65be27845400	2047	#define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \
AnnaBridge	172:65be27845400	2048	MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM345CLKSource__))
AnnaBridge	172:65be27845400	2049
AnnaBridge	172:65be27845400	2050
AnnaBridge	172:65be27845400	2051	/** @brief macro to get the LPTIM3/4/5 clock source.
AnnaBridge	172:65be27845400	2052	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	2053	* @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock
AnnaBridge	172:65be27845400	2054	* @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock
AnnaBridge	172:65be27845400	2055	* @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock
AnnaBridge	172:65be27845400	2056	* @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock
AnnaBridge	172:65be27845400	2057	* @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock
AnnaBridge	172:65be27845400	2058	* @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock
AnnaBridge	172:65be27845400	2059	*/
AnnaBridge	172:65be27845400	2060	#define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))
AnnaBridge	172:65be27845400	2061
AnnaBridge	172:65be27845400	2062	/** @brief macro to get the LPTIM3 clock source.
AnnaBridge	172:65be27845400	2063	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	2064	* @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock
AnnaBridge	172:65be27845400	2065	* @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock
AnnaBridge	172:65be27845400	2066	* @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock
AnnaBridge	172:65be27845400	2067	* @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock
AnnaBridge	172:65be27845400	2068	* @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock
AnnaBridge	172:65be27845400	2069	* @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock
AnnaBridge	172:65be27845400	2070	*/
AnnaBridge	172:65be27845400	2071	#define __HAL_RCC_LPTIM3_CONFIG(__LPTIM3CLKSource__) \
AnnaBridge	172:65be27845400	2072	MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM3CLKSource__))
AnnaBridge	172:65be27845400	2073
AnnaBridge	172:65be27845400	2074
AnnaBridge	172:65be27845400	2075	/** @brief macro to get the LPTIM3 clock source.
AnnaBridge	172:65be27845400	2076	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	2077	* @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock
AnnaBridge	172:65be27845400	2078	* @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock
AnnaBridge	172:65be27845400	2079	* @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock
AnnaBridge	172:65be27845400	2080	* @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock
AnnaBridge	172:65be27845400	2081	* @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock
AnnaBridge	172:65be27845400	2082	* @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock
AnnaBridge	172:65be27845400	2083	*/
AnnaBridge	172:65be27845400	2084	#define __HAL_RCC_GET_LPTIM3_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))
AnnaBridge	172:65be27845400	2085
AnnaBridge	172:65be27845400	2086	/** @brief macro to get the LPTIM4 clock source.
AnnaBridge	172:65be27845400	2087	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	2088	* @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock
AnnaBridge	172:65be27845400	2089	* @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock
AnnaBridge	172:65be27845400	2090	* @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock
AnnaBridge	172:65be27845400	2091	* @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock
AnnaBridge	172:65be27845400	2092	* @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock
AnnaBridge	172:65be27845400	2093	* @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock
AnnaBridge	172:65be27845400	2094	*/
AnnaBridge	172:65be27845400	2095	#define __HAL_RCC_LPTIM4_CONFIG(__LPTIM4CLKSource__) \
AnnaBridge	172:65be27845400	2096	MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM4CLKSource__))
AnnaBridge	172:65be27845400	2097
AnnaBridge	172:65be27845400	2098
AnnaBridge	172:65be27845400	2099	/** @brief macro to get the LPTIM4 clock source.
AnnaBridge	172:65be27845400	2100	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	2101	* @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock
AnnaBridge	172:65be27845400	2102	* @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock
AnnaBridge	172:65be27845400	2103	* @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock
AnnaBridge	172:65be27845400	2104	* @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock
AnnaBridge	172:65be27845400	2105	* @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock
AnnaBridge	172:65be27845400	2106	* @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock
AnnaBridge	172:65be27845400	2107	*/
AnnaBridge	172:65be27845400	2108	#define __HAL_RCC_GET_LPTIM4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))
AnnaBridge	172:65be27845400	2109
AnnaBridge	172:65be27845400	2110	/** @brief macro to configure the LPTIM5 clock source.
AnnaBridge	172:65be27845400	2111	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	2112	* @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock
AnnaBridge	172:65be27845400	2113	* @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock
AnnaBridge	172:65be27845400	2114	* @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock
AnnaBridge	172:65be27845400	2115	* @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock
AnnaBridge	172:65be27845400	2116	* @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock
AnnaBridge	172:65be27845400	2117	* @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock
AnnaBridge	172:65be27845400	2118	*/
AnnaBridge	172:65be27845400	2119	#define __HAL_RCC_LPTIM5_CONFIG(__LPTIM5CLKSource__) \
AnnaBridge	172:65be27845400	2120	MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM5CLKSource__))
AnnaBridge	172:65be27845400	2121
AnnaBridge	172:65be27845400	2122
AnnaBridge	172:65be27845400	2123	/** @brief macro to get the LPTIM5 clock source.
AnnaBridge	172:65be27845400	2124	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	2125	* @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock
AnnaBridge	172:65be27845400	2126	* @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock
AnnaBridge	172:65be27845400	2127	* @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock
AnnaBridge	172:65be27845400	2128	* @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock
AnnaBridge	172:65be27845400	2129	* @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock
AnnaBridge	172:65be27845400	2130	* @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock
AnnaBridge	172:65be27845400	2131	*/
AnnaBridge	172:65be27845400	2132	#define __HAL_RCC_GET_LPTIM5_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))
AnnaBridge	172:65be27845400	2133
AnnaBridge	172:65be27845400	2134	/** @brief macro to configure the QSPI clock source.
AnnaBridge	172:65be27845400	2135	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	2136	* @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock
AnnaBridge	172:65be27845400	2137	* @arg RCC_RCC_QSPICLKSOURCE_PLL : PLL1_Q Clock selected as QSPI clock
AnnaBridge	172:65be27845400	2138	* @arg RCC_RCC_QSPICLKSOURCE_PLL2 : PLL2_R Clock selected as QSPI clock
AnnaBridge	172:65be27845400	2139	* @arg RCC_RCC_QSPICLKSOURCE_CLKP CLKP selected as QSPI clock
AnnaBridge	172:65be27845400	2140	*/
AnnaBridge	172:65be27845400	2141	#define __HAL_RCC_QSPI_CONFIG(__QSPICLKSource__) \
AnnaBridge	172:65be27845400	2142	MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, (uint32_t)(__QSPICLKSource__))
AnnaBridge	172:65be27845400	2143
AnnaBridge	172:65be27845400	2144
AnnaBridge	172:65be27845400	2145	/** @brief macro to get the QSPI clock source.
AnnaBridge	172:65be27845400	2146	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	2147	* @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock
AnnaBridge	172:65be27845400	2148	* @arg RCC_RCC_QSPICLKSOURCE_PLL : PLL1_Q Clock selected as QSPI clock
AnnaBridge	172:65be27845400	2149	* @arg RCC_RCC_QSPICLKSOURCE_PLL2 : PLL2_R Clock selected as QSPI clock
AnnaBridge	172:65be27845400	2150	* @arg RCC_RCC_QSPICLKSOURCE_CLKP CLKP selected as QSPI clock
AnnaBridge	172:65be27845400	2151	*/
AnnaBridge	172:65be27845400	2152	#define __HAL_RCC_GET_QSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL)))
AnnaBridge	172:65be27845400	2153
AnnaBridge	172:65be27845400	2154	/** @brief macro to configure the FMC clock source.
AnnaBridge	172:65be27845400	2155	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	2156	* @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock
AnnaBridge	172:65be27845400	2157	* @arg RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock
AnnaBridge	172:65be27845400	2158	* @arg RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock
AnnaBridge	172:65be27845400	2159	* @arg RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock
AnnaBridge	172:65be27845400	2160	*/
AnnaBridge	172:65be27845400	2161	#define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \
AnnaBridge	172:65be27845400	2162	MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))
AnnaBridge	172:65be27845400	2163
AnnaBridge	172:65be27845400	2164
AnnaBridge	172:65be27845400	2165	/** @brief macro to get the FMC clock source.
AnnaBridge	172:65be27845400	2166	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	2167	* @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock
AnnaBridge	172:65be27845400	2168	* @arg RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock
AnnaBridge	172:65be27845400	2169	* @arg RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock
AnnaBridge	172:65be27845400	2170	* @arg RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock
AnnaBridge	172:65be27845400	2171	*/
AnnaBridge	172:65be27845400	2172	#define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL)))
AnnaBridge	172:65be27845400	2173
AnnaBridge	172:65be27845400	2174	/** @brief Macro to configure the USB clock (USBCLK).
AnnaBridge	172:65be27845400	2175	* @param __USBCLKSource__: specifies the USB clock source.
AnnaBridge	172:65be27845400	2176	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2177	* @arg RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock
AnnaBridge	172:65be27845400	2178	* @arg RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock
AnnaBridge	172:65be27845400	2179	* @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock
AnnaBridge	172:65be27845400	2180	*/
AnnaBridge	172:65be27845400	2181	#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
AnnaBridge	172:65be27845400	2182	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))
AnnaBridge	172:65be27845400	2183
AnnaBridge	172:65be27845400	2184	/** @brief Macro to get the USB clock source.
AnnaBridge	172:65be27845400	2185	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	2186	* @arg RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock
AnnaBridge	172:65be27845400	2187	* @arg RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock
AnnaBridge	172:65be27845400	2188	* @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock
AnnaBridge	172:65be27845400	2189	*/
AnnaBridge	172:65be27845400	2190	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL)))
AnnaBridge	172:65be27845400	2191
AnnaBridge	172:65be27845400	2192
AnnaBridge	172:65be27845400	2193	/** @brief Macro to configure the ADC clock
AnnaBridge	172:65be27845400	2194	* @param __ADCCLKSource__: specifies the ADC digital interface clock source.
AnnaBridge	172:65be27845400	2195	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2196	* @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock
AnnaBridge	172:65be27845400	2197	* @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock
AnnaBridge	172:65be27845400	2198	* @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock
AnnaBridge	172:65be27845400	2199	*/
AnnaBridge	172:65be27845400	2200	#define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \
AnnaBridge	172:65be27845400	2201	MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))
AnnaBridge	172:65be27845400	2202
AnnaBridge	172:65be27845400	2203	/** @brief Macro to get the ADC clock source.
AnnaBridge	172:65be27845400	2204	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	2205	* @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock
AnnaBridge	172:65be27845400	2206	* @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock
AnnaBridge	172:65be27845400	2207	* @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock
AnnaBridge	172:65be27845400	2208	*/
AnnaBridge	172:65be27845400	2209	#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL)))
AnnaBridge	172:65be27845400	2210
AnnaBridge	172:65be27845400	2211	/** @brief Macro to configure the SWPMI1 clock
AnnaBridge	172:65be27845400	2212	* @param __SWPMI1CLKSource__: specifies the SWPMI1 clock source.
AnnaBridge	172:65be27845400	2213	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2214	* @arg RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock
AnnaBridge	172:65be27845400	2215	* @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock
AnnaBridge	172:65be27845400	2216	*/
AnnaBridge	172:65be27845400	2217	#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \
AnnaBridge	172:65be27845400	2218	MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))
AnnaBridge	172:65be27845400	2219
AnnaBridge	172:65be27845400	2220	/** @brief Macro to get the SWPMI1 clock source.
AnnaBridge	172:65be27845400	2221	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	2222	* @arg RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock
AnnaBridge	172:65be27845400	2223	* @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock
AnnaBridge	172:65be27845400	2224	*/
AnnaBridge	172:65be27845400	2225	#define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL)))
AnnaBridge	172:65be27845400	2226
AnnaBridge	172:65be27845400	2227	/** @brief Macro to configure the DFSDM1 clock
AnnaBridge	172:65be27845400	2228	* @param __DFSDM1CLKSource__: specifies the DFSDM1 clock source.
AnnaBridge	172:65be27845400	2229	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2230	* @arg RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock
AnnaBridge	172:65be27845400	2231	* @arg RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock
AnnaBridge	172:65be27845400	2232	*/
AnnaBridge	172:65be27845400	2233	#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \
AnnaBridge	172:65be27845400	2234	MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))
AnnaBridge	172:65be27845400	2235
AnnaBridge	172:65be27845400	2236	/** @brief Macro to get the DFSDM1 clock source.
AnnaBridge	172:65be27845400	2237	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	2238	* @arg RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock
AnnaBridge	172:65be27845400	2239	* @arg RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock
AnnaBridge	172:65be27845400	2240	*/
AnnaBridge	172:65be27845400	2241	#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL)))
AnnaBridge	172:65be27845400	2242
AnnaBridge	172:65be27845400	2243	/** @brief macro to configure the CEC clock (CECCLK).
AnnaBridge	172:65be27845400	2244	*
AnnaBridge	172:65be27845400	2245	* @param __CECCLKSource__: specifies the CEC clock source.
AnnaBridge	172:65be27845400	2246	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2247	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
AnnaBridge	172:65be27845400	2248	* @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock
AnnaBridge	172:65be27845400	2249	* @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock
AnnaBridge	172:65be27845400	2250	*/
AnnaBridge	172:65be27845400	2251	#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
AnnaBridge	172:65be27845400	2252	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))
AnnaBridge	172:65be27845400	2253
AnnaBridge	172:65be27845400	2254	/** @brief macro to get the CEC clock source.
AnnaBridge	172:65be27845400	2255	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	2256	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
AnnaBridge	172:65be27845400	2257	* @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock
AnnaBridge	172:65be27845400	2258	* @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock
AnnaBridge	172:65be27845400	2259	*/
AnnaBridge	172:65be27845400	2260	#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL)))
AnnaBridge	172:65be27845400	2261
AnnaBridge	172:65be27845400	2262
AnnaBridge	172:65be27845400	2263	/** @brief Macro to configure the CLKP : Oscillator clock for peripheral
AnnaBridge	172:65be27845400	2264	* @param __CLKPSource__: specifies Oscillator clock for peripheral
AnnaBridge	172:65be27845400	2265	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2266	* @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral
AnnaBridge	172:65be27845400	2267	* @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral
AnnaBridge	172:65be27845400	2268	* @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral
AnnaBridge	172:65be27845400	2269	*/
AnnaBridge	172:65be27845400	2270	#define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \
AnnaBridge	172:65be27845400	2271	MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))
AnnaBridge	172:65be27845400	2272
AnnaBridge	172:65be27845400	2273	/** @brief Macro to get the Oscillator clock for peripheral source.
AnnaBridge	172:65be27845400	2274	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	2275	* @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral
AnnaBridge	172:65be27845400	2276	* @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral
AnnaBridge	172:65be27845400	2277	* @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral
AnnaBridge	172:65be27845400	2278	*/
AnnaBridge	172:65be27845400	2279	#define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL)))
AnnaBridge	172:65be27845400	2280
AnnaBridge	172:65be27845400	2281	#if defined(FDCAN1) \|\| defined(FDCAN2)
AnnaBridge	172:65be27845400	2282	/** @brief Macro to configure the FDCAN clock
AnnaBridge	172:65be27845400	2283	* @param __FDCANCLKSource__: specifies clock source for FDCAN
AnnaBridge	172:65be27845400	2284	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2285	* @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock
AnnaBridge	172:65be27845400	2286	* @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock
AnnaBridge	172:65be27845400	2287	* @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock
AnnaBridge	172:65be27845400	2288	*/
AnnaBridge	172:65be27845400	2289	#define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \
AnnaBridge	172:65be27845400	2290	MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__))
AnnaBridge	172:65be27845400	2291
AnnaBridge	172:65be27845400	2292	/** @brief Macro to get the FDCAN clock
AnnaBridge	172:65be27845400	2293	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	2294	* @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock
AnnaBridge	172:65be27845400	2295	* @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock
AnnaBridge	172:65be27845400	2296	* @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock
AnnaBridge	172:65be27845400	2297	*/
AnnaBridge	172:65be27845400	2298	#define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL)))
AnnaBridge	172:65be27845400	2299	#endif /FDCAN1 \|\| FDCAN2/
AnnaBridge	172:65be27845400	2300	/**
AnnaBridge	172:65be27845400	2301	* @brief Macro to Configure the SPI1/2/3 clock source.
AnnaBridge	172:65be27845400	2302	* @param __RCC_SPI123CLKSource__: defines the SPI1/2/3 clock source. This clock is derived
AnnaBridge	172:65be27845400	2303	* from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
AnnaBridge	172:65be27845400	2304	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2305	* @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL
AnnaBridge	172:65be27845400	2306	* @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2
AnnaBridge	172:65be27845400	2307	* @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3
AnnaBridge	172:65be27845400	2308	* @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock = CLKP
AnnaBridge	172:65be27845400	2309	* @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock
AnnaBridge	172:65be27845400	2310	* @retval None
AnnaBridge	172:65be27845400	2311	*/
AnnaBridge	172:65be27845400	2312	#define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\
AnnaBridge	172:65be27845400	2313	MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__))
AnnaBridge	172:65be27845400	2314
AnnaBridge	172:65be27845400	2315	/** @brief Macro to get the SPI1/2/3 clock source.
AnnaBridge	172:65be27845400	2316	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	2317	* @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL
AnnaBridge	172:65be27845400	2318	* @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2
AnnaBridge	172:65be27845400	2319	* @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3
AnnaBridge	172:65be27845400	2320	* @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock = CLKP
AnnaBridge	172:65be27845400	2321	* @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock
AnnaBridge	172:65be27845400	2322	*/
AnnaBridge	172:65be27845400	2323	#define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))
AnnaBridge	172:65be27845400	2324
AnnaBridge	172:65be27845400	2325	/**
AnnaBridge	172:65be27845400	2326	* @brief Macro to Configure the SPI1 clock source.
AnnaBridge	172:65be27845400	2327	* @param __RCC_SPI1CLKSource__: defines the SPI1 clock source. This clock is derived
AnnaBridge	172:65be27845400	2328	* from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
AnnaBridge	172:65be27845400	2329	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2330	* @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL
AnnaBridge	172:65be27845400	2331	* @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2
AnnaBridge	172:65be27845400	2332	* @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3
AnnaBridge	172:65be27845400	2333	* @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock = CLKP
AnnaBridge	172:65be27845400	2334	* @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock
AnnaBridge	172:65be27845400	2335	* @retval None
AnnaBridge	172:65be27845400	2336	*/
AnnaBridge	172:65be27845400	2337	#define __HAL_RCC_SPI1_CONFIG(__RCC_SPI1CLKSource__ )\
AnnaBridge	172:65be27845400	2338	MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI1CLKSource__))
AnnaBridge	172:65be27845400	2339
AnnaBridge	172:65be27845400	2340	/** @brief Macro to get the SPI1 clock source.
AnnaBridge	172:65be27845400	2341	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	2342	* @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL
AnnaBridge	172:65be27845400	2343	* @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2
AnnaBridge	172:65be27845400	2344	* @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3
AnnaBridge	172:65be27845400	2345	* @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock = CLKP
AnnaBridge	172:65be27845400	2346	* @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock
AnnaBridge	172:65be27845400	2347	*/
AnnaBridge	172:65be27845400	2348	#define __HAL_RCC_GET_SPI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))
AnnaBridge	172:65be27845400	2349
AnnaBridge	172:65be27845400	2350	/**
AnnaBridge	172:65be27845400	2351	* @brief Macro to Configure the SPI2 clock source.
AnnaBridge	172:65be27845400	2352	* @param __RCC_SPI2CLKSource__: defines the SPI2 clock source. This clock is derived
AnnaBridge	172:65be27845400	2353	* from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
AnnaBridge	172:65be27845400	2354	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2355	* @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL
AnnaBridge	172:65be27845400	2356	* @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2
AnnaBridge	172:65be27845400	2357	* @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3
AnnaBridge	172:65be27845400	2358	* @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock = CLKP
AnnaBridge	172:65be27845400	2359	* @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock
AnnaBridge	172:65be27845400	2360	* @retval None
AnnaBridge	172:65be27845400	2361	*/
AnnaBridge	172:65be27845400	2362	#define __HAL_RCC_SPI2_CONFIG(__RCC_SPI2CLKSource__ )\
AnnaBridge	172:65be27845400	2363	MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI2CLKSource__))
AnnaBridge	172:65be27845400	2364
AnnaBridge	172:65be27845400	2365	/** @brief Macro to get the SPI2 clock source.
AnnaBridge	172:65be27845400	2366	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	2367	* @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL
AnnaBridge	172:65be27845400	2368	* @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2
AnnaBridge	172:65be27845400	2369	* @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3
AnnaBridge	172:65be27845400	2370	* @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock = CLKP
AnnaBridge	172:65be27845400	2371	* @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock
AnnaBridge	172:65be27845400	2372	*/
AnnaBridge	172:65be27845400	2373	#define __HAL_RCC_GET_SPI2_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))
AnnaBridge	172:65be27845400	2374
AnnaBridge	172:65be27845400	2375	/**
AnnaBridge	172:65be27845400	2376	* @brief Macro to Configure the SPI3 clock source.
AnnaBridge	172:65be27845400	2377	* @param __RCC_SPI3CLKSource__: defines the SPI3 clock source. This clock is derived
AnnaBridge	172:65be27845400	2378	* from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)
AnnaBridge	172:65be27845400	2379	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2380	* @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL
AnnaBridge	172:65be27845400	2381	* @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2
AnnaBridge	172:65be27845400	2382	* @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3
AnnaBridge	172:65be27845400	2383	* @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock = CLKP
AnnaBridge	172:65be27845400	2384	* @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock
AnnaBridge	172:65be27845400	2385	* @retval None
AnnaBridge	172:65be27845400	2386	*/
AnnaBridge	172:65be27845400	2387	#define __HAL_RCC_SPI3_CONFIG(__RCC_SPI3CLKSource__ )\
AnnaBridge	172:65be27845400	2388	MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI3CLKSource__))
AnnaBridge	172:65be27845400	2389
AnnaBridge	172:65be27845400	2390	/** @brief Macro to get the SPI3 clock source.
AnnaBridge	172:65be27845400	2391	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	2392	* @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL
AnnaBridge	172:65be27845400	2393	* @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2
AnnaBridge	172:65be27845400	2394	* @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3
AnnaBridge	172:65be27845400	2395	* @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock = CLKP
AnnaBridge	172:65be27845400	2396	* @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock
AnnaBridge	172:65be27845400	2397	*/
AnnaBridge	172:65be27845400	2398	#define __HAL_RCC_GET_SPI3_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))
AnnaBridge	172:65be27845400	2399
AnnaBridge	172:65be27845400	2400	/**
AnnaBridge	172:65be27845400	2401	* @brief Macro to Configure the SPI4/5 clock source.
AnnaBridge	172:65be27845400	2402	* @param __RCC_SPI45CLKSource__: defines the SPI4/5 clock source. This clock is derived
AnnaBridge	172:65be27845400	2403	* from system PCLK, PLL2, PLL3, OSC
AnnaBridge	172:65be27845400	2404	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2405	* @arg RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1
AnnaBridge	172:65be27845400	2406	* @arg RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2
AnnaBridge	172:65be27845400	2407	* @arg RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3
AnnaBridge	172:65be27845400	2408	* @arg RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI
AnnaBridge	172:65be27845400	2409	* @arg RCC_SPI45CLKSOURCE_CSI: SPI4/5 clock = CSI
AnnaBridge	172:65be27845400	2410	* @arg RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE
AnnaBridge	172:65be27845400	2411	* @retval None
AnnaBridge	172:65be27845400	2412	*/
AnnaBridge	172:65be27845400	2413	#define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\
AnnaBridge	172:65be27845400	2414	MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__))
AnnaBridge	172:65be27845400	2415
AnnaBridge	172:65be27845400	2416	/** @brief Macro to get the SPI4/5 clock source.
AnnaBridge	172:65be27845400	2417	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	2418	* @arg RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1
AnnaBridge	172:65be27845400	2419	* @arg RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2
AnnaBridge	172:65be27845400	2420	* @arg RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3
AnnaBridge	172:65be27845400	2421	* @arg RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI
AnnaBridge	172:65be27845400	2422	* @arg RCC_SPI45CLKSOURCE_CSI: SPI4/5 clock = CSI
AnnaBridge	172:65be27845400	2423	* @arg RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE
AnnaBridge	172:65be27845400	2424	*/
AnnaBridge	172:65be27845400	2425	#define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL)))
AnnaBridge	172:65be27845400	2426
AnnaBridge	172:65be27845400	2427	/**
AnnaBridge	172:65be27845400	2428	* @brief Macro to Configure the SPI4 clock source.
AnnaBridge	172:65be27845400	2429	* @param __RCC_SPI4CLKSource__: defines the SPI4 clock source. This clock is derived
AnnaBridge	172:65be27845400	2430	* from system PCLK, PLL2, PLL3, OSC
AnnaBridge	172:65be27845400	2431	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2432	* @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1
AnnaBridge	172:65be27845400	2433	* @arg RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2
AnnaBridge	172:65be27845400	2434	* @arg RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3
AnnaBridge	172:65be27845400	2435	* @arg RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI
AnnaBridge	172:65be27845400	2436	* @arg RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI
AnnaBridge	172:65be27845400	2437	* @arg RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE
AnnaBridge	172:65be27845400	2438	* @retval None
AnnaBridge	172:65be27845400	2439	*/
AnnaBridge	172:65be27845400	2440	#define __HAL_RCC_SPI4_CONFIG(__RCC_SPI4CLKSource__ )\
AnnaBridge	172:65be27845400	2441	MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI4CLKSource__))
AnnaBridge	172:65be27845400	2442
AnnaBridge	172:65be27845400	2443	/** @brief Macro to get the SPI4 clock source.
AnnaBridge	172:65be27845400	2444	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	2445	* @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1
AnnaBridge	172:65be27845400	2446	* @arg RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2
AnnaBridge	172:65be27845400	2447	* @arg RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3
AnnaBridge	172:65be27845400	2448	* @arg RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI
AnnaBridge	172:65be27845400	2449	* @arg RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI
AnnaBridge	172:65be27845400	2450	* @arg RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE
AnnaBridge	172:65be27845400	2451	*/
AnnaBridge	172:65be27845400	2452	#define __HAL_RCC_GET_SPI4_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL)))
AnnaBridge	172:65be27845400	2453
AnnaBridge	172:65be27845400	2454	/**
AnnaBridge	172:65be27845400	2455	* @brief Macro to Configure the SPI5 clock source.
AnnaBridge	172:65be27845400	2456	* @param __RCC_SPI5CLKSource__: defines the SPI5 clock source. This clock is derived
AnnaBridge	172:65be27845400	2457	* from system PCLK, PLL2, PLL3, OSC
AnnaBridge	172:65be27845400	2458	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2459	* @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1
AnnaBridge	172:65be27845400	2460	* @arg RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2
AnnaBridge	172:65be27845400	2461	* @arg RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3
AnnaBridge	172:65be27845400	2462	* @arg RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI
AnnaBridge	172:65be27845400	2463	* @arg RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI
AnnaBridge	172:65be27845400	2464	* @arg RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE
AnnaBridge	172:65be27845400	2465	* @retval None
AnnaBridge	172:65be27845400	2466	*/
AnnaBridge	172:65be27845400	2467	#define __HAL_RCC_SPI5_CONFIG(__RCC_SPI5CLKSource__ )\
AnnaBridge	172:65be27845400	2468	MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI5CLKSource__))
AnnaBridge	172:65be27845400	2469
AnnaBridge	172:65be27845400	2470	/** @brief Macro to get the SPI5 clock source.
AnnaBridge	172:65be27845400	2471	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	2472	* @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1
AnnaBridge	172:65be27845400	2473	* @arg RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2
AnnaBridge	172:65be27845400	2474	* @arg RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3
AnnaBridge	172:65be27845400	2475	* @arg RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI
AnnaBridge	172:65be27845400	2476	* @arg RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI
AnnaBridge	172:65be27845400	2477	* @arg RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE
AnnaBridge	172:65be27845400	2478	*/
AnnaBridge	172:65be27845400	2479	#define __HAL_RCC_GET_SPI5_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL)))
AnnaBridge	172:65be27845400	2480
AnnaBridge	172:65be27845400	2481	/**
AnnaBridge	172:65be27845400	2482	* @brief Macro to Configure the SPI6 clock source.
AnnaBridge	172:65be27845400	2483	* @param __RCC_SPI6CLKSource__: defines the SPI6 clock source. This clock is derived
AnnaBridge	172:65be27845400	2484	* from system PCLK, PLL2, PLL3, OSC
AnnaBridge	172:65be27845400	2485	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2486	* @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1
AnnaBridge	172:65be27845400	2487	* @arg RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2
AnnaBridge	172:65be27845400	2488	* @arg RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3
AnnaBridge	172:65be27845400	2489	* @arg RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI
AnnaBridge	172:65be27845400	2490	* @arg RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI
AnnaBridge	172:65be27845400	2491	* @arg RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE
AnnaBridge	172:65be27845400	2492	* @retval None
AnnaBridge	172:65be27845400	2493	*/
AnnaBridge	172:65be27845400	2494	#define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\
AnnaBridge	172:65be27845400	2495	MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))
AnnaBridge	172:65be27845400	2496
AnnaBridge	172:65be27845400	2497	/** @brief Macro to get the SPI6 clock source.
AnnaBridge	172:65be27845400	2498	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	2499	* @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1
AnnaBridge	172:65be27845400	2500	* @arg RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2
AnnaBridge	172:65be27845400	2501	* @arg RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3
AnnaBridge	172:65be27845400	2502	* @arg RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI
AnnaBridge	172:65be27845400	2503	* @arg RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI
AnnaBridge	172:65be27845400	2504	* @arg RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE
AnnaBridge	172:65be27845400	2505	*/
AnnaBridge	172:65be27845400	2506	#define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL)))
AnnaBridge	172:65be27845400	2507
AnnaBridge	172:65be27845400	2508	/** @brief Macro to configure the SDMMC clock
AnnaBridge	172:65be27845400	2509	* @param __SDMMCCLKSource__: specifies clock source for SDMMC
AnnaBridge	172:65be27845400	2510	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2511	* @arg RCC_SDMMCCLKSOURCE_PLL: PLLQ selected as SDMMC clock
AnnaBridge	172:65be27845400	2512	* @arg RCC_SDMMCCLKSOURCE_PLL2: PLL2R selected as SDMMC clock
AnnaBridge	172:65be27845400	2513	*/
AnnaBridge	172:65be27845400	2514	#define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \
AnnaBridge	172:65be27845400	2515	MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))
AnnaBridge	172:65be27845400	2516
AnnaBridge	172:65be27845400	2517	/** @brief Macro to get the SDMMC clock
AnnaBridge	172:65be27845400	2518	*/
AnnaBridge	172:65be27845400	2519	#define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL)))
AnnaBridge	172:65be27845400	2520
AnnaBridge	172:65be27845400	2521	/** @brief macro to configure the RNG clock (RNGCLK).
AnnaBridge	172:65be27845400	2522	*
AnnaBridge	172:65be27845400	2523	* @param __RNGCLKSource__: specifies the RNG clock source.
AnnaBridge	172:65be27845400	2524	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2525	* @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
AnnaBridge	172:65be27845400	2526	* @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock
AnnaBridge	172:65be27845400	2527	* @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock
AnnaBridge	172:65be27845400	2528	* @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock
AnnaBridge	172:65be27845400	2529	*/
AnnaBridge	172:65be27845400	2530	#define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \
AnnaBridge	172:65be27845400	2531	MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))
AnnaBridge	172:65be27845400	2532
AnnaBridge	172:65be27845400	2533	/** @brief macro to get the RNG clock source.
AnnaBridge	172:65be27845400	2534	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	2535	* @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
AnnaBridge	172:65be27845400	2536	* @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock
AnnaBridge	172:65be27845400	2537	* @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock
AnnaBridge	172:65be27845400	2538	* @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock
AnnaBridge	172:65be27845400	2539	*/
AnnaBridge	172:65be27845400	2540	#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL)))
AnnaBridge	172:65be27845400	2541
AnnaBridge	172:65be27845400	2542
AnnaBridge	172:65be27845400	2543	/** @defgroup RCCEx_HRTIMx_Clock_Config RCC Extended HRTIMx Clock Config
AnnaBridge	172:65be27845400	2544	* @{
AnnaBridge	172:65be27845400	2545	*/
AnnaBridge	172:65be27845400	2546	/** @brief Macro to configure the HRTIM1 prescaler clock source.
AnnaBridge	172:65be27845400	2547	* @param __HRTIM1CLKSource__ specifies the HRTIM1 prescaler clock source.
AnnaBridge	172:65be27845400	2548	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2549	* @arg @ref RCC_HRTIM1CLK_TIMCLK Timers clock selected as HRTIM1 prescaler clock
AnnaBridge	172:65be27845400	2550	* @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock
AnnaBridge	172:65be27845400	2551	*/
AnnaBridge	172:65be27845400	2552	#define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \
AnnaBridge	172:65be27845400	2553	MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, (uint32_t)(__HRTIM1CLKSource__))
AnnaBridge	172:65be27845400	2554
AnnaBridge	172:65be27845400	2555	/** @brief Macro to get the HRTIM1 clock source.
AnnaBridge	172:65be27845400	2556	* @retval The clock source can be one of the following values:
AnnaBridge	172:65be27845400	2557	* @arg @ref RCC_HRTIM1CLK_TIMCLK Timers clock selected as HRTIM1 prescaler clock
AnnaBridge	172:65be27845400	2558	* @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock
AnnaBridge	172:65be27845400	2559	*/
AnnaBridge	172:65be27845400	2560	#define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL)))
AnnaBridge	172:65be27845400	2561
AnnaBridge	172:65be27845400	2562	/** @brief Macro to configure the Timers clocks prescalers
AnnaBridge	172:65be27845400	2563	* @param __PRESC__ : specifies the Timers clocks prescalers selection
AnnaBridge	172:65be27845400	2564	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2565	* @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
AnnaBridge	172:65be27845400	2566	* equal to rcc_hclk1 if D2PPREx is corresponding to division by 1 or 2,
AnnaBridge	172:65be27845400	2567	* else it is equal to 2 x Frcc_pclkx_d2 (default after reset)
AnnaBridge	172:65be27845400	2568	* @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
AnnaBridge	172:65be27845400	2569	* equal to rcc_hclk1 if D2PPREx is corresponding to division by 1, 2 or 4,
AnnaBridge	172:65be27845400	2570	* else it is equal to 4 x Frcc_pclkx_d2
AnnaBridge	172:65be27845400	2571	*/
AnnaBridge	172:65be27845400	2572	#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->CFGR &= ~(RCC_CFGR_TIMPRE);\
AnnaBridge	172:65be27845400	2573	RCC->CFGR \|= (__PRESC__); \
AnnaBridge	172:65be27845400	2574	}while(0)
AnnaBridge	172:65be27845400	2575
AnnaBridge	172:65be27845400	2576	/**
AnnaBridge	172:65be27845400	2577	* @}
AnnaBridge	172:65be27845400	2578	*/
AnnaBridge	172:65be27845400	2579	/**
AnnaBridge	172:65be27845400	2580	* @brief Enable the specified CRS interrupts.
AnnaBridge	172:65be27845400	2581	* @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
AnnaBridge	172:65be27845400	2582	* This parameter can be any combination of the following values:
AnnaBridge	172:65be27845400	2583	* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
AnnaBridge	172:65be27845400	2584	* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
AnnaBridge	172:65be27845400	2585	* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
AnnaBridge	172:65be27845400	2586	* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
AnnaBridge	172:65be27845400	2587	* @retval None
AnnaBridge	172:65be27845400	2588	*/
AnnaBridge	172:65be27845400	2589	#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
AnnaBridge	172:65be27845400	2590
AnnaBridge	172:65be27845400	2591	/**
AnnaBridge	172:65be27845400	2592	* @brief Disable the specified CRS interrupts.
AnnaBridge	172:65be27845400	2593	* @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
AnnaBridge	172:65be27845400	2594	* This parameter can be any combination of the following values:
AnnaBridge	172:65be27845400	2595	* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
AnnaBridge	172:65be27845400	2596	* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
AnnaBridge	172:65be27845400	2597	* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
AnnaBridge	172:65be27845400	2598	* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
AnnaBridge	172:65be27845400	2599	* @retval None
AnnaBridge	172:65be27845400	2600	*/
AnnaBridge	172:65be27845400	2601	#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
AnnaBridge	172:65be27845400	2602
AnnaBridge	172:65be27845400	2603	/** @brief Check whether the CRS interrupt has occurred or not.
AnnaBridge	172:65be27845400	2604	* @param __INTERRUPT__ specifies the CRS interrupt source to check.
AnnaBridge	172:65be27845400	2605	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2606	* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
AnnaBridge	172:65be27845400	2607	* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
AnnaBridge	172:65be27845400	2608	* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
AnnaBridge	172:65be27845400	2609	* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
AnnaBridge	172:65be27845400	2610	* @retval The new state of __INTERRUPT__ (SET or RESET).
AnnaBridge	172:65be27845400	2611	*/
AnnaBridge	172:65be27845400	2612	#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)
AnnaBridge	172:65be27845400	2613
AnnaBridge	172:65be27845400	2614	/** @brief Clear the CRS interrupt pending bits
AnnaBridge	172:65be27845400	2615	* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
AnnaBridge	172:65be27845400	2616	* This parameter can be any combination of the following values:
AnnaBridge	172:65be27845400	2617	* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
AnnaBridge	172:65be27845400	2618	* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
AnnaBridge	172:65be27845400	2619	* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
AnnaBridge	172:65be27845400	2620	* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
AnnaBridge	172:65be27845400	2621	* @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt
AnnaBridge	172:65be27845400	2622	* @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt
AnnaBridge	172:65be27845400	2623	* @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt
AnnaBridge	172:65be27845400	2624	*/
AnnaBridge	172:65be27845400	2625	/* CRS IT Error Mask */
AnnaBridge	172:65be27845400	2626	#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF \| RCC_CRS_IT_SYNCERR \| RCC_CRS_IT_SYNCMISS))
AnnaBridge	172:65be27845400	2627
AnnaBridge	172:65be27845400	2628	#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \
AnnaBridge	172:65be27845400	2629	if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \
AnnaBridge	172:65be27845400	2630	{ \
AnnaBridge	172:65be27845400	2631	WRITE_REG(CRS->ICR, CRS_ICR_ERRC \| ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
AnnaBridge	172:65be27845400	2632	} \
AnnaBridge	172:65be27845400	2633	else \
AnnaBridge	172:65be27845400	2634	{ \
AnnaBridge	172:65be27845400	2635	WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
AnnaBridge	172:65be27845400	2636	} \
AnnaBridge	172:65be27845400	2637	} while(0)
AnnaBridge	172:65be27845400	2638
AnnaBridge	172:65be27845400	2639	/**
AnnaBridge	172:65be27845400	2640	* @brief Check whether the specified CRS flag is set or not.
AnnaBridge	172:65be27845400	2641	* @param __FLAG__ specifies the flag to check.
AnnaBridge	172:65be27845400	2642	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2643	* @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
AnnaBridge	172:65be27845400	2644	* @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
AnnaBridge	172:65be27845400	2645	* @arg @ref RCC_CRS_FLAG_ERR Error
AnnaBridge	172:65be27845400	2646	* @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
AnnaBridge	172:65be27845400	2647	* @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
AnnaBridge	172:65be27845400	2648	* @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
AnnaBridge	172:65be27845400	2649	* @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
AnnaBridge	172:65be27845400	2650	* @retval The new state of _FLAG_ (TRUE or FALSE).
AnnaBridge	172:65be27845400	2651	*/
AnnaBridge	172:65be27845400	2652	#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
AnnaBridge	172:65be27845400	2653
AnnaBridge	172:65be27845400	2654	/**
AnnaBridge	172:65be27845400	2655	* @brief Clear the CRS specified FLAG.
AnnaBridge	172:65be27845400	2656	* @param __FLAG__ specifies the flag to clear.
AnnaBridge	172:65be27845400	2657	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2658	* @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
AnnaBridge	172:65be27845400	2659	* @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
AnnaBridge	172:65be27845400	2660	* @arg @ref RCC_CRS_FLAG_ERR Error
AnnaBridge	172:65be27845400	2661	* @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
AnnaBridge	172:65be27845400	2662	* @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
AnnaBridge	172:65be27845400	2663	* @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
AnnaBridge	172:65be27845400	2664	* @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
AnnaBridge	172:65be27845400	2665	* @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
AnnaBridge	172:65be27845400	2666	* @retval None
AnnaBridge	172:65be27845400	2667	*/
AnnaBridge	172:65be27845400	2668
AnnaBridge	172:65be27845400	2669	/* CRS Flag Error Mask */
AnnaBridge	172:65be27845400	2670	#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF \| RCC_CRS_FLAG_SYNCERR \| RCC_CRS_FLAG_SYNCMISS))
AnnaBridge	172:65be27845400	2671
AnnaBridge	172:65be27845400	2672	#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \
AnnaBridge	172:65be27845400	2673	if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \
AnnaBridge	172:65be27845400	2674	{ \
AnnaBridge	172:65be27845400	2675	WRITE_REG(CRS->ICR, CRS_ICR_ERRC \| ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
AnnaBridge	172:65be27845400	2676	} \
AnnaBridge	172:65be27845400	2677	else \
AnnaBridge	172:65be27845400	2678	{ \
AnnaBridge	172:65be27845400	2679	WRITE_REG(CRS->ICR, (__FLAG__)); \
AnnaBridge	172:65be27845400	2680	} \
AnnaBridge	172:65be27845400	2681	} while(0)
AnnaBridge	172:65be27845400	2682
AnnaBridge	172:65be27845400	2683	/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
AnnaBridge	172:65be27845400	2684	* @{
AnnaBridge	172:65be27845400	2685	*/
AnnaBridge	172:65be27845400	2686	/**
AnnaBridge	172:65be27845400	2687	* @brief Enable the oscillator clock for frequency error counter.
AnnaBridge	172:65be27845400	2688	* @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
AnnaBridge	172:65be27845400	2689	* @retval None
AnnaBridge	172:65be27845400	2690	*/
AnnaBridge	172:65be27845400	2691	#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
AnnaBridge	172:65be27845400	2692
AnnaBridge	172:65be27845400	2693	/**
AnnaBridge	172:65be27845400	2694	* @brief Disable the oscillator clock for frequency error counter.
AnnaBridge	172:65be27845400	2695	* @retval None
AnnaBridge	172:65be27845400	2696	*/
AnnaBridge	172:65be27845400	2697	#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
AnnaBridge	172:65be27845400	2698
AnnaBridge	172:65be27845400	2699	/**
AnnaBridge	172:65be27845400	2700	* @brief Enable the automatic hardware adjustment of TRIM bits.
AnnaBridge	172:65be27845400	2701	* @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
AnnaBridge	172:65be27845400	2702	* @retval None
AnnaBridge	172:65be27845400	2703	*/
AnnaBridge	172:65be27845400	2704	#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
AnnaBridge	172:65be27845400	2705
AnnaBridge	172:65be27845400	2706	/**
AnnaBridge	172:65be27845400	2707	* @brief Enable or disable the automatic hardware adjustment of TRIM bits.
AnnaBridge	172:65be27845400	2708	* @retval None
AnnaBridge	172:65be27845400	2709	*/
AnnaBridge	172:65be27845400	2710	#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
AnnaBridge	172:65be27845400	2711
AnnaBridge	172:65be27845400	2712	/**
AnnaBridge	172:65be27845400	2713	* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
AnnaBridge	172:65be27845400	2714	* @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
AnnaBridge	172:65be27845400	2715	* of the synchronization source after pre-scaling. It is then decreased by one in order to
AnnaBridge	172:65be27845400	2716	* reach the expected synchronization on the zero value. The formula is the following:
AnnaBridge	172:65be27845400	2717	* RELOAD = (fTARGET / fSYNC) -1
AnnaBridge	172:65be27845400	2718	* @param __FTARGET__ Target frequency (value in Hz)
AnnaBridge	172:65be27845400	2719	* @param __FSYNC__ Synchronization signal frequency (value in Hz)
AnnaBridge	172:65be27845400	2720	* @retval None
AnnaBridge	172:65be27845400	2721	*/
AnnaBridge	172:65be27845400	2722	#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
AnnaBridge	172:65be27845400	2723
AnnaBridge	172:65be27845400	2724
AnnaBridge	172:65be27845400	2725	/**
AnnaBridge	172:65be27845400	2726	* @}
AnnaBridge	172:65be27845400	2727	*/
AnnaBridge	172:65be27845400	2728
AnnaBridge	172:65be27845400	2729
AnnaBridge	172:65be27845400	2730	/**
AnnaBridge	172:65be27845400	2731	* @}
AnnaBridge	172:65be27845400	2732	*/
AnnaBridge	172:65be27845400	2733
AnnaBridge	172:65be27845400	2734
AnnaBridge	172:65be27845400	2735	/* Exported functions --------------------------------------------------------*/
AnnaBridge	172:65be27845400	2736	/** @addtogroup RCCEx_Exported_Functions_Group1
AnnaBridge	172:65be27845400	2737	* @{
AnnaBridge	172:65be27845400	2738	*/
AnnaBridge	172:65be27845400	2739	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
AnnaBridge	172:65be27845400	2740	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
AnnaBridge	172:65be27845400	2741	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
AnnaBridge	172:65be27845400	2742	uint32_t HAL_RCCEx_GetD1PCLK1Freq(void);
AnnaBridge	172:65be27845400	2743	uint32_t HAL_RCCEx_GetD3PCLK1Freq(void);
AnnaBridge	172:65be27845400	2744	uint32_t HAL_RCCEx_GetD1SysClockFreq(void);
AnnaBridge	172:65be27845400	2745	void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks);
AnnaBridge	172:65be27845400	2746	void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks);
AnnaBridge	172:65be27845400	2747	void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks);
AnnaBridge	172:65be27845400	2748	/**
AnnaBridge	172:65be27845400	2749	* @}
AnnaBridge	172:65be27845400	2750	*/
AnnaBridge	172:65be27845400	2751
AnnaBridge	172:65be27845400	2752	/** @addtogroup RCCEx_Exported_Functions_Group2
AnnaBridge	172:65be27845400	2753	* @{
AnnaBridge	172:65be27845400	2754	*/
AnnaBridge	172:65be27845400	2755	void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);
AnnaBridge	172:65be27845400	2756	void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk);
AnnaBridge	172:65be27845400	2757	void HAL_RCCEx_EnableLSECSS(void);
AnnaBridge	172:65be27845400	2758	void HAL_RCCEx_DisableLSECSS(void);
AnnaBridge	172:65be27845400	2759	void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx);
AnnaBridge	172:65be27845400	2760	/**
AnnaBridge	172:65be27845400	2761	* @}
AnnaBridge	172:65be27845400	2762	*/
AnnaBridge	172:65be27845400	2763
AnnaBridge	172:65be27845400	2764
AnnaBridge	172:65be27845400	2765	/** @addtogroup RCCEx_Exported_Functions_Group3
AnnaBridge	172:65be27845400	2766	* @{
AnnaBridge	172:65be27845400	2767	*/
AnnaBridge	172:65be27845400	2768
AnnaBridge	172:65be27845400	2769	void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
AnnaBridge	172:65be27845400	2770	void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
AnnaBridge	172:65be27845400	2771	void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
AnnaBridge	172:65be27845400	2772	uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
AnnaBridge	172:65be27845400	2773	void HAL_RCCEx_CRS_IRQHandler(void);
AnnaBridge	172:65be27845400	2774	void HAL_RCCEx_CRS_SyncOkCallback(void);
AnnaBridge	172:65be27845400	2775	void HAL_RCCEx_CRS_SyncWarnCallback(void);
AnnaBridge	172:65be27845400	2776	void HAL_RCCEx_CRS_ExpectedSyncCallback(void);
AnnaBridge	172:65be27845400	2777	void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
AnnaBridge	172:65be27845400	2778
AnnaBridge	172:65be27845400	2779	/**
AnnaBridge	172:65be27845400	2780	* @}
AnnaBridge	172:65be27845400	2781	*/
AnnaBridge	172:65be27845400	2782
AnnaBridge	172:65be27845400	2783	/* Private macros ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	2784	/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
AnnaBridge	172:65be27845400	2785	* @{
AnnaBridge	172:65be27845400	2786	*/
AnnaBridge	172:65be27845400	2787	/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
AnnaBridge	172:65be27845400	2788	* @{
AnnaBridge	172:65be27845400	2789	*/
AnnaBridge	172:65be27845400	2790
AnnaBridge	172:65be27845400	2791	#define IS_RCC_PLL2CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL2_DIVP) \|\| \
AnnaBridge	172:65be27845400	2792	((VALUE) == RCC_PLL2_DIVQ) \|\| \
AnnaBridge	172:65be27845400	2793	((VALUE) == RCC_PLL2_DIVR))
AnnaBridge	172:65be27845400	2794
AnnaBridge	172:65be27845400	2795	#define IS_RCC_PLL3CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL3_DIVP) \|\| \
AnnaBridge	172:65be27845400	2796	((VALUE) == RCC_PLL3_DIVQ) \|\| \
AnnaBridge	172:65be27845400	2797	((VALUE) == RCC_PLL3_DIVR))
AnnaBridge	172:65be27845400	2798
AnnaBridge	172:65be27845400	2799	#define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)\|\| \
AnnaBridge	172:65be27845400	2800	((SOURCE) == RCC_USART16CLKSOURCE_PLL2) \|\| \
AnnaBridge	172:65be27845400	2801	((SOURCE) == RCC_USART16CLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	2802	((SOURCE) == RCC_USART16CLKSOURCE_CSI) \|\| \
AnnaBridge	172:65be27845400	2803	((SOURCE) == RCC_USART16CLKSOURCE_LSE) \|\| \
AnnaBridge	172:65be27845400	2804	((SOURCE) == RCC_USART16CLKSOURCE_HSI))
AnnaBridge	172:65be27845400	2805
AnnaBridge	172:65be27845400	2806	#define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)\|\| \
AnnaBridge	172:65be27845400	2807	((SOURCE) == RCC_USART234578CLKSOURCE_PLL2) \|\| \
AnnaBridge	172:65be27845400	2808	((SOURCE) == RCC_USART234578CLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	2809	((SOURCE) == RCC_USART234578CLKSOURCE_CSI) \|\| \
AnnaBridge	172:65be27845400	2810	((SOURCE) == RCC_USART234578CLKSOURCE_LSE) \|\| \
AnnaBridge	172:65be27845400	2811	((SOURCE) == RCC_USART234578CLKSOURCE_HSI))
AnnaBridge	172:65be27845400	2812
AnnaBridge	172:65be27845400	2813	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_D2PCLK2)\|\| \
AnnaBridge	172:65be27845400	2814	((SOURCE) == RCC_USART1CLKSOURCE_PLL2) \|\| \
AnnaBridge	172:65be27845400	2815	((SOURCE) == RCC_USART1CLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	2816	((SOURCE) == RCC_USART1CLKSOURCE_CSI) \|\| \
AnnaBridge	172:65be27845400	2817	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
AnnaBridge	172:65be27845400	2818	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
AnnaBridge	172:65be27845400	2819
AnnaBridge	172:65be27845400	2820	#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_D2PCLK1)\|\| \
AnnaBridge	172:65be27845400	2821	((SOURCE) == RCC_USART2CLKSOURCE_PLL2) \|\| \
AnnaBridge	172:65be27845400	2822	((SOURCE) == RCC_USART2CLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	2823	((SOURCE) == RCC_USART2CLKSOURCE_CSI) \|\| \
AnnaBridge	172:65be27845400	2824	((SOURCE) == RCC_USART2CLKSOURCE_LSE) \|\| \
AnnaBridge	172:65be27845400	2825	((SOURCE) == RCC_USART2CLKSOURCE_HSI))
AnnaBridge	172:65be27845400	2826
AnnaBridge	172:65be27845400	2827	#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_D2PCLK1)\|\| \
AnnaBridge	172:65be27845400	2828	((SOURCE) == RCC_USART3CLKSOURCE_PLL2) \|\| \
AnnaBridge	172:65be27845400	2829	((SOURCE) == RCC_USART3CLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	2830	((SOURCE) == RCC_USART3CLKSOURCE_CSI) \|\| \
AnnaBridge	172:65be27845400	2831	((SOURCE) == RCC_USART3CLKSOURCE_LSE) \|\| \
AnnaBridge	172:65be27845400	2832	((SOURCE) == RCC_USART3CLKSOURCE_HSI))
AnnaBridge	172:65be27845400	2833
AnnaBridge	172:65be27845400	2834	#define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_D2PCLK1) \|\| \
AnnaBridge	172:65be27845400	2835	((SOURCE) == RCC_UART4CLKSOURCE_PLL2) \|\| \
AnnaBridge	172:65be27845400	2836	((SOURCE) == RCC_UART4CLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	2837	((SOURCE) == RCC_UART4CLKSOURCE_CSI) \|\| \
AnnaBridge	172:65be27845400	2838	((SOURCE) == RCC_UART4CLKSOURCE_LSE) \|\| \
AnnaBridge	172:65be27845400	2839	((SOURCE) == RCC_UART4CLKSOURCE_HSI))
AnnaBridge	172:65be27845400	2840
AnnaBridge	172:65be27845400	2841	#define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_D2PCLK1) \|\| \
AnnaBridge	172:65be27845400	2842	((SOURCE) == RCC_UART5CLKSOURCE_PLL2) \|\| \
AnnaBridge	172:65be27845400	2843	((SOURCE) == RCC_UART5CLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	2844	((SOURCE) == RCC_UART5CLKSOURCE_CSI) \|\| \
AnnaBridge	172:65be27845400	2845	((SOURCE) == RCC_UART5CLKSOURCE_LSE) \|\| \
AnnaBridge	172:65be27845400	2846	((SOURCE) == RCC_UART5CLKSOURCE_HSI))
AnnaBridge	172:65be27845400	2847
AnnaBridge	172:65be27845400	2848	#define IS_RCC_USART6CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART6CLKSOURCE_D2PCLK2)\|\| \
AnnaBridge	172:65be27845400	2849	((SOURCE) == RCC_USART6CLKSOURCE_PLL2) \|\| \
AnnaBridge	172:65be27845400	2850	((SOURCE) == RCC_USART6CLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	2851	((SOURCE) == RCC_USART6CLKSOURCE_CSI) \|\| \
AnnaBridge	172:65be27845400	2852	((SOURCE) == RCC_USART6CLKSOURCE_LSE) \|\| \
AnnaBridge	172:65be27845400	2853	((SOURCE) == RCC_USART6CLKSOURCE_HSI))
AnnaBridge	172:65be27845400	2854
AnnaBridge	172:65be27845400	2855	#define IS_RCC_UART7CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART7CLKSOURCE_D2PCLK1)\|\| \
AnnaBridge	172:65be27845400	2856	((SOURCE) == RCC_UART7CLKSOURCE_PLL2) \|\| \
AnnaBridge	172:65be27845400	2857	((SOURCE) == RCC_UART7CLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	2858	((SOURCE) == RCC_UART7CLKSOURCE_CSI) \|\| \
AnnaBridge	172:65be27845400	2859	((SOURCE) == RCC_UART7CLKSOURCE_LSE) \|\| \
AnnaBridge	172:65be27845400	2860	((SOURCE) == RCC_UART7CLKSOURCE_HSI))
AnnaBridge	172:65be27845400	2861
AnnaBridge	172:65be27845400	2862	#define IS_RCC_UART8CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART8CLKSOURCE_D2PCLK1)\|\| \
AnnaBridge	172:65be27845400	2863	((SOURCE) == RCC_UART8CLKSOURCE_PLL2) \|\| \
AnnaBridge	172:65be27845400	2864	((SOURCE) == RCC_UART8CLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	2865	((SOURCE) == RCC_UART8CLKSOURCE_CSI) \|\| \
AnnaBridge	172:65be27845400	2866	((SOURCE) == RCC_UART8CLKSOURCE_LSE) \|\| \
AnnaBridge	172:65be27845400	2867	((SOURCE) == RCC_UART8CLKSOURCE_HSI))
AnnaBridge	172:65be27845400	2868
AnnaBridge	172:65be27845400	2869	#define IS_RCC_LPUART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPUART1CLKSOURCE_D3PCLK1) \|\| \
AnnaBridge	172:65be27845400	2870	((SOURCE) == RCC_LPUART1CLKSOURCE_PLL2) \|\| \
AnnaBridge	172:65be27845400	2871	((SOURCE) == RCC_LPUART1CLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	2872	((SOURCE) == RCC_LPUART1CLKSOURCE_CSI) \|\| \
AnnaBridge	172:65be27845400	2873	((SOURCE) == RCC_LPUART1CLKSOURCE_LSE) \|\| \
AnnaBridge	172:65be27845400	2874	((SOURCE) == RCC_LPUART1CLKSOURCE_HSI))
AnnaBridge	172:65be27845400	2875
AnnaBridge	172:65be27845400	2876	#define IS_RCC_I2C123CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C123CLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	2877	((SOURCE) == RCC_I2C123CLKSOURCE_HSI) \|\| \
AnnaBridge	172:65be27845400	2878	((SOURCE) == RCC_I2C123CLKSOURCE_D2PCLK1)\|\| \
AnnaBridge	172:65be27845400	2879	((SOURCE) == RCC_I2C123CLKSOURCE_CSI))
AnnaBridge	172:65be27845400	2880
AnnaBridge	172:65be27845400	2881	#define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	2882	((SOURCE) == RCC_I2C1CLKSOURCE_HSI) \|\| \
AnnaBridge	172:65be27845400	2883	((SOURCE) == RCC_I2C1CLKSOURCE_D2PCLK1)\|\| \
AnnaBridge	172:65be27845400	2884	((SOURCE) == RCC_I2C1CLKSOURCE_CSI))
AnnaBridge	172:65be27845400	2885
AnnaBridge	172:65be27845400	2886	#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	2887	((SOURCE) == RCC_I2C2CLKSOURCE_HSI) \|\| \
AnnaBridge	172:65be27845400	2888	((SOURCE) == RCC_I2C2CLKSOURCE_D2PCLK1)\|\| \
AnnaBridge	172:65be27845400	2889	((SOURCE) == RCC_I2C2CLKSOURCE_CSI))
AnnaBridge	172:65be27845400	2890
AnnaBridge	172:65be27845400	2891	#define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	2892	((SOURCE) == RCC_I2C3CLKSOURCE_HSI) \|\| \
AnnaBridge	172:65be27845400	2893	((SOURCE) == RCC_I2C3CLKSOURCE_D2PCLK1)\|\| \
AnnaBridge	172:65be27845400	2894	((SOURCE) == RCC_I2C3CLKSOURCE_CSI))
AnnaBridge	172:65be27845400	2895
AnnaBridge	172:65be27845400	2896	#define IS_RCC_I2C4CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C4CLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	2897	((SOURCE) == RCC_I2C4CLKSOURCE_HSI) \|\| \
AnnaBridge	172:65be27845400	2898	((SOURCE) == RCC_I2C4CLKSOURCE_D3PCLK1)\|\| \
AnnaBridge	172:65be27845400	2899	((SOURCE) == RCC_I2C3CLKSOURCE_CSI))
AnnaBridge	172:65be27845400	2900
AnnaBridge	172:65be27845400	2901	#define IS_RCC_RNGCLKSOURCE(SOURCE) (((SOURCE) == RCC_RNGCLKSOURCE_HSI48)\|\| \
AnnaBridge	172:65be27845400	2902	((SOURCE) == RCC_RNGCLKSOURCE_PLL) \|\| \
AnnaBridge	172:65be27845400	2903	((SOURCE) == RCC_RNGCLKSOURCE_LSE) \|\| \
AnnaBridge	172:65be27845400	2904	((SOURCE) == RCC_RNGCLKSOURCE_LSI))
AnnaBridge	172:65be27845400	2905
AnnaBridge	172:65be27845400	2906	#define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_TIMCLK) \|\| \
AnnaBridge	172:65be27845400	2907	((SOURCE) == RCC_HRTIM1CLK_CPUCLK))
AnnaBridge	172:65be27845400	2908
AnnaBridge	172:65be27845400	2909	#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLL) \|\| \
AnnaBridge	172:65be27845400	2910	((SOURCE) == RCC_USBCLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	2911	((SOURCE) == RCC_USBCLKSOURCE_HSI48))
AnnaBridge	172:65be27845400	2912
AnnaBridge	172:65be27845400	2913	#define IS_RCC_SAI1CLK(__SOURCE__) \
AnnaBridge	172:65be27845400	2914	(((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) \|\| \
AnnaBridge	172:65be27845400	2915	((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) \|\| \
AnnaBridge	172:65be27845400	2916	((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	2917	((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP) \|\| \
AnnaBridge	172:65be27845400	2918	((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
AnnaBridge	172:65be27845400	2919
AnnaBridge	172:65be27845400	2920	#define IS_RCC_SAI23CLK(__SOURCE__) \
AnnaBridge	172:65be27845400	2921	(((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL) \|\| \
AnnaBridge	172:65be27845400	2922	((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL2) \|\| \
AnnaBridge	172:65be27845400	2923	((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	2924	((__SOURCE__) == RCC_SAI23CLKSOURCE_CLKP) \|\| \
AnnaBridge	172:65be27845400	2925	((__SOURCE__) == RCC_SAI23CLKSOURCE_PIN))
AnnaBridge	172:65be27845400	2926
AnnaBridge	172:65be27845400	2927	#define IS_RCC_SAI2CLK(__SOURCE__) \
AnnaBridge	172:65be27845400	2928	(((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL) \|\| \
AnnaBridge	172:65be27845400	2929	((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2) \|\| \
AnnaBridge	172:65be27845400	2930	((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	2931	((__SOURCE__) == RCC_SAI2CLKSOURCE_CLKP) \|\| \
AnnaBridge	172:65be27845400	2932	((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN))
AnnaBridge	172:65be27845400	2933
AnnaBridge	172:65be27845400	2934	#define IS_RCC_SAI3CLK(__SOURCE__) \
AnnaBridge	172:65be27845400	2935	(((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL) \|\| \
AnnaBridge	172:65be27845400	2936	((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL2) \|\| \
AnnaBridge	172:65be27845400	2937	((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	2938	((__SOURCE__) == RCC_SAI3CLKSOURCE_CLKP) \|\| \
AnnaBridge	172:65be27845400	2939	((__SOURCE__) == RCC_SAI3CLKSOURCE_PIN))
AnnaBridge	172:65be27845400	2940
AnnaBridge	172:65be27845400	2941	#define IS_RCC_SPI123CLK(__SOURCE__) \
AnnaBridge	172:65be27845400	2942	(((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL) \|\| \
AnnaBridge	172:65be27845400	2943	((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL2) \|\| \
AnnaBridge	172:65be27845400	2944	((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	2945	((__SOURCE__) == RCC_SPI123CLKSOURCE_CLKP) \|\| \
AnnaBridge	172:65be27845400	2946	((__SOURCE__) == RCC_SPI123CLKSOURCE_PIN))
AnnaBridge	172:65be27845400	2947
AnnaBridge	172:65be27845400	2948	#define IS_RCC_SPI1CLK(__SOURCE__) \
AnnaBridge	172:65be27845400	2949	(((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL) \|\| \
AnnaBridge	172:65be27845400	2950	((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2) \|\| \
AnnaBridge	172:65be27845400	2951	((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	2952	((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP) \|\| \
AnnaBridge	172:65be27845400	2953	((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN))
AnnaBridge	172:65be27845400	2954
AnnaBridge	172:65be27845400	2955	#define IS_RCC_SPI2CLK(__SOURCE__) \
AnnaBridge	172:65be27845400	2956	(((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL) \|\| \
AnnaBridge	172:65be27845400	2957	((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL2) \|\| \
AnnaBridge	172:65be27845400	2958	((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	2959	((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP) \|\| \
AnnaBridge	172:65be27845400	2960	((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN))
AnnaBridge	172:65be27845400	2961
AnnaBridge	172:65be27845400	2962	#define IS_RCC_SPI3CLK(__SOURCE__) \
AnnaBridge	172:65be27845400	2963	(((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL) \|\| \
AnnaBridge	172:65be27845400	2964	((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL2) \|\| \
AnnaBridge	172:65be27845400	2965	((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	2966	((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP) \|\| \
AnnaBridge	172:65be27845400	2967	((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN))
AnnaBridge	172:65be27845400	2968
AnnaBridge	172:65be27845400	2969	#define IS_RCC_SPI45CLK(__SOURCE__) \
AnnaBridge	172:65be27845400	2970	(((__SOURCE__) == RCC_SPI45CLKSOURCE_D2PCLK1) \|\| \
AnnaBridge	172:65be27845400	2971	((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL2) \|\| \
AnnaBridge	172:65be27845400	2972	((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	2973	((__SOURCE__) == RCC_SPI45CLKSOURCE_HSI) \|\| \
AnnaBridge	172:65be27845400	2974	((__SOURCE__) == RCC_SPI45CLKSOURCE_CSI) \|\| \
AnnaBridge	172:65be27845400	2975	((__SOURCE__) == RCC_SPI45CLKSOURCE_HSE))
AnnaBridge	172:65be27845400	2976
AnnaBridge	172:65be27845400	2977	#define IS_RCC_SPI4CLK(__SOURCE__) \
AnnaBridge	172:65be27845400	2978	(((__SOURCE__) == RCC_SPI4CLKSOURCE_D2PCLK1) \|\| \
AnnaBridge	172:65be27845400	2979	((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL2) \|\| \
AnnaBridge	172:65be27845400	2980	((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	2981	((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI) \|\| \
AnnaBridge	172:65be27845400	2982	((__SOURCE__) == RCC_SPI4CLKSOURCE_CSI) \|\| \
AnnaBridge	172:65be27845400	2983	((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE))
AnnaBridge	172:65be27845400	2984
AnnaBridge	172:65be27845400	2985	#define IS_RCC_SPI5CLK(__SOURCE__) \
AnnaBridge	172:65be27845400	2986	(((__SOURCE__) == RCC_SPI5CLKSOURCE_D2PCLK1)\|\| \
AnnaBridge	172:65be27845400	2987	((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL2) \|\| \
AnnaBridge	172:65be27845400	2988	((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	2989	((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI) \|\| \
AnnaBridge	172:65be27845400	2990	((__SOURCE__) == RCC_SPI5CLKSOURCE_CSI) \|\| \
AnnaBridge	172:65be27845400	2991	((__SOURCE__) == RCC_SPI5CLKSOURCE_HSE))
AnnaBridge	172:65be27845400	2992
AnnaBridge	172:65be27845400	2993	#define IS_RCC_SPI6CLK(__SOURCE__) \
AnnaBridge	172:65be27845400	2994	(((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) \|\| \
AnnaBridge	172:65be27845400	2995	((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2) \|\| \
AnnaBridge	172:65be27845400	2996	((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	2997	((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI) \|\| \
AnnaBridge	172:65be27845400	2998	((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI) \|\| \
AnnaBridge	172:65be27845400	2999	((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE))
AnnaBridge	172:65be27845400	3000
AnnaBridge	172:65be27845400	3001	#define IS_RCC_SAI4ACLK(__SOURCE__) \
AnnaBridge	172:65be27845400	3002	(((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL) \|\| \
AnnaBridge	172:65be27845400	3003	((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL2) \|\| \
AnnaBridge	172:65be27845400	3004	((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	3005	((__SOURCE__) == RCC_SAI4ACLKSOURCE_CLKP) \|\| \
AnnaBridge	172:65be27845400	3006	((__SOURCE__) == RCC_SAI4ACLKSOURCE_PIN))
AnnaBridge	172:65be27845400	3007
AnnaBridge	172:65be27845400	3008	#define IS_RCC_SAI4BCLK(__SOURCE__) \
AnnaBridge	172:65be27845400	3009	(((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL) \|\| \
AnnaBridge	172:65be27845400	3010	((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL2) \|\| \
AnnaBridge	172:65be27845400	3011	((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	3012	((__SOURCE__) == RCC_SAI4BCLKSOURCE_CLKP) \|\| \
AnnaBridge	172:65be27845400	3013	((__SOURCE__) == RCC_SAI4BCLKSOURCE_PIN))
AnnaBridge	172:65be27845400	3014
AnnaBridge	172:65be27845400	3015	#define IS_RCC_PLL3M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))
AnnaBridge	172:65be27845400	3016	#define IS_RCC_PLL3N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))
AnnaBridge	172:65be27845400	3017	#define IS_RCC_PLL3P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
AnnaBridge	172:65be27845400	3018	#define IS_RCC_PLL3Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
AnnaBridge	172:65be27845400	3019	#define IS_RCC_PLL3R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
AnnaBridge	172:65be27845400	3020
AnnaBridge	172:65be27845400	3021	#define IS_RCC_PLL2M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))
AnnaBridge	172:65be27845400	3022	#define IS_RCC_PLL2N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))
AnnaBridge	172:65be27845400	3023	#define IS_RCC_PLL2P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
AnnaBridge	172:65be27845400	3024	#define IS_RCC_PLL2Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
AnnaBridge	172:65be27845400	3025	#define IS_RCC_PLL2R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))
AnnaBridge	172:65be27845400	3026
AnnaBridge	172:65be27845400	3027	#define IS_RCC_PLL2RGE_VALUE(VALUE) (((VALUE) == RCC_PLL2VCIRANGE_0) \|\| \
AnnaBridge	172:65be27845400	3028	((VALUE) == RCC_PLL2VCIRANGE_1) \|\| \
AnnaBridge	172:65be27845400	3029	((VALUE) == RCC_PLL2VCIRANGE_2) \|\| \
AnnaBridge	172:65be27845400	3030	((VALUE) == RCC_PLL2VCIRANGE_3))
AnnaBridge	172:65be27845400	3031
AnnaBridge	172:65be27845400	3032	#define IS_RCC_PLL3RGE_VALUE(VALUE) (((VALUE) == RCC_PLL3VCIRANGE_0) \|\| \
AnnaBridge	172:65be27845400	3033	((VALUE) == RCC_PLL3VCIRANGE_1) \|\| \
AnnaBridge	172:65be27845400	3034	((VALUE) == RCC_PLL3VCIRANGE_2) \|\| \
AnnaBridge	172:65be27845400	3035	((VALUE) == RCC_PLL3VCIRANGE_3))
AnnaBridge	172:65be27845400	3036
AnnaBridge	172:65be27845400	3037	#define IS_RCC_PLL2VCO_VALUE(VALUE) (((VALUE) == RCC_PLL2VCOWIDE) \|\| \
AnnaBridge	172:65be27845400	3038	((VALUE) == RCC_PLL2VCOMEDIUM))
AnnaBridge	172:65be27845400	3039
AnnaBridge	172:65be27845400	3040	#define IS_RCC_PLL3VCO_VALUE(VALUE) (((VALUE) == RCC_PLL3VCOWIDE) \|\| \
AnnaBridge	172:65be27845400	3041	((VALUE) == RCC_PLL3VCOMEDIUM))
AnnaBridge	172:65be27845400	3042
AnnaBridge	172:65be27845400	3043	#define IS_RCC_PLLFRACN_VALUE(VALUE) ((VALUE) <=8191U)
AnnaBridge	172:65be27845400	3044
AnnaBridge	172:65be27845400	3045	#define IS_RCC_LPTIM1CLK(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_D2PCLK1)\|\| \
AnnaBridge	172:65be27845400	3046	((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL2) \|\| \
AnnaBridge	172:65be27845400	3047	((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	3048	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE) \|\| \
AnnaBridge	172:65be27845400	3049	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) \|\| \
AnnaBridge	172:65be27845400	3050	((SOURCE) == RCC_LPTIM1CLKSOURCE_CLKP))
AnnaBridge	172:65be27845400	3051
AnnaBridge	172:65be27845400	3052	#define IS_RCC_LPTIM2CLK(SOURCE) (((SOURCE) == RCC_LPTIM2CLKSOURCE_D3PCLK1)\|\| \
AnnaBridge	172:65be27845400	3053	((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL2) \|\| \
AnnaBridge	172:65be27845400	3054	((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	3055	((SOURCE) == RCC_LPTIM2CLKSOURCE_LSE) \|\| \
AnnaBridge	172:65be27845400	3056	((SOURCE) == RCC_LPTIM2CLKSOURCE_LSI) \|\| \
AnnaBridge	172:65be27845400	3057	((SOURCE) == RCC_LPTIM2CLKSOURCE_CLKP))
AnnaBridge	172:65be27845400	3058
AnnaBridge	172:65be27845400	3059	#define IS_RCC_LPTIM345CLK(SOURCE) (((SOURCE) == RCC_LPTIM345CLKSOURCE_D3PCLK1)\|\| \
AnnaBridge	172:65be27845400	3060	((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL2) \|\| \
AnnaBridge	172:65be27845400	3061	((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	3062	((SOURCE) == RCC_LPTIM345CLKSOURCE_LSE) \|\| \
AnnaBridge	172:65be27845400	3063	((SOURCE) == RCC_LPTIM345CLKSOURCE_LSI) \|\| \
AnnaBridge	172:65be27845400	3064	((SOURCE) == RCC_LPTIM345CLKSOURCE_CLKP))
AnnaBridge	172:65be27845400	3065
AnnaBridge	172:65be27845400	3066	#define IS_RCC_LPTIM3CLK(SOURCE) (((SOURCE) == RCC_LPTIM3CLKSOURCE_D3PCLK1)\|\| \
AnnaBridge	172:65be27845400	3067	((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL2) \|\| \
AnnaBridge	172:65be27845400	3068	((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	3069	((SOURCE) == RCC_LPTIM3CLKSOURCE_LSE) \|\| \
AnnaBridge	172:65be27845400	3070	((SOURCE) == RCC_LPTIM3CLKSOURCE_LSI) \|\| \
AnnaBridge	172:65be27845400	3071	((SOURCE) == RCC_LPTIM3CLKSOURCE_CLKP))
AnnaBridge	172:65be27845400	3072
AnnaBridge	172:65be27845400	3073	#define IS_RCC_LPTIM4CLK(SOURCE) (((SOURCE) == RCC_LPTIM4CLKSOURCE_D3PCLK1)\|\| \
AnnaBridge	172:65be27845400	3074	((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL2) \|\| \
AnnaBridge	172:65be27845400	3075	((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	3076	((SOURCE) == RCC_LPTIM4CLKSOURCE_LSE) \|\| \
AnnaBridge	172:65be27845400	3077	((SOURCE) == RCC_LPTIM4CLKSOURCE_LSI) \|\| \
AnnaBridge	172:65be27845400	3078	((SOURCE) == RCC_LPTIM4CLKSOURCE_CLKP))
AnnaBridge	172:65be27845400	3079
AnnaBridge	172:65be27845400	3080	#define IS_RCC_LPTIM5CLK(SOURCE) (((SOURCE) == RCC_LPTIM5CLKSOURCE_D3PCLK1)\|\| \
AnnaBridge	172:65be27845400	3081	((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL2) \|\| \
AnnaBridge	172:65be27845400	3082	((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	3083	((SOURCE) == RCC_LPTIM5CLKSOURCE_LSE) \|\| \
AnnaBridge	172:65be27845400	3084	((SOURCE) == RCC_LPTIM5CLKSOURCE_LSI) \|\| \
AnnaBridge	172:65be27845400	3085	((SOURCE) == RCC_LPTIM5CLKSOURCE_CLKP))
AnnaBridge	172:65be27845400	3086
AnnaBridge	172:65be27845400	3087	#define IS_RCC_QSPICLK(__SOURCE__) \
AnnaBridge	172:65be27845400	3088	(((__SOURCE__) == RCC_QSPICLKSOURCE_D1HCLK) \|\| \
AnnaBridge	172:65be27845400	3089	((__SOURCE__) == RCC_QSPICLKSOURCE_PLL) \|\| \
AnnaBridge	172:65be27845400	3090	((__SOURCE__) == RCC_QSPICLKSOURCE_PLL2) \|\| \
AnnaBridge	172:65be27845400	3091	((__SOURCE__) == RCC_QSPICLKSOURCE_CLKP))
AnnaBridge	172:65be27845400	3092
AnnaBridge	172:65be27845400	3093	#define IS_RCC_FMCCLK(__SOURCE__) \
AnnaBridge	172:65be27845400	3094	(((__SOURCE__) == RCC_FMCCLKSOURCE_D1HCLK) \|\| \
AnnaBridge	172:65be27845400	3095	((__SOURCE__) == RCC_FMCCLKSOURCE_PLL) \|\| \
AnnaBridge	172:65be27845400	3096	((__SOURCE__) == RCC_FMCCLKSOURCE_PLL2) \|\| \
AnnaBridge	172:65be27845400	3097	((__SOURCE__) == RCC_FMCCLKSOURCE_CLKP))
AnnaBridge	172:65be27845400	3098
AnnaBridge	172:65be27845400	3099	#if defined(FDCAN1) \|\| defined(FDCAN2)
AnnaBridge	172:65be27845400	3100	#define IS_RCC_FDCANCLK(__SOURCE__) \
AnnaBridge	172:65be27845400	3101	(((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) \|\| \
AnnaBridge	172:65be27845400	3102	((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL) \|\| \
AnnaBridge	172:65be27845400	3103	((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL2))
AnnaBridge	172:65be27845400	3104	#endif /FDCAN1 \|\| FDCAN2/
AnnaBridge	172:65be27845400	3105
AnnaBridge	172:65be27845400	3106	#define IS_RCC_SDMMC(__SOURCE__) \
AnnaBridge	172:65be27845400	3107	(((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL) \|\| \
AnnaBridge	172:65be27845400	3108	((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL2))
AnnaBridge	172:65be27845400	3109
AnnaBridge	172:65be27845400	3110	#define IS_RCC_ADCCLKSOURCE(SOURCE) (((SOURCE) == RCC_ADCCLKSOURCE_PLL2) \|\| \
AnnaBridge	172:65be27845400	3111	((SOURCE) == RCC_ADCCLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	3112	((SOURCE) == RCC_ADCCLKSOURCE_CLKP))
AnnaBridge	172:65be27845400	3113
AnnaBridge	172:65be27845400	3114	#define IS_RCC_SWPMI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SWPMI1CLKSOURCE_D2PCLK1) \|\| \
AnnaBridge	172:65be27845400	3115	((SOURCE) == RCC_SWPMI1CLKSOURCE_HSI))
AnnaBridge	172:65be27845400	3116
AnnaBridge	172:65be27845400	3117	#define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_D2PCLK1) \|\| \
AnnaBridge	172:65be27845400	3118	((SOURCE) == RCC_DFSDM1CLKSOURCE_SYS))
AnnaBridge	172:65be27845400	3119
AnnaBridge	172:65be27845400	3120	#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE)(((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL) \|\| \
AnnaBridge	172:65be27845400	3121	((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL2) \|\| \
AnnaBridge	172:65be27845400	3122	((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL3) \|\| \
AnnaBridge	172:65be27845400	3123	((SOURCE) == RCC_SPDIFRXCLKSOURCE_HSI))
AnnaBridge	172:65be27845400	3124
AnnaBridge	172:65be27845400	3125	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_LSE) \|\| \
AnnaBridge	172:65be27845400	3126	((SOURCE) == RCC_CECCLKSOURCE_LSI) \|\| \
AnnaBridge	172:65be27845400	3127	((SOURCE) == RCC_CECCLKSOURCE_CSI))
AnnaBridge	172:65be27845400	3128
AnnaBridge	172:65be27845400	3129	#define IS_RCC_CLKPSOURCE(SOURCE) (((SOURCE) == RCC_CLKPSOURCE_HSI) \|\| \
AnnaBridge	172:65be27845400	3130	((SOURCE) == RCC_CLKPSOURCE_CSI) \|\| \
AnnaBridge	172:65be27845400	3131	((SOURCE) == RCC_CLKPSOURCE_HSE))
AnnaBridge	172:65be27845400	3132	#define IS_RCC_TIMPRES(VALUE) \
AnnaBridge	172:65be27845400	3133	(((VALUE) == RCC_TIMPRES_DESACTIVATED) \|\| \
AnnaBridge	172:65be27845400	3134	((VALUE) == RCC_TIMPRES_ACTIVATED))
AnnaBridge	172:65be27845400	3135
AnnaBridge	172:65be27845400	3136
AnnaBridge	172:65be27845400	3137	#define IS_RCC_SCOPE_WWDG(WWDG) ((WWDG) == RCC_WWDG1)
AnnaBridge	172:65be27845400	3138
AnnaBridge	172:65be27845400	3139
AnnaBridge	172:65be27845400	3140	#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB2) \|\| \
AnnaBridge	172:65be27845400	3141	((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) \|\| \
AnnaBridge	172:65be27845400	3142	((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB1))
AnnaBridge	172:65be27845400	3143
AnnaBridge	172:65be27845400	3144	#define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) \|\| ((__DIV__) == RCC_CRS_SYNC_DIV2) \|\| \
AnnaBridge	172:65be27845400	3145	((__DIV__) == RCC_CRS_SYNC_DIV4) \|\| ((__DIV__) == RCC_CRS_SYNC_DIV8) \|\| \
AnnaBridge	172:65be27845400	3146	((__DIV__) == RCC_CRS_SYNC_DIV16) \|\| ((__DIV__) == RCC_CRS_SYNC_DIV32) \|\| \
AnnaBridge	172:65be27845400	3147	((__DIV__) == RCC_CRS_SYNC_DIV64) \|\| ((__DIV__) == RCC_CRS_SYNC_DIV128))
AnnaBridge	172:65be27845400	3148
AnnaBridge	172:65be27845400	3149	#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) \|\| \
AnnaBridge	172:65be27845400	3150	((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
AnnaBridge	172:65be27845400	3151
AnnaBridge	172:65be27845400	3152	#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))
AnnaBridge	172:65be27845400	3153
AnnaBridge	172:65be27845400	3154	#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))
AnnaBridge	172:65be27845400	3155
AnnaBridge	172:65be27845400	3156	#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
AnnaBridge	172:65be27845400	3157
AnnaBridge	172:65be27845400	3158	#define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) \|\| \
AnnaBridge	172:65be27845400	3159	((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
AnnaBridge	172:65be27845400	3160	/**
AnnaBridge	172:65be27845400	3161	* @}
AnnaBridge	172:65be27845400	3162	*/
AnnaBridge	172:65be27845400	3163
AnnaBridge	172:65be27845400	3164	/**
AnnaBridge	172:65be27845400	3165	* @}
AnnaBridge	172:65be27845400	3166	*/
AnnaBridge	172:65be27845400	3167	/**
AnnaBridge	172:65be27845400	3168	* @}
AnnaBridge	172:65be27845400	3169	*/
AnnaBridge	172:65be27845400	3170
AnnaBridge	172:65be27845400	3171	/**
AnnaBridge	172:65be27845400	3172	* @}
AnnaBridge	172:65be27845400	3173	*/
AnnaBridge	172:65be27845400	3174
AnnaBridge	172:65be27845400	3175	#ifdef __cplusplus
AnnaBridge	172:65be27845400	3176	}
AnnaBridge	172:65be27845400	3177	#endif
AnnaBridge	172:65be27845400	3178
AnnaBridge	172:65be27845400	3179	#endif /* STM32H7xx_HAL_RCC_EX_H */
AnnaBridge	172:65be27845400	3180
AnnaBridge	172:65be27845400	3181	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/