mbed official
The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.
Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more
mbed 2
This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.
TARGET_NUCLEO_H743ZI/TOOLCHAIN_ARM_MICRO/stm32h7xx_hal_pwr_ex.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 172:65be27845400 | 1 | /** |
| AnnaBridge | 172:65be27845400 | 2 | ****************************************************************************** |
| AnnaBridge | 172:65be27845400 | 3 | * @file stm32h7xx_hal_pwr_ex.h |
| AnnaBridge | 172:65be27845400 | 4 | * @author MCD Application Team |
| AnnaBridge | 172:65be27845400 | 5 | * @brief Header file of PWR HAL Extension module. |
| AnnaBridge | 172:65be27845400 | 6 | ****************************************************************************** |
| AnnaBridge | 172:65be27845400 | 7 | * @attention |
| AnnaBridge | 172:65be27845400 | 8 | * |
| AnnaBridge | 172:65be27845400 | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics. |
| AnnaBridge | 172:65be27845400 | 10 | * All rights reserved.</center></h2> |
| AnnaBridge | 172:65be27845400 | 11 | * |
| AnnaBridge | 172:65be27845400 | 12 | * This software component is licensed by ST under BSD 3-Clause license, |
| AnnaBridge | 172:65be27845400 | 13 | * the "License"; You may not use this file except in compliance with the |
| AnnaBridge | 172:65be27845400 | 14 | * License. You may obtain a copy of the License at: |
| AnnaBridge | 172:65be27845400 | 15 | * opensource.org/licenses/BSD-3-Clause |
| AnnaBridge | 172:65be27845400 | 16 | * |
| AnnaBridge | 172:65be27845400 | 17 | ****************************************************************************** |
| AnnaBridge | 172:65be27845400 | 18 | */ |
| AnnaBridge | 172:65be27845400 | 19 | |
| AnnaBridge | 172:65be27845400 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 21 | #ifndef STM32H7xx_HAL_PWR_EX_H |
| AnnaBridge | 172:65be27845400 | 22 | #define STM32H7xx_HAL_PWR_EX_H |
| AnnaBridge | 172:65be27845400 | 23 | |
| AnnaBridge | 172:65be27845400 | 24 | #ifdef __cplusplus |
| AnnaBridge | 172:65be27845400 | 25 | extern "C" { |
| AnnaBridge | 172:65be27845400 | 26 | #endif |
| AnnaBridge | 172:65be27845400 | 27 | |
| AnnaBridge | 172:65be27845400 | 28 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 29 | #include "stm32h7xx_hal_def.h" |
| AnnaBridge | 172:65be27845400 | 30 | |
| AnnaBridge | 172:65be27845400 | 31 | /** @addtogroup STM32H7xx_HAL_Driver |
| AnnaBridge | 172:65be27845400 | 32 | * @{ |
| AnnaBridge | 172:65be27845400 | 33 | */ |
| AnnaBridge | 172:65be27845400 | 34 | |
| AnnaBridge | 172:65be27845400 | 35 | /** @addtogroup PWREx |
| AnnaBridge | 172:65be27845400 | 36 | * @{ |
| AnnaBridge | 172:65be27845400 | 37 | */ |
| AnnaBridge | 172:65be27845400 | 38 | |
| AnnaBridge | 172:65be27845400 | 39 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 40 | /** @defgroup PWREx_Exported_Types PWREx Exported Types |
| AnnaBridge | 172:65be27845400 | 41 | * @{ |
| AnnaBridge | 172:65be27845400 | 42 | */ |
| AnnaBridge | 172:65be27845400 | 43 | /** |
| AnnaBridge | 172:65be27845400 | 44 | * @brief PWREx AVD configuration structure definition |
| AnnaBridge | 172:65be27845400 | 45 | */ |
| AnnaBridge | 172:65be27845400 | 46 | typedef struct |
| AnnaBridge | 172:65be27845400 | 47 | { |
| AnnaBridge | 172:65be27845400 | 48 | uint32_t AVDLevel; /*!< AVDLevel: Specifies the AVD detection level. |
| AnnaBridge | 172:65be27845400 | 49 | This parameter can be a value of @ref PWREx_AVD_detection_level */ |
| AnnaBridge | 172:65be27845400 | 50 | |
| AnnaBridge | 172:65be27845400 | 51 | uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. |
| AnnaBridge | 172:65be27845400 | 52 | This parameter can be a value of @ref PWREx_AVD_Mode */ |
| AnnaBridge | 172:65be27845400 | 53 | }PWREx_AVDTypeDef; |
| AnnaBridge | 172:65be27845400 | 54 | |
| AnnaBridge | 172:65be27845400 | 55 | /** |
| AnnaBridge | 172:65be27845400 | 56 | * @brief PWREx Wakeup pin configuration structure definition |
| AnnaBridge | 172:65be27845400 | 57 | */ |
| AnnaBridge | 172:65be27845400 | 58 | typedef struct |
| AnnaBridge | 172:65be27845400 | 59 | { |
| AnnaBridge | 172:65be27845400 | 60 | uint32_t WakeUpPin; /*!< WakeUpPin: Specifies the Wake-Up pin to be enabled. |
| AnnaBridge | 172:65be27845400 | 61 | This parameter can be a value of @ref PWREx_WakeUp_Pins */ |
| AnnaBridge | 172:65be27845400 | 62 | |
| AnnaBridge | 172:65be27845400 | 63 | uint32_t PinPolarity; /*!< PinPolarity: Specifies the Wake-Up pin polarity. |
| AnnaBridge | 172:65be27845400 | 64 | This parameter can be a value of @ref PWREx_PIN_Polarity */ |
| AnnaBridge | 172:65be27845400 | 65 | |
| AnnaBridge | 172:65be27845400 | 66 | uint32_t PinPull; /*!< PinPull: Specifies the Wake-Up pin pull. |
| AnnaBridge | 172:65be27845400 | 67 | This parameter can be a value of @ref PWREx_PIN_Pull */ |
| AnnaBridge | 172:65be27845400 | 68 | }PWREx_WakeupPinTypeDef; |
| AnnaBridge | 172:65be27845400 | 69 | |
| AnnaBridge | 172:65be27845400 | 70 | /** |
| AnnaBridge | 172:65be27845400 | 71 | * @} |
| AnnaBridge | 172:65be27845400 | 72 | */ |
| AnnaBridge | 172:65be27845400 | 73 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 74 | |
| AnnaBridge | 172:65be27845400 | 75 | /** @defgroup PWREx_Exported_Constants PWREx Exported Constants |
| AnnaBridge | 172:65be27845400 | 76 | * @{ |
| AnnaBridge | 172:65be27845400 | 77 | */ |
| AnnaBridge | 172:65be27845400 | 78 | /** @defgroup PWREx_WakeUp_Pins PWREx Wake-Up Pins |
| AnnaBridge | 172:65be27845400 | 79 | * @{ |
| AnnaBridge | 172:65be27845400 | 80 | */ |
| AnnaBridge | 172:65be27845400 | 81 | #define PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN6 |
| AnnaBridge | 172:65be27845400 | 82 | #define PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN5 |
| AnnaBridge | 172:65be27845400 | 83 | #define PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4 |
| AnnaBridge | 172:65be27845400 | 84 | #define PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3 |
| AnnaBridge | 172:65be27845400 | 85 | #define PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2 |
| AnnaBridge | 172:65be27845400 | 86 | #define PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1 |
| AnnaBridge | 172:65be27845400 | 87 | /* High level and No pull */ |
| AnnaBridge | 172:65be27845400 | 88 | #define PWR_WAKEUP_PIN6_HIGH PWR_WKUPEPR_WKUPEN6 |
| AnnaBridge | 172:65be27845400 | 89 | #define PWR_WAKEUP_PIN5_HIGH PWR_WKUPEPR_WKUPEN5 |
| AnnaBridge | 172:65be27845400 | 90 | #define PWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN4 |
| AnnaBridge | 172:65be27845400 | 91 | #define PWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN3 |
| AnnaBridge | 172:65be27845400 | 92 | #define PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN2 |
| AnnaBridge | 172:65be27845400 | 93 | #define PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN1 |
| AnnaBridge | 172:65be27845400 | 94 | /* Low level and No pull */ |
| AnnaBridge | 172:65be27845400 | 95 | #define PWR_WAKEUP_PIN6_LOW (uint32_t)(PWR_WKUPEPR_WKUPP6 | PWR_WKUPEPR_WKUPEN6) |
| AnnaBridge | 172:65be27845400 | 96 | #define PWR_WAKEUP_PIN5_LOW (uint32_t)(PWR_WKUPEPR_WKUPP5 | PWR_WKUPEPR_WKUPEN5) |
| AnnaBridge | 172:65be27845400 | 97 | #define PWR_WAKEUP_PIN4_LOW (uint32_t)(PWR_WKUPEPR_WKUPP4 | PWR_WKUPEPR_WKUPEN4) |
| AnnaBridge | 172:65be27845400 | 98 | #define PWR_WAKEUP_PIN3_LOW (uint32_t)(PWR_WKUPEPR_WKUPP3 | PWR_WKUPEPR_WKUPEN3) |
| AnnaBridge | 172:65be27845400 | 99 | #define PWR_WAKEUP_PIN2_LOW (uint32_t)(PWR_WKUPEPR_WKUPP2 | PWR_WKUPEPR_WKUPEN2) |
| AnnaBridge | 172:65be27845400 | 100 | #define PWR_WAKEUP_PIN1_LOW (uint32_t)(PWR_WKUPEPR_WKUPP1 | PWR_WKUPEPR_WKUPEN1) |
| AnnaBridge | 172:65be27845400 | 101 | /** |
| AnnaBridge | 172:65be27845400 | 102 | * @} |
| AnnaBridge | 172:65be27845400 | 103 | */ |
| AnnaBridge | 172:65be27845400 | 104 | |
| AnnaBridge | 172:65be27845400 | 105 | /** @defgroup PWREx_PIN_Polarity PWREx Pin Polarity configuration |
| AnnaBridge | 172:65be27845400 | 106 | * @{ |
| AnnaBridge | 172:65be27845400 | 107 | */ |
| AnnaBridge | 172:65be27845400 | 108 | #define PWR_PIN_POLARITY_HIGH ((uint32_t)0x00000000U) |
| AnnaBridge | 172:65be27845400 | 109 | #define PWR_PIN_POLARITY_LOW ((uint32_t)0x00000001U) |
| AnnaBridge | 172:65be27845400 | 110 | /** |
| AnnaBridge | 172:65be27845400 | 111 | * @} |
| AnnaBridge | 172:65be27845400 | 112 | */ |
| AnnaBridge | 172:65be27845400 | 113 | |
| AnnaBridge | 172:65be27845400 | 114 | /** @defgroup PWREx_PIN_Pull PWREx Pin Pull configuration |
| AnnaBridge | 172:65be27845400 | 115 | * @{ |
| AnnaBridge | 172:65be27845400 | 116 | */ |
| AnnaBridge | 172:65be27845400 | 117 | #define PWR_PIN_NO_PULL ((uint32_t)0x00000000U) |
| AnnaBridge | 172:65be27845400 | 118 | #define PWR_PIN_PULL_UP ((uint32_t)0x00000001U) |
| AnnaBridge | 172:65be27845400 | 119 | #define PWR_PIN_PULL_DOWN ((uint32_t)0x00000002U) |
| AnnaBridge | 172:65be27845400 | 120 | /** |
| AnnaBridge | 172:65be27845400 | 121 | * @} |
| AnnaBridge | 172:65be27845400 | 122 | */ |
| AnnaBridge | 172:65be27845400 | 123 | |
| AnnaBridge | 172:65be27845400 | 124 | |
| AnnaBridge | 172:65be27845400 | 125 | /** @defgroup PWREx_Wakeup_Pins_Flags PWREx Wakeup Pins Flags. |
| AnnaBridge | 172:65be27845400 | 126 | * @{ |
| AnnaBridge | 172:65be27845400 | 127 | */ |
| AnnaBridge | 172:65be27845400 | 128 | #define PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1 /*!< Wakeup event on pin 1 */ |
| AnnaBridge | 172:65be27845400 | 129 | #define PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2 /*!< Wakeup event on pin 2 */ |
| AnnaBridge | 172:65be27845400 | 130 | #define PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3 /*!< Wakeup event on pin 3 */ |
| AnnaBridge | 172:65be27845400 | 131 | #define PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4 /*!< Wakeup event on pin 4 */ |
| AnnaBridge | 172:65be27845400 | 132 | #define PWR_WAKEUP_FLAG5 PWR_WKUPFR_WKUPF5 /*!< Wakeup event on pin 5 */ |
| AnnaBridge | 172:65be27845400 | 133 | #define PWR_WAKEUP_FLAG6 PWR_WKUPFR_WKUPF6 /*!< Wakeup event on pin 6 */ |
| AnnaBridge | 172:65be27845400 | 134 | /** |
| AnnaBridge | 172:65be27845400 | 135 | * @} |
| AnnaBridge | 172:65be27845400 | 136 | */ |
| AnnaBridge | 172:65be27845400 | 137 | |
| AnnaBridge | 172:65be27845400 | 138 | /** @defgroup PWREx_Domains PWREx Domains definition |
| AnnaBridge | 172:65be27845400 | 139 | * @{ |
| AnnaBridge | 172:65be27845400 | 140 | */ |
| AnnaBridge | 172:65be27845400 | 141 | #define PWR_D1_DOMAIN ((uint32_t)0x00000000U) |
| AnnaBridge | 172:65be27845400 | 142 | #define PWR_D2_DOMAIN ((uint32_t)0x00000001U) |
| AnnaBridge | 172:65be27845400 | 143 | #define PWR_D3_DOMAIN ((uint32_t)0x00000002U) |
| AnnaBridge | 172:65be27845400 | 144 | /** |
| AnnaBridge | 172:65be27845400 | 145 | * @} |
| AnnaBridge | 172:65be27845400 | 146 | */ |
| AnnaBridge | 172:65be27845400 | 147 | |
| AnnaBridge | 172:65be27845400 | 148 | /** @defgroup PWREx_Domain_Flags PWREx Domain Flags definition |
| AnnaBridge | 172:65be27845400 | 149 | * @{ |
| AnnaBridge | 172:65be27845400 | 150 | */ |
| AnnaBridge | 172:65be27845400 | 151 | #define PWR_CPU_FLAGS ((uint32_t)0x00000000U) |
| AnnaBridge | 172:65be27845400 | 152 | /** |
| AnnaBridge | 172:65be27845400 | 153 | * @} |
| AnnaBridge | 172:65be27845400 | 154 | */ |
| AnnaBridge | 172:65be27845400 | 155 | |
| AnnaBridge | 172:65be27845400 | 156 | /** @defgroup PWREx_D3_State PWREx D3 Domain State |
| AnnaBridge | 172:65be27845400 | 157 | * @{ |
| AnnaBridge | 172:65be27845400 | 158 | */ |
| AnnaBridge | 172:65be27845400 | 159 | #define PWR_D3_DOMAIN_STOP ((uint32_t)0x00000000U) |
| AnnaBridge | 172:65be27845400 | 160 | #define PWR_D3_DOMAIN_RUN ((uint32_t)0x00000800U) |
| AnnaBridge | 172:65be27845400 | 161 | |
| AnnaBridge | 172:65be27845400 | 162 | /** |
| AnnaBridge | 172:65be27845400 | 163 | * @} |
| AnnaBridge | 172:65be27845400 | 164 | */ |
| AnnaBridge | 172:65be27845400 | 165 | |
| AnnaBridge | 172:65be27845400 | 166 | /** @defgroup PWREx_Supply_configuration PWREx Supply configuration |
| AnnaBridge | 172:65be27845400 | 167 | * @{ |
| AnnaBridge | 172:65be27845400 | 168 | */ |
| AnnaBridge | 172:65be27845400 | 169 | #define PWR_LDO_SUPPLY PWR_CR3_LDOEN /*!< Core domains are suppplied from the LDO */ |
| AnnaBridge | 172:65be27845400 | 170 | #define PWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS /*!< the LDO Bypass. The Core domain is supplied from an external source */ |
| AnnaBridge | 172:65be27845400 | 171 | #define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS) |
| AnnaBridge | 172:65be27845400 | 172 | /** |
| AnnaBridge | 172:65be27845400 | 173 | * @} |
| AnnaBridge | 172:65be27845400 | 174 | */ |
| AnnaBridge | 172:65be27845400 | 175 | |
| AnnaBridge | 172:65be27845400 | 176 | |
| AnnaBridge | 172:65be27845400 | 177 | /** @defgroup PWREx_AVD_detection_level PWREx AVD detection level |
| AnnaBridge | 172:65be27845400 | 178 | * @{ |
| AnnaBridge | 172:65be27845400 | 179 | */ |
| AnnaBridge | 172:65be27845400 | 180 | #define PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0 |
| AnnaBridge | 172:65be27845400 | 181 | #define PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1 |
| AnnaBridge | 172:65be27845400 | 182 | #define PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2 |
| AnnaBridge | 172:65be27845400 | 183 | #define PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3 |
| AnnaBridge | 172:65be27845400 | 184 | /** |
| AnnaBridge | 172:65be27845400 | 185 | * @} |
| AnnaBridge | 172:65be27845400 | 186 | */ |
| AnnaBridge | 172:65be27845400 | 187 | |
| AnnaBridge | 172:65be27845400 | 188 | /** @defgroup PWREx_AVD_Mode PWREx AVD Mode |
| AnnaBridge | 172:65be27845400 | 189 | * @{ |
| AnnaBridge | 172:65be27845400 | 190 | */ |
| AnnaBridge | 172:65be27845400 | 191 | #define PWR_AVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Basic mode is used */ |
| AnnaBridge | 172:65be27845400 | 192 | #define PWR_AVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ |
| AnnaBridge | 172:65be27845400 | 193 | #define PWR_AVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ |
| AnnaBridge | 172:65be27845400 | 194 | #define PWR_AVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ |
| AnnaBridge | 172:65be27845400 | 195 | #define PWR_AVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */ |
| AnnaBridge | 172:65be27845400 | 196 | #define PWR_AVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */ |
| AnnaBridge | 172:65be27845400 | 197 | #define PWR_AVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ |
| AnnaBridge | 172:65be27845400 | 198 | /** |
| AnnaBridge | 172:65be27845400 | 199 | * @} |
| AnnaBridge | 172:65be27845400 | 200 | */ |
| AnnaBridge | 172:65be27845400 | 201 | |
| AnnaBridge | 172:65be27845400 | 202 | /** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale |
| AnnaBridge | 172:65be27845400 | 203 | * @{ |
| AnnaBridge | 172:65be27845400 | 204 | */ |
| AnnaBridge | 172:65be27845400 | 205 | #define PWR_REGULATOR_SVOS_SCALE5 (PWR_CR1_SVOS_0) |
| AnnaBridge | 172:65be27845400 | 206 | #define PWR_REGULATOR_SVOS_SCALE4 (PWR_CR1_SVOS_1) |
| AnnaBridge | 172:65be27845400 | 207 | #define PWR_REGULATOR_SVOS_SCALE3 (uint32_t)(PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1) |
| AnnaBridge | 172:65be27845400 | 208 | /** |
| AnnaBridge | 172:65be27845400 | 209 | * @} |
| AnnaBridge | 172:65be27845400 | 210 | */ |
| AnnaBridge | 172:65be27845400 | 211 | |
| AnnaBridge | 172:65be27845400 | 212 | /** @defgroup PWREx_VBAT_Battery_Charging_Resistor PWR battery charging resistor selection |
| AnnaBridge | 172:65be27845400 | 213 | * @{ |
| AnnaBridge | 172:65be27845400 | 214 | */ |
| AnnaBridge | 172:65be27845400 | 215 | #define PWR_BATTERY_CHARGING_RESISTOR_5 ((uint32_t)0x00000000U) /*!< VBAT charging through a 5 kOhms resistor */ |
| AnnaBridge | 172:65be27845400 | 216 | #define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR3_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */ |
| AnnaBridge | 172:65be27845400 | 217 | /** |
| AnnaBridge | 172:65be27845400 | 218 | * @} |
| AnnaBridge | 172:65be27845400 | 219 | */ |
| AnnaBridge | 172:65be27845400 | 220 | |
| AnnaBridge | 172:65be27845400 | 221 | /** @defgroup PWREx_VBAT_Thresholds PWREx VBAT Thresholds |
| AnnaBridge | 172:65be27845400 | 222 | * @{ |
| AnnaBridge | 172:65be27845400 | 223 | */ |
| AnnaBridge | 172:65be27845400 | 224 | #define PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD ((uint32_t)0x00000000U) |
| AnnaBridge | 172:65be27845400 | 225 | #define PWR_VBAT_BELOW_LOW_THRESHOLD PWR_CR2_VBATL |
| AnnaBridge | 172:65be27845400 | 226 | #define PWR_VBAT_ABOVE_HIGH_THRESHOLD PWR_CR2_VBATH |
| AnnaBridge | 172:65be27845400 | 227 | /** |
| AnnaBridge | 172:65be27845400 | 228 | * @} |
| AnnaBridge | 172:65be27845400 | 229 | */ |
| AnnaBridge | 172:65be27845400 | 230 | |
| AnnaBridge | 172:65be27845400 | 231 | /** @defgroup PWREx_TEMP_Thresholds PWREx Temperature Thresholds |
| AnnaBridge | 172:65be27845400 | 232 | * @{ |
| AnnaBridge | 172:65be27845400 | 233 | */ |
| AnnaBridge | 172:65be27845400 | 234 | #define PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD ((uint32_t)0x00000000U) |
| AnnaBridge | 172:65be27845400 | 235 | #define PWR_TEMP_BELOW_LOW_THRESHOLD PWR_CR2_TEMPL |
| AnnaBridge | 172:65be27845400 | 236 | #define PWR_TEMP_ABOVE_HIGH_THRESHOLD PWR_CR2_TEMPH |
| AnnaBridge | 172:65be27845400 | 237 | /** |
| AnnaBridge | 172:65be27845400 | 238 | * @} |
| AnnaBridge | 172:65be27845400 | 239 | */ |
| AnnaBridge | 172:65be27845400 | 240 | /** @defgroup PWREx_AVD_EXTI_Line PWREx AVD EXTI Line 16 |
| AnnaBridge | 172:65be27845400 | 241 | * @{ |
| AnnaBridge | 172:65be27845400 | 242 | */ |
| AnnaBridge | 172:65be27845400 | 243 | #define PWR_EXTI_LINE_AVD ((uint32_t)EXTI_IMR1_IM16) /*!< External interrupt line 16 Connected to the AVD EXTI Line */ |
| AnnaBridge | 172:65be27845400 | 244 | /** |
| AnnaBridge | 172:65be27845400 | 245 | * @} |
| AnnaBridge | 172:65be27845400 | 246 | */ |
| AnnaBridge | 172:65be27845400 | 247 | /** |
| AnnaBridge | 172:65be27845400 | 248 | * @} |
| AnnaBridge | 172:65be27845400 | 249 | */ |
| AnnaBridge | 172:65be27845400 | 250 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 251 | /** @defgroup PWREx_Exported_Macro PWREx Exported Macro |
| AnnaBridge | 172:65be27845400 | 252 | * @{ |
| AnnaBridge | 172:65be27845400 | 253 | */ |
| AnnaBridge | 172:65be27845400 | 254 | |
| AnnaBridge | 172:65be27845400 | 255 | /** |
| AnnaBridge | 172:65be27845400 | 256 | * @brief Enable the AVD EXTI Line 16. |
| AnnaBridge | 172:65be27845400 | 257 | * @retval None. |
| AnnaBridge | 172:65be27845400 | 258 | */ |
| AnnaBridge | 172:65be27845400 | 259 | #define __HAL_PWR_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD) |
| AnnaBridge | 172:65be27845400 | 260 | |
| AnnaBridge | 172:65be27845400 | 261 | /** |
| AnnaBridge | 172:65be27845400 | 262 | * @brief Disable the AVD EXTI Line 16 |
| AnnaBridge | 172:65be27845400 | 263 | * @retval None. |
| AnnaBridge | 172:65be27845400 | 264 | */ |
| AnnaBridge | 172:65be27845400 | 265 | #define __HAL_PWR_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD) |
| AnnaBridge | 172:65be27845400 | 266 | |
| AnnaBridge | 172:65be27845400 | 267 | /** |
| AnnaBridge | 172:65be27845400 | 268 | * @brief Enable event on AVD EXTI Line 16. |
| AnnaBridge | 172:65be27845400 | 269 | * @retval None. |
| AnnaBridge | 172:65be27845400 | 270 | */ |
| AnnaBridge | 172:65be27845400 | 271 | #define __HAL_PWR_AVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD) |
| AnnaBridge | 172:65be27845400 | 272 | |
| AnnaBridge | 172:65be27845400 | 273 | /** |
| AnnaBridge | 172:65be27845400 | 274 | * @brief Disable event on AVD EXTI Line 16. |
| AnnaBridge | 172:65be27845400 | 275 | * @retval None. |
| AnnaBridge | 172:65be27845400 | 276 | */ |
| AnnaBridge | 172:65be27845400 | 277 | #define __HAL_PWR_AVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD) |
| AnnaBridge | 172:65be27845400 | 278 | |
| AnnaBridge | 172:65be27845400 | 279 | /** |
| AnnaBridge | 172:65be27845400 | 280 | * @brief Enable the AVD Extended Interrupt Rising Trigger. |
| AnnaBridge | 172:65be27845400 | 281 | * @retval None. |
| AnnaBridge | 172:65be27845400 | 282 | */ |
| AnnaBridge | 172:65be27845400 | 283 | #define __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD) |
| AnnaBridge | 172:65be27845400 | 284 | |
| AnnaBridge | 172:65be27845400 | 285 | /** |
| AnnaBridge | 172:65be27845400 | 286 | * @brief Disable the AVD Extended Interrupt Rising Trigger. |
| AnnaBridge | 172:65be27845400 | 287 | * @retval None. |
| AnnaBridge | 172:65be27845400 | 288 | */ |
| AnnaBridge | 172:65be27845400 | 289 | #define __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD) |
| AnnaBridge | 172:65be27845400 | 290 | |
| AnnaBridge | 172:65be27845400 | 291 | /** |
| AnnaBridge | 172:65be27845400 | 292 | * @brief Enable the AVD Extended Interrupt Falling Trigger. |
| AnnaBridge | 172:65be27845400 | 293 | * @retval None. |
| AnnaBridge | 172:65be27845400 | 294 | */ |
| AnnaBridge | 172:65be27845400 | 295 | #define __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD) |
| AnnaBridge | 172:65be27845400 | 296 | |
| AnnaBridge | 172:65be27845400 | 297 | |
| AnnaBridge | 172:65be27845400 | 298 | /** |
| AnnaBridge | 172:65be27845400 | 299 | * @brief Disable the AVD Extended Interrupt Falling Trigger. |
| AnnaBridge | 172:65be27845400 | 300 | * @retval None. |
| AnnaBridge | 172:65be27845400 | 301 | */ |
| AnnaBridge | 172:65be27845400 | 302 | #define __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD) |
| AnnaBridge | 172:65be27845400 | 303 | |
| AnnaBridge | 172:65be27845400 | 304 | |
| AnnaBridge | 172:65be27845400 | 305 | /** |
| AnnaBridge | 172:65be27845400 | 306 | * @brief AVD EXTI line configuration: set rising & falling edge trigger. |
| AnnaBridge | 172:65be27845400 | 307 | * @retval None. |
| AnnaBridge | 172:65be27845400 | 308 | */ |
| AnnaBridge | 172:65be27845400 | 309 | #define __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ |
| AnnaBridge | 172:65be27845400 | 310 | __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE(); \ |
| AnnaBridge | 172:65be27845400 | 311 | __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE(); \ |
| AnnaBridge | 172:65be27845400 | 312 | } while(0); |
| AnnaBridge | 172:65be27845400 | 313 | |
| AnnaBridge | 172:65be27845400 | 314 | /** |
| AnnaBridge | 172:65be27845400 | 315 | * @brief Disable the AVD Extended Interrupt Rising & Falling Trigger. |
| AnnaBridge | 172:65be27845400 | 316 | * @retval None. |
| AnnaBridge | 172:65be27845400 | 317 | */ |
| AnnaBridge | 172:65be27845400 | 318 | #define __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ |
| AnnaBridge | 172:65be27845400 | 319 | do { \ |
| AnnaBridge | 172:65be27845400 | 320 | __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE(); \ |
| AnnaBridge | 172:65be27845400 | 321 | __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE(); \ |
| AnnaBridge | 172:65be27845400 | 322 | } while(0); |
| AnnaBridge | 172:65be27845400 | 323 | |
| AnnaBridge | 172:65be27845400 | 324 | /** |
| AnnaBridge | 172:65be27845400 | 325 | * @brief Check whether the specified AVD EXTI interrupt flag is set or not. |
| AnnaBridge | 172:65be27845400 | 326 | * @retval EXTI AVD Line Status. |
| AnnaBridge | 172:65be27845400 | 327 | */ |
| AnnaBridge | 172:65be27845400 | 328 | #define __HAL_PWR_AVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? SET : RESET) |
| AnnaBridge | 172:65be27845400 | 329 | |
| AnnaBridge | 172:65be27845400 | 330 | /** |
| AnnaBridge | 172:65be27845400 | 331 | * @brief Clear the AVD EXTI flag. |
| AnnaBridge | 172:65be27845400 | 332 | * @retval None. |
| AnnaBridge | 172:65be27845400 | 333 | */ |
| AnnaBridge | 172:65be27845400 | 334 | #define __HAL_PWR_AVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) |
| AnnaBridge | 172:65be27845400 | 335 | |
| AnnaBridge | 172:65be27845400 | 336 | /** |
| AnnaBridge | 172:65be27845400 | 337 | * @} |
| AnnaBridge | 172:65be27845400 | 338 | */ |
| AnnaBridge | 172:65be27845400 | 339 | |
| AnnaBridge | 172:65be27845400 | 340 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 341 | /** @addtogroup PWREx_Exported_Functions PWREx Exported Functions |
| AnnaBridge | 172:65be27845400 | 342 | * @{ |
| AnnaBridge | 172:65be27845400 | 343 | */ |
| AnnaBridge | 172:65be27845400 | 344 | |
| AnnaBridge | 172:65be27845400 | 345 | /** @addtogroup PWREx_Exported_Functions_Group1 Power supply control functions |
| AnnaBridge | 172:65be27845400 | 346 | * @{ |
| AnnaBridge | 172:65be27845400 | 347 | */ |
| AnnaBridge | 172:65be27845400 | 348 | /* Power supply control functions */ |
| AnnaBridge | 172:65be27845400 | 349 | HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource); |
| AnnaBridge | 172:65be27845400 | 350 | uint32_t HAL_PWREx_GetSupplyConfig(void); |
| AnnaBridge | 172:65be27845400 | 351 | /* Power volatge scaling functions */ |
| AnnaBridge | 172:65be27845400 | 352 | HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); |
| AnnaBridge | 172:65be27845400 | 353 | uint32_t HAL_PWREx_GetVoltageRange(void); |
| AnnaBridge | 172:65be27845400 | 354 | HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling(uint32_t VoltageScaling); |
| AnnaBridge | 172:65be27845400 | 355 | uint32_t HAL_PWREx_GetStopModeVoltageRange(void); |
| AnnaBridge | 172:65be27845400 | 356 | /** |
| AnnaBridge | 172:65be27845400 | 357 | * @} |
| AnnaBridge | 172:65be27845400 | 358 | */ |
| AnnaBridge | 172:65be27845400 | 359 | |
| AnnaBridge | 172:65be27845400 | 360 | /** @addtogroup PWREx_Exported_Functions_Group2 Low power control functions |
| AnnaBridge | 172:65be27845400 | 361 | * @{ |
| AnnaBridge | 172:65be27845400 | 362 | */ |
| AnnaBridge | 172:65be27845400 | 363 | /* System low power control functions */ |
| AnnaBridge | 172:65be27845400 | 364 | void HAL_PWREx_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain); |
| AnnaBridge | 172:65be27845400 | 365 | void HAL_PWREx_EnterSTANDBYMode(uint32_t Domain); |
| AnnaBridge | 172:65be27845400 | 366 | void HAL_PWREx_ConfigD3Domain(uint32_t D3State); |
| AnnaBridge | 172:65be27845400 | 367 | |
| AnnaBridge | 172:65be27845400 | 368 | /* Clear pending event function */ |
| AnnaBridge | 172:65be27845400 | 369 | void HAL_PWREx_ClearPendingEvent(void); |
| AnnaBridge | 172:65be27845400 | 370 | |
| AnnaBridge | 172:65be27845400 | 371 | /* Flash low power control functions */ |
| AnnaBridge | 172:65be27845400 | 372 | void HAL_PWREx_EnableFlashPowerDown(void); |
| AnnaBridge | 172:65be27845400 | 373 | void HAL_PWREx_DisableFlashPowerDown(void); |
| AnnaBridge | 172:65be27845400 | 374 | /* Wakeup Pins control functions */ |
| AnnaBridge | 172:65be27845400 | 375 | void HAL_PWREx_EnableWakeUpPin(PWREx_WakeupPinTypeDef *sPinParams); |
| AnnaBridge | 172:65be27845400 | 376 | void HAL_PWREx_DisableWakeUpPin(uint32_t WakeUpPin); |
| AnnaBridge | 172:65be27845400 | 377 | uint32_t HAL_PWREx_GetWakeupFlag(uint32_t WakeUpFlag); |
| AnnaBridge | 172:65be27845400 | 378 | HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag(uint32_t WakeUpFlag); |
| AnnaBridge | 172:65be27845400 | 379 | |
| AnnaBridge | 172:65be27845400 | 380 | /* Power Wakeup PIN IRQ Handler */ |
| AnnaBridge | 172:65be27845400 | 381 | void HAL_PWREx_WAKEUP_PIN_IRQHandler(void); |
| AnnaBridge | 172:65be27845400 | 382 | void HAL_PWREx_WKUP1_Callback(void); |
| AnnaBridge | 172:65be27845400 | 383 | void HAL_PWREx_WKUP2_Callback(void); |
| AnnaBridge | 172:65be27845400 | 384 | void HAL_PWREx_WKUP3_Callback(void); |
| AnnaBridge | 172:65be27845400 | 385 | void HAL_PWREx_WKUP4_Callback(void); |
| AnnaBridge | 172:65be27845400 | 386 | void HAL_PWREx_WKUP5_Callback(void); |
| AnnaBridge | 172:65be27845400 | 387 | void HAL_PWREx_WKUP6_Callback(void); |
| AnnaBridge | 172:65be27845400 | 388 | /** |
| AnnaBridge | 172:65be27845400 | 389 | * @} |
| AnnaBridge | 172:65be27845400 | 390 | */ |
| AnnaBridge | 172:65be27845400 | 391 | |
| AnnaBridge | 172:65be27845400 | 392 | /** @addtogroup PWREx_Exported_Functions_Group3 Peripherals control functions |
| AnnaBridge | 172:65be27845400 | 393 | * @{ |
| AnnaBridge | 172:65be27845400 | 394 | */ |
| AnnaBridge | 172:65be27845400 | 395 | /* Backup regulator control functions */ |
| AnnaBridge | 172:65be27845400 | 396 | HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void); |
| AnnaBridge | 172:65be27845400 | 397 | HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void); |
| AnnaBridge | 172:65be27845400 | 398 | |
| AnnaBridge | 172:65be27845400 | 399 | /* USB regulator control functions */ |
| AnnaBridge | 172:65be27845400 | 400 | HAL_StatusTypeDef HAL_PWREx_EnableUSBReg(void); |
| AnnaBridge | 172:65be27845400 | 401 | HAL_StatusTypeDef HAL_PWREx_DisableUSBReg(void); |
| AnnaBridge | 172:65be27845400 | 402 | void HAL_PWREx_EnableUSBVoltageDetector(void); |
| AnnaBridge | 172:65be27845400 | 403 | void HAL_PWREx_DisableUSBVoltageDetector(void); |
| AnnaBridge | 172:65be27845400 | 404 | |
| AnnaBridge | 172:65be27845400 | 405 | /* Battery control functions */ |
| AnnaBridge | 172:65be27845400 | 406 | void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue); |
| AnnaBridge | 172:65be27845400 | 407 | void HAL_PWREx_DisableBatteryCharging(void); |
| AnnaBridge | 172:65be27845400 | 408 | /** |
| AnnaBridge | 172:65be27845400 | 409 | * @} |
| AnnaBridge | 172:65be27845400 | 410 | */ |
| AnnaBridge | 172:65be27845400 | 411 | |
| AnnaBridge | 172:65be27845400 | 412 | /** @addtogroup PWREx_Exported_Functions_Group4 Power Monitoring functions |
| AnnaBridge | 172:65be27845400 | 413 | * @{ |
| AnnaBridge | 172:65be27845400 | 414 | */ |
| AnnaBridge | 172:65be27845400 | 415 | /* Power VBAT/Temperature monitoring functions */ |
| AnnaBridge | 172:65be27845400 | 416 | void HAL_PWREx_EnableMonitoring(void); |
| AnnaBridge | 172:65be27845400 | 417 | void HAL_PWREx_DisableMonitoring(void); |
| AnnaBridge | 172:65be27845400 | 418 | uint32_t HAL_PWREx_GetTemperatureLevel(void); |
| AnnaBridge | 172:65be27845400 | 419 | uint32_t HAL_PWREx_GetVBATLevel(void); |
| AnnaBridge | 172:65be27845400 | 420 | |
| AnnaBridge | 172:65be27845400 | 421 | /* Power AVD configuration functions */ |
| AnnaBridge | 172:65be27845400 | 422 | void HAL_PWREx_ConfigAVD(PWREx_AVDTypeDef *sConfigAVD); |
| AnnaBridge | 172:65be27845400 | 423 | void HAL_PWREx_EnableAVD(void); |
| AnnaBridge | 172:65be27845400 | 424 | void HAL_PWREx_DisableAVD(void); |
| AnnaBridge | 172:65be27845400 | 425 | |
| AnnaBridge | 172:65be27845400 | 426 | /* Power PVD/AVD IRQ Handler */ |
| AnnaBridge | 172:65be27845400 | 427 | void HAL_PWREx_PVD_AVD_IRQHandler(void); |
| AnnaBridge | 172:65be27845400 | 428 | void HAL_PWREx_AVDCallback(void); |
| AnnaBridge | 172:65be27845400 | 429 | |
| AnnaBridge | 172:65be27845400 | 430 | /** |
| AnnaBridge | 172:65be27845400 | 431 | * @} |
| AnnaBridge | 172:65be27845400 | 432 | */ |
| AnnaBridge | 172:65be27845400 | 433 | |
| AnnaBridge | 172:65be27845400 | 434 | /** |
| AnnaBridge | 172:65be27845400 | 435 | * @} |
| AnnaBridge | 172:65be27845400 | 436 | */ |
| AnnaBridge | 172:65be27845400 | 437 | /* Private types -------------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 438 | /* Private variables ---------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 439 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 440 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 441 | /** @defgroup PWREx_Private_Macros PWREx Private Macros |
| AnnaBridge | 172:65be27845400 | 442 | * @{ |
| AnnaBridge | 172:65be27845400 | 443 | */ |
| AnnaBridge | 172:65be27845400 | 444 | |
| AnnaBridge | 172:65be27845400 | 445 | /** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters |
| AnnaBridge | 172:65be27845400 | 446 | * @{ |
| AnnaBridge | 172:65be27845400 | 447 | */ |
| AnnaBridge | 172:65be27845400 | 448 | #define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) || \ |
| AnnaBridge | 172:65be27845400 | 449 | ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY)) |
| AnnaBridge | 172:65be27845400 | 450 | |
| AnnaBridge | 172:65be27845400 | 451 | #define IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE3) || \ |
| AnnaBridge | 172:65be27845400 | 452 | ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE4) || \ |
| AnnaBridge | 172:65be27845400 | 453 | ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE5)) |
| AnnaBridge | 172:65be27845400 | 454 | |
| AnnaBridge | 172:65be27845400 | 455 | #define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) || \ |
| AnnaBridge | 172:65be27845400 | 456 | ((DOMAIN) == PWR_D2_DOMAIN) || \ |
| AnnaBridge | 172:65be27845400 | 457 | ((DOMAIN) == PWR_D3_DOMAIN)) |
| AnnaBridge | 172:65be27845400 | 458 | |
| AnnaBridge | 172:65be27845400 | 459 | #define IS_D3_STATE(STATE) (((STATE) == PWR_D3_DOMAIN_STOP) || ((STATE) == PWR_D3_DOMAIN_RUN)) |
| AnnaBridge | 172:65be27845400 | 460 | |
| AnnaBridge | 172:65be27845400 | 461 | #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ |
| AnnaBridge | 172:65be27845400 | 462 | ((PIN) == PWR_WAKEUP_PIN2) || \ |
| AnnaBridge | 172:65be27845400 | 463 | ((PIN) == PWR_WAKEUP_PIN3) || \ |
| AnnaBridge | 172:65be27845400 | 464 | ((PIN) == PWR_WAKEUP_PIN4) || \ |
| AnnaBridge | 172:65be27845400 | 465 | ((PIN) == PWR_WAKEUP_PIN5) || \ |
| AnnaBridge | 172:65be27845400 | 466 | ((PIN) == PWR_WAKEUP_PIN6) || \ |
| AnnaBridge | 172:65be27845400 | 467 | ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \ |
| AnnaBridge | 172:65be27845400 | 468 | ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \ |
| AnnaBridge | 172:65be27845400 | 469 | ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \ |
| AnnaBridge | 172:65be27845400 | 470 | ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \ |
| AnnaBridge | 172:65be27845400 | 471 | ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \ |
| AnnaBridge | 172:65be27845400 | 472 | ((PIN) == PWR_WAKEUP_PIN6_HIGH) || \ |
| AnnaBridge | 172:65be27845400 | 473 | ((PIN) == PWR_WAKEUP_PIN1_LOW) || \ |
| AnnaBridge | 172:65be27845400 | 474 | ((PIN) == PWR_WAKEUP_PIN2_LOW) || \ |
| AnnaBridge | 172:65be27845400 | 475 | ((PIN) == PWR_WAKEUP_PIN3_LOW) || \ |
| AnnaBridge | 172:65be27845400 | 476 | ((PIN) == PWR_WAKEUP_PIN4_LOW) || \ |
| AnnaBridge | 172:65be27845400 | 477 | ((PIN) == PWR_WAKEUP_PIN5_LOW) || \ |
| AnnaBridge | 172:65be27845400 | 478 | ((PIN) == PWR_WAKEUP_PIN6_LOW)) |
| AnnaBridge | 172:65be27845400 | 479 | |
| AnnaBridge | 172:65be27845400 | 480 | #define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) || \ |
| AnnaBridge | 172:65be27845400 | 481 | ((POLARITY) == PWR_PIN_POLARITY_LOW)) |
| AnnaBridge | 172:65be27845400 | 482 | |
| AnnaBridge | 172:65be27845400 | 483 | #define IS_PWR_WAKEUP_PIN_PULL(PULL) (((PULL) == PWR_PIN_NO_PULL) || \ |
| AnnaBridge | 172:65be27845400 | 484 | ((PULL) == PWR_PIN_PULL_UP) || \ |
| AnnaBridge | 172:65be27845400 | 485 | ((PULL) == PWR_PIN_PULL_DOWN)) |
| AnnaBridge | 172:65be27845400 | 486 | |
| AnnaBridge | 172:65be27845400 | 487 | #define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) || \ |
| AnnaBridge | 172:65be27845400 | 488 | ((FLAG) == PWR_WAKEUP_FLAG2) || \ |
| AnnaBridge | 172:65be27845400 | 489 | ((FLAG) == PWR_WAKEUP_FLAG3) || \ |
| AnnaBridge | 172:65be27845400 | 490 | ((FLAG) == PWR_WAKEUP_FLAG4) || \ |
| AnnaBridge | 172:65be27845400 | 491 | ((FLAG) == PWR_WAKEUP_FLAG5) || \ |
| AnnaBridge | 172:65be27845400 | 492 | ((FLAG) == PWR_WAKEUP_FLAG6)) |
| AnnaBridge | 172:65be27845400 | 493 | |
| AnnaBridge | 172:65be27845400 | 494 | #define IS_PWR_AVD_LEVEL(LEVEL) (((LEVEL) == PWR_AVDLEVEL_0) || ((LEVEL) == PWR_AVDLEVEL_1) || \ |
| AnnaBridge | 172:65be27845400 | 495 | ((LEVEL) == PWR_AVDLEVEL_2) || ((LEVEL) == PWR_AVDLEVEL_3)) |
| AnnaBridge | 172:65be27845400 | 496 | |
| AnnaBridge | 172:65be27845400 | 497 | #define IS_PWR_AVD_MODE(MODE) (((MODE) == PWR_AVD_MODE_IT_RISING)|| ((MODE) == PWR_AVD_MODE_IT_FALLING) || \ |
| AnnaBridge | 172:65be27845400 | 498 | ((MODE) == PWR_AVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_AVD_MODE_EVENT_RISING) || \ |
| AnnaBridge | 172:65be27845400 | 499 | ((MODE) == PWR_AVD_MODE_EVENT_FALLING) || ((MODE) == PWR_AVD_MODE_EVENT_RISING_FALLING) || \ |
| AnnaBridge | 172:65be27845400 | 500 | ((MODE) == PWR_AVD_MODE_NORMAL)) |
| AnnaBridge | 172:65be27845400 | 501 | |
| AnnaBridge | 172:65be27845400 | 502 | #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ |
| AnnaBridge | 172:65be27845400 | 503 | ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) |
| AnnaBridge | 172:65be27845400 | 504 | |
| AnnaBridge | 172:65be27845400 | 505 | #define IS_PWR_D1_CPU(CPU) ((CPU) == CM7_CPUID) |
| AnnaBridge | 172:65be27845400 | 506 | |
| AnnaBridge | 172:65be27845400 | 507 | /** |
| AnnaBridge | 172:65be27845400 | 508 | * @} |
| AnnaBridge | 172:65be27845400 | 509 | */ |
| AnnaBridge | 172:65be27845400 | 510 | /** |
| AnnaBridge | 172:65be27845400 | 511 | * @} |
| AnnaBridge | 172:65be27845400 | 512 | */ |
| AnnaBridge | 172:65be27845400 | 513 | |
| AnnaBridge | 172:65be27845400 | 514 | /** |
| AnnaBridge | 172:65be27845400 | 515 | * @} |
| AnnaBridge | 172:65be27845400 | 516 | */ |
| AnnaBridge | 172:65be27845400 | 517 | |
| AnnaBridge | 172:65be27845400 | 518 | /** |
| AnnaBridge | 172:65be27845400 | 519 | * @} |
| AnnaBridge | 172:65be27845400 | 520 | */ |
| AnnaBridge | 172:65be27845400 | 521 | #ifdef __cplusplus |
| AnnaBridge | 172:65be27845400 | 522 | } |
| AnnaBridge | 172:65be27845400 | 523 | #endif |
| AnnaBridge | 172:65be27845400 | 524 | |
| AnnaBridge | 172:65be27845400 | 525 | |
| AnnaBridge | 172:65be27845400 | 526 | #endif /* STM32H7xx_HAL_PWR_EX_H */ |
| AnnaBridge | 172:65be27845400 | 527 | |
| AnnaBridge | 172:65be27845400 | 528 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
