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TARGET_NUCLEO_H743ZI/TOOLCHAIN_ARM_MICRO/stm32h7xx_hal_pwr.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 172:65be27845400 | 1 | /** |
| AnnaBridge | 172:65be27845400 | 2 | ****************************************************************************** |
| AnnaBridge | 172:65be27845400 | 3 | * @file stm32h7xx_hal_pwr.h |
| AnnaBridge | 172:65be27845400 | 4 | * @author MCD Application Team |
| AnnaBridge | 172:65be27845400 | 5 | * @brief Header file of PWR HAL module. |
| AnnaBridge | 172:65be27845400 | 6 | ****************************************************************************** |
| AnnaBridge | 172:65be27845400 | 7 | * @attention |
| AnnaBridge | 172:65be27845400 | 8 | * |
| AnnaBridge | 172:65be27845400 | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics. |
| AnnaBridge | 172:65be27845400 | 10 | * All rights reserved.</center></h2> |
| AnnaBridge | 172:65be27845400 | 11 | * |
| AnnaBridge | 172:65be27845400 | 12 | * This software component is licensed by ST under BSD 3-Clause license, |
| AnnaBridge | 172:65be27845400 | 13 | * the "License"; You may not use this file except in compliance with the |
| AnnaBridge | 172:65be27845400 | 14 | * License. You may obtain a copy of the License at: |
| AnnaBridge | 172:65be27845400 | 15 | * opensource.org/licenses/BSD-3-Clause |
| AnnaBridge | 172:65be27845400 | 16 | * |
| AnnaBridge | 172:65be27845400 | 17 | ****************************************************************************** |
| AnnaBridge | 172:65be27845400 | 18 | */ |
| AnnaBridge | 172:65be27845400 | 19 | |
| AnnaBridge | 172:65be27845400 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 21 | #ifndef STM32H7xx_HAL_PWR_H |
| AnnaBridge | 172:65be27845400 | 22 | #define STM32H7xx_HAL_PWR_H |
| AnnaBridge | 172:65be27845400 | 23 | |
| AnnaBridge | 172:65be27845400 | 24 | #ifdef __cplusplus |
| AnnaBridge | 172:65be27845400 | 25 | extern "C" { |
| AnnaBridge | 172:65be27845400 | 26 | #endif |
| AnnaBridge | 172:65be27845400 | 27 | |
| AnnaBridge | 172:65be27845400 | 28 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 29 | #include "stm32h7xx_hal_def.h" |
| AnnaBridge | 172:65be27845400 | 30 | |
| AnnaBridge | 172:65be27845400 | 31 | /** @addtogroup STM32H7xx_HAL_Driver |
| AnnaBridge | 172:65be27845400 | 32 | * @{ |
| AnnaBridge | 172:65be27845400 | 33 | */ |
| AnnaBridge | 172:65be27845400 | 34 | |
| AnnaBridge | 172:65be27845400 | 35 | /** @addtogroup PWR |
| AnnaBridge | 172:65be27845400 | 36 | * @{ |
| AnnaBridge | 172:65be27845400 | 37 | */ |
| AnnaBridge | 172:65be27845400 | 38 | |
| AnnaBridge | 172:65be27845400 | 39 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 40 | |
| AnnaBridge | 172:65be27845400 | 41 | /** @defgroup PWR_Exported_Types PWR Exported Types |
| AnnaBridge | 172:65be27845400 | 42 | * @{ |
| AnnaBridge | 172:65be27845400 | 43 | */ |
| AnnaBridge | 172:65be27845400 | 44 | |
| AnnaBridge | 172:65be27845400 | 45 | /** |
| AnnaBridge | 172:65be27845400 | 46 | * @brief PWR PVD configuration structure definition |
| AnnaBridge | 172:65be27845400 | 47 | */ |
| AnnaBridge | 172:65be27845400 | 48 | typedef struct |
| AnnaBridge | 172:65be27845400 | 49 | { |
| AnnaBridge | 172:65be27845400 | 50 | uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. |
| AnnaBridge | 172:65be27845400 | 51 | This parameter can be a value of @ref PWR_PVD_detection_level */ |
| AnnaBridge | 172:65be27845400 | 52 | |
| AnnaBridge | 172:65be27845400 | 53 | uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. |
| AnnaBridge | 172:65be27845400 | 54 | This parameter can be a value of @ref PWR_PVD_Mode */ |
| AnnaBridge | 172:65be27845400 | 55 | }PWR_PVDTypeDef; |
| AnnaBridge | 172:65be27845400 | 56 | |
| AnnaBridge | 172:65be27845400 | 57 | /** |
| AnnaBridge | 172:65be27845400 | 58 | * @} |
| AnnaBridge | 172:65be27845400 | 59 | */ |
| AnnaBridge | 172:65be27845400 | 60 | |
| AnnaBridge | 172:65be27845400 | 61 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 62 | /** @defgroup PWR_Exported_Constants PWR Exported Constants |
| AnnaBridge | 172:65be27845400 | 63 | * @{ |
| AnnaBridge | 172:65be27845400 | 64 | */ |
| AnnaBridge | 172:65be27845400 | 65 | |
| AnnaBridge | 172:65be27845400 | 66 | /** @defgroup PWR_PVD_detection_level PWR PVD detection level |
| AnnaBridge | 172:65be27845400 | 67 | * @{ |
| AnnaBridge | 172:65be27845400 | 68 | */ |
| AnnaBridge | 172:65be27845400 | 69 | #define PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 /*!< Programmable voltage detector level 0 selection : 1V95 */ |
| AnnaBridge | 172:65be27845400 | 70 | #define PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 /*!< Programmable voltage detector level 1 selection : 2V1 */ |
| AnnaBridge | 172:65be27845400 | 71 | #define PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 /*!< Programmable voltage detector level 2 selection : 2V25 */ |
| AnnaBridge | 172:65be27845400 | 72 | #define PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 /*!< Programmable voltage detector level 3 selection : 2V4 */ |
| AnnaBridge | 172:65be27845400 | 73 | #define PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 /*!< Programmable voltage detector level 4 selection : 2V55 */ |
| AnnaBridge | 172:65be27845400 | 74 | #define PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 /*!< Programmable voltage detector level 5 selection : 2V7 */ |
| AnnaBridge | 172:65be27845400 | 75 | #define PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 /*!< Programmable voltage detector level 6 selection : 2V85 */ |
| AnnaBridge | 172:65be27845400 | 76 | #define PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7 /*!< External input analog voltage (Compare internally to VREFINT) */ |
| AnnaBridge | 172:65be27845400 | 77 | /** |
| AnnaBridge | 172:65be27845400 | 78 | * @} |
| AnnaBridge | 172:65be27845400 | 79 | */ |
| AnnaBridge | 172:65be27845400 | 80 | |
| AnnaBridge | 172:65be27845400 | 81 | /** @defgroup PWR_PVD_Mode PWR PVD Mode |
| AnnaBridge | 172:65be27845400 | 82 | * @{ |
| AnnaBridge | 172:65be27845400 | 83 | */ |
| AnnaBridge | 172:65be27845400 | 84 | #define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Basic mode is used */ |
| AnnaBridge | 172:65be27845400 | 85 | #define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ |
| AnnaBridge | 172:65be27845400 | 86 | #define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ |
| AnnaBridge | 172:65be27845400 | 87 | #define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ |
| AnnaBridge | 172:65be27845400 | 88 | #define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */ |
| AnnaBridge | 172:65be27845400 | 89 | #define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */ |
| AnnaBridge | 172:65be27845400 | 90 | #define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ |
| AnnaBridge | 172:65be27845400 | 91 | /** |
| AnnaBridge | 172:65be27845400 | 92 | * @} |
| AnnaBridge | 172:65be27845400 | 93 | */ |
| AnnaBridge | 172:65be27845400 | 94 | |
| AnnaBridge | 172:65be27845400 | 95 | /** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode |
| AnnaBridge | 172:65be27845400 | 96 | * @{ |
| AnnaBridge | 172:65be27845400 | 97 | */ |
| AnnaBridge | 172:65be27845400 | 98 | #define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U) |
| AnnaBridge | 172:65be27845400 | 99 | #define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS |
| AnnaBridge | 172:65be27845400 | 100 | /** |
| AnnaBridge | 172:65be27845400 | 101 | * @} |
| AnnaBridge | 172:65be27845400 | 102 | */ |
| AnnaBridge | 172:65be27845400 | 103 | |
| AnnaBridge | 172:65be27845400 | 104 | /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry |
| AnnaBridge | 172:65be27845400 | 105 | * @{ |
| AnnaBridge | 172:65be27845400 | 106 | */ |
| AnnaBridge | 172:65be27845400 | 107 | #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U) |
| AnnaBridge | 172:65be27845400 | 108 | #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U) |
| AnnaBridge | 172:65be27845400 | 109 | /** |
| AnnaBridge | 172:65be27845400 | 110 | * @} |
| AnnaBridge | 172:65be27845400 | 111 | */ |
| AnnaBridge | 172:65be27845400 | 112 | |
| AnnaBridge | 172:65be27845400 | 113 | /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry |
| AnnaBridge | 172:65be27845400 | 114 | * @{ |
| AnnaBridge | 172:65be27845400 | 115 | */ |
| AnnaBridge | 172:65be27845400 | 116 | #define PWR_STOPENTRY_WFI ((uint8_t)0x01U) |
| AnnaBridge | 172:65be27845400 | 117 | #define PWR_STOPENTRY_WFE ((uint8_t)0x02U) |
| AnnaBridge | 172:65be27845400 | 118 | /** |
| AnnaBridge | 172:65be27845400 | 119 | * @} |
| AnnaBridge | 172:65be27845400 | 120 | */ |
| AnnaBridge | 172:65be27845400 | 121 | |
| AnnaBridge | 172:65be27845400 | 122 | /** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale |
| AnnaBridge | 172:65be27845400 | 123 | * @{ |
| AnnaBridge | 172:65be27845400 | 124 | */ |
| AnnaBridge | 172:65be27845400 | 125 | #define PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0) |
| AnnaBridge | 172:65be27845400 | 126 | #define PWR_REGULATOR_VOLTAGE_SCALE2 (PWR_D3CR_VOS_1) |
| AnnaBridge | 172:65be27845400 | 127 | #define PWR_REGULATOR_VOLTAGE_SCALE3 (PWR_D3CR_VOS_0) |
| AnnaBridge | 172:65be27845400 | 128 | /** |
| AnnaBridge | 172:65be27845400 | 129 | * @} |
| AnnaBridge | 172:65be27845400 | 130 | */ |
| AnnaBridge | 172:65be27845400 | 131 | |
| AnnaBridge | 172:65be27845400 | 132 | /** @defgroup PWR_Flag PWR Flag |
| AnnaBridge | 172:65be27845400 | 133 | * @{ |
| AnnaBridge | 172:65be27845400 | 134 | */ |
| AnnaBridge | 172:65be27845400 | 135 | #define PWR_FLAG_STOP ((uint8_t)0x01U) |
| AnnaBridge | 172:65be27845400 | 136 | #define PWR_FLAG_SB_D1 ((uint8_t)0x02U) |
| AnnaBridge | 172:65be27845400 | 137 | #define PWR_FLAG_SB_D2 ((uint8_t)0x03U) |
| AnnaBridge | 172:65be27845400 | 138 | #define PWR_FLAG_SB ((uint8_t)0x04U) |
| AnnaBridge | 172:65be27845400 | 139 | #define PWR_FLAG_PVDO ((uint8_t)0x0BU) |
| AnnaBridge | 172:65be27845400 | 140 | #define PWR_FLAG_AVDO ((uint8_t)0x0CU) |
| AnnaBridge | 172:65be27845400 | 141 | #define PWR_FLAG_ACTVOSRDY ((uint8_t)0x0DU) |
| AnnaBridge | 172:65be27845400 | 142 | #define PWR_FLAG_ACTVOS ((uint8_t)0x0EU) |
| AnnaBridge | 172:65be27845400 | 143 | #define PWR_FLAG_BRR ((uint8_t)0x0FU) |
| AnnaBridge | 172:65be27845400 | 144 | #define PWR_FLAG_VOSRDY ((uint8_t)0x10U) |
| AnnaBridge | 172:65be27845400 | 145 | #define PWR_FLAG_SCUEN ((uint8_t)0x11U) |
| AnnaBridge | 172:65be27845400 | 146 | /** |
| AnnaBridge | 172:65be27845400 | 147 | * @} |
| AnnaBridge | 172:65be27845400 | 148 | */ |
| AnnaBridge | 172:65be27845400 | 149 | |
| AnnaBridge | 172:65be27845400 | 150 | /** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask |
| AnnaBridge | 172:65be27845400 | 151 | * @{ |
| AnnaBridge | 172:65be27845400 | 152 | */ |
| AnnaBridge | 172:65be27845400 | 153 | #define PWR_EWUP_MASK ((uint32_t)0x0FFF3F3FU) |
| AnnaBridge | 172:65be27845400 | 154 | /** |
| AnnaBridge | 172:65be27845400 | 155 | * @} |
| AnnaBridge | 172:65be27845400 | 156 | */ |
| AnnaBridge | 172:65be27845400 | 157 | |
| AnnaBridge | 172:65be27845400 | 158 | /** |
| AnnaBridge | 172:65be27845400 | 159 | * @} |
| AnnaBridge | 172:65be27845400 | 160 | */ |
| AnnaBridge | 172:65be27845400 | 161 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 162 | /** @defgroup PWR_Exported_Macro PWR Exported Macro |
| AnnaBridge | 172:65be27845400 | 163 | * @{ |
| AnnaBridge | 172:65be27845400 | 164 | */ |
| AnnaBridge | 172:65be27845400 | 165 | |
| AnnaBridge | 172:65be27845400 | 166 | /** @brief macros configure the main internal regulator output voltage. |
| AnnaBridge | 172:65be27845400 | 167 | * @param __REGULATOR__: specifies the regulator output voltage to achieve |
| AnnaBridge | 172:65be27845400 | 168 | * a tradeoff between performance and power consumption when the device does |
| AnnaBridge | 172:65be27845400 | 169 | * not operate at the maximum frequency (refer to the datasheets for more details). |
| AnnaBridge | 172:65be27845400 | 170 | * This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 171 | * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode |
| AnnaBridge | 172:65be27845400 | 172 | * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode |
| AnnaBridge | 172:65be27845400 | 173 | * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode |
| AnnaBridge | 172:65be27845400 | 174 | * @retval None |
| AnnaBridge | 172:65be27845400 | 175 | */ |
| AnnaBridge | 172:65be27845400 | 176 | #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \ |
| AnnaBridge | 172:65be27845400 | 177 | do { \ |
| AnnaBridge | 172:65be27845400 | 178 | __IO uint32_t tmpreg = 0x00; \ |
| AnnaBridge | 172:65be27845400 | 179 | MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \ |
| AnnaBridge | 172:65be27845400 | 180 | /* Delay after setting the voltage scaling */ \ |
| AnnaBridge | 172:65be27845400 | 181 | tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \ |
| AnnaBridge | 172:65be27845400 | 182 | UNUSED(tmpreg); \ |
| AnnaBridge | 172:65be27845400 | 183 | } while(0) |
| AnnaBridge | 172:65be27845400 | 184 | |
| AnnaBridge | 172:65be27845400 | 185 | |
| AnnaBridge | 172:65be27845400 | 186 | /** @brief Check PWR PVD/AVD and VOSflags are set or not. |
| AnnaBridge | 172:65be27845400 | 187 | * @param __FLAG__: specifies the flag to check. |
| AnnaBridge | 172:65be27845400 | 188 | * This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 189 | * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled |
| AnnaBridge | 172:65be27845400 | 190 | * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode. |
| AnnaBridge | 172:65be27845400 | 191 | * For this reason, this bit is equal to 0 after Standby or reset |
| AnnaBridge | 172:65be27845400 | 192 | * until the PVDE bit is set. |
| AnnaBridge | 172:65be27845400 | 193 | * @arg PWR_FLAG_AVDO: AVD Output. This flag is valid only if AVD is enabled |
| AnnaBridge | 172:65be27845400 | 194 | * by the HAL_PWREx_EnableAVD() function. The AVD is stopped by Standby mode. |
| AnnaBridge | 172:65be27845400 | 195 | * For this reason, this bit is equal to 0 after Standby or reset |
| AnnaBridge | 172:65be27845400 | 196 | * until the AVDE bit is set. |
| AnnaBridge | 172:65be27845400 | 197 | * @arg PWR_FLAG_ACTVOSRDY: This flag indicates that the Regulator voltage |
| AnnaBridge | 172:65be27845400 | 198 | * scaling output selection is ready. |
| AnnaBridge | 172:65be27845400 | 199 | * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage |
| AnnaBridge | 172:65be27845400 | 200 | * scaling output selection is ready. |
| AnnaBridge | 172:65be27845400 | 201 | * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset |
| AnnaBridge | 172:65be27845400 | 202 | * when the device wakes up from Standby mode or by a system reset |
| AnnaBridge | 172:65be27845400 | 203 | * or power reset. |
| AnnaBridge | 172:65be27845400 | 204 | * @arg PWR_FLAG_SB: StandBy flag |
| AnnaBridge | 172:65be27845400 | 205 | * @arg PWR_FLAG_STOP: STOP flag |
| AnnaBridge | 172:65be27845400 | 206 | * @arg PWR_FLAG_SB_D1: StandBy D1 flag |
| AnnaBridge | 172:65be27845400 | 207 | * @arg PWR_FLAG_SB_D2: StandBy D2 flag |
| AnnaBridge | 172:65be27845400 | 208 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| AnnaBridge | 172:65be27845400 | 209 | */ |
| AnnaBridge | 172:65be27845400 | 210 | #define __HAL_PWR_GET_FLAG(__FLAG__) ( \ |
| AnnaBridge | 172:65be27845400 | 211 | ((__FLAG__) == PWR_FLAG_PVDO)?((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) : \ |
| AnnaBridge | 172:65be27845400 | 212 | ((__FLAG__) == PWR_FLAG_AVDO)?((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) : \ |
| AnnaBridge | 172:65be27845400 | 213 | ((__FLAG__) == PWR_FLAG_ACTVOSRDY)?((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) : \ |
| AnnaBridge | 172:65be27845400 | 214 | ((__FLAG__) == PWR_FLAG_VOSRDY)?((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) : \ |
| AnnaBridge | 172:65be27845400 | 215 | ((__FLAG__) == PWR_FLAG_SCUEN)?((PWR->CR3 & PWR_CR3_SCUEN) == PWR_CR3_SCUEN) : \ |
| AnnaBridge | 172:65be27845400 | 216 | ((__FLAG__) == PWR_FLAG_BRR)?((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) : \ |
| AnnaBridge | 172:65be27845400 | 217 | ((__FLAG__) == PWR_FLAG_SB)?((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) : \ |
| AnnaBridge | 172:65be27845400 | 218 | ((__FLAG__) == PWR_FLAG_STOP)?((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) : \ |
| AnnaBridge | 172:65be27845400 | 219 | ((__FLAG__) == PWR_FLAG_SB_D1)?((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) : \ |
| AnnaBridge | 172:65be27845400 | 220 | ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2)) |
| AnnaBridge | 172:65be27845400 | 221 | |
| AnnaBridge | 172:65be27845400 | 222 | |
| AnnaBridge | 172:65be27845400 | 223 | /** @brief Clear PWR flags. |
| AnnaBridge | 172:65be27845400 | 224 | * @param __FLAG__: specifies the flag to clear. |
| AnnaBridge | 172:65be27845400 | 225 | * This parameter can be one of the following values: |
| AnnaBridge | 172:65be27845400 | 226 | * @arg PWR_FLAG_SB: Standby flag. |
| AnnaBridge | 172:65be27845400 | 227 | * @arg PWR_CPU_FLAGS: Clear STOPF, SBF, SBF_D1, and SBF_D2 CPU flags. |
| AnnaBridge | 172:65be27845400 | 228 | * @retval None. |
| AnnaBridge | 172:65be27845400 | 229 | */ |
| AnnaBridge | 172:65be27845400 | 230 | #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF) |
| AnnaBridge | 172:65be27845400 | 231 | |
| AnnaBridge | 172:65be27845400 | 232 | /** |
| AnnaBridge | 172:65be27845400 | 233 | * @brief Enable the PVD EXTI Line 16. |
| AnnaBridge | 172:65be27845400 | 234 | * @retval None. |
| AnnaBridge | 172:65be27845400 | 235 | */ |
| AnnaBridge | 172:65be27845400 | 236 | #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 172:65be27845400 | 237 | |
| AnnaBridge | 172:65be27845400 | 238 | /** |
| AnnaBridge | 172:65be27845400 | 239 | * @brief Disable the PVD EXTI Line 16. |
| AnnaBridge | 172:65be27845400 | 240 | * @retval None. |
| AnnaBridge | 172:65be27845400 | 241 | */ |
| AnnaBridge | 172:65be27845400 | 242 | #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 172:65be27845400 | 243 | |
| AnnaBridge | 172:65be27845400 | 244 | /** |
| AnnaBridge | 172:65be27845400 | 245 | * @brief Enable event on PVD EXTI Line 16. |
| AnnaBridge | 172:65be27845400 | 246 | * @retval None. |
| AnnaBridge | 172:65be27845400 | 247 | */ |
| AnnaBridge | 172:65be27845400 | 248 | #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 172:65be27845400 | 249 | |
| AnnaBridge | 172:65be27845400 | 250 | /** |
| AnnaBridge | 172:65be27845400 | 251 | * @brief Disable event on PVD EXTI Line 16. |
| AnnaBridge | 172:65be27845400 | 252 | * @retval None. |
| AnnaBridge | 172:65be27845400 | 253 | */ |
| AnnaBridge | 172:65be27845400 | 254 | #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 172:65be27845400 | 255 | |
| AnnaBridge | 172:65be27845400 | 256 | /** |
| AnnaBridge | 172:65be27845400 | 257 | * @brief Enable the PVD Extended Interrupt Rising Trigger. |
| AnnaBridge | 172:65be27845400 | 258 | * @retval None. |
| AnnaBridge | 172:65be27845400 | 259 | */ |
| AnnaBridge | 172:65be27845400 | 260 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 172:65be27845400 | 261 | |
| AnnaBridge | 172:65be27845400 | 262 | /** |
| AnnaBridge | 172:65be27845400 | 263 | * @brief Disable the PVD Extended Interrupt Rising Trigger. |
| AnnaBridge | 172:65be27845400 | 264 | * @retval None. |
| AnnaBridge | 172:65be27845400 | 265 | */ |
| AnnaBridge | 172:65be27845400 | 266 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 172:65be27845400 | 267 | |
| AnnaBridge | 172:65be27845400 | 268 | /** |
| AnnaBridge | 172:65be27845400 | 269 | * @brief Enable the PVD Extended Interrupt Falling Trigger. |
| AnnaBridge | 172:65be27845400 | 270 | * @retval None. |
| AnnaBridge | 172:65be27845400 | 271 | */ |
| AnnaBridge | 172:65be27845400 | 272 | #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 172:65be27845400 | 273 | |
| AnnaBridge | 172:65be27845400 | 274 | |
| AnnaBridge | 172:65be27845400 | 275 | /** |
| AnnaBridge | 172:65be27845400 | 276 | * @brief Disable the PVD Extended Interrupt Falling Trigger. |
| AnnaBridge | 172:65be27845400 | 277 | * @retval None. |
| AnnaBridge | 172:65be27845400 | 278 | */ |
| AnnaBridge | 172:65be27845400 | 279 | #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 172:65be27845400 | 280 | |
| AnnaBridge | 172:65be27845400 | 281 | |
| AnnaBridge | 172:65be27845400 | 282 | /** |
| AnnaBridge | 172:65be27845400 | 283 | * @brief PVD EXTI line configuration: set rising & falling edge trigger. |
| AnnaBridge | 172:65be27845400 | 284 | * @retval None. |
| AnnaBridge | 172:65be27845400 | 285 | */ |
| AnnaBridge | 172:65be27845400 | 286 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ |
| AnnaBridge | 172:65be27845400 | 287 | do { \ |
| AnnaBridge | 172:65be27845400 | 288 | __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ |
| AnnaBridge | 172:65be27845400 | 289 | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ |
| AnnaBridge | 172:65be27845400 | 290 | } while(0); |
| AnnaBridge | 172:65be27845400 | 291 | |
| AnnaBridge | 172:65be27845400 | 292 | /** |
| AnnaBridge | 172:65be27845400 | 293 | * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. |
| AnnaBridge | 172:65be27845400 | 294 | * @retval None. |
| AnnaBridge | 172:65be27845400 | 295 | */ |
| AnnaBridge | 172:65be27845400 | 296 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ |
| AnnaBridge | 172:65be27845400 | 297 | do { \ |
| AnnaBridge | 172:65be27845400 | 298 | __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ |
| AnnaBridge | 172:65be27845400 | 299 | __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ |
| AnnaBridge | 172:65be27845400 | 300 | } while(0); |
| AnnaBridge | 172:65be27845400 | 301 | |
| AnnaBridge | 172:65be27845400 | 302 | /** |
| AnnaBridge | 172:65be27845400 | 303 | * @brief Check whether the specified PVD EXTI interrupt flag is set or not. |
| AnnaBridge | 172:65be27845400 | 304 | * @retval EXTI PVD Line Status. |
| AnnaBridge | 172:65be27845400 | 305 | */ |
| AnnaBridge | 172:65be27845400 | 306 | #define __HAL_PWR_PVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? SET : RESET) |
| AnnaBridge | 172:65be27845400 | 307 | |
| AnnaBridge | 172:65be27845400 | 308 | /** |
| AnnaBridge | 172:65be27845400 | 309 | * @brief Clear the PVD EXTI flag. |
| AnnaBridge | 172:65be27845400 | 310 | * @retval None. |
| AnnaBridge | 172:65be27845400 | 311 | */ |
| AnnaBridge | 172:65be27845400 | 312 | #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 172:65be27845400 | 313 | |
| AnnaBridge | 172:65be27845400 | 314 | /** |
| AnnaBridge | 172:65be27845400 | 315 | * @brief Generates a Software interrupt on PVD EXTI line. |
| AnnaBridge | 172:65be27845400 | 316 | * @retval None. |
| AnnaBridge | 172:65be27845400 | 317 | */ |
| AnnaBridge | 172:65be27845400 | 318 | #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 172:65be27845400 | 319 | /** |
| AnnaBridge | 172:65be27845400 | 320 | * @} |
| AnnaBridge | 172:65be27845400 | 321 | */ |
| AnnaBridge | 172:65be27845400 | 322 | |
| AnnaBridge | 172:65be27845400 | 323 | |
| AnnaBridge | 172:65be27845400 | 324 | /* Include PWR HAL Extension module */ |
| AnnaBridge | 172:65be27845400 | 325 | #include "stm32h7xx_hal_pwr_ex.h" |
| AnnaBridge | 172:65be27845400 | 326 | |
| AnnaBridge | 172:65be27845400 | 327 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 328 | /** @addtogroup PWR_Exported_Functions PWR Exported Functions |
| AnnaBridge | 172:65be27845400 | 329 | * @{ |
| AnnaBridge | 172:65be27845400 | 330 | */ |
| AnnaBridge | 172:65be27845400 | 331 | |
| AnnaBridge | 172:65be27845400 | 332 | /** @addtogroup PWR_Exported_Functions_Group1 Initialization and De-Initialization functions |
| AnnaBridge | 172:65be27845400 | 333 | * @{ |
| AnnaBridge | 172:65be27845400 | 334 | */ |
| AnnaBridge | 172:65be27845400 | 335 | /* Initialization and de-initialization functions *****************************/ |
| AnnaBridge | 172:65be27845400 | 336 | void HAL_PWR_DeInit(void); |
| AnnaBridge | 172:65be27845400 | 337 | void HAL_PWR_EnableBkUpAccess(void); |
| AnnaBridge | 172:65be27845400 | 338 | void HAL_PWR_DisableBkUpAccess(void); |
| AnnaBridge | 172:65be27845400 | 339 | /** |
| AnnaBridge | 172:65be27845400 | 340 | * @} |
| AnnaBridge | 172:65be27845400 | 341 | */ |
| AnnaBridge | 172:65be27845400 | 342 | |
| AnnaBridge | 172:65be27845400 | 343 | /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions |
| AnnaBridge | 172:65be27845400 | 344 | * @{ |
| AnnaBridge | 172:65be27845400 | 345 | */ |
| AnnaBridge | 172:65be27845400 | 346 | /* Peripheral Control functions **********************************************/ |
| AnnaBridge | 172:65be27845400 | 347 | /* PVD configuration */ |
| AnnaBridge | 172:65be27845400 | 348 | void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); |
| AnnaBridge | 172:65be27845400 | 349 | void HAL_PWR_EnablePVD(void); |
| AnnaBridge | 172:65be27845400 | 350 | void HAL_PWR_DisablePVD(void); |
| AnnaBridge | 172:65be27845400 | 351 | |
| AnnaBridge | 172:65be27845400 | 352 | /* WakeUp pins configuration */ |
| AnnaBridge | 172:65be27845400 | 353 | void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity); |
| AnnaBridge | 172:65be27845400 | 354 | void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); |
| AnnaBridge | 172:65be27845400 | 355 | |
| AnnaBridge | 172:65be27845400 | 356 | /* Low Power modes entry */ |
| AnnaBridge | 172:65be27845400 | 357 | void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); |
| AnnaBridge | 172:65be27845400 | 358 | void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); |
| AnnaBridge | 172:65be27845400 | 359 | void HAL_PWR_EnterSTANDBYMode(void); |
| AnnaBridge | 172:65be27845400 | 360 | |
| AnnaBridge | 172:65be27845400 | 361 | /* Power PVD IRQ Handler */ |
| AnnaBridge | 172:65be27845400 | 362 | void HAL_PWR_PVD_IRQHandler(void); |
| AnnaBridge | 172:65be27845400 | 363 | void HAL_PWR_PVDCallback(void); |
| AnnaBridge | 172:65be27845400 | 364 | |
| AnnaBridge | 172:65be27845400 | 365 | /* Cortex System Control functions *******************************************/ |
| AnnaBridge | 172:65be27845400 | 366 | void HAL_PWR_EnableSleepOnExit(void); |
| AnnaBridge | 172:65be27845400 | 367 | void HAL_PWR_DisableSleepOnExit(void); |
| AnnaBridge | 172:65be27845400 | 368 | void HAL_PWR_EnableSEVOnPend(void); |
| AnnaBridge | 172:65be27845400 | 369 | void HAL_PWR_DisableSEVOnPend(void); |
| AnnaBridge | 172:65be27845400 | 370 | /** |
| AnnaBridge | 172:65be27845400 | 371 | * @} |
| AnnaBridge | 172:65be27845400 | 372 | */ |
| AnnaBridge | 172:65be27845400 | 373 | |
| AnnaBridge | 172:65be27845400 | 374 | /** |
| AnnaBridge | 172:65be27845400 | 375 | * @} |
| AnnaBridge | 172:65be27845400 | 376 | */ |
| AnnaBridge | 172:65be27845400 | 377 | |
| AnnaBridge | 172:65be27845400 | 378 | /* Private types -------------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 379 | /* Private variables ---------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 380 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 381 | /** @defgroup PWR_Private_Constants PWR Private Constants |
| AnnaBridge | 172:65be27845400 | 382 | * @{ |
| AnnaBridge | 172:65be27845400 | 383 | */ |
| AnnaBridge | 172:65be27845400 | 384 | |
| AnnaBridge | 172:65be27845400 | 385 | /** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line |
| AnnaBridge | 172:65be27845400 | 386 | * @{ |
| AnnaBridge | 172:65be27845400 | 387 | */ |
| AnnaBridge | 172:65be27845400 | 388 | /*!< External interrupt line 16 Connected to the PVD EXTI Line */ |
| AnnaBridge | 172:65be27845400 | 389 | #define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR1_IM16) |
| AnnaBridge | 172:65be27845400 | 390 | /** |
| AnnaBridge | 172:65be27845400 | 391 | * @} |
| AnnaBridge | 172:65be27845400 | 392 | */ |
| AnnaBridge | 172:65be27845400 | 393 | |
| AnnaBridge | 172:65be27845400 | 394 | /** |
| AnnaBridge | 172:65be27845400 | 395 | * @} |
| AnnaBridge | 172:65be27845400 | 396 | */ |
| AnnaBridge | 172:65be27845400 | 397 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 398 | /** @defgroup PWR_Private_Macros PWR Private Macros |
| AnnaBridge | 172:65be27845400 | 399 | * @{ |
| AnnaBridge | 172:65be27845400 | 400 | */ |
| AnnaBridge | 172:65be27845400 | 401 | |
| AnnaBridge | 172:65be27845400 | 402 | /** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters |
| AnnaBridge | 172:65be27845400 | 403 | * @{ |
| AnnaBridge | 172:65be27845400 | 404 | */ |
| AnnaBridge | 172:65be27845400 | 405 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ |
| AnnaBridge | 172:65be27845400 | 406 | ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ |
| AnnaBridge | 172:65be27845400 | 407 | ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ |
| AnnaBridge | 172:65be27845400 | 408 | ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) |
| AnnaBridge | 172:65be27845400 | 409 | |
| AnnaBridge | 172:65be27845400 | 410 | #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ |
| AnnaBridge | 172:65be27845400 | 411 | ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ |
| AnnaBridge | 172:65be27845400 | 412 | ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ |
| AnnaBridge | 172:65be27845400 | 413 | ((MODE) == PWR_PVD_MODE_NORMAL)) |
| AnnaBridge | 172:65be27845400 | 414 | |
| AnnaBridge | 172:65be27845400 | 415 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ |
| AnnaBridge | 172:65be27845400 | 416 | ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) |
| AnnaBridge | 172:65be27845400 | 417 | |
| AnnaBridge | 172:65be27845400 | 418 | #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) |
| AnnaBridge | 172:65be27845400 | 419 | |
| AnnaBridge | 172:65be27845400 | 420 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) |
| AnnaBridge | 172:65be27845400 | 421 | #define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ |
| AnnaBridge | 172:65be27845400 | 422 | ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \ |
| AnnaBridge | 172:65be27845400 | 423 | ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) |
| AnnaBridge | 172:65be27845400 | 424 | |
| AnnaBridge | 172:65be27845400 | 425 | /** |
| AnnaBridge | 172:65be27845400 | 426 | * @} |
| AnnaBridge | 172:65be27845400 | 427 | */ |
| AnnaBridge | 172:65be27845400 | 428 | |
| AnnaBridge | 172:65be27845400 | 429 | /** |
| AnnaBridge | 172:65be27845400 | 430 | * @} |
| AnnaBridge | 172:65be27845400 | 431 | */ |
| AnnaBridge | 172:65be27845400 | 432 | |
| AnnaBridge | 172:65be27845400 | 433 | /** |
| AnnaBridge | 172:65be27845400 | 434 | * @} |
| AnnaBridge | 172:65be27845400 | 435 | */ |
| AnnaBridge | 172:65be27845400 | 436 | |
| AnnaBridge | 172:65be27845400 | 437 | /** |
| AnnaBridge | 172:65be27845400 | 438 | * @} |
| AnnaBridge | 172:65be27845400 | 439 | */ |
| AnnaBridge | 172:65be27845400 | 440 | |
| AnnaBridge | 172:65be27845400 | 441 | #ifdef __cplusplus |
| AnnaBridge | 172:65be27845400 | 442 | } |
| AnnaBridge | 172:65be27845400 | 443 | #endif |
| AnnaBridge | 172:65be27845400 | 444 | |
| AnnaBridge | 172:65be27845400 | 445 | |
| AnnaBridge | 172:65be27845400 | 446 | #endif /* STM32H7xx_HAL_PWR_H */ |
| AnnaBridge | 172:65be27845400 | 447 | |
| AnnaBridge | 172:65be27845400 | 448 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
