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TARGET_NUCLEO_H743ZI/TOOLCHAIN_ARM_MICRO/stm32h7xx_hal_hrtim.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	172:65be27845400	1	/**
AnnaBridge	172:65be27845400	2	******************************************************************************
AnnaBridge	172:65be27845400	3	* @file stm32h7xx_hal_hrtim.h
AnnaBridge	172:65be27845400	4	* @author MCD Application Team
AnnaBridge	172:65be27845400	5	* @brief Header file of HRTIM HAL module.
AnnaBridge	172:65be27845400	6	******************************************************************************
AnnaBridge	172:65be27845400	7	* @attention
AnnaBridge	172:65be27845400	8	*
AnnaBridge	172:65be27845400	9	* <h2><center>© Copyright (c) 2017 STMicroelectronics.
AnnaBridge	172:65be27845400	10	* All rights reserved.</center></h2>
AnnaBridge	172:65be27845400	11	*
AnnaBridge	172:65be27845400	12	* This software component is licensed by ST under BSD 3-Clause license,
AnnaBridge	172:65be27845400	13	* the "License"; You may not use this file except in compliance with the
AnnaBridge	172:65be27845400	14	* License. You may obtain a copy of the License at:
AnnaBridge	172:65be27845400	15	* opensource.org/licenses/BSD-3-Clause
AnnaBridge	172:65be27845400	16	*
AnnaBridge	172:65be27845400	17	******************************************************************************
AnnaBridge	172:65be27845400	18	*/
AnnaBridge	172:65be27845400	19
AnnaBridge	172:65be27845400	20	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	172:65be27845400	21	#ifndef STM32H7xx_HAL_HRTIM_H
AnnaBridge	172:65be27845400	22	#define STM32H7xx_HAL_HRTIM_H
AnnaBridge	172:65be27845400	23
AnnaBridge	172:65be27845400	24	#ifdef __cplusplus
AnnaBridge	172:65be27845400	25	extern "C" {
AnnaBridge	172:65be27845400	26	#endif
AnnaBridge	172:65be27845400	27
AnnaBridge	172:65be27845400	28	/* Includes ------------------------------------------------------------------*/
AnnaBridge	172:65be27845400	29	#include "stm32h7xx_hal_def.h"
AnnaBridge	172:65be27845400	30
AnnaBridge	172:65be27845400	31	/** @addtogroup STM32H7xx_HAL_Driver
AnnaBridge	172:65be27845400	32	* @{
AnnaBridge	172:65be27845400	33	*/
AnnaBridge	172:65be27845400	34
AnnaBridge	172:65be27845400	35	/** @addtogroup HRTIM HRTIM
AnnaBridge	172:65be27845400	36	* @{
AnnaBridge	172:65be27845400	37	*/
AnnaBridge	172:65be27845400	38
AnnaBridge	172:65be27845400	39	/* Exported types ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	40	/** @addtogroup HRTIM_Exported_Constants HRTIM Exported Constants
AnnaBridge	172:65be27845400	41	* @{
AnnaBridge	172:65be27845400	42	*/
AnnaBridge	172:65be27845400	43	/** @defgroup HRTIM_Max_Timer HRTIM Max Timer
AnnaBridge	172:65be27845400	44	* @{
AnnaBridge	172:65be27845400	45	*/
AnnaBridge	172:65be27845400	46	#define MAX_HRTIM_TIMER 6U
AnnaBridge	172:65be27845400	47	/**
AnnaBridge	172:65be27845400	48	* @}
AnnaBridge	172:65be27845400	49	*/
AnnaBridge	172:65be27845400	50	/**
AnnaBridge	172:65be27845400	51	* @}
AnnaBridge	172:65be27845400	52	*/
AnnaBridge	172:65be27845400	53
AnnaBridge	172:65be27845400	54	/** @defgroup HRTIM_Exported_Types HRTIM Exported Types
AnnaBridge	172:65be27845400	55	* @{
AnnaBridge	172:65be27845400	56	*/
AnnaBridge	172:65be27845400	57
AnnaBridge	172:65be27845400	58	/**
AnnaBridge	172:65be27845400	59	* @brief HRTIM Configuration Structure definition - Time base related parameters
AnnaBridge	172:65be27845400	60	*/
AnnaBridge	172:65be27845400	61	typedef struct
AnnaBridge	172:65be27845400	62	{
AnnaBridge	172:65be27845400	63	uint32_t HRTIMInterruptResquests; /*!< Specifies which interrupts requests must enabled for the HRTIM instance.
AnnaBridge	172:65be27845400	64	This parameter can be any combination of @ref HRTIM_Common_Interrupt_Enable */
AnnaBridge	172:65be27845400	65	uint32_t SyncOptions; /*!< Specifies how the HRTIM instance handles the external synchronization signals.
AnnaBridge	172:65be27845400	66	The HRTIM instance can be configured to act as a slave (waiting for a trigger
AnnaBridge	172:65be27845400	67	to be synchronized) or a master (generating a synchronization signal) or both.
AnnaBridge	172:65be27845400	68	This parameter can be a combination of @ref HRTIM_Synchronization_Options.*/
AnnaBridge	172:65be27845400	69	uint32_t SyncInputSource; /*!< Specifies the external synchronization input source (significant only when
AnnaBridge	172:65be27845400	70	the HRTIM instance is configured as a slave).
AnnaBridge	172:65be27845400	71	This parameter can be a value of @ref HRTIM_Synchronization_Input_Source. */
AnnaBridge	172:65be27845400	72	uint32_t SyncOutputSource; /*!< Specifies the source and event to be sent on the external synchronization outputs
AnnaBridge	172:65be27845400	73	(significant only when the HRTIM instance is configured as a master).
AnnaBridge	172:65be27845400	74	This parameter can be a value of @ref HRTIM_Synchronization_Output_Source */
AnnaBridge	172:65be27845400	75	uint32_t SyncOutputPolarity; /*!< Specifies the conditioning of the event to be sent on the external synchronization
AnnaBridge	172:65be27845400	76	outputs (significant only when the HRTIM instance is configured as a master).
AnnaBridge	172:65be27845400	77	This parameter can be a value of @ref HRTIM_Synchronization_Output_Polarity */
AnnaBridge	172:65be27845400	78	} HRTIM_InitTypeDef;
AnnaBridge	172:65be27845400	79
AnnaBridge	172:65be27845400	80	/**
AnnaBridge	172:65be27845400	81	* @brief HAL State structures definition
AnnaBridge	172:65be27845400	82	*/
AnnaBridge	172:65be27845400	83	typedef enum
AnnaBridge	172:65be27845400	84	{
AnnaBridge	172:65be27845400	85	HAL_HRTIM_STATE_RESET = 0x00U, /!< Peripheral is not yet Initialized /
AnnaBridge	172:65be27845400	86	HAL_HRTIM_STATE_READY = 0x01U, /!< Peripheral Initialized and ready for use /
AnnaBridge	172:65be27845400	87	HAL_HRTIM_STATE_BUSY = 0x02U, /!< an internal process is ongoing /
AnnaBridge	172:65be27845400	88	HAL_HRTIM_STATE_TIMEOUT = 0x06U, /!< Timeout state /
AnnaBridge	172:65be27845400	89	HAL_HRTIM_STATE_ERROR = 0x07U, /!< Error state /
AnnaBridge	172:65be27845400	90	#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
AnnaBridge	172:65be27845400	91	HAL_HRTIM_STATE_INVALID_CALLBACK = 0x08U /!< Invalid Callback error /
AnnaBridge	172:65be27845400	92	#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
AnnaBridge	172:65be27845400	93	} HAL_HRTIM_StateTypeDef;
AnnaBridge	172:65be27845400	94
AnnaBridge	172:65be27845400	95	/**
AnnaBridge	172:65be27845400	96	* @brief HRTIM Timer Structure definition
AnnaBridge	172:65be27845400	97	*/
AnnaBridge	172:65be27845400	98	typedef struct
AnnaBridge	172:65be27845400	99	{
AnnaBridge	172:65be27845400	100	uint32_t CaptureTrigger1; /*!< Event(s) triggering capture unit 1.
AnnaBridge	172:65be27845400	101	When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels.
AnnaBridge	172:65be27845400	102	When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */
AnnaBridge	172:65be27845400	103	uint32_t CaptureTrigger2; /*!< Event(s) triggering capture unit 2.
AnnaBridge	172:65be27845400	104	When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels.
AnnaBridge	172:65be27845400	105	When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */
AnnaBridge	172:65be27845400	106	uint32_t InterruptRequests; /!< Interrupts requests enabled for the timer. /
AnnaBridge	172:65be27845400	107	uint32_t DMARequests; /!< DMA requests enabled for the timer. /
AnnaBridge	172:65be27845400	108	uint32_t DMASrcAddress; /!< Address of the source address of the DMA transfer. /
AnnaBridge	172:65be27845400	109	uint32_t DMADstAddress; /!< Address of the destination address of the DMA transfer. /
AnnaBridge	172:65be27845400	110	uint32_t DMASize; /!< Size of the DMA transfer /
AnnaBridge	172:65be27845400	111	} HRTIM_TimerParamTypeDef;
AnnaBridge	172:65be27845400	112
AnnaBridge	172:65be27845400	113	/**
AnnaBridge	172:65be27845400	114	* @brief HRTIM Handle Structure definition
AnnaBridge	172:65be27845400	115	*/
AnnaBridge	172:65be27845400	116	#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
AnnaBridge	172:65be27845400	117	typedef struct __HRTIM_HandleTypeDef
AnnaBridge	172:65be27845400	118	#else
AnnaBridge	172:65be27845400	119	typedef struct
AnnaBridge	172:65be27845400	120	#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
AnnaBridge	172:65be27845400	121	{
AnnaBridge	172:65be27845400	122	HRTIM_TypeDef * Instance; /!< Register base address /
AnnaBridge	172:65be27845400	123
AnnaBridge	172:65be27845400	124	HRTIM_InitTypeDef Init; /!< HRTIM required parameters /
AnnaBridge	172:65be27845400	125
AnnaBridge	172:65be27845400	126	HRTIM_TimerParamTypeDef TimerParam[MAX_HRTIM_TIMER]; /!< HRTIM timers - including the master - parameters /
AnnaBridge	172:65be27845400	127
AnnaBridge	172:65be27845400	128	HAL_LockTypeDef Lock; /!< Locking object /
AnnaBridge	172:65be27845400	129
AnnaBridge	172:65be27845400	130	__IO HAL_HRTIM_StateTypeDef State; /!< HRTIM communication state /
AnnaBridge	172:65be27845400	131
AnnaBridge	172:65be27845400	132	DMA_HandleTypeDef * hdmaMaster; /!< Master timer DMA handle parameters /
AnnaBridge	172:65be27845400	133	DMA_HandleTypeDef * hdmaTimerA; /!< Timer A DMA handle parameters /
AnnaBridge	172:65be27845400	134	DMA_HandleTypeDef * hdmaTimerB; /!< Timer B DMA handle parameters /
AnnaBridge	172:65be27845400	135	DMA_HandleTypeDef * hdmaTimerC; /!< Timer C DMA handle parameters /
AnnaBridge	172:65be27845400	136	DMA_HandleTypeDef * hdmaTimerD; /!< Timer D DMA handle parameters /
AnnaBridge	172:65be27845400	137	DMA_HandleTypeDef * hdmaTimerE; /!< Timer E DMA handle parameters /
AnnaBridge	172:65be27845400	138
AnnaBridge	172:65be27845400	139	#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
AnnaBridge	172:65be27845400	140	void (* Fault1Callback)(struct __HRTIM_HandleTypeDef hhrtim); /!< Fault 1 interrupt callback function pointer */
AnnaBridge	172:65be27845400	141	void (* Fault2Callback)(struct __HRTIM_HandleTypeDef hhrtim); /!< Fault 2 interrupt callback function pointer */
AnnaBridge	172:65be27845400	142	void (* Fault3Callback)(struct __HRTIM_HandleTypeDef hhrtim); /!< Fault 3 interrupt callback function pointer */
AnnaBridge	172:65be27845400	143	void (* Fault4Callback)(struct __HRTIM_HandleTypeDef hhrtim); /!< Fault 4 interrupt callback function pointer */
AnnaBridge	172:65be27845400	144	void (* Fault5Callback)(struct __HRTIM_HandleTypeDef hhrtim); /!< Fault 5 interrupt callback function pointer */
AnnaBridge	172:65be27845400	145	void (* SystemFaultCallback)(struct __HRTIM_HandleTypeDef hhrtim); /!< System fault interrupt callback function pointer */
AnnaBridge	172:65be27845400	146	void (* BurstModePeriodCallback)(struct __HRTIM_HandleTypeDef hhrtim); /!< Burst mode period interrupt callback function pointer */
AnnaBridge	172:65be27845400	147	void (* SynchronizationEventCallback)(struct __HRTIM_HandleTypeDef hhrtim); /!< Sync Input interrupt callback function pointer */
AnnaBridge	172:65be27845400	148	void (* ErrorCallback)(struct __HRTIM_HandleTypeDef hhrtim); /!< DMA error callback function pointer */
AnnaBridge	172:65be27845400	149
AnnaBridge	172:65be27845400	150	void (* RegistersUpdateCallback)(struct __HRTIM_HandleTypeDef hhrtim, uint32_t TimerIdx); /!< Timer x Update interrupt callback function pointer */
AnnaBridge	172:65be27845400	151	void (* RepetitionEventCallback)(struct __HRTIM_HandleTypeDef hhrtim, uint32_t TimerIdx); /!< Timer x Repetition interrupt callback function pointer */
AnnaBridge	172:65be27845400	152	void (* Compare1EventCallback)(struct __HRTIM_HandleTypeDef hhrtim, uint32_t TimerIdx); /!< Timer x Compare 1 match interrupt callback function pointer */
AnnaBridge	172:65be27845400	153	void (* Compare2EventCallback)(struct __HRTIM_HandleTypeDef hhrtim, uint32_t TimerIdx); /!< Timer x Compare 2 match interrupt callback function pointer */
AnnaBridge	172:65be27845400	154	void (* Compare3EventCallback)(struct __HRTIM_HandleTypeDef hhrtim, uint32_t TimerIdx); /!< Timer x Compare 3 match interrupt callback function pointer */
AnnaBridge	172:65be27845400	155	void (* Compare4EventCallback)(struct __HRTIM_HandleTypeDef hhrtim, uint32_t TimerIdx); /!< Timer x Compare 4 match interrupt callback function pointer */
AnnaBridge	172:65be27845400	156	void (* Capture1EventCallback)(struct __HRTIM_HandleTypeDef hhrtim, uint32_t TimerIdx); /!< Timer x Capture 1 interrupts callback function pointer */
AnnaBridge	172:65be27845400	157	void (* Capture2EventCallback)(struct __HRTIM_HandleTypeDef hhrtim, uint32_t TimerIdx); /!< Timer x Capture 2 interrupts callback function pointer */
AnnaBridge	172:65be27845400	158	void (* DelayedProtectionCallback)(struct __HRTIM_HandleTypeDef hhrtim, uint32_t TimerIdx); /!< Timer x Delayed protection interrupt callback function pointer */
AnnaBridge	172:65be27845400	159	void (* CounterResetCallback)(struct __HRTIM_HandleTypeDef hhrtim, uint32_t TimerIdx); /!< Timer x counter reset/roll-over interrupt callback function pointer */
AnnaBridge	172:65be27845400	160	void (* Output1SetCallback)(struct __HRTIM_HandleTypeDef hhrtim, uint32_t TimerIdx); /!< Timer x output 1 set interrupt callback function pointer */
AnnaBridge	172:65be27845400	161	void (* Output1ResetCallback)(struct __HRTIM_HandleTypeDef hhrtim, uint32_t TimerIdx); /!< Timer x output 1 reset interrupt callback function pointer */
AnnaBridge	172:65be27845400	162	void (* Output2SetCallback)(struct __HRTIM_HandleTypeDef hhrtim, uint32_t TimerIdx); /!< Timer x output 2 set interrupt callback function pointer */
AnnaBridge	172:65be27845400	163	void (* Output2ResetCallback)(struct __HRTIM_HandleTypeDef hhrtim, uint32_t TimerIdx); /!< Timer x output 2 reset interrupt callback function pointer */
AnnaBridge	172:65be27845400	164	void (* BurstDMATransferCallback)(struct __HRTIM_HandleTypeDef hhrtim, uint32_t TimerIdx); /!< Timer x Burst DMA completed interrupt callback function pointer */
AnnaBridge	172:65be27845400	165
AnnaBridge	172:65be27845400	166	void (* MspInitCallback)(struct __HRTIM_HandleTypeDef hhrtim); /!< HRTIM MspInit callback function pointer */
AnnaBridge	172:65be27845400	167	void (* MspDeInitCallback)(struct __HRTIM_HandleTypeDef hhrtim); /!< HRTIM MspInit callback function pointer */
AnnaBridge	172:65be27845400	168	#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
AnnaBridge	172:65be27845400	169	} HRTIM_HandleTypeDef;
AnnaBridge	172:65be27845400	170
AnnaBridge	172:65be27845400	171	/**
AnnaBridge	172:65be27845400	172	* @brief Simple output compare mode configuration definition
AnnaBridge	172:65be27845400	173	*/
AnnaBridge	172:65be27845400	174	typedef struct {
AnnaBridge	172:65be27845400	175	uint32_t Period; /*!< Specifies the timer period.
AnnaBridge	172:65be27845400	176	The period value must be above 3 periods of the fHRTIM clock.
AnnaBridge	172:65be27845400	177	Maximum value is = 0xFFDFU */
AnnaBridge	172:65be27845400	178	uint32_t RepetitionCounter; /*!< Specifies the timer repetition period.
AnnaBridge	172:65be27845400	179	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
AnnaBridge	172:65be27845400	180	uint32_t PrescalerRatio; /*!< Specifies the timer clock prescaler ratio.
AnnaBridge	172:65be27845400	181	This parameter can be any value of @ref HRTIM_Prescaler_Ratio */
AnnaBridge	172:65be27845400	182	uint32_t Mode; /*!< Specifies the counter operating mode.
AnnaBridge	172:65be27845400	183	This parameter can be any value of @ref HRTIM_Counter_Operating_Mode */
AnnaBridge	172:65be27845400	184	} HRTIM_TimeBaseCfgTypeDef;
AnnaBridge	172:65be27845400	185
AnnaBridge	172:65be27845400	186	/**
AnnaBridge	172:65be27845400	187	* @brief Simple output compare mode configuration definition
AnnaBridge	172:65be27845400	188	*/
AnnaBridge	172:65be27845400	189	typedef struct {
AnnaBridge	172:65be27845400	190	uint32_t Mode; /*!< Specifies the output compare mode (toggle, active, inactive).
AnnaBridge	172:65be27845400	191	This parameter can be any value of of @ref HRTIM_Simple_OC_Mode */
AnnaBridge	172:65be27845400	192	uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
AnnaBridge	172:65be27845400	193	The compare value must be above or equal to 3 periods of the fHRTIM clock */
AnnaBridge	172:65be27845400	194	uint32_t Polarity; /*!< Specifies the output polarity.
AnnaBridge	172:65be27845400	195	This parameter can be any value of @ref HRTIM_Output_Polarity */
AnnaBridge	172:65be27845400	196	uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state.
AnnaBridge	172:65be27845400	197	This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
AnnaBridge	172:65be27845400	198	} HRTIM_SimpleOCChannelCfgTypeDef;
AnnaBridge	172:65be27845400	199
AnnaBridge	172:65be27845400	200	/**
AnnaBridge	172:65be27845400	201	* @brief Simple PWM output mode configuration definition
AnnaBridge	172:65be27845400	202	*/
AnnaBridge	172:65be27845400	203	typedef struct {
AnnaBridge	172:65be27845400	204	uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
AnnaBridge	172:65be27845400	205	The compare value must be above or equal to 3 periods of the fHRTIM clock */
AnnaBridge	172:65be27845400	206	uint32_t Polarity; /*!< Specifies the output polarity.
AnnaBridge	172:65be27845400	207	This parameter can be any value of @ref HRTIM_Output_Polarity */
AnnaBridge	172:65be27845400	208	uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state.
AnnaBridge	172:65be27845400	209	This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
AnnaBridge	172:65be27845400	210	} HRTIM_SimplePWMChannelCfgTypeDef;
AnnaBridge	172:65be27845400	211
AnnaBridge	172:65be27845400	212	/**
AnnaBridge	172:65be27845400	213	* @brief Simple capture mode configuration definition
AnnaBridge	172:65be27845400	214	*/
AnnaBridge	172:65be27845400	215	typedef struct {
AnnaBridge	172:65be27845400	216	uint32_t Event; /*!< Specifies the external event triggering the capture.
AnnaBridge	172:65be27845400	217	This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
AnnaBridge	172:65be27845400	218	uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity).
AnnaBridge	172:65be27845400	219	This parameter can be a value of @ref HRTIM_External_Event_Polarity */
AnnaBridge	172:65be27845400	220	uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event.
AnnaBridge	172:65be27845400	221	This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
AnnaBridge	172:65be27845400	222	uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
AnnaBridge	172:65be27845400	223	This parameter can be a value of @ref HRTIM_External_Event_Filter */
AnnaBridge	172:65be27845400	224	} HRTIM_SimpleCaptureChannelCfgTypeDef;
AnnaBridge	172:65be27845400	225
AnnaBridge	172:65be27845400	226	/**
AnnaBridge	172:65be27845400	227	* @brief Simple One Pulse mode configuration definition
AnnaBridge	172:65be27845400	228	*/
AnnaBridge	172:65be27845400	229	typedef struct {
AnnaBridge	172:65be27845400	230	uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
AnnaBridge	172:65be27845400	231	The compare value must be above or equal to 3 periods of the fHRTIM clock */
AnnaBridge	172:65be27845400	232	uint32_t OutputPolarity; /*!< Specifies the output polarity.
AnnaBridge	172:65be27845400	233	This parameter can be any value of @ref HRTIM_Output_Polarity */
AnnaBridge	172:65be27845400	234	uint32_t OutputIdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state.
AnnaBridge	172:65be27845400	235	This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
AnnaBridge	172:65be27845400	236	uint32_t Event; /*!< Specifies the external event triggering the pulse generation.
AnnaBridge	172:65be27845400	237	This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
AnnaBridge	172:65be27845400	238	uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity).
AnnaBridge	172:65be27845400	239	This parameter can be a value of @ref HRTIM_External_Event_Polarity */
AnnaBridge	172:65be27845400	240	uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event.
AnnaBridge	172:65be27845400	241	This parameter can be a value of @ref HRTIM_External_Event_Sensitivity. */
AnnaBridge	172:65be27845400	242	uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
AnnaBridge	172:65be27845400	243	This parameter can be a value of @ref HRTIM_External_Event_Filter */
AnnaBridge	172:65be27845400	244	} HRTIM_SimpleOnePulseChannelCfgTypeDef;
AnnaBridge	172:65be27845400	245
AnnaBridge	172:65be27845400	246	/**
AnnaBridge	172:65be27845400	247	* @brief Timer configuration definition
AnnaBridge	172:65be27845400	248	*/
AnnaBridge	172:65be27845400	249	typedef struct {
AnnaBridge	172:65be27845400	250	uint32_t InterruptRequests; /*!< Relevant for all HRTIM timers, including the master.
AnnaBridge	172:65be27845400	251	Specifies which interrupts requests must enabled for the timer.
AnnaBridge	172:65be27845400	252	This parameter can be any combination of @ref HRTIM_Master_Interrupt_Enable
AnnaBridge	172:65be27845400	253	or @ref HRTIM_Timing_Unit_Interrupt_Enable */
AnnaBridge	172:65be27845400	254	uint32_t DMARequests; /*!< Relevant for all HRTIM timers, including the master.
AnnaBridge	172:65be27845400	255	Specifies which DMA requests must be enabled for the timer.
AnnaBridge	172:65be27845400	256	This parameter can be any combination of @ref HRTIM_Master_DMA_Request_Enable
AnnaBridge	172:65be27845400	257	or @ref HRTIM_Timing_Unit_DMA_Request_Enable */
AnnaBridge	172:65be27845400	258	uint32_t DMASrcAddress; /*!< Relevant for all HRTIM timers, including the master.
AnnaBridge	172:65be27845400	259	Specifies the address of the source address of the DMA transfer */
AnnaBridge	172:65be27845400	260	uint32_t DMADstAddress; /*!< Relevant for all HRTIM timers, including the master.
AnnaBridge	172:65be27845400	261	Specifies the address of the destination address of the DMA transfer */
AnnaBridge	172:65be27845400	262	uint32_t DMASize; /*!< Relevant for all HRTIM timers, including the master.
AnnaBridge	172:65be27845400	263	Specifies the size of the DMA transfer */
AnnaBridge	172:65be27845400	264	uint32_t HalfModeEnable; /*!< Relevant for all HRTIM timers, including the master.
AnnaBridge	172:65be27845400	265	Specifies whether or not half mode is enabled
AnnaBridge	172:65be27845400	266	This parameter can be any value of @ref HRTIM_Half_Mode_Enable */
AnnaBridge	172:65be27845400	267	uint32_t StartOnSync; /*!< Relevant for all HRTIM timers, including the master.
AnnaBridge	172:65be27845400	268	Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled).
AnnaBridge	172:65be27845400	269	This parameter can be any value of @ref HRTIM_Start_On_Sync_Input_Event */
AnnaBridge	172:65be27845400	270	uint32_t ResetOnSync; /*!< Relevant for all HRTIM timers, including the master.
AnnaBridge	172:65be27845400	271	Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled).
AnnaBridge	172:65be27845400	272	This parameter can be any value of @ref HRTIM_Reset_On_Sync_Input_Event */
AnnaBridge	172:65be27845400	273	uint32_t DACSynchro; /*!< Relevant for all HRTIM timers, including the master.
AnnaBridge	172:65be27845400	274	Indicates whether or not the a DAC synchronization event is generated.
AnnaBridge	172:65be27845400	275	This parameter can be any value of @ref HRTIM_DAC_Synchronization */
AnnaBridge	172:65be27845400	276	uint32_t PreloadEnable; /*!< Relevant for all HRTIM timers, including the master.
AnnaBridge	172:65be27845400	277	Specifies whether or not register preload is enabled.
AnnaBridge	172:65be27845400	278	This parameter can be any value of @ref HRTIM_Register_Preload_Enable */
AnnaBridge	172:65be27845400	279	uint32_t UpdateGating; /*!< Relevant for all HRTIM timers, including the master.
AnnaBridge	172:65be27845400	280	Specifies how the update occurs with respect to a burst DMA transaction or
AnnaBridge	172:65be27845400	281	update enable inputs (Slave timers only).
AnnaBridge	172:65be27845400	282	This parameter can be any value of @ref HRTIM_Update_Gating */
AnnaBridge	172:65be27845400	283	uint32_t BurstMode; /*!< Relevant for all HRTIM timers, including the master.
AnnaBridge	172:65be27845400	284	Specifies how the timer behaves during a burst mode operation.
AnnaBridge	172:65be27845400	285	This parameter can be any value of @ref HRTIM_Timer_Burst_Mode */
AnnaBridge	172:65be27845400	286	uint32_t RepetitionUpdate; /*!< Relevant for all HRTIM timers, including the master.
AnnaBridge	172:65be27845400	287	Specifies whether or not registers update is triggered by the repetition event.
AnnaBridge	172:65be27845400	288	This parameter can be any value of @ref HRTIM_Timer_Repetition_Update */
AnnaBridge	172:65be27845400	289	uint32_t PushPull; /*!< Relevant for Timer A to Timer E.
AnnaBridge	172:65be27845400	290	Specifies whether or not the push-pull mode is enabled.
AnnaBridge	172:65be27845400	291	This parameter can be any value of @ref HRTIM_Timer_Push_Pull_Mode */
AnnaBridge	172:65be27845400	292	uint32_t FaultEnable; /*!< Relevant for Timer A to Timer E.
AnnaBridge	172:65be27845400	293	Specifies which fault channels are enabled for the timer.
AnnaBridge	172:65be27845400	294	This parameter can be a combination of @ref HRTIM_Timer_Fault_Enabling */
AnnaBridge	172:65be27845400	295	uint32_t FaultLock; /*!< Relevant for Timer A to Timer E.
AnnaBridge	172:65be27845400	296	Specifies whether or not fault enabling status is write protected.
AnnaBridge	172:65be27845400	297	This parameter can be a value of @ref HRTIM_Timer_Fault_Lock */
AnnaBridge	172:65be27845400	298	uint32_t DeadTimeInsertion; /*!< Relevant for Timer A to Timer E.
AnnaBridge	172:65be27845400	299	Specifies whether or not dead-time insertion is enabled for the timer.
AnnaBridge	172:65be27845400	300	This parameter can be a value of @ref HRTIM_Timer_Deadtime_Insertion */
AnnaBridge	172:65be27845400	301	uint32_t DelayedProtectionMode; /*!< Relevant for Timer A to Timer E.
AnnaBridge	172:65be27845400	302	Specifies the delayed protection mode.
AnnaBridge	172:65be27845400	303	This parameter can be a value of @ref HRTIM_Timer_Delayed_Protection_Mode */
AnnaBridge	172:65be27845400	304	uint32_t UpdateTrigger; /*!< Relevant for Timer A to Timer E.
AnnaBridge	172:65be27845400	305	Specifies source(s) triggering the timer registers update.
AnnaBridge	172:65be27845400	306	This parameter can be a combination of @ref HRTIM_Timer_Update_Trigger */
AnnaBridge	172:65be27845400	307	uint32_t ResetTrigger; /*!< Relevant for Timer A to Timer E.
AnnaBridge	172:65be27845400	308	Specifies source(s) triggering the timer counter reset.
AnnaBridge	172:65be27845400	309	This parameter can be a combination of @ref HRTIM_Timer_Reset_Trigger */
AnnaBridge	172:65be27845400	310	uint32_t ResetUpdate; /*!< Relevant for Timer A to Timer E.
AnnaBridge	172:65be27845400	311	Specifies whether or not registers update is triggered when the timer counter is reset.
AnnaBridge	172:65be27845400	312	This parameter can be a value of @ref HRTIM_Timer_Reset_Update */
AnnaBridge	172:65be27845400	313	} HRTIM_TimerCfgTypeDef;
AnnaBridge	172:65be27845400	314
AnnaBridge	172:65be27845400	315	/**
AnnaBridge	172:65be27845400	316	* @brief Compare unit configuration definition
AnnaBridge	172:65be27845400	317	*/
AnnaBridge	172:65be27845400	318	typedef struct {
AnnaBridge	172:65be27845400	319	uint32_t CompareValue; /*!< Specifies the compare value of the timer compare unit.
AnnaBridge	172:65be27845400	320	The minimum value must be greater than or equal to 3 periods of the fHRTIM clock.
AnnaBridge	172:65be27845400	321	The maximum value must be less than or equal to 0xFFFFU - 1 periods of the fHRTIM clock */
AnnaBridge	172:65be27845400	322	uint32_t AutoDelayedMode; /*!< Specifies the auto delayed mode for compare unit 2 or 4.
AnnaBridge	172:65be27845400	323	This parameter can be a value of @ref HRTIM_Compare_Unit_Auto_Delayed_Mode */
AnnaBridge	172:65be27845400	324	uint32_t AutoDelayedTimeout; /*!< Specifies compare value for timing unit 1 or 3 when auto delayed mode with time out is selected.
AnnaBridge	172:65be27845400	325	CompareValue + AutoDelayedTimeout must be less than 0xFFFFU */
AnnaBridge	172:65be27845400	326	} HRTIM_CompareCfgTypeDef;
AnnaBridge	172:65be27845400	327
AnnaBridge	172:65be27845400	328	/**
AnnaBridge	172:65be27845400	329	* @brief Capture unit configuration definition
AnnaBridge	172:65be27845400	330	*/
AnnaBridge	172:65be27845400	331	typedef struct {
AnnaBridge	172:65be27845400	332	uint32_t Trigger; /*!< Specifies source(s) triggering the capture.
AnnaBridge	172:65be27845400	333	This parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger */
AnnaBridge	172:65be27845400	334	} HRTIM_CaptureCfgTypeDef;
AnnaBridge	172:65be27845400	335
AnnaBridge	172:65be27845400	336	/**
AnnaBridge	172:65be27845400	337	* @brief Output configuration definition
AnnaBridge	172:65be27845400	338	*/
AnnaBridge	172:65be27845400	339	typedef struct {
AnnaBridge	172:65be27845400	340	uint32_t Polarity; /*!< Specifies the output polarity.
AnnaBridge	172:65be27845400	341	This parameter can be any value of @ref HRTIM_Output_Polarity */
AnnaBridge	172:65be27845400	342	uint32_t SetSource; /*!< Specifies the event(s) transitioning the output from its inactive level to its active level.
AnnaBridge	172:65be27845400	343	This parameter can be a combination of @ref HRTIM_Output_Set_Source */
AnnaBridge	172:65be27845400	344	uint32_t ResetSource; /*!< Specifies the event(s) transitioning the output from its active level to its inactive level.
AnnaBridge	172:65be27845400	345	This parameter can be a combination of @ref HRTIM_Output_Reset_Source */
AnnaBridge	172:65be27845400	346	uint32_t IdleMode; /*!< Specifies whether or not the output is affected by a burst mode operation.
AnnaBridge	172:65be27845400	347	This parameter can be any value of @ref HRTIM_Output_Idle_Mode */
AnnaBridge	172:65be27845400	348	uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state.
AnnaBridge	172:65be27845400	349	This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
AnnaBridge	172:65be27845400	350	uint32_t FaultLevel; /*!< Specifies whether the output level is active or inactive when in FAULT state.
AnnaBridge	172:65be27845400	351	This parameter can be any value of @ref HRTIM_Output_FAULT_Level */
AnnaBridge	172:65be27845400	352	uint32_t ChopperModeEnable; /*!< Indicates whether or not the chopper mode is enabled
AnnaBridge	172:65be27845400	353	This parameter can be any value of @ref HRTIM_Output_Chopper_Mode_Enable */
AnnaBridge	172:65be27845400	354	uint32_t BurstModeEntryDelayed; /*!< Indicates whether or not dead-time is inserted when entering the IDLE state during a burst mode operation.
AnnaBridge	172:65be27845400	355	This parameters can be any value of @ref HRTIM_Output_Burst_Mode_Entry_Delayed */
AnnaBridge	172:65be27845400	356	} HRTIM_OutputCfgTypeDef;
AnnaBridge	172:65be27845400	357
AnnaBridge	172:65be27845400	358	/**
AnnaBridge	172:65be27845400	359	* @brief External event filtering in timing units configuration definition
AnnaBridge	172:65be27845400	360	*/
AnnaBridge	172:65be27845400	361	typedef struct {
AnnaBridge	172:65be27845400	362	uint32_t Filter; /*!< Specifies the type of event filtering within the timing unit.
AnnaBridge	172:65be27845400	363	This parameter can be a value of @ref HRTIM_Timer_External_Event_Filter */
AnnaBridge	172:65be27845400	364	uint32_t Latch; /*!< Specifies whether or not the signal is latched.
AnnaBridge	172:65be27845400	365	This parameter can be a value of @ref HRTIM_Timer_External_Event_Latch */
AnnaBridge	172:65be27845400	366	} HRTIM_TimerEventFilteringCfgTypeDef;
AnnaBridge	172:65be27845400	367
AnnaBridge	172:65be27845400	368	/**
AnnaBridge	172:65be27845400	369	* @brief Dead time feature configuration definition
AnnaBridge	172:65be27845400	370	*/
AnnaBridge	172:65be27845400	371	typedef struct {
AnnaBridge	172:65be27845400	372	uint32_t Prescaler; /*!< Specifies the dead-time prescaler.
AnnaBridge	172:65be27845400	373	This parameter can be a value of @ref HRTIM_Deadtime_Prescaler_Ratio */
AnnaBridge	172:65be27845400	374	uint32_t RisingValue; /*!< Specifies the dead-time following a rising edge.
AnnaBridge	172:65be27845400	375	This parameter can be a number between 0x0 and 0x1FFU */
AnnaBridge	172:65be27845400	376	uint32_t RisingSign; /*!< Specifies whether the dead-time is positive or negative on rising edge.
AnnaBridge	172:65be27845400	377	This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign */
AnnaBridge	172:65be27845400	378	uint32_t RisingLock; /*!< Specifies whether or not dead-time rising settings (value and sign) are write protected.
AnnaBridge	172:65be27845400	379	This parameter can be a value of @ref HRTIM_Deadtime_Rising_Lock */
AnnaBridge	172:65be27845400	380	uint32_t RisingSignLock; /*!< Specifies whether or not dead-time rising sign is write protected.
AnnaBridge	172:65be27845400	381	This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign_Lock */
AnnaBridge	172:65be27845400	382	uint32_t FallingValue; /*!< Specifies the dead-time following a falling edge.
AnnaBridge	172:65be27845400	383	This parameter can be a number between 0x0 and 0x1FFU */
AnnaBridge	172:65be27845400	384	uint32_t FallingSign; /*!< Specifies whether the dead-time is positive or negative on falling edge.
AnnaBridge	172:65be27845400	385	This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign */
AnnaBridge	172:65be27845400	386	uint32_t FallingLock; /*!< Specifies whether or not dead-time falling settings (value and sign) are write protected.
AnnaBridge	172:65be27845400	387	This parameter can be a value of @ref HRTIM_Deadtime_Falling_Lock */
AnnaBridge	172:65be27845400	388	uint32_t FallingSignLock; /*!< Specifies whether or not dead-time falling sign is write protected.
AnnaBridge	172:65be27845400	389	This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign_Lock */
AnnaBridge	172:65be27845400	390	} HRTIM_DeadTimeCfgTypeDef ;
AnnaBridge	172:65be27845400	391
AnnaBridge	172:65be27845400	392	/**
AnnaBridge	172:65be27845400	393	* @brief Chopper mode configuration definition
AnnaBridge	172:65be27845400	394	*/
AnnaBridge	172:65be27845400	395	typedef struct {
AnnaBridge	172:65be27845400	396	uint32_t CarrierFreq; /*!< Specifies the Timer carrier frequency value.
AnnaBridge	172:65be27845400	397	This parameter can be a value of @ref HRTIM_Chopper_Frequency */
AnnaBridge	172:65be27845400	398	uint32_t DutyCycle; /*!< Specifies the Timer chopper duty cycle value.
AnnaBridge	172:65be27845400	399	This parameter can be a value of @ref HRTIM_Chopper_Duty_Cycle */
AnnaBridge	172:65be27845400	400	uint32_t StartPulse; /*!< Specifies the Timer pulse width value.
AnnaBridge	172:65be27845400	401	This parameter can be a value of @ref HRTIM_Chopper_Start_Pulse_Width */
AnnaBridge	172:65be27845400	402	} HRTIM_ChopperModeCfgTypeDef;
AnnaBridge	172:65be27845400	403
AnnaBridge	172:65be27845400	404	/**
AnnaBridge	172:65be27845400	405	* @brief External event channel configuration definition
AnnaBridge	172:65be27845400	406	*/
AnnaBridge	172:65be27845400	407	typedef struct {
AnnaBridge	172:65be27845400	408	uint32_t Source; /*!< Identifies the source of the external event.
AnnaBridge	172:65be27845400	409	This parameter can be a value of @ref HRTIM_External_Event_Sources */
AnnaBridge	172:65be27845400	410	uint32_t Polarity; /*!< Specifies the polarity of the external event (in case of level sensitivity).
AnnaBridge	172:65be27845400	411	This parameter can be a value of @ref HRTIM_External_Event_Polarity */
AnnaBridge	172:65be27845400	412	uint32_t Sensitivity; /*!< Specifies the sensitivity of the external event.
AnnaBridge	172:65be27845400	413	This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
AnnaBridge	172:65be27845400	414	uint32_t Filter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
AnnaBridge	172:65be27845400	415	This parameter can be a value of @ref HRTIM_External_Event_Filter */
AnnaBridge	172:65be27845400	416	uint32_t FastMode; /*!< Indicates whether or not low latency mode is enabled for the external event.
AnnaBridge	172:65be27845400	417	This parameter can be a value of @ref HRTIM_External_Event_Fast_Mode */
AnnaBridge	172:65be27845400	418	} HRTIM_EventCfgTypeDef;
AnnaBridge	172:65be27845400	419
AnnaBridge	172:65be27845400	420	/**
AnnaBridge	172:65be27845400	421	* @brief Fault channel configuration definition
AnnaBridge	172:65be27845400	422	*/
AnnaBridge	172:65be27845400	423	typedef struct {
AnnaBridge	172:65be27845400	424	uint32_t Source; /*!< Identifies the source of the fault.
AnnaBridge	172:65be27845400	425	This parameter can be a value of @ref HRTIM_Fault_Sources */
AnnaBridge	172:65be27845400	426	uint32_t Polarity; /*!< Specifies the polarity of the fault event.
AnnaBridge	172:65be27845400	427	This parameter can be a value of @ref HRTIM_Fault_Polarity */
AnnaBridge	172:65be27845400	428	uint32_t Filter; /*!< Defines the frequency used to sample the Fault input and the length of the digital filter.
AnnaBridge	172:65be27845400	429	This parameter can be a value of @ref HRTIM_Fault_Filter */
AnnaBridge	172:65be27845400	430	uint32_t Lock; /*!< Indicates whether or not fault programming bits are write protected.
AnnaBridge	172:65be27845400	431	This parameter can be a value of @ref HRTIM_Fault_Lock */
AnnaBridge	172:65be27845400	432	} HRTIM_FaultCfgTypeDef;
AnnaBridge	172:65be27845400	433
AnnaBridge	172:65be27845400	434	/**
AnnaBridge	172:65be27845400	435	* @brief Burst mode configuration definition
AnnaBridge	172:65be27845400	436	*/
AnnaBridge	172:65be27845400	437	typedef struct {
AnnaBridge	172:65be27845400	438	uint32_t Mode; /*!< Specifies the burst mode operating mode.
AnnaBridge	172:65be27845400	439	This parameter can be a value of @ref HRTIM_Burst_Mode_Operating_Mode */
AnnaBridge	172:65be27845400	440	uint32_t ClockSource; /*!< Specifies the burst mode clock source.
AnnaBridge	172:65be27845400	441	This parameter can be a value of @ref HRTIM_Burst_Mode_Clock_Source */
AnnaBridge	172:65be27845400	442	uint32_t Prescaler; /*!< Specifies the burst mode prescaler.
AnnaBridge	172:65be27845400	443	This parameter can be a value of @ref HRTIM_Burst_Mode_Prescaler */
AnnaBridge	172:65be27845400	444	uint32_t PreloadEnable; /*!< Specifies whether or not preload is enabled for burst mode related registers (HRTIM_BMCMPR and HRTIM_BMPER).
AnnaBridge	172:65be27845400	445	This parameter can be a combination of @ref HRTIM_Burst_Mode_Register_Preload_Enable */
AnnaBridge	172:65be27845400	446	uint32_t Trigger; /*!< Specifies the event(s) triggering the burst operation.
AnnaBridge	172:65be27845400	447	This parameter can be a combination of @ref HRTIM_Burst_Mode_Trigger */
AnnaBridge	172:65be27845400	448	uint32_t IdleDuration; /*!< Specifies number of periods during which the selected timers are in idle state.
AnnaBridge	172:65be27845400	449	This parameter can be a number between 0x0 and 0xFFFF */
AnnaBridge	172:65be27845400	450	uint32_t Period; /*!< Specifies burst mode repetition period.
AnnaBridge	172:65be27845400	451	This parameter can be a number between 0x1 and 0xFFFF */
AnnaBridge	172:65be27845400	452	} HRTIM_BurstModeCfgTypeDef;
AnnaBridge	172:65be27845400	453
AnnaBridge	172:65be27845400	454	/**
AnnaBridge	172:65be27845400	455	* @brief ADC trigger configuration definition
AnnaBridge	172:65be27845400	456	*/
AnnaBridge	172:65be27845400	457	typedef struct {
AnnaBridge	172:65be27845400	458	uint32_t UpdateSource; /*!< Specifies the ADC trigger update source.
AnnaBridge	172:65be27845400	459	This parameter can be a value of @ref HRTIM_ADC_Trigger_Update_Source */
AnnaBridge	172:65be27845400	460	uint32_t Trigger; /*!< Specifies the event(s) triggering the ADC conversion.
AnnaBridge	172:65be27845400	461	This parameter can be a combination of @ref HRTIM_ADC_Trigger_Event */
AnnaBridge	172:65be27845400	462	} HRTIM_ADCTriggerCfgTypeDef;
AnnaBridge	172:65be27845400	463
AnnaBridge	172:65be27845400	464	#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
AnnaBridge	172:65be27845400	465	/**
AnnaBridge	172:65be27845400	466	* @brief HAL HRTIM Callback ID enumeration definition
AnnaBridge	172:65be27845400	467	*/
AnnaBridge	172:65be27845400	468	typedef enum {
AnnaBridge	172:65be27845400	469	HAL_HRTIM_FAULT1CALLBACK_CB_ID = 0x00U, /!< Fault 1 interrupt callback ID /
AnnaBridge	172:65be27845400	470	HAL_HRTIM_FAULT2CALLBACK_CB_ID = 0x01U, /!< Fault 2 interrupt callback ID /
AnnaBridge	172:65be27845400	471	HAL_HRTIM_FAULT3CALLBACK_CB_ID = 0x02U, /!< Fault 3 interrupt callback ID /
AnnaBridge	172:65be27845400	472	HAL_HRTIM_FAULT4CALLBACK_CB_ID = 0x03U, /!< Fault 4 interrupt callback ID /
AnnaBridge	172:65be27845400	473	HAL_HRTIM_FAULT5CALLBACK_CB_ID = 0x04U, /!< Fault 5 interrupt callback ID /
AnnaBridge	172:65be27845400	474	HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID = 0x05U, /!< System fault interrupt callback ID /
AnnaBridge	172:65be27845400	475	HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID = 0x07U, /!< Burst mode period interrupt callback ID /
AnnaBridge	172:65be27845400	476	HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID = 0x08U, /!< Sync Input interrupt callback ID /
AnnaBridge	172:65be27845400	477	HAL_HRTIM_ERRORCALLBACK_CB_ID = 0x09U, /!< DMA error callback ID /
AnnaBridge	172:65be27845400	478
AnnaBridge	172:65be27845400	479	HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID = 0x10U, /!< Timer x Update interrupt callback ID /
AnnaBridge	172:65be27845400	480	HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID = 0x11U, /!< Timer x Repetition interrupt callback ID /
AnnaBridge	172:65be27845400	481	HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID = 0x12U, /!< Timer x Compare 1 match interrupt callback ID /
AnnaBridge	172:65be27845400	482	HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID = 0x13U, /!< Timer x Compare 2 match interrupt callback ID /
AnnaBridge	172:65be27845400	483	HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID = 0x14U, /!< Timer x Compare 3 match interrupt callback ID /
AnnaBridge	172:65be27845400	484	HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID = 0x15U, /!< Timer x Compare 4 match interrupt callback ID /
AnnaBridge	172:65be27845400	485	HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID = 0x16U, /!< Timer x Capture 1 interrupts callback ID /
AnnaBridge	172:65be27845400	486	HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID = 0x17U, /!< Timer x Capture 2 interrupts callback ID /
AnnaBridge	172:65be27845400	487	HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID = 0x18U, /!< Timer x Delayed protection interrupt callback ID /
AnnaBridge	172:65be27845400	488	HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID = 0x19U, /!< Timer x counter reset/roll-over interrupt callback ID /
AnnaBridge	172:65be27845400	489	HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID = 0x1AU, /!< Timer x output 1 set interrupt callback ID /
AnnaBridge	172:65be27845400	490	HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID = 0x1BU, /!< Timer x output 1 reset interrupt callback ID /
AnnaBridge	172:65be27845400	491	HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID = 0x1CU, /!< Timer x output 2 set interrupt callback ID /
AnnaBridge	172:65be27845400	492	HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID = 0x1DU, /!< Timer x output 2 reset interrupt callback ID /
AnnaBridge	172:65be27845400	493	HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID = 0x1EU, /!< Timer x Burst DMA completed interrupt callback ID /
AnnaBridge	172:65be27845400	494
AnnaBridge	172:65be27845400	495	HAL_HRTIM_MSPINIT_CB_ID = 0x20U, /!< HRTIM MspInit callback ID /
AnnaBridge	172:65be27845400	496	HAL_HRTIM_MSPDEINIT_CB_ID = 0x21U, /!< HRTIM MspInit callback ID /
AnnaBridge	172:65be27845400	497	}HAL_HRTIM_CallbackIDTypeDef;
AnnaBridge	172:65be27845400	498
AnnaBridge	172:65be27845400	499	/**
AnnaBridge	172:65be27845400	500	* @brief HAL HRTIM Callback function pointer definitions
AnnaBridge	172:65be27845400	501	*/
AnnaBridge	172:65be27845400	502	typedef void (* pHRTIM_CallbackTypeDef)(HRTIM_HandleTypeDef hhrtim); /!< HRTIM related callback function pointer */
AnnaBridge	172:65be27845400	503
AnnaBridge	172:65be27845400	504	typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef hhrtim, /!< HRTIM Timer x related callback function pointer */
AnnaBridge	172:65be27845400	505	uint32_t TimerIdx);
AnnaBridge	172:65be27845400	506	#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
AnnaBridge	172:65be27845400	507
AnnaBridge	172:65be27845400	508	/**
AnnaBridge	172:65be27845400	509	* @}
AnnaBridge	172:65be27845400	510	*/
AnnaBridge	172:65be27845400	511
AnnaBridge	172:65be27845400	512	/* Exported constants --------------------------------------------------------*/
AnnaBridge	172:65be27845400	513	/** @defgroup HRTIM_Exported_Constants HRTIM Exported Constants
AnnaBridge	172:65be27845400	514	* @{
AnnaBridge	172:65be27845400	515	*/
AnnaBridge	172:65be27845400	516
AnnaBridge	172:65be27845400	517	/** @defgroup HRTIM_Timer_Index HRTIM Timer Index
AnnaBridge	172:65be27845400	518	* @{
AnnaBridge	172:65be27845400	519	* @brief Constants defining the timer indexes
AnnaBridge	172:65be27845400	520	*/
AnnaBridge	172:65be27845400	521	#define HRTIM_TIMERINDEX_TIMER_A 0x0U /!< Index used to access timer A registers /
AnnaBridge	172:65be27845400	522	#define HRTIM_TIMERINDEX_TIMER_B 0x1U /!< Index used to access timer B registers /
AnnaBridge	172:65be27845400	523	#define HRTIM_TIMERINDEX_TIMER_C 0x2U /!< Index used to access timer C registers /
AnnaBridge	172:65be27845400	524	#define HRTIM_TIMERINDEX_TIMER_D 0x3U /!< Index used to access timer D registers /
AnnaBridge	172:65be27845400	525	#define HRTIM_TIMERINDEX_TIMER_E 0x4U /!< Index used to access timer E registers /
AnnaBridge	172:65be27845400	526	#define HRTIM_TIMERINDEX_MASTER 0x5U /!< Index used to access master registers /
AnnaBridge	172:65be27845400	527	#define HRTIM_TIMERINDEX_COMMON 0xFFU /!< Index used to access HRTIM common registers /
AnnaBridge	172:65be27845400	528	/**
AnnaBridge	172:65be27845400	529	* @}
AnnaBridge	172:65be27845400	530	*/
AnnaBridge	172:65be27845400	531
AnnaBridge	172:65be27845400	532	/** @defgroup HRTIM_Timer_identifier HRTIM Timer identifier
AnnaBridge	172:65be27845400	533	* @{
AnnaBridge	172:65be27845400	534	* @brief Constants defining timer identifiers
AnnaBridge	172:65be27845400	535	*/
AnnaBridge	172:65be27845400	536	#define HRTIM_TIMERID_MASTER (HRTIM_MCR_MCEN) /!< Master identifier /
AnnaBridge	172:65be27845400	537	#define HRTIM_TIMERID_TIMER_A (HRTIM_MCR_TACEN) /!< Timer A identifier /
AnnaBridge	172:65be27845400	538	#define HRTIM_TIMERID_TIMER_B (HRTIM_MCR_TBCEN) /!< Timer B identifier /
AnnaBridge	172:65be27845400	539	#define HRTIM_TIMERID_TIMER_C (HRTIM_MCR_TCCEN) /!< Timer C identifier /
AnnaBridge	172:65be27845400	540	#define HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN) /!< Timer D identifier /
AnnaBridge	172:65be27845400	541	#define HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN) /!< Timer E identifier /
AnnaBridge	172:65be27845400	542	/**
AnnaBridge	172:65be27845400	543	* @}
AnnaBridge	172:65be27845400	544	*/
AnnaBridge	172:65be27845400	545
AnnaBridge	172:65be27845400	546	/** @defgroup HRTIM_Compare_Unit HRTIM Compare Unit
AnnaBridge	172:65be27845400	547	* @{
AnnaBridge	172:65be27845400	548	* @brief Constants defining compare unit identifiers
AnnaBridge	172:65be27845400	549	*/
AnnaBridge	172:65be27845400	550	#define HRTIM_COMPAREUNIT_1 0x00000001U /!< Compare unit 1 identifier /
AnnaBridge	172:65be27845400	551	#define HRTIM_COMPAREUNIT_2 0x00000002U /!< Compare unit 2 identifier /
AnnaBridge	172:65be27845400	552	#define HRTIM_COMPAREUNIT_3 0x00000004U /!< Compare unit 3 identifier /
AnnaBridge	172:65be27845400	553	#define HRTIM_COMPAREUNIT_4 0x00000008U /!< Compare unit 4 identifier /
AnnaBridge	172:65be27845400	554	/**
AnnaBridge	172:65be27845400	555	* @}
AnnaBridge	172:65be27845400	556	*/
AnnaBridge	172:65be27845400	557
AnnaBridge	172:65be27845400	558	/** @defgroup HRTIM_Capture_Unit HRTIM Capture Unit
AnnaBridge	172:65be27845400	559	* @{
AnnaBridge	172:65be27845400	560	* @brief Constants defining capture unit identifiers
AnnaBridge	172:65be27845400	561	*/
AnnaBridge	172:65be27845400	562	#define HRTIM_CAPTUREUNIT_1 0x00000001U /!< Capture unit 1 identifier /
AnnaBridge	172:65be27845400	563	#define HRTIM_CAPTUREUNIT_2 0x00000002U /!< Capture unit 2 identifier /
AnnaBridge	172:65be27845400	564	/**
AnnaBridge	172:65be27845400	565	* @}
AnnaBridge	172:65be27845400	566	*/
AnnaBridge	172:65be27845400	567
AnnaBridge	172:65be27845400	568	/** @defgroup HRTIM_Timer_Output HRTIM Timer Output
AnnaBridge	172:65be27845400	569	* @{
AnnaBridge	172:65be27845400	570	* @brief Constants defining timer output identifiers
AnnaBridge	172:65be27845400	571	*/
AnnaBridge	172:65be27845400	572	#define HRTIM_OUTPUT_TA1 0x00000001U /!< Timer A - Output 1 identifier /
AnnaBridge	172:65be27845400	573	#define HRTIM_OUTPUT_TA2 0x00000002U /!< Timer A - Output 2 identifier /
AnnaBridge	172:65be27845400	574	#define HRTIM_OUTPUT_TB1 0x00000004U /!< Timer B - Output 1 identifier /
AnnaBridge	172:65be27845400	575	#define HRTIM_OUTPUT_TB2 0x00000008U /!< Timer B - Output 2 identifier /
AnnaBridge	172:65be27845400	576	#define HRTIM_OUTPUT_TC1 0x00000010U /!< Timer C - Output 1 identifier /
AnnaBridge	172:65be27845400	577	#define HRTIM_OUTPUT_TC2 0x00000020U /!< Timer C - Output 2 identifier /
AnnaBridge	172:65be27845400	578	#define HRTIM_OUTPUT_TD1 0x00000040U /!< Timer D - Output 1 identifier /
AnnaBridge	172:65be27845400	579	#define HRTIM_OUTPUT_TD2 0x00000080U /!< Timer D - Output 2 identifier /
AnnaBridge	172:65be27845400	580	#define HRTIM_OUTPUT_TE1 0x00000100U /!< Timer E - Output 1 identifier /
AnnaBridge	172:65be27845400	581	#define HRTIM_OUTPUT_TE2 0x00000200U /!< Timer E - Output 2 identifier /
AnnaBridge	172:65be27845400	582	/**
AnnaBridge	172:65be27845400	583	* @}
AnnaBridge	172:65be27845400	584	*/
AnnaBridge	172:65be27845400	585
AnnaBridge	172:65be27845400	586	/** @defgroup HRTIM_ADC_Trigger HRTIM ADC Trigger
AnnaBridge	172:65be27845400	587	* @{
AnnaBridge	172:65be27845400	588	* @brief Constants defining ADC triggers identifiers
AnnaBridge	172:65be27845400	589	*/
AnnaBridge	172:65be27845400	590	#define HRTIM_ADCTRIGGER_1 0x00000001U /!< ADC trigger 1 identifier /
AnnaBridge	172:65be27845400	591	#define HRTIM_ADCTRIGGER_2 0x00000002U /!< ADC trigger 2 identifier /
AnnaBridge	172:65be27845400	592	#define HRTIM_ADCTRIGGER_3 0x00000004U /!< ADC trigger 3 identifier /
AnnaBridge	172:65be27845400	593	#define HRTIM_ADCTRIGGER_4 0x00000008U /!< ADC trigger 4 identifier /
AnnaBridge	172:65be27845400	594
AnnaBridge	172:65be27845400	595	#define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\
AnnaBridge	172:65be27845400	596	(((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) \|\| \
AnnaBridge	172:65be27845400	597	((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) \|\| \
AnnaBridge	172:65be27845400	598	((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) \|\| \
AnnaBridge	172:65be27845400	599	((ADCTRIGGER) == HRTIM_ADCTRIGGER_4))
AnnaBridge	172:65be27845400	600	/**
AnnaBridge	172:65be27845400	601	* @}
AnnaBridge	172:65be27845400	602	*/
AnnaBridge	172:65be27845400	603	/** @defgroup HRTIM_External_Event_Channels HRTIM External Event Channels
AnnaBridge	172:65be27845400	604	* @{
AnnaBridge	172:65be27845400	605	* @brief Constants defining external event channel identifiers
AnnaBridge	172:65be27845400	606	*/
AnnaBridge	172:65be27845400	607	#define HRTIM_EVENT_NONE (0x00000000U) /!< Undefined event channel /
AnnaBridge	172:65be27845400	608	#define HRTIM_EVENT_1 (0x00000001U) /!< External event channel 1 identifier /
AnnaBridge	172:65be27845400	609	#define HRTIM_EVENT_2 (0x00000002U) /!< External event channel 2 identifier /
AnnaBridge	172:65be27845400	610	#define HRTIM_EVENT_3 (0x00000003U) /!< External event channel 3 identifier /
AnnaBridge	172:65be27845400	611	#define HRTIM_EVENT_4 (0x00000004U) /!< External event channel 4 identifier /
AnnaBridge	172:65be27845400	612	#define HRTIM_EVENT_5 (0x00000005U) /!< External event channel 5 identifier /
AnnaBridge	172:65be27845400	613	#define HRTIM_EVENT_6 (0x00000006U) /!< External event channel 6 identifier /
AnnaBridge	172:65be27845400	614	#define HRTIM_EVENT_7 (0x00000007U) /!< External event channel 7 identifier /
AnnaBridge	172:65be27845400	615	#define HRTIM_EVENT_8 (0x00000008U) /!< External event channel 8 identifier /
AnnaBridge	172:65be27845400	616	#define HRTIM_EVENT_9 (0x00000009U) /!< External event channel 9 identifier /
AnnaBridge	172:65be27845400	617	#define HRTIM_EVENT_10 (0x0000000AU) /!< External event channel 10 identifier /
AnnaBridge	172:65be27845400	618	/**
AnnaBridge	172:65be27845400	619	* @}
AnnaBridge	172:65be27845400	620	*/
AnnaBridge	172:65be27845400	621
AnnaBridge	172:65be27845400	622	/** @defgroup HRTIM_Fault_Channel HRTIM Fault Channel
AnnaBridge	172:65be27845400	623	* @{
AnnaBridge	172:65be27845400	624	* @brief Constants defining fault channel identifiers
AnnaBridge	172:65be27845400	625	*/
AnnaBridge	172:65be27845400	626	#define HRTIM_FAULT_1 (0x01U) /!< Fault channel 1 identifier /
AnnaBridge	172:65be27845400	627	#define HRTIM_FAULT_2 (0x02U) /!< Fault channel 2 identifier /
AnnaBridge	172:65be27845400	628	#define HRTIM_FAULT_3 (0x04U) /!< Fault channel 3 identifier /
AnnaBridge	172:65be27845400	629	#define HRTIM_FAULT_4 (0x08U) /!< Fault channel 4 identifier /
AnnaBridge	172:65be27845400	630	#define HRTIM_FAULT_5 (0x10U) /!< Fault channel 5 identifier /
AnnaBridge	172:65be27845400	631	/**
AnnaBridge	172:65be27845400	632	* @}
AnnaBridge	172:65be27845400	633	*/
AnnaBridge	172:65be27845400	634
AnnaBridge	172:65be27845400	635
AnnaBridge	172:65be27845400	636	/** @defgroup HRTIM_Prescaler_Ratio HRTIM Prescaler Ratio
AnnaBridge	172:65be27845400	637	* @{
AnnaBridge	172:65be27845400	638	* @brief Constants defining timer high-resolution clock prescaler ratio.
AnnaBridge	172:65be27845400	639	*/
AnnaBridge	172:65be27845400	640	#define HRTIM_PRESCALERRATIO_MUL32 (0x00000000U) /!< fHRCK: fHRTIM x 32U = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) /
AnnaBridge	172:65be27845400	641	#define HRTIM_PRESCALERRATIO_MUL16 (0x00000001U) /!< fHRCK: fHRTIM x 16U = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) /
AnnaBridge	172:65be27845400	642	#define HRTIM_PRESCALERRATIO_MUL8 (0x00000002U) /!< fHRCK: fHRTIM x 8U = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) /
AnnaBridge	172:65be27845400	643	#define HRTIM_PRESCALERRATIO_MUL4 (0x00000003U) /!< fHRCK: fHRTIM x 4U = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) /
AnnaBridge	172:65be27845400	644	#define HRTIM_PRESCALERRATIO_MUL2 (0x00000004U) /!< fHRCK: fHRTIM x 2U = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) /
AnnaBridge	172:65be27845400	645	#define HRTIM_PRESCALERRATIO_DIV1 (0x00000005U) /!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) /
AnnaBridge	172:65be27845400	646	#define HRTIM_PRESCALERRATIO_DIV2 (0x00000006U) /!< fHRCK: fHRTIM / 2U = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) /
AnnaBridge	172:65be27845400	647	#define HRTIM_PRESCALERRATIO_DIV4 (0x00000007U) /!< fHRCK: fHRTIM / 4U = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) /
AnnaBridge	172:65be27845400	648	/**
AnnaBridge	172:65be27845400	649	* @}
AnnaBridge	172:65be27845400	650	*/
AnnaBridge	172:65be27845400	651
AnnaBridge	172:65be27845400	652	/** @defgroup HRTIM_Counter_Operating_Mode HRTIM Counter Operating Mode
AnnaBridge	172:65be27845400	653	* @{
AnnaBridge	172:65be27845400	654	* @brief Constants defining timer counter operating mode.
AnnaBridge	172:65be27845400	655	*/
AnnaBridge	172:65be27845400	656	#define HRTIM_MODE_CONTINUOUS (0x00000008U) /!< The timer operates in continuous (free-running) mode /
AnnaBridge	172:65be27845400	657	#define HRTIM_MODE_SINGLESHOT (0x00000000U) /!< The timer operates in non retriggerable single-shot mode /
AnnaBridge	172:65be27845400	658	#define HRTIM_MODE_SINGLESHOT_RETRIGGERABLE (0x00000010U) /!< The timer operates in retriggerable single-shot mode /
AnnaBridge	172:65be27845400	659	/**
AnnaBridge	172:65be27845400	660	* @}
AnnaBridge	172:65be27845400	661	*/
AnnaBridge	172:65be27845400	662
AnnaBridge	172:65be27845400	663	/** @defgroup HRTIM_Half_Mode_Enable HRTIM Half Mode Enable
AnnaBridge	172:65be27845400	664	* @{
AnnaBridge	172:65be27845400	665	* @brief Constants defining half mode enabling status.
AnnaBridge	172:65be27845400	666	*/
AnnaBridge	172:65be27845400	667	#define HRTIM_HALFMODE_DISABLED (0x00000000U) /!< Half mode is disabled /
AnnaBridge	172:65be27845400	668	#define HRTIM_HALFMODE_ENABLED (0x00000020U) /!< Half mode is enabled /
AnnaBridge	172:65be27845400	669	/**
AnnaBridge	172:65be27845400	670	* @}
AnnaBridge	172:65be27845400	671	*/
AnnaBridge	172:65be27845400	672
AnnaBridge	172:65be27845400	673	/** @defgroup HRTIM_Start_On_Sync_Input_Event HRTIM Start On Sync Input Event
AnnaBridge	172:65be27845400	674	* @{
AnnaBridge	172:65be27845400	675	* @brief Constants defining the timer behavior following the synchronization event
AnnaBridge	172:65be27845400	676	*/
AnnaBridge	172:65be27845400	677	#define HRTIM_SYNCSTART_DISABLED (0x00000000U) /!< Synchronization input event has effect on the timer /
AnnaBridge	172:65be27845400	678	#define HRTIM_SYNCSTART_ENABLED (HRTIM_MCR_SYNCSTRTM) /!< Synchronization input event starts the timer /
AnnaBridge	172:65be27845400	679	/**
AnnaBridge	172:65be27845400	680	* @}
AnnaBridge	172:65be27845400	681	*/
AnnaBridge	172:65be27845400	682
AnnaBridge	172:65be27845400	683	/** @defgroup HRTIM_Reset_On_Sync_Input_Event HRTIM Reset On Sync Input Event
AnnaBridge	172:65be27845400	684	* @{
AnnaBridge	172:65be27845400	685	* @brief Constants defining the timer behavior following the synchronization event
AnnaBridge	172:65be27845400	686	*/
AnnaBridge	172:65be27845400	687	#define HRTIM_SYNCRESET_DISABLED (0x00000000U) /!< Synchronization input event has effect on the timer /
AnnaBridge	172:65be27845400	688	#define HRTIM_SYNCRESET_ENABLED (HRTIM_MCR_SYNCRSTM) /!< Synchronization input event resets the timer /
AnnaBridge	172:65be27845400	689	/**
AnnaBridge	172:65be27845400	690	* @}
AnnaBridge	172:65be27845400	691	*/
AnnaBridge	172:65be27845400	692
AnnaBridge	172:65be27845400	693	/** @defgroup HRTIM_DAC_Synchronization HRTIM DAC Synchronization
AnnaBridge	172:65be27845400	694	* @{
AnnaBridge	172:65be27845400	695	* @brief Constants defining on which output the DAC synchronization event is sent
AnnaBridge	172:65be27845400	696	*/
AnnaBridge	172:65be27845400	697	#define HRTIM_DACSYNC_NONE 0x00000000U /!< No DAC synchronization event generated /
AnnaBridge	172:65be27845400	698	#define HRTIM_DACSYNC_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /!< DAC synchronization event generated on DACTrigOut1 output upon timer update /
AnnaBridge	172:65be27845400	699	#define HRTIM_DACSYNC_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /!< DAC synchronization event generated on DACTrigOut2 output upon timer update /
AnnaBridge	172:65be27845400	700	#define HRTIM_DACSYNC_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 \| HRTIM_MCR_DACSYNC_0) /!< DAC update generated on DACTrigOut3 output upon timer update /
AnnaBridge	172:65be27845400	701	/**
AnnaBridge	172:65be27845400	702	* @}
AnnaBridge	172:65be27845400	703	*/
AnnaBridge	172:65be27845400	704
AnnaBridge	172:65be27845400	705	/** @defgroup HRTIM_Register_Preload_Enable HRTIM Register Preload Enable
AnnaBridge	172:65be27845400	706	* @{
AnnaBridge	172:65be27845400	707	* @brief Constants defining whether a write access into a preloadable
AnnaBridge	172:65be27845400	708	* register is done into the active or the preload register.
AnnaBridge	172:65be27845400	709	*/
AnnaBridge	172:65be27845400	710	#define HRTIM_PRELOAD_DISABLED (0x00000000U) /!< Preload disabled: the write access is directly done into the active register /
AnnaBridge	172:65be27845400	711	#define HRTIM_PRELOAD_ENABLED (HRTIM_MCR_PREEN) /!< Preload enabled: the write access is done into the preload register /
AnnaBridge	172:65be27845400	712	/**
AnnaBridge	172:65be27845400	713	* @}
AnnaBridge	172:65be27845400	714	*/
AnnaBridge	172:65be27845400	715
AnnaBridge	172:65be27845400	716	/** @defgroup HRTIM_Update_Gating HRTIM Update Gating
AnnaBridge	172:65be27845400	717	* @{
AnnaBridge	172:65be27845400	718	* @brief Constants defining how the update occurs relatively to the burst DMA
AnnaBridge	172:65be27845400	719	* transaction and the external update request on update enable inputs 1 to 3.
AnnaBridge	172:65be27845400	720	*/
AnnaBridge	172:65be27845400	721	#define HRTIM_UPDATEGATING_INDEPENDENT 0x00000000U /!< Update done independently from the DMA burst transfer completion /
AnnaBridge	172:65be27845400	722	#define HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /!< Update done when the DMA burst transfer is completed /
AnnaBridge	172:65be27845400	723	#define HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /!< Update done on timer roll-over following a DMA burst transfer completion/
AnnaBridge	172:65be27845400	724	#define HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 \| HRTIM_TIMCR_UPDGAT_0) /!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1U /
AnnaBridge	172:65be27845400	725	#define HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2U /
AnnaBridge	172:65be27845400	726	#define HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 \| HRTIM_TIMCR_UPDGAT_0) /!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3U /
AnnaBridge	172:65be27845400	727	#define HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 \| HRTIM_TIMCR_UPDGAT_1) /!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1U /
AnnaBridge	172:65be27845400	728	#define HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 \| HRTIM_TIMCR_UPDGAT_1 \| HRTIM_TIMCR_UPDGAT_0) /!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2U /
AnnaBridge	172:65be27845400	729	#define HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3U /
AnnaBridge	172:65be27845400	730	/**
AnnaBridge	172:65be27845400	731	* @}
AnnaBridge	172:65be27845400	732	*/
AnnaBridge	172:65be27845400	733
AnnaBridge	172:65be27845400	734	/** @defgroup HRTIM_Timer_Burst_Mode HRTIM Timer Burst Mode
AnnaBridge	172:65be27845400	735	* @{
AnnaBridge	172:65be27845400	736	* @brief Constants defining how the timer behaves during a burst
AnnaBridge	172:65be27845400	737	mode operation.
AnnaBridge	172:65be27845400	738	*/
AnnaBridge	172:65be27845400	739	#define HRTIM_TIMERBURSTMODE_MAINTAINCLOCK 0x00000000U /!< Timer counter clock is maintained and the timer operates normally /
AnnaBridge	172:65be27845400	740	#define HRTIM_TIMERBURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /!< Timer counter clock is stopped and the counter is reset /
AnnaBridge	172:65be27845400	741	/**
AnnaBridge	172:65be27845400	742	* @}
AnnaBridge	172:65be27845400	743	*/
AnnaBridge	172:65be27845400	744
AnnaBridge	172:65be27845400	745	/** @defgroup HRTIM_Timer_Repetition_Update HRTIM Timer Repetition Update
AnnaBridge	172:65be27845400	746	* @{
AnnaBridge	172:65be27845400	747	* @brief Constants defining whether registers are updated when the timer
AnnaBridge	172:65be27845400	748	* repetition period is completed (either due to roll-over or
AnnaBridge	172:65be27845400	749	* reset events)
AnnaBridge	172:65be27845400	750	*/
AnnaBridge	172:65be27845400	751	#define HRTIM_UPDATEONREPETITION_DISABLED 0x00000000U /!< Update on repetition disabled /
AnnaBridge	172:65be27845400	752	#define HRTIM_UPDATEONREPETITION_ENABLED (HRTIM_MCR_MREPU) /!< Update on repetition enabled /
AnnaBridge	172:65be27845400	753	/**
AnnaBridge	172:65be27845400	754	* @}
AnnaBridge	172:65be27845400	755	*/
AnnaBridge	172:65be27845400	756
AnnaBridge	172:65be27845400	757
AnnaBridge	172:65be27845400	758	/** @defgroup HRTIM_Timer_Push_Pull_Mode HRTIM Timer Push Pull Mode
AnnaBridge	172:65be27845400	759	* @{
AnnaBridge	172:65be27845400	760	* @brief Constants defining whether or not the push-pull mode is enabled for
AnnaBridge	172:65be27845400	761	* a timer.
AnnaBridge	172:65be27845400	762	*/
AnnaBridge	172:65be27845400	763	#define HRTIM_TIMPUSHPULLMODE_DISABLED 0x00000000U /!< Push-Pull mode disabled /
AnnaBridge	172:65be27845400	764	#define HRTIM_TIMPUSHPULLMODE_ENABLED (HRTIM_TIMCR_PSHPLL) /!< Push-Pull mode enabled /
AnnaBridge	172:65be27845400	765	/**
AnnaBridge	172:65be27845400	766	* @}
AnnaBridge	172:65be27845400	767	*/
AnnaBridge	172:65be27845400	768
AnnaBridge	172:65be27845400	769	/** @defgroup HRTIM_Timer_Fault_Enabling HRTIM Timer Fault Enabling
AnnaBridge	172:65be27845400	770	* @{
AnnaBridge	172:65be27845400	771	* @brief Constants defining whether a fault channel is enabled for a timer
AnnaBridge	172:65be27845400	772	*/
AnnaBridge	172:65be27845400	773	#define HRTIM_TIMFAULTENABLE_NONE 0x00000000U /!< No fault enabled /
AnnaBridge	172:65be27845400	774	#define HRTIM_TIMFAULTENABLE_FAULT1 (HRTIM_FLTR_FLT1EN) /!< Fault 1 enabled /
AnnaBridge	172:65be27845400	775	#define HRTIM_TIMFAULTENABLE_FAULT2 (HRTIM_FLTR_FLT2EN) /!< Fault 2 enabled /
AnnaBridge	172:65be27845400	776	#define HRTIM_TIMFAULTENABLE_FAULT3 (HRTIM_FLTR_FLT3EN) /!< Fault 3 enabled /
AnnaBridge	172:65be27845400	777	#define HRTIM_TIMFAULTENABLE_FAULT4 (HRTIM_FLTR_FLT4EN) /!< Fault 4 enabled /
AnnaBridge	172:65be27845400	778	#define HRTIM_TIMFAULTENABLE_FAULT5 (HRTIM_FLTR_FLT5EN) /!< Fault 5 enabled /
AnnaBridge	172:65be27845400	779	/**
AnnaBridge	172:65be27845400	780	* @}
AnnaBridge	172:65be27845400	781	*/
AnnaBridge	172:65be27845400	782
AnnaBridge	172:65be27845400	783	/** @defgroup HRTIM_Timer_Fault_Lock HRTIM Timer Fault Lock
AnnaBridge	172:65be27845400	784	* @{
AnnaBridge	172:65be27845400	785	* @brief Constants defining whether or not fault enabling bits are write
AnnaBridge	172:65be27845400	786	* protected for a timer
AnnaBridge	172:65be27845400	787	*/
AnnaBridge	172:65be27845400	788	#define HRTIM_TIMFAULTLOCK_READWRITE (0x00000000U) /!< Timer fault enabling bits are read/write /
AnnaBridge	172:65be27845400	789	#define HRTIM_TIMFAULTLOCK_READONLY (HRTIM_FLTR_FLTLCK) /!< Timer fault enabling bits are read only /
AnnaBridge	172:65be27845400	790	/**
AnnaBridge	172:65be27845400	791	* @}
AnnaBridge	172:65be27845400	792	*/
AnnaBridge	172:65be27845400	793
AnnaBridge	172:65be27845400	794	/** @defgroup HRTIM_Timer_Deadtime_Insertion HRTIM Timer Dead-time Insertion
AnnaBridge	172:65be27845400	795	* @{
AnnaBridge	172:65be27845400	796	* @brief Constants defining whether or not fault the dead time insertion
AnnaBridge	172:65be27845400	797	* feature is enabled for a timer
AnnaBridge	172:65be27845400	798	*/
AnnaBridge	172:65be27845400	799	#define HRTIM_TIMDEADTIMEINSERTION_DISABLED (0x00000000U) /!< Output 1 and output 2 signals are independent /
AnnaBridge	172:65be27845400	800	#define HRTIM_TIMDEADTIMEINSERTION_ENABLED HRTIM_OUTR_DTEN /!< Dead-time is inserted between output 1 and output 2U /
AnnaBridge	172:65be27845400	801	/**
AnnaBridge	172:65be27845400	802	* @}
AnnaBridge	172:65be27845400	803	*/
AnnaBridge	172:65be27845400	804
AnnaBridge	172:65be27845400	805	/** @defgroup HRTIM_Timer_Delayed_Protection_Mode HRTIM Timer Delayed Protection Mode
AnnaBridge	172:65be27845400	806	* @{
AnnaBridge	172:65be27845400	807	* @brief Constants defining all possible delayed protection modes
AnnaBridge	172:65be27845400	808	* for a timer. Also define the source and outputs on which the delayed
AnnaBridge	172:65be27845400	809	* protection schemes are applied
AnnaBridge	172:65be27845400	810	*/
AnnaBridge	172:65be27845400	811	#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED (0x00000000U) /!< No action /
AnnaBridge	172:65be27845400	812	#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 (HRTIM_OUTR_DLYPRTEN) /!< Timers A, B, C: Output 1 delayed Idle on external Event 6U /
AnnaBridge	172:65be27845400	813	#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 (HRTIM_OUTR_DLYPRT_0 \| HRTIM_OUTR_DLYPRTEN) /!< Timers A, B, C: Output 2 delayed Idle on external Event 6U /
AnnaBridge	172:65be27845400	814	#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 (HRTIM_OUTR_DLYPRT_1 \| HRTIM_OUTR_DLYPRTEN) /!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6U /
AnnaBridge	172:65be27845400	815	#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 (HRTIM_OUTR_DLYPRT_1 \| HRTIM_OUTR_DLYPRT_0 \| HRTIM_OUTR_DLYPRTEN) /!< Timers A, B, C: Balanced Idle on external Event 6U /
AnnaBridge	172:65be27845400	816	#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 (HRTIM_OUTR_DLYPRT_2 \| HRTIM_OUTR_DLYPRTEN) /!< Timers A, B, C: Output 1 delayed Idle on external Event 7U /
AnnaBridge	172:65be27845400	817	#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 (HRTIM_OUTR_DLYPRT_2 \| HRTIM_OUTR_DLYPRT_0 \| HRTIM_OUTR_DLYPRTEN) /!< Timers A, B, C: Output 2 delayed Idle on external Event 7U /
AnnaBridge	172:65be27845400	818	#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 (HRTIM_OUTR_DLYPRT_2 \| HRTIM_OUTR_DLYPRT_1 \| HRTIM_OUTR_DLYPRTEN) /!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7U /
AnnaBridge	172:65be27845400	819	#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 (HRTIM_OUTR_DLYPRT_2 \| HRTIM_OUTR_DLYPRT_1 \| HRTIM_OUTR_DLYPRT_0 \| HRTIM_OUTR_DLYPRTEN) /!< Timers A, B, C: Balanced Idle on external Event 7U /
AnnaBridge	172:65be27845400	820
AnnaBridge	172:65be27845400	821	#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DISABLED (0x00000000U) /!< No action /
AnnaBridge	172:65be27845400	822	#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_EEV8 (HRTIM_OUTR_DLYPRTEN) /!< Timers D, E: Output 1 delayed Idle on external Event 6U /
AnnaBridge	172:65be27845400	823	#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0 \| HRTIM_OUTR_DLYPRTEN) /!< Timers D, E: Output 2 delayed Idle on external Event 6U /
AnnaBridge	172:65be27845400	824	#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1 \| HRTIM_OUTR_DLYPRTEN) /!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 6U /
AnnaBridge	172:65be27845400	825	#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 \| HRTIM_OUTR_DLYPRT_0 \| HRTIM_OUTR_DLYPRTEN) /!< Timers D, E: Balanced Idle on external Event 6U /
AnnaBridge	172:65be27845400	826	#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9 (HRTIM_OUTR_DLYPRT_2 \| HRTIM_OUTR_DLYPRTEN) /!< Timers D, E: Output 1 delayed Idle on external Event 7U /
AnnaBridge	172:65be27845400	827	#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9 (HRTIM_OUTR_DLYPRT_2 \| HRTIM_OUTR_DLYPRT_0 \| HRTIM_OUTR_DLYPRTEN) /!< Timers D, E: Output 2 delayed Idle on external Event 7U /
AnnaBridge	172:65be27845400	828	#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 \| HRTIM_OUTR_DLYPRT_1 \| HRTIM_OUTR_DLYPRTEN) /!< Timers D, E: Output 1 and output2 delayed Idle on external Event 7U /
AnnaBridge	172:65be27845400	829	#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 \| HRTIM_OUTR_DLYPRT_1 \| HRTIM_OUTR_DLYPRT_0 \| HRTIM_OUTR_DLYPRTEN) /!< Timers D, E: Balanced Idle on external Event 7U /
AnnaBridge	172:65be27845400	830	/**
AnnaBridge	172:65be27845400	831	* @}
AnnaBridge	172:65be27845400	832	*/
AnnaBridge	172:65be27845400	833
AnnaBridge	172:65be27845400	834	/** @defgroup HRTIM_Timer_Update_Trigger HRTIM Timer Update Trigger
AnnaBridge	172:65be27845400	835	* @{
AnnaBridge	172:65be27845400	836	* @brief Constants defining whether the registers update is done synchronously
AnnaBridge	172:65be27845400	837	* with any other timer or master update
AnnaBridge	172:65be27845400	838	*/
AnnaBridge	172:65be27845400	839	#define HRTIM_TIMUPDATETRIGGER_NONE 0x00000000U /!< Register update is disabled /
AnnaBridge	172:65be27845400	840	#define HRTIM_TIMUPDATETRIGGER_MASTER (HRTIM_TIMCR_MSTU) /!< Register update is triggered by the master timer update /
AnnaBridge	172:65be27845400	841	#define HRTIM_TIMUPDATETRIGGER_TIMER_A (HRTIM_TIMCR_TAU) /!< Register update is triggered by the timer A update /
AnnaBridge	172:65be27845400	842	#define HRTIM_TIMUPDATETRIGGER_TIMER_B (HRTIM_TIMCR_TBU) /!< Register update is triggered by the timer B update /
AnnaBridge	172:65be27845400	843	#define HRTIM_TIMUPDATETRIGGER_TIMER_C (HRTIM_TIMCR_TCU) /!< Register update is triggered by the timer C update/
AnnaBridge	172:65be27845400	844	#define HRTIM_TIMUPDATETRIGGER_TIMER_D (HRTIM_TIMCR_TDU) /!< Register update is triggered by the timer D update /
AnnaBridge	172:65be27845400	845	#define HRTIM_TIMUPDATETRIGGER_TIMER_E (HRTIM_TIMCR_TEU) /!< Register update is triggered by the timer E update /
AnnaBridge	172:65be27845400	846	/**
AnnaBridge	172:65be27845400	847	* @}
AnnaBridge	172:65be27845400	848	*/
AnnaBridge	172:65be27845400	849
AnnaBridge	172:65be27845400	850	/** @defgroup HRTIM_Timer_Reset_Trigger HRTIM Timer Reset Trigger
AnnaBridge	172:65be27845400	851	* @{
AnnaBridge	172:65be27845400	852	* @brief Constants defining the events that can be selected to trigger the reset
AnnaBridge	172:65be27845400	853	* of the timer counter
AnnaBridge	172:65be27845400	854	*/
AnnaBridge	172:65be27845400	855	#define HRTIM_TIMRESETTRIGGER_NONE 0x00000000U /!< No counter reset trigger /
AnnaBridge	172:65be27845400	856	#define HRTIM_TIMRESETTRIGGER_UPDATE (HRTIM_RSTR_UPDATE) /!< The timer counter is reset upon update event /
AnnaBridge	172:65be27845400	857	#define HRTIM_TIMRESETTRIGGER_CMP2 (HRTIM_RSTR_CMP2) /!< The timer counter is reset upon Timer Compare 2 event /
AnnaBridge	172:65be27845400	858	#define HRTIM_TIMRESETTRIGGER_CMP4 (HRTIM_RSTR_CMP4) /!< The timer counter is reset upon Timer Compare 4 event /
AnnaBridge	172:65be27845400	859	#define HRTIM_TIMRESETTRIGGER_MASTER_PER (HRTIM_RSTR_MSTPER) /!< The timer counter is reset upon master timer period event /
AnnaBridge	172:65be27845400	860	#define HRTIM_TIMRESETTRIGGER_MASTER_CMP1 (HRTIM_RSTR_MSTCMP1) /!< The timer counter is reset upon master timer Compare 1 event /
AnnaBridge	172:65be27845400	861	#define HRTIM_TIMRESETTRIGGER_MASTER_CMP2 (HRTIM_RSTR_MSTCMP2) /!< The timer counter is reset upon master timer Compare 2 event /
AnnaBridge	172:65be27845400	862	#define HRTIM_TIMRESETTRIGGER_MASTER_CMP3 (HRTIM_RSTR_MSTCMP3) /!< The timer counter is reset upon master timer Compare 3 event /
AnnaBridge	172:65be27845400	863	#define HRTIM_TIMRESETTRIGGER_MASTER_CMP4 (HRTIM_RSTR_MSTCMP4) /!< The timer counter is reset upon master timer Compare 4 event /
AnnaBridge	172:65be27845400	864	#define HRTIM_TIMRESETTRIGGER_EEV_1 (HRTIM_RSTR_EXTEVNT1) /!< The timer counter is reset upon external event 1U /
AnnaBridge	172:65be27845400	865	#define HRTIM_TIMRESETTRIGGER_EEV_2 (HRTIM_RSTR_EXTEVNT2) /!< The timer counter is reset upon external event 2U /
AnnaBridge	172:65be27845400	866	#define HRTIM_TIMRESETTRIGGER_EEV_3 (HRTIM_RSTR_EXTEVNT3) /!< The timer counter is reset upon external event 3U /
AnnaBridge	172:65be27845400	867	#define HRTIM_TIMRESETTRIGGER_EEV_4 (HRTIM_RSTR_EXTEVNT4) /!< The timer counter is reset upon external event 4U /
AnnaBridge	172:65be27845400	868	#define HRTIM_TIMRESETTRIGGER_EEV_5 (HRTIM_RSTR_EXTEVNT5) /!< The timer counter is reset upon external event 5U /
AnnaBridge	172:65be27845400	869	#define HRTIM_TIMRESETTRIGGER_EEV_6 (HRTIM_RSTR_EXTEVNT6) /!< The timer counter is reset upon external event 6U /
AnnaBridge	172:65be27845400	870	#define HRTIM_TIMRESETTRIGGER_EEV_7 (HRTIM_RSTR_EXTEVNT7) /!< The timer counter is reset upon external event 7U /
AnnaBridge	172:65be27845400	871	#define HRTIM_TIMRESETTRIGGER_EEV_8 (HRTIM_RSTR_EXTEVNT8) /!< The timer counter is reset upon external event 8U /
AnnaBridge	172:65be27845400	872	#define HRTIM_TIMRESETTRIGGER_EEV_9 (HRTIM_RSTR_EXTEVNT9) /!< The timer counter is reset upon external event 9U /
AnnaBridge	172:65be27845400	873	#define HRTIM_TIMRESETTRIGGER_EEV_10 (HRTIM_RSTR_EXTEVNT10) /!< The timer counter is reset upon external event 10U /
AnnaBridge	172:65be27845400	874	#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 (HRTIM_RSTR_TIMBCMP1) /!< The timer counter is reset upon other timer Compare 1 event /
AnnaBridge	172:65be27845400	875	#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 (HRTIM_RSTR_TIMBCMP2) /!< The timer counter is reset upon other timer Compare 2 event /
AnnaBridge	172:65be27845400	876	#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 (HRTIM_RSTR_TIMBCMP4) /!< The timer counter is reset upon other timer Compare 4 event /
AnnaBridge	172:65be27845400	877	#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP1 (HRTIM_RSTR_TIMCCMP1) /!< The timer counter is reset upon other timer Compare 1 event /
AnnaBridge	172:65be27845400	878	#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP2 (HRTIM_RSTR_TIMCCMP2) /!< The timer counter is reset upon other timer Compare 2 event /
AnnaBridge	172:65be27845400	879	#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP4 (HRTIM_RSTR_TIMCCMP4) /!< The timer counter is reset upon other timer Compare 4 event /
AnnaBridge	172:65be27845400	880	#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP1 (HRTIM_RSTR_TIMDCMP1) /!< The timer counter is reset upon other timer Compare 1 event /
AnnaBridge	172:65be27845400	881	#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP2 (HRTIM_RSTR_TIMDCMP2) /!< The timer counter is reset upon other timer Compare 2 event /
AnnaBridge	172:65be27845400	882	#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP4 (HRTIM_RSTR_TIMDCMP4) /!< The timer counter is reset upon other timer Compare 4 event /
AnnaBridge	172:65be27845400	883	#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP1 (HRTIM_RSTR_TIMECMP1) /!< The timer counter is reset upon other timer Compare 1 event /
AnnaBridge	172:65be27845400	884	#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP2 (HRTIM_RSTR_TIMECMP2) /!< The timer counter is reset upon other timer Compare 2 event /
AnnaBridge	172:65be27845400	885	#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP4 (HRTIM_RSTR_TIMECMP4) /!< The timer counter is reset upon other timer Compare 4 event /
AnnaBridge	172:65be27845400	886	/**
AnnaBridge	172:65be27845400	887	* @}
AnnaBridge	172:65be27845400	888	*/
AnnaBridge	172:65be27845400	889
AnnaBridge	172:65be27845400	890	/** @defgroup HRTIM_Timer_Reset_Update HRTIM Timer Reset Update
AnnaBridge	172:65be27845400	891	* @{
AnnaBridge	172:65be27845400	892	* @brief Constants defining whether the register are updated upon Timerx
AnnaBridge	172:65be27845400	893	* counter reset or roll-over to 0 after reaching the period value
AnnaBridge	172:65be27845400	894	* in continuous mode
AnnaBridge	172:65be27845400	895	*/
AnnaBridge	172:65be27845400	896	#define HRTIM_TIMUPDATEONRESET_DISABLED 0x00000000U /!< Update by timer x reset / roll-over disabled /
AnnaBridge	172:65be27845400	897	#define HRTIM_TIMUPDATEONRESET_ENABLED (HRTIM_TIMCR_TRSTU) /!< Update by timer x reset / roll-over enabled /
AnnaBridge	172:65be27845400	898	/**
AnnaBridge	172:65be27845400	899	* @}
AnnaBridge	172:65be27845400	900	*/
AnnaBridge	172:65be27845400	901
AnnaBridge	172:65be27845400	902	/** @defgroup HRTIM_Compare_Unit_Auto_Delayed_Mode HRTIM Compare Unit Auto Delayed Mode
AnnaBridge	172:65be27845400	903	* @{
AnnaBridge	172:65be27845400	904	* @brief Constants defining whether the compare register is behaving in
AnnaBridge	172:65be27845400	905	* regular mode (compare match issued as soon as counter equal compare),
AnnaBridge	172:65be27845400	906	* or in auto-delayed mode
AnnaBridge	172:65be27845400	907	*/
AnnaBridge	172:65be27845400	908	#define HRTIM_AUTODELAYEDMODE_REGULAR (0x00000000U) /!< standard compare mode /
AnnaBridge	172:65be27845400	909	#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /!< Compare event generated only if a capture has occurred /
AnnaBridge	172:65be27845400	910	#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 (HRTIM_TIMCR_DELCMP2_1) /!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) /
AnnaBridge	172:65be27845400	911	#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 (HRTIM_TIMCR_DELCMP2_1 \| HRTIM_TIMCR_DELCMP2_0) /!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) /
AnnaBridge	172:65be27845400	912	/**
AnnaBridge	172:65be27845400	913	* @}
AnnaBridge	172:65be27845400	914	*/
AnnaBridge	172:65be27845400	915
AnnaBridge	172:65be27845400	916	/** @defgroup HRTIM_Simple_OC_Mode HRTIM Simple OC Mode
AnnaBridge	172:65be27845400	917	* @{
AnnaBridge	172:65be27845400	918	* @brief Constants defining the behavior of the output signal when the timer
AnnaBridge	172:65be27845400	919	operates in basic output compare mode
AnnaBridge	172:65be27845400	920	*/
AnnaBridge	172:65be27845400	921	#define HRTIM_BASICOCMODE_TOGGLE (0x00000001U) /!< Output toggles when the timer counter reaches the compare value /
AnnaBridge	172:65be27845400	922	#define HRTIM_BASICOCMODE_INACTIVE (0x00000002U) /!< Output forced to active level when the timer counter reaches the compare value /
AnnaBridge	172:65be27845400	923	#define HRTIM_BASICOCMODE_ACTIVE (0x00000003U) /!< Output forced to inactive level when the timer counter reaches the compare value /
AnnaBridge	172:65be27845400	924
AnnaBridge	172:65be27845400	925	#define IS_HRTIM_BASICOCMODE(BASICOCMODE)\
AnnaBridge	172:65be27845400	926	(((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) \|\| \
AnnaBridge	172:65be27845400	927	((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) \|\| \
AnnaBridge	172:65be27845400	928	((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE))
AnnaBridge	172:65be27845400	929	/**
AnnaBridge	172:65be27845400	930	* @}
AnnaBridge	172:65be27845400	931	*/
AnnaBridge	172:65be27845400	932
AnnaBridge	172:65be27845400	933	/** @defgroup HRTIM_Output_Polarity HRTIM Output Polarity
AnnaBridge	172:65be27845400	934	* @{
AnnaBridge	172:65be27845400	935	* @brief Constants defining the polarity of a timer output
AnnaBridge	172:65be27845400	936	*/
AnnaBridge	172:65be27845400	937	#define HRTIM_OUTPUTPOLARITY_HIGH (0x00000000U) /!< Output is acitve HIGH /
AnnaBridge	172:65be27845400	938	#define HRTIM_OUTPUTPOLARITY_LOW (HRTIM_OUTR_POL1) /!< Output is active LOW /
AnnaBridge	172:65be27845400	939	/**
AnnaBridge	172:65be27845400	940	* @}
AnnaBridge	172:65be27845400	941	*/
AnnaBridge	172:65be27845400	942
AnnaBridge	172:65be27845400	943	/** @defgroup HRTIM_Output_Set_Source HRTIM Output Set Source
AnnaBridge	172:65be27845400	944	* @{
AnnaBridge	172:65be27845400	945	* @brief Constants defining the events that can be selected to configure the
AnnaBridge	172:65be27845400	946	* set crossbar of a timer output
AnnaBridge	172:65be27845400	947	*/
AnnaBridge	172:65be27845400	948	#define HRTIM_OUTPUTSET_NONE 0x00000000U /!< Reset the output set crossbar /
AnnaBridge	172:65be27845400	949	#define HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) /!< Timer reset event coming solely from software or SYNC input forces the output to its active state /
AnnaBridge	172:65be27845400	950	#define HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) /!< Timer period event forces the output to its active state /
AnnaBridge	172:65be27845400	951	#define HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) /!< Timer compare 1 event forces the output to its active state /
AnnaBridge	172:65be27845400	952	#define HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2) /!< Timer compare 2 event forces the output to its active state /
AnnaBridge	172:65be27845400	953	#define HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3) /!< Timer compare 3 event forces the output to its active state /
AnnaBridge	172:65be27845400	954	#define HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4) /!< Timer compare 4 event forces the output to its active state /
AnnaBridge	172:65be27845400	955	#define HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER) /!< The master timer period event forces the output to its active state /
AnnaBridge	172:65be27845400	956	#define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /!< Master Timer compare 1 event forces the output to its active state /
AnnaBridge	172:65be27845400	957	#define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /!< Master Timer compare 2 event forces the output to its active state /
AnnaBridge	172:65be27845400	958	#define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /!< Master Timer compare 3 event forces the output to its active state /
AnnaBridge	172:65be27845400	959	#define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /!< Master Timer compare 4 event forces the output to its active state /
AnnaBridge	172:65be27845400	960	/* Timer Events mapping for Timer A */
AnnaBridge	172:65be27845400	961	#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 (HRTIM_SET1R_TIMEVNT1) /!< Timer event 1 forces the output to its active state /
AnnaBridge	172:65be27845400	962	#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 (HRTIM_SET1R_TIMEVNT2) /!< Timer event 2 forces the output to its active state /
AnnaBridge	172:65be27845400	963	#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 (HRTIM_SET1R_TIMEVNT3) /!< Timer event 3 forces the output to its active state /
AnnaBridge	172:65be27845400	964	#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 (HRTIM_SET1R_TIMEVNT4) /!< Timer event 4 forces the output to its active state /
AnnaBridge	172:65be27845400	965	#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 (HRTIM_SET1R_TIMEVNT5) /!< Timer event 5 forces the output to its active state /
AnnaBridge	172:65be27845400	966	#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 (HRTIM_SET1R_TIMEVNT6) /!< Timer event 6 forces the output to its active state /
AnnaBridge	172:65be27845400	967	#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 (HRTIM_SET1R_TIMEVNT7) /!< Timer event 7 forces the output to its active state /
AnnaBridge	172:65be27845400	968	#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 (HRTIM_SET1R_TIMEVNT8) /!< Timer event 8 forces the output to its active state /
AnnaBridge	172:65be27845400	969	#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 (HRTIM_SET1R_TIMEVNT9) /!< Timer event 9 forces the output to its active state /
AnnaBridge	172:65be27845400	970	/* Timer Events mapping for Timer B */
AnnaBridge	172:65be27845400	971	#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 (HRTIM_SET1R_TIMEVNT1) /!< Timer event 1 forces the output to its active state /
AnnaBridge	172:65be27845400	972	#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 (HRTIM_SET1R_TIMEVNT2) /!< Timer event 2 forces the output to its active state /
AnnaBridge	172:65be27845400	973	#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 (HRTIM_SET1R_TIMEVNT3) /!< Timer event 3 forces the output to its active state /
AnnaBridge	172:65be27845400	974	#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 (HRTIM_SET1R_TIMEVNT4) /!< Timer event 4 forces the output to its active state /
AnnaBridge	172:65be27845400	975	#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 (HRTIM_SET1R_TIMEVNT5) /!< Timer event 5 forces the output to its active state /
AnnaBridge	172:65be27845400	976	#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 (HRTIM_SET1R_TIMEVNT6) /!< Timer event 6 forces the output to its active state /
AnnaBridge	172:65be27845400	977	#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 (HRTIM_SET1R_TIMEVNT7) /!< Timer event 7 forces the output to its active state /
AnnaBridge	172:65be27845400	978	#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 (HRTIM_SET1R_TIMEVNT8) /!< Timer event 8 forces the output to its active state /
AnnaBridge	172:65be27845400	979	#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 (HRTIM_SET1R_TIMEVNT9) /!< Timer event 9 forces the output to its active state /
AnnaBridge	172:65be27845400	980	/* Timer Events mapping for Timer C */
AnnaBridge	172:65be27845400	981	#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 (HRTIM_SET1R_TIMEVNT1) /!< Timer event 1 forces the output to its active state /
AnnaBridge	172:65be27845400	982	#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 (HRTIM_SET1R_TIMEVNT2) /!< Timer event 2 forces the output to its active state /
AnnaBridge	172:65be27845400	983	#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 (HRTIM_SET1R_TIMEVNT3) /!< Timer event 3 forces the output to its active state /
AnnaBridge	172:65be27845400	984	#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 (HRTIM_SET1R_TIMEVNT4) /!< Timer event 4 forces the output to its active state /
AnnaBridge	172:65be27845400	985	#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 (HRTIM_SET1R_TIMEVNT5) /!< Timer event 5 forces the output to its active state /
AnnaBridge	172:65be27845400	986	#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 (HRTIM_SET1R_TIMEVNT6) /!< Timer event 6 forces the output to its active state /
AnnaBridge	172:65be27845400	987	#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 (HRTIM_SET1R_TIMEVNT7) /!< Timer event 7 forces the output to its active state /
AnnaBridge	172:65be27845400	988	#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 (HRTIM_SET1R_TIMEVNT8) /!< Timer event 8 forces the output to its active state /
AnnaBridge	172:65be27845400	989	#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 (HRTIM_SET1R_TIMEVNT9) /!< Timer event 9 forces the output to its active state /
AnnaBridge	172:65be27845400	990	/* Timer Events mapping for Timer D */
AnnaBridge	172:65be27845400	991	#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 (HRTIM_SET1R_TIMEVNT1) /!< Timer event 1 forces the output to its active state /
AnnaBridge	172:65be27845400	992	#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 (HRTIM_SET1R_TIMEVNT2) /!< Timer event 2 forces the output to its active state /
AnnaBridge	172:65be27845400	993	#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 (HRTIM_SET1R_TIMEVNT3) /!< Timer event 3 forces the output to its active state /
AnnaBridge	172:65be27845400	994	#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 (HRTIM_SET1R_TIMEVNT4) /!< Timer event 4 forces the output to its active state /
AnnaBridge	172:65be27845400	995	#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 (HRTIM_SET1R_TIMEVNT5) /!< Timer event 5 forces the output to its active state /
AnnaBridge	172:65be27845400	996	#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 (HRTIM_SET1R_TIMEVNT6) /!< Timer event 6 forces the output to its active state /
AnnaBridge	172:65be27845400	997	#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 (HRTIM_SET1R_TIMEVNT7) /!< Timer event 7 forces the output to its active state /
AnnaBridge	172:65be27845400	998	#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 (HRTIM_SET1R_TIMEVNT8) /!< Timer event 8 forces the output to its active state /
AnnaBridge	172:65be27845400	999	#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 (HRTIM_SET1R_TIMEVNT9) /!< Timer event 9 forces the output to its active state /
AnnaBridge	172:65be27845400	1000	/* Timer Events mapping for Timer E */
AnnaBridge	172:65be27845400	1001	#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 (HRTIM_SET1R_TIMEVNT1) /!< Timer event 1 forces the output to its active state /
AnnaBridge	172:65be27845400	1002	#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 (HRTIM_SET1R_TIMEVNT2) /!< Timer event 2 forces the output to its active state /
AnnaBridge	172:65be27845400	1003	#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 (HRTIM_SET1R_TIMEVNT3) /!< Timer event 3 forces the output to its active state /
AnnaBridge	172:65be27845400	1004	#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 (HRTIM_SET1R_TIMEVNT4) /!< Timer event 4 forces the output to its active state /
AnnaBridge	172:65be27845400	1005	#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 (HRTIM_SET1R_TIMEVNT5) /!< Timer event 5 forces the output to its active state /
AnnaBridge	172:65be27845400	1006	#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 (HRTIM_SET1R_TIMEVNT6) /!< Timer event 6 forces the output to its active state /
AnnaBridge	172:65be27845400	1007	#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 (HRTIM_SET1R_TIMEVNT7) /!< Timer event 7 forces the output to its active state /
AnnaBridge	172:65be27845400	1008	#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 (HRTIM_SET1R_TIMEVNT8) /!< Timer event 8 forces the output to its active state /
AnnaBridge	172:65be27845400	1009	#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 (HRTIM_SET1R_TIMEVNT9) /!< Timer event 9 forces the output to its active state /
AnnaBridge	172:65be27845400	1010	/* Timer Events mapping for Timer F */
AnnaBridge	172:65be27845400	1011	#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 (HRTIM_SET1R_TIMEVNT1) /!< Timer event 1 forces the output to its active state /
AnnaBridge	172:65be27845400	1012	#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 (HRTIM_SET1R_TIMEVNT2) /!< Timer event 2 forces the output to its active state /
AnnaBridge	172:65be27845400	1013	#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 (HRTIM_SET1R_TIMEVNT3) /!< Timer event 3 forces the output to its active state /
AnnaBridge	172:65be27845400	1014	#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 (HRTIM_SET1R_TIMEVNT4) /!< Timer event 4 forces the output to its active state /
AnnaBridge	172:65be27845400	1015	#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 (HRTIM_SET1R_TIMEVNT5) /!< Timer event 5 forces the output to its active state /
AnnaBridge	172:65be27845400	1016	#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 (HRTIM_SET1R_TIMEVNT6) /!< Timer event 6 forces the output to its active state /
AnnaBridge	172:65be27845400	1017	#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 (HRTIM_SET1R_TIMEVNT7) /!< Timer event 7 forces the output to its active state /
AnnaBridge	172:65be27845400	1018	#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 (HRTIM_SET1R_TIMEVNT8) /!< Timer event 8 forces the output to its active state /
AnnaBridge	172:65be27845400	1019	#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 (HRTIM_SET1R_TIMEVNT9) /!< Timer event 9 forces the output to its active state /
AnnaBridge	172:65be27845400	1020
AnnaBridge	172:65be27845400	1021	#define HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1) /!< External event 1 forces the output to its active state /
AnnaBridge	172:65be27845400	1022	#define HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2) /!< External event 2 forces the output to its active state /
AnnaBridge	172:65be27845400	1023	#define HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3) /!< External event 3 forces the output to its active state /
AnnaBridge	172:65be27845400	1024	#define HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4) /!< External event 4 forces the output to its active state /
AnnaBridge	172:65be27845400	1025	#define HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5) /!< External event 5 forces the output to its active state /
AnnaBridge	172:65be27845400	1026	#define HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6) /!< External event 6 forces the output to its active state /
AnnaBridge	172:65be27845400	1027	#define HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7) /!< External event 7 forces the output to its active state /
AnnaBridge	172:65be27845400	1028	#define HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8) /!< External event 8 forces the output to its active state /
AnnaBridge	172:65be27845400	1029	#define HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9) /!< External event 9 forces the output to its active state /
AnnaBridge	172:65be27845400	1030	#define HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10) /!< External event 10 forces the output to its active state /
AnnaBridge	172:65be27845400	1031	#define HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE) /!< Timer register update event forces the output to its active state /
AnnaBridge	172:65be27845400	1032	/**
AnnaBridge	172:65be27845400	1033	* @}
AnnaBridge	172:65be27845400	1034	*/
AnnaBridge	172:65be27845400	1035
AnnaBridge	172:65be27845400	1036	/** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source
AnnaBridge	172:65be27845400	1037	* @{
AnnaBridge	172:65be27845400	1038	* @brief Constants defining the events that can be selected to configure the
AnnaBridge	172:65be27845400	1039	* set crossbar of a timer output
AnnaBridge	172:65be27845400	1040	*/
AnnaBridge	172:65be27845400	1041	#define HRTIM_OUTPUTRESET_NONE 0x00000000U /!< Reset the output reset crossbar /
AnnaBridge	172:65be27845400	1042	#define HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state /
AnnaBridge	172:65be27845400	1043	#define HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) /!< Timer period event forces the output to its inactive state /
AnnaBridge	172:65be27845400	1044	#define HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) /!< Timer compare 1 event forces the output to its inactive state /
AnnaBridge	172:65be27845400	1045	#define HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2) /!< Timer compare 2 event forces the output to its inactive state /
AnnaBridge	172:65be27845400	1046	#define HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3) /!< Timer compare 3 event forces the output to its inactive state /
AnnaBridge	172:65be27845400	1047	#define HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4) /!< Timer compare 4 event forces the output to its inactive state /
AnnaBridge	172:65be27845400	1048	#define HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER) /!< The master timer period event forces the output to its inactive state /
AnnaBridge	172:65be27845400	1049	#define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1) /!< Master Timer compare 1 event forces the output to its inactive state /
AnnaBridge	172:65be27845400	1050	#define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /!< Master Timer compare 2 event forces the output to its inactive state /
AnnaBridge	172:65be27845400	1051	#define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /!< Master Timer compare 3 event forces the output to its inactive state /
AnnaBridge	172:65be27845400	1052	#define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /!< Master Timer compare 4 event forces the output to its inactive state /
AnnaBridge	172:65be27845400	1053	/* Timer Events mapping for Timer A */
AnnaBridge	172:65be27845400	1054	#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 (HRTIM_RST1R_TIMEVNT1) /!< Timer event 1 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1055	#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 (HRTIM_RST1R_TIMEVNT2) /!< Timer event 2 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1056	#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 (HRTIM_RST1R_TIMEVNT3) /!< Timer event 3 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1057	#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 (HRTIM_RST1R_TIMEVNT4) /!< Timer event 4 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1058	#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 (HRTIM_RST1R_TIMEVNT5) /!< Timer event 5 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1059	#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 (HRTIM_RST1R_TIMEVNT6) /!< Timer event 6 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1060	#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 (HRTIM_RST1R_TIMEVNT7) /!< Timer event 7 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1061	#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 (HRTIM_RST1R_TIMEVNT8) /!< Timer event 8 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1062	#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 (HRTIM_RST1R_TIMEVNT9) /!< Timer event 9 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1063	/* Timer Events mapping for Timer B */
AnnaBridge	172:65be27845400	1064	#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 (HRTIM_RST1R_TIMEVNT1) /!< Timer event 1 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1065	#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 (HRTIM_RST1R_TIMEVNT2) /!< Timer event 2 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1066	#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 (HRTIM_RST1R_TIMEVNT3) /!< Timer event 3 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1067	#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 (HRTIM_RST1R_TIMEVNT4) /!< Timer event 4 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1068	#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 (HRTIM_RST1R_TIMEVNT5) /!< Timer event 5 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1069	#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 (HRTIM_RST1R_TIMEVNT6) /!< Timer event 6 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1070	#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 (HRTIM_RST1R_TIMEVNT7) /!< Timer event 7 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1071	#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 (HRTIM_RST1R_TIMEVNT8) /!< Timer event 8 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1072	#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 (HRTIM_RST1R_TIMEVNT9) /!< Timer event 9 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1073	/* Timer Events mapping for Timer C */
AnnaBridge	172:65be27845400	1074	#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 (HRTIM_RST1R_TIMEVNT1) /!< Timer event 1 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1075	#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 (HRTIM_RST1R_TIMEVNT2) /!< Timer event 2 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1076	#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 (HRTIM_RST1R_TIMEVNT3) /!< Timer event 3 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1077	#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 (HRTIM_RST1R_TIMEVNT4) /!< Timer event 4 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1078	#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 (HRTIM_RST1R_TIMEVNT5) /!< Timer event 5 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1079	#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 (HRTIM_RST1R_TIMEVNT6) /!< Timer event 6 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1080	#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 (HRTIM_RST1R_TIMEVNT7) /!< Timer event 7 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1081	#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 (HRTIM_RST1R_TIMEVNT8) /!< Timer event 8 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1082	#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 (HRTIM_RST1R_TIMEVNT9) /!< Timer event 9 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1083	/* Timer Events mapping for Timer D */
AnnaBridge	172:65be27845400	1084	#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 (HRTIM_RST1R_TIMEVNT1) /!< Timer event 1 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1085	#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 (HRTIM_RST1R_TIMEVNT2) /!< Timer event 2 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1086	#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 (HRTIM_RST1R_TIMEVNT3) /!< Timer event 3 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1087	#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 (HRTIM_RST1R_TIMEVNT4) /!< Timer event 4 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1088	#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 (HRTIM_RST1R_TIMEVNT5) /!< Timer event 5 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1089	#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 (HRTIM_RST1R_TIMEVNT6) /!< Timer event 6 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1090	#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 (HRTIM_RST1R_TIMEVNT7) /!< Timer event 7 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1091	#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 (HRTIM_RST1R_TIMEVNT8) /!< Timer event 8 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1092	#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 (HRTIM_RST1R_TIMEVNT9) /!< Timer event 9 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1093	/* Timer Events mapping for Timer E */
AnnaBridge	172:65be27845400	1094	#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 (HRTIM_RST1R_TIMEVNT1) /!< Timer event 1 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1095	#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 (HRTIM_RST1R_TIMEVNT2) /!< Timer event 2 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1096	#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 (HRTIM_RST1R_TIMEVNT3) /!< Timer event 3 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1097	#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 (HRTIM_RST1R_TIMEVNT4) /!< Timer event 4 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1098	#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 (HRTIM_RST1R_TIMEVNT5) /!< Timer event 5 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1099	#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 (HRTIM_RST1R_TIMEVNT6) /!< Timer event 6 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1100	#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 (HRTIM_RST1R_TIMEVNT7) /!< Timer event 7 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1101	#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 (HRTIM_RST1R_TIMEVNT8) /!< Timer event 8 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1102	#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 (HRTIM_RST1R_TIMEVNT9) /!< Timer event 9 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1103	/* Timer Events mapping for Timer F */
AnnaBridge	172:65be27845400	1104	#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 (HRTIM_RST1R_TIMEVNT1) /!< Timer event 1 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1105	#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 (HRTIM_RST1R_TIMEVNT2) /!< Timer event 2 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1106	#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 (HRTIM_RST1R_TIMEVNT3) /!< Timer event 3 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1107	#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 (HRTIM_RST1R_TIMEVNT4) /!< Timer event 4 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1108	#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 (HRTIM_RST1R_TIMEVNT5) /!< Timer event 5 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1109	#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 (HRTIM_RST1R_TIMEVNT6) /!< Timer event 6 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1110	#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 (HRTIM_RST1R_TIMEVNT7) /!< Timer event 7 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1111	#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 (HRTIM_RST1R_TIMEVNT8) /!< Timer event 8 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1112	#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 (HRTIM_RST1R_TIMEVNT9) /!< Timer event 9 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1113
AnnaBridge	172:65be27845400	1114	#define HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /!< External event 1 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1115	#define HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /!< External event 2 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1116	#define HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /!< External event 3 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1117	#define HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4) /!< External event 4 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1118	#define HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5) /!< External event 5 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1119	#define HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6) /!< External event 6 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1120	#define HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7) /!< External event 7 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1121	#define HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8) /!< External event 8 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1122	#define HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9) /!< External event 9 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1123	#define HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10) /!< External event 10 forces the output to its inactive state /
AnnaBridge	172:65be27845400	1124	#define HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE) /!< Timer register update event forces the output to its inactive state /
AnnaBridge	172:65be27845400	1125	/**
AnnaBridge	172:65be27845400	1126	* @}
AnnaBridge	172:65be27845400	1127	*/
AnnaBridge	172:65be27845400	1128
AnnaBridge	172:65be27845400	1129	/** @defgroup HRTIM_Output_Idle_Mode HRTIM Output Idle Mode
AnnaBridge	172:65be27845400	1130	* @{
AnnaBridge	172:65be27845400	1131	* @brief Constants defining whether or not the timer output transition to its
AnnaBridge	172:65be27845400	1132	IDLE state when burst mode is entered
AnnaBridge	172:65be27845400	1133	*/
AnnaBridge	172:65be27845400	1134	#define HRTIM_OUTPUTIDLEMODE_NONE 0x00000000U /!< The output is not affected by the burst mode operation /
AnnaBridge	172:65be27845400	1135	#define HRTIM_OUTPUTIDLEMODE_IDLE (HRTIM_OUTR_IDLM1) /!< The output is in idle state when requested by the burst mode controller /
AnnaBridge	172:65be27845400	1136	/**
AnnaBridge	172:65be27845400	1137	* @}
AnnaBridge	172:65be27845400	1138	*/
AnnaBridge	172:65be27845400	1139
AnnaBridge	172:65be27845400	1140	/** @defgroup HRTIM_Output_IDLE_Level HRTIM Output IDLE Level
AnnaBridge	172:65be27845400	1141	* @{
AnnaBridge	172:65be27845400	1142	* @brief Constants defining the output level when output is in IDLE state
AnnaBridge	172:65be27845400	1143	*/
AnnaBridge	172:65be27845400	1144	#define HRTIM_OUTPUTIDLELEVEL_INACTIVE 0x00000000U /!< Output at inactive level when in IDLE state /
AnnaBridge	172:65be27845400	1145	#define HRTIM_OUTPUTIDLELEVEL_ACTIVE (HRTIM_OUTR_IDLES1) /!< Output at active level when in IDLE state /
AnnaBridge	172:65be27845400	1146	/**
AnnaBridge	172:65be27845400	1147	* @}
AnnaBridge	172:65be27845400	1148	*/
AnnaBridge	172:65be27845400	1149
AnnaBridge	172:65be27845400	1150	/** @defgroup HRTIM_Output_FAULT_Level HRTIM Output FAULT Level
AnnaBridge	172:65be27845400	1151	* @{
AnnaBridge	172:65be27845400	1152	* @brief Constants defining the output level when output is in FAULT state
AnnaBridge	172:65be27845400	1153	*/
AnnaBridge	172:65be27845400	1154	#define HRTIM_OUTPUTFAULTLEVEL_NONE 0x00000000U /!< The output is not affected by the fault input /
AnnaBridge	172:65be27845400	1155	#define HRTIM_OUTPUTFAULTLEVEL_ACTIVE (HRTIM_OUTR_FAULT1_0) /!< Output at active level when in FAULT state /
AnnaBridge	172:65be27845400	1156	#define HRTIM_OUTPUTFAULTLEVEL_INACTIVE (HRTIM_OUTR_FAULT1_1) /!< Output at inactive level when in FAULT state /
AnnaBridge	172:65be27845400	1157	#define HRTIM_OUTPUTFAULTLEVEL_HIGHZ (HRTIM_OUTR_FAULT1_1 \| HRTIM_OUTR_FAULT1_0) /!< Output is tri-stated when in FAULT state /
AnnaBridge	172:65be27845400	1158	/**
AnnaBridge	172:65be27845400	1159	* @}
AnnaBridge	172:65be27845400	1160	*/
AnnaBridge	172:65be27845400	1161
AnnaBridge	172:65be27845400	1162	/** @defgroup HRTIM_Output_Chopper_Mode_Enable HRTIM Output Chopper Mode Enable
AnnaBridge	172:65be27845400	1163	* @{
AnnaBridge	172:65be27845400	1164	* @brief Constants defining whether or not chopper mode is enabled for a timer
AnnaBridge	172:65be27845400	1165	output
AnnaBridge	172:65be27845400	1166	*/
AnnaBridge	172:65be27845400	1167	#define HRTIM_OUTPUTCHOPPERMODE_DISABLED 0x00000000U /!< Output signal is not altered /
AnnaBridge	172:65be27845400	1168	#define HRTIM_OUTPUTCHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /!< Output signal is chopped by a carrier signal /
AnnaBridge	172:65be27845400	1169	/**
AnnaBridge	172:65be27845400	1170	* @}
AnnaBridge	172:65be27845400	1171	*/
AnnaBridge	172:65be27845400	1172
AnnaBridge	172:65be27845400	1173	/** @defgroup HRTIM_Output_Burst_Mode_Entry_Delayed HRTIM Output Burst Mode Entry Delayed
AnnaBridge	172:65be27845400	1174	* @{
AnnaBridge	172:65be27845400	1175	* @brief Constants defining the idle mode entry is delayed by forcing a
AnnaBridge	172:65be27845400	1176	dead-time insertion before switching the outputs to their idle state
AnnaBridge	172:65be27845400	1177	*/
AnnaBridge	172:65be27845400	1178	#define HRTIM_OUTPUTBURSTMODEENTRY_REGULAR 0x00000000U /!< The programmed Idle state is applied immediately to the Output /
AnnaBridge	172:65be27845400	1179	#define HRTIM_OUTPUTBURSTMODEENTRY_DELAYED (HRTIM_OUTR_DIDL1) /!< Dead-time is inserted on output before entering the idle mode /
AnnaBridge	172:65be27845400	1180	/**
AnnaBridge	172:65be27845400	1181	* @}
AnnaBridge	172:65be27845400	1182	*/
AnnaBridge	172:65be27845400	1183
AnnaBridge	172:65be27845400	1184
AnnaBridge	172:65be27845400	1185	/** @defgroup HRTIM_Capture_Unit_Trigger HRTIM Capture Unit Trigger
AnnaBridge	172:65be27845400	1186	* @{
AnnaBridge	172:65be27845400	1187	* @brief Constants defining the events that can be selected to trigger the
AnnaBridge	172:65be27845400	1188	* capture of the timing unit counter
AnnaBridge	172:65be27845400	1189	*/
AnnaBridge	172:65be27845400	1190	#define HRTIM_CAPTURETRIGGER_NONE 0x00000000U /!< Capture trigger is disabled /
AnnaBridge	172:65be27845400	1191	#define HRTIM_CAPTURETRIGGER_UPDATE (HRTIM_CPT1CR_UPDCPT) /!< The update event triggers the Capture /
AnnaBridge	172:65be27845400	1192	#define HRTIM_CAPTURETRIGGER_EEV_1 (HRTIM_CPT1CR_EXEV1CPT) /!< The External event 1 triggers the Capture /
AnnaBridge	172:65be27845400	1193	#define HRTIM_CAPTURETRIGGER_EEV_2 (HRTIM_CPT1CR_EXEV2CPT) /!< The External event 2 triggers the Capture /
AnnaBridge	172:65be27845400	1194	#define HRTIM_CAPTURETRIGGER_EEV_3 (HRTIM_CPT1CR_EXEV3CPT) /!< The External event 3 triggers the Capture /
AnnaBridge	172:65be27845400	1195	#define HRTIM_CAPTURETRIGGER_EEV_4 (HRTIM_CPT1CR_EXEV4CPT) /!< The External event 4 triggers the Capture /
AnnaBridge	172:65be27845400	1196	#define HRTIM_CAPTURETRIGGER_EEV_5 (HRTIM_CPT1CR_EXEV5CPT) /!< The External event 5 triggers the Capture /
AnnaBridge	172:65be27845400	1197	#define HRTIM_CAPTURETRIGGER_EEV_6 (HRTIM_CPT1CR_EXEV6CPT) /!< The External event 6 triggers the Capture /
AnnaBridge	172:65be27845400	1198	#define HRTIM_CAPTURETRIGGER_EEV_7 (HRTIM_CPT1CR_EXEV7CPT) /!< The External event 7 triggers the Capture /
AnnaBridge	172:65be27845400	1199	#define HRTIM_CAPTURETRIGGER_EEV_8 (HRTIM_CPT1CR_EXEV8CPT) /!< The External event 8 triggers the Capture /
AnnaBridge	172:65be27845400	1200	#define HRTIM_CAPTURETRIGGER_EEV_9 (HRTIM_CPT1CR_EXEV9CPT) /!< The External event 9 triggers the Capture /
AnnaBridge	172:65be27845400	1201	#define HRTIM_CAPTURETRIGGER_EEV_10 (HRTIM_CPT1CR_EXEV10CPT) /!< The External event 10 triggers the Capture /
AnnaBridge	172:65be27845400	1202	#define HRTIM_CAPTURETRIGGER_TA1_SET (HRTIM_CPT1CR_TA1SET) /!< Capture is triggered by TA1 output inactive to active transition /
AnnaBridge	172:65be27845400	1203	#define HRTIM_CAPTURETRIGGER_TA1_RESET (HRTIM_CPT1CR_TA1RST) /!< Capture is triggered by TA1 output active to inactive transition /
AnnaBridge	172:65be27845400	1204	#define HRTIM_CAPTURETRIGGER_TIMERA_CMP1 (HRTIM_CPT1CR_TIMACMP1) /!< Timer A Compare 1 triggers Capture /
AnnaBridge	172:65be27845400	1205	#define HRTIM_CAPTURETRIGGER_TIMERA_CMP2 (HRTIM_CPT1CR_TIMACMP2) /!< Timer A Compare 2 triggers Capture /
AnnaBridge	172:65be27845400	1206	#define HRTIM_CAPTURETRIGGER_TB1_SET (HRTIM_CPT1CR_TB1SET) /!< Capture is triggered by TB1 output inactive to active transition /
AnnaBridge	172:65be27845400	1207	#define HRTIM_CAPTURETRIGGER_TB1_RESET (HRTIM_CPT1CR_TB1RST) /!< Capture is triggered by TB1 output active to inactive transition /
AnnaBridge	172:65be27845400	1208	#define HRTIM_CAPTURETRIGGER_TIMERB_CMP1 (HRTIM_CPT1CR_TIMBCMP1) /!< Timer B Compare 1 triggers Capture /
AnnaBridge	172:65be27845400	1209	#define HRTIM_CAPTURETRIGGER_TIMERB_CMP2 (HRTIM_CPT1CR_TIMBCMP2) /!< Timer B Compare 2 triggers Capture /
AnnaBridge	172:65be27845400	1210	#define HRTIM_CAPTURETRIGGER_TC1_SET (HRTIM_CPT1CR_TC1SET) /!< Capture is triggered by TC1 output inactive to active transition /
AnnaBridge	172:65be27845400	1211	#define HRTIM_CAPTURETRIGGER_TC1_RESET (HRTIM_CPT1CR_TC1RST) /!< Capture is triggered by TC1 output active to inactive transition /
AnnaBridge	172:65be27845400	1212	#define HRTIM_CAPTURETRIGGER_TIMERC_CMP1 (HRTIM_CPT1CR_TIMCCMP1) /!< Timer C Compare 1 triggers Capture /
AnnaBridge	172:65be27845400	1213	#define HRTIM_CAPTURETRIGGER_TIMERC_CMP2 (HRTIM_CPT1CR_TIMCCMP2) /!< Timer C Compare 2 triggers Capture /
AnnaBridge	172:65be27845400	1214	#define HRTIM_CAPTURETRIGGER_TD1_SET (HRTIM_CPT1CR_TD1SET) /!< Capture is triggered by TD1 output inactive to active transition /
AnnaBridge	172:65be27845400	1215	#define HRTIM_CAPTURETRIGGER_TD1_RESET (HRTIM_CPT1CR_TD1RST) /!< Capture is triggered by TD1 output active to inactive transition /
AnnaBridge	172:65be27845400	1216	#define HRTIM_CAPTURETRIGGER_TIMERD_CMP1 (HRTIM_CPT1CR_TIMDCMP1) /!< Timer D Compare 1 triggers Capture /
AnnaBridge	172:65be27845400	1217	#define HRTIM_CAPTURETRIGGER_TIMERD_CMP2 (HRTIM_CPT1CR_TIMDCMP2) /!< Timer D Compare 2 triggers Capture /
AnnaBridge	172:65be27845400	1218	#define HRTIM_CAPTURETRIGGER_TE1_SET (HRTIM_CPT1CR_TE1SET) /!< Capture is triggered by TE1 output inactive to active transition /
AnnaBridge	172:65be27845400	1219	#define HRTIM_CAPTURETRIGGER_TE1_RESET (HRTIM_CPT1CR_TE1RST) /!< Capture is triggered by TE1 output active to inactive transition /
AnnaBridge	172:65be27845400	1220	#define HRTIM_CAPTURETRIGGER_TIMERE_CMP1 (HRTIM_CPT1CR_TIMECMP1) /!< Timer E Compare 1 triggers Capture /
AnnaBridge	172:65be27845400	1221	#define HRTIM_CAPTURETRIGGER_TIMERE_CMP2 (HRTIM_CPT1CR_TIMECMP2) /!< Timer E Compare 2 triggers Capture /
AnnaBridge	172:65be27845400	1222	/**
AnnaBridge	172:65be27845400	1223	* @}
AnnaBridge	172:65be27845400	1224	*/
AnnaBridge	172:65be27845400	1225	/**
AnnaBridge	172:65be27845400	1226	* @}
AnnaBridge	172:65be27845400	1227	*/
AnnaBridge	172:65be27845400	1228
AnnaBridge	172:65be27845400	1229	/** @defgroup HRTIM_Timer_External_Event_Filter HRTIM Timer External Event Filter
AnnaBridge	172:65be27845400	1230	* @{
AnnaBridge	172:65be27845400	1231	* @brief Constants defining the event filtering applied to external events
AnnaBridge	172:65be27845400	1232	* by a timer
AnnaBridge	172:65be27845400	1233	*/
AnnaBridge	172:65be27845400	1234	#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
AnnaBridge	172:65be27845400	1235	#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /!< Blanking from counter reset/roll-over to Compare 1U /
AnnaBridge	172:65be27845400	1236	#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /!< Blanking from counter reset/roll-over to Compare 2U /
AnnaBridge	172:65be27845400	1237	#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 \| HRTIM_EEFR1_EE1FLTR_0) /!< Blanking from counter reset/roll-over to Compare 3U /
AnnaBridge	172:65be27845400	1238	#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /!< Blanking from counter reset/roll-over to Compare 4U /
AnnaBridge	172:65be27845400	1239	#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 \| HRTIM_EEFR1_EE1FLTR_0) /!< Blanking from another timing unit: TIMFLTR1 source /
AnnaBridge	172:65be27845400	1240	#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 \| HRTIM_EEFR1_EE1FLTR_1) /!< Blanking from another timing unit: TIMFLTR2 source /
AnnaBridge	172:65be27845400	1241	#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 \| HRTIM_EEFR1_EE1FLTR_1 \| HRTIM_EEFR1_EE1FLTR_0) /!< Blanking from another timing unit: TIMFLTR3 source /
AnnaBridge	172:65be27845400	1242	#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) /!< Blanking from another timing unit: TIMFLTR4 source /
AnnaBridge	172:65be27845400	1243	#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_0) /!< Blanking from another timing unit: TIMFLTR5 source /
AnnaBridge	172:65be27845400	1244	#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_1) /!< Blanking from another timing unit: TIMFLTR6 source /
AnnaBridge	172:65be27845400	1245	#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_1 \| HRTIM_EEFR1_EE1FLTR_0) /!< Blanking from another timing unit: TIMFLTR7 source /
AnnaBridge	172:65be27845400	1246	#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_2) /!< Blanking from another timing unit: TIMFLTR8 source /
AnnaBridge	172:65be27845400	1247	#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_2 \| HRTIM_EEFR1_EE1FLTR_0) /!< Windowing from counter reset/roll-over to Compare 2U /
AnnaBridge	172:65be27845400	1248	#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_2 \| HRTIM_EEFR1_EE1FLTR_1) /!< Windowing from counter reset/roll-over to Compare 3U /
AnnaBridge	172:65be27845400	1249	#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_2 \| HRTIM_EEFR1_EE1FLTR_1 \| HRTIM_EEFR1_EE1FLTR_3 \| HRTIM_EEFR1_EE1FLTR_2 \| HRTIM_EEFR1_EE1FLTR_0) /!< Windowing from another timing unit: TIMWIN source /
AnnaBridge	172:65be27845400	1250	/**
AnnaBridge	172:65be27845400	1251	* @}
AnnaBridge	172:65be27845400	1252	*/
AnnaBridge	172:65be27845400	1253
AnnaBridge	172:65be27845400	1254	/** @defgroup HRTIM_Timer_External_Event_Latch HRTIM Timer External Event Latch
AnnaBridge	172:65be27845400	1255	* @{
AnnaBridge	172:65be27845400	1256	* @brief Constants defining whether or not the external event is
AnnaBridge	172:65be27845400	1257	* memorized (latched) and generated as soon as the blanking period
AnnaBridge	172:65be27845400	1258	* is completed or the window ends
AnnaBridge	172:65be27845400	1259	*/
AnnaBridge	172:65be27845400	1260	#define HRTIM_TIMEVENTLATCH_DISABLED (0x00000000U) /!< Event is ignored if it happens during a blank, or passed through during a window /
AnnaBridge	172:65be27845400	1261	#define HRTIM_TIMEVENTLATCH_ENABLED HRTIM_EEFR1_EE1LTCH /!< Event is latched and delayed till the end of the blanking or windowing period /
AnnaBridge	172:65be27845400	1262	/**
AnnaBridge	172:65be27845400	1263	* @}
AnnaBridge	172:65be27845400	1264	*/
AnnaBridge	172:65be27845400	1265
AnnaBridge	172:65be27845400	1266	/** @defgroup HRTIM_Deadtime_Prescaler_Ratio HRTIM Dead-time Prescaler Ratio
AnnaBridge	172:65be27845400	1267	* @{
AnnaBridge	172:65be27845400	1268	* @brief Constants defining division ratio between the timer clock frequency
AnnaBridge	172:65be27845400	1269	* (fHRTIM) and the dead-time generator clock (fDTG)
AnnaBridge	172:65be27845400	1270	*/
AnnaBridge	172:65be27845400	1271	#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8 (0x00000000U) /!< fDTG = fHRTIM 8U */
AnnaBridge	172:65be27845400	1272	#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4 (HRTIM_DTR_DTPRSC_0) /!< fDTG = fHRTIM 4U */
AnnaBridge	172:65be27845400	1273	#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2 (HRTIM_DTR_DTPRSC_1) /!< fDTG = fHRTIM 2U */
AnnaBridge	172:65be27845400	1274	#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1 (HRTIM_DTR_DTPRSC_1 \| HRTIM_DTR_DTPRSC_0) /!< fDTG = fHRTIM /
AnnaBridge	172:65be27845400	1275	#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2 (HRTIM_DTR_DTPRSC_2) /!< fDTG = fHRTIM / 2U /
AnnaBridge	172:65be27845400	1276	#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4 (HRTIM_DTR_DTPRSC_2 \| HRTIM_DTR_DTPRSC_0) /!< fDTG = fHRTIM / 4U /
AnnaBridge	172:65be27845400	1277	#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8 (HRTIM_DTR_DTPRSC_2 \| HRTIM_DTR_DTPRSC_1) /!< fDTG = fHRTIM / 8U /
AnnaBridge	172:65be27845400	1278	#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16 (HRTIM_DTR_DTPRSC_2 \| HRTIM_DTR_DTPRSC_1 \| HRTIM_DTR_DTPRSC_0) /!< fDTG = fHRTIM / 16U /
AnnaBridge	172:65be27845400	1279	/**
AnnaBridge	172:65be27845400	1280	* @}
AnnaBridge	172:65be27845400	1281	*/
AnnaBridge	172:65be27845400	1282
AnnaBridge	172:65be27845400	1283	/** @defgroup HRTIM_Deadtime_Rising_Sign HRTIM Dead-time Rising Sign
AnnaBridge	172:65be27845400	1284	* @{
AnnaBridge	172:65be27845400	1285	* @brief Constants defining whether the dead-time is positive or negative
AnnaBridge	172:65be27845400	1286	* (overlapping signal) on rising edge
AnnaBridge	172:65be27845400	1287	*/
AnnaBridge	172:65be27845400	1288	#define HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE (0x00000000U) /!< Positive dead-time on rising edge /
AnnaBridge	172:65be27845400	1289	#define HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE (HRTIM_DTR_SDTR) /!< Negative dead-time on rising edge /
AnnaBridge	172:65be27845400	1290	/**
AnnaBridge	172:65be27845400	1291	* @}
AnnaBridge	172:65be27845400	1292	*/
AnnaBridge	172:65be27845400	1293
AnnaBridge	172:65be27845400	1294	/** @defgroup HRTIM_Deadtime_Rising_Lock HRTIM Dead-time Rising Lock
AnnaBridge	172:65be27845400	1295	* @{
AnnaBridge	172:65be27845400	1296	* @brief Constants defining whether or not the dead-time (rising sign and
AnnaBridge	172:65be27845400	1297	* value) is write protected
AnnaBridge	172:65be27845400	1298	*/
AnnaBridge	172:65be27845400	1299	#define HRTIM_TIMDEADTIME_RISINGLOCK_WRITE (0x00000000U) /!< Dead-time rising value and sign is writeable /
AnnaBridge	172:65be27845400	1300	#define HRTIM_TIMDEADTIME_RISINGLOCK_READONLY (HRTIM_DTR_DTRLK) /!< Dead-time rising value and sign is read-only /
AnnaBridge	172:65be27845400	1301	/**
AnnaBridge	172:65be27845400	1302	* @}
AnnaBridge	172:65be27845400	1303	*/
AnnaBridge	172:65be27845400	1304
AnnaBridge	172:65be27845400	1305	/** @defgroup HRTIM_Deadtime_Rising_Sign_Lock HRTIM Dead-time Rising Sign Lock
AnnaBridge	172:65be27845400	1306	* @{
AnnaBridge	172:65be27845400	1307	* @brief Constants defining whether or not the dead-time rising sign is write
AnnaBridge	172:65be27845400	1308	* protected
AnnaBridge	172:65be27845400	1309	*/
AnnaBridge	172:65be27845400	1310	#define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE (0x00000000U) /!< Dead-time rising sign is writeable /
AnnaBridge	172:65be27845400	1311	#define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY (HRTIM_DTR_DTRSLK) /!< Dead-time rising sign is read-only /
AnnaBridge	172:65be27845400	1312	/**
AnnaBridge	172:65be27845400	1313	* @}
AnnaBridge	172:65be27845400	1314	*/
AnnaBridge	172:65be27845400	1315
AnnaBridge	172:65be27845400	1316	/** @defgroup HRTIM_Deadtime_Falling_Sign HRTIM Dead-time Falling Sign
AnnaBridge	172:65be27845400	1317	* @{
AnnaBridge	172:65be27845400	1318	* @brief Constants defining whether the dead-time is positive or negative
AnnaBridge	172:65be27845400	1319	* (overlapping signal) on falling edge
AnnaBridge	172:65be27845400	1320	*/
AnnaBridge	172:65be27845400	1321	#define HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE (0x00000000U) /!< Positive dead-time on falling edge /
AnnaBridge	172:65be27845400	1322	#define HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE (HRTIM_DTR_SDTF) /!< Negative dead-time on falling edge /
AnnaBridge	172:65be27845400	1323	/**
AnnaBridge	172:65be27845400	1324	* @}
AnnaBridge	172:65be27845400	1325	*/
AnnaBridge	172:65be27845400	1326
AnnaBridge	172:65be27845400	1327	/** @defgroup HRTIM_Deadtime_Falling_Lock HRTIM Dead-time Falling Lock
AnnaBridge	172:65be27845400	1328	* @{
AnnaBridge	172:65be27845400	1329	* @brief Constants defining whether or not the dead-time (falling sign and
AnnaBridge	172:65be27845400	1330	* value) is write protected
AnnaBridge	172:65be27845400	1331	*/
AnnaBridge	172:65be27845400	1332	#define HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE (0x00000000U) /!< Dead-time falling value and sign is writeable /
AnnaBridge	172:65be27845400	1333	#define HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY (HRTIM_DTR_DTFLK) /!< Dead-time falling value and sign is read-only /
AnnaBridge	172:65be27845400	1334	/**
AnnaBridge	172:65be27845400	1335	* @}
AnnaBridge	172:65be27845400	1336	*/
AnnaBridge	172:65be27845400	1337
AnnaBridge	172:65be27845400	1338	/** @defgroup HRTIM_Deadtime_Falling_Sign_Lock HRTIM Dead-time Falling Sign Lock
AnnaBridge	172:65be27845400	1339	* @{
AnnaBridge	172:65be27845400	1340	* @brief Constants defining whether or not the dead-time falling sign is write
AnnaBridge	172:65be27845400	1341	* protected
AnnaBridge	172:65be27845400	1342	*/
AnnaBridge	172:65be27845400	1343	#define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE (0x00000000U) /!< Dead-time falling sign is writeable /
AnnaBridge	172:65be27845400	1344	#define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY (HRTIM_DTR_DTFSLK) /!< Dead-time falling sign is read-only /
AnnaBridge	172:65be27845400	1345	/**
AnnaBridge	172:65be27845400	1346	* @}
AnnaBridge	172:65be27845400	1347	*/
AnnaBridge	172:65be27845400	1348
AnnaBridge	172:65be27845400	1349	/** @defgroup HRTIM_Chopper_Frequency HRTIM Chopper Frequency
AnnaBridge	172:65be27845400	1350	* @{
AnnaBridge	172:65be27845400	1351	* @brief Constants defining the frequency of the generated high frequency carrier
AnnaBridge	172:65be27845400	1352	*/
AnnaBridge	172:65be27845400	1353	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV16 (0x000000U) /!< fCHPFRQ = fHRTIM / 16 /
AnnaBridge	172:65be27845400	1354	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV32 (HRTIM_CHPR_CARFRQ_0) /!< fCHPFRQ = fHRTIM / 32 /
AnnaBridge	172:65be27845400	1355	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV48 (HRTIM_CHPR_CARFRQ_1) /!< fCHPFRQ = fHRTIM / 48 /
AnnaBridge	172:65be27845400	1356	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV64 (HRTIM_CHPR_CARFRQ_1 \| HRTIM_CHPR_CARFRQ_0) /!< fCHPFRQ = fHRTIM / 64 /
AnnaBridge	172:65be27845400	1357	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV80 (HRTIM_CHPR_CARFRQ_2) /!< fCHPFRQ = fHRTIM / 80 /
AnnaBridge	172:65be27845400	1358	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV96 (HRTIM_CHPR_CARFRQ_2 \| HRTIM_CHPR_CARFRQ_0) /!< fCHPFRQ = fHRTIM / 96 /
AnnaBridge	172:65be27845400	1359	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV112 (HRTIM_CHPR_CARFRQ_2 \| HRTIM_CHPR_CARFRQ_1) /!< fCHPFRQ = fHRTIM / 112 /
AnnaBridge	172:65be27845400	1360	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV128 (HRTIM_CHPR_CARFRQ_2 \| HRTIM_CHPR_CARFRQ_1 \| HRTIM_CHPR_CARFRQ_0) /!< fCHPFRQ = fHRTIM / 128 /
AnnaBridge	172:65be27845400	1361	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV144 (HRTIM_CHPR_CARFRQ_3) /!< fCHPFRQ = fHRTIM / 144 /
AnnaBridge	172:65be27845400	1362	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV160 (HRTIM_CHPR_CARFRQ_3 \| HRTIM_CHPR_CARFRQ_0) /!< fCHPFRQ = fHRTIM / 160 /
AnnaBridge	172:65be27845400	1363	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV176 (HRTIM_CHPR_CARFRQ_3 \| HRTIM_CHPR_CARFRQ_1) /!< fCHPFRQ = fHRTIM / 176 /
AnnaBridge	172:65be27845400	1364	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV192 (HRTIM_CHPR_CARFRQ_3 \| HRTIM_CHPR_CARFRQ_1 \| HRTIM_CHPR_CARFRQ_0) /!< fCHPFRQ = fHRTIM / 192 /
AnnaBridge	172:65be27845400	1365	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV208 (HRTIM_CHPR_CARFRQ_3 \| HRTIM_CHPR_CARFRQ_2) /!< fCHPFRQ = fHRTIM / 208 /
AnnaBridge	172:65be27845400	1366	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV224 (HRTIM_CHPR_CARFRQ_3 \| HRTIM_CHPR_CARFRQ_2 \| HRTIM_CHPR_CARFRQ_0) /!< fCHPFRQ = fHRTIM / 224 /
AnnaBridge	172:65be27845400	1367	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV240 (HRTIM_CHPR_CARFRQ_3 \| HRTIM_CHPR_CARFRQ_2 \| HRTIM_CHPR_CARFRQ_1) /!< fCHPFRQ = fHRTIM / 240 /
AnnaBridge	172:65be27845400	1368	#define HRTIM_CHOPPER_PRESCALERRATIO_DIV256 (HRTIM_CHPR_CARFRQ_3 \| HRTIM_CHPR_CARFRQ_2 \| HRTIM_CHPR_CARFRQ_1 \| HRTIM_CHPR_CARFRQ_0) /!< fCHPFRQ = fHRTIM / 256 /
AnnaBridge	172:65be27845400	1369	/**
AnnaBridge	172:65be27845400	1370	* @}
AnnaBridge	172:65be27845400	1371	*/
AnnaBridge	172:65be27845400	1372
AnnaBridge	172:65be27845400	1373	/** @defgroup HRTIM_Chopper_Duty_Cycle HRTIM Chopper Duty Cycle
AnnaBridge	172:65be27845400	1374	* @{
AnnaBridge	172:65be27845400	1375	* @brief Constants defining the duty cycle of the generated high frequency carrier
AnnaBridge	172:65be27845400	1376	* Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)
AnnaBridge	172:65be27845400	1377	*/
AnnaBridge	172:65be27845400	1378	#define HRTIM_CHOPPER_DUTYCYCLE_0 (0x000000U) /!< Only 1st pulse is present /
AnnaBridge	172:65be27845400	1379	#define HRTIM_CHOPPER_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0) /!< Duty cycle of the carrier signal is 12.5U % /
AnnaBridge	172:65be27845400	1380	#define HRTIM_CHOPPER_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1) /!< Duty cycle of the carrier signal is 25U % /
AnnaBridge	172:65be27845400	1381	#define HRTIM_CHOPPER_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 \| HRTIM_CHPR_CARDTY_0) /!< Duty cycle of the carrier signal is 37.5U % /
AnnaBridge	172:65be27845400	1382	#define HRTIM_CHOPPER_DUTYCYCLE_500 (HRTIM_CHPR_CARDTY_2) /!< Duty cycle of the carrier signal is 50U % /
AnnaBridge	172:65be27845400	1383	#define HRTIM_CHOPPER_DUTYCYCLE_625 (HRTIM_CHPR_CARDTY_2 \| HRTIM_CHPR_CARDTY_0) /!< Duty cycle of the carrier signal is 62.5U % /
AnnaBridge	172:65be27845400	1384	#define HRTIM_CHOPPER_DUTYCYCLE_750 (HRTIM_CHPR_CARDTY_2 \| HRTIM_CHPR_CARDTY_1) /!< Duty cycle of the carrier signal is 75U % /
AnnaBridge	172:65be27845400	1385	#define HRTIM_CHOPPER_DUTYCYCLE_875 (HRTIM_CHPR_CARDTY_2 \| HRTIM_CHPR_CARDTY_1 \| HRTIM_CHPR_CARDTY_0) /!< Duty cycle of the carrier signal is 87.5U % /
AnnaBridge	172:65be27845400	1386	/**
AnnaBridge	172:65be27845400	1387	* @}
AnnaBridge	172:65be27845400	1388	*/
AnnaBridge	172:65be27845400	1389
AnnaBridge	172:65be27845400	1390	/** @defgroup HRTIM_Chopper_Start_Pulse_Width HRTIM Chopper Start Pulse Width
AnnaBridge	172:65be27845400	1391	* @{
AnnaBridge	172:65be27845400	1392	* @brief Constants defining the pulse width of the first pulse of the generated
AnnaBridge	172:65be27845400	1393	* high frequency carrier
AnnaBridge	172:65be27845400	1394	*/
AnnaBridge	172:65be27845400	1395	#define HRTIM_CHOPPER_PULSEWIDTH_16 (0x000000U) /!< tSTPW = tHRTIM x 16 /
AnnaBridge	172:65be27845400	1396	#define HRTIM_CHOPPER_PULSEWIDTH_32 (HRTIM_CHPR_STRPW_0) /!< tSTPW = tHRTIM x 32 /
AnnaBridge	172:65be27845400	1397	#define HRTIM_CHOPPER_PULSEWIDTH_48 (HRTIM_CHPR_STRPW_1) /!< tSTPW = tHRTIM x 48 /
AnnaBridge	172:65be27845400	1398	#define HRTIM_CHOPPER_PULSEWIDTH_64 (HRTIM_CHPR_STRPW_1 \| HRTIM_CHPR_STRPW_0) /!< tSTPW = tHRTIM x 64 /
AnnaBridge	172:65be27845400	1399	#define HRTIM_CHOPPER_PULSEWIDTH_80 (HRTIM_CHPR_STRPW_2) /!< tSTPW = tHRTIM x 80 /
AnnaBridge	172:65be27845400	1400	#define HRTIM_CHOPPER_PULSEWIDTH_96 (HRTIM_CHPR_STRPW_2 \| HRTIM_CHPR_STRPW_0) /!< tSTPW = tHRTIM x 96 /
AnnaBridge	172:65be27845400	1401	#define HRTIM_CHOPPER_PULSEWIDTH_112 (HRTIM_CHPR_STRPW_2 \| HRTIM_CHPR_STRPW_1) /!< tSTPW = tHRTIM x 112 /
AnnaBridge	172:65be27845400	1402	#define HRTIM_CHOPPER_PULSEWIDTH_128 (HRTIM_CHPR_STRPW_2 \| HRTIM_CHPR_STRPW_1 \| HRTIM_CHPR_STRPW_0) /!< tSTPW = tHRTIM x 128 /
AnnaBridge	172:65be27845400	1403	#define HRTIM_CHOPPER_PULSEWIDTH_144 (HRTIM_CHPR_STRPW_3) /!< tSTPW = tHRTIM x 144 /
AnnaBridge	172:65be27845400	1404	#define HRTIM_CHOPPER_PULSEWIDTH_160 (HRTIM_CHPR_STRPW_3 \| HRTIM_CHPR_STRPW_0) /!< tSTPW = tHRTIM x 160 /
AnnaBridge	172:65be27845400	1405	#define HRTIM_CHOPPER_PULSEWIDTH_176 (HRTIM_CHPR_STRPW_3 \| HRTIM_CHPR_STRPW_1) /!< tSTPW = tHRTIM x 176 /
AnnaBridge	172:65be27845400	1406	#define HRTIM_CHOPPER_PULSEWIDTH_192 (HRTIM_CHPR_STRPW_3 \| HRTIM_CHPR_STRPW_1 \| HRTIM_CHPR_STRPW_0) /!< tSTPW = tHRTIM x 192 /
AnnaBridge	172:65be27845400	1407	#define HRTIM_CHOPPER_PULSEWIDTH_208 (HRTIM_CHPR_STRPW_3 \| HRTIM_CHPR_STRPW_2) /!< tSTPW = tHRTIM x 208 /
AnnaBridge	172:65be27845400	1408	#define HRTIM_CHOPPER_PULSEWIDTH_224 (HRTIM_CHPR_STRPW_3 \| HRTIM_CHPR_STRPW_2 \| HRTIM_CHPR_STRPW_0) /!< tSTPW = tHRTIM x 224 /
AnnaBridge	172:65be27845400	1409	#define HRTIM_CHOPPER_PULSEWIDTH_240 (HRTIM_CHPR_STRPW_3 \| HRTIM_CHPR_STRPW_2 \| HRTIM_CHPR_STRPW_1) /!< tSTPW = tHRTIM x 240 /
AnnaBridge	172:65be27845400	1410	#define HRTIM_CHOPPER_PULSEWIDTH_256 (HRTIM_CHPR_STRPW_3 \| HRTIM_CHPR_STRPW_2 \| HRTIM_CHPR_STRPW_1 \| HRTIM_CHPR_STRPW_0) /!< tSTPW = tHRTIM x 256 /
AnnaBridge	172:65be27845400	1411	/**
AnnaBridge	172:65be27845400	1412	* @}
AnnaBridge	172:65be27845400	1413	*/
AnnaBridge	172:65be27845400	1414
AnnaBridge	172:65be27845400	1415	/** @defgroup HRTIM_Synchronization_Options HRTIM Synchronization Options
AnnaBridge	172:65be27845400	1416	* @{
AnnaBridge	172:65be27845400	1417	* @brief Constants defining the options for synchronizing multiple HRTIM
AnnaBridge	172:65be27845400	1418	* instances, as a master unit (generating a synchronization signal)
AnnaBridge	172:65be27845400	1419	* or as a slave (waiting for a trigger to be synchronized)
AnnaBridge	172:65be27845400	1420	*/
AnnaBridge	172:65be27845400	1421	#define HRTIM_SYNCOPTION_NONE 0x00000000U /!< HRTIM instance doesn't handle external synchronization signals (SYNCIN, SYNCOUT) /
AnnaBridge	172:65be27845400	1422	#define HRTIM_SYNCOPTION_MASTER 0x00000001U /!< HRTIM instance acts as a MASTER, i.e. generates external synchronization output (SYNCOUT)/
AnnaBridge	172:65be27845400	1423	#define HRTIM_SYNCOPTION_SLAVE 0x00000002U /!< HRTIM instance acts as a SLAVE, i.e. it is synchronized by external sources (SYNCIN) /
AnnaBridge	172:65be27845400	1424	/**
AnnaBridge	172:65be27845400	1425	* @}
AnnaBridge	172:65be27845400	1426	*/
AnnaBridge	172:65be27845400	1427
AnnaBridge	172:65be27845400	1428	/** @defgroup HRTIM_Synchronization_Input_Source HRTIM Synchronization Input Source
AnnaBridge	172:65be27845400	1429	* @{
AnnaBridge	172:65be27845400	1430	* @brief Constants defining defining the synchronization input source
AnnaBridge	172:65be27845400	1431	*/
AnnaBridge	172:65be27845400	1432	#define HRTIM_SYNCINPUTSOURCE_NONE 0x00000000U /!< disabled. HRTIM is not synchronized and runs in standalone mode /
AnnaBridge	172:65be27845400	1433	#define HRTIM_SYNCINPUTSOURCE_INTERNALEVENT HRTIM_MCR_SYNC_IN_1 /!< The HRTIM is synchronized with the on-chip timer /
AnnaBridge	172:65be27845400	1434	#define HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT (HRTIM_MCR_SYNC_IN_1 \| HRTIM_MCR_SYNC_IN_0) /!< A positive pulse on SYNCIN input triggers the HRTIM /
AnnaBridge	172:65be27845400	1435	/**
AnnaBridge	172:65be27845400	1436	* @}
AnnaBridge	172:65be27845400	1437	*/
AnnaBridge	172:65be27845400	1438
AnnaBridge	172:65be27845400	1439	/** @defgroup HRTIM_Synchronization_Output_Source HRTIM Synchronization Output Source
AnnaBridge	172:65be27845400	1440	* @{
AnnaBridge	172:65be27845400	1441	* @brief Constants defining the source and event to be sent on the
AnnaBridge	172:65be27845400	1442	* synchronization outputs
AnnaBridge	172:65be27845400	1443	*/
AnnaBridge	172:65be27845400	1444	#define HRTIM_SYNCOUTPUTSOURCE_MASTER_START 0x00000000U /!< A pulse is sent on the SYNCOUT output upon master timer start event /
AnnaBridge	172:65be27845400	1445	#define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /!< A pulse is sent on the SYNCOUT output upon master timer compare 1 event/
AnnaBridge	172:65be27845400	1446	#define HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /!< A pulse is sent on the SYNCOUT output upon timer A start or reset events /
AnnaBridge	172:65be27845400	1447	#define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 \| HRTIM_MCR_SYNC_SRC_0) /!< A pulse is sent on the SYNCOUT output upon timer A compare 1 event /
AnnaBridge	172:65be27845400	1448	/**
AnnaBridge	172:65be27845400	1449	* @}
AnnaBridge	172:65be27845400	1450	*/
AnnaBridge	172:65be27845400	1451
AnnaBridge	172:65be27845400	1452	/** @defgroup HRTIM_Synchronization_Output_Polarity HRTIM Synchronization Output Polarity
AnnaBridge	172:65be27845400	1453	* @{
AnnaBridge	172:65be27845400	1454	* @brief Constants defining the routing and conditioning of the synchronization output event
AnnaBridge	172:65be27845400	1455	*/
AnnaBridge	172:65be27845400	1456	#define HRTIM_SYNCOUTPUTPOLARITY_NONE 0x00000000U /!< Synchronization output event is disabled /
AnnaBridge	172:65be27845400	1457	#define HRTIM_SYNCOUTPUTPOLARITY_POSITIVE (HRTIM_MCR_SYNC_OUT_1) /!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization /
AnnaBridge	172:65be27845400	1458	#define HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE (HRTIM_MCR_SYNC_OUT_1 \| HRTIM_MCR_SYNC_OUT_0) /!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization /
AnnaBridge	172:65be27845400	1459	/**
AnnaBridge	172:65be27845400	1460	* @}
AnnaBridge	172:65be27845400	1461	*/
AnnaBridge	172:65be27845400	1462
AnnaBridge	172:65be27845400	1463	/** @defgroup HRTIM_External_Event_Sources HRTIM External Event Sources
AnnaBridge	172:65be27845400	1464	* @{
AnnaBridge	172:65be27845400	1465	* @brief Constants defining available sources associated to external events
AnnaBridge	172:65be27845400	1466	*/
AnnaBridge	172:65be27845400	1467	#define HRTIM_EVENTSRC_1 (0x00000000U) /!< External event source 1U /
AnnaBridge	172:65be27845400	1468	#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) /!< External event source 2U /
AnnaBridge	172:65be27845400	1469	#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) /!< External event source 3U /
AnnaBridge	172:65be27845400	1470	#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 \| HRTIM_EECR1_EE1SRC_0) /!< External event source 4U /
AnnaBridge	172:65be27845400	1471	/**
AnnaBridge	172:65be27845400	1472	* @}
AnnaBridge	172:65be27845400	1473	*/
AnnaBridge	172:65be27845400	1474
AnnaBridge	172:65be27845400	1475	/** @defgroup HRTIM_External_Event_Polarity HRTIM External Event Polarity
AnnaBridge	172:65be27845400	1476	* @{
AnnaBridge	172:65be27845400	1477	* @brief Constants defining the polarity of an external event
AnnaBridge	172:65be27845400	1478	*/
AnnaBridge	172:65be27845400	1479	#define HRTIM_EVENTPOLARITY_HIGH (0x00000000U) /!< External event is active high /
AnnaBridge	172:65be27845400	1480	#define HRTIM_EVENTPOLARITY_LOW (HRTIM_EECR1_EE1POL) /!< External event is active low /
AnnaBridge	172:65be27845400	1481	/**
AnnaBridge	172:65be27845400	1482	* @}
AnnaBridge	172:65be27845400	1483	*/
AnnaBridge	172:65be27845400	1484
AnnaBridge	172:65be27845400	1485	/** @defgroup HRTIM_External_Event_Sensitivity HRTIM External Event Sensitivity
AnnaBridge	172:65be27845400	1486	* @{
AnnaBridge	172:65be27845400	1487	* @brief Constants defining the sensitivity (level-sensitive or edge-sensitive)
AnnaBridge	172:65be27845400	1488	* of an external event
AnnaBridge	172:65be27845400	1489	*/
AnnaBridge	172:65be27845400	1490	#define HRTIM_EVENTSENSITIVITY_LEVEL (0x00000000U) /!< External event is active on level /
AnnaBridge	172:65be27845400	1491	#define HRTIM_EVENTSENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /!< External event is active on Rising edge /
AnnaBridge	172:65be27845400	1492	#define HRTIM_EVENTSENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /!< External event is active on Falling edge /
AnnaBridge	172:65be27845400	1493	#define HRTIM_EVENTSENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 \| HRTIM_EECR1_EE1SNS_0) /!< External event is active on Rising and Falling edges /
AnnaBridge	172:65be27845400	1494	/**
AnnaBridge	172:65be27845400	1495	* @}
AnnaBridge	172:65be27845400	1496	*/
AnnaBridge	172:65be27845400	1497
AnnaBridge	172:65be27845400	1498	/** @defgroup HRTIM_External_Event_Fast_Mode HRTIM External Event Fast Mode
AnnaBridge	172:65be27845400	1499	* @{
AnnaBridge	172:65be27845400	1500	* @brief Constants defining whether or not an external event is programmed in
AnnaBridge	172:65be27845400	1501	fast mode
AnnaBridge	172:65be27845400	1502	*/
AnnaBridge	172:65be27845400	1503	#define HRTIM_EVENTFASTMODE_DISABLE (0x00000000U) /!< External Event is re-synchronized by the HRTIM logic before acting on outputs /
AnnaBridge	172:65be27845400	1504	#define HRTIM_EVENTFASTMODE_ENABLE (HRTIM_EECR1_EE1FAST) /!< External Event is acting asynchronously on outputs (low latency mode) /
AnnaBridge	172:65be27845400	1505	/**
AnnaBridge	172:65be27845400	1506	* @}
AnnaBridge	172:65be27845400	1507	*/
AnnaBridge	172:65be27845400	1508
AnnaBridge	172:65be27845400	1509	/** @defgroup HRTIM_External_Event_Filter HRTIM External Event Filter
AnnaBridge	172:65be27845400	1510	* @{
AnnaBridge	172:65be27845400	1511	* @brief Constants defining the frequency used to sample an external event 6
AnnaBridge	172:65be27845400	1512	* input and the length (N) of the digital filter applied
AnnaBridge	172:65be27845400	1513	*/
AnnaBridge	172:65be27845400	1514	#define HRTIM_EVENTFILTER_NONE (0x00000000U) /!< Filter disabled /
AnnaBridge	172:65be27845400	1515	#define HRTIM_EVENTFILTER_1 (HRTIM_EECR3_EE6F_0) /!< fSAMPLING= fHRTIM, N=2U /
AnnaBridge	172:65be27845400	1516	#define HRTIM_EVENTFILTER_2 (HRTIM_EECR3_EE6F_1) /!< fSAMPLING= fHRTIM, N=4U /
AnnaBridge	172:65be27845400	1517	#define HRTIM_EVENTFILTER_3 (HRTIM_EECR3_EE6F_1 \| HRTIM_EECR3_EE6F_0) /!< fSAMPLING= fHRTIM, N=8U /
AnnaBridge	172:65be27845400	1518	#define HRTIM_EVENTFILTER_4 (HRTIM_EECR3_EE6F_2) /!< fSAMPLING= fEEVS/2U, N=6U /
AnnaBridge	172:65be27845400	1519	#define HRTIM_EVENTFILTER_5 (HRTIM_EECR3_EE6F_2 \| HRTIM_EECR3_EE6F_0) /!< fSAMPLING= fEEVS/2U, N=8U /
AnnaBridge	172:65be27845400	1520	#define HRTIM_EVENTFILTER_6 (HRTIM_EECR3_EE6F_2 \| HRTIM_EECR3_EE6F_1) /!< fSAMPLING= fEEVS/4U, N=6U /
AnnaBridge	172:65be27845400	1521	#define HRTIM_EVENTFILTER_7 (HRTIM_EECR3_EE6F_2 \| HRTIM_EECR3_EE6F_1 \| HRTIM_EECR3_EE6F_0) /!< fSAMPLING= fEEVS/4U, N=8U /
AnnaBridge	172:65be27845400	1522	#define HRTIM_EVENTFILTER_8 (HRTIM_EECR3_EE6F_3) /!< fSAMPLING= fEEVS/8U, N=6U /
AnnaBridge	172:65be27845400	1523	#define HRTIM_EVENTFILTER_9 (HRTIM_EECR3_EE6F_3 \| HRTIM_EECR3_EE6F_0) /!< fSAMPLING= fEEVS/8U, N=8U /
AnnaBridge	172:65be27845400	1524	#define HRTIM_EVENTFILTER_10 (HRTIM_EECR3_EE6F_3 \| HRTIM_EECR3_EE6F_1) /!< fSAMPLING= fEEVS/16U, N=5U /
AnnaBridge	172:65be27845400	1525	#define HRTIM_EVENTFILTER_11 (HRTIM_EECR3_EE6F_3 \| HRTIM_EECR3_EE6F_1 \| HRTIM_EECR3_EE6F_0) /!< fSAMPLING= fEEVS/16U, N=6U /
AnnaBridge	172:65be27845400	1526	#define HRTIM_EVENTFILTER_12 (HRTIM_EECR3_EE6F_3 \| HRTIM_EECR3_EE6F_2) /!< fSAMPLING= fEEVS/16U, N=8U /
AnnaBridge	172:65be27845400	1527	#define HRTIM_EVENTFILTER_13 (HRTIM_EECR3_EE6F_3 \| HRTIM_EECR3_EE6F_2 \| HRTIM_EECR3_EE6F_0) /!< fSAMPLING= fEEVS/32U, N=5U /
AnnaBridge	172:65be27845400	1528	#define HRTIM_EVENTFILTER_14 (HRTIM_EECR3_EE6F_3 \| HRTIM_EECR3_EE6F_2 \| HRTIM_EECR3_EE6F_1) /!< fSAMPLING= fEEVS/32U, N=6U /
AnnaBridge	172:65be27845400	1529	#define HRTIM_EVENTFILTER_15 (HRTIM_EECR3_EE6F_3 \| HRTIM_EECR3_EE6F_2 \| HRTIM_EECR3_EE6F_1 \| HRTIM_EECR3_EE6F_0) /!< fSAMPLING= fEEVS/32U, N=8U /
AnnaBridge	172:65be27845400	1530	/**
AnnaBridge	172:65be27845400	1531	* @}
AnnaBridge	172:65be27845400	1532	*/
AnnaBridge	172:65be27845400	1533
AnnaBridge	172:65be27845400	1534	/** @defgroup HRTIM_External_Event_Prescaler HRTIM External Event Prescaler
AnnaBridge	172:65be27845400	1535	* @{
AnnaBridge	172:65be27845400	1536	* @brief Constants defining division ratio between the timer clock frequency
AnnaBridge	172:65be27845400	1537	* fHRTIM) and the external event signal sampling clock (fEEVS)
AnnaBridge	172:65be27845400	1538	* used by the digital filters
AnnaBridge	172:65be27845400	1539	*/
AnnaBridge	172:65be27845400	1540	#define HRTIM_EVENTPRESCALER_DIV1 (0x00000000U) /!< fEEVS=fHRTIM /
AnnaBridge	172:65be27845400	1541	#define HRTIM_EVENTPRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0) /!< fEEVS=fHRTIM / 2U /
AnnaBridge	172:65be27845400	1542	#define HRTIM_EVENTPRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1) /!< fEEVS=fHRTIM / 4U /
AnnaBridge	172:65be27845400	1543	#define HRTIM_EVENTPRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 \| HRTIM_EECR3_EEVSD_0) /!< fEEVS=fHRTIM / 8U /
AnnaBridge	172:65be27845400	1544	/**
AnnaBridge	172:65be27845400	1545	* @}
AnnaBridge	172:65be27845400	1546	*/
AnnaBridge	172:65be27845400	1547
AnnaBridge	172:65be27845400	1548	/** @defgroup HRTIM_Fault_Sources HRTIM Fault Sources
AnnaBridge	172:65be27845400	1549	* @{
AnnaBridge	172:65be27845400	1550	* @brief Constants defining whether a fault is triggered by any external
AnnaBridge	172:65be27845400	1551	* or internal fault source
AnnaBridge	172:65be27845400	1552	*/
AnnaBridge	172:65be27845400	1553	#define HRTIM_FAULTSOURCE_DIGITALINPUT (0x00000000U) /!< Fault input is FLT input pin /
AnnaBridge	172:65be27845400	1554	#define HRTIM_FAULTSOURCE_INTERNAL (HRTIM_FLTINR1_FLT1SRC) /!< Fault input is FLT_Int signal (e.g. internal comparator) /
AnnaBridge	172:65be27845400	1555	/**
AnnaBridge	172:65be27845400	1556	* @}
AnnaBridge	172:65be27845400	1557	*/
AnnaBridge	172:65be27845400	1558
AnnaBridge	172:65be27845400	1559	/** @defgroup HRTIM_Fault_Polarity HRTIM Fault Polarity
AnnaBridge	172:65be27845400	1560	* @{
AnnaBridge	172:65be27845400	1561	* @brief Constants defining the polarity of a fault event
AnnaBridge	172:65be27845400	1562	*/
AnnaBridge	172:65be27845400	1563	#define HRTIM_FAULTPOLARITY_LOW (0x00000000U) /!< Fault input is active low /
AnnaBridge	172:65be27845400	1564	#define HRTIM_FAULTPOLARITY_HIGH (HRTIM_FLTINR1_FLT1P) /!< Fault input is active high /
AnnaBridge	172:65be27845400	1565	/**
AnnaBridge	172:65be27845400	1566	* @}
AnnaBridge	172:65be27845400	1567	*/
AnnaBridge	172:65be27845400	1568
AnnaBridge	172:65be27845400	1569	/** @defgroup HRTIM_Fault_Filter HRTIM Fault Filter
AnnaBridge	172:65be27845400	1570	* @{
AnnaBridge	172:65be27845400	1571	* @ brief Constants defining the frequency used to sample the fault input and
AnnaBridge	172:65be27845400	1572	* the length (N) of the digital filter applied
AnnaBridge	172:65be27845400	1573	*/
AnnaBridge	172:65be27845400	1574	#define HRTIM_FAULTFILTER_NONE (0x00000000U) /!< Filter disabled /
AnnaBridge	172:65be27845400	1575	#define HRTIM_FAULTFILTER_1 (HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fHRTIM, N=2U /
AnnaBridge	172:65be27845400	1576	#define HRTIM_FAULTFILTER_2 (HRTIM_FLTINR1_FLT1F_1) /!< fSAMPLING= fHRTIM, N=4U /
AnnaBridge	172:65be27845400	1577	#define HRTIM_FAULTFILTER_3 (HRTIM_FLTINR1_FLT1F_1 \| HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fHRTIM, N=8U /
AnnaBridge	172:65be27845400	1578	#define HRTIM_FAULTFILTER_4 (HRTIM_FLTINR1_FLT1F_2) /!< fSAMPLING= fFLTS/2U, N=6U /
AnnaBridge	172:65be27845400	1579	#define HRTIM_FAULTFILTER_5 (HRTIM_FLTINR1_FLT1F_2 \| HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fFLTS/2U, N=8U /
AnnaBridge	172:65be27845400	1580	#define HRTIM_FAULTFILTER_6 (HRTIM_FLTINR1_FLT1F_2 \| HRTIM_FLTINR1_FLT1F_1) /!< fSAMPLING= fFLTS/4U, N=6U /
AnnaBridge	172:65be27845400	1581	#define HRTIM_FAULTFILTER_7 (HRTIM_FLTINR1_FLT1F_2 \| HRTIM_FLTINR1_FLT1F_1 \| HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fFLTS/4U, N=8U /
AnnaBridge	172:65be27845400	1582	#define HRTIM_FAULTFILTER_8 (HRTIM_FLTINR1_FLT1F_3) /!< fSAMPLING= fFLTS/8U, N=6U /
AnnaBridge	172:65be27845400	1583	#define HRTIM_FAULTFILTER_9 (HRTIM_FLTINR1_FLT1F_3 \| HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fFLTS/8U, N=8U /
AnnaBridge	172:65be27845400	1584	#define HRTIM_FAULTFILTER_10 (HRTIM_FLTINR1_FLT1F_3 \| HRTIM_FLTINR1_FLT1F_1) /!< fSAMPLING= fFLTS/16U, N=5U /
AnnaBridge	172:65be27845400	1585	#define HRTIM_FAULTFILTER_11 (HRTIM_FLTINR1_FLT1F_3 \| HRTIM_FLTINR1_FLT1F_1 \| HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fFLTS/16U, N=6U /
AnnaBridge	172:65be27845400	1586	#define HRTIM_FAULTFILTER_12 (HRTIM_FLTINR1_FLT1F_3 \| HRTIM_FLTINR1_FLT1F_2) /!< fSAMPLING= fFLTS/16U, N=8U /
AnnaBridge	172:65be27845400	1587	#define HRTIM_FAULTFILTER_13 (HRTIM_FLTINR1_FLT1F_3 \| HRTIM_FLTINR1_FLT1F_2 \| HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fFLTS/32U, N=5U /
AnnaBridge	172:65be27845400	1588	#define HRTIM_FAULTFILTER_14 (HRTIM_FLTINR1_FLT1F_3 \| HRTIM_FLTINR1_FLT1F_2 \| HRTIM_FLTINR1_FLT1F_1) /!< fSAMPLING= fFLTS/32U, N=6U /
AnnaBridge	172:65be27845400	1589	#define HRTIM_FAULTFILTER_15 (HRTIM_FLTINR1_FLT1F_3 \| HRTIM_FLTINR1_FLT1F_2 \| HRTIM_FLTINR1_FLT1F_1 \| HRTIM_FLTINR1_FLT1F_0) /!< fSAMPLING= fFLTS/32U, N=8U /
AnnaBridge	172:65be27845400	1590	/**
AnnaBridge	172:65be27845400	1591	* @}
AnnaBridge	172:65be27845400	1592	*/
AnnaBridge	172:65be27845400	1593
AnnaBridge	172:65be27845400	1594	/** @defgroup HRTIM_Fault_Lock HRTIM Fault Lock
AnnaBridge	172:65be27845400	1595	* @{
AnnaBridge	172:65be27845400	1596	* @brief Constants defining whether or not the fault programming bits are
AnnaBridge	172:65be27845400	1597	write protected
AnnaBridge	172:65be27845400	1598	*/
AnnaBridge	172:65be27845400	1599	#define HRTIM_FAULTLOCK_READWRITE (0x00000000U) /!< Fault settings bits are read/write /
AnnaBridge	172:65be27845400	1600	#define HRTIM_FAULTLOCK_READONLY (HRTIM_FLTINR1_FLT1LCK) /!< Fault settings bits are read only /
AnnaBridge	172:65be27845400	1601	/**
AnnaBridge	172:65be27845400	1602	* @}
AnnaBridge	172:65be27845400	1603	*/
AnnaBridge	172:65be27845400	1604
AnnaBridge	172:65be27845400	1605	/** @defgroup HRTIM_External_Fault_Prescaler HRTIM External Fault Prescaler
AnnaBridge	172:65be27845400	1606	* @{
AnnaBridge	172:65be27845400	1607	* @brief Constants defining the division ratio between the timer clock
AnnaBridge	172:65be27845400	1608	* frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used
AnnaBridge	172:65be27845400	1609	* by the digital filters.
AnnaBridge	172:65be27845400	1610	*/
AnnaBridge	172:65be27845400	1611	#define HRTIM_FAULTPRESCALER_DIV1 (0x00000000U) /!< fFLTS=fHRTIM /
AnnaBridge	172:65be27845400	1612	#define HRTIM_FAULTPRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0) /!< fFLTS=fHRTIM / 2U /
AnnaBridge	172:65be27845400	1613	#define HRTIM_FAULTPRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1) /!< fFLTS=fHRTIM / 4U /
AnnaBridge	172:65be27845400	1614	#define HRTIM_FAULTPRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 \| HRTIM_FLTINR2_FLTSD_0) /!< fFLTS=fHRTIM / 8U /
AnnaBridge	172:65be27845400	1615	/**
AnnaBridge	172:65be27845400	1616	* @}
AnnaBridge	172:65be27845400	1617	*/
AnnaBridge	172:65be27845400	1618
AnnaBridge	172:65be27845400	1619	/** @defgroup HRTIM_Burst_Mode_Operating_Mode HRTIM Burst Mode Operating Mode
AnnaBridge	172:65be27845400	1620	* @{
AnnaBridge	172:65be27845400	1621	* @brief Constants defining if the burst mode is entered once or if it is
AnnaBridge	172:65be27845400	1622	* continuously operating
AnnaBridge	172:65be27845400	1623	*/
AnnaBridge	172:65be27845400	1624	#define HRTIM_BURSTMODE_SINGLESHOT (0x00000000U) /!< Burst mode operates in single shot mode /
AnnaBridge	172:65be27845400	1625	#define HRTIM_BURSTMODE_CONTINOUS (HRTIM_BMCR_BMOM) /!< Burst mode operates in continuous mode /
AnnaBridge	172:65be27845400	1626	/**
AnnaBridge	172:65be27845400	1627	* @}
AnnaBridge	172:65be27845400	1628	*/
AnnaBridge	172:65be27845400	1629
AnnaBridge	172:65be27845400	1630	/** @defgroup HRTIM_Burst_Mode_Clock_Source HRTIM Burst Mode Clock Source
AnnaBridge	172:65be27845400	1631	* @{
AnnaBridge	172:65be27845400	1632	* @brief Constants defining the clock source for the burst mode counter
AnnaBridge	172:65be27845400	1633	*/
AnnaBridge	172:65be27845400	1634	#define HRTIM_BURSTMODECLOCKSOURCE_MASTER (0x00000000U) /!< Master timer counter reset/roll-over is used as clock source for the burst mode counter /
AnnaBridge	172:65be27845400	1635	#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_A (HRTIM_BMCR_BMCLK_0) /!< Timer A counter reset/roll-over is used as clock source for the burst mode counter /
AnnaBridge	172:65be27845400	1636	#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_B (HRTIM_BMCR_BMCLK_1) /!< Timer B counter reset/roll-over is used as clock source for the burst mode counter /
AnnaBridge	172:65be27845400	1637	#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_C (HRTIM_BMCR_BMCLK_1 \| HRTIM_BMCR_BMCLK_0) /!< Timer C counter reset/roll-over is used as clock source for the burst mode counter /
AnnaBridge	172:65be27845400	1638	#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_D (HRTIM_BMCR_BMCLK_2) /!< Timer D counter reset/roll-over is used as clock source for the burst mode counter /
AnnaBridge	172:65be27845400	1639	#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_E (HRTIM_BMCR_BMCLK_2 \| HRTIM_BMCR_BMCLK_0) /!< Timer E counter reset/roll-over is used as clock source for the burst mode counter /
AnnaBridge	172:65be27845400	1640	#define HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC (HRTIM_BMCR_BMCLK_2 \| HRTIM_BMCR_BMCLK_1) /!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock /
AnnaBridge	172:65be27845400	1641	#define HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC (HRTIM_BMCR_BMCLK_2 \| HRTIM_BMCR_BMCLK_1 \| HRTIM_BMCR_BMCLK_0) /!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock /
AnnaBridge	172:65be27845400	1642	#define HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO (HRTIM_BMCR_BMCLK_3) /!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock /
AnnaBridge	172:65be27845400	1643	#define HRTIM_BURSTMODECLOCKSOURCE_FHRTIM (HRTIM_BMCR_BMCLK_3 \| HRTIM_BMCR_BMCLK_1) /!< Prescaled fHRTIM clock is used as clock source for the burst mode counter /
AnnaBridge	172:65be27845400	1644	/**
AnnaBridge	172:65be27845400	1645	* @}
AnnaBridge	172:65be27845400	1646	*/
AnnaBridge	172:65be27845400	1647
AnnaBridge	172:65be27845400	1648	/** @defgroup HRTIM_Burst_Mode_Prescaler HRTIM Burst Mode Prescaler
AnnaBridge	172:65be27845400	1649	* @{
AnnaBridge	172:65be27845400	1650	* @brief Constants defining the prescaling ratio of the fHRTIM clock
AnnaBridge	172:65be27845400	1651	* for the burst mode controller
AnnaBridge	172:65be27845400	1652	*/
AnnaBridge	172:65be27845400	1653	#define HRTIM_BURSTMODEPRESCALER_DIV1 (0x00000000U) /!< fBRST = fHRTIM /
AnnaBridge	172:65be27845400	1654	#define HRTIM_BURSTMODEPRESCALER_DIV2 (HRTIM_BMCR_BMPRSC_0) /!< fBRST = fHRTIM/2U /
AnnaBridge	172:65be27845400	1655	#define HRTIM_BURSTMODEPRESCALER_DIV4 (HRTIM_BMCR_BMPRSC_1) /!< fBRST = fHRTIM/4U /
AnnaBridge	172:65be27845400	1656	#define HRTIM_BURSTMODEPRESCALER_DIV8 (HRTIM_BMCR_BMPRSC_1 \| HRTIM_BMCR_BMPRSC_0) /!< fBRST = fHRTIM/8U /
AnnaBridge	172:65be27845400	1657	#define HRTIM_BURSTMODEPRESCALER_DIV16 (HRTIM_BMCR_BMPRSC_2) /!< fBRST = fHRTIM/16U /
AnnaBridge	172:65be27845400	1658	#define HRTIM_BURSTMODEPRESCALER_DIV32 (HRTIM_BMCR_BMPRSC_2 \| HRTIM_BMCR_BMPRSC_0) /!< fBRST = fHRTIM/32U /
AnnaBridge	172:65be27845400	1659	#define HRTIM_BURSTMODEPRESCALER_DIV64 (HRTIM_BMCR_BMPRSC_2 \| HRTIM_BMCR_BMPRSC_1) /!< fBRST = fHRTIM/64U /
AnnaBridge	172:65be27845400	1660	#define HRTIM_BURSTMODEPRESCALER_DIV128 (HRTIM_BMCR_BMPRSC_2 \| HRTIM_BMCR_BMPRSC_1 \| HRTIM_BMCR_BMPRSC_0) /!< fBRST = fHRTIM/128U /
AnnaBridge	172:65be27845400	1661	#define HRTIM_BURSTMODEPRESCALER_DIV256 (HRTIM_BMCR_BMPRSC_3) /!< fBRST = fHRTIM/256U /
AnnaBridge	172:65be27845400	1662	#define HRTIM_BURSTMODEPRESCALER_DIV512 (HRTIM_BMCR_BMPRSC_3 \| HRTIM_BMCR_BMPRSC_0) /!< fBRST = fHRTIM/512U /
AnnaBridge	172:65be27845400	1663	#define HRTIM_BURSTMODEPRESCALER_DIV1024 (HRTIM_BMCR_BMPRSC_3 \| HRTIM_BMCR_BMPRSC_1) /!< fBRST = fHRTIM/1024U /
AnnaBridge	172:65be27845400	1664	#define HRTIM_BURSTMODEPRESCALER_DIV2048 (HRTIM_BMCR_BMPRSC_3 \| HRTIM_BMCR_BMPRSC_1 \| HRTIM_BMCR_BMPRSC_0) /!< fBRST = fHRTIM/2048U/
AnnaBridge	172:65be27845400	1665	#define HRTIM_BURSTMODEPRESCALER_DIV4096 (HRTIM_BMCR_BMPRSC_3 \| HRTIM_BMCR_BMPRSC_2) /!< fBRST = fHRTIM/4096U /
AnnaBridge	172:65be27845400	1666	#define HRTIM_BURSTMODEPRESCALER_DIV8192 (HRTIM_BMCR_BMPRSC_3 \| HRTIM_BMCR_BMPRSC_2 \| HRTIM_BMCR_BMPRSC_0) /!< fBRST = fHRTIM/8192U /
AnnaBridge	172:65be27845400	1667	#define HRTIM_BURSTMODEPRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 \| HRTIM_BMCR_BMPRSC_2 \| HRTIM_BMCR_BMPRSC_1) /!< fBRST = fHRTIM/16384U /
AnnaBridge	172:65be27845400	1668	#define HRTIM_BURSTMODEPRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 \| HRTIM_BMCR_BMPRSC_2 \| HRTIM_BMCR_BMPRSC_1 \| HRTIM_BMCR_BMPRSC_0) /!< fBRST = fHRTIM/32768U /
AnnaBridge	172:65be27845400	1669	/**
AnnaBridge	172:65be27845400	1670	* @}
AnnaBridge	172:65be27845400	1671	*/
AnnaBridge	172:65be27845400	1672
AnnaBridge	172:65be27845400	1673	/** @defgroup HRTIM_Burst_Mode_Register_Preload_Enable HRTIM Burst Mode Register Preload Enable
AnnaBridge	172:65be27845400	1674	* @{
AnnaBridge	172:65be27845400	1675	* @brief Constants defining whether or not burst mode registers preload
AnnaBridge	172:65be27845400	1676	mechanism is enabled, i.e. a write access into a preloadable register
AnnaBridge	172:65be27845400	1677	(HRTIM_BMCMPR, HRTIM_BMPER) is done into the active or the preload register
AnnaBridge	172:65be27845400	1678	*/
AnnaBridge	172:65be27845400	1679	#define HRIM_BURSTMODEPRELOAD_DISABLED (0x00000000U) /!< Preload disabled: the write access is directly done into active registers /
AnnaBridge	172:65be27845400	1680	#define HRIM_BURSTMODEPRELOAD_ENABLED (HRTIM_BMCR_BMPREN) /!< Preload enabled: the write access is done into preload registers /
AnnaBridge	172:65be27845400	1681	/**
AnnaBridge	172:65be27845400	1682	* @}
AnnaBridge	172:65be27845400	1683	*/
AnnaBridge	172:65be27845400	1684
AnnaBridge	172:65be27845400	1685	/** @defgroup HRTIM_Burst_Mode_Trigger HRTIM Burst Mode Trigger
AnnaBridge	172:65be27845400	1686	* @{
AnnaBridge	172:65be27845400	1687	* @brief Constants defining the events that can be used tor trig the burst
AnnaBridge	172:65be27845400	1688	* mode operation
AnnaBridge	172:65be27845400	1689	*/
AnnaBridge	172:65be27845400	1690	#define HRTIM_BURSTMODETRIGGER_NONE 0x00000000U /!< No trigger /
AnnaBridge	172:65be27845400	1691	#define HRTIM_BURSTMODETRIGGER_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /!< Master reset /
AnnaBridge	172:65be27845400	1692	#define HRTIM_BURSTMODETRIGGER_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /!< Master repetition /
AnnaBridge	172:65be27845400	1693	#define HRTIM_BURSTMODETRIGGER_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /!< Master compare 1U /
AnnaBridge	172:65be27845400	1694	#define HRTIM_BURSTMODETRIGGER_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /!< Master compare 2U /
AnnaBridge	172:65be27845400	1695	#define HRTIM_BURSTMODETRIGGER_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /!< Master compare 3U /
AnnaBridge	172:65be27845400	1696	#define HRTIM_BURSTMODETRIGGER_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /!< Master compare 4U /
AnnaBridge	172:65be27845400	1697	#define HRTIM_BURSTMODETRIGGER_TIMERA_RESET (HRTIM_BMTRGR_TARST) /!< Timer A reset /
AnnaBridge	172:65be27845400	1698	#define HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION (HRTIM_BMTRGR_TAREP) /!< Timer A repetition /
AnnaBridge	172:65be27845400	1699	#define HRTIM_BURSTMODETRIGGER_TIMERA_CMP1 (HRTIM_BMTRGR_TACMP1) /!< Timer A compare 1 /
AnnaBridge	172:65be27845400	1700	#define HRTIM_BURSTMODETRIGGER_TIMERA_CMP2 (HRTIM_BMTRGR_TACMP2) /!< Timer A compare 2 /
AnnaBridge	172:65be27845400	1701	#define HRTIM_BURSTMODETRIGGER_TIMERB_RESET (HRTIM_BMTRGR_TBRST) /!< Timer B reset /
AnnaBridge	172:65be27845400	1702	#define HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION (HRTIM_BMTRGR_TBREP) /!< Timer B repetition /
AnnaBridge	172:65be27845400	1703	#define HRTIM_BURSTMODETRIGGER_TIMERB_CMP1 (HRTIM_BMTRGR_TBCMP1) /!< Timer B compare 1 /
AnnaBridge	172:65be27845400	1704	#define HRTIM_BURSTMODETRIGGER_TIMERB_CMP2 (HRTIM_BMTRGR_TBCMP2) /!< Timer B compare 2 /
AnnaBridge	172:65be27845400	1705	#define HRTIM_BURSTMODETRIGGER_TIMERC_RESET (HRTIM_BMTRGR_TCRST) /!< Timer C reset /
AnnaBridge	172:65be27845400	1706	#define HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION (HRTIM_BMTRGR_TCREP) /!< Timer C repetition /
AnnaBridge	172:65be27845400	1707	#define HRTIM_BURSTMODETRIGGER_TIMERC_CMP1 (HRTIM_BMTRGR_TCCMP1) /!< Timer C compare 1 /
AnnaBridge	172:65be27845400	1708	#define HRTIM_BURSTMODETRIGGER_TIMERC_CMP2 (HRTIM_BMTRGR_TCCMP2) /!< Timer C compare 2 /
AnnaBridge	172:65be27845400	1709	#define HRTIM_BURSTMODETRIGGER_TIMERD_RESET (HRTIM_BMTRGR_TDRST) /!< Timer D reset /
AnnaBridge	172:65be27845400	1710	#define HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION (HRTIM_BMTRGR_TDREP) /!< Timer D repetition /
AnnaBridge	172:65be27845400	1711	#define HRTIM_BURSTMODETRIGGER_TIMERD_CMP1 (HRTIM_BMTRGR_TDCMP1) /!< Timer D compare 1 /
AnnaBridge	172:65be27845400	1712	#define HRTIM_BURSTMODETRIGGER_TIMERD_CMP2 (HRTIM_BMTRGR_TDCMP2) /!< Timer D compare 2 /
AnnaBridge	172:65be27845400	1713	#define HRTIM_BURSTMODETRIGGER_TIMERE_RESET (HRTIM_BMTRGR_TERST) /!< Timer E reset /
AnnaBridge	172:65be27845400	1714	#define HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION (HRTIM_BMTRGR_TEREP) /!< Timer E repetition /
AnnaBridge	172:65be27845400	1715	#define HRTIM_BURSTMODETRIGGER_TIMERE_CMP1 (HRTIM_BMTRGR_TECMP1) /!< Timer E compare 1 /
AnnaBridge	172:65be27845400	1716	#define HRTIM_BURSTMODETRIGGER_TIMERE_CMP2 (HRTIM_BMTRGR_TECMP2) /!< Timer E compare 2 /
AnnaBridge	172:65be27845400	1717	#define HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7 (HRTIM_BMTRGR_TAEEV7) /!< Timer A period following External Event 7 /
AnnaBridge	172:65be27845400	1718	#define HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8 (HRTIM_BMTRGR_TDEEV8) /!< Timer D period following External Event 8 /
AnnaBridge	172:65be27845400	1719	#define HRTIM_BURSTMODETRIGGER_EVENT_7 (HRTIM_BMTRGR_EEV7) /!< External Event 7 (timer A filters applied) /
AnnaBridge	172:65be27845400	1720	#define HRTIM_BURSTMODETRIGGER_EVENT_8 (HRTIM_BMTRGR_EEV8) /!< External Event 8 (timer D filters applied)/
AnnaBridge	172:65be27845400	1721	#define HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV) /!< On-chip Event /
AnnaBridge	172:65be27845400	1722	/**
AnnaBridge	172:65be27845400	1723	* @}
AnnaBridge	172:65be27845400	1724	*/
AnnaBridge	172:65be27845400	1725
AnnaBridge	172:65be27845400	1726	/** @defgroup HRTIM_ADC_Trigger_Update_Source HRTIM ADC Trigger Update Source
AnnaBridge	172:65be27845400	1727	* @{
AnnaBridge	172:65be27845400	1728	* @brief constants defining the source triggering the update of the
AnnaBridge	172:65be27845400	1729	HRTIM_ADCxR register (transfer from preload to active register).
AnnaBridge	172:65be27845400	1730	*/
AnnaBridge	172:65be27845400	1731	#define HRTIM_ADCTRIGGERUPDATE_MASTER 0x00000000U /!< Master timer /
AnnaBridge	172:65be27845400	1732	#define HRTIM_ADCTRIGGERUPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0) /!< Timer A /
AnnaBridge	172:65be27845400	1733	#define HRTIM_ADCTRIGGERUPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1) /!< Timer B /
AnnaBridge	172:65be27845400	1734	#define HRTIM_ADCTRIGGERUPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 \| HRTIM_CR1_ADC1USRC_0) /!< Timer C /
AnnaBridge	172:65be27845400	1735	#define HRTIM_ADCTRIGGERUPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2) /!< Timer D /
AnnaBridge	172:65be27845400	1736	#define HRTIM_ADCTRIGGERUPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 \| HRTIM_CR1_ADC1USRC_0) /!< Timer E /
AnnaBridge	172:65be27845400	1737	/**
AnnaBridge	172:65be27845400	1738	* @}
AnnaBridge	172:65be27845400	1739	*/
AnnaBridge	172:65be27845400	1740
AnnaBridge	172:65be27845400	1741	/** @defgroup HRTIM_ADC_Trigger_Event HRTIM ADC Trigger Event
AnnaBridge	172:65be27845400	1742	* @{
AnnaBridge	172:65be27845400	1743	* @brief constants defining the events triggering ADC conversion.
AnnaBridge	172:65be27845400	1744	* HRTIM_ADCTRIGGEREVENT13_*: ADC Triggers 1 and 3
AnnaBridge	172:65be27845400	1745	* HRTIM_ADCTRIGGEREVENT24_*: ADC Triggers 2 and 4
AnnaBridge	172:65be27845400	1746	*/
AnnaBridge	172:65be27845400	1747	#define HRTIM_ADCTRIGGEREVENT13_NONE 0x00000000U /!< No ADC trigger event /
AnnaBridge	172:65be27845400	1748	#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1 (HRTIM_ADC1R_AD1MC1) /!< ADC Trigger on master compare 1U /
AnnaBridge	172:65be27845400	1749	#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2 (HRTIM_ADC1R_AD1MC2) /!< ADC Trigger on master compare 2U /
AnnaBridge	172:65be27845400	1750	#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3 (HRTIM_ADC1R_AD1MC3) /!< ADC Trigger on master compare 3U /
AnnaBridge	172:65be27845400	1751	#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4 (HRTIM_ADC1R_AD1MC4) /!< ADC Trigger on master compare 4U /
AnnaBridge	172:65be27845400	1752	#define HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD (HRTIM_ADC1R_AD1MPER) /!< ADC Trigger on master period /
AnnaBridge	172:65be27845400	1753	#define HRTIM_ADCTRIGGEREVENT13_EVENT_1 (HRTIM_ADC1R_AD1EEV1) /!< ADC Trigger on external event 1U /
AnnaBridge	172:65be27845400	1754	#define HRTIM_ADCTRIGGEREVENT13_EVENT_2 (HRTIM_ADC1R_AD1EEV2) /!< ADC Trigger on external event 2U /
AnnaBridge	172:65be27845400	1755	#define HRTIM_ADCTRIGGEREVENT13_EVENT_3 (HRTIM_ADC1R_AD1EEV3) /!< ADC Trigger on external event 3U /
AnnaBridge	172:65be27845400	1756	#define HRTIM_ADCTRIGGEREVENT13_EVENT_4 (HRTIM_ADC1R_AD1EEV4) /!< ADC Trigger on external event 4U /
AnnaBridge	172:65be27845400	1757	#define HRTIM_ADCTRIGGEREVENT13_EVENT_5 (HRTIM_ADC1R_AD1EEV5) /!< ADC Trigger on external event 5U /
AnnaBridge	172:65be27845400	1758	#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP2 (HRTIM_ADC1R_AD1TAC2) /!< ADC Trigger on Timer A compare 2U /
AnnaBridge	172:65be27845400	1759	#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3 (HRTIM_ADC1R_AD1TAC3) /!< ADC Trigger on Timer A compare 3U /
AnnaBridge	172:65be27845400	1760	#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4 (HRTIM_ADC1R_AD1TAC4) /!< ADC Trigger on Timer A compare 4U /
AnnaBridge	172:65be27845400	1761	#define HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD (HRTIM_ADC1R_AD1TAPER) /!< ADC Trigger on Timer A period /
AnnaBridge	172:65be27845400	1762	#define HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET (HRTIM_ADC1R_AD1TARST) /!< ADC Trigger on Timer A reset /
AnnaBridge	172:65be27845400	1763	#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP2 (HRTIM_ADC1R_AD1TBC2) /!< ADC Trigger on Timer B compare 2U /
AnnaBridge	172:65be27845400	1764	#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3 (HRTIM_ADC1R_AD1TBC3) /!< ADC Trigger on Timer B compare 3U /
AnnaBridge	172:65be27845400	1765	#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4 (HRTIM_ADC1R_AD1TBC4) /!< ADC Trigger on Timer B compare 4U /
AnnaBridge	172:65be27845400	1766	#define HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD (HRTIM_ADC1R_AD1TBPER) /!< ADC Trigger on Timer B period /
AnnaBridge	172:65be27845400	1767	#define HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET (HRTIM_ADC1R_AD1TBRST) /!< ADC Trigger on Timer B reset /
AnnaBridge	172:65be27845400	1768	#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP2 (HRTIM_ADC1R_AD1TCC2) /!< ADC Trigger on Timer C compare 2U /
AnnaBridge	172:65be27845400	1769	#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3 (HRTIM_ADC1R_AD1TCC3) /!< ADC Trigger on Timer C compare 3U /
AnnaBridge	172:65be27845400	1770	#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4 (HRTIM_ADC1R_AD1TCC4) /!< ADC Trigger on Timer C compare 4U /
AnnaBridge	172:65be27845400	1771	#define HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD (HRTIM_ADC1R_AD1TCPER) /!< ADC Trigger on Timer C period /
AnnaBridge	172:65be27845400	1772	#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP2 (HRTIM_ADC1R_AD1TDC2) /!< ADC Trigger on Timer D compare 2U /
AnnaBridge	172:65be27845400	1773	#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3 (HRTIM_ADC1R_AD1TDC3) /!< ADC Trigger on Timer D compare 3U /
AnnaBridge	172:65be27845400	1774	#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4 (HRTIM_ADC1R_AD1TDC4) /!< ADC Trigger on Timer D compare 4U /
AnnaBridge	172:65be27845400	1775	#define HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD (HRTIM_ADC1R_AD1TDPER) /!< ADC Trigger on Timer D period /
AnnaBridge	172:65be27845400	1776	#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP2 (HRTIM_ADC1R_AD1TEC2) /!< ADC Trigger on Timer E compare 2U /
AnnaBridge	172:65be27845400	1777	#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3 (HRTIM_ADC1R_AD1TEC3) /!< ADC Trigger on Timer E compare 3U /
AnnaBridge	172:65be27845400	1778	#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4 (HRTIM_ADC1R_AD1TEC4) /!< ADC Trigger on Timer E compare 4U /
AnnaBridge	172:65be27845400	1779	#define HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD (HRTIM_ADC1R_AD1TEPER) /!< ADC Trigger on Timer E period /
AnnaBridge	172:65be27845400	1780
AnnaBridge	172:65be27845400	1781	#define HRTIM_ADCTRIGGEREVENT24_NONE 0x00000000U /!< No ADC trigger event /
AnnaBridge	172:65be27845400	1782	#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1 (HRTIM_ADC2R_AD2MC1) /!< ADC Trigger on master compare 1U /
AnnaBridge	172:65be27845400	1783	#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2 (HRTIM_ADC2R_AD2MC2) /!< ADC Trigger on master compare 2U /
AnnaBridge	172:65be27845400	1784	#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3 (HRTIM_ADC2R_AD2MC3) /!< ADC Trigger on master compare 3U /
AnnaBridge	172:65be27845400	1785	#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4 (HRTIM_ADC2R_AD2MC4) /!< ADC Trigger on master compare 4U /
AnnaBridge	172:65be27845400	1786	#define HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD (HRTIM_ADC2R_AD2MPER) /!< ADC Trigger on master period /
AnnaBridge	172:65be27845400	1787	#define HRTIM_ADCTRIGGEREVENT24_EVENT_6 (HRTIM_ADC2R_AD2EEV6) /!< ADC Trigger on external event 6U /
AnnaBridge	172:65be27845400	1788	#define HRTIM_ADCTRIGGEREVENT24_EVENT_7 (HRTIM_ADC2R_AD2EEV7) /!< ADC Trigger on external event 7U /
AnnaBridge	172:65be27845400	1789	#define HRTIM_ADCTRIGGEREVENT24_EVENT_8 (HRTIM_ADC2R_AD2EEV8) /!< ADC Trigger on external event 8U /
AnnaBridge	172:65be27845400	1790	#define HRTIM_ADCTRIGGEREVENT24_EVENT_9 (HRTIM_ADC2R_AD2EEV9) /!< ADC Trigger on external event 9U /
AnnaBridge	172:65be27845400	1791	#define HRTIM_ADCTRIGGEREVENT24_EVENT_10 (HRTIM_ADC2R_AD2EEV10) /!< ADC Trigger on external event 10U /
AnnaBridge	172:65be27845400	1792	#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2 (HRTIM_ADC2R_AD2TAC2) /!< ADC Trigger on Timer A compare 2U /
AnnaBridge	172:65be27845400	1793	#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP3 (HRTIM_ADC2R_AD2TAC3) /!< ADC Trigger on Timer A compare 3U /
AnnaBridge	172:65be27845400	1794	#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4 (HRTIM_ADC2R_AD2TAC4) /!< ADC Trigger on Timer A compare 4U /
AnnaBridge	172:65be27845400	1795	#define HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD (HRTIM_ADC2R_AD2TAPER) /!< ADC Trigger on Timer A period /
AnnaBridge	172:65be27845400	1796	#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2 (HRTIM_ADC2R_AD2TBC2) /!< ADC Trigger on Timer B compare 2U /
AnnaBridge	172:65be27845400	1797	#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP3 (HRTIM_ADC2R_AD2TBC3) /!< ADC Trigger on Timer B compare 3U /
AnnaBridge	172:65be27845400	1798	#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4 (HRTIM_ADC2R_AD2TBC4) /!< ADC Trigger on Timer B compare 4U /
AnnaBridge	172:65be27845400	1799	#define HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD (HRTIM_ADC2R_AD2TBPER) /!< ADC Trigger on Timer B period /
AnnaBridge	172:65be27845400	1800	#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2 (HRTIM_ADC2R_AD2TCC2) /!< ADC Trigger on Timer C compare 2U /
AnnaBridge	172:65be27845400	1801	#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP3 (HRTIM_ADC2R_AD2TCC3) /!< ADC Trigger on Timer C compare 3U /
AnnaBridge	172:65be27845400	1802	#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4 (HRTIM_ADC2R_AD2TCC4) /!< ADC Trigger on Timer C compare 4U /
AnnaBridge	172:65be27845400	1803	#define HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD (HRTIM_ADC2R_AD2TCPER) /!< ADC Trigger on Timer C period /
AnnaBridge	172:65be27845400	1804	#define HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET (HRTIM_ADC2R_AD2TCRST) /!< ADC Trigger on Timer C reset /
AnnaBridge	172:65be27845400	1805	#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2 (HRTIM_ADC2R_AD2TDC2) /!< ADC Trigger on Timer D compare 2U /
AnnaBridge	172:65be27845400	1806	#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP3 (HRTIM_ADC2R_AD2TDC3) /!< ADC Trigger on Timer D compare 3U /
AnnaBridge	172:65be27845400	1807	#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4 (HRTIM_ADC2R_AD2TDC4) /!< ADC Trigger on Timer D compare 4U /
AnnaBridge	172:65be27845400	1808	#define HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD (HRTIM_ADC2R_AD2TDPER) /!< ADC Trigger on Timer D period /
AnnaBridge	172:65be27845400	1809	#define HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET (HRTIM_ADC2R_AD2TDRST) /!< ADC Trigger on Timer D reset /
AnnaBridge	172:65be27845400	1810	#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2 (HRTIM_ADC2R_AD2TEC2) /!< ADC Trigger on Timer E compare 2U /
AnnaBridge	172:65be27845400	1811	#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3 (HRTIM_ADC2R_AD2TEC3) /!< ADC Trigger on Timer E compare 3U /
AnnaBridge	172:65be27845400	1812	#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4 (HRTIM_ADC2R_AD2TEC4) /!< ADC Trigger on Timer E compare 4U /
AnnaBridge	172:65be27845400	1813	#define HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET (HRTIM_ADC2R_AD2TERST) /!< ADC Trigger on Timer E reset /
AnnaBridge	172:65be27845400	1814
AnnaBridge	172:65be27845400	1815	/**
AnnaBridge	172:65be27845400	1816	* @}
AnnaBridge	172:65be27845400	1817	*/
AnnaBridge	172:65be27845400	1818
AnnaBridge	172:65be27845400	1819	/** @defgroup HRTIM_Burst_DMA_Registers_Update HRTIM Burst DMA Registers Update
AnnaBridge	172:65be27845400	1820	* @{
AnnaBridge	172:65be27845400	1821	* @brief Constants defining the registers that can be written during a burst
AnnaBridge	172:65be27845400	1822	* DMA operation
AnnaBridge	172:65be27845400	1823	*/
AnnaBridge	172:65be27845400	1824	#define HRTIM_BURSTDMA_NONE 0x00000000U /!< No register is updated by Burst DMA accesses /
AnnaBridge	172:65be27845400	1825	#define HRTIM_BURSTDMA_CR (HRTIM_BDTUPR_TIMCR) /!< MCR or TIMxCR register is updated by Burst DMA accesses /
AnnaBridge	172:65be27845400	1826	#define HRTIM_BURSTDMA_ICR (HRTIM_BDTUPR_TIMICR) /!< MICR or TIMxICR register is updated by Burst DMA accesses /
AnnaBridge	172:65be27845400	1827	#define HRTIM_BURSTDMA_DIER (HRTIM_BDTUPR_TIMDIER) /!< MDIER or TIMxDIER register is updated by Burst DMA accesses /
AnnaBridge	172:65be27845400	1828	#define HRTIM_BURSTDMA_CNT (HRTIM_BDTUPR_TIMCNT) /!< MCNTR or CNTxCR register is updated by Burst DMA accesses /
AnnaBridge	172:65be27845400	1829	#define HRTIM_BURSTDMA_PER (HRTIM_BDTUPR_TIMPER) /!< MPER or PERxR register is updated by Burst DMA accesses /
AnnaBridge	172:65be27845400	1830	#define HRTIM_BURSTDMA_REP (HRTIM_BDTUPR_TIMREP) /!< MREPR or REPxR register is updated by Burst DMA accesses /
AnnaBridge	172:65be27845400	1831	#define HRTIM_BURSTDMA_CMP1 (HRTIM_BDTUPR_TIMCMP1) /!< MCMP1R or CMP1xR register is updated by Burst DMA accesses /
AnnaBridge	172:65be27845400	1832	#define HRTIM_BURSTDMA_CMP2 (HRTIM_BDTUPR_TIMCMP2) /!< MCMP2R or CMP2xR register is updated by Burst DMA accesses /
AnnaBridge	172:65be27845400	1833	#define HRTIM_BURSTDMA_CMP3 (HRTIM_BDTUPR_TIMCMP3) /!< MCMP3R or CMP3xR register is updated by Burst DMA accesses /
AnnaBridge	172:65be27845400	1834	#define HRTIM_BURSTDMA_CMP4 (HRTIM_BDTUPR_TIMCMP4) /!< MCMP4R or CMP4xR register is updated by Burst DMA accesses /
AnnaBridge	172:65be27845400	1835	#define HRTIM_BURSTDMA_DTR (HRTIM_BDTUPR_TIMDTR) /!< TDxR register is updated by Burst DMA accesses /
AnnaBridge	172:65be27845400	1836	#define HRTIM_BURSTDMA_SET1R (HRTIM_BDTUPR_TIMSET1R) /!< SET1R register is updated by Burst DMA accesses /
AnnaBridge	172:65be27845400	1837	#define HRTIM_BURSTDMA_RST1R (HRTIM_BDTUPR_TIMRST1R) /!< RST1R register is updated by Burst DMA accesses /
AnnaBridge	172:65be27845400	1838	#define HRTIM_BURSTDMA_SET2R (HRTIM_BDTUPR_TIMSET2R) /!< SET2R register is updated by Burst DMA accesses /
AnnaBridge	172:65be27845400	1839	#define HRTIM_BURSTDMA_RST2R (HRTIM_BDTUPR_TIMRST2R) /!< RST1R register is updated by Burst DMA accesses /
AnnaBridge	172:65be27845400	1840	#define HRTIM_BURSTDMA_EEFR1 (HRTIM_BDTUPR_TIMEEFR1) /!< EEFxR1 register is updated by Burst DMA accesses /
AnnaBridge	172:65be27845400	1841	#define HRTIM_BURSTDMA_EEFR2 (HRTIM_BDTUPR_TIMEEFR2) /!< EEFxR2 register is updated by Burst DMA accesses /
AnnaBridge	172:65be27845400	1842	#define HRTIM_BURSTDMA_RSTR (HRTIM_BDTUPR_TIMRSTR) /!< RSTxR register is updated by Burst DMA accesses /
AnnaBridge	172:65be27845400	1843	#define HRTIM_BURSTDMA_CHPR (HRTIM_BDTUPR_TIMCHPR) /!< CHPxR register is updated by Burst DMA accesses /
AnnaBridge	172:65be27845400	1844	#define HRTIM_BURSTDMA_OUTR (HRTIM_BDTUPR_TIMOUTR) /!< OUTxR register is updated by Burst DMA accesses /
AnnaBridge	172:65be27845400	1845	#define HRTIM_BURSTDMA_FLTR (HRTIM_BDTUPR_TIMFLTR) /!< FLTxR register is updated by Burst DMA accesses /
AnnaBridge	172:65be27845400	1846	/**
AnnaBridge	172:65be27845400	1847	* @}
AnnaBridge	172:65be27845400	1848	*/
AnnaBridge	172:65be27845400	1849
AnnaBridge	172:65be27845400	1850	/** @defgroup HRTIM_Burst_Mode_Control HRTIM Burst Mode Control
AnnaBridge	172:65be27845400	1851	* @{
AnnaBridge	172:65be27845400	1852	* @brief Constants used to enable or disable the burst mode controller
AnnaBridge	172:65be27845400	1853	*/
AnnaBridge	172:65be27845400	1854	#define HRTIM_BURSTMODECTL_DISABLED 0x00000000U /!< Burst mode disabled /
AnnaBridge	172:65be27845400	1855	#define HRTIM_BURSTMODECTL_ENABLED (HRTIM_BMCR_BME) /!< Burst mode enabled /
AnnaBridge	172:65be27845400	1856	/**
AnnaBridge	172:65be27845400	1857	* @}
AnnaBridge	172:65be27845400	1858	*/
AnnaBridge	172:65be27845400	1859
AnnaBridge	172:65be27845400	1860	/** @defgroup HRTIM_Fault_Mode_Control HRTIM Fault Mode Control
AnnaBridge	172:65be27845400	1861	* @{
AnnaBridge	172:65be27845400	1862	* @brief Constants used to enable or disable a fault channel
AnnaBridge	172:65be27845400	1863	*/
AnnaBridge	172:65be27845400	1864	#define HRTIM_FAULTMODECTL_DISABLED 0x00000000U /!< Fault channel is disabled /
AnnaBridge	172:65be27845400	1865	#define HRTIM_FAULTMODECTL_ENABLED 0x00000001U /!< Fault channel is enabled /
AnnaBridge	172:65be27845400	1866	/**
AnnaBridge	172:65be27845400	1867	* @}
AnnaBridge	172:65be27845400	1868	*/
AnnaBridge	172:65be27845400	1869
AnnaBridge	172:65be27845400	1870	/** @defgroup HRTIM_Software_Timer_Update HRTIM Software Timer Update
AnnaBridge	172:65be27845400	1871	* @{
AnnaBridge	172:65be27845400	1872	* @brief Constants used to force timer registers update
AnnaBridge	172:65be27845400	1873	*/
AnnaBridge	172:65be27845400	1874	#define HRTIM_TIMERUPDATE_MASTER (HRTIM_CR2_MSWU) /!< Force an immediate transfer from the preload to the active register in the master timer /
AnnaBridge	172:65be27845400	1875	#define HRTIM_TIMERUPDATE_A (HRTIM_CR2_TASWU) /!< Force an immediate transfer from the preload to the active register in the timer A /
AnnaBridge	172:65be27845400	1876	#define HRTIM_TIMERUPDATE_B (HRTIM_CR2_TBSWU) /!< Force an immediate transfer from the preload to the active register in the timer B /
AnnaBridge	172:65be27845400	1877	#define HRTIM_TIMERUPDATE_C (HRTIM_CR2_TCSWU) /!< Force an immediate transfer from the preload to the active register in the timer C /
AnnaBridge	172:65be27845400	1878	#define HRTIM_TIMERUPDATE_D (HRTIM_CR2_TDSWU) /!< Force an immediate transfer from the preload to the active register in the timer D /
AnnaBridge	172:65be27845400	1879	#define HRTIM_TIMERUPDATE_E (HRTIM_CR2_TESWU) /!< Force an immediate transfer from the preload to the active register in the timer E /
AnnaBridge	172:65be27845400	1880	/**
AnnaBridge	172:65be27845400	1881	* @}
AnnaBridge	172:65be27845400	1882	*/
AnnaBridge	172:65be27845400	1883
AnnaBridge	172:65be27845400	1884	/** @defgroup HRTIM_Software_Timer_Reset HRTIM Software Timer Reset
AnnaBridge	172:65be27845400	1885	* @{
AnnaBridge	172:65be27845400	1886	* @brief Constants used to force timer counter reset
AnnaBridge	172:65be27845400	1887	*/
AnnaBridge	172:65be27845400	1888	#define HRTIM_TIMERRESET_MASTER (HRTIM_CR2_MRST) /!< Reset the master timer counter /
AnnaBridge	172:65be27845400	1889	#define HRTIM_TIMERRESET_TIMER_A (HRTIM_CR2_TARST) /!< Reset the timer A counter /
AnnaBridge	172:65be27845400	1890	#define HRTIM_TIMERRESET_TIMER_B (HRTIM_CR2_TBRST) /!< Reset the timer B counter /
AnnaBridge	172:65be27845400	1891	#define HRTIM_TIMERRESET_TIMER_C (HRTIM_CR2_TCRST) /!< Reset the timer C counter /
AnnaBridge	172:65be27845400	1892	#define HRTIM_TIMERRESET_TIMER_D (HRTIM_CR2_TDRST) /!< Reset the timer D counter /
AnnaBridge	172:65be27845400	1893	#define HRTIM_TIMERRESET_TIMER_E (HRTIM_CR2_TERST) /!< Reset the timer E counter /
AnnaBridge	172:65be27845400	1894	/**
AnnaBridge	172:65be27845400	1895	* @}
AnnaBridge	172:65be27845400	1896	*/
AnnaBridge	172:65be27845400	1897
AnnaBridge	172:65be27845400	1898	/** @defgroup HRTIM_Output_Level HRTIM Output Level
AnnaBridge	172:65be27845400	1899	* @{
AnnaBridge	172:65be27845400	1900	* @brief Constants defining the level of a timer output
AnnaBridge	172:65be27845400	1901	*/
AnnaBridge	172:65be27845400	1902	#define HRTIM_OUTPUTLEVEL_ACTIVE (0x00000001U) /!< Force the output to its active state /
AnnaBridge	172:65be27845400	1903	#define HRTIM_OUTPUTLEVEL_INACTIVE (0x00000002U) /!< Force the output to its inactive state /
AnnaBridge	172:65be27845400	1904
AnnaBridge	172:65be27845400	1905	#define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\
AnnaBridge	172:65be27845400	1906	(((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) \|\| \
AnnaBridge	172:65be27845400	1907	((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE))
AnnaBridge	172:65be27845400	1908	/**
AnnaBridge	172:65be27845400	1909	* @}
AnnaBridge	172:65be27845400	1910	*/
AnnaBridge	172:65be27845400	1911
AnnaBridge	172:65be27845400	1912	/** @defgroup HRTIM_Output_State HRTIM Output State
AnnaBridge	172:65be27845400	1913	* @{
AnnaBridge	172:65be27845400	1914	* @brief Constants defining the state of a timer output
AnnaBridge	172:65be27845400	1915	*/
AnnaBridge	172:65be27845400	1916	#define HRTIM_OUTPUTSTATE_IDLE (0x00000001U) /*!< Main operating mode, where the output can take the active or
AnnaBridge	172:65be27845400	1917	inactive level as programmed in the crossbar unit */
AnnaBridge	172:65be27845400	1918	#define HRTIM_OUTPUTSTATE_RUN (0x00000002U) /*!< Default operating state (e.g. after an HRTIM reset, when the
AnnaBridge	172:65be27845400	1919	outputs are disabled by software or during a burst mode operation */
AnnaBridge	172:65be27845400	1920	#define HRTIM_OUTPUTSTATE_FAULT (0x00000003U) /*!< Safety state, entered in case of a shut-down request on
AnnaBridge	172:65be27845400	1921	FAULTx inputs */
AnnaBridge	172:65be27845400	1922	/**
AnnaBridge	172:65be27845400	1923	* @}
AnnaBridge	172:65be27845400	1924	*/
AnnaBridge	172:65be27845400	1925
AnnaBridge	172:65be27845400	1926	/** @defgroup HRTIM_Burst_Mode_Status HRTIM Burst Mode Status
AnnaBridge	172:65be27845400	1927	* @{
AnnaBridge	172:65be27845400	1928	* @brief Constants defining the operating state of the burst mode controller
AnnaBridge	172:65be27845400	1929	*/
AnnaBridge	172:65be27845400	1930	#define HRTIM_BURSTMODESTATUS_NORMAL 0x00000000U /!< Normal operation /
AnnaBridge	172:65be27845400	1931	#define HRTIM_BURSTMODESTATUS_ONGOING (HRTIM_BMCR_BMSTAT) /!< Burst operation on-going /
AnnaBridge	172:65be27845400	1932	/**
AnnaBridge	172:65be27845400	1933	* @}
AnnaBridge	172:65be27845400	1934	*/
AnnaBridge	172:65be27845400	1935
AnnaBridge	172:65be27845400	1936	/** @defgroup HRTIM_Current_Push_Pull_Status HRTIM Current Push Pull Status
AnnaBridge	172:65be27845400	1937	* @{
AnnaBridge	172:65be27845400	1938	* @brief Constants defining on which output the signal is currently applied
AnnaBridge	172:65be27845400	1939	* in push-pull mode
AnnaBridge	172:65be27845400	1940	*/
AnnaBridge	172:65be27845400	1941	#define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1 0x00000000U /!< Signal applied on output 1 and output 2 forced inactive /
AnnaBridge	172:65be27845400	1942	#define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /!< Signal applied on output 2 and output 1 forced inactive /
AnnaBridge	172:65be27845400	1943	/**
AnnaBridge	172:65be27845400	1944	* @}
AnnaBridge	172:65be27845400	1945	*/
AnnaBridge	172:65be27845400	1946
AnnaBridge	172:65be27845400	1947	/** @defgroup HRTIM_Idle_Push_Pull_Status HRTIM Idle Push Pull Status
AnnaBridge	172:65be27845400	1948	* @{
AnnaBridge	172:65be27845400	1949	* @brief Constants defining on which output the signal was applied, in
AnnaBridge	172:65be27845400	1950	* push-pull mode balanced fault mode or delayed idle mode, when the
AnnaBridge	172:65be27845400	1951	* protection was triggered
AnnaBridge	172:65be27845400	1952	*/
AnnaBridge	172:65be27845400	1953	#define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1 0x00000000U /!< Protection occurred when the output 1 was active and output 2 forced inactive /
AnnaBridge	172:65be27845400	1954	#define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /!< Protection occurred when the output 2 was active and output 1 forced inactive /
AnnaBridge	172:65be27845400	1955	/**
AnnaBridge	172:65be27845400	1956	* @}
AnnaBridge	172:65be27845400	1957	*/
AnnaBridge	172:65be27845400	1958
AnnaBridge	172:65be27845400	1959	/** @defgroup HRTIM_Common_Interrupt_Enable HRTIM Common Interrupt Enable
AnnaBridge	172:65be27845400	1960	* @{
AnnaBridge	172:65be27845400	1961	*/
AnnaBridge	172:65be27845400	1962	#define HRTIM_IT_NONE 0x00000000U /!< No interrupt enabled /
AnnaBridge	172:65be27845400	1963	#define HRTIM_IT_FLT1 HRTIM_IER_FLT1 /!< Fault 1 interrupt enable /
AnnaBridge	172:65be27845400	1964	#define HRTIM_IT_FLT2 HRTIM_IER_FLT2 /!< Fault 2 interrupt enable /
AnnaBridge	172:65be27845400	1965	#define HRTIM_IT_FLT3 HRTIM_IER_FLT3 /!< Fault 3 interrupt enable /
AnnaBridge	172:65be27845400	1966	#define HRTIM_IT_FLT4 HRTIM_IER_FLT4 /!< Fault 4 interrupt enable /
AnnaBridge	172:65be27845400	1967	#define HRTIM_IT_FLT5 HRTIM_IER_FLT5 /!< Fault 5 interrupt enable /
AnnaBridge	172:65be27845400	1968	#define HRTIM_IT_SYSFLT HRTIM_IER_SYSFLT /!< System Fault interrupt enable /
AnnaBridge	172:65be27845400	1969	#define HRTIM_IT_BMPER HRTIM_IER_BMPER /!< Burst mode period interrupt enable /
AnnaBridge	172:65be27845400	1970	/**
AnnaBridge	172:65be27845400	1971	* @}
AnnaBridge	172:65be27845400	1972	*/
AnnaBridge	172:65be27845400	1973
AnnaBridge	172:65be27845400	1974	/** @defgroup HRTIM_Master_Interrupt_Enable HRTIM Master Interrupt Enable
AnnaBridge	172:65be27845400	1975	* @{
AnnaBridge	172:65be27845400	1976	*/
AnnaBridge	172:65be27845400	1977	#define HRTIM_MASTER_IT_NONE 0x00000000U /!< No interrupt enabled /
AnnaBridge	172:65be27845400	1978	#define HRTIM_MASTER_IT_MCMP1 HRTIM_MDIER_MCMP1IE /!< Master compare 1 interrupt enable /
AnnaBridge	172:65be27845400	1979	#define HRTIM_MASTER_IT_MCMP2 HRTIM_MDIER_MCMP2IE /!< Master compare 2 interrupt enable /
AnnaBridge	172:65be27845400	1980	#define HRTIM_MASTER_IT_MCMP3 HRTIM_MDIER_MCMP3IE /!< Master compare 3 interrupt enable /
AnnaBridge	172:65be27845400	1981	#define HRTIM_MASTER_IT_MCMP4 HRTIM_MDIER_MCMP4IE /!< Master compare 4 interrupt enable /
AnnaBridge	172:65be27845400	1982	#define HRTIM_MASTER_IT_MREP HRTIM_MDIER_MREPIE /!< Master Repetition interrupt enable /
AnnaBridge	172:65be27845400	1983	#define HRTIM_MASTER_IT_SYNC HRTIM_MDIER_SYNCIE /!< Synchronization input interrupt enable /
AnnaBridge	172:65be27845400	1984	#define HRTIM_MASTER_IT_MUPD HRTIM_MDIER_MUPDIE /!< Master update interrupt enable /
AnnaBridge	172:65be27845400	1985	/**
AnnaBridge	172:65be27845400	1986	* @}
AnnaBridge	172:65be27845400	1987	*/
AnnaBridge	172:65be27845400	1988
AnnaBridge	172:65be27845400	1989	/** @defgroup HRTIM_Timing_Unit_Interrupt_Enable HRTIM Timing Unit Interrupt Enable
AnnaBridge	172:65be27845400	1990	* @{
AnnaBridge	172:65be27845400	1991	*/
AnnaBridge	172:65be27845400	1992	#define HRTIM_TIM_IT_NONE 0x00000000U /!< No interrupt enabled /
AnnaBridge	172:65be27845400	1993	#define HRTIM_TIM_IT_CMP1 HRTIM_TIMDIER_CMP1IE /!< Timer compare 1 interrupt enable /
AnnaBridge	172:65be27845400	1994	#define HRTIM_TIM_IT_CMP2 HRTIM_TIMDIER_CMP2IE /!< Timer compare 2 interrupt enable /
AnnaBridge	172:65be27845400	1995	#define HRTIM_TIM_IT_CMP3 HRTIM_TIMDIER_CMP3IE /!< Timer compare 3 interrupt enable /
AnnaBridge	172:65be27845400	1996	#define HRTIM_TIM_IT_CMP4 HRTIM_TIMDIER_CMP4IE /!< Timer compare 4 interrupt enable /
AnnaBridge	172:65be27845400	1997	#define HRTIM_TIM_IT_REP HRTIM_TIMDIER_REPIE /!< Timer repetition interrupt enable /
AnnaBridge	172:65be27845400	1998	#define HRTIM_TIM_IT_UPD HRTIM_TIMDIER_UPDIE /!< Timer update interrupt enable /
AnnaBridge	172:65be27845400	1999	#define HRTIM_TIM_IT_CPT1 HRTIM_TIMDIER_CPT1IE /!< Timer capture 1 interrupt enable /
AnnaBridge	172:65be27845400	2000	#define HRTIM_TIM_IT_CPT2 HRTIM_TIMDIER_CPT2IE /!< Timer capture 2 interrupt enable /
AnnaBridge	172:65be27845400	2001	#define HRTIM_TIM_IT_SET1 HRTIM_TIMDIER_SET1IE /!< Timer output 1 set interrupt enable /
AnnaBridge	172:65be27845400	2002	#define HRTIM_TIM_IT_RST1 HRTIM_TIMDIER_RST1IE /!< Timer output 1 reset interrupt enable /
AnnaBridge	172:65be27845400	2003	#define HRTIM_TIM_IT_SET2 HRTIM_TIMDIER_SET2IE /!< Timer output 2 set interrupt enable /
AnnaBridge	172:65be27845400	2004	#define HRTIM_TIM_IT_RST2 HRTIM_TIMDIER_RST2IE /!< Timer output 2 reset interrupt enable /
AnnaBridge	172:65be27845400	2005	#define HRTIM_TIM_IT_RST HRTIM_TIMDIER_RSTIE /!< Timer reset interrupt enable /
AnnaBridge	172:65be27845400	2006	#define HRTIM_TIM_IT_DLYPRT HRTIM_TIMDIER_DLYPRTIE /!< Timer delay protection interrupt enable /
AnnaBridge	172:65be27845400	2007	/**
AnnaBridge	172:65be27845400	2008	* @}
AnnaBridge	172:65be27845400	2009	*/
AnnaBridge	172:65be27845400	2010
AnnaBridge	172:65be27845400	2011	/** @defgroup HRTIM_Common_Interrupt_Flag HRTIM Common Interrupt Flag
AnnaBridge	172:65be27845400	2012	* @{
AnnaBridge	172:65be27845400	2013	*/
AnnaBridge	172:65be27845400	2014	#define HRTIM_FLAG_FLT1 HRTIM_ISR_FLT1 /!< Fault 1 interrupt flag /
AnnaBridge	172:65be27845400	2015	#define HRTIM_FLAG_FLT2 HRTIM_ISR_FLT2 /!< Fault 2 interrupt flag /
AnnaBridge	172:65be27845400	2016	#define HRTIM_FLAG_FLT3 HRTIM_ISR_FLT3 /!< Fault 3 interrupt flag /
AnnaBridge	172:65be27845400	2017	#define HRTIM_FLAG_FLT4 HRTIM_ISR_FLT4 /!< Fault 4 interrupt flag /
AnnaBridge	172:65be27845400	2018	#define HRTIM_FLAG_FLT5 HRTIM_ISR_FLT5 /!< Fault 5 interrupt flag /
AnnaBridge	172:65be27845400	2019	#define HRTIM_FLAG_SYSFLT HRTIM_ISR_SYSFLT /!< System Fault interrupt flag /
AnnaBridge	172:65be27845400	2020	#define HRTIM_FLAG_BMPER HRTIM_ISR_BMPER /!< Burst mode period interrupt flag /
AnnaBridge	172:65be27845400	2021	/**
AnnaBridge	172:65be27845400	2022	* @}
AnnaBridge	172:65be27845400	2023	*/
AnnaBridge	172:65be27845400	2024
AnnaBridge	172:65be27845400	2025	/** @defgroup HRTIM_Master_Interrupt_Flag HRTIM Master Interrupt Flag
AnnaBridge	172:65be27845400	2026	* @{
AnnaBridge	172:65be27845400	2027	*/
AnnaBridge	172:65be27845400	2028	#define HRTIM_MASTER_FLAG_MCMP1 HRTIM_MISR_MCMP1 /!< Master compare 1 interrupt flag /
AnnaBridge	172:65be27845400	2029	#define HRTIM_MASTER_FLAG_MCMP2 HRTIM_MISR_MCMP2 /!< Master compare 2 interrupt flag /
AnnaBridge	172:65be27845400	2030	#define HRTIM_MASTER_FLAG_MCMP3 HRTIM_MISR_MCMP3 /!< Master compare 3 interrupt flag /
AnnaBridge	172:65be27845400	2031	#define HRTIM_MASTER_FLAG_MCMP4 HRTIM_MISR_MCMP4 /!< Master compare 4 interrupt flag /
AnnaBridge	172:65be27845400	2032	#define HRTIM_MASTER_FLAG_MREP HRTIM_MISR_MREP /!< Master Repetition interrupt flag /
AnnaBridge	172:65be27845400	2033	#define HRTIM_MASTER_FLAG_SYNC HRTIM_MISR_SYNC /!< Synchronization input interrupt flag /
AnnaBridge	172:65be27845400	2034	#define HRTIM_MASTER_FLAG_MUPD HRTIM_MISR_MUPD /!< Master update interrupt flag /
AnnaBridge	172:65be27845400	2035	/**
AnnaBridge	172:65be27845400	2036	* @}
AnnaBridge	172:65be27845400	2037	*/
AnnaBridge	172:65be27845400	2038
AnnaBridge	172:65be27845400	2039	/** @defgroup HRTIM_Timing_Unit_Interrupt_Flag HRTIM Timing Unit Interrupt Flag
AnnaBridge	172:65be27845400	2040	* @{
AnnaBridge	172:65be27845400	2041	*/
AnnaBridge	172:65be27845400	2042	#define HRTIM_TIM_FLAG_CMP1 HRTIM_TIMISR_CMP1 /!< Timer compare 1 interrupt flag /
AnnaBridge	172:65be27845400	2043	#define HRTIM_TIM_FLAG_CMP2 HRTIM_TIMISR_CMP2 /!< Timer compare 2 interrupt flag /
AnnaBridge	172:65be27845400	2044	#define HRTIM_TIM_FLAG_CMP3 HRTIM_TIMISR_CMP3 /!< Timer compare 3 interrupt flag /
AnnaBridge	172:65be27845400	2045	#define HRTIM_TIM_FLAG_CMP4 HRTIM_TIMISR_CMP4 /!< Timer compare 4 interrupt flag /
AnnaBridge	172:65be27845400	2046	#define HRTIM_TIM_FLAG_REP HRTIM_TIMISR_REP /!< Timer repetition interrupt flag /
AnnaBridge	172:65be27845400	2047	#define HRTIM_TIM_FLAG_UPD HRTIM_TIMISR_UPD /!< Timer update interrupt flag /
AnnaBridge	172:65be27845400	2048	#define HRTIM_TIM_FLAG_CPT1 HRTIM_TIMISR_CPT1 /!< Timer capture 1 interrupt flag /
AnnaBridge	172:65be27845400	2049	#define HRTIM_TIM_FLAG_CPT2 HRTIM_TIMISR_CPT2 /!< Timer capture 2 interrupt flag /
AnnaBridge	172:65be27845400	2050	#define HRTIM_TIM_FLAG_SET1 HRTIM_TIMISR_SET1 /!< Timer output 1 set interrupt flag /
AnnaBridge	172:65be27845400	2051	#define HRTIM_TIM_FLAG_RST1 HRTIM_TIMISR_RST1 /!< Timer output 1 reset interrupt flag /
AnnaBridge	172:65be27845400	2052	#define HRTIM_TIM_FLAG_SET2 HRTIM_TIMISR_SET2 /!< Timer output 2 set interrupt flag /
AnnaBridge	172:65be27845400	2053	#define HRTIM_TIM_FLAG_RST2 HRTIM_TIMISR_RST2 /!< Timer output 2 reset interrupt flag /
AnnaBridge	172:65be27845400	2054	#define HRTIM_TIM_FLAG_RST HRTIM_TIMISR_RST /!< Timer reset interrupt flag /
AnnaBridge	172:65be27845400	2055	#define HRTIM_TIM_FLAG_DLYPRT HRTIM_TIMISR_DLYPRT /!< Timer delay protection interrupt flag /
AnnaBridge	172:65be27845400	2056	/**
AnnaBridge	172:65be27845400	2057	* @}
AnnaBridge	172:65be27845400	2058	*/
AnnaBridge	172:65be27845400	2059
AnnaBridge	172:65be27845400	2060	/** @defgroup HRTIM_Master_DMA_Request_Enable HRTIM Master DMA Request Enable
AnnaBridge	172:65be27845400	2061	* @{
AnnaBridge	172:65be27845400	2062	*/
AnnaBridge	172:65be27845400	2063	#define HRTIM_MASTER_DMA_NONE 0x00000000U /!< No DMA request enable /
AnnaBridge	172:65be27845400	2064	#define HRTIM_MASTER_DMA_MCMP1 HRTIM_MDIER_MCMP1DE /!< Master compare 1 DMA request enable /
AnnaBridge	172:65be27845400	2065	#define HRTIM_MASTER_DMA_MCMP2 HRTIM_MDIER_MCMP2DE /!< Master compare 2 DMA request enable /
AnnaBridge	172:65be27845400	2066	#define HRTIM_MASTER_DMA_MCMP3 HRTIM_MDIER_MCMP3DE /!< Master compare 3 DMA request enable /
AnnaBridge	172:65be27845400	2067	#define HRTIM_MASTER_DMA_MCMP4 HRTIM_MDIER_MCMP4DE /!< Master compare 4 DMA request enable /
AnnaBridge	172:65be27845400	2068	#define HRTIM_MASTER_DMA_MREP HRTIM_MDIER_MREPDE /!< Master Repetition DMA request enable /
AnnaBridge	172:65be27845400	2069	#define HRTIM_MASTER_DMA_SYNC HRTIM_MDIER_SYNCDE /!< Synchronization input DMA request enable /
AnnaBridge	172:65be27845400	2070	#define HRTIM_MASTER_DMA_MUPD HRTIM_MDIER_MUPDDE /!< Master update DMA request enable /
AnnaBridge	172:65be27845400	2071	/**
AnnaBridge	172:65be27845400	2072	* @}
AnnaBridge	172:65be27845400	2073	*/
AnnaBridge	172:65be27845400	2074
AnnaBridge	172:65be27845400	2075	/** @defgroup HRTIM_Timing_Unit_DMA_Request_Enable HRTIM Timing Unit DMA Request Enable
AnnaBridge	172:65be27845400	2076	* @{
AnnaBridge	172:65be27845400	2077	*/
AnnaBridge	172:65be27845400	2078	#define HRTIM_TIM_DMA_NONE 0x00000000U /!< No DMA request enable /
AnnaBridge	172:65be27845400	2079	#define HRTIM_TIM_DMA_CMP1 HRTIM_TIMDIER_CMP1DE /!< Timer compare 1 DMA request enable /
AnnaBridge	172:65be27845400	2080	#define HRTIM_TIM_DMA_CMP2 HRTIM_TIMDIER_CMP2DE /!< Timer compare 2 DMA request enable /
AnnaBridge	172:65be27845400	2081	#define HRTIM_TIM_DMA_CMP3 HRTIM_TIMDIER_CMP3DE /!< Timer compare 3 DMA request enable /
AnnaBridge	172:65be27845400	2082	#define HRTIM_TIM_DMA_CMP4 HRTIM_TIMDIER_CMP4DE /!< Timer compare 4 DMA request enable /
AnnaBridge	172:65be27845400	2083	#define HRTIM_TIM_DMA_REP HRTIM_TIMDIER_REPDE /!< Timer repetition DMA request enable /
AnnaBridge	172:65be27845400	2084	#define HRTIM_TIM_DMA_UPD HRTIM_TIMDIER_UPDDE /!< Timer update DMA request enable /
AnnaBridge	172:65be27845400	2085	#define HRTIM_TIM_DMA_CPT1 HRTIM_TIMDIER_CPT1DE /!< Timer capture 1 DMA request enable /
AnnaBridge	172:65be27845400	2086	#define HRTIM_TIM_DMA_CPT2 HRTIM_TIMDIER_CPT2DE /!< Timer capture 2 DMA request enable /
AnnaBridge	172:65be27845400	2087	#define HRTIM_TIM_DMA_SET1 HRTIM_TIMDIER_SET1DE /!< Timer output 1 set DMA request enable /
AnnaBridge	172:65be27845400	2088	#define HRTIM_TIM_DMA_RST1 HRTIM_TIMDIER_RST1DE /!< Timer output 1 reset DMA request enable /
AnnaBridge	172:65be27845400	2089	#define HRTIM_TIM_DMA_SET2 HRTIM_TIMDIER_SET2DE /!< Timer output 2 set DMA request enable /
AnnaBridge	172:65be27845400	2090	#define HRTIM_TIM_DMA_RST2 HRTIM_TIMDIER_RST2DE /!< Timer output 2 reset DMA request enable /
AnnaBridge	172:65be27845400	2091	#define HRTIM_TIM_DMA_RST HRTIM_TIMDIER_RSTDE /!< Timer reset DMA request enable /
AnnaBridge	172:65be27845400	2092	#define HRTIM_TIM_DMA_DLYPRT HRTIM_TIMDIER_DLYPRTDE /!< Timer delay protection DMA request enable /
AnnaBridge	172:65be27845400	2093	/**
AnnaBridge	172:65be27845400	2094	* @}
AnnaBridge	172:65be27845400	2095	*/
AnnaBridge	172:65be27845400	2096
AnnaBridge	172:65be27845400	2097	/**
AnnaBridge	172:65be27845400	2098	* @}
AnnaBridge	172:65be27845400	2099	*/
AnnaBridge	172:65be27845400	2100
AnnaBridge	172:65be27845400	2101	/* Private macros --------------------------------------------------------*/
AnnaBridge	172:65be27845400	2102	/** @addtogroup HRTIM_Private_Macros HRTIM Private Macros
AnnaBridge	172:65be27845400	2103	* @{
AnnaBridge	172:65be27845400	2104	*/
AnnaBridge	172:65be27845400	2105	#define IS_HRTIM_TIMERINDEX(TIMERINDEX)\
AnnaBridge	172:65be27845400	2106	(((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER) \|\| \
AnnaBridge	172:65be27845400	2107	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) \|\| \
AnnaBridge	172:65be27845400	2108	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) \|\| \
AnnaBridge	172:65be27845400	2109	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) \|\| \
AnnaBridge	172:65be27845400	2110	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) \|\| \
AnnaBridge	172:65be27845400	2111	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
AnnaBridge	172:65be27845400	2112
AnnaBridge	172:65be27845400	2113	#define IS_HRTIM_TIMING_UNIT(TIMERINDEX)\
AnnaBridge	172:65be27845400	2114	(((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) \|\| \
AnnaBridge	172:65be27845400	2115	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) \|\| \
AnnaBridge	172:65be27845400	2116	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) \|\| \
AnnaBridge	172:65be27845400	2117	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) \|\| \
AnnaBridge	172:65be27845400	2118	((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
AnnaBridge	172:65be27845400	2119
AnnaBridge	172:65be27845400	2120	#define IS_HRTIM_TIMERID(TIMERID) (((TIMERID) & 0xFFC0FFFFU) == 0x00000000U)
AnnaBridge	172:65be27845400	2121
AnnaBridge	172:65be27845400	2122	#define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\
AnnaBridge	172:65be27845400	2123	(((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) \|\| \
AnnaBridge	172:65be27845400	2124	((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) \|\| \
AnnaBridge	172:65be27845400	2125	((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) \|\| \
AnnaBridge	172:65be27845400	2126	((COMPAREUNIT) == HRTIM_COMPAREUNIT_4))
AnnaBridge	172:65be27845400	2127
AnnaBridge	172:65be27845400	2128	#define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\
AnnaBridge	172:65be27845400	2129	(((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) \|\| \
AnnaBridge	172:65be27845400	2130	((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2))
AnnaBridge	172:65be27845400	2131
AnnaBridge	172:65be27845400	2132	#define IS_HRTIM_OUTPUT(OUTPUT) (((OUTPUT) & 0xFFFFFC00U) == 0x00000000U)
AnnaBridge	172:65be27845400	2133
AnnaBridge	172:65be27845400	2134	#define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\
AnnaBridge	172:65be27845400	2135	((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \
AnnaBridge	172:65be27845400	2136	(((OUTPUT) == HRTIM_OUTPUT_TA1) \|\| \
AnnaBridge	172:65be27845400	2137	((OUTPUT) == HRTIM_OUTPUT_TA2))) \
AnnaBridge	172:65be27845400	2138	\|\| \
AnnaBridge	172:65be27845400	2139	(((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \
AnnaBridge	172:65be27845400	2140	(((OUTPUT) == HRTIM_OUTPUT_TB1) \|\| \
AnnaBridge	172:65be27845400	2141	((OUTPUT) == HRTIM_OUTPUT_TB2))) \
AnnaBridge	172:65be27845400	2142	\|\| \
AnnaBridge	172:65be27845400	2143	(((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \
AnnaBridge	172:65be27845400	2144	(((OUTPUT) == HRTIM_OUTPUT_TC1) \|\| \
AnnaBridge	172:65be27845400	2145	((OUTPUT) == HRTIM_OUTPUT_TC2))) \
AnnaBridge	172:65be27845400	2146	\|\| \
AnnaBridge	172:65be27845400	2147	(((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \
AnnaBridge	172:65be27845400	2148	(((OUTPUT) == HRTIM_OUTPUT_TD1) \|\| \
AnnaBridge	172:65be27845400	2149	((OUTPUT) == HRTIM_OUTPUT_TD2))) \
AnnaBridge	172:65be27845400	2150	\|\| \
AnnaBridge	172:65be27845400	2151	(((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \
AnnaBridge	172:65be27845400	2152	(((OUTPUT) == HRTIM_OUTPUT_TE1) \|\| \
AnnaBridge	172:65be27845400	2153	((OUTPUT) == HRTIM_OUTPUT_TE2))))
AnnaBridge	172:65be27845400	2154
AnnaBridge	172:65be27845400	2155	#define IS_HRTIM_EVENT(EVENT)\
AnnaBridge	172:65be27845400	2156	(((EVENT) == HRTIM_EVENT_NONE)\|\| \
AnnaBridge	172:65be27845400	2157	((EVENT) == HRTIM_EVENT_1) \|\| \
AnnaBridge	172:65be27845400	2158	((EVENT) == HRTIM_EVENT_2) \|\| \
AnnaBridge	172:65be27845400	2159	((EVENT) == HRTIM_EVENT_3) \|\| \
AnnaBridge	172:65be27845400	2160	((EVENT) == HRTIM_EVENT_4) \|\| \
AnnaBridge	172:65be27845400	2161	((EVENT) == HRTIM_EVENT_5) \|\| \
AnnaBridge	172:65be27845400	2162	((EVENT) == HRTIM_EVENT_6) \|\| \
AnnaBridge	172:65be27845400	2163	((EVENT) == HRTIM_EVENT_7) \|\| \
AnnaBridge	172:65be27845400	2164	((EVENT) == HRTIM_EVENT_8) \|\| \
AnnaBridge	172:65be27845400	2165	((EVENT) == HRTIM_EVENT_9) \|\| \
AnnaBridge	172:65be27845400	2166	((EVENT) == HRTIM_EVENT_10))
AnnaBridge	172:65be27845400	2167
AnnaBridge	172:65be27845400	2168	#define IS_HRTIM_FAULT(FAULT)\
AnnaBridge	172:65be27845400	2169	(((FAULT) == HRTIM_FAULT_1) \|\| \
AnnaBridge	172:65be27845400	2170	((FAULT) == HRTIM_FAULT_2) \|\| \
AnnaBridge	172:65be27845400	2171	((FAULT) == HRTIM_FAULT_3) \|\| \
AnnaBridge	172:65be27845400	2172	((FAULT) == HRTIM_FAULT_4) \|\| \
AnnaBridge	172:65be27845400	2173	((FAULT) == HRTIM_FAULT_5))
AnnaBridge	172:65be27845400	2174
AnnaBridge	172:65be27845400	2175	#define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\
AnnaBridge	172:65be27845400	2176	(((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL32) \|\| \
AnnaBridge	172:65be27845400	2177	((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL16) \|\| \
AnnaBridge	172:65be27845400	2178	((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL8) \|\| \
AnnaBridge	172:65be27845400	2179	((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL4) \|\| \
AnnaBridge	172:65be27845400	2180	((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL2) \|\| \
AnnaBridge	172:65be27845400	2181	((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) \|\| \
AnnaBridge	172:65be27845400	2182	((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) \|\| \
AnnaBridge	172:65be27845400	2183	((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4))
AnnaBridge	172:65be27845400	2184
AnnaBridge	172:65be27845400	2185	#define IS_HRTIM_MODE(MODE)\
AnnaBridge	172:65be27845400	2186	(((MODE) == HRTIM_MODE_CONTINUOUS) \|\| \
AnnaBridge	172:65be27845400	2187	((MODE) == HRTIM_MODE_SINGLESHOT) \|\| \
AnnaBridge	172:65be27845400	2188	((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
AnnaBridge	172:65be27845400	2189
AnnaBridge	172:65be27845400	2190	#define IS_HRTIM_MODE_ONEPULSE(MODE)\
AnnaBridge	172:65be27845400	2191	(((MODE) == HRTIM_MODE_SINGLESHOT) \|\| \
AnnaBridge	172:65be27845400	2192	((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
AnnaBridge	172:65be27845400	2193
AnnaBridge	172:65be27845400	2194
AnnaBridge	172:65be27845400	2195	#define IS_HRTIM_HALFMODE(HALFMODE)\
AnnaBridge	172:65be27845400	2196	(((HALFMODE) == HRTIM_HALFMODE_DISABLED) \|\| \
AnnaBridge	172:65be27845400	2197	((HALFMODE) == HRTIM_HALFMODE_ENABLED))
AnnaBridge	172:65be27845400	2198
AnnaBridge	172:65be27845400	2199	#define IS_HRTIM_SYNCSTART(SYNCSTART)\
AnnaBridge	172:65be27845400	2200	(((SYNCSTART) == HRTIM_SYNCSTART_DISABLED) \|\| \
AnnaBridge	172:65be27845400	2201	((SYNCSTART) == HRTIM_SYNCSTART_ENABLED))
AnnaBridge	172:65be27845400	2202
AnnaBridge	172:65be27845400	2203	#define IS_HRTIM_SYNCRESET(SYNCRESET)\
AnnaBridge	172:65be27845400	2204	(((SYNCRESET) == HRTIM_SYNCRESET_DISABLED) \|\| \
AnnaBridge	172:65be27845400	2205	((SYNCRESET) == HRTIM_SYNCRESET_ENABLED))
AnnaBridge	172:65be27845400	2206
AnnaBridge	172:65be27845400	2207	#define IS_HRTIM_DACSYNC(DACSYNC)\
AnnaBridge	172:65be27845400	2208	(((DACSYNC) == HRTIM_DACSYNC_NONE) \|\| \
AnnaBridge	172:65be27845400	2209	((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1) \|\| \
AnnaBridge	172:65be27845400	2210	((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2) \|\| \
AnnaBridge	172:65be27845400	2211	((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3))
AnnaBridge	172:65be27845400	2212
AnnaBridge	172:65be27845400	2213	#define IS_HRTIM_PRELOAD(PRELOAD)\
AnnaBridge	172:65be27845400	2214	(((PRELOAD) == HRTIM_PRELOAD_DISABLED) \|\| \
AnnaBridge	172:65be27845400	2215	((PRELOAD) == HRTIM_PRELOAD_ENABLED))
AnnaBridge	172:65be27845400	2216
AnnaBridge	172:65be27845400	2217	#define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)\
AnnaBridge	172:65be27845400	2218	(((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) \|\| \
AnnaBridge	172:65be27845400	2219	((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) \|\| \
AnnaBridge	172:65be27845400	2220	((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE))
AnnaBridge	172:65be27845400	2221
AnnaBridge	172:65be27845400	2222	#define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)\
AnnaBridge	172:65be27845400	2223	(((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) \|\| \
AnnaBridge	172:65be27845400	2224	((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) \|\| \
AnnaBridge	172:65be27845400	2225	((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE) \|\| \
AnnaBridge	172:65be27845400	2226	((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1) \|\| \
AnnaBridge	172:65be27845400	2227	((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2) \|\| \
AnnaBridge	172:65be27845400	2228	((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3) \|\| \
AnnaBridge	172:65be27845400	2229	((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE) \|\| \
AnnaBridge	172:65be27845400	2230	((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE) \|\| \
AnnaBridge	172:65be27845400	2231	((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE))
AnnaBridge	172:65be27845400	2232
AnnaBridge	172:65be27845400	2233	#define IS_HRTIM_TIMERBURSTMODE(MODE) \
AnnaBridge	172:65be27845400	2234	(((MODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) \|\| \
AnnaBridge	172:65be27845400	2235	((MODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER))
AnnaBridge	172:65be27845400	2236	#define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION) \
AnnaBridge	172:65be27845400	2237	(((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED) \|\| \
AnnaBridge	172:65be27845400	2238	((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED))
AnnaBridge	172:65be27845400	2239
AnnaBridge	172:65be27845400	2240	#define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\
AnnaBridge	172:65be27845400	2241	(((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) \|\| \
AnnaBridge	172:65be27845400	2242	((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED))
AnnaBridge	172:65be27845400	2243	#define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFE0U) == 0x00000000U)
AnnaBridge	172:65be27845400	2244
AnnaBridge	172:65be27845400	2245	#define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\
AnnaBridge	172:65be27845400	2246	(((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) \|\| \
AnnaBridge	172:65be27845400	2247	((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY))
AnnaBridge	172:65be27845400	2248
AnnaBridge	172:65be27845400	2249	#define IS_HRTIM_TIMDEADTIMEINSERTION(TIMPUSHPULLMODE, TIMDEADTIMEINSERTION)\
AnnaBridge	172:65be27845400	2250	((((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) && \
AnnaBridge	172:65be27845400	2251	((((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) \|\| \
AnnaBridge	172:65be27845400	2252	((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED)))) \
AnnaBridge	172:65be27845400	2253	\|\| \
AnnaBridge	172:65be27845400	2254	(((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \
AnnaBridge	172:65be27845400	2255	((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED)))
AnnaBridge	172:65be27845400	2256
AnnaBridge	172:65be27845400	2257	#define IS_HRTIM_TIMDELAYEDPROTECTION(TIMPUSHPULLMODE, TIMDELAYEDPROTECTION)\
AnnaBridge	172:65be27845400	2258	((((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED) \|\| \
AnnaBridge	172:65be27845400	2259	((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6) \|\| \
AnnaBridge	172:65be27845400	2260	((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6) \|\| \
AnnaBridge	172:65be27845400	2261	((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6) \|\| \
AnnaBridge	172:65be27845400	2262	((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7) \|\| \
AnnaBridge	172:65be27845400	2263	((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7) \|\| \
AnnaBridge	172:65be27845400	2264	((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7)) \
AnnaBridge	172:65be27845400	2265	\|\| \
AnnaBridge	172:65be27845400	2266	(((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \
AnnaBridge	172:65be27845400	2267	(((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) \|\| \
AnnaBridge	172:65be27845400	2268	((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))))
AnnaBridge	172:65be27845400	2269
AnnaBridge	172:65be27845400	2270	#define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFFU) == 0x00000000U)
AnnaBridge	172:65be27845400	2271
AnnaBridge	172:65be27845400	2272	#define IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x80000001U) == 0x00000000U)
AnnaBridge	172:65be27845400	2273
AnnaBridge	172:65be27845400	2274
AnnaBridge	172:65be27845400	2275	#define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET) \
AnnaBridge	172:65be27845400	2276	(((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) \|\| \
AnnaBridge	172:65be27845400	2277	((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED))
AnnaBridge	172:65be27845400	2278
AnnaBridge	172:65be27845400	2279	#define IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)\
AnnaBridge	172:65be27845400	2280	(((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) \|\| \
AnnaBridge	172:65be27845400	2281	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) \|\| \
AnnaBridge	172:65be27845400	2282	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) \|\| \
AnnaBridge	172:65be27845400	2283	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))
AnnaBridge	172:65be27845400	2284
AnnaBridge	172:65be27845400	2285	/* Auto delayed mode is only available for compare units 2 and 4U */
AnnaBridge	172:65be27845400	2286	#define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE) \
AnnaBridge	172:65be27845400	2287	((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) && \
AnnaBridge	172:65be27845400	2288	(((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) \|\| \
AnnaBridge	172:65be27845400	2289	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) \|\| \
AnnaBridge	172:65be27845400	2290	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) \|\| \
AnnaBridge	172:65be27845400	2291	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))) \
AnnaBridge	172:65be27845400	2292	\|\| \
AnnaBridge	172:65be27845400	2293	(((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) && \
AnnaBridge	172:65be27845400	2294	(((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) \|\| \
AnnaBridge	172:65be27845400	2295	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) \|\| \
AnnaBridge	172:65be27845400	2296	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) \|\| \
AnnaBridge	172:65be27845400	2297	((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))))
AnnaBridge	172:65be27845400	2298
AnnaBridge	172:65be27845400	2299	#define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)\
AnnaBridge	172:65be27845400	2300	(((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) \|\| \
AnnaBridge	172:65be27845400	2301	((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW))
AnnaBridge	172:65be27845400	2302
AnnaBridge	172:65be27845400	2303	#define IS_HRTIM_OUTPUTPULSE(OUTPUTPULSE) ((OUTPUTPULSE) <= 0x0000FFFFU)
AnnaBridge	172:65be27845400	2304
AnnaBridge	172:65be27845400	2305	#define IS_HRTIM_OUTPUTSET(OUTPUTSET)\
AnnaBridge	172:65be27845400	2306	(((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) \|\| \
AnnaBridge	172:65be27845400	2307	((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) \|\| \
AnnaBridge	172:65be27845400	2308	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) \|\| \
AnnaBridge	172:65be27845400	2309	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) \|\| \
AnnaBridge	172:65be27845400	2310	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) \|\| \
AnnaBridge	172:65be27845400	2311	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) \|\| \
AnnaBridge	172:65be27845400	2312	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) \|\| \
AnnaBridge	172:65be27845400	2313	((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) \|\| \
AnnaBridge	172:65be27845400	2314	((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) \|\| \
AnnaBridge	172:65be27845400	2315	((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) \|\| \
AnnaBridge	172:65be27845400	2316	((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) \|\| \
AnnaBridge	172:65be27845400	2317	((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) \|\| \
AnnaBridge	172:65be27845400	2318	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1) \|\| \
AnnaBridge	172:65be27845400	2319	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2) \|\| \
AnnaBridge	172:65be27845400	2320	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3) \|\| \
AnnaBridge	172:65be27845400	2321	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_4) \|\| \
AnnaBridge	172:65be27845400	2322	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_5) \|\| \
AnnaBridge	172:65be27845400	2323	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_6) \|\| \
AnnaBridge	172:65be27845400	2324	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7) \|\| \
AnnaBridge	172:65be27845400	2325	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8) \|\| \
AnnaBridge	172:65be27845400	2326	((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9) \|\| \
AnnaBridge	172:65be27845400	2327	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) \|\| \
AnnaBridge	172:65be27845400	2328	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) \|\| \
AnnaBridge	172:65be27845400	2329	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) \|\| \
AnnaBridge	172:65be27845400	2330	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) \|\| \
AnnaBridge	172:65be27845400	2331	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) \|\| \
AnnaBridge	172:65be27845400	2332	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) \|\| \
AnnaBridge	172:65be27845400	2333	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) \|\| \
AnnaBridge	172:65be27845400	2334	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) \|\| \
AnnaBridge	172:65be27845400	2335	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) \|\| \
AnnaBridge	172:65be27845400	2336	((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) \|\| \
AnnaBridge	172:65be27845400	2337	((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE))
AnnaBridge	172:65be27845400	2338
AnnaBridge	172:65be27845400	2339	#define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\
AnnaBridge	172:65be27845400	2340	(((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) \|\| \
AnnaBridge	172:65be27845400	2341	((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) \|\| \
AnnaBridge	172:65be27845400	2342	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) \|\| \
AnnaBridge	172:65be27845400	2343	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) \|\| \
AnnaBridge	172:65be27845400	2344	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) \|\| \
AnnaBridge	172:65be27845400	2345	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) \|\| \
AnnaBridge	172:65be27845400	2346	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) \|\| \
AnnaBridge	172:65be27845400	2347	((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) \|\| \
AnnaBridge	172:65be27845400	2348	((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) \|\| \
AnnaBridge	172:65be27845400	2349	((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) \|\| \
AnnaBridge	172:65be27845400	2350	((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) \|\| \
AnnaBridge	172:65be27845400	2351	((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) \|\| \
AnnaBridge	172:65be27845400	2352	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1) \|\| \
AnnaBridge	172:65be27845400	2353	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2) \|\| \
AnnaBridge	172:65be27845400	2354	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3) \|\| \
AnnaBridge	172:65be27845400	2355	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_4) \|\| \
AnnaBridge	172:65be27845400	2356	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_5) \|\| \
AnnaBridge	172:65be27845400	2357	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_6) \|\| \
AnnaBridge	172:65be27845400	2358	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7) \|\| \
AnnaBridge	172:65be27845400	2359	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8) \|\| \
AnnaBridge	172:65be27845400	2360	((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9) \|\| \
AnnaBridge	172:65be27845400	2361	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) \|\| \
AnnaBridge	172:65be27845400	2362	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) \|\| \
AnnaBridge	172:65be27845400	2363	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) \|\| \
AnnaBridge	172:65be27845400	2364	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) \|\| \
AnnaBridge	172:65be27845400	2365	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) \|\| \
AnnaBridge	172:65be27845400	2366	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) \|\| \
AnnaBridge	172:65be27845400	2367	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) \|\| \
AnnaBridge	172:65be27845400	2368	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) \|\| \
AnnaBridge	172:65be27845400	2369	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) \|\| \
AnnaBridge	172:65be27845400	2370	((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) \|\| \
AnnaBridge	172:65be27845400	2371	((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE))
AnnaBridge	172:65be27845400	2372
AnnaBridge	172:65be27845400	2373	#define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\
AnnaBridge	172:65be27845400	2374	(((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) \|\| \
AnnaBridge	172:65be27845400	2375	((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE))
AnnaBridge	172:65be27845400	2376
AnnaBridge	172:65be27845400	2377	#define IS_HRTIM_OUTPUTIDLELEVEL(OUTPUTIDLELEVEL)\
AnnaBridge	172:65be27845400	2378	(((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) \|\| \
AnnaBridge	172:65be27845400	2379	((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE))
AnnaBridge	172:65be27845400	2380
AnnaBridge	172:65be27845400	2381	#define IS_HRTIM_OUTPUTFAULTLEVEL(OUTPUTFAULTLEVEL)\
AnnaBridge	172:65be27845400	2382	(((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE) \|\| \
AnnaBridge	172:65be27845400	2383	((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE) \|\| \
AnnaBridge	172:65be27845400	2384	((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) \|\| \
AnnaBridge	172:65be27845400	2385	((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ))
AnnaBridge	172:65be27845400	2386
AnnaBridge	172:65be27845400	2387	#define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)\
AnnaBridge	172:65be27845400	2388	(((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED) \|\| \
AnnaBridge	172:65be27845400	2389	((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED))
AnnaBridge	172:65be27845400	2390
AnnaBridge	172:65be27845400	2391	#define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)\
AnnaBridge	172:65be27845400	2392	(((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR) \|\| \
AnnaBridge	172:65be27845400	2393	((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED))
AnnaBridge	172:65be27845400	2394
AnnaBridge	172:65be27845400	2395
AnnaBridge	172:65be27845400	2396	#define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER) \
AnnaBridge	172:65be27845400	2397	(((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE) \|\| \
AnnaBridge	172:65be27845400	2398	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE) \|\| \
AnnaBridge	172:65be27845400	2399	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_1) \|\| \
AnnaBridge	172:65be27845400	2400	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_2) \|\| \
AnnaBridge	172:65be27845400	2401	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_3) \|\| \
AnnaBridge	172:65be27845400	2402	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_4) \|\| \
AnnaBridge	172:65be27845400	2403	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_5) \|\| \
AnnaBridge	172:65be27845400	2404	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_6) \|\| \
AnnaBridge	172:65be27845400	2405	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_7) \|\| \
AnnaBridge	172:65be27845400	2406	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_8) \|\| \
AnnaBridge	172:65be27845400	2407	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_9) \|\| \
AnnaBridge	172:65be27845400	2408	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_10) \
AnnaBridge	172:65be27845400	2409	\|\| \
AnnaBridge	172:65be27845400	2410	(((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \
AnnaBridge	172:65be27845400	2411	(((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) \|\| \
AnnaBridge	172:65be27845400	2412	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) \|\| \
AnnaBridge	172:65be27845400	2413	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) \|\| \
AnnaBridge	172:65be27845400	2414	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) \|\| \
AnnaBridge	172:65be27845400	2415	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) \|\| \
AnnaBridge	172:65be27845400	2416	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) \|\| \
AnnaBridge	172:65be27845400	2417	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) \|\| \
AnnaBridge	172:65be27845400	2418	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) \|\| \
AnnaBridge	172:65be27845400	2419	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) \|\| \
AnnaBridge	172:65be27845400	2420	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) \|\| \
AnnaBridge	172:65be27845400	2421	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) \|\| \
AnnaBridge	172:65be27845400	2422	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) \|\| \
AnnaBridge	172:65be27845400	2423	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) \|\| \
AnnaBridge	172:65be27845400	2424	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) \|\| \
AnnaBridge	172:65be27845400	2425	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) \|\| \
AnnaBridge	172:65be27845400	2426	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
AnnaBridge	172:65be27845400	2427	\|\| \
AnnaBridge	172:65be27845400	2428	(((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \
AnnaBridge	172:65be27845400	2429	(((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) \|\| \
AnnaBridge	172:65be27845400	2430	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) \|\| \
AnnaBridge	172:65be27845400	2431	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) \|\| \
AnnaBridge	172:65be27845400	2432	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) \|\| \
AnnaBridge	172:65be27845400	2433	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) \|\| \
AnnaBridge	172:65be27845400	2434	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) \|\| \
AnnaBridge	172:65be27845400	2435	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) \|\| \
AnnaBridge	172:65be27845400	2436	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) \|\| \
AnnaBridge	172:65be27845400	2437	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) \|\| \
AnnaBridge	172:65be27845400	2438	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) \|\| \
AnnaBridge	172:65be27845400	2439	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) \|\| \
AnnaBridge	172:65be27845400	2440	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) \|\| \
AnnaBridge	172:65be27845400	2441	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) \|\| \
AnnaBridge	172:65be27845400	2442	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) \|\| \
AnnaBridge	172:65be27845400	2443	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) \|\| \
AnnaBridge	172:65be27845400	2444	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
AnnaBridge	172:65be27845400	2445	\|\| \
AnnaBridge	172:65be27845400	2446	(((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \
AnnaBridge	172:65be27845400	2447	(((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) \|\| \
AnnaBridge	172:65be27845400	2448	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) \|\| \
AnnaBridge	172:65be27845400	2449	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) \|\| \
AnnaBridge	172:65be27845400	2450	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) \|\| \
AnnaBridge	172:65be27845400	2451	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) \|\| \
AnnaBridge	172:65be27845400	2452	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) \|\| \
AnnaBridge	172:65be27845400	2453	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) \|\| \
AnnaBridge	172:65be27845400	2454	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) \|\| \
AnnaBridge	172:65be27845400	2455	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) \|\| \
AnnaBridge	172:65be27845400	2456	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) \|\| \
AnnaBridge	172:65be27845400	2457	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) \|\| \
AnnaBridge	172:65be27845400	2458	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) \|\| \
AnnaBridge	172:65be27845400	2459	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) \|\| \
AnnaBridge	172:65be27845400	2460	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) \|\| \
AnnaBridge	172:65be27845400	2461	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) \|\| \
AnnaBridge	172:65be27845400	2462	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
AnnaBridge	172:65be27845400	2463	\|\| \
AnnaBridge	172:65be27845400	2464	(((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \
AnnaBridge	172:65be27845400	2465	(((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) \|\| \
AnnaBridge	172:65be27845400	2466	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) \|\| \
AnnaBridge	172:65be27845400	2467	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) \|\| \
AnnaBridge	172:65be27845400	2468	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) \|\| \
AnnaBridge	172:65be27845400	2469	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) \|\| \
AnnaBridge	172:65be27845400	2470	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) \|\| \
AnnaBridge	172:65be27845400	2471	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) \|\| \
AnnaBridge	172:65be27845400	2472	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) \|\| \
AnnaBridge	172:65be27845400	2473	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) \|\| \
AnnaBridge	172:65be27845400	2474	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) \|\| \
AnnaBridge	172:65be27845400	2475	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) \|\| \
AnnaBridge	172:65be27845400	2476	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) \|\| \
AnnaBridge	172:65be27845400	2477	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) \|\| \
AnnaBridge	172:65be27845400	2478	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) \|\| \
AnnaBridge	172:65be27845400	2479	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) \|\| \
AnnaBridge	172:65be27845400	2480	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
AnnaBridge	172:65be27845400	2481	\|\| \
AnnaBridge	172:65be27845400	2482	(((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \
AnnaBridge	172:65be27845400	2483	(((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) \|\| \
AnnaBridge	172:65be27845400	2484	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) \|\| \
AnnaBridge	172:65be27845400	2485	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) \|\| \
AnnaBridge	172:65be27845400	2486	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) \|\| \
AnnaBridge	172:65be27845400	2487	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) \|\| \
AnnaBridge	172:65be27845400	2488	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) \|\| \
AnnaBridge	172:65be27845400	2489	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) \|\| \
AnnaBridge	172:65be27845400	2490	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) \|\| \
AnnaBridge	172:65be27845400	2491	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) \|\| \
AnnaBridge	172:65be27845400	2492	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) \|\| \
AnnaBridge	172:65be27845400	2493	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) \|\| \
AnnaBridge	172:65be27845400	2494	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) \|\| \
AnnaBridge	172:65be27845400	2495	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) \|\| \
AnnaBridge	172:65be27845400	2496	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) \|\| \
AnnaBridge	172:65be27845400	2497	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) \|\| \
AnnaBridge	172:65be27845400	2498	((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2))))
AnnaBridge	172:65be27845400	2499
AnnaBridge	172:65be27845400	2500	#define IS_HRTIM_TIMEVENTFILTER(TIMEVENTFILTER)\
AnnaBridge	172:65be27845400	2501	(((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_NONE) \|\| \
AnnaBridge	172:65be27845400	2502	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP1) \|\| \
AnnaBridge	172:65be27845400	2503	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP2) \|\| \
AnnaBridge	172:65be27845400	2504	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP3) \|\| \
AnnaBridge	172:65be27845400	2505	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP4) \|\| \
AnnaBridge	172:65be27845400	2506	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR1) \|\| \
AnnaBridge	172:65be27845400	2507	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR2) \|\| \
AnnaBridge	172:65be27845400	2508	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR3) \|\| \
AnnaBridge	172:65be27845400	2509	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR4) \|\| \
AnnaBridge	172:65be27845400	2510	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR5) \|\| \
AnnaBridge	172:65be27845400	2511	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR6) \|\| \
AnnaBridge	172:65be27845400	2512	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR7) \|\| \
AnnaBridge	172:65be27845400	2513	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR8) \|\| \
AnnaBridge	172:65be27845400	2514	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2) \|\| \
AnnaBridge	172:65be27845400	2515	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3) \|\| \
AnnaBridge	172:65be27845400	2516	((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM))
AnnaBridge	172:65be27845400	2517
AnnaBridge	172:65be27845400	2518	#define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\
AnnaBridge	172:65be27845400	2519	(((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) \|\| \
AnnaBridge	172:65be27845400	2520	((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED))
AnnaBridge	172:65be27845400	2521
AnnaBridge	172:65be27845400	2522	#define IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(PRESCALERRATIO)\
AnnaBridge	172:65be27845400	2523	(((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8) \|\| \
AnnaBridge	172:65be27845400	2524	((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4) \|\| \
AnnaBridge	172:65be27845400	2525	((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2) \|\| \
AnnaBridge	172:65be27845400	2526	((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) \|\| \
AnnaBridge	172:65be27845400	2527	((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) \|\| \
AnnaBridge	172:65be27845400	2528	((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) \|\| \
AnnaBridge	172:65be27845400	2529	((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) \|\| \
AnnaBridge	172:65be27845400	2530	((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16))
AnnaBridge	172:65be27845400	2531
AnnaBridge	172:65be27845400	2532	#define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\
AnnaBridge	172:65be27845400	2533	(((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE) \|\| \
AnnaBridge	172:65be27845400	2534	((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE))
AnnaBridge	172:65be27845400	2535
AnnaBridge	172:65be27845400	2536	#define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\
AnnaBridge	172:65be27845400	2537	(((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE) \|\| \
AnnaBridge	172:65be27845400	2538	((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY))
AnnaBridge	172:65be27845400	2539
AnnaBridge	172:65be27845400	2540	#define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)\
AnnaBridge	172:65be27845400	2541	(((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE) \|\| \
AnnaBridge	172:65be27845400	2542	((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY))
AnnaBridge	172:65be27845400	2543
AnnaBridge	172:65be27845400	2544	#define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)\
AnnaBridge	172:65be27845400	2545	(((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE) \|\| \
AnnaBridge	172:65be27845400	2546	((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE))
AnnaBridge	172:65be27845400	2547
AnnaBridge	172:65be27845400	2548	#define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)\
AnnaBridge	172:65be27845400	2549	(((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE) \|\| \
AnnaBridge	172:65be27845400	2550	((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY))
AnnaBridge	172:65be27845400	2551
AnnaBridge	172:65be27845400	2552	#define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)\
AnnaBridge	172:65be27845400	2553	(((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE) \|\| \
AnnaBridge	172:65be27845400	2554	((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY))
AnnaBridge	172:65be27845400	2555
AnnaBridge	172:65be27845400	2556	#define IS_HRTIM_CHOPPER_PRESCALERRATIO(PRESCALERRATIO)\
AnnaBridge	172:65be27845400	2557	(((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16) \|\| \
AnnaBridge	172:65be27845400	2558	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32) \|\| \
AnnaBridge	172:65be27845400	2559	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48) \|\| \
AnnaBridge	172:65be27845400	2560	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64) \|\| \
AnnaBridge	172:65be27845400	2561	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80) \|\| \
AnnaBridge	172:65be27845400	2562	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96) \|\| \
AnnaBridge	172:65be27845400	2563	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112) \|\| \
AnnaBridge	172:65be27845400	2564	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128) \|\| \
AnnaBridge	172:65be27845400	2565	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144) \|\| \
AnnaBridge	172:65be27845400	2566	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160) \|\| \
AnnaBridge	172:65be27845400	2567	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176) \|\| \
AnnaBridge	172:65be27845400	2568	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192) \|\| \
AnnaBridge	172:65be27845400	2569	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208) \|\| \
AnnaBridge	172:65be27845400	2570	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224) \|\| \
AnnaBridge	172:65be27845400	2571	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240) \|\| \
AnnaBridge	172:65be27845400	2572	((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256))
AnnaBridge	172:65be27845400	2573
AnnaBridge	172:65be27845400	2574	#define IS_HRTIM_CHOPPER_DUTYCYCLE(DUTYCYCLE)\
AnnaBridge	172:65be27845400	2575	(((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0) \|\| \
AnnaBridge	172:65be27845400	2576	((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125) \|\| \
AnnaBridge	172:65be27845400	2577	((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250) \|\| \
AnnaBridge	172:65be27845400	2578	((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375) \|\| \
AnnaBridge	172:65be27845400	2579	((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500) \|\| \
AnnaBridge	172:65be27845400	2580	((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625) \|\| \
AnnaBridge	172:65be27845400	2581	((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750) \|\| \
AnnaBridge	172:65be27845400	2582	((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875))
AnnaBridge	172:65be27845400	2583
AnnaBridge	172:65be27845400	2584	#define IS_HRTIM_CHOPPER_PULSEWIDTH(PULSEWIDTH)\
AnnaBridge	172:65be27845400	2585	(((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16) \|\| \
AnnaBridge	172:65be27845400	2586	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32) \|\| \
AnnaBridge	172:65be27845400	2587	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48) \|\| \
AnnaBridge	172:65be27845400	2588	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64) \|\| \
AnnaBridge	172:65be27845400	2589	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80) \|\| \
AnnaBridge	172:65be27845400	2590	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96) \|\| \
AnnaBridge	172:65be27845400	2591	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112) \|\| \
AnnaBridge	172:65be27845400	2592	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128) \|\| \
AnnaBridge	172:65be27845400	2593	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144) \|\| \
AnnaBridge	172:65be27845400	2594	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160) \|\| \
AnnaBridge	172:65be27845400	2595	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176) \|\| \
AnnaBridge	172:65be27845400	2596	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192) \|\| \
AnnaBridge	172:65be27845400	2597	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208) \|\| \
AnnaBridge	172:65be27845400	2598	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224) \|\| \
AnnaBridge	172:65be27845400	2599	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240) \|\| \
AnnaBridge	172:65be27845400	2600	((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256))
AnnaBridge	172:65be27845400	2601
AnnaBridge	172:65be27845400	2602	#define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)\
AnnaBridge	172:65be27845400	2603	(((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE) \|\| \
AnnaBridge	172:65be27845400	2604	((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT) \|\| \
AnnaBridge	172:65be27845400	2605	((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT))
AnnaBridge	172:65be27845400	2606
AnnaBridge	172:65be27845400	2607	#define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)\
AnnaBridge	172:65be27845400	2608	(((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START) \|\| \
AnnaBridge	172:65be27845400	2609	((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1) \|\| \
AnnaBridge	172:65be27845400	2610	((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START) \|\| \
AnnaBridge	172:65be27845400	2611	((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1))
AnnaBridge	172:65be27845400	2612
AnnaBridge	172:65be27845400	2613	#define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)\
AnnaBridge	172:65be27845400	2614	(((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE) \|\| \
AnnaBridge	172:65be27845400	2615	((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) \|\| \
AnnaBridge	172:65be27845400	2616	((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE))
AnnaBridge	172:65be27845400	2617
AnnaBridge	172:65be27845400	2618	#define IS_HRTIM_EVENTSRC(EVENTSRC)\
AnnaBridge	172:65be27845400	2619	(((EVENTSRC) == HRTIM_EVENTSRC_1) \|\| \
AnnaBridge	172:65be27845400	2620	((EVENTSRC) == HRTIM_EVENTSRC_2) \|\| \
AnnaBridge	172:65be27845400	2621	((EVENTSRC) == HRTIM_EVENTSRC_3) \|\| \
AnnaBridge	172:65be27845400	2622	((EVENTSRC) == HRTIM_EVENTSRC_4))
AnnaBridge	172:65be27845400	2623
AnnaBridge	172:65be27845400	2624	#define IS_HRTIM_EVENTPOLARITY(EVENTSENSITIVITY, EVENTPOLARITY)\
AnnaBridge	172:65be27845400	2625	((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) && \
AnnaBridge	172:65be27845400	2626	(((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH) \|\| \
AnnaBridge	172:65be27845400	2627	((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW))) \
AnnaBridge	172:65be27845400	2628	\|\| \
AnnaBridge	172:65be27845400	2629	(((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) \|\| \
AnnaBridge	172:65be27845400	2630	((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)\|\| \
AnnaBridge	172:65be27845400	2631	((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)))
AnnaBridge	172:65be27845400	2632
AnnaBridge	172:65be27845400	2633	#define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)\
AnnaBridge	172:65be27845400	2634	(((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) \|\| \
AnnaBridge	172:65be27845400	2635	((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) \|\| \
AnnaBridge	172:65be27845400	2636	((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) \|\| \
AnnaBridge	172:65be27845400	2637	((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))
AnnaBridge	172:65be27845400	2638
AnnaBridge	172:65be27845400	2639	#define IS_HRTIM_EVENTFASTMODE(EVENT, FASTMODE)\
AnnaBridge	172:65be27845400	2640	(((((EVENT) == HRTIM_EVENT_1) \|\| \
AnnaBridge	172:65be27845400	2641	((EVENT) == HRTIM_EVENT_2) \|\| \
AnnaBridge	172:65be27845400	2642	((EVENT) == HRTIM_EVENT_3) \|\| \
AnnaBridge	172:65be27845400	2643	((EVENT) == HRTIM_EVENT_4) \|\| \
AnnaBridge	172:65be27845400	2644	((EVENT) == HRTIM_EVENT_5)) && \
AnnaBridge	172:65be27845400	2645	(((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) \|\| \
AnnaBridge	172:65be27845400	2646	((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \
AnnaBridge	172:65be27845400	2647	\|\| \
AnnaBridge	172:65be27845400	2648	(((EVENT) == HRTIM_EVENT_6) \|\| \
AnnaBridge	172:65be27845400	2649	((EVENT) == HRTIM_EVENT_7) \|\| \
AnnaBridge	172:65be27845400	2650	((EVENT) == HRTIM_EVENT_8) \|\| \
AnnaBridge	172:65be27845400	2651	((EVENT) == HRTIM_EVENT_9) \|\| \
AnnaBridge	172:65be27845400	2652	((EVENT) == HRTIM_EVENT_10)))
AnnaBridge	172:65be27845400	2653
AnnaBridge	172:65be27845400	2654
AnnaBridge	172:65be27845400	2655	#define IS_HRTIM_EVENTFILTER(EVENT, FILTER)\
AnnaBridge	172:65be27845400	2656	((((EVENT) == HRTIM_EVENT_1) \|\| \
AnnaBridge	172:65be27845400	2657	((EVENT) == HRTIM_EVENT_2) \|\| \
AnnaBridge	172:65be27845400	2658	((EVENT) == HRTIM_EVENT_3) \|\| \
AnnaBridge	172:65be27845400	2659	((EVENT) == HRTIM_EVENT_4) \|\| \
AnnaBridge	172:65be27845400	2660	((EVENT) == HRTIM_EVENT_5)) \
AnnaBridge	172:65be27845400	2661	\|\| \
AnnaBridge	172:65be27845400	2662	((((EVENT) == HRTIM_EVENT_6) \|\| \
AnnaBridge	172:65be27845400	2663	((EVENT) == HRTIM_EVENT_7) \|\| \
AnnaBridge	172:65be27845400	2664	((EVENT) == HRTIM_EVENT_8) \|\| \
AnnaBridge	172:65be27845400	2665	((EVENT) == HRTIM_EVENT_9) \|\| \
AnnaBridge	172:65be27845400	2666	((EVENT) == HRTIM_EVENT_10)) && \
AnnaBridge	172:65be27845400	2667	(((FILTER) == HRTIM_EVENTFILTER_NONE) \|\| \
AnnaBridge	172:65be27845400	2668	((FILTER) == HRTIM_EVENTFILTER_1) \|\| \
AnnaBridge	172:65be27845400	2669	((FILTER) == HRTIM_EVENTFILTER_2) \|\| \
AnnaBridge	172:65be27845400	2670	((FILTER) == HRTIM_EVENTFILTER_3) \|\| \
AnnaBridge	172:65be27845400	2671	((FILTER) == HRTIM_EVENTFILTER_4) \|\| \
AnnaBridge	172:65be27845400	2672	((FILTER) == HRTIM_EVENTFILTER_5) \|\| \
AnnaBridge	172:65be27845400	2673	((FILTER) == HRTIM_EVENTFILTER_6) \|\| \
AnnaBridge	172:65be27845400	2674	((FILTER) == HRTIM_EVENTFILTER_7) \|\| \
AnnaBridge	172:65be27845400	2675	((FILTER) == HRTIM_EVENTFILTER_8) \|\| \
AnnaBridge	172:65be27845400	2676	((FILTER) == HRTIM_EVENTFILTER_9) \|\| \
AnnaBridge	172:65be27845400	2677	((FILTER) == HRTIM_EVENTFILTER_10) \|\| \
AnnaBridge	172:65be27845400	2678	((FILTER) == HRTIM_EVENTFILTER_11) \|\| \
AnnaBridge	172:65be27845400	2679	((FILTER) == HRTIM_EVENTFILTER_12) \|\| \
AnnaBridge	172:65be27845400	2680	((FILTER) == HRTIM_EVENTFILTER_13) \|\| \
AnnaBridge	172:65be27845400	2681	((FILTER) == HRTIM_EVENTFILTER_14) \|\| \
AnnaBridge	172:65be27845400	2682	((FILTER) == HRTIM_EVENTFILTER_15))))
AnnaBridge	172:65be27845400	2683
AnnaBridge	172:65be27845400	2684	#define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\
AnnaBridge	172:65be27845400	2685	(((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1) \|\| \
AnnaBridge	172:65be27845400	2686	((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2) \|\| \
AnnaBridge	172:65be27845400	2687	((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4) \|\| \
AnnaBridge	172:65be27845400	2688	((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8))
AnnaBridge	172:65be27845400	2689
AnnaBridge	172:65be27845400	2690	#define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\
AnnaBridge	172:65be27845400	2691	(((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) \|\| \
AnnaBridge	172:65be27845400	2692	((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL))
AnnaBridge	172:65be27845400	2693
AnnaBridge	172:65be27845400	2694	#define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\
AnnaBridge	172:65be27845400	2695	(((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) \|\| \
AnnaBridge	172:65be27845400	2696	((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH))
AnnaBridge	172:65be27845400	2697
AnnaBridge	172:65be27845400	2698	#define IS_HRTIM_FAULTMODECTL(FAULTMODECTL)\
AnnaBridge	172:65be27845400	2699	(((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED) \|\| \
AnnaBridge	172:65be27845400	2700	((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED))
AnnaBridge	172:65be27845400	2701
AnnaBridge	172:65be27845400	2702	#define IS_HRTIM_FAULTFILTER(FAULTFILTER)\
AnnaBridge	172:65be27845400	2703	(((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) \|\| \
AnnaBridge	172:65be27845400	2704	((FAULTFILTER) == HRTIM_FAULTFILTER_1) \|\| \
AnnaBridge	172:65be27845400	2705	((FAULTFILTER) == HRTIM_FAULTFILTER_2) \|\| \
AnnaBridge	172:65be27845400	2706	((FAULTFILTER) == HRTIM_FAULTFILTER_3) \|\| \
AnnaBridge	172:65be27845400	2707	((FAULTFILTER) == HRTIM_FAULTFILTER_4) \|\| \
AnnaBridge	172:65be27845400	2708	((FAULTFILTER) == HRTIM_FAULTFILTER_5) \|\| \
AnnaBridge	172:65be27845400	2709	((FAULTFILTER) == HRTIM_FAULTFILTER_6) \|\| \
AnnaBridge	172:65be27845400	2710	((FAULTFILTER) == HRTIM_FAULTFILTER_7) \|\| \
AnnaBridge	172:65be27845400	2711	((FAULTFILTER) == HRTIM_FAULTFILTER_8) \|\| \
AnnaBridge	172:65be27845400	2712	((FAULTFILTER) == HRTIM_FAULTFILTER_9) \|\| \
AnnaBridge	172:65be27845400	2713	((FAULTFILTER) == HRTIM_FAULTFILTER_10) \|\| \
AnnaBridge	172:65be27845400	2714	((FAULTFILTER) == HRTIM_FAULTFILTER_11) \|\| \
AnnaBridge	172:65be27845400	2715	((FAULTFILTER) == HRTIM_FAULTFILTER_12) \|\| \
AnnaBridge	172:65be27845400	2716	((FAULTFILTER) == HRTIM_FAULTFILTER_13) \|\| \
AnnaBridge	172:65be27845400	2717	((FAULTFILTER) == HRTIM_FAULTFILTER_14) \|\| \
AnnaBridge	172:65be27845400	2718	((FAULTFILTER) == HRTIM_FAULTFILTER_15))
AnnaBridge	172:65be27845400	2719
AnnaBridge	172:65be27845400	2720	#define IS_HRTIM_FAULTLOCK(FAULTLOCK)\
AnnaBridge	172:65be27845400	2721	(((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) \|\| \
AnnaBridge	172:65be27845400	2722	((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY))
AnnaBridge	172:65be27845400	2723
AnnaBridge	172:65be27845400	2724	#define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)\
AnnaBridge	172:65be27845400	2725	(((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1) \|\| \
AnnaBridge	172:65be27845400	2726	((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2) \|\| \
AnnaBridge	172:65be27845400	2727	((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4) \|\| \
AnnaBridge	172:65be27845400	2728	((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8))
AnnaBridge	172:65be27845400	2729
AnnaBridge	172:65be27845400	2730	#define IS_HRTIM_BURSTMODE(BURSTMODE)\
AnnaBridge	172:65be27845400	2731	(((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT) \|\| \
AnnaBridge	172:65be27845400	2732	((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS))
AnnaBridge	172:65be27845400	2733
AnnaBridge	172:65be27845400	2734	#define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)\
AnnaBridge	172:65be27845400	2735	(((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER) \|\| \
AnnaBridge	172:65be27845400	2736	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A) \|\| \
AnnaBridge	172:65be27845400	2737	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B) \|\| \
AnnaBridge	172:65be27845400	2738	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C) \|\| \
AnnaBridge	172:65be27845400	2739	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D) \|\| \
AnnaBridge	172:65be27845400	2740	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E) \|\| \
AnnaBridge	172:65be27845400	2741	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC) \|\| \
AnnaBridge	172:65be27845400	2742	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC) \|\| \
AnnaBridge	172:65be27845400	2743	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO) \|\| \
AnnaBridge	172:65be27845400	2744	((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM))
AnnaBridge	172:65be27845400	2745
AnnaBridge	172:65be27845400	2746	#define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)\
AnnaBridge	172:65be27845400	2747	(((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1) \|\| \
AnnaBridge	172:65be27845400	2748	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2) \|\| \
AnnaBridge	172:65be27845400	2749	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4) \|\| \
AnnaBridge	172:65be27845400	2750	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8) \|\| \
AnnaBridge	172:65be27845400	2751	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16) \|\| \
AnnaBridge	172:65be27845400	2752	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32) \|\| \
AnnaBridge	172:65be27845400	2753	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64) \|\| \
AnnaBridge	172:65be27845400	2754	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128) \|\| \
AnnaBridge	172:65be27845400	2755	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256) \|\| \
AnnaBridge	172:65be27845400	2756	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512) \|\| \
AnnaBridge	172:65be27845400	2757	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024) \|\| \
AnnaBridge	172:65be27845400	2758	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048) \|\| \
AnnaBridge	172:65be27845400	2759	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096) \|\| \
AnnaBridge	172:65be27845400	2760	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192) \|\| \
AnnaBridge	172:65be27845400	2761	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) \|\| \
AnnaBridge	172:65be27845400	2762	((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768))
AnnaBridge	172:65be27845400	2763
AnnaBridge	172:65be27845400	2764	#define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)\
AnnaBridge	172:65be27845400	2765	(((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED) \|\| \
AnnaBridge	172:65be27845400	2766	((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED))
AnnaBridge	172:65be27845400	2767
AnnaBridge	172:65be27845400	2768	#define IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)\
AnnaBridge	172:65be27845400	2769	(((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE) \|\| \
AnnaBridge	172:65be27845400	2770	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET) \|\| \
AnnaBridge	172:65be27845400	2771	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION) \|\| \
AnnaBridge	172:65be27845400	2772	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP1) \|\| \
AnnaBridge	172:65be27845400	2773	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP2) \|\| \
AnnaBridge	172:65be27845400	2774	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP3) \|\| \
AnnaBridge	172:65be27845400	2775	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP4) \|\| \
AnnaBridge	172:65be27845400	2776	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_RESET) \|\| \
AnnaBridge	172:65be27845400	2777	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) \|\| \
AnnaBridge	172:65be27845400	2778	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP1) \|\| \
AnnaBridge	172:65be27845400	2779	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP2) \|\| \
AnnaBridge	172:65be27845400	2780	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_RESET) \|\| \
AnnaBridge	172:65be27845400	2781	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) \|\| \
AnnaBridge	172:65be27845400	2782	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP1) \|\| \
AnnaBridge	172:65be27845400	2783	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP2) \|\| \
AnnaBridge	172:65be27845400	2784	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_RESET) \|\| \
AnnaBridge	172:65be27845400	2785	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) \|\| \
AnnaBridge	172:65be27845400	2786	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP1) \|\| \
AnnaBridge	172:65be27845400	2787	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP2) \|\| \
AnnaBridge	172:65be27845400	2788	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_RESET) \|\| \
AnnaBridge	172:65be27845400	2789	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) \|\| \
AnnaBridge	172:65be27845400	2790	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP1) \|\| \
AnnaBridge	172:65be27845400	2791	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP2) \|\| \
AnnaBridge	172:65be27845400	2792	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_RESET) \|\| \
AnnaBridge	172:65be27845400	2793	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) \|\| \
AnnaBridge	172:65be27845400	2794	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP1) \|\| \
AnnaBridge	172:65be27845400	2795	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP2) \|\| \
AnnaBridge	172:65be27845400	2796	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7) \|\| \
AnnaBridge	172:65be27845400	2797	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8) \|\| \
AnnaBridge	172:65be27845400	2798	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_7) \|\| \
AnnaBridge	172:65be27845400	2799	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_8) \|\| \
AnnaBridge	172:65be27845400	2800	((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP))
AnnaBridge	172:65be27845400	2801
AnnaBridge	172:65be27845400	2802	#define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)\
AnnaBridge	172:65be27845400	2803	(((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER) \|\| \
AnnaBridge	172:65be27845400	2804	((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A) \|\| \
AnnaBridge	172:65be27845400	2805	((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B) \|\| \
AnnaBridge	172:65be27845400	2806	((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C) \|\| \
AnnaBridge	172:65be27845400	2807	((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D) \|\| \
AnnaBridge	172:65be27845400	2808	((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E))
AnnaBridge	172:65be27845400	2809
AnnaBridge	172:65be27845400	2810	#define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\
AnnaBridge	172:65be27845400	2811	(((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) \|\| \
AnnaBridge	172:65be27845400	2812	((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_7300) \|\| \
AnnaBridge	172:65be27845400	2813	((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_910) \|\| \
AnnaBridge	172:65be27845400	2814	((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_114) \|\| \
AnnaBridge	172:65be27845400	2815	((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14))
AnnaBridge	172:65be27845400	2816
AnnaBridge	172:65be27845400	2817	#define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \
AnnaBridge	172:65be27845400	2818	((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFFC000U) == 0x00000000U)) \
AnnaBridge	172:65be27845400	2819	\|\| \
AnnaBridge	172:65be27845400	2820	(((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
AnnaBridge	172:65be27845400	2821	\|\| \
AnnaBridge	172:65be27845400	2822	(((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
AnnaBridge	172:65be27845400	2823	\|\| \
AnnaBridge	172:65be27845400	2824	(((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
AnnaBridge	172:65be27845400	2825	\|\| \
AnnaBridge	172:65be27845400	2826	(((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
AnnaBridge	172:65be27845400	2827	\|\| \
AnnaBridge	172:65be27845400	2828	(((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)))
AnnaBridge	172:65be27845400	2829
AnnaBridge	172:65be27845400	2830	#define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\
AnnaBridge	172:65be27845400	2831	(((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) \|\| \
AnnaBridge	172:65be27845400	2832	((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED))
AnnaBridge	172:65be27845400	2833
AnnaBridge	172:65be27845400	2834	#define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFFC0U) == 0x00000000U)
AnnaBridge	172:65be27845400	2835
AnnaBridge	172:65be27845400	2836	#define IS_HRTIM_TIMERRESET(TIMERRESET) (((TIMERRESET) & 0xFFFFC0FFU) == 0x00000000U)
AnnaBridge	172:65be27845400	2837
AnnaBridge	172:65be27845400	2838	#define IS_HRTIM_IT(IT) (((IT) & 0xFFFCFFC0U) == 0x00000000U)
AnnaBridge	172:65be27845400	2839
AnnaBridge	172:65be27845400	2840
AnnaBridge	172:65be27845400	2841	#define IS_HRTIM_MASTER_IT(MASTER_IT) (((MASTER_IT) & 0xFFFFFF80U) == 0x00000000U)
AnnaBridge	172:65be27845400	2842
AnnaBridge	172:65be27845400	2843
AnnaBridge	172:65be27845400	2844	#define IS_HRTIM_TIM_IT(TIM_IT) (((TIM_IT) & 0xFFFF8020U) == 0x00000000U)
AnnaBridge	172:65be27845400	2845
AnnaBridge	172:65be27845400	2846
AnnaBridge	172:65be27845400	2847	#define IS_HRTIM_MASTER_DMA(MASTER_DMA) (((MASTER_DMA) & 0xFF80FFFFU) == 0x00000000U)
AnnaBridge	172:65be27845400	2848
AnnaBridge	172:65be27845400	2849	#define IS_HRTIM_TIM_DMA(TIM_DMA) (((TIM_DMA) & 0x8020FFFFU) == 0x00000000U)
AnnaBridge	172:65be27845400	2850	/**
AnnaBridge	172:65be27845400	2851	* @}
AnnaBridge	172:65be27845400	2852	*/
AnnaBridge	172:65be27845400	2853
AnnaBridge	172:65be27845400	2854	/* Exported macros -----------------------------------------------------------*/
AnnaBridge	172:65be27845400	2855	/** @defgroup HRTIM_Exported_Macros HRTIM Exported Macros
AnnaBridge	172:65be27845400	2856	* @{
AnnaBridge	172:65be27845400	2857	*/
AnnaBridge	172:65be27845400	2858
AnnaBridge	172:65be27845400	2859	/** @brief Reset HRTIM handle state
AnnaBridge	172:65be27845400	2860	* @param __HANDLE__ HRTIM handle.
AnnaBridge	172:65be27845400	2861	* @retval None
AnnaBridge	172:65be27845400	2862	*/
AnnaBridge	172:65be27845400	2863	#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
AnnaBridge	172:65be27845400	2864	#define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) do{ \
AnnaBridge	172:65be27845400	2865	(__HANDLE__)->State = HAL_HRTIM_STATE_RESET; \
AnnaBridge	172:65be27845400	2866	(__HANDLE__)->MspInitCallback = NULL; \
AnnaBridge	172:65be27845400	2867	(__HANDLE__)->MspDeInitCallback = NULL; \
AnnaBridge	172:65be27845400	2868	} while(0)
AnnaBridge	172:65be27845400	2869	#else
AnnaBridge	172:65be27845400	2870	#define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HRTIM_STATE_RESET)
AnnaBridge	172:65be27845400	2871	#endif
AnnaBridge	172:65be27845400	2872
AnnaBridge	172:65be27845400	2873	/** @brief Enables or disables the timer counter(s)
AnnaBridge	172:65be27845400	2874	* @param __HANDLE__ specifies the HRTIM Handle.
AnnaBridge	172:65be27845400	2875	* @param __TIMERS__ timers to enable/disable
AnnaBridge	172:65be27845400	2876	* This parameter can be any combinations of the following values:
AnnaBridge	172:65be27845400	2877	* @arg HRTIM_TIMERID_MASTER: Master timer identifier
AnnaBridge	172:65be27845400	2878	* @arg HRTIM_TIMERID_TIMER_A: Timer A identifier
AnnaBridge	172:65be27845400	2879	* @arg HRTIM_TIMERID_TIMER_B: Timer B identifier
AnnaBridge	172:65be27845400	2880	* @arg HRTIM_TIMERID_TIMER_C: Timer C identifier
AnnaBridge	172:65be27845400	2881	* @arg HRTIM_TIMERID_TIMER_D: Timer D identifier
AnnaBridge	172:65be27845400	2882	* @arg HRTIM_TIMERID_TIMER_E: Timer E identifier
AnnaBridge	172:65be27845400	2883	* @retval None
AnnaBridge	172:65be27845400	2884	*/
AnnaBridge	172:65be27845400	2885	#define __HAL_HRTIM_ENABLE(__HANDLE__, __TIMERS__) ((__HANDLE__)->Instance->sMasterRegs.MCR \|= (__TIMERS__))
AnnaBridge	172:65be27845400	2886
AnnaBridge	172:65be27845400	2887	/* The counter of a timing unit is disabled only if all the timer outputs */
AnnaBridge	172:65be27845400	2888	/* are disabled and no capture is configured */
AnnaBridge	172:65be27845400	2889	#define HRTIM_TAOEN_MASK (HRTIM_OENR_TA2OEN \| HRTIM_OENR_TA1OEN)
AnnaBridge	172:65be27845400	2890	#define HRTIM_TBOEN_MASK (HRTIM_OENR_TB2OEN \| HRTIM_OENR_TB1OEN)
AnnaBridge	172:65be27845400	2891	#define HRTIM_TCOEN_MASK (HRTIM_OENR_TC2OEN \| HRTIM_OENR_TC1OEN)
AnnaBridge	172:65be27845400	2892	#define HRTIM_TDOEN_MASK (HRTIM_OENR_TD2OEN \| HRTIM_OENR_TD1OEN)
AnnaBridge	172:65be27845400	2893	#define HRTIM_TEOEN_MASK (HRTIM_OENR_TE2OEN \| HRTIM_OENR_TE1OEN)
AnnaBridge	172:65be27845400	2894	#define __HAL_HRTIM_DISABLE(__HANDLE__, __TIMERS__)\
AnnaBridge	172:65be27845400	2895	do {\
AnnaBridge	172:65be27845400	2896	if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\
AnnaBridge	172:65be27845400	2897	{\
AnnaBridge	172:65be27845400	2898	((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\
AnnaBridge	172:65be27845400	2899	}\
AnnaBridge	172:65be27845400	2900	if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\
AnnaBridge	172:65be27845400	2901	{\
AnnaBridge	172:65be27845400	2902	if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == (uint32_t)RESET)\
AnnaBridge	172:65be27845400	2903	{\
AnnaBridge	172:65be27845400	2904	((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\
AnnaBridge	172:65be27845400	2905	}\
AnnaBridge	172:65be27845400	2906	}\
AnnaBridge	172:65be27845400	2907	if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\
AnnaBridge	172:65be27845400	2908	{\
AnnaBridge	172:65be27845400	2909	if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == (uint32_t)RESET)\
AnnaBridge	172:65be27845400	2910	{\
AnnaBridge	172:65be27845400	2911	((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\
AnnaBridge	172:65be27845400	2912	}\
AnnaBridge	172:65be27845400	2913	}\
AnnaBridge	172:65be27845400	2914	if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\
AnnaBridge	172:65be27845400	2915	{\
AnnaBridge	172:65be27845400	2916	if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == (uint32_t)RESET)\
AnnaBridge	172:65be27845400	2917	{\
AnnaBridge	172:65be27845400	2918	((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\
AnnaBridge	172:65be27845400	2919	}\
AnnaBridge	172:65be27845400	2920	}\
AnnaBridge	172:65be27845400	2921	if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\
AnnaBridge	172:65be27845400	2922	{\
AnnaBridge	172:65be27845400	2923	if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == (uint32_t)RESET)\
AnnaBridge	172:65be27845400	2924	{\
AnnaBridge	172:65be27845400	2925	((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\
AnnaBridge	172:65be27845400	2926	}\
AnnaBridge	172:65be27845400	2927	}\
AnnaBridge	172:65be27845400	2928	if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\
AnnaBridge	172:65be27845400	2929	{\
AnnaBridge	172:65be27845400	2930	if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == (uint32_t)RESET)\
AnnaBridge	172:65be27845400	2931	{\
AnnaBridge	172:65be27845400	2932	((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\
AnnaBridge	172:65be27845400	2933	}\
AnnaBridge	172:65be27845400	2934	}\
AnnaBridge	172:65be27845400	2935	} while(0U)
AnnaBridge	172:65be27845400	2936
AnnaBridge	172:65be27845400	2937
AnnaBridge	172:65be27845400	2938	/** @brief Enables or disables the specified HRTIM common interrupts.
AnnaBridge	172:65be27845400	2939	* @param __HANDLE__ specifies the HRTIM Handle.
AnnaBridge	172:65be27845400	2940	* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
AnnaBridge	172:65be27845400	2941	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2942	* @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
AnnaBridge	172:65be27845400	2943	* @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
AnnaBridge	172:65be27845400	2944	* @arg HRTIM_IT_FLT3: Fault 3 interrupt enable
AnnaBridge	172:65be27845400	2945	* @arg HRTIM_IT_FLT4: Fault 4 interrupt enable
AnnaBridge	172:65be27845400	2946	* @arg HRTIM_IT_FLT5: Fault 5 interrupt enable
AnnaBridge	172:65be27845400	2947	* @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
AnnaBridge	172:65be27845400	2948	* @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
AnnaBridge	172:65be27845400	2949	* @retval None
AnnaBridge	172:65be27845400	2950	*/
AnnaBridge	172:65be27845400	2951	#define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER \|= (__INTERRUPT__))
AnnaBridge	172:65be27845400	2952	#define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
AnnaBridge	172:65be27845400	2953
AnnaBridge	172:65be27845400	2954	/** @brief Enables or disables the specified HRTIM Master timer interrupts.
AnnaBridge	172:65be27845400	2955	* @param __HANDLE__ specifies the HRTIM Handle.
AnnaBridge	172:65be27845400	2956	* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
AnnaBridge	172:65be27845400	2957	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2958	* @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
AnnaBridge	172:65be27845400	2959	* @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
AnnaBridge	172:65be27845400	2960	* @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
AnnaBridge	172:65be27845400	2961	* @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
AnnaBridge	172:65be27845400	2962	* @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
AnnaBridge	172:65be27845400	2963	* @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
AnnaBridge	172:65be27845400	2964	* @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
AnnaBridge	172:65be27845400	2965	* @retval None
AnnaBridge	172:65be27845400	2966	*/
AnnaBridge	172:65be27845400	2967	#define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER \|= (__INTERRUPT__))
AnnaBridge	172:65be27845400	2968	#define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__INTERRUPT__))
AnnaBridge	172:65be27845400	2969
AnnaBridge	172:65be27845400	2970	/** @brief Enables or disables the specified HRTIM Timerx interrupts.
AnnaBridge	172:65be27845400	2971	* @param __HANDLE__ specifies the HRTIM Handle.
AnnaBridge	172:65be27845400	2972	* @param __TIMER__ specified the timing unit (Timer A to E)
AnnaBridge	172:65be27845400	2973	* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
AnnaBridge	172:65be27845400	2974	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2975	* @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
AnnaBridge	172:65be27845400	2976	* @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
AnnaBridge	172:65be27845400	2977	* @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
AnnaBridge	172:65be27845400	2978	* @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
AnnaBridge	172:65be27845400	2979	* @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
AnnaBridge	172:65be27845400	2980	* @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
AnnaBridge	172:65be27845400	2981	* @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
AnnaBridge	172:65be27845400	2982	* @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
AnnaBridge	172:65be27845400	2983	* @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
AnnaBridge	172:65be27845400	2984	* @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
AnnaBridge	172:65be27845400	2985	* @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
AnnaBridge	172:65be27845400	2986	* @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
AnnaBridge	172:65be27845400	2987	* @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
AnnaBridge	172:65be27845400	2988	* @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
AnnaBridge	172:65be27845400	2989	* @retval None
AnnaBridge	172:65be27845400	2990	*/
AnnaBridge	172:65be27845400	2991	#define __HAL_HRTIM_TIMER_ENABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER \|= (__INTERRUPT__))
AnnaBridge	172:65be27845400	2992	#define __HAL_HRTIM_TIMER_DISABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__INTERRUPT__))
AnnaBridge	172:65be27845400	2993
AnnaBridge	172:65be27845400	2994	/** @brief Checks if the specified HRTIM common interrupt source is enabled or disabled.
AnnaBridge	172:65be27845400	2995	* @param __HANDLE__ specifies the HRTIM Handle.
AnnaBridge	172:65be27845400	2996	* @param __INTERRUPT__ specifies the interrupt source to check.
AnnaBridge	172:65be27845400	2997	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	2998	* @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
AnnaBridge	172:65be27845400	2999	* @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
AnnaBridge	172:65be27845400	3000	* @arg HRTIM_IT_FLT3: Fault 3 enable
AnnaBridge	172:65be27845400	3001	* @arg HRTIM_IT_FLT4: Fault 4 enable
AnnaBridge	172:65be27845400	3002	* @arg HRTIM_IT_FLT5: Fault 5 enable
AnnaBridge	172:65be27845400	3003	* @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
AnnaBridge	172:65be27845400	3004	* @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
AnnaBridge	172:65be27845400	3005	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
AnnaBridge	172:65be27845400	3006	*/
AnnaBridge	172:65be27845400	3007	#define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sCommonRegs.IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
AnnaBridge	172:65be27845400	3008
AnnaBridge	172:65be27845400	3009	/** @brief Checks if the specified HRTIM Master interrupt source is enabled or disabled.
AnnaBridge	172:65be27845400	3010	* @param __HANDLE__ specifies the HRTIM Handle.
AnnaBridge	172:65be27845400	3011	* @param __INTERRUPT__ specifies the interrupt source to check.
AnnaBridge	172:65be27845400	3012	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3013	* @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
AnnaBridge	172:65be27845400	3014	* @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
AnnaBridge	172:65be27845400	3015	* @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
AnnaBridge	172:65be27845400	3016	* @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
AnnaBridge	172:65be27845400	3017	* @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
AnnaBridge	172:65be27845400	3018	* @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
AnnaBridge	172:65be27845400	3019	* @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
AnnaBridge	172:65be27845400	3020	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
AnnaBridge	172:65be27845400	3021	*/
AnnaBridge	172:65be27845400	3022	#define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sMasterRegs.MDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
AnnaBridge	172:65be27845400	3023
AnnaBridge	172:65be27845400	3024	/** @brief Checks if the specified HRTIM Timerx interrupt source is enabled or disabled.
AnnaBridge	172:65be27845400	3025	* @param __HANDLE__ specifies the HRTIM Handle.
AnnaBridge	172:65be27845400	3026	* @param __TIMER__ specified the timing unit (Timer A to E)
AnnaBridge	172:65be27845400	3027	* @param __INTERRUPT__ specifies the interrupt source to check.
AnnaBridge	172:65be27845400	3028	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3029	* @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
AnnaBridge	172:65be27845400	3030	* @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
AnnaBridge	172:65be27845400	3031	* @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
AnnaBridge	172:65be27845400	3032	* @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
AnnaBridge	172:65be27845400	3033	* @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
AnnaBridge	172:65be27845400	3034	* @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
AnnaBridge	172:65be27845400	3035	* @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
AnnaBridge	172:65be27845400	3036	* @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
AnnaBridge	172:65be27845400	3037	* @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
AnnaBridge	172:65be27845400	3038	* @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
AnnaBridge	172:65be27845400	3039	* @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
AnnaBridge	172:65be27845400	3040	* @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
AnnaBridge	172:65be27845400	3041	* @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
AnnaBridge	172:65be27845400	3042	* @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
AnnaBridge	172:65be27845400	3043	* @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
AnnaBridge	172:65be27845400	3044	* @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
AnnaBridge	172:65be27845400	3045	* @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
AnnaBridge	172:65be27845400	3046	* @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
AnnaBridge	172:65be27845400	3047	* @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
AnnaBridge	172:65be27845400	3048	* @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
AnnaBridge	172:65be27845400	3049	* @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
AnnaBridge	172:65be27845400	3050	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
AnnaBridge	172:65be27845400	3051	*/
AnnaBridge	172:65be27845400	3052	#define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__) ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
AnnaBridge	172:65be27845400	3053
AnnaBridge	172:65be27845400	3054	/** @brief Clears the specified HRTIM common pending flag.
AnnaBridge	172:65be27845400	3055	* @param __HANDLE__ specifies the HRTIM Handle.
AnnaBridge	172:65be27845400	3056	* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
AnnaBridge	172:65be27845400	3057	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3058	* @arg HRTIM_IT_FLT1: Fault 1 interrupt clear flag
AnnaBridge	172:65be27845400	3059	* @arg HRTIM_IT_FLT2: Fault 2 interrupt clear flag
AnnaBridge	172:65be27845400	3060	* @arg HRTIM_IT_FLT3: Fault 3 clear flag
AnnaBridge	172:65be27845400	3061	* @arg HRTIM_IT_FLT4: Fault 4 clear flag
AnnaBridge	172:65be27845400	3062	* @arg HRTIM_IT_FLT5: Fault 5 clear flag
AnnaBridge	172:65be27845400	3063	* @arg HRTIM_IT_SYSFLT: System Fault interrupt clear flag
AnnaBridge	172:65be27845400	3064	* @arg HRTIM_IT_BMPER: Burst mode period interrupt clear flag
AnnaBridge	172:65be27845400	3065	* @retval None
AnnaBridge	172:65be27845400	3066	*/
AnnaBridge	172:65be27845400	3067	#define __HAL_HRTIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__INTERRUPT__))
AnnaBridge	172:65be27845400	3068
AnnaBridge	172:65be27845400	3069	/** @brief Clears the specified HRTIM Master pending flag.
AnnaBridge	172:65be27845400	3070	* @param __HANDLE__ specifies the HRTIM Handle.
AnnaBridge	172:65be27845400	3071	* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
AnnaBridge	172:65be27845400	3072	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3073	* @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt clear flag
AnnaBridge	172:65be27845400	3074	* @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt clear flag
AnnaBridge	172:65be27845400	3075	* @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt clear flag
AnnaBridge	172:65be27845400	3076	* @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt clear flag
AnnaBridge	172:65be27845400	3077	* @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt clear flag
AnnaBridge	172:65be27845400	3078	* @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt clear flag
AnnaBridge	172:65be27845400	3079	* @arg HRTIM_MASTER_IT_MUPD: Master update interrupt clear flag
AnnaBridge	172:65be27845400	3080	* @retval None
AnnaBridge	172:65be27845400	3081	*/
AnnaBridge	172:65be27845400	3082	#define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__INTERRUPT__))
AnnaBridge	172:65be27845400	3083
AnnaBridge	172:65be27845400	3084	/** @brief Clears the specified HRTIM Timerx pending flag.
AnnaBridge	172:65be27845400	3085	* @param __HANDLE__ specifies the HRTIM Handle.
AnnaBridge	172:65be27845400	3086	* @param __TIMER__ specified the timing unit (Timer A to E)
AnnaBridge	172:65be27845400	3087	* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
AnnaBridge	172:65be27845400	3088	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3089	* @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt clear flag
AnnaBridge	172:65be27845400	3090	* @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt clear flag
AnnaBridge	172:65be27845400	3091	* @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt clear flag
AnnaBridge	172:65be27845400	3092	* @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt clear flag
AnnaBridge	172:65be27845400	3093	* @arg HRTIM_TIM_IT_REP: Timer repetition interrupt clear flag
AnnaBridge	172:65be27845400	3094	* @arg HRTIM_TIM_IT_UPD: Timer update interrupt clear flag
AnnaBridge	172:65be27845400	3095	* @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt clear flag
AnnaBridge	172:65be27845400	3096	* @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt clear flag
AnnaBridge	172:65be27845400	3097	* @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt clear flag
AnnaBridge	172:65be27845400	3098	* @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt clear flag
AnnaBridge	172:65be27845400	3099	* @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt clear flag
AnnaBridge	172:65be27845400	3100	* @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt clear flag
AnnaBridge	172:65be27845400	3101	* @arg HRTIM_TIM_IT_RST: Timer reset interrupt clear flag
AnnaBridge	172:65be27845400	3102	* @arg HRTIM_TIM_IT_DLYPRT: Timer output 1 delay protection interrupt clear flag
AnnaBridge	172:65be27845400	3103	* @retval None
AnnaBridge	172:65be27845400	3104	*/
AnnaBridge	172:65be27845400	3105	#define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__INTERRUPT__))
AnnaBridge	172:65be27845400	3106
AnnaBridge	172:65be27845400	3107	/* DMA HANDLING */
AnnaBridge	172:65be27845400	3108	/** @brief Enables or disables the specified HRTIM Master timer DMA requests.
AnnaBridge	172:65be27845400	3109	* @param __HANDLE__ specifies the HRTIM Handle.
AnnaBridge	172:65be27845400	3110	* @param __DMA__ specifies the DMA request to enable or disable.
AnnaBridge	172:65be27845400	3111	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3112	* @arg HRTIM_MASTER_DMA_MCMP1: Master compare 1 DMA request enable
AnnaBridge	172:65be27845400	3113	* @arg HRTIM_MASTER_DMA_MCMP2: Master compare 2 DMA request enable
AnnaBridge	172:65be27845400	3114	* @arg HRTIM_MASTER_DMA_MCMP3: Master compare 3 DMA request enable
AnnaBridge	172:65be27845400	3115	* @arg HRTIM_MASTER_DMA_MCMP4: Master compare 4 DMA request enable
AnnaBridge	172:65be27845400	3116	* @arg HRTIM_MASTER_DMA_MREP: Master Repetition DMA request enable
AnnaBridge	172:65be27845400	3117	* @arg HRTIM_MASTER_DMA_SYNC: Synchronization input DMA request enable
AnnaBridge	172:65be27845400	3118	* @arg HRTIM_MASTER_DMA_MUPD: Master update DMA request enable
AnnaBridge	172:65be27845400	3119	* @retval None
AnnaBridge	172:65be27845400	3120	*/
AnnaBridge	172:65be27845400	3121	#define __HAL_HRTIM_MASTER_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER \|= (__DMA__))
AnnaBridge	172:65be27845400	3122	#define __HAL_HRTIM_MASTER_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__DMA__))
AnnaBridge	172:65be27845400	3123
AnnaBridge	172:65be27845400	3124	/** @brief Enables or disables the specified HRTIM Timerx DMA requests.
AnnaBridge	172:65be27845400	3125	* @param __HANDLE__ specifies the HRTIM Handle.
AnnaBridge	172:65be27845400	3126	* @param __TIMER__ specified the timing unit (Timer A to E)
AnnaBridge	172:65be27845400	3127	* @param __DMA__ specifies the DMA request to enable or disable.
AnnaBridge	172:65be27845400	3128	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3129	* @arg HRTIM_TIM_DMA_CMP1: Timer compare 1 DMA request enable
AnnaBridge	172:65be27845400	3130	* @arg HRTIM_TIM_DMA_CMP2: Timer compare 2 DMA request enable
AnnaBridge	172:65be27845400	3131	* @arg HRTIM_TIM_DMA_CMP3: Timer compare 3 DMA request enable
AnnaBridge	172:65be27845400	3132	* @arg HRTIM_TIM_DMA_CMP4: Timer compare 4 DMA request enable
AnnaBridge	172:65be27845400	3133	* @arg HRTIM_TIM_DMA_REP: Timer repetition DMA request enable
AnnaBridge	172:65be27845400	3134	* @arg HRTIM_TIM_DMA_UPD: Timer update DMA request enable
AnnaBridge	172:65be27845400	3135	* @arg HRTIM_TIM_DMA_CPT1: Timer capture 1 DMA request enable
AnnaBridge	172:65be27845400	3136	* @arg HRTIM_TIM_DMA_CPT2: Timer capture 2 DMA request enable
AnnaBridge	172:65be27845400	3137	* @arg HRTIM_TIM_DMA_SET1: Timer output 1 set DMA request enable
AnnaBridge	172:65be27845400	3138	* @arg HRTIM_TIM_DMA_RST1: Timer output 1 reset DMA request enable
AnnaBridge	172:65be27845400	3139	* @arg HRTIM_TIM_DMA_SET2: Timer output 2 set DMA request enable
AnnaBridge	172:65be27845400	3140	* @arg HRTIM_TIM_DMA_RST2: Timer output 2 reset DMA request enable
AnnaBridge	172:65be27845400	3141	* @arg HRTIM_TIM_DMA_RST: Timer reset DMA request enable
AnnaBridge	172:65be27845400	3142	* @arg HRTIM_TIM_DMA_DLYPRT: Timer delay protection DMA request enable
AnnaBridge	172:65be27845400	3143	* @retval None
AnnaBridge	172:65be27845400	3144	*/
AnnaBridge	172:65be27845400	3145	#define __HAL_HRTIM_TIMER_ENABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER \|= (__DMA__))
AnnaBridge	172:65be27845400	3146	#define __HAL_HRTIM_TIMER_DISABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__DMA__))
AnnaBridge	172:65be27845400	3147
AnnaBridge	172:65be27845400	3148	#define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sCommonRegs.ISR & (__FLAG__)) == (__FLAG__))
AnnaBridge	172:65be27845400	3149	#define __HAL_HRTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__FLAG__))
AnnaBridge	172:65be27845400	3150
AnnaBridge	172:65be27845400	3151	#define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sMasterRegs.MISR & (__FLAG__)) == (__FLAG__))
AnnaBridge	172:65be27845400	3152	#define __HAL_HRTIM_MASTER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__FLAG__))
AnnaBridge	172:65be27845400	3153
AnnaBridge	172:65be27845400	3154	#define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__, __TIMER__, __FLAG__) (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR & (__FLAG__)) == (__FLAG__))
AnnaBridge	172:65be27845400	3155	#define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__, __TIMER__, __FLAG__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__FLAG__))
AnnaBridge	172:65be27845400	3156
AnnaBridge	172:65be27845400	3157	/** @brief Sets the HRTIM timer Counter Register value on runtime
AnnaBridge	172:65be27845400	3158	* @param __HANDLE__ HRTIM Handle.
AnnaBridge	172:65be27845400	3159	* @param __TIMER__ HRTIM timer
AnnaBridge	172:65be27845400	3160	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3161	* @arg 0x5 for master timer
AnnaBridge	172:65be27845400	3162	* @arg 0x0 to 0x4 for timers A to E
AnnaBridge	172:65be27845400	3163	* @param __COUNTER__ specifies the Counter Register new value.
AnnaBridge	172:65be27845400	3164	* @retval None
AnnaBridge	172:65be27845400	3165	*/
AnnaBridge	172:65be27845400	3166	#define __HAL_HRTIM_SETCOUNTER(__HANDLE__, __TIMER__, __COUNTER__) \
AnnaBridge	172:65be27845400	3167	(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR = (__COUNTER__)) :\
AnnaBridge	172:65be27845400	3168	((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR = (__COUNTER__)))
AnnaBridge	172:65be27845400	3169
AnnaBridge	172:65be27845400	3170	/** @brief Gets the HRTIM timer Counter Register value on runtime
AnnaBridge	172:65be27845400	3171	* @param __HANDLE__ HRTIM Handle.
AnnaBridge	172:65be27845400	3172	* @param __TIMER__ HRTIM timer
AnnaBridge	172:65be27845400	3173	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3174	* @arg 0x5 for master timer
AnnaBridge	172:65be27845400	3175	* @arg 0x0 to 0x4 for timers A to E
AnnaBridge	172:65be27845400	3176	* @retval HRTIM timer Counter Register value
AnnaBridge	172:65be27845400	3177	*/
AnnaBridge	172:65be27845400	3178	#define __HAL_HRTIM_GETCOUNTER(__HANDLE__, __TIMER__) \
AnnaBridge	172:65be27845400	3179	(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR) :\
AnnaBridge	172:65be27845400	3180	((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR))
AnnaBridge	172:65be27845400	3181
AnnaBridge	172:65be27845400	3182	/** @brief Sets the HRTIM timer Period value on runtime
AnnaBridge	172:65be27845400	3183	* @param __HANDLE__ HRTIM Handle.
AnnaBridge	172:65be27845400	3184	* @param __TIMER__ HRTIM timer
AnnaBridge	172:65be27845400	3185	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3186	* @arg 0x5 for master timer
AnnaBridge	172:65be27845400	3187	* @arg 0x0 to 0x4 for timers A to E
AnnaBridge	172:65be27845400	3188	* @param __PERIOD__ specifies the Period Register new value.
AnnaBridge	172:65be27845400	3189	* @retval None
AnnaBridge	172:65be27845400	3190	*/
AnnaBridge	172:65be27845400	3191	#define __HAL_HRTIM_SETPERIOD(__HANDLE__, __TIMER__, __PERIOD__) \
AnnaBridge	172:65be27845400	3192	(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER = (__PERIOD__)) :\
AnnaBridge	172:65be27845400	3193	((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR = (__PERIOD__)))
AnnaBridge	172:65be27845400	3194
AnnaBridge	172:65be27845400	3195	/** @brief Gets the HRTIM timer Period Register value on runtime
AnnaBridge	172:65be27845400	3196	* @param __HANDLE__ HRTIM Handle.
AnnaBridge	172:65be27845400	3197	* @param __TIMER__ HRTIM timer
AnnaBridge	172:65be27845400	3198	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3199	* @arg 0x5 for master timer
AnnaBridge	172:65be27845400	3200	* @arg 0x0 to 0x4 for timers A to E
AnnaBridge	172:65be27845400	3201	* @retval timer Period Register
AnnaBridge	172:65be27845400	3202	*/
AnnaBridge	172:65be27845400	3203	#define __HAL_HRTIM_GETPERIOD(__HANDLE__, __TIMER__) \
AnnaBridge	172:65be27845400	3204	(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER) :\
AnnaBridge	172:65be27845400	3205	((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR))
AnnaBridge	172:65be27845400	3206
AnnaBridge	172:65be27845400	3207	/** @brief Sets the HRTIM timer clock prescaler value on runtime
AnnaBridge	172:65be27845400	3208	* @param __HANDLE__ HRTIM Handle.
AnnaBridge	172:65be27845400	3209	* @param __TIMER__ HRTIM timer
AnnaBridge	172:65be27845400	3210	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3211	* @arg 0x5 for master timer
AnnaBridge	172:65be27845400	3212	* @arg 0x0 to 0x4 for timers A to E
AnnaBridge	172:65be27845400	3213	* @param __PRESCALER__ specifies the clock prescaler new value.
AnnaBridge	172:65be27845400	3214	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3215	* @arg HRTIM_PRESCALERRATIO_MUL32: fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz)
AnnaBridge	172:65be27845400	3216	* @arg HRTIM_PRESCALERRATIO_MUL16: fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz)
AnnaBridge	172:65be27845400	3217	* @arg HRTIM_PRESCALERRATIO_MUL8: fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz)
AnnaBridge	172:65be27845400	3218	* @arg HRTIM_PRESCALERRATIO_MUL4: fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz)
AnnaBridge	172:65be27845400	3219	* @arg HRTIM_PRESCALERRATIO_MUL2: fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz)
AnnaBridge	172:65be27845400	3220	* @arg HRTIM_PRESCALERRATIO_DIV1: fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz)
AnnaBridge	172:65be27845400	3221	* @arg HRTIM_PRESCALERRATIO_DIV2: fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz)
AnnaBridge	172:65be27845400	3222	* @arg HRTIM_PRESCALERRATIO_DIV4: fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz)
AnnaBridge	172:65be27845400	3223	* @retval None
AnnaBridge	172:65be27845400	3224	*/
AnnaBridge	172:65be27845400	3225	#define __HAL_HRTIM_SETCLOCKPRESCALER(__HANDLE__, __TIMER__, __PRESCALER__) \
AnnaBridge	172:65be27845400	3226	(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? (MODIFY_REG((__HANDLE__)->Instance->sMasterRegs.MCR, HRTIM_MCR_CK_PSC, (__PRESCALER__))) :\
AnnaBridge	172:65be27845400	3227	(MODIFY_REG((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR, HRTIM_TIMCR_CK_PSC, (__PRESCALER__))))
AnnaBridge	172:65be27845400	3228
AnnaBridge	172:65be27845400	3229	/** @brief Gets the HRTIM timer clock prescaler value on runtime
AnnaBridge	172:65be27845400	3230	* @param __HANDLE__ HRTIM Handle.
AnnaBridge	172:65be27845400	3231	* @param __TIMER__ HRTIM timer
AnnaBridge	172:65be27845400	3232	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3233	* @arg 0x5 for master timer
AnnaBridge	172:65be27845400	3234	* @arg 0x0 to 0x4 for timers A to E
AnnaBridge	172:65be27845400	3235	* @retval timer clock prescaler value
AnnaBridge	172:65be27845400	3236	*/
AnnaBridge	172:65be27845400	3237	#define __HAL_HRTIM_GETCLOCKPRESCALER(__HANDLE__, __TIMER__) \
AnnaBridge	172:65be27845400	3238	(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCR & HRTIM_MCR_CK_PSC) :\
AnnaBridge	172:65be27845400	3239	((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR & HRTIM_TIMCR_CK_PSC))
AnnaBridge	172:65be27845400	3240
AnnaBridge	172:65be27845400	3241	/** @brief Sets the HRTIM timer Compare Register value on runtime
AnnaBridge	172:65be27845400	3242	* @param __HANDLE__ HRTIM Handle.
AnnaBridge	172:65be27845400	3243	* @param __TIMER__ HRTIM timer
AnnaBridge	172:65be27845400	3244	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3245	* @arg 0x0 to 0x4 for timers A to E
AnnaBridge	172:65be27845400	3246	* @param __COMPAREUNIT__ timer compare unit
AnnaBridge	172:65be27845400	3247	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3248	* @arg HRTIM_COMPAREUNIT_1: Compare unit 1
AnnaBridge	172:65be27845400	3249	* @arg HRTIM_COMPAREUNIT_2: Compare unit 2
AnnaBridge	172:65be27845400	3250	* @arg HRTIM_COMPAREUNIT_3: Compare unit 3
AnnaBridge	172:65be27845400	3251	* @arg HRTIM_COMPAREUNIT_4: Compare unit 4
AnnaBridge	172:65be27845400	3252	* @param __COMPARE__ specifies the Compare new value.
AnnaBridge	172:65be27845400	3253	* @retval None
AnnaBridge	172:65be27845400	3254	*/
AnnaBridge	172:65be27845400	3255	#define __HAL_HRTIM_SETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__, __COMPARE__) \
AnnaBridge	172:65be27845400	3256	(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
AnnaBridge	172:65be27845400	3257	(((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\
AnnaBridge	172:65be27845400	3258	((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\
AnnaBridge	172:65be27845400	3259	((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\
AnnaBridge	172:65be27845400	3260	((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \
AnnaBridge	172:65be27845400	3261	: \
AnnaBridge	172:65be27845400	3262	(((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\
AnnaBridge	172:65be27845400	3263	((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\
AnnaBridge	172:65be27845400	3264	((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\
AnnaBridge	172:65be27845400	3265	((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__))))
AnnaBridge	172:65be27845400	3266
AnnaBridge	172:65be27845400	3267	/** @brief Gets the HRTIM timer Compare Register value on runtime
AnnaBridge	172:65be27845400	3268	* @param __HANDLE__ HRTIM Handle.
AnnaBridge	172:65be27845400	3269	* @param __TIMER__ HRTIM timer
AnnaBridge	172:65be27845400	3270	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3271	* @arg 0x0 to 0x4 for timers A to E
AnnaBridge	172:65be27845400	3272	* @param __COMPAREUNIT__ timer compare unit
AnnaBridge	172:65be27845400	3273	* This parameter can be one of the following values:
AnnaBridge	172:65be27845400	3274	* @arg HRTIM_COMPAREUNIT_1: Compare unit 1
AnnaBridge	172:65be27845400	3275	* @arg HRTIM_COMPAREUNIT_2: Compare unit 2
AnnaBridge	172:65be27845400	3276	* @arg HRTIM_COMPAREUNIT_3: Compare unit 3
AnnaBridge	172:65be27845400	3277	* @arg HRTIM_COMPAREUNIT_4: Compare unit 4
AnnaBridge	172:65be27845400	3278	* @retval Compare value
AnnaBridge	172:65be27845400	3279	*/
AnnaBridge	172:65be27845400	3280	#define __HAL_HRTIM_GETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__) \
AnnaBridge	172:65be27845400	3281	(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
AnnaBridge	172:65be27845400	3282	(((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\
AnnaBridge	172:65be27845400	3283	((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\
AnnaBridge	172:65be27845400	3284	((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\
AnnaBridge	172:65be27845400	3285	((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \
AnnaBridge	172:65be27845400	3286	: \
AnnaBridge	172:65be27845400	3287	(((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\
AnnaBridge	172:65be27845400	3288	((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\
AnnaBridge	172:65be27845400	3289	((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\
AnnaBridge	172:65be27845400	3290	((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR)))
AnnaBridge	172:65be27845400	3291
AnnaBridge	172:65be27845400	3292	/**
AnnaBridge	172:65be27845400	3293	* @}
AnnaBridge	172:65be27845400	3294	*/
AnnaBridge	172:65be27845400	3295
AnnaBridge	172:65be27845400	3296	/* Exported functions --------------------------------------------------------*/
AnnaBridge	172:65be27845400	3297	/** @addtogroup HRTIM_Exported_Functions
AnnaBridge	172:65be27845400	3298	* @{
AnnaBridge	172:65be27845400	3299	*/
AnnaBridge	172:65be27845400	3300
AnnaBridge	172:65be27845400	3301	/** @addtogroup HRTIM_Exported_Functions_Group1
AnnaBridge	172:65be27845400	3302	* @{
AnnaBridge	172:65be27845400	3303	*/
AnnaBridge	172:65be27845400	3304
AnnaBridge	172:65be27845400	3305	/* Initialization and Configuration functions ********************************/
AnnaBridge	172:65be27845400	3306	HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim);
AnnaBridge	172:65be27845400	3307
AnnaBridge	172:65be27845400	3308	HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef *hhrtim);
AnnaBridge	172:65be27845400	3309
AnnaBridge	172:65be27845400	3310	void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim);
AnnaBridge	172:65be27845400	3311
AnnaBridge	172:65be27845400	3312	void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim);
AnnaBridge	172:65be27845400	3313
AnnaBridge	172:65be27845400	3314	HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3315	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3316	HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
AnnaBridge	172:65be27845400	3317	/**
AnnaBridge	172:65be27845400	3318	* @}
AnnaBridge	172:65be27845400	3319	*/
AnnaBridge	172:65be27845400	3320
AnnaBridge	172:65be27845400	3321	/** @addtogroup HRTIM_Exported_Functions_Group2
AnnaBridge	172:65be27845400	3322	* @{
AnnaBridge	172:65be27845400	3323	*/
AnnaBridge	172:65be27845400	3324
AnnaBridge	172:65be27845400	3325	/* Simple time base related functions *****************************************/
AnnaBridge	172:65be27845400	3326	HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3327	uint32_t TimerIdx);
AnnaBridge	172:65be27845400	3328
AnnaBridge	172:65be27845400	3329	HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3330	uint32_t TimerIdx);
AnnaBridge	172:65be27845400	3331
AnnaBridge	172:65be27845400	3332	HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3333	uint32_t TimerIdx);
AnnaBridge	172:65be27845400	3334
AnnaBridge	172:65be27845400	3335	HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3336	uint32_t TimerIdx);
AnnaBridge	172:65be27845400	3337
AnnaBridge	172:65be27845400	3338	HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3339	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3340	uint32_t SrcAddr,
AnnaBridge	172:65be27845400	3341	uint32_t DestAddr,
AnnaBridge	172:65be27845400	3342	uint32_t Length);
AnnaBridge	172:65be27845400	3343
AnnaBridge	172:65be27845400	3344	HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3345	uint32_t TimerIdx);
AnnaBridge	172:65be27845400	3346
AnnaBridge	172:65be27845400	3347	/**
AnnaBridge	172:65be27845400	3348	* @}
AnnaBridge	172:65be27845400	3349	*/
AnnaBridge	172:65be27845400	3350
AnnaBridge	172:65be27845400	3351	/** @addtogroup HRTIM_Exported_Functions_Group3
AnnaBridge	172:65be27845400	3352	* @{
AnnaBridge	172:65be27845400	3353	*/
AnnaBridge	172:65be27845400	3354	/* Simple output compare related functions ************************************/
AnnaBridge	172:65be27845400	3355	HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3356	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3357	uint32_t OCChannel,
AnnaBridge	172:65be27845400	3358	HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg);
AnnaBridge	172:65be27845400	3359
AnnaBridge	172:65be27845400	3360	HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3361	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3362	uint32_t OCChannel);
AnnaBridge	172:65be27845400	3363
AnnaBridge	172:65be27845400	3364	HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3365	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3366	uint32_t OCChannel);
AnnaBridge	172:65be27845400	3367
AnnaBridge	172:65be27845400	3368	HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3369	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3370	uint32_t OCChannel);
AnnaBridge	172:65be27845400	3371
AnnaBridge	172:65be27845400	3372	HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3373	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3374	uint32_t OCChannel);
AnnaBridge	172:65be27845400	3375
AnnaBridge	172:65be27845400	3376	HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3377	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3378	uint32_t OCChannel,
AnnaBridge	172:65be27845400	3379	uint32_t SrcAddr,
AnnaBridge	172:65be27845400	3380	uint32_t DestAddr,
AnnaBridge	172:65be27845400	3381	uint32_t Length);
AnnaBridge	172:65be27845400	3382
AnnaBridge	172:65be27845400	3383	HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3384	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3385	uint32_t OCChannel);
AnnaBridge	172:65be27845400	3386
AnnaBridge	172:65be27845400	3387	/**
AnnaBridge	172:65be27845400	3388	* @}
AnnaBridge	172:65be27845400	3389	*/
AnnaBridge	172:65be27845400	3390
AnnaBridge	172:65be27845400	3391	/** @addtogroup HRTIM_Exported_Functions_Group4
AnnaBridge	172:65be27845400	3392	* @{
AnnaBridge	172:65be27845400	3393	*/
AnnaBridge	172:65be27845400	3394	/* Simple PWM output related functions ****************************************/
AnnaBridge	172:65be27845400	3395	HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3396	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3397	uint32_t PWMChannel,
AnnaBridge	172:65be27845400	3398	HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg);
AnnaBridge	172:65be27845400	3399
AnnaBridge	172:65be27845400	3400	HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3401	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3402	uint32_t PWMChannel);
AnnaBridge	172:65be27845400	3403
AnnaBridge	172:65be27845400	3404	HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3405	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3406	uint32_t PWMChannel);
AnnaBridge	172:65be27845400	3407
AnnaBridge	172:65be27845400	3408	HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3409	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3410	uint32_t PWMChannel);
AnnaBridge	172:65be27845400	3411
AnnaBridge	172:65be27845400	3412	HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3413	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3414	uint32_t PWMChannel);
AnnaBridge	172:65be27845400	3415
AnnaBridge	172:65be27845400	3416	HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3417	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3418	uint32_t PWMChannel,
AnnaBridge	172:65be27845400	3419	uint32_t SrcAddr,
AnnaBridge	172:65be27845400	3420	uint32_t DestAddr,
AnnaBridge	172:65be27845400	3421	uint32_t Length);
AnnaBridge	172:65be27845400	3422
AnnaBridge	172:65be27845400	3423	HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3424	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3425	uint32_t PWMChannel);
AnnaBridge	172:65be27845400	3426
AnnaBridge	172:65be27845400	3427	/**
AnnaBridge	172:65be27845400	3428	* @}
AnnaBridge	172:65be27845400	3429	*/
AnnaBridge	172:65be27845400	3430
AnnaBridge	172:65be27845400	3431	/** @addtogroup HRTIM_Exported_Functions_Group5
AnnaBridge	172:65be27845400	3432	* @{
AnnaBridge	172:65be27845400	3433	*/
AnnaBridge	172:65be27845400	3434	/* Simple capture related functions *******************************************/
AnnaBridge	172:65be27845400	3435	HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3436	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3437	uint32_t CaptureChannel,
AnnaBridge	172:65be27845400	3438	HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg);
AnnaBridge	172:65be27845400	3439
AnnaBridge	172:65be27845400	3440	HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3441	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3442	uint32_t CaptureChannel);
AnnaBridge	172:65be27845400	3443
AnnaBridge	172:65be27845400	3444	HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3445	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3446	uint32_t CaptureChannel);
AnnaBridge	172:65be27845400	3447
AnnaBridge	172:65be27845400	3448	HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3449	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3450	uint32_t CaptureChannel);
AnnaBridge	172:65be27845400	3451
AnnaBridge	172:65be27845400	3452	HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3453	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3454	uint32_t CaptureChannel);
AnnaBridge	172:65be27845400	3455
AnnaBridge	172:65be27845400	3456	HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3457	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3458	uint32_t CaptureChannel,
AnnaBridge	172:65be27845400	3459	uint32_t SrcAddr,
AnnaBridge	172:65be27845400	3460	uint32_t DestAddr,
AnnaBridge	172:65be27845400	3461	uint32_t Length);
AnnaBridge	172:65be27845400	3462
AnnaBridge	172:65be27845400	3463	HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3464	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3465	uint32_t CaptureChannel);
AnnaBridge	172:65be27845400	3466
AnnaBridge	172:65be27845400	3467	/**
AnnaBridge	172:65be27845400	3468	* @}
AnnaBridge	172:65be27845400	3469	*/
AnnaBridge	172:65be27845400	3470
AnnaBridge	172:65be27845400	3471	/** @addtogroup HRTIM_Exported_Functions_Group6
AnnaBridge	172:65be27845400	3472	* @{
AnnaBridge	172:65be27845400	3473	*/
AnnaBridge	172:65be27845400	3474	/* Simple one pulse related functions *****************************************/
AnnaBridge	172:65be27845400	3475	HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3476	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3477	uint32_t OnePulseChannel,
AnnaBridge	172:65be27845400	3478	HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg);
AnnaBridge	172:65be27845400	3479
AnnaBridge	172:65be27845400	3480	HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3481	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3482	uint32_t OnePulseChannel);
AnnaBridge	172:65be27845400	3483
AnnaBridge	172:65be27845400	3484	HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3485	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3486	uint32_t OnePulseChannel);
AnnaBridge	172:65be27845400	3487
AnnaBridge	172:65be27845400	3488	HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3489	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3490	uint32_t OnePulseChannel);
AnnaBridge	172:65be27845400	3491
AnnaBridge	172:65be27845400	3492	HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3493	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3494	uint32_t OnePulseChannel);
AnnaBridge	172:65be27845400	3495
AnnaBridge	172:65be27845400	3496	/**
AnnaBridge	172:65be27845400	3497	* @}
AnnaBridge	172:65be27845400	3498	*/
AnnaBridge	172:65be27845400	3499
AnnaBridge	172:65be27845400	3500	/** @addtogroup HRTIM_Exported_Functions_Group7
AnnaBridge	172:65be27845400	3501	* @{
AnnaBridge	172:65be27845400	3502	*/
AnnaBridge	172:65be27845400	3503	HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3504	HRTIM_BurstModeCfgTypeDef* pBurstModeCfg);
AnnaBridge	172:65be27845400	3505
AnnaBridge	172:65be27845400	3506	HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3507	uint32_t Event,
AnnaBridge	172:65be27845400	3508	HRTIM_EventCfgTypeDef* pEventCfg);
AnnaBridge	172:65be27845400	3509
AnnaBridge	172:65be27845400	3510	HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3511	uint32_t Prescaler);
AnnaBridge	172:65be27845400	3512
AnnaBridge	172:65be27845400	3513	HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3514	uint32_t Fault,
AnnaBridge	172:65be27845400	3515	HRTIM_FaultCfgTypeDef* pFaultCfg);
AnnaBridge	172:65be27845400	3516
AnnaBridge	172:65be27845400	3517	HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3518	uint32_t Prescaler);
AnnaBridge	172:65be27845400	3519
AnnaBridge	172:65be27845400	3520	void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
AnnaBridge	172:65be27845400	3521	uint32_t Faults,
AnnaBridge	172:65be27845400	3522	uint32_t Enable);
AnnaBridge	172:65be27845400	3523
AnnaBridge	172:65be27845400	3524	HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3525	uint32_t ADCTrigger,
AnnaBridge	172:65be27845400	3526	HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg);
AnnaBridge	172:65be27845400	3527
AnnaBridge	172:65be27845400	3528	/**
AnnaBridge	172:65be27845400	3529	* @}
AnnaBridge	172:65be27845400	3530	*/
AnnaBridge	172:65be27845400	3531
AnnaBridge	172:65be27845400	3532	/** @addtogroup HRTIM_Exported_Functions_Group8
AnnaBridge	172:65be27845400	3533	* @{
AnnaBridge	172:65be27845400	3534	*/
AnnaBridge	172:65be27845400	3535	/* Waveform related functions *************************************************/
AnnaBridge	172:65be27845400	3536	HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3537	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3538	HRTIM_TimerCfgTypeDef * pTimerCfg);
AnnaBridge	172:65be27845400	3539
AnnaBridge	172:65be27845400	3540	HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3541	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3542	uint32_t CompareUnit,
AnnaBridge	172:65be27845400	3543	HRTIM_CompareCfgTypeDef* pCompareCfg);
AnnaBridge	172:65be27845400	3544
AnnaBridge	172:65be27845400	3545	HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3546	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3547	uint32_t CaptureUnit,
AnnaBridge	172:65be27845400	3548	HRTIM_CaptureCfgTypeDef* pCaptureCfg);
AnnaBridge	172:65be27845400	3549
AnnaBridge	172:65be27845400	3550	HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3551	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3552	uint32_t Output,
AnnaBridge	172:65be27845400	3553	HRTIM_OutputCfgTypeDef * pOutputCfg);
AnnaBridge	172:65be27845400	3554
AnnaBridge	172:65be27845400	3555	HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3556	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3557	uint32_t Output,
AnnaBridge	172:65be27845400	3558	uint32_t OutputLevel);
AnnaBridge	172:65be27845400	3559
AnnaBridge	172:65be27845400	3560	HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3561	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3562	uint32_t Event,
AnnaBridge	172:65be27845400	3563	HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg);
AnnaBridge	172:65be27845400	3564
AnnaBridge	172:65be27845400	3565	HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3566	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3567	HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg);
AnnaBridge	172:65be27845400	3568
AnnaBridge	172:65be27845400	3569	HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3570	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3571	HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg);
AnnaBridge	172:65be27845400	3572
AnnaBridge	172:65be27845400	3573	HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3574	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3575	uint32_t RegistersToUpdate);
AnnaBridge	172:65be27845400	3576
AnnaBridge	172:65be27845400	3577
AnnaBridge	172:65be27845400	3578	HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3579	uint32_t Timers);
AnnaBridge	172:65be27845400	3580
AnnaBridge	172:65be27845400	3581	HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3582	uint32_t Timers);
AnnaBridge	172:65be27845400	3583
AnnaBridge	172:65be27845400	3584	HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3585	uint32_t Timers);
AnnaBridge	172:65be27845400	3586
AnnaBridge	172:65be27845400	3587	HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3588	uint32_t Timers);
AnnaBridge	172:65be27845400	3589
AnnaBridge	172:65be27845400	3590	HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3591	uint32_t Timers);
AnnaBridge	172:65be27845400	3592
AnnaBridge	172:65be27845400	3593	HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3594	uint32_t Timers);
AnnaBridge	172:65be27845400	3595
AnnaBridge	172:65be27845400	3596	HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3597	uint32_t OutputsToStart);
AnnaBridge	172:65be27845400	3598
AnnaBridge	172:65be27845400	3599	HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3600	uint32_t OutputsToStop);
AnnaBridge	172:65be27845400	3601
AnnaBridge	172:65be27845400	3602	HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3603	uint32_t Enable);
AnnaBridge	172:65be27845400	3604
AnnaBridge	172:65be27845400	3605	HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim);
AnnaBridge	172:65be27845400	3606
AnnaBridge	172:65be27845400	3607	HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3608	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3609	uint32_t CaptureUnit);
AnnaBridge	172:65be27845400	3610
AnnaBridge	172:65be27845400	3611	HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3612	uint32_t Timers);
AnnaBridge	172:65be27845400	3613
AnnaBridge	172:65be27845400	3614	HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3615	uint32_t Timers);
AnnaBridge	172:65be27845400	3616
AnnaBridge	172:65be27845400	3617	HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3618	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3619	uint32_t BurstBufferAddress,
AnnaBridge	172:65be27845400	3620	uint32_t BurstBufferLength);
AnnaBridge	172:65be27845400	3621
AnnaBridge	172:65be27845400	3622	HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3623	uint32_t Timers);
AnnaBridge	172:65be27845400	3624
AnnaBridge	172:65be27845400	3625	HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3626	uint32_t Timers);
AnnaBridge	172:65be27845400	3627
AnnaBridge	172:65be27845400	3628	/**
AnnaBridge	172:65be27845400	3629	* @}
AnnaBridge	172:65be27845400	3630	*/
AnnaBridge	172:65be27845400	3631
AnnaBridge	172:65be27845400	3632	/** @addtogroup HRTIM_Exported_Functions_Group9
AnnaBridge	172:65be27845400	3633	* @{
AnnaBridge	172:65be27845400	3634	*/
AnnaBridge	172:65be27845400	3635	/* HRTIM peripheral state functions */
AnnaBridge	172:65be27845400	3636	HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim);
AnnaBridge	172:65be27845400	3637
AnnaBridge	172:65be27845400	3638	uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim,
AnnaBridge	172:65be27845400	3639	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3640	uint32_t CaptureUnit);
AnnaBridge	172:65be27845400	3641
AnnaBridge	172:65be27845400	3642	uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3643	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3644	uint32_t Output);
AnnaBridge	172:65be27845400	3645
AnnaBridge	172:65be27845400	3646	uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim,
AnnaBridge	172:65be27845400	3647	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3648	uint32_t Output);
AnnaBridge	172:65be27845400	3649
AnnaBridge	172:65be27845400	3650	uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3651	uint32_t TimerIdx,
AnnaBridge	172:65be27845400	3652	uint32_t Output);
AnnaBridge	172:65be27845400	3653
AnnaBridge	172:65be27845400	3654	uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef *hhrtim);
AnnaBridge	172:65be27845400	3655
AnnaBridge	172:65be27845400	3656	uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3657	uint32_t TimerIdx);
AnnaBridge	172:65be27845400	3658
AnnaBridge	172:65be27845400	3659	uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3660	uint32_t TimerIdx);
AnnaBridge	172:65be27845400	3661
AnnaBridge	172:65be27845400	3662	/**
AnnaBridge	172:65be27845400	3663	* @}
AnnaBridge	172:65be27845400	3664	*/
AnnaBridge	172:65be27845400	3665
AnnaBridge	172:65be27845400	3666	/** @addtogroup HRTIM_Exported_Functions_Group10
AnnaBridge	172:65be27845400	3667	* @{
AnnaBridge	172:65be27845400	3668	*/
AnnaBridge	172:65be27845400	3669	/* IRQ handler */
AnnaBridge	172:65be27845400	3670	void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3671	uint32_t TimerIdx);
AnnaBridge	172:65be27845400	3672
AnnaBridge	172:65be27845400	3673	/* HRTIM events related callback functions */
AnnaBridge	172:65be27845400	3674	void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef *hhrtim);
AnnaBridge	172:65be27845400	3675	void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef *hhrtim);
AnnaBridge	172:65be27845400	3676	void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef *hhrtim);
AnnaBridge	172:65be27845400	3677	void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef *hhrtim);
AnnaBridge	172:65be27845400	3678	void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef *hhrtim);
AnnaBridge	172:65be27845400	3679	void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef *hhrtim);
AnnaBridge	172:65be27845400	3680	void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef *hhrtim);
AnnaBridge	172:65be27845400	3681	void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim);
AnnaBridge	172:65be27845400	3682
AnnaBridge	172:65be27845400	3683	/* Timer events related callback functions */
AnnaBridge	172:65be27845400	3684	void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3685	uint32_t TimerIdx);
AnnaBridge	172:65be27845400	3686	void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3687	uint32_t TimerIdx);
AnnaBridge	172:65be27845400	3688	void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3689	uint32_t TimerIdx);
AnnaBridge	172:65be27845400	3690	void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3691	uint32_t TimerIdx);
AnnaBridge	172:65be27845400	3692	void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3693	uint32_t TimerIdx);
AnnaBridge	172:65be27845400	3694	void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3695	uint32_t TimerIdx);
AnnaBridge	172:65be27845400	3696	void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3697	uint32_t TimerIdx);
AnnaBridge	172:65be27845400	3698	void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3699	uint32_t TimerIdx);
AnnaBridge	172:65be27845400	3700	void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3701	uint32_t TimerIdx);
AnnaBridge	172:65be27845400	3702	void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3703	uint32_t TimerIdx);
AnnaBridge	172:65be27845400	3704	void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3705	uint32_t TimerIdx);
AnnaBridge	172:65be27845400	3706	void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3707	uint32_t TimerIdx);
AnnaBridge	172:65be27845400	3708	void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3709	uint32_t TimerIdx);
AnnaBridge	172:65be27845400	3710	void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3711	uint32_t TimerIdx);
AnnaBridge	172:65be27845400	3712	void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim,
AnnaBridge	172:65be27845400	3713	uint32_t TimerIdx);
AnnaBridge	172:65be27845400	3714	void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim);
AnnaBridge	172:65be27845400	3715
AnnaBridge	172:65be27845400	3716	#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
AnnaBridge	172:65be27845400	3717	HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef * hhrtim,
AnnaBridge	172:65be27845400	3718	HAL_HRTIM_CallbackIDTypeDef CallbackID,
AnnaBridge	172:65be27845400	3719	pHRTIM_CallbackTypeDef pCallback);
AnnaBridge	172:65be27845400	3720
AnnaBridge	172:65be27845400	3721	HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,
AnnaBridge	172:65be27845400	3722	HAL_HRTIM_CallbackIDTypeDef CallbackID);
AnnaBridge	172:65be27845400	3723
AnnaBridge	172:65be27845400	3724	HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim,
AnnaBridge	172:65be27845400	3725	HAL_HRTIM_CallbackIDTypeDef CallbackID,
AnnaBridge	172:65be27845400	3726	pHRTIM_TIMxCallbackTypeDef pCallback);
AnnaBridge	172:65be27845400	3727
AnnaBridge	172:65be27845400	3728	HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,
AnnaBridge	172:65be27845400	3729	HAL_HRTIM_CallbackIDTypeDef CallbackID);
AnnaBridge	172:65be27845400	3730	#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
AnnaBridge	172:65be27845400	3731
AnnaBridge	172:65be27845400	3732	/**
AnnaBridge	172:65be27845400	3733	* @}
AnnaBridge	172:65be27845400	3734	*/
AnnaBridge	172:65be27845400	3735
AnnaBridge	172:65be27845400	3736	/**
AnnaBridge	172:65be27845400	3737	* @}
AnnaBridge	172:65be27845400	3738	*/
AnnaBridge	172:65be27845400	3739
AnnaBridge	172:65be27845400	3740	/**
AnnaBridge	172:65be27845400	3741	* @}
AnnaBridge	172:65be27845400	3742	*/
AnnaBridge	172:65be27845400	3743
AnnaBridge	172:65be27845400	3744	/**
AnnaBridge	172:65be27845400	3745	* @}
AnnaBridge	172:65be27845400	3746	*/
AnnaBridge	172:65be27845400	3747
AnnaBridge	172:65be27845400	3748
AnnaBridge	172:65be27845400	3749	#ifdef __cplusplus
AnnaBridge	172:65be27845400	3750	}
AnnaBridge	172:65be27845400	3751	#endif
AnnaBridge	172:65be27845400	3752
AnnaBridge	172:65be27845400	3753	#endif /* STM32H7xx_HAL_HRTIM_H */
AnnaBridge	172:65be27845400	3754
AnnaBridge	172:65be27845400	3755	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/