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TARGET_NUCLEO_H743ZI/TOOLCHAIN_ARM_MICRO/stm32h7xx_hal_flash_ex.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 172:65be27845400 | 1 | /** |
| AnnaBridge | 172:65be27845400 | 2 | ****************************************************************************** |
| AnnaBridge | 172:65be27845400 | 3 | * @file stm32H7xx_hal_flash_ex.h |
| AnnaBridge | 172:65be27845400 | 4 | * @author MCD Application Team |
| AnnaBridge | 172:65be27845400 | 5 | * @brief Header file of FLASH HAL module. |
| AnnaBridge | 172:65be27845400 | 6 | ****************************************************************************** |
| AnnaBridge | 172:65be27845400 | 7 | * @attention |
| AnnaBridge | 172:65be27845400 | 8 | * |
| AnnaBridge | 172:65be27845400 | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics. |
| AnnaBridge | 172:65be27845400 | 10 | * All rights reserved.</center></h2> |
| AnnaBridge | 172:65be27845400 | 11 | * |
| AnnaBridge | 172:65be27845400 | 12 | * This software component is licensed by ST under BSD 3-Clause license, |
| AnnaBridge | 172:65be27845400 | 13 | * the "License"; You may not use this file except in compliance with the |
| AnnaBridge | 172:65be27845400 | 14 | * License. You may obtain a copy of the License at: |
| AnnaBridge | 172:65be27845400 | 15 | * opensource.org/licenses/BSD-3-Clause |
| AnnaBridge | 172:65be27845400 | 16 | * |
| AnnaBridge | 172:65be27845400 | 17 | ****************************************************************************** |
| AnnaBridge | 172:65be27845400 | 18 | */ |
| AnnaBridge | 172:65be27845400 | 19 | |
| AnnaBridge | 172:65be27845400 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 21 | #ifndef STM32H7xx_HAL_FLASH_EX_H |
| AnnaBridge | 172:65be27845400 | 22 | #define STM32H7xx_HAL_FLASH_EX_H |
| AnnaBridge | 172:65be27845400 | 23 | |
| AnnaBridge | 172:65be27845400 | 24 | #ifdef __cplusplus |
| AnnaBridge | 172:65be27845400 | 25 | extern "C" { |
| AnnaBridge | 172:65be27845400 | 26 | #endif |
| AnnaBridge | 172:65be27845400 | 27 | |
| AnnaBridge | 172:65be27845400 | 28 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 29 | #include "stm32h7xx_hal_def.h" |
| AnnaBridge | 172:65be27845400 | 30 | |
| AnnaBridge | 172:65be27845400 | 31 | /** @addtogroup STM32H7xx_HAL_Driver |
| AnnaBridge | 172:65be27845400 | 32 | * @{ |
| AnnaBridge | 172:65be27845400 | 33 | */ |
| AnnaBridge | 172:65be27845400 | 34 | |
| AnnaBridge | 172:65be27845400 | 35 | /** @addtogroup FLASHEx |
| AnnaBridge | 172:65be27845400 | 36 | * @{ |
| AnnaBridge | 172:65be27845400 | 37 | */ |
| AnnaBridge | 172:65be27845400 | 38 | |
| AnnaBridge | 172:65be27845400 | 39 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 40 | /** @defgroup FLASHEx_Exported_Types FLASH Exported Types |
| AnnaBridge | 172:65be27845400 | 41 | * @{ |
| AnnaBridge | 172:65be27845400 | 42 | */ |
| AnnaBridge | 172:65be27845400 | 43 | |
| AnnaBridge | 172:65be27845400 | 44 | /** |
| AnnaBridge | 172:65be27845400 | 45 | * @brief FLASH Erase structure definition |
| AnnaBridge | 172:65be27845400 | 46 | */ |
| AnnaBridge | 172:65be27845400 | 47 | typedef struct |
| AnnaBridge | 172:65be27845400 | 48 | { |
| AnnaBridge | 172:65be27845400 | 49 | uint32_t TypeErase; /*!< Mass erase or sector Erase. |
| AnnaBridge | 172:65be27845400 | 50 | This parameter can be a value of @ref FLASHEx_Type_Erase */ |
| AnnaBridge | 172:65be27845400 | 51 | |
| AnnaBridge | 172:65be27845400 | 52 | uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. |
| AnnaBridge | 172:65be27845400 | 53 | This parameter must be a value of @ref FLASHEx_Banks */ |
| AnnaBridge | 172:65be27845400 | 54 | |
| AnnaBridge | 172:65be27845400 | 55 | uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled |
| AnnaBridge | 172:65be27845400 | 56 | This parameter must be a value of @ref FLASH_Sectors */ |
| AnnaBridge | 172:65be27845400 | 57 | |
| AnnaBridge | 172:65be27845400 | 58 | uint32_t NbSectors; /*!< Number of sectors to be erased. |
| AnnaBridge | 172:65be27845400 | 59 | This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/ |
| AnnaBridge | 172:65be27845400 | 60 | |
| AnnaBridge | 172:65be27845400 | 61 | uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism |
| AnnaBridge | 172:65be27845400 | 62 | This parameter must be a value of @ref FLASHEx_Voltage_Range */ |
| AnnaBridge | 172:65be27845400 | 63 | |
| AnnaBridge | 172:65be27845400 | 64 | } FLASH_EraseInitTypeDef; |
| AnnaBridge | 172:65be27845400 | 65 | |
| AnnaBridge | 172:65be27845400 | 66 | |
| AnnaBridge | 172:65be27845400 | 67 | /** |
| AnnaBridge | 172:65be27845400 | 68 | * @brief FLASH Option Bytes Program structure definition |
| AnnaBridge | 172:65be27845400 | 69 | */ |
| AnnaBridge | 172:65be27845400 | 70 | typedef struct |
| AnnaBridge | 172:65be27845400 | 71 | { |
| AnnaBridge | 172:65be27845400 | 72 | uint32_t OptionType; /*!< Option byte to be configured. |
| AnnaBridge | 172:65be27845400 | 73 | This parameter can be a value of @ref FLASHEx_Option_Type */ |
| AnnaBridge | 172:65be27845400 | 74 | |
| AnnaBridge | 172:65be27845400 | 75 | uint32_t WRPState; /*!< Write protection activation or deactivation. |
| AnnaBridge | 172:65be27845400 | 76 | This parameter can be a value of @ref FLASHEx_WRP_State */ |
| AnnaBridge | 172:65be27845400 | 77 | |
| AnnaBridge | 172:65be27845400 | 78 | uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected. |
| AnnaBridge | 172:65be27845400 | 79 | The value of this parameter depend on device used within the same series */ |
| AnnaBridge | 172:65be27845400 | 80 | |
| AnnaBridge | 172:65be27845400 | 81 | uint32_t RDPLevel; /*!< Set the read protection level. |
| AnnaBridge | 172:65be27845400 | 82 | This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */ |
| AnnaBridge | 172:65be27845400 | 83 | |
| AnnaBridge | 172:65be27845400 | 84 | uint32_t BORLevel; /*!< Set the BOR Level. |
| AnnaBridge | 172:65be27845400 | 85 | This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */ |
| AnnaBridge | 172:65be27845400 | 86 | |
| AnnaBridge | 172:65be27845400 | 87 | uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). |
| AnnaBridge | 172:65be27845400 | 88 | This parameter can be a combination of @ref FLASHEx_OB_USER_Type */ |
| AnnaBridge | 172:65be27845400 | 89 | |
| AnnaBridge | 172:65be27845400 | 90 | uint32_t USERConfig; /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY / |
| AnnaBridge | 172:65be27845400 | 91 | IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / IO_HSLV / SWAP_BANK_OPT */ |
| AnnaBridge | 172:65be27845400 | 92 | |
| AnnaBridge | 172:65be27845400 | 93 | uint32_t Banks; /*!< Select banks for WRP , PCROP and secure area config . |
| AnnaBridge | 172:65be27845400 | 94 | This parameter must be a value of @ref FLASHEx_Banks */ |
| AnnaBridge | 172:65be27845400 | 95 | |
| AnnaBridge | 172:65be27845400 | 96 | uint32_t PCROPConfig; /*!< specifies if the PCROP area shall be erased or not |
| AnnaBridge | 172:65be27845400 | 97 | when RDP level decreased from Level 1 to Level 0 or during a mass erase. |
| AnnaBridge | 172:65be27845400 | 98 | This parameter must be a value of @ref FLASHEx_OB_PCROP_RDP enumeration */ |
| AnnaBridge | 172:65be27845400 | 99 | |
| AnnaBridge | 172:65be27845400 | 100 | uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP). |
| AnnaBridge | 172:65be27845400 | 101 | This parameter must be a value between begin and end of a bank */ |
| AnnaBridge | 172:65be27845400 | 102 | |
| AnnaBridge | 172:65be27845400 | 103 | uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). |
| AnnaBridge | 172:65be27845400 | 104 | This parameter must be a value between PCROP Start address and end of a bank */ |
| AnnaBridge | 172:65be27845400 | 105 | |
| AnnaBridge | 172:65be27845400 | 106 | uint32_t BootConfig; /*!< Specifies if the Boot Address to be configured BOOT_ADD0, BOOT_ADD1 |
| AnnaBridge | 172:65be27845400 | 107 | or both. This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */ |
| AnnaBridge | 172:65be27845400 | 108 | |
| AnnaBridge | 172:65be27845400 | 109 | uint32_t BootAddr0; /*!< Boot Address 0. |
| AnnaBridge | 172:65be27845400 | 110 | This parameter must be a value between begin and end of a bank */ |
| AnnaBridge | 172:65be27845400 | 111 | |
| AnnaBridge | 172:65be27845400 | 112 | uint32_t BootAddr1; /*!< Boot Address 1. |
| AnnaBridge | 172:65be27845400 | 113 | This parameter must be a value between begin and end of a bank */ |
| AnnaBridge | 172:65be27845400 | 114 | |
| AnnaBridge | 172:65be27845400 | 115 | uint32_t SecureAreaConfig; /*!< specifies if the bank secured area shall be erased or not |
| AnnaBridge | 172:65be27845400 | 116 | when RDP level decreased from Level 1 to Level 0 or during a mass erase. |
| AnnaBridge | 172:65be27845400 | 117 | This parameter must be a value of @ref FLASHEx_OB_SECURE_RDP enumeration */ |
| AnnaBridge | 172:65be27845400 | 118 | |
| AnnaBridge | 172:65be27845400 | 119 | uint32_t SecureAreaStartAddr; /*!< Bank Secure area Start address. |
| AnnaBridge | 172:65be27845400 | 120 | This parameter must be a value between begin address and end address of bank1 */ |
| AnnaBridge | 172:65be27845400 | 121 | |
| AnnaBridge | 172:65be27845400 | 122 | uint32_t SecureAreaEndAddr; /*!< Bank Secure area End address . |
| AnnaBridge | 172:65be27845400 | 123 | This parameter must be a value between Secure Area Start address and end address of a bank1 */ |
| AnnaBridge | 172:65be27845400 | 124 | |
| AnnaBridge | 172:65be27845400 | 125 | } FLASH_OBProgramInitTypeDef; |
| AnnaBridge | 172:65be27845400 | 126 | |
| AnnaBridge | 172:65be27845400 | 127 | /** |
| AnnaBridge | 172:65be27845400 | 128 | * @brief FLASH Erase structure definition |
| AnnaBridge | 172:65be27845400 | 129 | */ |
| AnnaBridge | 172:65be27845400 | 130 | typedef struct |
| AnnaBridge | 172:65be27845400 | 131 | { |
| AnnaBridge | 172:65be27845400 | 132 | uint32_t TypeCRC; /*!< CRC Selection Type. |
| AnnaBridge | 172:65be27845400 | 133 | This parameter can be a value of @ref FLASHEx_CRC_Selection_Type */ |
| AnnaBridge | 172:65be27845400 | 134 | |
| AnnaBridge | 172:65be27845400 | 135 | uint32_t BurstSize; /*!< CRC Burst Size. |
| AnnaBridge | 172:65be27845400 | 136 | This parameter can be a value of @ref FLASHEx_CRC_Burst_Size */ |
| AnnaBridge | 172:65be27845400 | 137 | |
| AnnaBridge | 172:65be27845400 | 138 | uint32_t Bank; /*!< Select bank where CRC computation is enabled. |
| AnnaBridge | 172:65be27845400 | 139 | This parameter must be FLASH_BANK_1 or FLASH_BANK_2 */ |
| AnnaBridge | 172:65be27845400 | 140 | |
| AnnaBridge | 172:65be27845400 | 141 | uint32_t Sector; /*!< Initial FLASH sector from which starts the CRC computation |
| AnnaBridge | 172:65be27845400 | 142 | This parameter must be a value of @ref FLASH_Sectors */ |
| AnnaBridge | 172:65be27845400 | 143 | |
| AnnaBridge | 172:65be27845400 | 144 | uint32_t NbSectors; /*!< Number of sectors to be computed. |
| AnnaBridge | 172:65be27845400 | 145 | This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/ |
| AnnaBridge | 172:65be27845400 | 146 | |
| AnnaBridge | 172:65be27845400 | 147 | uint32_t CRCStartAddr; /*!< CRC Start address. |
| AnnaBridge | 172:65be27845400 | 148 | This parameter must be a value between begin address and end address of a bank */ |
| AnnaBridge | 172:65be27845400 | 149 | |
| AnnaBridge | 172:65be27845400 | 150 | uint32_t CRCEndAddr; /*!< CRC End address. |
| AnnaBridge | 172:65be27845400 | 151 | This parameter must be a value between CRC Start address and end address of a bank */ |
| AnnaBridge | 172:65be27845400 | 152 | |
| AnnaBridge | 172:65be27845400 | 153 | } FLASH_CRCInitTypeDef; |
| AnnaBridge | 172:65be27845400 | 154 | |
| AnnaBridge | 172:65be27845400 | 155 | /** |
| AnnaBridge | 172:65be27845400 | 156 | * @} |
| AnnaBridge | 172:65be27845400 | 157 | */ |
| AnnaBridge | 172:65be27845400 | 158 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 159 | |
| AnnaBridge | 172:65be27845400 | 160 | /** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants |
| AnnaBridge | 172:65be27845400 | 161 | * @{ |
| AnnaBridge | 172:65be27845400 | 162 | */ |
| AnnaBridge | 172:65be27845400 | 163 | |
| AnnaBridge | 172:65be27845400 | 164 | /** @defgroup FLASHEx_Type_Erase FLASH Type Erase |
| AnnaBridge | 172:65be27845400 | 165 | * @{ |
| AnnaBridge | 172:65be27845400 | 166 | */ |
| AnnaBridge | 172:65be27845400 | 167 | #define FLASH_TYPEERASE_SECTORS 0x00U /*!< Sectors erase only */ |
| AnnaBridge | 172:65be27845400 | 168 | #define FLASH_TYPEERASE_MASSERASE 0x01U /*!< Flash Mass erase activation */ |
| AnnaBridge | 172:65be27845400 | 169 | /** |
| AnnaBridge | 172:65be27845400 | 170 | * @} |
| AnnaBridge | 172:65be27845400 | 171 | */ |
| AnnaBridge | 172:65be27845400 | 172 | |
| AnnaBridge | 172:65be27845400 | 173 | /** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range |
| AnnaBridge | 172:65be27845400 | 174 | * @{ |
| AnnaBridge | 172:65be27845400 | 175 | */ |
| AnnaBridge | 172:65be27845400 | 176 | #define FLASH_VOLTAGE_RANGE_1 0x00000000U /*!< Flash program/erase by 8 bits */ |
| AnnaBridge | 172:65be27845400 | 177 | #define FLASH_VOLTAGE_RANGE_2 FLASH_CR_PSIZE_0 /*!< Flash program/erase by 16 bits */ |
| AnnaBridge | 172:65be27845400 | 178 | #define FLASH_VOLTAGE_RANGE_3 FLASH_CR_PSIZE_1 /*!< Flash program/erase by 32 bits */ |
| AnnaBridge | 172:65be27845400 | 179 | #define FLASH_VOLTAGE_RANGE_4 FLASH_CR_PSIZE /*!< Flash program/erase by 64 bits */ |
| AnnaBridge | 172:65be27845400 | 180 | /** |
| AnnaBridge | 172:65be27845400 | 181 | * @} |
| AnnaBridge | 172:65be27845400 | 182 | */ |
| AnnaBridge | 172:65be27845400 | 183 | |
| AnnaBridge | 172:65be27845400 | 184 | /** @defgroup FLASHEx_WRP_State FLASH WRP State |
| AnnaBridge | 172:65be27845400 | 185 | * @{ |
| AnnaBridge | 172:65be27845400 | 186 | */ |
| AnnaBridge | 172:65be27845400 | 187 | #define OB_WRPSTATE_DISABLE 0x00000000U /*!< Disable the write protection of the desired bank 1 sectors */ |
| AnnaBridge | 172:65be27845400 | 188 | #define OB_WRPSTATE_ENABLE 0x00000001U /*!< Enable the write protection of the desired bank 1 sectors */ |
| AnnaBridge | 172:65be27845400 | 189 | /** |
| AnnaBridge | 172:65be27845400 | 190 | * @} |
| AnnaBridge | 172:65be27845400 | 191 | */ |
| AnnaBridge | 172:65be27845400 | 192 | |
| AnnaBridge | 172:65be27845400 | 193 | /** @defgroup FLASHEx_Option_Type FLASH Option Type |
| AnnaBridge | 172:65be27845400 | 194 | * @{ |
| AnnaBridge | 172:65be27845400 | 195 | */ |
| AnnaBridge | 172:65be27845400 | 196 | #define OPTIONBYTE_WRP 0x01U /*!< WRP option byte configuration */ |
| AnnaBridge | 172:65be27845400 | 197 | #define OPTIONBYTE_RDP 0x02U /*!< RDP option byte configuration */ |
| AnnaBridge | 172:65be27845400 | 198 | #define OPTIONBYTE_USER 0x04U /*!< USER option byte configuration */ |
| AnnaBridge | 172:65be27845400 | 199 | #define OPTIONBYTE_PCROP 0x08U /*!< PCROP option byte configuration */ |
| AnnaBridge | 172:65be27845400 | 200 | #define OPTIONBYTE_BOR 0x10U /*!< BOR option byte configuration */ |
| AnnaBridge | 172:65be27845400 | 201 | #define OPTIONBYTE_SECURE_AREA 0x20U /*!< secure area option byte configuration */ |
| AnnaBridge | 172:65be27845400 | 202 | #define OPTIONBYTE_BOOTADD 0x40U /*!< BOOT ADD option byte configuration */ |
| AnnaBridge | 172:65be27845400 | 203 | /** |
| AnnaBridge | 172:65be27845400 | 204 | * @} |
| AnnaBridge | 172:65be27845400 | 205 | */ |
| AnnaBridge | 172:65be27845400 | 206 | |
| AnnaBridge | 172:65be27845400 | 207 | /** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection |
| AnnaBridge | 172:65be27845400 | 208 | * @{ |
| AnnaBridge | 172:65be27845400 | 209 | */ |
| AnnaBridge | 172:65be27845400 | 210 | #define OB_RDP_LEVEL_0 0xAA00U |
| AnnaBridge | 172:65be27845400 | 211 | #define OB_RDP_LEVEL_1 0x5500U |
| AnnaBridge | 172:65be27845400 | 212 | #define OB_RDP_LEVEL_2 0xCC00U /*!< Warning: When enabling read protection level 2 |
| AnnaBridge | 172:65be27845400 | 213 | it s no more possible to go back to level 1 or 0 */ |
| AnnaBridge | 172:65be27845400 | 214 | /** |
| AnnaBridge | 172:65be27845400 | 215 | * @} |
| AnnaBridge | 172:65be27845400 | 216 | */ |
| AnnaBridge | 172:65be27845400 | 217 | |
| AnnaBridge | 172:65be27845400 | 218 | /** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog |
| AnnaBridge | 172:65be27845400 | 219 | * @{ |
| AnnaBridge | 172:65be27845400 | 220 | */ |
| AnnaBridge | 172:65be27845400 | 221 | #define OB_WWDG_SW 0x10U /*!< Software WWDG selected */ |
| AnnaBridge | 172:65be27845400 | 222 | #define OB_WWDG_HW 0x00U /*!< Hardware WWDG selected */ |
| AnnaBridge | 172:65be27845400 | 223 | /** |
| AnnaBridge | 172:65be27845400 | 224 | * @} |
| AnnaBridge | 172:65be27845400 | 225 | */ |
| AnnaBridge | 172:65be27845400 | 226 | |
| AnnaBridge | 172:65be27845400 | 227 | |
| AnnaBridge | 172:65be27845400 | 228 | /** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog |
| AnnaBridge | 172:65be27845400 | 229 | * @{ |
| AnnaBridge | 172:65be27845400 | 230 | */ |
| AnnaBridge | 172:65be27845400 | 231 | #define OB_IWDG_SW 0x20U /*!< Software IWDG selected */ |
| AnnaBridge | 172:65be27845400 | 232 | #define OB_IWDG_HW 0x00U /*!< Hardware IWDG selected */ |
| AnnaBridge | 172:65be27845400 | 233 | /** |
| AnnaBridge | 172:65be27845400 | 234 | * @} |
| AnnaBridge | 172:65be27845400 | 235 | */ |
| AnnaBridge | 172:65be27845400 | 236 | |
| AnnaBridge | 172:65be27845400 | 237 | /** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP |
| AnnaBridge | 172:65be27845400 | 238 | * @{ |
| AnnaBridge | 172:65be27845400 | 239 | */ |
| AnnaBridge | 172:65be27845400 | 240 | #define OB_STOP_NO_RST 0x40U /*!< No reset generated when entering in STOP */ |
| AnnaBridge | 172:65be27845400 | 241 | #define OB_STOP_RST 0x00U /*!< Reset generated when entering in STOP */ |
| AnnaBridge | 172:65be27845400 | 242 | /** |
| AnnaBridge | 172:65be27845400 | 243 | * @} |
| AnnaBridge | 172:65be27845400 | 244 | */ |
| AnnaBridge | 172:65be27845400 | 245 | |
| AnnaBridge | 172:65be27845400 | 246 | /** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY |
| AnnaBridge | 172:65be27845400 | 247 | * @{ |
| AnnaBridge | 172:65be27845400 | 248 | */ |
| AnnaBridge | 172:65be27845400 | 249 | #define OB_STDBY_NO_RST 0x80U /*!< No reset generated when entering in STANDBY */ |
| AnnaBridge | 172:65be27845400 | 250 | #define OB_STDBY_RST 0x00U /*!< Reset generated when entering in STANDBY */ |
| AnnaBridge | 172:65be27845400 | 251 | /** |
| AnnaBridge | 172:65be27845400 | 252 | * @} |
| AnnaBridge | 172:65be27845400 | 253 | */ |
| AnnaBridge | 172:65be27845400 | 254 | |
| AnnaBridge | 172:65be27845400 | 255 | /** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP |
| AnnaBridge | 172:65be27845400 | 256 | * @{ |
| AnnaBridge | 172:65be27845400 | 257 | */ |
| AnnaBridge | 172:65be27845400 | 258 | #define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Freeze IWDG counter in STOP mode */ |
| AnnaBridge | 172:65be27845400 | 259 | #define OB_IWDG_STOP_ACTIVE FLASH_OPTSR_FZ_IWDG_STOP /*!< IWDG counter active in STOP mode */ |
| AnnaBridge | 172:65be27845400 | 260 | /** |
| AnnaBridge | 172:65be27845400 | 261 | * @} |
| AnnaBridge | 172:65be27845400 | 262 | */ |
| AnnaBridge | 172:65be27845400 | 263 | |
| AnnaBridge | 172:65be27845400 | 264 | /** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY |
| AnnaBridge | 172:65be27845400 | 265 | * @{ |
| AnnaBridge | 172:65be27845400 | 266 | */ |
| AnnaBridge | 172:65be27845400 | 267 | #define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Freeze IWDG counter in STANDBY mode */ |
| AnnaBridge | 172:65be27845400 | 268 | #define OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_FZ_IWDG_SDBY /*!< IWDG counter active in STANDBY mode */ |
| AnnaBridge | 172:65be27845400 | 269 | /** |
| AnnaBridge | 172:65be27845400 | 270 | * @} |
| AnnaBridge | 172:65be27845400 | 271 | */ |
| AnnaBridge | 172:65be27845400 | 272 | |
| AnnaBridge | 172:65be27845400 | 273 | /** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level |
| AnnaBridge | 172:65be27845400 | 274 | * @{ |
| AnnaBridge | 172:65be27845400 | 275 | */ |
| AnnaBridge | 172:65be27845400 | 276 | #define OB_BOR_LEVEL0 0x00000000U /*!< Reset level threshold is set to 1.6V */ |
| AnnaBridge | 172:65be27845400 | 277 | #define OB_BOR_LEVEL1 FLASH_OPTSR_BOR_LEV_0 /*!< Reset level threshold is set to 2.1V */ |
| AnnaBridge | 172:65be27845400 | 278 | #define OB_BOR_LEVEL2 FLASH_OPTSR_BOR_LEV_1 /*!< Reset level threshold is set to 2.4V */ |
| AnnaBridge | 172:65be27845400 | 279 | #define OB_BOR_LEVEL3 (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0) /*!< Reset level threshold is set to 2.7V */ |
| AnnaBridge | 172:65be27845400 | 280 | /** |
| AnnaBridge | 172:65be27845400 | 281 | * @} |
| AnnaBridge | 172:65be27845400 | 282 | */ |
| AnnaBridge | 172:65be27845400 | 283 | |
| AnnaBridge | 172:65be27845400 | 284 | |
| AnnaBridge | 172:65be27845400 | 285 | |
| AnnaBridge | 172:65be27845400 | 286 | /** @defgroup FLASHEx_Boot_Address FLASH Boot Address |
| AnnaBridge | 172:65be27845400 | 287 | * @{ |
| AnnaBridge | 172:65be27845400 | 288 | */ |
| AnnaBridge | 172:65be27845400 | 289 | #define OB_BOOTADDR_ITCM_RAM 0x0000U /*!< Boot from ITCM RAM (0x00000000) */ |
| AnnaBridge | 172:65be27845400 | 290 | #define OB_BOOTADDR_SYSTEM 0x0040U /*!< Boot from System memory bootloader (0x00100000) */ |
| AnnaBridge | 172:65be27845400 | 291 | #define OB_BOOTADDR_ITCM_FLASH 0x0080U /*!< Boot from Flash on ITCM interface (0x00200000) */ |
| AnnaBridge | 172:65be27845400 | 292 | #define OB_BOOTADDR_AXIM_FLASH 0x2000U /*!< Boot from Flash on AXIM interface (0x08000000) */ |
| AnnaBridge | 172:65be27845400 | 293 | #define OB_BOOTADDR_DTCM_RAM 0x8000U /*!< Boot from DTCM RAM (0x20000000) */ |
| AnnaBridge | 172:65be27845400 | 294 | #define OB_BOOTADDR_SRAM1 0x8004U /*!< Boot from SRAM1 (0x20010000) */ |
| AnnaBridge | 172:65be27845400 | 295 | #define OB_BOOTADDR_SRAM2 0x8013U /*!< Boot from SRAM2 (0x2004C000) */ |
| AnnaBridge | 172:65be27845400 | 296 | /** |
| AnnaBridge | 172:65be27845400 | 297 | * @} |
| AnnaBridge | 172:65be27845400 | 298 | */ |
| AnnaBridge | 172:65be27845400 | 299 | |
| AnnaBridge | 172:65be27845400 | 300 | /** @defgroup FLASH_Latency FLASH Latency |
| AnnaBridge | 172:65be27845400 | 301 | * @{ |
| AnnaBridge | 172:65be27845400 | 302 | */ |
| AnnaBridge | 172:65be27845400 | 303 | #define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */ |
| AnnaBridge | 172:65be27845400 | 304 | #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */ |
| AnnaBridge | 172:65be27845400 | 305 | #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */ |
| AnnaBridge | 172:65be27845400 | 306 | #define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */ |
| AnnaBridge | 172:65be27845400 | 307 | #define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */ |
| AnnaBridge | 172:65be27845400 | 308 | #define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */ |
| AnnaBridge | 172:65be27845400 | 309 | #define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */ |
| AnnaBridge | 172:65be27845400 | 310 | #define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */ |
| AnnaBridge | 172:65be27845400 | 311 | #define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight Latency cycle */ |
| AnnaBridge | 172:65be27845400 | 312 | #define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine Latency cycle */ |
| AnnaBridge | 172:65be27845400 | 313 | #define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten Latency cycles */ |
| AnnaBridge | 172:65be27845400 | 314 | #define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven Latency cycles */ |
| AnnaBridge | 172:65be27845400 | 315 | #define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve Latency cycles */ |
| AnnaBridge | 172:65be27845400 | 316 | #define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen Latency cycles */ |
| AnnaBridge | 172:65be27845400 | 317 | #define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen Latency cycles */ |
| AnnaBridge | 172:65be27845400 | 318 | #define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen Latency cycles */ |
| AnnaBridge | 172:65be27845400 | 319 | /** |
| AnnaBridge | 172:65be27845400 | 320 | * @} |
| AnnaBridge | 172:65be27845400 | 321 | */ |
| AnnaBridge | 172:65be27845400 | 322 | |
| AnnaBridge | 172:65be27845400 | 323 | /** @defgroup FLASHEx_Banks FLASH Banks |
| AnnaBridge | 172:65be27845400 | 324 | * @{ |
| AnnaBridge | 172:65be27845400 | 325 | */ |
| AnnaBridge | 172:65be27845400 | 326 | #define FLASH_BANK_1 0x01U /*!< Bank 1 */ |
| AnnaBridge | 172:65be27845400 | 327 | #define FLASH_BANK_2 0x02U /*!< Bank 2 */ |
| AnnaBridge | 172:65be27845400 | 328 | #define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */ |
| AnnaBridge | 172:65be27845400 | 329 | /** |
| AnnaBridge | 172:65be27845400 | 330 | * @} |
| AnnaBridge | 172:65be27845400 | 331 | */ |
| AnnaBridge | 172:65be27845400 | 332 | |
| AnnaBridge | 172:65be27845400 | 333 | /** @defgroup FLASHEx_OB_PCROP_RDP FLASHEx OB PCROP RDP |
| AnnaBridge | 172:65be27845400 | 334 | * @{ |
| AnnaBridge | 172:65be27845400 | 335 | */ |
| AnnaBridge | 172:65be27845400 | 336 | #define OB_PCROP_RDP_NOT_ERASE 0x00000000U /*!< PCROP area is not erased when the RDP level |
| AnnaBridge | 172:65be27845400 | 337 | is decreased from Level 1 to Level 0 or during a mass erase */ |
| AnnaBridge | 172:65be27845400 | 338 | #define OB_PCROP_RDP_ERASE FLASH_PRAR_DMEP /*!< PCROP area is erased when the RDP level is |
| AnnaBridge | 172:65be27845400 | 339 | decreased from Level 1 to Level 0 (full mass erase) */ |
| AnnaBridge | 172:65be27845400 | 340 | |
| AnnaBridge | 172:65be27845400 | 341 | /** |
| AnnaBridge | 172:65be27845400 | 342 | * @} |
| AnnaBridge | 172:65be27845400 | 343 | */ |
| AnnaBridge | 172:65be27845400 | 344 | |
| AnnaBridge | 172:65be27845400 | 345 | /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection |
| AnnaBridge | 172:65be27845400 | 346 | * @{ |
| AnnaBridge | 172:65be27845400 | 347 | */ |
| AnnaBridge | 172:65be27845400 | 348 | #define OB_WRP_SECTOR_0 0x00000001U /*!< Write protection of Sector0 */ |
| AnnaBridge | 172:65be27845400 | 349 | #define OB_WRP_SECTOR_1 0x00000002U /*!< Write protection of Sector1 */ |
| AnnaBridge | 172:65be27845400 | 350 | #define OB_WRP_SECTOR_2 0x00000004U /*!< Write protection of Sector2 */ |
| AnnaBridge | 172:65be27845400 | 351 | #define OB_WRP_SECTOR_3 0x00000008U /*!< Write protection of Sector3 */ |
| AnnaBridge | 172:65be27845400 | 352 | #define OB_WRP_SECTOR_4 0x00000010U /*!< Write protection of Sector4 */ |
| AnnaBridge | 172:65be27845400 | 353 | #define OB_WRP_SECTOR_5 0x00000020U /*!< Write protection of Sector5 */ |
| AnnaBridge | 172:65be27845400 | 354 | #define OB_WRP_SECTOR_6 0x00000040U /*!< Write protection of Sector6 */ |
| AnnaBridge | 172:65be27845400 | 355 | #define OB_WRP_SECTOR_7 0x00000080U /*!< Write protection of Sector7 */ |
| AnnaBridge | 172:65be27845400 | 356 | #define OB_WRP_SECTOR_All 0x000000FFU /*!< Write protection of all Sectors */ |
| AnnaBridge | 172:65be27845400 | 357 | /** |
| AnnaBridge | 172:65be27845400 | 358 | * @} |
| AnnaBridge | 172:65be27845400 | 359 | */ |
| AnnaBridge | 172:65be27845400 | 360 | |
| AnnaBridge | 172:65be27845400 | 361 | /** @defgroup FLASHEx_OB_SECURITY FLASHEx OB SECURITY |
| AnnaBridge | 172:65be27845400 | 362 | * @{ |
| AnnaBridge | 172:65be27845400 | 363 | */ |
| AnnaBridge | 172:65be27845400 | 364 | #define OB_SECURITY_DISABLE 0x00000000U /*!< security enabled */ |
| AnnaBridge | 172:65be27845400 | 365 | #define OB_SECURITY_ENABLE FLASH_OPTSR_SECURITY /*!< security disabled */ |
| AnnaBridge | 172:65be27845400 | 366 | /** |
| AnnaBridge | 172:65be27845400 | 367 | * @} |
| AnnaBridge | 172:65be27845400 | 368 | */ |
| AnnaBridge | 172:65be27845400 | 369 | |
| AnnaBridge | 172:65be27845400 | 370 | /** @defgroup FLASHEx_OB_ST_RAM_SIZE FLASHEx OB ST RAM SIZE |
| AnnaBridge | 172:65be27845400 | 371 | * @{ |
| AnnaBridge | 172:65be27845400 | 372 | */ |
| AnnaBridge | 172:65be27845400 | 373 | #define OB_ST_RAM_SIZE_2KB 0x00000000U /*!< 2 Kbytes reserved to ST code */ |
| AnnaBridge | 172:65be27845400 | 374 | #define OB_ST_RAM_SIZE_4KB FLASH_OPTSR_ST_RAM_SIZE_0 /*!< 4 Kbytes reserved to ST code */ |
| AnnaBridge | 172:65be27845400 | 375 | #define OB_ST_RAM_SIZE_8KB FLASH_OPTSR_ST_RAM_SIZE_1 /*!< 8 Kbytes reserved to ST code */ |
| AnnaBridge | 172:65be27845400 | 376 | #define OB_ST_RAM_SIZE_16KB FLASH_OPTSR_ST_RAM_SIZE /*!< 16 Kbytes reserved to ST code */ |
| AnnaBridge | 172:65be27845400 | 377 | /** |
| AnnaBridge | 172:65be27845400 | 378 | * @} |
| AnnaBridge | 172:65be27845400 | 379 | */ |
| AnnaBridge | 172:65be27845400 | 380 | |
| AnnaBridge | 172:65be27845400 | 381 | |
| AnnaBridge | 172:65be27845400 | 382 | /** @defgroup FLASHEx_OB_IWDG1_SW FLASHEx OB IWDG1 SW |
| AnnaBridge | 172:65be27845400 | 383 | * @{ |
| AnnaBridge | 172:65be27845400 | 384 | */ |
| AnnaBridge | 172:65be27845400 | 385 | #define OB_IWDG1_SW FLASH_OPTSR_IWDG1_SW /*!< Hardware independent watchdog 1 */ |
| AnnaBridge | 172:65be27845400 | 386 | #define OB_IWDG1_HW 0x00000000U /*!< Software independent watchdog 1 */ |
| AnnaBridge | 172:65be27845400 | 387 | /** |
| AnnaBridge | 172:65be27845400 | 388 | * @} |
| AnnaBridge | 172:65be27845400 | 389 | */ |
| AnnaBridge | 172:65be27845400 | 390 | |
| AnnaBridge | 172:65be27845400 | 391 | |
| AnnaBridge | 172:65be27845400 | 392 | /** @defgroup FLASHEx_OB_NRST_STOP_D1 FLASHEx OB NRST STOP D1 |
| AnnaBridge | 172:65be27845400 | 393 | * @{ |
| AnnaBridge | 172:65be27845400 | 394 | */ |
| AnnaBridge | 172:65be27845400 | 395 | #define OB_STOP_RST_D1 0x00000000U /*!< Reset generated when entering the D1 to stop mode */ |
| AnnaBridge | 172:65be27845400 | 396 | #define OB_STOP_NO_RST_D1 FLASH_OPTSR_NRST_STOP_D1 /*!< No reset generated when entering the D1 to stop mode */ |
| AnnaBridge | 172:65be27845400 | 397 | /** |
| AnnaBridge | 172:65be27845400 | 398 | * @} |
| AnnaBridge | 172:65be27845400 | 399 | */ |
| AnnaBridge | 172:65be27845400 | 400 | |
| AnnaBridge | 172:65be27845400 | 401 | /** @defgroup FLASHEx_OB_NRST_STDBY_D1 FLASHEx OB NRST STDBY D1 |
| AnnaBridge | 172:65be27845400 | 402 | * @{ |
| AnnaBridge | 172:65be27845400 | 403 | */ |
| AnnaBridge | 172:65be27845400 | 404 | #define OB_STDBY_RST_D1 0x00000000U /*!< Reset generated when entering the D1 to standby mode */ |
| AnnaBridge | 172:65be27845400 | 405 | #define OB_STDBY_NO_RST_D1 FLASH_OPTSR_NRST_STBY_D1 /*!< No reset generated when entering the D1 to standby mode */ |
| AnnaBridge | 172:65be27845400 | 406 | /** |
| AnnaBridge | 172:65be27845400 | 407 | * @} |
| AnnaBridge | 172:65be27845400 | 408 | */ |
| AnnaBridge | 172:65be27845400 | 409 | |
| AnnaBridge | 172:65be27845400 | 410 | |
| AnnaBridge | 172:65be27845400 | 411 | /** @defgroup FLASHEx_OB_SWAP_BANK FLASHEx OB SWAP BANK |
| AnnaBridge | 172:65be27845400 | 412 | * @{ |
| AnnaBridge | 172:65be27845400 | 413 | */ |
| AnnaBridge | 172:65be27845400 | 414 | #define OB_SWAP_BANK_DISABLE 0x00000000U /*!< Bank swap disabled */ |
| AnnaBridge | 172:65be27845400 | 415 | #define OB_SWAP_BANK_ENABLE FLASH_OPTSR_SWAP_BANK_OPT /*!< Bank swap enabled */ |
| AnnaBridge | 172:65be27845400 | 416 | /** |
| AnnaBridge | 172:65be27845400 | 417 | * @} |
| AnnaBridge | 172:65be27845400 | 418 | */ |
| AnnaBridge | 172:65be27845400 | 419 | |
| AnnaBridge | 172:65be27845400 | 420 | /** @defgroup FLASHEx_OB_IOHSLV FLASHEx OB IOHSLV |
| AnnaBridge | 172:65be27845400 | 421 | * @{ |
| AnnaBridge | 172:65be27845400 | 422 | */ |
| AnnaBridge | 172:65be27845400 | 423 | #define OB_IOHSLV_DISABLE 0x00000000U /*!< IOHSLV disabled */ |
| AnnaBridge | 172:65be27845400 | 424 | #define OB_IOHSLV_ENABLE FLASH_OPTSR_IO_HSLV /*!< IOHSLV enabled */ |
| AnnaBridge | 172:65be27845400 | 425 | /** |
| AnnaBridge | 172:65be27845400 | 426 | * @} |
| AnnaBridge | 172:65be27845400 | 427 | */ |
| AnnaBridge | 172:65be27845400 | 428 | |
| AnnaBridge | 172:65be27845400 | 429 | /** @defgroup FLASHEx_OB_BOOT_OPTION FLASHEx OB BOOT OPTION |
| AnnaBridge | 172:65be27845400 | 430 | * @{ |
| AnnaBridge | 172:65be27845400 | 431 | */ |
| AnnaBridge | 172:65be27845400 | 432 | #define OB_BOOT_ADD0 0x01U /*!< Select Boot Address 0 */ |
| AnnaBridge | 172:65be27845400 | 433 | #define OB_BOOT_ADD1 0x02U /*!< Select Boot Address 1 */ |
| AnnaBridge | 172:65be27845400 | 434 | #define OB_BOOT_ADD_BOTH 0x03U /*!< Select Boot Address 0 and 1 */ |
| AnnaBridge | 172:65be27845400 | 435 | /** |
| AnnaBridge | 172:65be27845400 | 436 | * @} |
| AnnaBridge | 172:65be27845400 | 437 | */ |
| AnnaBridge | 172:65be27845400 | 438 | |
| AnnaBridge | 172:65be27845400 | 439 | /** @defgroup FLASHEx_OB_USER_Type FLASHEx OB USER Type |
| AnnaBridge | 172:65be27845400 | 440 | * @{ |
| AnnaBridge | 172:65be27845400 | 441 | */ |
| AnnaBridge | 172:65be27845400 | 442 | #define OB_USER_IWDG1_SW 0x0001U /*!< Independent watchdog selection */ |
| AnnaBridge | 172:65be27845400 | 443 | #define OB_USER_NRST_STOP_D1 0x0002U /*!< Reset when entering Stop mode selection*/ |
| AnnaBridge | 172:65be27845400 | 444 | #define OB_USER_NRST_STDBY_D1 0x0004U /*!< Reset when entering standby mode selection*/ |
| AnnaBridge | 172:65be27845400 | 445 | #define OB_USER_IWDG_STOP 0x0008U /*!< Independent watchdog counter freeze in stop mode */ |
| AnnaBridge | 172:65be27845400 | 446 | #define OB_USER_IWDG_STDBY 0x0010U /*!< Independent watchdog counter freeze in standby mode */ |
| AnnaBridge | 172:65be27845400 | 447 | #define OB_USER_ST_RAM_SIZE 0x0020U /*!< dedicated DTCM Ram size selection */ |
| AnnaBridge | 172:65be27845400 | 448 | #define OB_USER_SECURITY 0x0040U /*!< security selection */ |
| AnnaBridge | 172:65be27845400 | 449 | #define OB_USER_IOHSLV 0x0080U /*!< IO HSLV selection */ |
| AnnaBridge | 172:65be27845400 | 450 | #define OB_USER_SWAP_BANK 0x0100U /*!< Bank swap selection */ |
| AnnaBridge | 172:65be27845400 | 451 | |
| AnnaBridge | 172:65be27845400 | 452 | /** |
| AnnaBridge | 172:65be27845400 | 453 | * @} |
| AnnaBridge | 172:65be27845400 | 454 | */ |
| AnnaBridge | 172:65be27845400 | 455 | |
| AnnaBridge | 172:65be27845400 | 456 | /** @defgroup FLASHEx_OB_SECURE_RDP FLASHEx OB SECURE RDP |
| AnnaBridge | 172:65be27845400 | 457 | * @{ |
| AnnaBridge | 172:65be27845400 | 458 | */ |
| AnnaBridge | 172:65be27845400 | 459 | #define OB_SECURE_RDP_NOT_ERASE 0x00000000U /*!< Secure area is not erased when the RDP level |
| AnnaBridge | 172:65be27845400 | 460 | is decreased from Level 1 to Level 0 or during a mass erase */ |
| AnnaBridge | 172:65be27845400 | 461 | #define OB_SECURE_RDP_ERASE FLASH_SCAR_DMES /*!< Secure area is erased when the RDP level is |
| AnnaBridge | 172:65be27845400 | 462 | decreased from Level 1 to Level 0 (full mass erase) */ |
| AnnaBridge | 172:65be27845400 | 463 | |
| AnnaBridge | 172:65be27845400 | 464 | /** |
| AnnaBridge | 172:65be27845400 | 465 | * @} |
| AnnaBridge | 172:65be27845400 | 466 | */ |
| AnnaBridge | 172:65be27845400 | 467 | |
| AnnaBridge | 172:65be27845400 | 468 | /** @defgroup FLASHEx_CRC_Selection_Type FLASH CRC Selection Type |
| AnnaBridge | 172:65be27845400 | 469 | * @{ |
| AnnaBridge | 172:65be27845400 | 470 | */ |
| AnnaBridge | 172:65be27845400 | 471 | #define FLASH_CRC_ADDR 0x00000000U /*!< CRC selection type by address */ |
| AnnaBridge | 172:65be27845400 | 472 | #define FLASH_CRC_SECTORS FLASH_CRCCR_CRC_BY_SECT /*!< CRC selection type by sectors */ |
| AnnaBridge | 172:65be27845400 | 473 | #define FLASH_CRC_BANK (FLASH_CRCCR_ALL_BANK | FLASH_CRCCR_CRC_BY_SECT) /*!< CRC selection type by bank */ |
| AnnaBridge | 172:65be27845400 | 474 | /** |
| AnnaBridge | 172:65be27845400 | 475 | * @} |
| AnnaBridge | 172:65be27845400 | 476 | */ |
| AnnaBridge | 172:65be27845400 | 477 | |
| AnnaBridge | 172:65be27845400 | 478 | /** @defgroup FLASHEx_CRC_Burst_Size FLASH CRC Burst Size |
| AnnaBridge | 172:65be27845400 | 479 | * @{ |
| AnnaBridge | 172:65be27845400 | 480 | */ |
| AnnaBridge | 172:65be27845400 | 481 | #define FLASH_CRC_BURST_SIZE_4 0x00000000U /*!< Every burst has a size of 4 Flash words (256-bit) */ |
| AnnaBridge | 172:65be27845400 | 482 | #define FLASH_CRC_BURST_SIZE_16 FLASH_CRCCR_CRC_BURST_0 /*!< Every burst has a size of 16 Flash words (256-bit) */ |
| AnnaBridge | 172:65be27845400 | 483 | #define FLASH_CRC_BURST_SIZE_64 FLASH_CRCCR_CRC_BURST_1 /*!< Every burst has a size of 64 Flash words (256-bit) */ |
| AnnaBridge | 172:65be27845400 | 484 | #define FLASH_CRC_BURST_SIZE_256 FLASH_CRCCR_CRC_BURST /*!< Every burst has a size of 256 Flash words (256-bit) */ |
| AnnaBridge | 172:65be27845400 | 485 | /** |
| AnnaBridge | 172:65be27845400 | 486 | * @} |
| AnnaBridge | 172:65be27845400 | 487 | */ |
| AnnaBridge | 172:65be27845400 | 488 | |
| AnnaBridge | 172:65be27845400 | 489 | /** @defgroup FLASHEx_Programming_Delay FLASH Programming Delay |
| AnnaBridge | 172:65be27845400 | 490 | * @{ |
| AnnaBridge | 172:65be27845400 | 491 | */ |
| AnnaBridge | 172:65be27845400 | 492 | #define FLASH_PROGRAMMING_DELAY_0 0x00000000U /*!< programming delay set for Flash running at 70 MHz or below */ |
| AnnaBridge | 172:65be27845400 | 493 | #define FLASH_PROGRAMMING_DELAY_1 FLASH_ACR_WRHIGHFREQ_0 /*!< programming delay set for Flash running between 70 MHz and 185 MHz */ |
| AnnaBridge | 172:65be27845400 | 494 | #define FLASH_PROGRAMMING_DELAY_2 FLASH_ACR_WRHIGHFREQ_1 /*!< programming delay set for Flash running between 185 MHz and 225 MHz */ |
| AnnaBridge | 172:65be27845400 | 495 | #define FLASH_PROGRAMMING_DELAY_3 FLASH_ACR_WRHIGHFREQ /*!< programming delay set for Flash at startup */ |
| AnnaBridge | 172:65be27845400 | 496 | /** |
| AnnaBridge | 172:65be27845400 | 497 | * @} |
| AnnaBridge | 172:65be27845400 | 498 | */ |
| AnnaBridge | 172:65be27845400 | 499 | |
| AnnaBridge | 172:65be27845400 | 500 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 501 | /** @defgroup FLASHEx_Exported_Macros FLASH Exported Macros |
| AnnaBridge | 172:65be27845400 | 502 | * @{ |
| AnnaBridge | 172:65be27845400 | 503 | */ |
| AnnaBridge | 172:65be27845400 | 504 | /** |
| AnnaBridge | 172:65be27845400 | 505 | * @brief Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1) |
| AnnaBridge | 172:65be27845400 | 506 | * @note Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14]. |
| AnnaBridge | 172:65be27845400 | 507 | * @param __ADDRESS__: FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB) |
| AnnaBridge | 172:65be27845400 | 508 | * @retval The FLASH Boot Base Adress |
| AnnaBridge | 172:65be27845400 | 509 | */ |
| AnnaBridge | 172:65be27845400 | 510 | #define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14U) |
| AnnaBridge | 172:65be27845400 | 511 | /** |
| AnnaBridge | 172:65be27845400 | 512 | * @} |
| AnnaBridge | 172:65be27845400 | 513 | */ |
| AnnaBridge | 172:65be27845400 | 514 | |
| AnnaBridge | 172:65be27845400 | 515 | /** |
| AnnaBridge | 172:65be27845400 | 516 | * @brief Set the FLASH Program/Erase parallelism. |
| AnnaBridge | 172:65be27845400 | 517 | * @param __PSIZE__ FLASH Program/Erase parallelism |
| AnnaBridge | 172:65be27845400 | 518 | * This parameter can be a value of @ref FLASH_Program_Parallelism |
| AnnaBridge | 172:65be27845400 | 519 | * @param __BANK__: Flash bank (FLASH_BANK_1 or FLASH_BANK_2) |
| AnnaBridge | 172:65be27845400 | 520 | * @retval none |
| AnnaBridge | 172:65be27845400 | 521 | */ |
| AnnaBridge | 172:65be27845400 | 522 | #define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) (((__BANK__) == FLASH_BANK_1) ? \ |
| AnnaBridge | 172:65be27845400 | 523 | MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__)) : \ |
| AnnaBridge | 172:65be27845400 | 524 | MODIFY_REG(FLASH->CR2, FLASH_CR_PSIZE, (__PSIZE__))) |
| AnnaBridge | 172:65be27845400 | 525 | |
| AnnaBridge | 172:65be27845400 | 526 | /** |
| AnnaBridge | 172:65be27845400 | 527 | * @brief Get the FLASH Program/Erase parallelism. |
| AnnaBridge | 172:65be27845400 | 528 | * @param __BANK__ Flash bank (FLASH_BANK_1 or FLASH_BANK_2) |
| AnnaBridge | 172:65be27845400 | 529 | * @retval FLASH Program/Erase parallelism |
| AnnaBridge | 172:65be27845400 | 530 | * This return value can be a value of @ref FLASH_Program_Parallelism |
| AnnaBridge | 172:65be27845400 | 531 | */ |
| AnnaBridge | 172:65be27845400 | 532 | #define __HAL_FLASH_GET_PSIZE(__BANK__) (((__BANK__) == FLASH_BANK_1) ? \ |
| AnnaBridge | 172:65be27845400 | 533 | READ_BIT((FLASH->CR1), FLASH_CR_PSIZE) : \ |
| AnnaBridge | 172:65be27845400 | 534 | READ_BIT((FLASH->CR2), FLASH_CR_PSIZE)) |
| AnnaBridge | 172:65be27845400 | 535 | |
| AnnaBridge | 172:65be27845400 | 536 | /** |
| AnnaBridge | 172:65be27845400 | 537 | * @brief Set the FLASH Programming Delay. |
| AnnaBridge | 172:65be27845400 | 538 | * @param __DELAY__ FLASH Programming Delay |
| AnnaBridge | 172:65be27845400 | 539 | * This parameter can be a value of @ref FLASHEx_Programming_Delay |
| AnnaBridge | 172:65be27845400 | 540 | * @retval none |
| AnnaBridge | 172:65be27845400 | 541 | */ |
| AnnaBridge | 172:65be27845400 | 542 | #define __HAL_FLASH_SET_PROGRAM_DELAY(__DELAY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_WRHIGHFREQ, (__DELAY__)) |
| AnnaBridge | 172:65be27845400 | 543 | |
| AnnaBridge | 172:65be27845400 | 544 | /** |
| AnnaBridge | 172:65be27845400 | 545 | * @brief Get the FLASH Programming Delay. |
| AnnaBridge | 172:65be27845400 | 546 | * @retval FLASH Programming Delay |
| AnnaBridge | 172:65be27845400 | 547 | * This return value can be a value of @ref FLASHEx_Programming_Delay |
| AnnaBridge | 172:65be27845400 | 548 | */ |
| AnnaBridge | 172:65be27845400 | 549 | #define __HAL_FLASH_GET_PROGRAM_DELAY() READ_BIT(FLASH->ACR, FLASH_ACR_WRHIGHFREQ) |
| AnnaBridge | 172:65be27845400 | 550 | |
| AnnaBridge | 172:65be27845400 | 551 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 552 | /** @addtogroup FLASHEx_Exported_Functions |
| AnnaBridge | 172:65be27845400 | 553 | * @{ |
| AnnaBridge | 172:65be27845400 | 554 | */ |
| AnnaBridge | 172:65be27845400 | 555 | |
| AnnaBridge | 172:65be27845400 | 556 | /** @addtogroup FLASHEx_Exported_Functions_Group1 |
| AnnaBridge | 172:65be27845400 | 557 | * @{ |
| AnnaBridge | 172:65be27845400 | 558 | */ |
| AnnaBridge | 172:65be27845400 | 559 | /* Extension Program operation functions *************************************/ |
| AnnaBridge | 172:65be27845400 | 560 | HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError); |
| AnnaBridge | 172:65be27845400 | 561 | HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); |
| AnnaBridge | 172:65be27845400 | 562 | HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); |
| AnnaBridge | 172:65be27845400 | 563 | void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); |
| AnnaBridge | 172:65be27845400 | 564 | |
| AnnaBridge | 172:65be27845400 | 565 | HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void); |
| AnnaBridge | 172:65be27845400 | 566 | HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void); |
| AnnaBridge | 172:65be27845400 | 567 | HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void); |
| AnnaBridge | 172:65be27845400 | 568 | HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void); |
| AnnaBridge | 172:65be27845400 | 569 | |
| AnnaBridge | 172:65be27845400 | 570 | HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result); |
| AnnaBridge | 172:65be27845400 | 571 | |
| AnnaBridge | 172:65be27845400 | 572 | /** |
| AnnaBridge | 172:65be27845400 | 573 | * @} |
| AnnaBridge | 172:65be27845400 | 574 | */ |
| AnnaBridge | 172:65be27845400 | 575 | |
| AnnaBridge | 172:65be27845400 | 576 | /** |
| AnnaBridge | 172:65be27845400 | 577 | * @} |
| AnnaBridge | 172:65be27845400 | 578 | */ |
| AnnaBridge | 172:65be27845400 | 579 | /* Private types -------------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 580 | /* Private variables ---------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 581 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 582 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 583 | /** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros |
| AnnaBridge | 172:65be27845400 | 584 | * @{ |
| AnnaBridge | 172:65be27845400 | 585 | */ |
| AnnaBridge | 172:65be27845400 | 586 | |
| AnnaBridge | 172:65be27845400 | 587 | /** @defgroup FLASHEx_IS_FLASH_Definitions FLASHEx Private macros to check input parameters |
| AnnaBridge | 172:65be27845400 | 588 | * @{ |
| AnnaBridge | 172:65be27845400 | 589 | */ |
| AnnaBridge | 172:65be27845400 | 590 | |
| AnnaBridge | 172:65be27845400 | 591 | #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \ |
| AnnaBridge | 172:65be27845400 | 592 | ((VALUE) == FLASH_TYPEERASE_MASSERASE)) |
| AnnaBridge | 172:65be27845400 | 593 | |
| AnnaBridge | 172:65be27845400 | 594 | #define IS_VOLTAGERANGE(RANGE) (((RANGE) == FLASH_VOLTAGE_RANGE_1) || \ |
| AnnaBridge | 172:65be27845400 | 595 | ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \ |
| AnnaBridge | 172:65be27845400 | 596 | ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \ |
| AnnaBridge | 172:65be27845400 | 597 | ((RANGE) == FLASH_VOLTAGE_RANGE_4)) |
| AnnaBridge | 172:65be27845400 | 598 | |
| AnnaBridge | 172:65be27845400 | 599 | #define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \ |
| AnnaBridge | 172:65be27845400 | 600 | ((VALUE) == OB_WRPSTATE_ENABLE)) |
| AnnaBridge | 172:65be27845400 | 601 | |
| AnnaBridge | 172:65be27845400 | 602 | #define IS_OPTIONBYTE(VALUE) (((VALUE) <= 0x01FFU) && ((VALUE) != 0U)) |
| AnnaBridge | 172:65be27845400 | 603 | |
| AnnaBridge | 172:65be27845400 | 604 | #define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013U) |
| AnnaBridge | 172:65be27845400 | 605 | |
| AnnaBridge | 172:65be27845400 | 606 | #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ |
| AnnaBridge | 172:65be27845400 | 607 | ((LEVEL) == OB_RDP_LEVEL_1) ||\ |
| AnnaBridge | 172:65be27845400 | 608 | ((LEVEL) == OB_RDP_LEVEL_2)) |
| AnnaBridge | 172:65be27845400 | 609 | |
| AnnaBridge | 172:65be27845400 | 610 | #define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW)) |
| AnnaBridge | 172:65be27845400 | 611 | |
| AnnaBridge | 172:65be27845400 | 612 | #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) |
| AnnaBridge | 172:65be27845400 | 613 | |
| AnnaBridge | 172:65be27845400 | 614 | #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) |
| AnnaBridge | 172:65be27845400 | 615 | |
| AnnaBridge | 172:65be27845400 | 616 | #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)) |
| AnnaBridge | 172:65be27845400 | 617 | |
| AnnaBridge | 172:65be27845400 | 618 | #define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE)) |
| AnnaBridge | 172:65be27845400 | 619 | |
| AnnaBridge | 172:65be27845400 | 620 | #define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE)) |
| AnnaBridge | 172:65be27845400 | 621 | |
| AnnaBridge | 172:65be27845400 | 622 | #define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL0) || ((LEVEL) == OB_BOR_LEVEL1) || \ |
| AnnaBridge | 172:65be27845400 | 623 | ((LEVEL) == OB_BOR_LEVEL2) || ((LEVEL) == OB_BOR_LEVEL3)) |
| AnnaBridge | 172:65be27845400 | 624 | |
| AnnaBridge | 172:65be27845400 | 625 | #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \ |
| AnnaBridge | 172:65be27845400 | 626 | ((LATENCY) == FLASH_LATENCY_1) || \ |
| AnnaBridge | 172:65be27845400 | 627 | ((LATENCY) == FLASH_LATENCY_2) || \ |
| AnnaBridge | 172:65be27845400 | 628 | ((LATENCY) == FLASH_LATENCY_3) || \ |
| AnnaBridge | 172:65be27845400 | 629 | ((LATENCY) == FLASH_LATENCY_4) || \ |
| AnnaBridge | 172:65be27845400 | 630 | ((LATENCY) == FLASH_LATENCY_5) || \ |
| AnnaBridge | 172:65be27845400 | 631 | ((LATENCY) == FLASH_LATENCY_6) || \ |
| AnnaBridge | 172:65be27845400 | 632 | ((LATENCY) == FLASH_LATENCY_7) || \ |
| AnnaBridge | 172:65be27845400 | 633 | ((LATENCY) == FLASH_LATENCY_8) || \ |
| AnnaBridge | 172:65be27845400 | 634 | ((LATENCY) == FLASH_LATENCY_9) || \ |
| AnnaBridge | 172:65be27845400 | 635 | ((LATENCY) == FLASH_LATENCY_10) || \ |
| AnnaBridge | 172:65be27845400 | 636 | ((LATENCY) == FLASH_LATENCY_11) || \ |
| AnnaBridge | 172:65be27845400 | 637 | ((LATENCY) == FLASH_LATENCY_12) || \ |
| AnnaBridge | 172:65be27845400 | 638 | ((LATENCY) == FLASH_LATENCY_13) || \ |
| AnnaBridge | 172:65be27845400 | 639 | ((LATENCY) == FLASH_LATENCY_14) || \ |
| AnnaBridge | 172:65be27845400 | 640 | ((LATENCY) == FLASH_LATENCY_15)) |
| AnnaBridge | 172:65be27845400 | 641 | |
| AnnaBridge | 172:65be27845400 | 642 | #define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) || \ |
| AnnaBridge | 172:65be27845400 | 643 | (((ADDRESS) >= FLASH_OTP_BANK1_BASE) && ((ADDRESS) <= FLASH_OTP_BANK1_END)) || \ |
| AnnaBridge | 172:65be27845400 | 644 | (((ADDRESS) >= FLASH_OTP_BANK2_BASE) && ((ADDRESS) <= FLASH_OTP_BANK2_END))) |
| AnnaBridge | 172:65be27845400 | 645 | |
| AnnaBridge | 172:65be27845400 | 646 | #define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL)) |
| AnnaBridge | 172:65be27845400 | 647 | |
| AnnaBridge | 172:65be27845400 | 648 | #define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\ |
| AnnaBridge | 172:65be27845400 | 649 | ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\ |
| AnnaBridge | 172:65be27845400 | 650 | ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\ |
| AnnaBridge | 172:65be27845400 | 651 | ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7)) |
| AnnaBridge | 172:65be27845400 | 652 | |
| AnnaBridge | 172:65be27845400 | 653 | #define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFFFFF00U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) |
| AnnaBridge | 172:65be27845400 | 654 | |
| AnnaBridge | 172:65be27845400 | 655 | #define IS_OB_PCROP_RDP(CONFIG) (((CONFIG) == OB_PCROP_RDP_NOT_ERASE) || \ |
| AnnaBridge | 172:65be27845400 | 656 | ((CONFIG) == OB_PCROP_RDP_ERASE)) |
| AnnaBridge | 172:65be27845400 | 657 | |
| AnnaBridge | 172:65be27845400 | 658 | #define IS_OB_SECURE_RDP(CONFIG) (((CONFIG) == OB_SECURE_RDP_NOT_ERASE) || \ |
| AnnaBridge | 172:65be27845400 | 659 | ((CONFIG) == OB_SECURE_RDP_ERASE)) |
| AnnaBridge | 172:65be27845400 | 660 | |
| AnnaBridge | 172:65be27845400 | 661 | #define IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE)) |
| AnnaBridge | 172:65be27845400 | 662 | |
| AnnaBridge | 172:65be27845400 | 663 | #define IS_OB_USER_IOHSLV(VALUE) (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE)) |
| AnnaBridge | 172:65be27845400 | 664 | |
| AnnaBridge | 172:65be27845400 | 665 | #define IS_OB_IWDG1_SOURCE(SOURCE) (((SOURCE) == OB_IWDG1_SW) || ((SOURCE) == OB_IWDG1_HW)) |
| AnnaBridge | 172:65be27845400 | 666 | |
| AnnaBridge | 172:65be27845400 | 667 | #define IS_OB_STOP_D1_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D1) || ((VALUE) == OB_STOP_RST_D1)) |
| AnnaBridge | 172:65be27845400 | 668 | |
| AnnaBridge | 172:65be27845400 | 669 | #define IS_OB_STDBY_D1_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D1) || ((VALUE) == OB_STDBY_RST_D1)) |
| AnnaBridge | 172:65be27845400 | 670 | |
| AnnaBridge | 172:65be27845400 | 671 | #define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_ACTIVE)) |
| AnnaBridge | 172:65be27845400 | 672 | |
| AnnaBridge | 172:65be27845400 | 673 | #define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_ACTIVE)) |
| AnnaBridge | 172:65be27845400 | 674 | |
| AnnaBridge | 172:65be27845400 | 675 | #define IS_OB_USER_ST_RAM_SIZE(VALUE) (((VALUE) == OB_ST_RAM_SIZE_2KB) || ((VALUE) == OB_ST_RAM_SIZE_4KB) || \ |
| AnnaBridge | 172:65be27845400 | 676 | ((VALUE) == OB_ST_RAM_SIZE_8KB) || ((VALUE) == OB_ST_RAM_SIZE_16KB)) |
| AnnaBridge | 172:65be27845400 | 677 | |
| AnnaBridge | 172:65be27845400 | 678 | #define IS_OB_USER_SECURITY(VALUE) (((VALUE) == OB_SECURITY_ENABLE) || ((VALUE) == OB_SECURITY_DISABLE)) |
| AnnaBridge | 172:65be27845400 | 679 | |
| AnnaBridge | 172:65be27845400 | 680 | #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x73FU) && ((TYPE) != 0U)) |
| AnnaBridge | 172:65be27845400 | 681 | |
| AnnaBridge | 172:65be27845400 | 682 | #define IS_OB_BOOT_ADD_OPTION(VALUE) (((VALUE) == OB_BOOT_ADD0) || \ |
| AnnaBridge | 172:65be27845400 | 683 | ((VALUE) == OB_BOOT_ADD1) || \ |
| AnnaBridge | 172:65be27845400 | 684 | ((VALUE) == OB_BOOT_ADD_BOTH)) |
| AnnaBridge | 172:65be27845400 | 685 | |
| AnnaBridge | 172:65be27845400 | 686 | #define IS_FLASH_TYPECRC(VALUE) (((VALUE) == FLASH_CRC_ADDR) || \ |
| AnnaBridge | 172:65be27845400 | 687 | ((VALUE) == FLASH_CRC_SECTORS) || \ |
| AnnaBridge | 172:65be27845400 | 688 | ((VALUE) == FLASH_CRC_BANK)) |
| AnnaBridge | 172:65be27845400 | 689 | /** |
| AnnaBridge | 172:65be27845400 | 690 | * @} |
| AnnaBridge | 172:65be27845400 | 691 | */ |
| AnnaBridge | 172:65be27845400 | 692 | |
| AnnaBridge | 172:65be27845400 | 693 | /** |
| AnnaBridge | 172:65be27845400 | 694 | * @} |
| AnnaBridge | 172:65be27845400 | 695 | */ |
| AnnaBridge | 172:65be27845400 | 696 | |
| AnnaBridge | 172:65be27845400 | 697 | /* Private functions ---------------------------------------------------------*/ |
| AnnaBridge | 172:65be27845400 | 698 | /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions |
| AnnaBridge | 172:65be27845400 | 699 | * @{ |
| AnnaBridge | 172:65be27845400 | 700 | */ |
| AnnaBridge | 172:65be27845400 | 701 | void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange); |
| AnnaBridge | 172:65be27845400 | 702 | /** |
| AnnaBridge | 172:65be27845400 | 703 | * @} |
| AnnaBridge | 172:65be27845400 | 704 | */ |
| AnnaBridge | 172:65be27845400 | 705 | |
| AnnaBridge | 172:65be27845400 | 706 | /** |
| AnnaBridge | 172:65be27845400 | 707 | * @} |
| AnnaBridge | 172:65be27845400 | 708 | */ |
| AnnaBridge | 172:65be27845400 | 709 | |
| AnnaBridge | 172:65be27845400 | 710 | /** |
| AnnaBridge | 172:65be27845400 | 711 | * @} |
| AnnaBridge | 172:65be27845400 | 712 | */ |
| AnnaBridge | 172:65be27845400 | 713 | |
| AnnaBridge | 172:65be27845400 | 714 | /** |
| AnnaBridge | 172:65be27845400 | 715 | * @} |
| AnnaBridge | 172:65be27845400 | 716 | */ |
| AnnaBridge | 172:65be27845400 | 717 | |
| AnnaBridge | 172:65be27845400 | 718 | #ifdef __cplusplus |
| AnnaBridge | 172:65be27845400 | 719 | } |
| AnnaBridge | 172:65be27845400 | 720 | #endif |
| AnnaBridge | 172:65be27845400 | 721 | |
| AnnaBridge | 172:65be27845400 | 722 | #endif /* STM32H7xx_HAL_FLASH_EX_H */ |
| AnnaBridge | 172:65be27845400 | 723 | |
| AnnaBridge | 172:65be27845400 | 724 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
