mbed - The official Mbed 2 C/C++ SDK provides the softwa…

Users » mbed_official » Code » mbed

mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_H743ZI/TOOLCHAIN_ARM_MICRO/stm32h7xx_hal_eth.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	172:65be27845400	1	/**
AnnaBridge	172:65be27845400	2	******************************************************************************
AnnaBridge	172:65be27845400	3	* @file stm32h7xx_hal_eth.h
AnnaBridge	172:65be27845400	4	* @author MCD Application Team
AnnaBridge	172:65be27845400	5	* @brief Header file of ETH HAL module.
AnnaBridge	172:65be27845400	6	******************************************************************************
AnnaBridge	172:65be27845400	7	* @attention
AnnaBridge	172:65be27845400	8	*
AnnaBridge	172:65be27845400	9	* <h2><center>© Copyright (c) 2017 STMicroelectronics.
AnnaBridge	172:65be27845400	10	* All rights reserved.</center></h2>
AnnaBridge	172:65be27845400	11	*
AnnaBridge	172:65be27845400	12	* This software component is licensed by ST under BSD 3-Clause license,
AnnaBridge	172:65be27845400	13	* the "License"; You may not use this file except in compliance with the
AnnaBridge	172:65be27845400	14	* License. You may obtain a copy of the License at:
AnnaBridge	172:65be27845400	15	* opensource.org/licenses/BSD-3-Clause
AnnaBridge	172:65be27845400	16	*
AnnaBridge	172:65be27845400	17	******************************************************************************
AnnaBridge	172:65be27845400	18	*/
AnnaBridge	172:65be27845400	19
AnnaBridge	172:65be27845400	20	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	172:65be27845400	21	#ifndef STM32H7xx_HAL_ETH_H
AnnaBridge	172:65be27845400	22	#define STM32H7xx_HAL_ETH_H
AnnaBridge	172:65be27845400	23
AnnaBridge	172:65be27845400	24	#ifdef __cplusplus
AnnaBridge	172:65be27845400	25	extern "C" {
AnnaBridge	172:65be27845400	26	#endif
AnnaBridge	172:65be27845400	27
AnnaBridge	172:65be27845400	28	/* Includes ------------------------------------------------------------------*/
AnnaBridge	172:65be27845400	29	#include "stm32h7xx_hal_def.h"
AnnaBridge	172:65be27845400	30
AnnaBridge	172:65be27845400	31	/** @addtogroup STM32H7xx_HAL_Driver
AnnaBridge	172:65be27845400	32	* @{
AnnaBridge	172:65be27845400	33	*/
AnnaBridge	172:65be27845400	34
AnnaBridge	172:65be27845400	35	/** @addtogroup ETH
AnnaBridge	172:65be27845400	36	* @{
AnnaBridge	172:65be27845400	37	*/
AnnaBridge	172:65be27845400	38
AnnaBridge	172:65be27845400	39	/* Exported types ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	40	#ifndef ETH_TX_DESC_CNT
AnnaBridge	172:65be27845400	41	#define ETH_TX_DESC_CNT 4U
AnnaBridge	172:65be27845400	42	#endif
AnnaBridge	172:65be27845400	43
AnnaBridge	172:65be27845400	44	#ifndef ETH_RX_DESC_CNT
AnnaBridge	172:65be27845400	45	#define ETH_RX_DESC_CNT 4U
AnnaBridge	172:65be27845400	46	#endif
AnnaBridge	172:65be27845400	47
AnnaBridge	172:65be27845400	48	/********************* Descriptors struct def section **********************/
AnnaBridge	172:65be27845400	49	/** @defgroup ETH_Exported_Types ETH Exported Types
AnnaBridge	172:65be27845400	50	* @{
AnnaBridge	172:65be27845400	51	*/
AnnaBridge	172:65be27845400	52
AnnaBridge	172:65be27845400	53	/**
AnnaBridge	172:65be27845400	54	* @brief ETH DMA Descriptor structure definition
AnnaBridge	172:65be27845400	55	*/
AnnaBridge	172:65be27845400	56	typedef struct
AnnaBridge	172:65be27845400	57	{
AnnaBridge	172:65be27845400	58	__IO uint32_t DESC0;
AnnaBridge	172:65be27845400	59	__IO uint32_t DESC1;
AnnaBridge	172:65be27845400	60	__IO uint32_t DESC2;
AnnaBridge	172:65be27845400	61	__IO uint32_t DESC3;
AnnaBridge	172:65be27845400	62	__IO uint32_t BackupAddr0; /* used to store rx buffer 1 address */
AnnaBridge	172:65be27845400	63	__IO uint32_t BackupAddr1; /* used to store rx buffer 2 address */
AnnaBridge	172:65be27845400	64	}ETH_DMADescTypeDef;
AnnaBridge	172:65be27845400	65	/**
AnnaBridge	172:65be27845400	66	*
AnnaBridge	172:65be27845400	67	*/
AnnaBridge	172:65be27845400	68
AnnaBridge	172:65be27845400	69	/**
AnnaBridge	172:65be27845400	70	* @brief ETH Buffers List structure definition
AnnaBridge	172:65be27845400	71	*/
AnnaBridge	172:65be27845400	72	typedef struct __ETH_BufferTypeDef
AnnaBridge	172:65be27845400	73	{
AnnaBridge	172:65be27845400	74	uint8_t buffer; /<! buffer address */
AnnaBridge	172:65be27845400	75
AnnaBridge	172:65be27845400	76	uint32_t len; /<! buffer length /
AnnaBridge	172:65be27845400	77
AnnaBridge	172:65be27845400	78	struct __ETH_BufferTypeDef next; /<! Pointer to the next buffer in the list */
AnnaBridge	172:65be27845400	79	}ETH_BufferTypeDef;
AnnaBridge	172:65be27845400	80	/**
AnnaBridge	172:65be27845400	81	*
AnnaBridge	172:65be27845400	82	*/
AnnaBridge	172:65be27845400	83
AnnaBridge	172:65be27845400	84	/**
AnnaBridge	172:65be27845400	85	* @brief DMA Transmit Descriptors Wrapper structure definition
AnnaBridge	172:65be27845400	86	*/
AnnaBridge	172:65be27845400	87	typedef struct
AnnaBridge	172:65be27845400	88	{
AnnaBridge	172:65be27845400	89	uint32_t TxDesc[ETH_TX_DESC_CNT]; /<! Tx DMA descriptors addresses /
AnnaBridge	172:65be27845400	90
AnnaBridge	172:65be27845400	91	uint32_t CurTxDesc; /<! Current Tx descriptor index for packet transmission /
AnnaBridge	172:65be27845400	92
AnnaBridge	172:65be27845400	93	}ETH_TxDescListTypeDef;
AnnaBridge	172:65be27845400	94	/**
AnnaBridge	172:65be27845400	95	*
AnnaBridge	172:65be27845400	96	*/
AnnaBridge	172:65be27845400	97
AnnaBridge	172:65be27845400	98	/**
AnnaBridge	172:65be27845400	99	* @brief Transmit Packet Configuration structure definition
AnnaBridge	172:65be27845400	100	*/
AnnaBridge	172:65be27845400	101	typedef struct
AnnaBridge	172:65be27845400	102	{
AnnaBridge	172:65be27845400	103	uint32_t Attributes; /*!< Tx packet HW features capabilities.
AnnaBridge	172:65be27845400	104	This parameter can be a combination of @ref ETH_Tx_Packet_Attributes*/
AnnaBridge	172:65be27845400	105
AnnaBridge	172:65be27845400	106	uint32_t Length; /!< Total packet length /
AnnaBridge	172:65be27845400	107
AnnaBridge	172:65be27845400	108	ETH_BufferTypeDef TxBuffer; /!< Tx buffers pointers */
AnnaBridge	172:65be27845400	109
AnnaBridge	172:65be27845400	110	uint32_t SrcAddrCtrl; /*!< Specifies the source address insertion control.
AnnaBridge	172:65be27845400	111	This parameter can be a value of @ref ETH_Tx_Packet_Source_Addr_Control */
AnnaBridge	172:65be27845400	112
AnnaBridge	172:65be27845400	113	uint32_t CRCPadCtrl; /*!< Specifies the CRC and Pad insertion and replacement control.
AnnaBridge	172:65be27845400	114	This parameter can be a value of @ref ETH_Tx_Packet_CRC_Pad_Control */
AnnaBridge	172:65be27845400	115
AnnaBridge	172:65be27845400	116	uint32_t ChecksumCtrl; /*!< Specifies the checksum insertion control.
AnnaBridge	172:65be27845400	117	This parameter can be a value of @ref ETH_Tx_Packet_Checksum_Control */
AnnaBridge	172:65be27845400	118
AnnaBridge	172:65be27845400	119	uint32_t MaxSegmentSize; /*!< Sets TCP maximum segment size only when TCP segmentation is enabled.
AnnaBridge	172:65be27845400	120	This parameter can be a value from 0x0 to 0x3FFF */
AnnaBridge	172:65be27845400	121
AnnaBridge	172:65be27845400	122	uint32_t PayloadLen; /*!< Sets Total payload length only when TCP segmentation is enabled.
AnnaBridge	172:65be27845400	123	This parameter can be a value from 0x0 to 0x3FFFF */
AnnaBridge	172:65be27845400	124
AnnaBridge	172:65be27845400	125	uint32_t TCPHeaderLen; /*!< Sets TCP header length only when TCP segmentation is enabled.
AnnaBridge	172:65be27845400	126	This parameter can be a value from 0x5 to 0xF */
AnnaBridge	172:65be27845400	127
AnnaBridge	172:65be27845400	128	uint32_t VlanTag; /*!< Sets VLAN Tag only when VLAN is enabled.
AnnaBridge	172:65be27845400	129	This parameter can be a value from 0x0 to 0xFFFF*/
AnnaBridge	172:65be27845400	130
AnnaBridge	172:65be27845400	131	uint32_t VlanCtrl; /*!< Specifies VLAN Tag insertion control only when VLAN is enabled.
AnnaBridge	172:65be27845400	132	This parameter can be a value of @ref ETH_Tx_Packet_VLAN_Control */
AnnaBridge	172:65be27845400	133
AnnaBridge	172:65be27845400	134	uint32_t InnerVlanTag; /*!< Sets Inner VLAN Tag only when Inner VLAN is enabled.
AnnaBridge	172:65be27845400	135	This parameter can be a value from 0x0 to 0x3FFFF */
AnnaBridge	172:65be27845400	136
AnnaBridge	172:65be27845400	137	uint32_t InnerVlanCtrl; /*!< Specifies Inner VLAN Tag insertion control only when Inner VLAN is enabled.
AnnaBridge	172:65be27845400	138	This parameter can be a value of @ref ETH_Tx_Packet_Inner_VLAN_Control */
AnnaBridge	172:65be27845400	139
AnnaBridge	172:65be27845400	140	}ETH_TxPacketConfig;
AnnaBridge	172:65be27845400	141	/**
AnnaBridge	172:65be27845400	142	*
AnnaBridge	172:65be27845400	143	*/
AnnaBridge	172:65be27845400	144
AnnaBridge	172:65be27845400	145	/**
AnnaBridge	172:65be27845400	146	* @brief DMA Receive Descriptors Wrapper structure definition
AnnaBridge	172:65be27845400	147	*/
AnnaBridge	172:65be27845400	148	typedef struct
AnnaBridge	172:65be27845400	149	{
AnnaBridge	172:65be27845400	150	uint32_t RxDesc[ETH_RX_DESC_CNT]; /<! Rx DMA descriptors addresses. /
AnnaBridge	172:65be27845400	151
AnnaBridge	172:65be27845400	152	uint32_t CurRxDesc; /<! Current Rx descriptor, ready for next reception. /
AnnaBridge	172:65be27845400	153
AnnaBridge	172:65be27845400	154	uint32_t FirstAppDesc; /<! First descriptor of last received packet. /
AnnaBridge	172:65be27845400	155
AnnaBridge	172:65be27845400	156	uint32_t AppDescNbr; /<! Number of descriptors of last received packet. /
AnnaBridge	172:65be27845400	157
AnnaBridge	172:65be27845400	158	uint32_t AppContextDesc; /*<! If 1 a context descriptor is present in last received packet.
AnnaBridge	172:65be27845400	159	If 0 no context descriptor is present in last received packet. */
AnnaBridge	172:65be27845400	160
AnnaBridge	172:65be27845400	161	uint32_t ItMode; /*<! If 1, DMA will generate the Rx complete interrupt.
AnnaBridge	172:65be27845400	162	If 0, DMA will not generate the Rx complete interrupt. */
AnnaBridge	172:65be27845400	163	}ETH_RxDescListTypeDef;
AnnaBridge	172:65be27845400	164	/**
AnnaBridge	172:65be27845400	165	*
AnnaBridge	172:65be27845400	166	*/
AnnaBridge	172:65be27845400	167
AnnaBridge	172:65be27845400	168	/**
AnnaBridge	172:65be27845400	169	* @brief Received Packet Information structure definition
AnnaBridge	172:65be27845400	170	*/
AnnaBridge	172:65be27845400	171	typedef struct
AnnaBridge	172:65be27845400	172	{
AnnaBridge	172:65be27845400	173	uint32_t SegmentCnt; /<! Number of Rx Descriptors /
AnnaBridge	172:65be27845400	174
AnnaBridge	172:65be27845400	175	uint32_t VlanTag; /<! Vlan Tag value /
AnnaBridge	172:65be27845400	176
AnnaBridge	172:65be27845400	177	uint32_t InnerVlanTag; /<! Inner Vlan Tag value /
AnnaBridge	172:65be27845400	178
AnnaBridge	172:65be27845400	179	uint32_t Checksum; /*<! Rx Checksum status.
AnnaBridge	172:65be27845400	180	This parameter can be a value of @ref ETH_Rx_Checksum_Status */
AnnaBridge	172:65be27845400	181
AnnaBridge	172:65be27845400	182	uint32_t HeaderType; /*<! IP header type.
AnnaBridge	172:65be27845400	183	This parameter can be a value of @ref ETH_Rx_IP_Header_Type */
AnnaBridge	172:65be27845400	184
AnnaBridge	172:65be27845400	185	uint32_t PayloadType; /*<! Payload type.
AnnaBridge	172:65be27845400	186	This parameter can be a value of @ref ETH_Rx_Payload_Type */
AnnaBridge	172:65be27845400	187
AnnaBridge	172:65be27845400	188	uint32_t MacFilterStatus; /*<! MAC filter status.
AnnaBridge	172:65be27845400	189	This parameter can be a value of @ref ETH_Rx_MAC_Filter_Status */
AnnaBridge	172:65be27845400	190
AnnaBridge	172:65be27845400	191	uint32_t L3FilterStatus; /*<! L3 filter status
AnnaBridge	172:65be27845400	192	This parameter can be a value of @ref ETH_Rx_L3_Filter_Status */
AnnaBridge	172:65be27845400	193
AnnaBridge	172:65be27845400	194	uint32_t L4FilterStatus; /*<! L4 filter status
AnnaBridge	172:65be27845400	195	This parameter can be a value of @ref ETH_Rx_L4_Filter_Status */
AnnaBridge	172:65be27845400	196
AnnaBridge	172:65be27845400	197	uint32_t ErrorCode; /*<! Rx error code
AnnaBridge	172:65be27845400	198	This parameter can be a combination of @ref ETH_Rx_Error_Code */
AnnaBridge	172:65be27845400	199
AnnaBridge	172:65be27845400	200	} ETH_RxPacketInfo;
AnnaBridge	172:65be27845400	201	/**
AnnaBridge	172:65be27845400	202	*
AnnaBridge	172:65be27845400	203	*/
AnnaBridge	172:65be27845400	204
AnnaBridge	172:65be27845400	205	/**
AnnaBridge	172:65be27845400	206	* @brief ETH MAC Configuration Structure definition
AnnaBridge	172:65be27845400	207	*/
AnnaBridge	172:65be27845400	208	typedef struct
AnnaBridge	172:65be27845400	209	{
AnnaBridge	172:65be27845400	210	uint32_t SourceAddrControl; /*!< Selects the Source Address Insertion or Replacement Control.
AnnaBridge	172:65be27845400	211	This parameter can be a value of @ref ETH_Source_Addr_Control */
AnnaBridge	172:65be27845400	212
AnnaBridge	172:65be27845400	213	FunctionalState ChecksumOffload; /!< Enables or Disable the checksum checking for received packet payloads TCP, UDP or ICMP headers /
AnnaBridge	172:65be27845400	214
AnnaBridge	172:65be27845400	215	uint32_t InterPacketGapVal; /*!< Sets the minimum IPG between Packet during transmission.
AnnaBridge	172:65be27845400	216	This parameter can be a value of @ref ETH_Inter_Packet_Gap */
AnnaBridge	172:65be27845400	217
AnnaBridge	172:65be27845400	218	FunctionalState GiantPacketSizeLimitControl; /!< Enables or disables the Giant Packet Size Limit Control. /
AnnaBridge	172:65be27845400	219
AnnaBridge	172:65be27845400	220	FunctionalState Support2KPacket; /!< Enables or disables the IEEE 802.3as Support for 2K length Packets /
AnnaBridge	172:65be27845400	221
AnnaBridge	172:65be27845400	222	FunctionalState CRCStripTypePacket; /!< Enables or disables the CRC stripping for Type packets./
AnnaBridge	172:65be27845400	223
AnnaBridge	172:65be27845400	224	FunctionalState AutomaticPadCRCStrip; /!< Enables or disables the Automatic MAC Pad/CRC Stripping./
AnnaBridge	172:65be27845400	225
AnnaBridge	172:65be27845400	226	FunctionalState Watchdog; /*!< Enables or disables the Watchdog timer on Rx path
AnnaBridge	172:65be27845400	227	When enabled, the MAC allows no more then 2048 bytes to be received.
AnnaBridge	172:65be27845400	228	When disabled, the MAC can receive up to 16384 bytes. */
AnnaBridge	172:65be27845400	229
AnnaBridge	172:65be27845400	230	FunctionalState Jabber; /*!< Enables or disables Jabber timer on Tx path
AnnaBridge	172:65be27845400	231	When enabled, the MAC allows no more then 2048 bytes to be sent.
AnnaBridge	172:65be27845400	232	When disabled, the MAC can send up to 16384 bytes. */
AnnaBridge	172:65be27845400	233
AnnaBridge	172:65be27845400	234	FunctionalState JumboPacket; /*!< Enables or disables receiving Jumbo Packet
AnnaBridge	172:65be27845400	235	When enabled, the MAC allows jumbo packets of 9,018 bytes
AnnaBridge	172:65be27845400	236	without reporting a giant packet error */
AnnaBridge	172:65be27845400	237
AnnaBridge	172:65be27845400	238	uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
AnnaBridge	172:65be27845400	239	This parameter can be a value of @ref ETH_Speed */
AnnaBridge	172:65be27845400	240
AnnaBridge	172:65be27845400	241	uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
AnnaBridge	172:65be27845400	242	This parameter can be a value of @ref ETH_Duplex_Mode */
AnnaBridge	172:65be27845400	243
AnnaBridge	172:65be27845400	244	FunctionalState LoopbackMode; /!< Enables or disables the loopback mode /
AnnaBridge	172:65be27845400	245
AnnaBridge	172:65be27845400	246	FunctionalState CarrierSenseBeforeTransmit; /!< Enables or disables the Carrier Sense Before Transmission in Full Duplex Mode. /
AnnaBridge	172:65be27845400	247
AnnaBridge	172:65be27845400	248	FunctionalState ReceiveOwn; /!< Enables or disables the Receive Own in Half Duplex mode. /
AnnaBridge	172:65be27845400	249
AnnaBridge	172:65be27845400	250	FunctionalState CarrierSenseDuringTransmit; /!< Enables or disables the Carrier Sense During Transmission in the Half Duplex mode /
AnnaBridge	172:65be27845400	251
AnnaBridge	172:65be27845400	252	FunctionalState RetryTransmission; /!< Enables or disables the MAC retry transmission, when a collision occurs in Half Duplex mode./
AnnaBridge	172:65be27845400	253
AnnaBridge	172:65be27845400	254	uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
AnnaBridge	172:65be27845400	255	This parameter can be a value of @ref ETH_Back_Off_Limit */
AnnaBridge	172:65be27845400	256
AnnaBridge	172:65be27845400	257	FunctionalState DeferralCheck; /!< Enables or disables the deferral check function in Half Duplex mode. /
AnnaBridge	172:65be27845400	258
AnnaBridge	172:65be27845400	259	uint32_t PreambleLength; /*!< Selects or not the Preamble Length for Transmit packets (Full Duplex mode).
AnnaBridge	172:65be27845400	260	This parameter can be a value of @ref ETH_Preamble_Length */
AnnaBridge	172:65be27845400	261
AnnaBridge	172:65be27845400	262	FunctionalState UnicastSlowProtocolPacketDetect; /!< Enable or disables the Detection of Slow Protocol Packets with unicast address. /
AnnaBridge	172:65be27845400	263
AnnaBridge	172:65be27845400	264	FunctionalState SlowProtocolDetect; /!< Enable or disables the Slow Protocol Detection. /
AnnaBridge	172:65be27845400	265
AnnaBridge	172:65be27845400	266	FunctionalState CRCCheckingRxPackets; /!< Enable or disables the CRC Checking for Received Packets. /
AnnaBridge	172:65be27845400	267
AnnaBridge	172:65be27845400	268	uint32_t GiantPacketSizeLimit; /*!< Specifies the packet size that the MAC will declare it as Giant, If it's size is
AnnaBridge	172:65be27845400	269	greater than the value programmed in this field in units of bytes
AnnaBridge	172:65be27845400	270	This parameter must be a number between Min_Data = 0x618 (1518 byte) and Max_Data = 0x3FFF (32 Kbyte)*/
AnnaBridge	172:65be27845400	271
AnnaBridge	172:65be27845400	272	FunctionalState ExtendedInterPacketGap; /!< Enable or disables the extended inter packet gap. /
AnnaBridge	172:65be27845400	273
AnnaBridge	172:65be27845400	274	uint32_t ExtendedInterPacketGapVal; /*!< Sets the Extended IPG between Packet during transmission.
AnnaBridge	172:65be27845400	275	This parameter can be a value from 0x0 to 0xFF */
AnnaBridge	172:65be27845400	276
AnnaBridge	172:65be27845400	277	FunctionalState ProgrammableWatchdog; /!< Enable or disables the Programmable Watchdog./
AnnaBridge	172:65be27845400	278
AnnaBridge	172:65be27845400	279	uint32_t WatchdogTimeout; /*!< This field is used as watchdog timeout for a received packet
AnnaBridge	172:65be27845400	280	This parameter can be a value of @ref ETH_Watchdog_Timeout */
AnnaBridge	172:65be27845400	281
AnnaBridge	172:65be27845400	282	uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control packet.
AnnaBridge	172:65be27845400	283	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
AnnaBridge	172:65be27845400	284
AnnaBridge	172:65be27845400	285	FunctionalState ZeroQuantaPause; /!< Enable or disables the automatic generation of Zero Quanta Pause Control packets./
AnnaBridge	172:65be27845400	286
AnnaBridge	172:65be27845400	287	uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Packet.
AnnaBridge	172:65be27845400	288	This parameter can be a value of @ref ETH_Pause_Low_Threshold */
AnnaBridge	172:65be27845400	289
AnnaBridge	172:65be27845400	290	FunctionalState TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause packets in Full Duplex mode
AnnaBridge	172:65be27845400	291	or the MAC back pressure operation in Half Duplex mode */
AnnaBridge	172:65be27845400	292
AnnaBridge	172:65be27845400	293	FunctionalState UnicastPausePacketDetect; /!< Enables or disables the MAC to detect Pause packets with unicast address of the station /
AnnaBridge	172:65be27845400	294
AnnaBridge	172:65be27845400	295	FunctionalState ReceiveFlowControl; /*!< Enables or disables the MAC to decodes the received Pause packet
AnnaBridge	172:65be27845400	296	and disables its transmitter for a specified (Pause) time */
AnnaBridge	172:65be27845400	297
AnnaBridge	172:65be27845400	298	uint32_t TransmitQueueMode; /*!< Specifies the Transmit Queue operating mode.
AnnaBridge	172:65be27845400	299	This parameter can be a value of @ref ETH_Transmit_Mode */
AnnaBridge	172:65be27845400	300
AnnaBridge	172:65be27845400	301	uint32_t ReceiveQueueMode; /*!< Specifies the Receive Queue operating mode.
AnnaBridge	172:65be27845400	302	This parameter can be a value of @ref ETH_Receive_Mode */
AnnaBridge	172:65be27845400	303
AnnaBridge	172:65be27845400	304	FunctionalState DropTCPIPChecksumErrorPacket; /!< Enables or disables Dropping of TCPIP Checksum Error Packets. /
AnnaBridge	172:65be27845400	305
AnnaBridge	172:65be27845400	306	FunctionalState ForwardRxErrorPacket; /!< Enables or disables forwarding Error Packets. /
AnnaBridge	172:65be27845400	307
AnnaBridge	172:65be27845400	308	FunctionalState ForwardRxUndersizedGoodPacket; /!< Enables or disables forwarding Undersized Good Packets./
AnnaBridge	172:65be27845400	309	} ETH_MACConfigTypeDef;
AnnaBridge	172:65be27845400	310	/**
AnnaBridge	172:65be27845400	311	*
AnnaBridge	172:65be27845400	312	*/
AnnaBridge	172:65be27845400	313
AnnaBridge	172:65be27845400	314	/**
AnnaBridge	172:65be27845400	315	* @brief ETH DMA Configuration Structure definition
AnnaBridge	172:65be27845400	316	*/
AnnaBridge	172:65be27845400	317	typedef struct
AnnaBridge	172:65be27845400	318	{
AnnaBridge	172:65be27845400	319	uint32_t DMAArbitration; /*!< Sets the arbitration scheme between DMA Tx and Rx
AnnaBridge	172:65be27845400	320	This parameter can be a value of @ref ETH_DMA_Arbitration */
AnnaBridge	172:65be27845400	321
AnnaBridge	172:65be27845400	322	FunctionalState AddressAlignedBeats; /*!< Enables or disables the AHB Master interface address aligned
AnnaBridge	172:65be27845400	323	burst transfers on Read and Write channels */
AnnaBridge	172:65be27845400	324
AnnaBridge	172:65be27845400	325	uint32_t BurstMode; /*!< Sets the AHB Master interface burst transfers.
AnnaBridge	172:65be27845400	326	This parameter can be a value of @ref ETH_Burst_Mode */
AnnaBridge	172:65be27845400	327
AnnaBridge	172:65be27845400	328	FunctionalState RebuildINCRxBurst; /*!< Enables or disables the AHB Master to rebuild the pending beats
AnnaBridge	172:65be27845400	329	of any initiated burst transfer with INCRx and SINGLE transfers. */
AnnaBridge	172:65be27845400	330
AnnaBridge	172:65be27845400	331	FunctionalState PBLx8Mode; /!< Enables or disables the PBL multiplication by eight. /
AnnaBridge	172:65be27845400	332
AnnaBridge	172:65be27845400	333	uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
AnnaBridge	172:65be27845400	334	This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
AnnaBridge	172:65be27845400	335
AnnaBridge	172:65be27845400	336	FunctionalState SecondPacketOperate; /*!< Enables or disables the Operate on second Packet mode, which allows the DMA to process a second
AnnaBridge	172:65be27845400	337	Packet of Transmit data even before obtaining the status for the first one. */
AnnaBridge	172:65be27845400	338
AnnaBridge	172:65be27845400	339	uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
AnnaBridge	172:65be27845400	340	This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
AnnaBridge	172:65be27845400	341
AnnaBridge	172:65be27845400	342	FunctionalState FlushRxPacket; /!< Enables or disables the Rx Packet Flush /
AnnaBridge	172:65be27845400	343
AnnaBridge	172:65be27845400	344	FunctionalState TCPSegmentation; /!< Enables or disables the TCP Segmentation /
AnnaBridge	172:65be27845400	345
AnnaBridge	172:65be27845400	346	uint32_t MaximumSegmentSize; /*!< Sets the maximum segment size that should be used while segmenting the packet
AnnaBridge	172:65be27845400	347	This parameter can be a value from 0x40 to 0x3FFF */
AnnaBridge	172:65be27845400	348	} ETH_DMAConfigTypeDef;
AnnaBridge	172:65be27845400	349	/**
AnnaBridge	172:65be27845400	350	*
AnnaBridge	172:65be27845400	351	*/
AnnaBridge	172:65be27845400	352
AnnaBridge	172:65be27845400	353	/**
AnnaBridge	172:65be27845400	354	* @brief HAL ETH Media Interfaces enum definition
AnnaBridge	172:65be27845400	355	*/
AnnaBridge	172:65be27845400	356	typedef enum
AnnaBridge	172:65be27845400	357	{
AnnaBridge	172:65be27845400	358	HAL_ETH_MII_MODE = 0x00U, /!< Media Independent Interface /
AnnaBridge	172:65be27845400	359	HAL_ETH_RMII_MODE = 0x01U /!< Reduced Media Independent Interface /
AnnaBridge	172:65be27845400	360	}ETH_MediaInterfaceTypeDef;
AnnaBridge	172:65be27845400	361	/**
AnnaBridge	172:65be27845400	362	*
AnnaBridge	172:65be27845400	363	*/
AnnaBridge	172:65be27845400	364
AnnaBridge	172:65be27845400	365	/**
AnnaBridge	172:65be27845400	366	* @brief ETH Init Structure definition
AnnaBridge	172:65be27845400	367	*/
AnnaBridge	172:65be27845400	368	typedef struct
AnnaBridge	172:65be27845400	369	{
AnnaBridge	172:65be27845400	370
AnnaBridge	172:65be27845400	371	uint8_t MACAddr; /!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
AnnaBridge	172:65be27845400	372
AnnaBridge	172:65be27845400	373	ETH_MediaInterfaceTypeDef MediaInterface; /!< Selects the MII interface or the RMII interface. /
AnnaBridge	172:65be27845400	374
AnnaBridge	172:65be27845400	375	ETH_DMADescTypeDef TxDesc; /!< Provides the address of the first DMA Tx descriptor in the list */
AnnaBridge	172:65be27845400	376
AnnaBridge	172:65be27845400	377	ETH_DMADescTypeDef RxDesc; /!< Provides the address of the first DMA Rx descriptor in the list */
AnnaBridge	172:65be27845400	378
AnnaBridge	172:65be27845400	379	uint32_t RxBuffLen; /!< Provides the length of Rx buffers size /
AnnaBridge	172:65be27845400	380
AnnaBridge	172:65be27845400	381	}ETH_InitTypeDef;
AnnaBridge	172:65be27845400	382	/**
AnnaBridge	172:65be27845400	383	*
AnnaBridge	172:65be27845400	384	*/
AnnaBridge	172:65be27845400	385
AnnaBridge	172:65be27845400	386	/**
AnnaBridge	172:65be27845400	387	* @brief HAL State structures definition
AnnaBridge	172:65be27845400	388	*/
AnnaBridge	172:65be27845400	389	typedef uint32_t HAL_ETH_StateTypeDef;
AnnaBridge	172:65be27845400	390	/**
AnnaBridge	172:65be27845400	391	*
AnnaBridge	172:65be27845400	392	*/
AnnaBridge	172:65be27845400	393
AnnaBridge	172:65be27845400	394	/**
AnnaBridge	172:65be27845400	395	* @brief ETH Handle Structure definition
AnnaBridge	172:65be27845400	396	*/
AnnaBridge	172:65be27845400	397	#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
AnnaBridge	172:65be27845400	398	typedef struct __ETH_HandleTypeDef
AnnaBridge	172:65be27845400	399	#else
AnnaBridge	172:65be27845400	400	typedef struct
AnnaBridge	172:65be27845400	401	#endif
AnnaBridge	172:65be27845400	402	{
AnnaBridge	172:65be27845400	403	ETH_TypeDef Instance; /!< Register base address */
AnnaBridge	172:65be27845400	404
AnnaBridge	172:65be27845400	405	ETH_InitTypeDef Init; /!< Ethernet Init Configuration /
AnnaBridge	172:65be27845400	406
AnnaBridge	172:65be27845400	407	ETH_TxDescListTypeDef TxDescList; /*!< Tx descriptor wrapper: holds all Tx descriptors list
AnnaBridge	172:65be27845400	408	addresses and current descriptor index */
AnnaBridge	172:65be27845400	409
AnnaBridge	172:65be27845400	410	ETH_RxDescListTypeDef RxDescList; /*!< Rx descriptor wrapper: holds all Rx descriptors list
AnnaBridge	172:65be27845400	411	addresses and current descriptor index */
AnnaBridge	172:65be27845400	412
AnnaBridge	172:65be27845400	413	HAL_LockTypeDef Lock; /!< Locking object /
AnnaBridge	172:65be27845400	414
AnnaBridge	172:65be27845400	415	__IO HAL_ETH_StateTypeDef gState; /*!< ETH state information related to global Handle management
AnnaBridge	172:65be27845400	416	and also related to Tx operations.
AnnaBridge	172:65be27845400	417	This parameter can be a value of @ref HAL_ETH_StateTypeDef */
AnnaBridge	172:65be27845400	418
AnnaBridge	172:65be27845400	419	__IO HAL_ETH_StateTypeDef RxState; /*!< ETH state information related to Rx operations.
AnnaBridge	172:65be27845400	420	This parameter can be a value of @ref HAL_ETH_StateTypeDef */
AnnaBridge	172:65be27845400	421
AnnaBridge	172:65be27845400	422	__IO uint32_t ErrorCode; /*!< Holds the global Error code of the ETH HAL status machine
AnnaBridge	172:65be27845400	423	This parameter can be a value of of @ref ETH_Error_Code */
AnnaBridge	172:65be27845400	424
AnnaBridge	172:65be27845400	425	__IO uint32_t DMAErrorCode; /*!< Holds the DMA Rx Tx Error code when a DMA AIS interrupt occurs
AnnaBridge	172:65be27845400	426	This parameter can be a combination of @ref ETH_DMA_Status_Flags */
AnnaBridge	172:65be27845400	427
AnnaBridge	172:65be27845400	428	__IO uint32_t MACErrorCode; /*!< Holds the MAC Rx Tx Error code when a MAC Rx or Tx status interrupt occurs
AnnaBridge	172:65be27845400	429	This parameter can be a combination of @ref ETH_MAC_Rx_Tx_Status */
AnnaBridge	172:65be27845400	430
AnnaBridge	172:65be27845400	431	__IO uint32_t MACWakeUpEvent; /*!< Holds the Wake Up event when the MAC exit the power down mode
AnnaBridge	172:65be27845400	432	This parameter can be a value of @ref ETH_MAC_Wake_Up_Event */
AnnaBridge	172:65be27845400	433
AnnaBridge	172:65be27845400	434	__IO uint32_t MACLPIEvent; /*!< Holds the LPI event when the an LPI status interrupt occurs.
AnnaBridge	172:65be27845400	435	This parameter can be a value of @ref ETHEx_LPI_Event */
AnnaBridge	172:65be27845400	436
AnnaBridge	172:65be27845400	437	#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
AnnaBridge	172:65be27845400	438
AnnaBridge	172:65be27845400	439	void (* TxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /!< ETH Tx Complete Callback /
AnnaBridge	172:65be27845400	440	void (* RxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /!< ETH Rx Complete Callback /
AnnaBridge	172:65be27845400	441	void (* DMAErrorCallback) ( struct __ETH_HandleTypeDef * heth); /!< ETH DMA Error Callback /
AnnaBridge	172:65be27845400	442	void (* MACErrorCallback) ( struct __ETH_HandleTypeDef * heth); /!< ETH MAC Error Callback /
AnnaBridge	172:65be27845400	443	void (* PMTCallback) ( struct __ETH_HandleTypeDef * heth); /!< ETH Power Management Callback /
AnnaBridge	172:65be27845400	444	void (* EEECallback) ( struct __ETH_HandleTypeDef * heth); /!< ETH EEE Callback /
AnnaBridge	172:65be27845400	445	void (* WakeUpCallback) ( struct __ETH_HandleTypeDef * heth); /!< ETH Wake UP Callback /
AnnaBridge	172:65be27845400	446
AnnaBridge	172:65be27845400	447	void (* MspInitCallback) ( struct __ETH_HandleTypeDef * heth); /!< ETH Msp Init callback /
AnnaBridge	172:65be27845400	448	void (* MspDeInitCallback) ( struct __ETH_HandleTypeDef * heth); /!< ETH Msp DeInit callback /
AnnaBridge	172:65be27845400	449
AnnaBridge	172:65be27845400	450	#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
AnnaBridge	172:65be27845400	451
AnnaBridge	172:65be27845400	452	} ETH_HandleTypeDef;
AnnaBridge	172:65be27845400	453	/**
AnnaBridge	172:65be27845400	454	*
AnnaBridge	172:65be27845400	455	*/
AnnaBridge	172:65be27845400	456
AnnaBridge	172:65be27845400	457	#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
AnnaBridge	172:65be27845400	458	/**
AnnaBridge	172:65be27845400	459	* @brief HAL ETH Callback ID enumeration definition
AnnaBridge	172:65be27845400	460	*/
AnnaBridge	172:65be27845400	461	typedef enum
AnnaBridge	172:65be27845400	462	{
AnnaBridge	172:65be27845400	463	HAL_ETH_MSPINIT_CB_ID = 0x00U, /!< ETH MspInit callback ID /
AnnaBridge	172:65be27845400	464	HAL_ETH_MSPDEINIT_CB_ID = 0x01U, /!< ETH MspDeInit callback ID /
AnnaBridge	172:65be27845400	465
AnnaBridge	172:65be27845400	466	HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /!< ETH Tx Complete Callback ID /
AnnaBridge	172:65be27845400	467	HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /!< ETH Rx Complete Callback ID /
AnnaBridge	172:65be27845400	468	HAL_ETH_DMA_ERROR_CB_ID = 0x04U, /!< ETH DMA Error Callback ID /
AnnaBridge	172:65be27845400	469	HAL_ETH_MAC_ERROR_CB_ID = 0x05U, /!< ETH MAC Error Callback ID /
AnnaBridge	172:65be27845400	470	HAL_ETH_PMT_CB_ID = 0x06U, /!< ETH Power Management Callback ID /
AnnaBridge	172:65be27845400	471	HAL_ETH_EEE_CB_ID = 0x07U, /!< ETH EEE Callback ID /
AnnaBridge	172:65be27845400	472	HAL_ETH_WAKEUP_CB_ID = 0x08U /!< ETH Wake UP Callback ID /
AnnaBridge	172:65be27845400	473
AnnaBridge	172:65be27845400	474
AnnaBridge	172:65be27845400	475	}HAL_ETH_CallbackIDTypeDef;
AnnaBridge	172:65be27845400	476
AnnaBridge	172:65be27845400	477	/**
AnnaBridge	172:65be27845400	478	* @brief HAL ETH Callback pointer definition
AnnaBridge	172:65be27845400	479	*/
AnnaBridge	172:65be27845400	480	typedef void (pETH_CallbackTypeDef)(ETH_HandleTypeDef heth); /!< pointer to an ETH callback function /
AnnaBridge	172:65be27845400	481
AnnaBridge	172:65be27845400	482	#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
AnnaBridge	172:65be27845400	483
AnnaBridge	172:65be27845400	484	/**
AnnaBridge	172:65be27845400	485	* @brief ETH MAC filter structure definition
AnnaBridge	172:65be27845400	486	*/
AnnaBridge	172:65be27845400	487	typedef struct{
AnnaBridge	172:65be27845400	488	FunctionalState PromiscuousMode; /!< Enable or Disable Promiscuous Mode /
AnnaBridge	172:65be27845400	489
AnnaBridge	172:65be27845400	490	FunctionalState ReceiveAllMode; /!< Enable or Disable Receive All Mode /
AnnaBridge	172:65be27845400	491
AnnaBridge	172:65be27845400	492	FunctionalState HachOrPerfectFilter; /!< Enable or Disable Perfect filtering in addition to Hash filtering /
AnnaBridge	172:65be27845400	493
AnnaBridge	172:65be27845400	494	FunctionalState HashUnicast; /!< Enable or Disable Hash filtering on unicast packets /
AnnaBridge	172:65be27845400	495
AnnaBridge	172:65be27845400	496	FunctionalState HashMulticast; /!< Enable or Disable Hash filtering on multicast packets /
AnnaBridge	172:65be27845400	497
AnnaBridge	172:65be27845400	498	FunctionalState PassAllMulticast; /!< Enable or Disable passing all multicast packets /
AnnaBridge	172:65be27845400	499
AnnaBridge	172:65be27845400	500	FunctionalState SrcAddrFiltering; /!< Enable or Disable source address filtering module /
AnnaBridge	172:65be27845400	501
AnnaBridge	172:65be27845400	502	FunctionalState SrcAddrInverseFiltering; /!< Enable or Disable source address inverse filtering /
AnnaBridge	172:65be27845400	503
AnnaBridge	172:65be27845400	504	FunctionalState DestAddrInverseFiltering; /!< Enable or Disable destination address inverse filtering /
AnnaBridge	172:65be27845400	505
AnnaBridge	172:65be27845400	506	FunctionalState BroadcastFilter; /!< Enable or Disable broadcast filter /
AnnaBridge	172:65be27845400	507
AnnaBridge	172:65be27845400	508	uint32_t ControlPacketsFilter; /*!< Set the control packets filter
AnnaBridge	172:65be27845400	509	This parameter can be a value of @ref ETH_Control_Packets_Filter */
AnnaBridge	172:65be27845400	510	}ETH_MACFilterConfigTypeDef;
AnnaBridge	172:65be27845400	511	/**
AnnaBridge	172:65be27845400	512	*
AnnaBridge	172:65be27845400	513	*/
AnnaBridge	172:65be27845400	514
AnnaBridge	172:65be27845400	515	/**
AnnaBridge	172:65be27845400	516	* @brief ETH Power Down structure definition
AnnaBridge	172:65be27845400	517	*/
AnnaBridge	172:65be27845400	518	typedef struct{
AnnaBridge	172:65be27845400	519	FunctionalState WakeUpPacket; /!< Enable or Disable Wake up packet detection in power down mode /
AnnaBridge	172:65be27845400	520
AnnaBridge	172:65be27845400	521	FunctionalState MagicPacket; /!< Enable or Disable Magic packet detection in power down mode /
AnnaBridge	172:65be27845400	522
AnnaBridge	172:65be27845400	523	FunctionalState GlobalUnicast; /!< Enable or Disable Global unicast packet detection in power down mode /
AnnaBridge	172:65be27845400	524
AnnaBridge	172:65be27845400	525	FunctionalState WakeUpForward; /!< Enable or Disable Forwarding Wake up packets /
AnnaBridge	172:65be27845400	526
AnnaBridge	172:65be27845400	527	}ETH_PowerDownConfigTypeDef;
AnnaBridge	172:65be27845400	528	/**
AnnaBridge	172:65be27845400	529	*
AnnaBridge	172:65be27845400	530	*/
AnnaBridge	172:65be27845400	531
AnnaBridge	172:65be27845400	532	/**
AnnaBridge	172:65be27845400	533	* @}
AnnaBridge	172:65be27845400	534	*/
AnnaBridge	172:65be27845400	535
AnnaBridge	172:65be27845400	536	/* Exported constants --------------------------------------------------------*/
AnnaBridge	172:65be27845400	537	/** @defgroup ETH_Exported_Constants ETH Exported Constants
AnnaBridge	172:65be27845400	538	* @{
AnnaBridge	172:65be27845400	539	*/
AnnaBridge	172:65be27845400	540
AnnaBridge	172:65be27845400	541	/** @defgroup ETH_DMA_Tx_Descriptor_Bit_Definition ETH DMA Tx Descriptor Bit Definition
AnnaBridge	172:65be27845400	542	* @{
AnnaBridge	172:65be27845400	543	*/
AnnaBridge	172:65be27845400	544
AnnaBridge	172:65be27845400	545	/*
AnnaBridge	172:65be27845400	546	DMA Tx Normal Desciptor Read Format
AnnaBridge	172:65be27845400	547	-----------------------------------------------------------------------------------------------
AnnaBridge	172:65be27845400	548	TDES0 \| Buffer1 or Header Address [31:0] \|
AnnaBridge	172:65be27845400	549	-----------------------------------------------------------------------------------------------
AnnaBridge	172:65be27845400	550	TDES1 \| Buffer2 Address [31:0] / Next Descriptor Address [31:0] \|
AnnaBridge	172:65be27845400	551	-----------------------------------------------------------------------------------------------
AnnaBridge	172:65be27845400	552	TDES2 \| IOC(31) \| TTSE(30) \| Buff2 Length[29:16] \| VTIR[15:14] \| Header or Buff1 Length[13:0] \|
AnnaBridge	172:65be27845400	553	-----------------------------------------------------------------------------------------------
AnnaBridge	172:65be27845400	554	TDES3 \| OWN(31) \| CTRL[30:26] \| Reserved[25:24] \| CTRL[23:20] \| Reserved[19:17] \| Status[16:0] \|
AnnaBridge	172:65be27845400	555	-----------------------------------------------------------------------------------------------
AnnaBridge	172:65be27845400	556	*/
AnnaBridge	172:65be27845400	557
AnnaBridge	172:65be27845400	558	/**
AnnaBridge	172:65be27845400	559	* @brief Bit definition of TDES0 RF register
AnnaBridge	172:65be27845400	560	*/
AnnaBridge	172:65be27845400	561	#define ETH_DMATXNDESCRF_B1AP ((uint32_t)0xFFFFFFFFU) /!< Transmit Packet Timestamp Low /
AnnaBridge	172:65be27845400	562
AnnaBridge	172:65be27845400	563	/**
AnnaBridge	172:65be27845400	564	* @brief Bit definition of TDES1 RF register
AnnaBridge	172:65be27845400	565	*/
AnnaBridge	172:65be27845400	566	#define ETH_DMATXNDESCRF_B2AP ((uint32_t)0xFFFFFFFFU) /!< Transmit Packet Timestamp High /
AnnaBridge	172:65be27845400	567
AnnaBridge	172:65be27845400	568	/**
AnnaBridge	172:65be27845400	569	* @brief Bit definition of TDES2 RF register
AnnaBridge	172:65be27845400	570	*/
AnnaBridge	172:65be27845400	571	#define ETH_DMATXNDESCRF_IOC ((uint32_t)0x80000000U) /!< Interrupt on Completion /
AnnaBridge	172:65be27845400	572	#define ETH_DMATXNDESCRF_TTSE ((uint32_t)0x40000000U) /!< Transmit Timestamp Enable /
AnnaBridge	172:65be27845400	573	#define ETH_DMATXNDESCRF_B2L ((uint32_t)0x3FFF0000U) /!< Buffer 2 Length /
AnnaBridge	172:65be27845400	574	#define ETH_DMATXNDESCRF_VTIR ((uint32_t)0x0000C000U) /!< VLAN Tag Insertion or Replacement mask /
AnnaBridge	172:65be27845400	575	#define ETH_DMATXNDESCRF_VTIR_DISABLE ((uint32_t)0x00000000U) /!< Do not add a VLAN tag. /
AnnaBridge	172:65be27845400	576	#define ETH_DMATXNDESCRF_VTIR_REMOVE ((uint32_t)0x00004000U) /!< Remove the VLAN tag from the packets before transmission. /
AnnaBridge	172:65be27845400	577	#define ETH_DMATXNDESCRF_VTIR_INSERT ((uint32_t)0x00008000U) /!< Insert a VLAN tag. /
AnnaBridge	172:65be27845400	578	#define ETH_DMATXNDESCRF_VTIR_REPLACE ((uint32_t)0x0000C000U) /!< Replace the VLAN tag. /
AnnaBridge	172:65be27845400	579	#define ETH_DMATXNDESCRF_B1L ((uint32_t)0x00003FFFU) /!< Buffer 1 Length /
AnnaBridge	172:65be27845400	580	#define ETH_DMATXNDESCRF_HL ((uint32_t)0x000003FFU) /!< Header Length /
AnnaBridge	172:65be27845400	581
AnnaBridge	172:65be27845400	582	/**
AnnaBridge	172:65be27845400	583	* @brief Bit definition of TDES3 RF register
AnnaBridge	172:65be27845400	584	*/
AnnaBridge	172:65be27845400	585	#define ETH_DMATXNDESCRF_OWN ((uint32_t)0x80000000U) /!< OWN bit: descriptor is owned by DMA engine /
AnnaBridge	172:65be27845400	586	#define ETH_DMATXNDESCRF_CTXT ((uint32_t)0x40000000U) /!< Context Type /
AnnaBridge	172:65be27845400	587	#define ETH_DMATXNDESCRF_FD ((uint32_t)0x20000000U) /!< First Descriptor /
AnnaBridge	172:65be27845400	588	#define ETH_DMATXNDESCRF_LD ((uint32_t)0x10000000U) /!< Last Descriptor /
AnnaBridge	172:65be27845400	589	#define ETH_DMATXNDESCRF_CPC ((uint32_t)0x0C000000U) /!< CRC Pad Control mask /
AnnaBridge	172:65be27845400	590	#define ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT ((uint32_t)0x00000000U) /!< CRC Pad Control: CRC and Pad Insertion /
AnnaBridge	172:65be27845400	591	#define ETH_DMATXNDESCRF_CPC_CRC_INSERT ((uint32_t)0x04000000U) /!< CRC Pad Control: CRC Insertion (Disable Pad Insertion) /
AnnaBridge	172:65be27845400	592	#define ETH_DMATXNDESCRF_CPC_DISABLE ((uint32_t)0x08000000U) /!< CRC Pad Control: Disable CRC Insertion /
AnnaBridge	172:65be27845400	593	#define ETH_DMATXNDESCRF_CPC_CRC_REPLACE ((uint32_t)0x0C000000U) /!< CRC Pad Control: CRC Replacement /
AnnaBridge	172:65be27845400	594	#define ETH_DMATXNDESCRF_SAIC ((uint32_t)0x03800000U) /!< SA Insertion Control mask/
AnnaBridge	172:65be27845400	595	#define ETH_DMATXNDESCRF_SAIC_DISABLE ((uint32_t)0x00000000U) /!< SA Insertion Control: Do not include the source address /
AnnaBridge	172:65be27845400	596	#define ETH_DMATXNDESCRF_SAIC_INSERT ((uint32_t)0x00800000U) /!< SA Insertion Control: Include or insert the source address /
AnnaBridge	172:65be27845400	597	#define ETH_DMATXNDESCRF_SAIC_REPLACE ((uint32_t)0x01000000U) /!< SA Insertion Control: Replace the source address /
AnnaBridge	172:65be27845400	598	#define ETH_DMATXNDESCRF_THL ((uint32_t)0x00780000U) /!< TCP Header Length /
AnnaBridge	172:65be27845400	599	#define ETH_DMATXNDESCRF_TSE ((uint32_t)0x00040000U) /!< TCP segmentation enable /
AnnaBridge	172:65be27845400	600	#define ETH_DMATXNDESCRF_CIC ((uint32_t)0x00030000U) /!< Checksum Insertion Control: 4 cases /
AnnaBridge	172:65be27845400	601	#define ETH_DMATXNDESCRF_CIC_DISABLE ((uint32_t)0x00000000U) /!< Do Nothing: Checksum Engine is disabled /
AnnaBridge	172:65be27845400	602	#define ETH_DMATXNDESCRF_CIC_IPHDR_INSERT ((uint32_t)0x00010000U) /!< Only IP header checksum calculation and insertion are enabled. /
AnnaBridge	172:65be27845400	603	#define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT ((uint32_t)0x00020000U) /*!< IP header checksum and payload checksum calculation and insertion are
AnnaBridge	172:65be27845400	604	enabled, but pseudo header checksum is not calculated in hardware */
AnnaBridge	172:65be27845400	605	#define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC ((uint32_t)0x00030000U) /*!< IP Header checksum and payload checksum calculation and insertion are
AnnaBridge	172:65be27845400	606	enabled, and pseudo header checksum is calculated in hardware. */
AnnaBridge	172:65be27845400	607	#define ETH_DMATXNDESCRF_TPL ((uint32_t)0x0003FFFFU) /!< TCP Payload Length /
AnnaBridge	172:65be27845400	608	#define ETH_DMATXNDESCRF_FL ((uint32_t)0x00007FFFU) /!< Transmit End of Ring /
AnnaBridge	172:65be27845400	609
AnnaBridge	172:65be27845400	610	/*
AnnaBridge	172:65be27845400	611	DMA Tx Normal Descriptor Write Back Format
AnnaBridge	172:65be27845400	612	-----------------------------------------------------------------------------------------------
AnnaBridge	172:65be27845400	613	TDES0 \| Timestamp Low \|
AnnaBridge	172:65be27845400	614	-----------------------------------------------------------------------------------------------
AnnaBridge	172:65be27845400	615	TDES1 \| Timestamp High \|
AnnaBridge	172:65be27845400	616	-----------------------------------------------------------------------------------------------
AnnaBridge	172:65be27845400	617	TDES2 \| Reserved[31:0] \|
AnnaBridge	172:65be27845400	618	-----------------------------------------------------------------------------------------------
AnnaBridge	172:65be27845400	619	TDES3 \| OWN(31) \| Status[30:0] \|
AnnaBridge	172:65be27845400	620	-----------------------------------------------------------------------------------------------
AnnaBridge	172:65be27845400	621	*/
AnnaBridge	172:65be27845400	622
AnnaBridge	172:65be27845400	623	/**
AnnaBridge	172:65be27845400	624	* @brief Bit definition of TDES0 WBF register
AnnaBridge	172:65be27845400	625	*/
AnnaBridge	172:65be27845400	626	#define ETH_DMATXNDESCWBF_TTSL ((uint32_t)0xFFFFFFFFU) /!< Buffer1 Address Pointer or TSO Header Address Pointer /
AnnaBridge	172:65be27845400	627
AnnaBridge	172:65be27845400	628	/**
AnnaBridge	172:65be27845400	629	* @brief Bit definition of TDES1 WBF register
AnnaBridge	172:65be27845400	630	*/
AnnaBridge	172:65be27845400	631	#define ETH_DMATXNDESCWBF_TTSH ((uint32_t)0xFFFFFFFFU) /!< Buffer2 Address Pointer /
AnnaBridge	172:65be27845400	632
AnnaBridge	172:65be27845400	633	/**
AnnaBridge	172:65be27845400	634	* @brief Bit definition of TDES3 WBF register
AnnaBridge	172:65be27845400	635	*/
AnnaBridge	172:65be27845400	636	#define ETH_DMATXNDESCWBF_OWN ((uint32_t)0x80000000U) /!< OWN bit: descriptor is owned by DMA engine /
AnnaBridge	172:65be27845400	637	#define ETH_DMATXNDESCWBF_CTXT ((uint32_t)0x40000000U) /!< Context Type /
AnnaBridge	172:65be27845400	638	#define ETH_DMATXNDESCWBF_FD ((uint32_t)0x20000000U) /!< First Descriptor /
AnnaBridge	172:65be27845400	639	#define ETH_DMATXNDESCWBF_LD ((uint32_t)0x10000000U) /!< Last Descriptor /
AnnaBridge	172:65be27845400	640	#define ETH_DMATXNDESCWBF_TTSS ((uint32_t)0x00020000U) /!< Tx Timestamp Status /
AnnaBridge	172:65be27845400	641	#define ETH_DMATXNDESCWBF_DP ((uint32_t)0x04000000U) /!< Disable Padding /
AnnaBridge	172:65be27845400	642	#define ETH_DMATXNDESCWBF_TTSE ((uint32_t)0x02000000U) /!< Transmit Timestamp Enable /
AnnaBridge	172:65be27845400	643	#define ETH_DMATXNDESCWBF_ES ((uint32_t)0x00008000U) /!< Error summary: OR of the following bits: IHE \|\| UF \|\| ED \|\| EC \|\| LCO \|\| PCE \|\| NC \|\| LCA \|\| FF \|\| JT /
AnnaBridge	172:65be27845400	644	#define ETH_DMATXNDESCWBF_JT ((uint32_t)0x00004000U) /!< Jabber Timeout /
AnnaBridge	172:65be27845400	645	#define ETH_DMATXNDESCWBF_FF ((uint32_t)0x00002000U) /!< Packet Flushed: DMA/MTL flushed the packet due to SW flush /
AnnaBridge	172:65be27845400	646	#define ETH_DMATXNDESCWBF_PCE ((uint32_t)0x00001000U) /!< Payload Checksum Error /
AnnaBridge	172:65be27845400	647	#define ETH_DMATXNDESCWBF_LCA ((uint32_t)0x00000800U) /!< Loss of Carrier: carrier lost during transmission /
AnnaBridge	172:65be27845400	648	#define ETH_DMATXNDESCWBF_NC ((uint32_t)0x00000400U) /!< No Carrier: no carrier signal from the transceiver /
AnnaBridge	172:65be27845400	649	#define ETH_DMATXNDESCWBF_LCO ((uint32_t)0x00000200U) /!< Late Collision: transmission aborted due to collision /
AnnaBridge	172:65be27845400	650	#define ETH_DMATXNDESCWBF_EC ((uint32_t)0x00000100U) /!< Excessive Collision: transmission aborted after 16 collisions /
AnnaBridge	172:65be27845400	651	#define ETH_DMATXNDESCWBF_CC ((uint32_t)0x000000F0U) /!< Collision Count /
AnnaBridge	172:65be27845400	652	#define ETH_DMATXNDESCWBF_ED ((uint32_t)0x00000008U) /!< Excessive Deferral /
AnnaBridge	172:65be27845400	653	#define ETH_DMATXNDESCWBF_UF ((uint32_t)0x00000004U) /!< Underflow Error: late data arrival from the memory /
AnnaBridge	172:65be27845400	654	#define ETH_DMATXNDESCWBF_DB ((uint32_t)0x00000002U) /!< Deferred Bit /
AnnaBridge	172:65be27845400	655	#define ETH_DMATXNDESCWBF_IHE ((uint32_t)0x00000004U) /!< IP Header Error /
AnnaBridge	172:65be27845400	656
AnnaBridge	172:65be27845400	657
AnnaBridge	172:65be27845400	658	/*
AnnaBridge	172:65be27845400	659	DMA Tx Context Desciptor
AnnaBridge	172:65be27845400	660	-----------------------------------------------------------------------------------------------
AnnaBridge	172:65be27845400	661	TDES0 \| Timestamp Low \|
AnnaBridge	172:65be27845400	662	-----------------------------------------------------------------------------------------------
AnnaBridge	172:65be27845400	663	TDES1 \| Timestamp High \|
AnnaBridge	172:65be27845400	664	-----------------------------------------------------------------------------------------------
AnnaBridge	172:65be27845400	665	TDES2 \| Inner VLAN Tag[31:16] \| Reserved(15) \| Maximum Segment Size [14:0] \|
AnnaBridge	172:65be27845400	666	-----------------------------------------------------------------------------------------------
AnnaBridge	172:65be27845400	667	TDES3 \| OWN(31) \| Status[30:0] \|
AnnaBridge	172:65be27845400	668	-----------------------------------------------------------------------------------------------
AnnaBridge	172:65be27845400	669	*/
AnnaBridge	172:65be27845400	670
AnnaBridge	172:65be27845400	671	/**
AnnaBridge	172:65be27845400	672	* @brief Bit definition of Tx context descriptor register 0
AnnaBridge	172:65be27845400	673	*/
AnnaBridge	172:65be27845400	674	#define ETH_DMATXCDESC_TTSL ((uint32_t)0xFFFFFFFFU) /!< Transmit Packet Timestamp Low /
AnnaBridge	172:65be27845400	675
AnnaBridge	172:65be27845400	676	/**
AnnaBridge	172:65be27845400	677	* @brief Bit definition of Tx context descriptor register 1
AnnaBridge	172:65be27845400	678	*/
AnnaBridge	172:65be27845400	679	#define ETH_DMATXCDESC_TTSH ((uint32_t)0xFFFFFFFFU) /!< Transmit Packet Timestamp High /
AnnaBridge	172:65be27845400	680
AnnaBridge	172:65be27845400	681	/**
AnnaBridge	172:65be27845400	682	* @brief Bit definition of Tx context descriptor register 2
AnnaBridge	172:65be27845400	683	*/
AnnaBridge	172:65be27845400	684	#define ETH_DMATXCDESC_IVT ((uint32_t)0xFFFF0000U) /!< Inner VLAN Tag /
AnnaBridge	172:65be27845400	685	#define ETH_DMATXCDESC_MSS ((uint32_t)0x00003FFFU) /!< Maximum Segment Size /
AnnaBridge	172:65be27845400	686
AnnaBridge	172:65be27845400	687	/**
AnnaBridge	172:65be27845400	688	* @brief Bit definition of Tx context descriptor register 3
AnnaBridge	172:65be27845400	689	*/
AnnaBridge	172:65be27845400	690	#define ETH_DMATXCDESC_OWN ((uint32_t)0x80000000U) /!< OWN bit: descriptor is owned by DMA engine /
AnnaBridge	172:65be27845400	691	#define ETH_DMATXCDESC_CTXT ((uint32_t)0x40000000U) /!< Context Type /
AnnaBridge	172:65be27845400	692	#define ETH_DMATXCDESC_OSTC ((uint32_t)0x08000000U) /!< One-Step Timestamp Correction Enable /
AnnaBridge	172:65be27845400	693	#define ETH_DMATXCDESC_TCMSSV ((uint32_t)0x04000000U) /!< One-Step Timestamp Correction Input or MSS Valid /
AnnaBridge	172:65be27845400	694	#define ETH_DMATXCDESC_CDE ((uint32_t)0x00800000U) /!< Context Descriptor Error /
AnnaBridge	172:65be27845400	695	#define ETH_DMATXCDESC_IVTIR ((uint32_t)0x000C0000U) /!< Inner VLAN Tag Insert or Replace Mask /
AnnaBridge	172:65be27845400	696	#define ETH_DMATXCDESC_IVTIR_DISABLE ((uint32_t)0x00000000U) /!< Do not add the inner VLAN tag. /
AnnaBridge	172:65be27845400	697	#define ETH_DMATXCDESC_IVTIR_REMOVE ((uint32_t)0x00040000U) /!< Remove the inner VLAN tag from the packets before transmission. /
AnnaBridge	172:65be27845400	698	#define ETH_DMATXCDESC_IVTIR_INSERT ((uint32_t)0x00080000U) /!< Insert the inner VLAN tag. /
AnnaBridge	172:65be27845400	699	#define ETH_DMATXCDESC_IVTIR_REPLACE ((uint32_t)0x000C0000U) /!< Replace the inner VLAN tag. /
AnnaBridge	172:65be27845400	700	#define ETH_DMATXCDESC_IVLTV ((uint32_t)0x00020000U) /!< Inner VLAN Tag Valid /
AnnaBridge	172:65be27845400	701	#define ETH_DMATXCDESC_VLTV ((uint32_t)0x00010000U) /!< VLAN Tag Valid /
AnnaBridge	172:65be27845400	702	#define ETH_DMATXCDESC_VT ((uint32_t)0x0000FFFFU) /!< VLAN Tag /
AnnaBridge	172:65be27845400	703
AnnaBridge	172:65be27845400	704	/**
AnnaBridge	172:65be27845400	705	* @}
AnnaBridge	172:65be27845400	706	*/
AnnaBridge	172:65be27845400	707
AnnaBridge	172:65be27845400	708
AnnaBridge	172:65be27845400	709	/** @defgroup ETH_DMA_Rx_Descriptor_Bit_Definition ETH DMA Rx Descriptor Bit Definition
AnnaBridge	172:65be27845400	710	* @{
AnnaBridge	172:65be27845400	711	*/
AnnaBridge	172:65be27845400	712
AnnaBridge	172:65be27845400	713	/*
AnnaBridge	172:65be27845400	714	DMA Rx Normal Descriptor read format
AnnaBridge	172:65be27845400	715	-----------------------------------------------------------------------------------------------------------
AnnaBridge	172:65be27845400	716	RDES0 \| Buffer1 or Header Address [31:0] \|
AnnaBridge	172:65be27845400	717	-----------------------------------------------------------------------------------------------------------
AnnaBridge	172:65be27845400	718	RDES1 \| Reserved \|
AnnaBridge	172:65be27845400	719	-----------------------------------------------------------------------------------------------------------
AnnaBridge	172:65be27845400	720	RDES2 \| Payload or Buffer2 Address[31:0] \|
AnnaBridge	172:65be27845400	721	-----------------------------------------------------------------------------------------------------------
AnnaBridge	172:65be27845400	722	RDES3 \| OWN(31) \| IOC(30) \| Reserved [29:26] \| BUF2V(25) \| BUF1V(24) \| Reserved [23:0] \|
AnnaBridge	172:65be27845400	723	-----------------------------------------------------------------------------------------------------------
AnnaBridge	172:65be27845400	724	*/
AnnaBridge	172:65be27845400	725
AnnaBridge	172:65be27845400	726	/**
AnnaBridge	172:65be27845400	727	* @brief Bit definition of Rx normal descriptor register 0 read format
AnnaBridge	172:65be27845400	728	*/
AnnaBridge	172:65be27845400	729	#define ETH_DMARXNDESCRF_BUF1AP ((uint32_t)0xFFFFFFFFU) /!< Header or Buffer 1 Address Pointer /
AnnaBridge	172:65be27845400	730
AnnaBridge	172:65be27845400	731	/**
AnnaBridge	172:65be27845400	732	* @brief Bit definition of Rx normal descriptor register 2 read format
AnnaBridge	172:65be27845400	733	*/
AnnaBridge	172:65be27845400	734	#define ETH_DMARXNDESCRF_BUF2AP ((uint32_t)0xFFFFFFFFU) /!< Buffer 2 Address Pointer /
AnnaBridge	172:65be27845400	735
AnnaBridge	172:65be27845400	736	/**
AnnaBridge	172:65be27845400	737	* @brief Bit definition of Rx normal descriptor register 3 read format
AnnaBridge	172:65be27845400	738	*/
AnnaBridge	172:65be27845400	739	#define ETH_DMARXNDESCRF_OWN ((uint32_t)0x80000000U) /!< OWN bit: descriptor is owned by DMA engine /
AnnaBridge	172:65be27845400	740	#define ETH_DMARXNDESCRF_IOC ((uint32_t)0x40000000U) /!< Interrupt Enabled on Completion /
AnnaBridge	172:65be27845400	741	#define ETH_DMARXNDESCRF_BUF2V ((uint32_t)0x02000000U) /!< Buffer 2 Address Valid /
AnnaBridge	172:65be27845400	742	#define ETH_DMARXNDESCRF_BUF1V ((uint32_t)0x01000000U) /!< Buffer 1 Address Valid /
AnnaBridge	172:65be27845400	743
AnnaBridge	172:65be27845400	744	/*
AnnaBridge	172:65be27845400	745	DMA Rx Normal Descriptor write back format
AnnaBridge	172:65be27845400	746	---------------------------------------------------------------------------------------------------------------------
AnnaBridge	172:65be27845400	747	RDES0 \| Inner VLAN Tag[31:16] \| Outer VLAN Tag[15:0] \|
AnnaBridge	172:65be27845400	748	---------------------------------------------------------------------------------------------------------------------
AnnaBridge	172:65be27845400	749	RDES1 \| OAM code, or MAC Control Opcode [31:16] \| Extended Status \|
AnnaBridge	172:65be27845400	750	---------------------------------------------------------------------------------------------------------------------
AnnaBridge	172:65be27845400	751	RDES2 \| MAC Filter Status[31:16] \| VF(15) \| Reserved [14:12] \| ARP Status [11:10] \| Header Length [9:0] \|
AnnaBridge	172:65be27845400	752	---------------------------------------------------------------------------------------------------------------------
AnnaBridge	172:65be27845400	753	RDES3 \| OWN(31) \| CTXT(30) \| FD(29) \| LD(28) \| Status[27:16] \| ES(15) \| Packet Length[14:0] \|
AnnaBridge	172:65be27845400	754	---------------------------------------------------------------------------------------------------------------------
AnnaBridge	172:65be27845400	755	*/
AnnaBridge	172:65be27845400	756
AnnaBridge	172:65be27845400	757	/**
AnnaBridge	172:65be27845400	758	* @brief Bit definition of Rx normal descriptor register 0 write back format
AnnaBridge	172:65be27845400	759	*/
AnnaBridge	172:65be27845400	760	#define ETH_DMARXNDESCWBF_IVT ((uint32_t)0xFFFF0000U) /!< Inner VLAN Tag /
AnnaBridge	172:65be27845400	761	#define ETH_DMARXNDESCWBF_OVT ((uint32_t)0x0000FFFFU) /!< Outer VLAN Tag /
AnnaBridge	172:65be27845400	762
AnnaBridge	172:65be27845400	763	/**
AnnaBridge	172:65be27845400	764	* @brief Bit definition of Rx normal descriptor register 1 write back format
AnnaBridge	172:65be27845400	765	*/
AnnaBridge	172:65be27845400	766	#define ETH_DMARXNDESCWBF_OPC ((uint32_t)0xFFFF0000U) /!< OAM Sub-Type Code, or MAC Control Packet opcode /
AnnaBridge	172:65be27845400	767	#define ETH_DMARXNDESCWBF_TD ((uint32_t)0x00008000U) /!< Timestamp Dropped /
AnnaBridge	172:65be27845400	768	#define ETH_DMARXNDESCWBF_TSA ((uint32_t)0x00004000U) /!< Timestamp Available /
AnnaBridge	172:65be27845400	769	#define ETH_DMARXNDESCWBF_PV ((uint32_t)0x00002000U) /!< PTP Version /
AnnaBridge	172:65be27845400	770	#define ETH_DMARXNDESCWBF_PFT ((uint32_t)0x00001000U) /!< PTP Packet Type /
AnnaBridge	172:65be27845400	771	#define ETH_DMARXNDESCWBF_PMT_NO ((uint32_t)0x00000000U) /!< PTP Message Type: No PTP message received /
AnnaBridge	172:65be27845400	772	#define ETH_DMARXNDESCWBF_PMT_SYNC ((uint32_t)0x00000100U) /!< PTP Message Type: SYNC (all clock types) /
AnnaBridge	172:65be27845400	773	#define ETH_DMARXNDESCWBF_PMT_FUP ((uint32_t)0x00000200U) /!< PTP Message Type: Follow_Up (all clock types) /
AnnaBridge	172:65be27845400	774	#define ETH_DMARXNDESCWBF_PMT_DREQ ((uint32_t)0x00000300U) /!< PTP Message Type: Delay_Req (all clock types) /
AnnaBridge	172:65be27845400	775	#define ETH_DMARXNDESCWBF_PMT_DRESP ((uint32_t)0x00000400U) /!< PTP Message Type: Delay_Resp (all clock types) /
AnnaBridge	172:65be27845400	776	#define ETH_DMARXNDESCWBF_PMT_PDREQ ((uint32_t)0x00000500U) /!< PTP Message Type: Pdelay_Req (in peer-to-peer transparent clock) /
AnnaBridge	172:65be27845400	777	#define ETH_DMARXNDESCWBF_PMT_PDRESP ((uint32_t)0x00000600U) /!< PTP Message Type: Pdelay_Resp (in peer-to-peer transparent clock) /
AnnaBridge	172:65be27845400	778	#define ETH_DMARXNDESCWBF_PMT_PDRESPFUP ((uint32_t)0x00000700U) /!< PTP Message Type: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock) /
AnnaBridge	172:65be27845400	779	#define ETH_DMARXNDESCWBF_PMT_ANNOUNCE ((uint32_t)0x00000800U) /!< PTP Message Type: Announce /
AnnaBridge	172:65be27845400	780	#define ETH_DMARXNDESCWBF_PMT_MANAG ((uint32_t)0x00000900U) /!< PTP Message Type: Management /
AnnaBridge	172:65be27845400	781	#define ETH_DMARXNDESCWBF_PMT_SIGN ((uint32_t)0x00000A00U) /!< PTP Message Type: Signaling /
AnnaBridge	172:65be27845400	782	#define ETH_DMARXNDESCWBF_PMT_RESERVED ((uint32_t)0x00000F00U) /!< PTP Message Type: PTP packet with Reserved message type /
AnnaBridge	172:65be27845400	783	#define ETH_DMARXNDESCWBF_IPCE ((uint32_t)0x00000080U) /!< IP Payload Error /
AnnaBridge	172:65be27845400	784	#define ETH_DMARXNDESCWBF_IPCB ((uint32_t)0x00000040U) /!< IP Checksum Bypassed /
AnnaBridge	172:65be27845400	785	#define ETH_DMARXNDESCWBF_IPV6 ((uint32_t)0x00000020U) /!< IPv6 header Present /
AnnaBridge	172:65be27845400	786	#define ETH_DMARXNDESCWBF_IPV4 ((uint32_t)0x00000010U) /!< IPv4 header Present /
AnnaBridge	172:65be27845400	787	#define ETH_DMARXNDESCWBF_IPHE ((uint32_t)0x00000008U) /!< IP Header Error /
AnnaBridge	172:65be27845400	788	#define ETH_DMARXNDESCWBF_PT ((uint32_t)0x00000003U) /!< Payload Type mask /
AnnaBridge	172:65be27845400	789	#define ETH_DMARXNDESCWBF_PT_UNKNOWN ((uint32_t)0x00000000U) /!< Payload Type: Unknown type or IP/AV payload not processed /
AnnaBridge	172:65be27845400	790	#define ETH_DMARXNDESCWBF_PT_UDP ((uint32_t)0x00000001U) /!< Payload Type: UDP /
AnnaBridge	172:65be27845400	791	#define ETH_DMARXNDESCWBF_PT_TCP ((uint32_t)0x00000002U) /!< Payload Type: TCP /
AnnaBridge	172:65be27845400	792	#define ETH_DMARXNDESCWBF_PT_ICMP ((uint32_t)0x00000003U) /!< Payload Type: ICMP /
AnnaBridge	172:65be27845400	793
AnnaBridge	172:65be27845400	794	/**
AnnaBridge	172:65be27845400	795	* @brief Bit definition of Rx normal descriptor register 2 write back format
AnnaBridge	172:65be27845400	796	*/
AnnaBridge	172:65be27845400	797	#define ETH_DMARXNDESCWBF_L3L4FM ((uint32_t)0x20000000U) /!< L3 and L4 Filter Number Matched: if reset filter 0 is matched , if set filter 1 is matched /
AnnaBridge	172:65be27845400	798	#define ETH_DMARXNDESCWBF_L4FM ((uint32_t)0x10000000U) /!< Layer 4 Filter Match /
AnnaBridge	172:65be27845400	799	#define ETH_DMARXNDESCWBF_L3FM ((uint32_t)0x08000000U) /!< Layer 3 Filter Match /
AnnaBridge	172:65be27845400	800	#define ETH_DMARXNDESCWBF_MADRM ((uint32_t)0x07F80000U) /!< MAC Address Match or Hash Value /
AnnaBridge	172:65be27845400	801	#define ETH_DMARXNDESCWBF_HF ((uint32_t)0x00040000U) /!< Hash Filter Status /
AnnaBridge	172:65be27845400	802	#define ETH_DMARXNDESCWBF_DAF ((uint32_t)0x00020000U) /!< Destination Address Filter Fail /
AnnaBridge	172:65be27845400	803	#define ETH_DMARXNDESCWBF_SAF ((uint32_t)0x00010000U) /!< SA Address Filter Fail /
AnnaBridge	172:65be27845400	804	#define ETH_DMARXNDESCWBF_VF ((uint32_t)0x00008000U) /!< VLAN Filter Status /
AnnaBridge	172:65be27845400	805	#define ETH_DMARXNDESCWBF_ARPNR ((uint32_t)0x00000400U) /!< ARP Reply Not Generated /
AnnaBridge	172:65be27845400	806
AnnaBridge	172:65be27845400	807
AnnaBridge	172:65be27845400	808	/**
AnnaBridge	172:65be27845400	809	* @brief Bit definition of Rx normal descriptor register 3 write back format
AnnaBridge	172:65be27845400	810	*/
AnnaBridge	172:65be27845400	811	#define ETH_DMARXNDESCWBF_OWN ((uint32_t)0x80000000U) /!< Own Bit /
AnnaBridge	172:65be27845400	812	#define ETH_DMARXNDESCWBF_CTXT ((uint32_t)0x40000000U) /!< Receive Context Descriptor /
AnnaBridge	172:65be27845400	813	#define ETH_DMARXNDESCWBF_FD ((uint32_t)0x20000000U) /!< First Descriptor /
AnnaBridge	172:65be27845400	814	#define ETH_DMARXNDESCWBF_LD ((uint32_t)0x10000000U) /!< Last Descriptor /
AnnaBridge	172:65be27845400	815	#define ETH_DMARXNDESCWBF_RS2V ((uint32_t)0x08000000U) /!< Receive Status RDES2 Valid /
AnnaBridge	172:65be27845400	816	#define ETH_DMARXNDESCWBF_RS1V ((uint32_t)0x04000000U) /!< Receive Status RDES1 Valid /
AnnaBridge	172:65be27845400	817	#define ETH_DMARXNDESCWBF_RS0V ((uint32_t)0x02000000U) /!< Receive Status RDES0 Valid /
AnnaBridge	172:65be27845400	818	#define ETH_DMARXNDESCWBF_CE ((uint32_t)0x01000000U) /!< CRC Error /
AnnaBridge	172:65be27845400	819	#define ETH_DMARXNDESCWBF_GP ((uint32_t)0x00800000U) /!< Giant Packet /
AnnaBridge	172:65be27845400	820	#define ETH_DMARXNDESCWBF_RWT ((uint32_t)0x00400000U) /!< Receive Watchdog Timeout /
AnnaBridge	172:65be27845400	821	#define ETH_DMARXNDESCWBF_OE ((uint32_t)0x00200000U) /!< Overflow Error /
AnnaBridge	172:65be27845400	822	#define ETH_DMARXNDESCWBF_RE ((uint32_t)0x00100000U) /!< Receive Error /
AnnaBridge	172:65be27845400	823	#define ETH_DMARXNDESCWBF_DE ((uint32_t)0x00080000U) /!< Dribble Bit Error /
AnnaBridge	172:65be27845400	824	#define ETH_DMARXNDESCWBF_LT ((uint32_t)0x00070000U) /!< Length/Type Field /
AnnaBridge	172:65be27845400	825	#define ETH_DMARXNDESCWBF_LT_LP ((uint32_t)0x00000000U) /!< The packet is a length packet /
AnnaBridge	172:65be27845400	826	#define ETH_DMARXNDESCWBF_LT_TP ((uint32_t)0x00010000U) /!< The packet is a type packet /
AnnaBridge	172:65be27845400	827	#define ETH_DMARXNDESCWBF_LT_ARP ((uint32_t)0x00030000U) /!< The packet is a ARP Request packet type /
AnnaBridge	172:65be27845400	828	#define ETH_DMARXNDESCWBF_LT_VLAN ((uint32_t)0x00040000U) /!< The packet is a type packet with VLAN Tag /
AnnaBridge	172:65be27845400	829	#define ETH_DMARXNDESCWBF_LT_DVLAN ((uint32_t)0x00050000U) /!< The packet is a type packet with Double VLAN Tag /
AnnaBridge	172:65be27845400	830	#define ETH_DMARXNDESCWBF_LT_MAC ((uint32_t)0x00060000U) /!< The packet is a MAC Control packet type /
AnnaBridge	172:65be27845400	831	#define ETH_DMARXNDESCWBF_LT_OAM ((uint32_t)0x00070000U) /!< The packet is a OAM packet type /
AnnaBridge	172:65be27845400	832	#define ETH_DMARXNDESCWBF_ES ((uint32_t)0x00008000U) /!< Error Summary /
AnnaBridge	172:65be27845400	833	#define ETH_DMARXNDESCWBF_PL ((uint32_t)0x00007FFFU) /!< Packet Length /
AnnaBridge	172:65be27845400	834
AnnaBridge	172:65be27845400	835	/*
AnnaBridge	172:65be27845400	836	DMA Rx context Descriptor
AnnaBridge	172:65be27845400	837	---------------------------------------------------------------------------------------------------------------------
AnnaBridge	172:65be27845400	838	RDES0 \| Timestamp Low[31:0] \|
AnnaBridge	172:65be27845400	839	---------------------------------------------------------------------------------------------------------------------
AnnaBridge	172:65be27845400	840	RDES1 \| Timestamp High[31:0] \|
AnnaBridge	172:65be27845400	841	---------------------------------------------------------------------------------------------------------------------
AnnaBridge	172:65be27845400	842	RDES2 \| Reserved \|
AnnaBridge	172:65be27845400	843	---------------------------------------------------------------------------------------------------------------------
AnnaBridge	172:65be27845400	844	RDES3 \| OWN(31) \| CTXT(30) \| Reserved[29:0] \|
AnnaBridge	172:65be27845400	845	---------------------------------------------------------------------------------------------------------------------
AnnaBridge	172:65be27845400	846	*/
AnnaBridge	172:65be27845400	847
AnnaBridge	172:65be27845400	848	/**
AnnaBridge	172:65be27845400	849	* @brief Bit definition of Rx context descriptor register 0
AnnaBridge	172:65be27845400	850	*/
AnnaBridge	172:65be27845400	851	#define ETH_DMARXCDESC_RTSL ((uint32_t)0xFFFFFFFFU) /!< Receive Packet Timestamp Low /
AnnaBridge	172:65be27845400	852
AnnaBridge	172:65be27845400	853	/**
AnnaBridge	172:65be27845400	854	* @brief Bit definition of Rx context descriptor register 1
AnnaBridge	172:65be27845400	855	*/
AnnaBridge	172:65be27845400	856	#define ETH_DMARXCDESC_RTSH ((uint32_t)0xFFFFFFFFU) /!< Receive Packet Timestamp High /
AnnaBridge	172:65be27845400	857
AnnaBridge	172:65be27845400	858	/**
AnnaBridge	172:65be27845400	859	* @brief Bit definition of Rx context descriptor register 3
AnnaBridge	172:65be27845400	860	*/
AnnaBridge	172:65be27845400	861	#define ETH_DMARXCDESC_OWN ((uint32_t)0x80000000U) /!< Own Bit /
AnnaBridge	172:65be27845400	862	#define ETH_DMARXCDESC_CTXT ((uint32_t)0x40000000U) /!< Receive Context Descriptor /
AnnaBridge	172:65be27845400	863
AnnaBridge	172:65be27845400	864	/**
AnnaBridge	172:65be27845400	865	* @}
AnnaBridge	172:65be27845400	866	*/
AnnaBridge	172:65be27845400	867
AnnaBridge	172:65be27845400	868	/** @defgroup ETH_Frame_settings ETH frame settings
AnnaBridge	172:65be27845400	869	* @{
AnnaBridge	172:65be27845400	870	*/
AnnaBridge	172:65be27845400	871	#define ETH_MAX_PACKET_SIZE ((uint32_t)1528U) /!< ETH_HEADER + 2VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */
AnnaBridge	172:65be27845400	872	#define ETH_HEADER ((uint32_t)14U) /!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type /
AnnaBridge	172:65be27845400	873	#define ETH_CRC ((uint32_t)4U) /!< Ethernet CRC /
AnnaBridge	172:65be27845400	874	#define ETH_VLAN_TAG ((uint32_t)4U) /!< optional 802.1q VLAN Tag /
AnnaBridge	172:65be27845400	875	#define ETH_MIN_PAYLOAD ((uint32_t)46U) /!< Minimum Ethernet payload size /
AnnaBridge	172:65be27845400	876	#define ETH_MAX_PAYLOAD ((uint32_t)1500U) /!< Maximum Ethernet payload size /
AnnaBridge	172:65be27845400	877	#define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000U) /!< Jumbo frame payload size /
AnnaBridge	172:65be27845400	878	/**
AnnaBridge	172:65be27845400	879	* @}
AnnaBridge	172:65be27845400	880	*/
AnnaBridge	172:65be27845400	881
AnnaBridge	172:65be27845400	882	/** @defgroup ETH_Error_Code ETH Error Code
AnnaBridge	172:65be27845400	883	* @{
AnnaBridge	172:65be27845400	884	*/
AnnaBridge	172:65be27845400	885	#define HAL_ETH_ERROR_NONE ((uint32_t)0x00000000U) /!< No error /
AnnaBridge	172:65be27845400	886	#define HAL_ETH_ERROR_PARAM ((uint32_t)0x00000001U) /!< Busy error /
AnnaBridge	172:65be27845400	887	#define HAL_ETH_ERROR_BUSY ((uint32_t)0x00000002U) /!< Parameter error /
AnnaBridge	172:65be27845400	888	#define HAL_ETH_ERROR_TIMEOUT ((uint32_t)0x00000004U) /!< Timeout error /
AnnaBridge	172:65be27845400	889	#define HAL_ETH_ERROR_DMA ((uint32_t)0x00000008U) /!< DMA transfer error /
AnnaBridge	172:65be27845400	890	#define HAL_ETH_ERROR_MAC ((uint32_t)0x00000010U) /!< MAC transfer error /
AnnaBridge	172:65be27845400	891	#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
AnnaBridge	172:65be27845400	892	#define HAL_ETH_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /!< Invalid Callback error /
AnnaBridge	172:65be27845400	893	#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
AnnaBridge	172:65be27845400	894	/**
AnnaBridge	172:65be27845400	895	* @}
AnnaBridge	172:65be27845400	896	*/
AnnaBridge	172:65be27845400	897
AnnaBridge	172:65be27845400	898	/** @defgroup ETH_Tx_Packet_Attributes ETH Tx Packet Attributes
AnnaBridge	172:65be27845400	899	* @{
AnnaBridge	172:65be27845400	900	*/
AnnaBridge	172:65be27845400	901	#define ETH_TX_PACKETS_FEATURES_CSUM ((uint32_t)0x00000001U)
AnnaBridge	172:65be27845400	902	#define ETH_TX_PACKETS_FEATURES_SAIC ((uint32_t)0x00000002U)
AnnaBridge	172:65be27845400	903	#define ETH_TX_PACKETS_FEATURES_VLANTAG ((uint32_t)0x00000004U)
AnnaBridge	172:65be27845400	904	#define ETH_TX_PACKETS_FEATURES_INNERVLANTAG ((uint32_t)0x00000008U)
AnnaBridge	172:65be27845400	905	#define ETH_TX_PACKETS_FEATURES_TSO ((uint32_t)0x00000010U)
AnnaBridge	172:65be27845400	906	#define ETH_TX_PACKETS_FEATURES_CRCPAD ((uint32_t)0x00000020U)
AnnaBridge	172:65be27845400	907	/**
AnnaBridge	172:65be27845400	908	* @}
AnnaBridge	172:65be27845400	909	*/
AnnaBridge	172:65be27845400	910
AnnaBridge	172:65be27845400	911	/** @defgroup ETH_Tx_Packet_Source_Addr_Control ETH Tx Packet Source Addr Control
AnnaBridge	172:65be27845400	912	* @{
AnnaBridge	172:65be27845400	913	*/
AnnaBridge	172:65be27845400	914	#define ETH_SRC_ADDR_CONTROL_DISABLE ETH_DMATXNDESCRF_SAIC_DISABLE
AnnaBridge	172:65be27845400	915	#define ETH_SRC_ADDR_INSERT ETH_DMATXNDESCRF_SAIC_INSERT
AnnaBridge	172:65be27845400	916	#define ETH_SRC_ADDR_REPLACE ETH_DMATXNDESCRF_SAIC_REPLACE
AnnaBridge	172:65be27845400	917	/**
AnnaBridge	172:65be27845400	918	* @}
AnnaBridge	172:65be27845400	919	*/
AnnaBridge	172:65be27845400	920
AnnaBridge	172:65be27845400	921	/** @defgroup ETH_Tx_Packet_CRC_Pad_Control ETH Tx Packet CRC Pad Control
AnnaBridge	172:65be27845400	922	* @{
AnnaBridge	172:65be27845400	923	*/
AnnaBridge	172:65be27845400	924	#define ETH_CRC_PAD_DISABLE ETH_DMATXNDESCRF_CPC_DISABLE
AnnaBridge	172:65be27845400	925	#define ETH_CRC_PAD_INSERT ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT
AnnaBridge	172:65be27845400	926	#define ETH_CRC_INSERT ETH_DMATXNDESCRF_CPC_CRC_INSERT
AnnaBridge	172:65be27845400	927	#define ETH_CRC_REPLACE ETH_DMATXNDESCRF_CPC_CRC_REPLACE
AnnaBridge	172:65be27845400	928	/**
AnnaBridge	172:65be27845400	929	* @}
AnnaBridge	172:65be27845400	930	*/
AnnaBridge	172:65be27845400	931
AnnaBridge	172:65be27845400	932	/** @defgroup ETH_Tx_Packet_Checksum_Control ETH Tx Packet Checksum Control
AnnaBridge	172:65be27845400	933	* @{
AnnaBridge	172:65be27845400	934	*/
AnnaBridge	172:65be27845400	935	#define ETH_CHECKSUM_DISABLE ETH_DMATXNDESCRF_CIC_DISABLE
AnnaBridge	172:65be27845400	936	#define ETH_CHECKSUM_IPHDR_INSERT ETH_DMATXNDESCRF_CIC_IPHDR_INSERT
AnnaBridge	172:65be27845400	937	#define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT
AnnaBridge	172:65be27845400	938	#define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC
AnnaBridge	172:65be27845400	939	/**
AnnaBridge	172:65be27845400	940	* @}
AnnaBridge	172:65be27845400	941	*/
AnnaBridge	172:65be27845400	942
AnnaBridge	172:65be27845400	943	/** @defgroup ETH_Tx_Packet_VLAN_Control ETH Tx Packet VLAN Control
AnnaBridge	172:65be27845400	944	* @{
AnnaBridge	172:65be27845400	945	*/
AnnaBridge	172:65be27845400	946	#define ETH_VLAN_DISABLE ETH_DMATXNDESCRF_VTIR_DISABLE
AnnaBridge	172:65be27845400	947	#define ETH_VLAN_REMOVE ETH_DMATXNDESCRF_VTIR_REMOVE
AnnaBridge	172:65be27845400	948	#define ETH_VLAN_INSERT ETH_DMATXNDESCRF_VTIR_INSERT
AnnaBridge	172:65be27845400	949	#define ETH_VLAN_REPLACE ETH_DMATXNDESCRF_VTIR_REPLACE
AnnaBridge	172:65be27845400	950	/**
AnnaBridge	172:65be27845400	951	* @}
AnnaBridge	172:65be27845400	952	*/
AnnaBridge	172:65be27845400	953
AnnaBridge	172:65be27845400	954	/** @defgroup ETH_Tx_Packet_Inner_VLAN_Control ETH Tx Packet Inner VLAN Control
AnnaBridge	172:65be27845400	955	* @{
AnnaBridge	172:65be27845400	956	*/
AnnaBridge	172:65be27845400	957	#define ETH_INNER_VLAN_DISABLE ETH_DMATXCDESC_IVTIR_DISABLE
AnnaBridge	172:65be27845400	958	#define ETH_INNER_VLAN_REMOVE ETH_DMATXCDESC_IVTIR_REMOVE
AnnaBridge	172:65be27845400	959	#define ETH_INNER_VLAN_INSERT ETH_DMATXCDESC_IVTIR_INSERT
AnnaBridge	172:65be27845400	960	#define ETH_INNER_VLAN_REPLACE ETH_DMATXCDESC_IVTIR_REPLACE
AnnaBridge	172:65be27845400	961	/**
AnnaBridge	172:65be27845400	962	* @}
AnnaBridge	172:65be27845400	963	*/
AnnaBridge	172:65be27845400	964
AnnaBridge	172:65be27845400	965	/** @defgroup ETH_Rx_Checksum_Status ETH Rx Checksum Status
AnnaBridge	172:65be27845400	966	* @{
AnnaBridge	172:65be27845400	967	*/
AnnaBridge	172:65be27845400	968	#define ETH_CHECKSUM_BYPASSED ETH_DMARXNDESCWBF_IPCB
AnnaBridge	172:65be27845400	969	#define ETH_CHECKSUM_IP_HEADER_ERROR ETH_DMARXNDESCWBF_IPHE
AnnaBridge	172:65be27845400	970	#define ETH_CHECKSUM_IP_PAYLOAD_ERROR ETH_DMARXNDESCWBF_IPCE
AnnaBridge	172:65be27845400	971	/**
AnnaBridge	172:65be27845400	972	* @}
AnnaBridge	172:65be27845400	973	*/
AnnaBridge	172:65be27845400	974
AnnaBridge	172:65be27845400	975	/** @defgroup ETH_Rx_IP_Header_Type ETH Rx IP Header Type
AnnaBridge	172:65be27845400	976	* @{
AnnaBridge	172:65be27845400	977	*/
AnnaBridge	172:65be27845400	978	#define ETH_IP_HEADER_IPV4 ETH_DMARXNDESCWBF_IPV4
AnnaBridge	172:65be27845400	979	#define ETH_IP_HEADER_IPV6 ETH_DMARXNDESCWBF_IPV6
AnnaBridge	172:65be27845400	980	/**
AnnaBridge	172:65be27845400	981	* @}
AnnaBridge	172:65be27845400	982	*/
AnnaBridge	172:65be27845400	983
AnnaBridge	172:65be27845400	984	/** @defgroup ETH_Rx_Payload_Type ETH Rx Payload Type
AnnaBridge	172:65be27845400	985	* @{
AnnaBridge	172:65be27845400	986	*/
AnnaBridge	172:65be27845400	987	#define ETH_IP_PAYLOAD_UNKNOWN ETH_DMARXNDESCWBF_PT_UNKNOWN
AnnaBridge	172:65be27845400	988	#define ETH_IP_PAYLOAD_UDP ETH_DMARXNDESCWBF_PT_UDP
AnnaBridge	172:65be27845400	989	#define ETH_IP_PAYLOAD_TCP ETH_DMARXNDESCWBF_PT_TCP
AnnaBridge	172:65be27845400	990	#define ETH_IP_PAYLOAD_ICMPN ETH_DMARXNDESCWBF_PT_ICMP
AnnaBridge	172:65be27845400	991	/**
AnnaBridge	172:65be27845400	992	* @}
AnnaBridge	172:65be27845400	993	*/
AnnaBridge	172:65be27845400	994
AnnaBridge	172:65be27845400	995	/** @defgroup ETH_Rx_MAC_Filter_Status ETH Rx MAC Filter Status
AnnaBridge	172:65be27845400	996	* @{
AnnaBridge	172:65be27845400	997	*/
AnnaBridge	172:65be27845400	998	#define ETH_HASH_FILTER_PASS ETH_DMARXNDESCWBF_HF
AnnaBridge	172:65be27845400	999	#define ETH_VLAN_FILTER_PASS ETH_DMARXNDESCWBF_VF
AnnaBridge	172:65be27845400	1000	#define ETH_DEST_ADDRESS_FAIL ETH_DMARXNDESCWBF_DAF
AnnaBridge	172:65be27845400	1001	#define ETH_SOURCE_ADDRESS_FAIL ETH_DMARXNDESCWBF_SAF
AnnaBridge	172:65be27845400	1002	/**
AnnaBridge	172:65be27845400	1003	* @}
AnnaBridge	172:65be27845400	1004	*/
AnnaBridge	172:65be27845400	1005
AnnaBridge	172:65be27845400	1006	/** @defgroup ETH_Rx_L3_Filter_Status ETH Rx L3 Filter Status
AnnaBridge	172:65be27845400	1007	* @{
AnnaBridge	172:65be27845400	1008	*/
AnnaBridge	172:65be27845400	1009	#define ETH_L3_FILTER0_MATCH ETH_DMARXNDESCWBF_L3FM
AnnaBridge	172:65be27845400	1010	#define ETH_L3_FILTER1_MATCH (ETH_DMARXNDESCWBF_L3FM \| ETH_DMARXNDESCWBF_L3L4FM)
AnnaBridge	172:65be27845400	1011	/**
AnnaBridge	172:65be27845400	1012	* @}
AnnaBridge	172:65be27845400	1013	*/
AnnaBridge	172:65be27845400	1014
AnnaBridge	172:65be27845400	1015	/** @defgroup ETH_Rx_L4_Filter_Status ETH Rx L4 Filter Status
AnnaBridge	172:65be27845400	1016	* @{
AnnaBridge	172:65be27845400	1017	*/
AnnaBridge	172:65be27845400	1018	#define ETH_L4_FILTER0_MATCH ETH_DMARXNDESCWBF_L4FM
AnnaBridge	172:65be27845400	1019	#define ETH_L4_FILTER1_MATCH (ETH_DMARXNDESCWBF_L4FM \| ETH_DMARXNDESCWBF_L3L4FM)
AnnaBridge	172:65be27845400	1020	/**
AnnaBridge	172:65be27845400	1021	* @}
AnnaBridge	172:65be27845400	1022	*/
AnnaBridge	172:65be27845400	1023
AnnaBridge	172:65be27845400	1024	/** @defgroup ETH_Rx_Error_Code ETH Rx Error Code
AnnaBridge	172:65be27845400	1025	* @{
AnnaBridge	172:65be27845400	1026	*/
AnnaBridge	172:65be27845400	1027	#define ETH_DRIBBLE_BIT_ERROR ETH_DMARXNDESCWBF_DE
AnnaBridge	172:65be27845400	1028	#define ETH_RECEIVE_ERROR ETH_DMARXNDESCWBF_RE
AnnaBridge	172:65be27845400	1029	#define ETH_RECEIVE_OVERFLOW ETH_DMARXNDESCWBF_OE
AnnaBridge	172:65be27845400	1030	#define ETH_WATCHDOG_TIMEOUT ETH_DMARXNDESCWBF_RWT
AnnaBridge	172:65be27845400	1031	#define ETH_GIANT_PACKET ETH_DMARXNDESCWBF_GP
AnnaBridge	172:65be27845400	1032	#define ETH_CRC_ERROR ETH_DMARXNDESCWBF_CE
AnnaBridge	172:65be27845400	1033	/**
AnnaBridge	172:65be27845400	1034	* @}
AnnaBridge	172:65be27845400	1035	*/
AnnaBridge	172:65be27845400	1036
AnnaBridge	172:65be27845400	1037	/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
AnnaBridge	172:65be27845400	1038	* @{
AnnaBridge	172:65be27845400	1039	*/
AnnaBridge	172:65be27845400	1040	#define ETH_DMAARBITRATION_RX ETH_DMAMR_DA
AnnaBridge	172:65be27845400	1041	#define ETH_DMAARBITRATION_RX1_TX1 ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	1042	#define ETH_DMAARBITRATION_RX2_TX1 ETH_DMAMR_PR_2_1
AnnaBridge	172:65be27845400	1043	#define ETH_DMAARBITRATION_RX3_TX1 ETH_DMAMR_PR_3_1
AnnaBridge	172:65be27845400	1044	#define ETH_DMAARBITRATION_RX4_TX1 ETH_DMAMR_PR_4_1
AnnaBridge	172:65be27845400	1045	#define ETH_DMAARBITRATION_RX5_TX1 ETH_DMAMR_PR_5_1
AnnaBridge	172:65be27845400	1046	#define ETH_DMAARBITRATION_RX6_TX1 ETH_DMAMR_PR_6_1
AnnaBridge	172:65be27845400	1047	#define ETH_DMAARBITRATION_RX7_TX1 ETH_DMAMR_PR_7_1
AnnaBridge	172:65be27845400	1048	#define ETH_DMAARBITRATION_RX8_TX1 ETH_DMAMR_PR_8_1
AnnaBridge	172:65be27845400	1049	#define ETH_DMAARBITRATION_TX (ETH_DMAMR_TXPR \| ETH_DMAMR_DA)
AnnaBridge	172:65be27845400	1050	#define ETH_DMAARBITRATION_TX1_RX1 ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	1051	#define ETH_DMAARBITRATION_TX2_RX1 (ETH_DMAMR_TXPR \| ETH_DMAMR_PR_2_1)
AnnaBridge	172:65be27845400	1052	#define ETH_DMAARBITRATION_TX3_RX1 (ETH_DMAMR_TXPR \| ETH_DMAMR_PR_3_1)
AnnaBridge	172:65be27845400	1053	#define ETH_DMAARBITRATION_TX4_RX1 (ETH_DMAMR_TXPR \| ETH_DMAMR_PR_4_1)
AnnaBridge	172:65be27845400	1054	#define ETH_DMAARBITRATION_TX5_RX1 (ETH_DMAMR_TXPR \| ETH_DMAMR_PR_5_1)
AnnaBridge	172:65be27845400	1055	#define ETH_DMAARBITRATION_TX6_RX1 (ETH_DMAMR_TXPR \| ETH_DMAMR_PR_6_1)
AnnaBridge	172:65be27845400	1056	#define ETH_DMAARBITRATION_TX7_RX1 (ETH_DMAMR_TXPR \| ETH_DMAMR_PR_7_1)
AnnaBridge	172:65be27845400	1057	#define ETH_DMAARBITRATION_TX8_RX1 (ETH_DMAMR_TXPR \| ETH_DMAMR_PR_8_1)
AnnaBridge	172:65be27845400	1058	/**
AnnaBridge	172:65be27845400	1059	* @}
AnnaBridge	172:65be27845400	1060	*/
AnnaBridge	172:65be27845400	1061
AnnaBridge	172:65be27845400	1062	/** @defgroup ETH_Burst_Mode ETH Burst Mode
AnnaBridge	172:65be27845400	1063	* @{
AnnaBridge	172:65be27845400	1064	*/
AnnaBridge	172:65be27845400	1065	#define ETH_BURSTLENGTH_FIXED ETH_DMASBMR_FB
AnnaBridge	172:65be27845400	1066	#define ETH_BURSTLENGTH_MIXED ETH_DMASBMR_MB
AnnaBridge	172:65be27845400	1067	#define ETH_BURSTLENGTH_UNSPECIFIED ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	1068	/**
AnnaBridge	172:65be27845400	1069	* @}
AnnaBridge	172:65be27845400	1070	*/
AnnaBridge	172:65be27845400	1071
AnnaBridge	172:65be27845400	1072	/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
AnnaBridge	172:65be27845400	1073	* @{
AnnaBridge	172:65be27845400	1074	*/
AnnaBridge	172:65be27845400	1075	#define ETH_TXDMABURSTLENGTH_1BEAT ETH_DMACTCR_TPBL_1PBL
AnnaBridge	172:65be27845400	1076	#define ETH_TXDMABURSTLENGTH_2BEAT ETH_DMACTCR_TPBL_2PBL
AnnaBridge	172:65be27845400	1077	#define ETH_TXDMABURSTLENGTH_4BEAT ETH_DMACTCR_TPBL_4PBL
AnnaBridge	172:65be27845400	1078	#define ETH_TXDMABURSTLENGTH_8BEAT ETH_DMACTCR_TPBL_8PBL
AnnaBridge	172:65be27845400	1079	#define ETH_TXDMABURSTLENGTH_16BEAT ETH_DMACTCR_TPBL_16PBL
AnnaBridge	172:65be27845400	1080	#define ETH_TXDMABURSTLENGTH_32BEAT ETH_DMACTCR_TPBL_32PBL
AnnaBridge	172:65be27845400	1081	/**
AnnaBridge	172:65be27845400	1082	* @}
AnnaBridge	172:65be27845400	1083	*/
AnnaBridge	172:65be27845400	1084
AnnaBridge	172:65be27845400	1085	/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
AnnaBridge	172:65be27845400	1086	* @{
AnnaBridge	172:65be27845400	1087	*/
AnnaBridge	172:65be27845400	1088	#define ETH_RXDMABURSTLENGTH_1BEAT ETH_DMACRCR_RPBL_1PBL
AnnaBridge	172:65be27845400	1089	#define ETH_RXDMABURSTLENGTH_2BEAT ETH_DMACRCR_RPBL_2PBL
AnnaBridge	172:65be27845400	1090	#define ETH_RXDMABURSTLENGTH_4BEAT ETH_DMACRCR_RPBL_4PBL
AnnaBridge	172:65be27845400	1091	#define ETH_RXDMABURSTLENGTH_8BEAT ETH_DMACRCR_RPBL_8PBL
AnnaBridge	172:65be27845400	1092	#define ETH_RXDMABURSTLENGTH_16BEAT ETH_DMACRCR_RPBL_16PBL
AnnaBridge	172:65be27845400	1093	#define ETH_RXDMABURSTLENGTH_32BEAT ETH_DMACRCR_RPBL_32PBL
AnnaBridge	172:65be27845400	1094	/**
AnnaBridge	172:65be27845400	1095	* @}
AnnaBridge	172:65be27845400	1096	*/
AnnaBridge	172:65be27845400	1097
AnnaBridge	172:65be27845400	1098	/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
AnnaBridge	172:65be27845400	1099	* @{
AnnaBridge	172:65be27845400	1100	*/
AnnaBridge	172:65be27845400	1101	#define ETH_DMA_NORMAL_IT ETH_DMACIER_NIE
AnnaBridge	172:65be27845400	1102	#define ETH_DMA_ABNORMAL_IT ETH_DMACIER_AIE
AnnaBridge	172:65be27845400	1103	#define ETH_DMA_CONTEXT_DESC_ERROR_IT ETH_DMACIER_CDEE
AnnaBridge	172:65be27845400	1104	#define ETH_DMA_FATAL_BUS_ERROR_IT ETH_DMACIER_FBEE
AnnaBridge	172:65be27845400	1105	#define ETH_DMA_EARLY_RX_IT ETH_DMACIER_ERIE
AnnaBridge	172:65be27845400	1106	#define ETH_DMA_EARLY_TX_IT ETH_DMACIER_ETIE
AnnaBridge	172:65be27845400	1107	#define ETH_DMA_RX_WATCHDOG_TIMEOUT_IT ETH_DMACIER_RWTE
AnnaBridge	172:65be27845400	1108	#define ETH_DMA_RX_PROCESS_STOPPED_IT ETH_DMACIER_RSE
AnnaBridge	172:65be27845400	1109	#define ETH_DMA_RX_BUFFER_UNAVAILABLE_IT ETH_DMACIER_RBUE
AnnaBridge	172:65be27845400	1110	#define ETH_DMA_RX_IT ETH_DMACIER_RIE
AnnaBridge	172:65be27845400	1111	#define ETH_DMA_TX_BUFFER_UNAVAILABLE_IT ETH_DMACIER_TBUE
AnnaBridge	172:65be27845400	1112	#define ETH_DMA_TX_PROCESS_STOPPED_IT ETH_DMACIER_TXSE
AnnaBridge	172:65be27845400	1113	#define ETH_DMA_TX_IT ETH_DMACIER_TIE
AnnaBridge	172:65be27845400	1114	/**
AnnaBridge	172:65be27845400	1115	* @}
AnnaBridge	172:65be27845400	1116	*/
AnnaBridge	172:65be27845400	1117
AnnaBridge	172:65be27845400	1118	/** @defgroup ETH_DMA_Status_Flags ETH DMA Status Flags
AnnaBridge	172:65be27845400	1119	* @{
AnnaBridge	172:65be27845400	1120	*/
AnnaBridge	172:65be27845400	1121	#define ETH_DMA_RX_NO_ERROR_FLAG ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	1122	#define ETH_DMA_RX_DESC_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 \| ETH_DMACSR_REB_BIT_1 \| ETH_DMACSR_REB_BIT_0)
AnnaBridge	172:65be27845400	1123	#define ETH_DMA_RX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 \| ETH_DMACSR_REB_BIT_1)
AnnaBridge	172:65be27845400	1124	#define ETH_DMA_RX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 \| ETH_DMACSR_REB_BIT_0)
AnnaBridge	172:65be27845400	1125	#define ETH_DMA_RX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_REB_BIT_2
AnnaBridge	172:65be27845400	1126	#define ETH_DMA_TX_NO_ERROR_FLAG ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	1127	#define ETH_DMA_TX_DESC_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 \| ETH_DMACSR_TEB_BIT_1 \| ETH_DMACSR_TEB_BIT_0)
AnnaBridge	172:65be27845400	1128	#define ETH_DMA_TX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 \| ETH_DMACSR_TEB_BIT_1)
AnnaBridge	172:65be27845400	1129	#define ETH_DMA_TX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 \| ETH_DMACSR_TEB_BIT_0)
AnnaBridge	172:65be27845400	1130	#define ETH_DMA_TX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_TEB_BIT_2
AnnaBridge	172:65be27845400	1131	#define ETH_DMA_CONTEXT_DESC_ERROR_FLAG ETH_DMACSR_CDE
AnnaBridge	172:65be27845400	1132	#define ETH_DMA_FATAL_BUS_ERROR_FLAG ETH_DMACSR_FBE
AnnaBridge	172:65be27845400	1133	#define ETH_DMA_EARLY_TX_IT_FLAG ETH_DMACSR_ERI
AnnaBridge	172:65be27845400	1134	#define ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG ETH_DMACSR_RWT
AnnaBridge	172:65be27845400	1135	#define ETH_DMA_RX_PROCESS_STOPPED_FLAG ETH_DMACSR_RPS
AnnaBridge	172:65be27845400	1136	#define ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG ETH_DMACSR_RBU
AnnaBridge	172:65be27845400	1137	#define ETH_DMA_TX_PROCESS_STOPPED_FLAG ETH_DMACSR_TPS
AnnaBridge	172:65be27845400	1138	/**
AnnaBridge	172:65be27845400	1139	* @}
AnnaBridge	172:65be27845400	1140	*/
AnnaBridge	172:65be27845400	1141
AnnaBridge	172:65be27845400	1142	/** @defgroup ETH_Transmit_Mode ETH Transmit Mode
AnnaBridge	172:65be27845400	1143	* @{
AnnaBridge	172:65be27845400	1144	*/
AnnaBridge	172:65be27845400	1145	#define ETH_TRANSMITSTOREFORWARD ETH_MTLTQOMR_TSF
AnnaBridge	172:65be27845400	1146	#define ETH_TRANSMITTHRESHOLD_32 ETH_MTLTQOMR_TTC_32BITS
AnnaBridge	172:65be27845400	1147	#define ETH_TRANSMITTHRESHOLD_64 ETH_MTLTQOMR_TTC_64BITS
AnnaBridge	172:65be27845400	1148	#define ETH_TRANSMITTHRESHOLD_96 ETH_MTLTQOMR_TTC_96BITS
AnnaBridge	172:65be27845400	1149	#define ETH_TRANSMITTHRESHOLD_128 ETH_MTLTQOMR_TTC_128BITS
AnnaBridge	172:65be27845400	1150	#define ETH_TRANSMITTHRESHOLD_192 ETH_MTLTQOMR_TTC_192BITS
AnnaBridge	172:65be27845400	1151	#define ETH_TRANSMITTHRESHOLD_256 ETH_MTLTQOMR_TTC_256BITS
AnnaBridge	172:65be27845400	1152	#define ETH_TRANSMITTHRESHOLD_384 ETH_MTLTQOMR_TTC_384BITS
AnnaBridge	172:65be27845400	1153	#define ETH_TRANSMITTHRESHOLD_512 ETH_MTLTQOMR_TTC_512BITS
AnnaBridge	172:65be27845400	1154	/**
AnnaBridge	172:65be27845400	1155	* @}
AnnaBridge	172:65be27845400	1156	*/
AnnaBridge	172:65be27845400	1157
AnnaBridge	172:65be27845400	1158	/** @defgroup ETH_Receive_Mode ETH Receive Mode
AnnaBridge	172:65be27845400	1159	* @{
AnnaBridge	172:65be27845400	1160	*/
AnnaBridge	172:65be27845400	1161	#define ETH_RECEIVESTOREFORWARD ETH_MTLRQOMR_RSF
AnnaBridge	172:65be27845400	1162	#define ETH_RECEIVETHRESHOLD8_64 ETH_MTLRQOMR_RTC_64BITS
AnnaBridge	172:65be27845400	1163	#define ETH_RECEIVETHRESHOLD8_32 ETH_MTLRQOMR_RTC_32BITS
AnnaBridge	172:65be27845400	1164	#define ETH_RECEIVETHRESHOLD8_96 ETH_MTLRQOMR_RTC_96BITS
AnnaBridge	172:65be27845400	1165	#define ETH_RECEIVETHRESHOLD8_128 ETH_MTLRQOMR_RTC_128BITS
AnnaBridge	172:65be27845400	1166	/**
AnnaBridge	172:65be27845400	1167	* @}
AnnaBridge	172:65be27845400	1168	*/
AnnaBridge	172:65be27845400	1169
AnnaBridge	172:65be27845400	1170	/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
AnnaBridge	172:65be27845400	1171	* @{
AnnaBridge	172:65be27845400	1172	*/
AnnaBridge	172:65be27845400	1173	#define ETH_PAUSELOWTHRESHOLD_MINUS_4 ETH_MACTFCR_PLT_MINUS4
AnnaBridge	172:65be27845400	1174	#define ETH_PAUSELOWTHRESHOLD_MINUS_28 ETH_MACTFCR_PLT_MINUS28
AnnaBridge	172:65be27845400	1175	#define ETH_PAUSELOWTHRESHOLD_MINUS_36 ETH_MACTFCR_PLT_MINUS36
AnnaBridge	172:65be27845400	1176	#define ETH_PAUSELOWTHRESHOLD_MINUS_144 ETH_MACTFCR_PLT_MINUS144
AnnaBridge	172:65be27845400	1177	#define ETH_PAUSELOWTHRESHOLD_MINUS_256 ETH_MACTFCR_PLT_MINUS256
AnnaBridge	172:65be27845400	1178	#define ETH_PAUSELOWTHRESHOLD_MINUS_512 ETH_MACTFCR_PLT_MINUS512
AnnaBridge	172:65be27845400	1179	/**
AnnaBridge	172:65be27845400	1180	* @}
AnnaBridge	172:65be27845400	1181	*/
AnnaBridge	172:65be27845400	1182
AnnaBridge	172:65be27845400	1183	/** @defgroup ETH_Watchdog_Timeout ETH Watchdog Timeout
AnnaBridge	172:65be27845400	1184	* @{
AnnaBridge	172:65be27845400	1185	*/
AnnaBridge	172:65be27845400	1186	#define ETH_WATCHDOGTIMEOUT_2KB ETH_MACWTR_WTO_2KB
AnnaBridge	172:65be27845400	1187	#define ETH_WATCHDOGTIMEOUT_3KB ETH_MACWTR_WTO_3KB
AnnaBridge	172:65be27845400	1188	#define ETH_WATCHDOGTIMEOUT_4KB ETH_MACWTR_WTO_4KB
AnnaBridge	172:65be27845400	1189	#define ETH_WATCHDOGTIMEOUT_5KB ETH_MACWTR_WTO_5KB
AnnaBridge	172:65be27845400	1190	#define ETH_WATCHDOGTIMEOUT_6KB ETH_MACWTR_WTO_6KB
AnnaBridge	172:65be27845400	1191	#define ETH_WATCHDOGTIMEOUT_7KB ETH_MACWTR_WTO_7KB
AnnaBridge	172:65be27845400	1192	#define ETH_WATCHDOGTIMEOUT_8KB ETH_MACWTR_WTO_8KB
AnnaBridge	172:65be27845400	1193	#define ETH_WATCHDOGTIMEOUT_9KB ETH_MACWTR_WTO_9KB
AnnaBridge	172:65be27845400	1194	#define ETH_WATCHDOGTIMEOUT_10KB ETH_MACWTR_WTO_10KB
AnnaBridge	172:65be27845400	1195	#define ETH_WATCHDOGTIMEOUT_11KB ETH_MACWTR_WTO_12KB
AnnaBridge	172:65be27845400	1196	#define ETH_WATCHDOGTIMEOUT_12KB ETH_MACWTR_WTO_12KB
AnnaBridge	172:65be27845400	1197	#define ETH_WATCHDOGTIMEOUT_13KB ETH_MACWTR_WTO_13KB
AnnaBridge	172:65be27845400	1198	#define ETH_WATCHDOGTIMEOUT_14KB ETH_MACWTR_WTO_14KB
AnnaBridge	172:65be27845400	1199	#define ETH_WATCHDOGTIMEOUT_15KB ETH_MACWTR_WTO_15KB
AnnaBridge	172:65be27845400	1200	#define ETH_WATCHDOGTIMEOUT_16KB ETH_MACWTR_WTO_16KB
AnnaBridge	172:65be27845400	1201	/**
AnnaBridge	172:65be27845400	1202	* @}
AnnaBridge	172:65be27845400	1203	*/
AnnaBridge	172:65be27845400	1204
AnnaBridge	172:65be27845400	1205	/** @defgroup ETH_Inter_Packet_Gap ETH Inter Packet Gap
AnnaBridge	172:65be27845400	1206	* @{
AnnaBridge	172:65be27845400	1207	*/
AnnaBridge	172:65be27845400	1208	#define ETH_INTERPACKETGAP_96BIT ETH_MACCR_IPG_96BIT
AnnaBridge	172:65be27845400	1209	#define ETH_INTERPACKETGAP_88BIT ETH_MACCR_IPG_88BIT
AnnaBridge	172:65be27845400	1210	#define ETH_INTERPACKETGAP_80BIT ETH_MACCR_IPG_80BIT
AnnaBridge	172:65be27845400	1211	#define ETH_INTERPACKETGAP_72BIT ETH_MACCR_IPG_72BIT
AnnaBridge	172:65be27845400	1212	#define ETH_INTERPACKETGAP_64BIT ETH_MACCR_IPG_64BIT
AnnaBridge	172:65be27845400	1213	#define ETH_INTERPACKETGAP_56BIT ETH_MACCR_IPG_56BIT
AnnaBridge	172:65be27845400	1214	#define ETH_INTERPACKETGAP_48BIT ETH_MACCR_IPG_48BIT
AnnaBridge	172:65be27845400	1215	#define ETH_INTERPACKETGAP_40BIT ETH_MACCR_IPG_40BIT
AnnaBridge	172:65be27845400	1216	/**
AnnaBridge	172:65be27845400	1217	* @}
AnnaBridge	172:65be27845400	1218	*/
AnnaBridge	172:65be27845400	1219
AnnaBridge	172:65be27845400	1220	/** @defgroup ETH_Speed ETH Speed
AnnaBridge	172:65be27845400	1221	* @{
AnnaBridge	172:65be27845400	1222	*/
AnnaBridge	172:65be27845400	1223	#define ETH_SPEED_10M ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	1224	#define ETH_SPEED_100M ETH_MACCR_FES
AnnaBridge	172:65be27845400	1225	/**
AnnaBridge	172:65be27845400	1226	* @}
AnnaBridge	172:65be27845400	1227	*/
AnnaBridge	172:65be27845400	1228
AnnaBridge	172:65be27845400	1229	/** @defgroup ETH_Duplex_Mode ETH Duplex Mode
AnnaBridge	172:65be27845400	1230	* @{
AnnaBridge	172:65be27845400	1231	*/
AnnaBridge	172:65be27845400	1232	#define ETH_FULLDUPLEX_MODE ETH_MACCR_DM
AnnaBridge	172:65be27845400	1233	#define ETH_HALFDUPLEX_MODE ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	1234	/**
AnnaBridge	172:65be27845400	1235	* @}
AnnaBridge	172:65be27845400	1236	*/
AnnaBridge	172:65be27845400	1237
AnnaBridge	172:65be27845400	1238	/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
AnnaBridge	172:65be27845400	1239	* @{
AnnaBridge	172:65be27845400	1240	*/
AnnaBridge	172:65be27845400	1241	#define ETH_BACKOFFLIMIT_10 ETH_MACCR_BL_10
AnnaBridge	172:65be27845400	1242	#define ETH_BACKOFFLIMIT_8 ETH_MACCR_BL_8
AnnaBridge	172:65be27845400	1243	#define ETH_BACKOFFLIMIT_4 ETH_MACCR_BL_4
AnnaBridge	172:65be27845400	1244	#define ETH_BACKOFFLIMIT_1 ETH_MACCR_BL_1
AnnaBridge	172:65be27845400	1245	/**
AnnaBridge	172:65be27845400	1246	* @}
AnnaBridge	172:65be27845400	1247	*/
AnnaBridge	172:65be27845400	1248
AnnaBridge	172:65be27845400	1249	/** @defgroup ETH_Preamble_Length ETH Preamble Length
AnnaBridge	172:65be27845400	1250	* @{
AnnaBridge	172:65be27845400	1251	*/
AnnaBridge	172:65be27845400	1252	#define ETH_PREAMBLELENGTH_7 ETH_MACCR_PRELEN_7
AnnaBridge	172:65be27845400	1253	#define ETH_PREAMBLELENGTH_5 ETH_MACCR_PRELEN_5
AnnaBridge	172:65be27845400	1254	#define ETH_PREAMBLELENGTH_3 ETH_MACCR_PRELEN_3
AnnaBridge	172:65be27845400	1255	/**
AnnaBridge	172:65be27845400	1256	* @}
AnnaBridge	172:65be27845400	1257	*/
AnnaBridge	172:65be27845400	1258
AnnaBridge	172:65be27845400	1259	/** @defgroup ETH_Source_Addr_Control ETH Source Addr Control
AnnaBridge	172:65be27845400	1260	* @{
AnnaBridge	172:65be27845400	1261	*/
AnnaBridge	172:65be27845400	1262	#define ETH_SOURCEADDRESS_DISABLE ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	1263	#define ETH_SOURCEADDRESS_INSERT_ADDR0 ETH_MACCR_SARC_INSADDR0
AnnaBridge	172:65be27845400	1264	#define ETH_SOURCEADDRESS_INSERT_ADDR1 ETH_MACCR_SARC_INSADDR1
AnnaBridge	172:65be27845400	1265	#define ETH_SOURCEADDRESS_REPLACE_ADDR0 ETH_MACCR_SARC_REPADDR0
AnnaBridge	172:65be27845400	1266	#define ETH_SOURCEADDRESS_REPLACE_ADDR1 ETH_MACCR_SARC_REPADDR1
AnnaBridge	172:65be27845400	1267	/**
AnnaBridge	172:65be27845400	1268	* @}
AnnaBridge	172:65be27845400	1269	*/
AnnaBridge	172:65be27845400	1270
AnnaBridge	172:65be27845400	1271	/** @defgroup ETH_Control_Packets_Filter ETH Control Packets Filter
AnnaBridge	172:65be27845400	1272	* @{
AnnaBridge	172:65be27845400	1273	*/
AnnaBridge	172:65be27845400	1274	#define ETH_CTRLPACKETS_BLOCK_ALL ETH_MACPFR_PCF_BLOCKALL
AnnaBridge	172:65be27845400	1275	#define ETH_CTRLPACKETS_FORWARD_ALL_EXCEPT_PA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA
AnnaBridge	172:65be27845400	1276	#define ETH_CTRLPACKETS_FORWARD_ALL ETH_MACPFR_PCF_FORWARDALL
AnnaBridge	172:65be27845400	1277	#define ETH_CTRLPACKETS_FORWARD_PASSED_ADDR_FILTER ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER
AnnaBridge	172:65be27845400	1278	/**
AnnaBridge	172:65be27845400	1279	* @}
AnnaBridge	172:65be27845400	1280	*/
AnnaBridge	172:65be27845400	1281
AnnaBridge	172:65be27845400	1282	/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
AnnaBridge	172:65be27845400	1283	* @{
AnnaBridge	172:65be27845400	1284	*/
AnnaBridge	172:65be27845400	1285	#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	1286	#define ETH_VLANTAGCOMPARISON_12BIT ETH_MACVTR_ETV
AnnaBridge	172:65be27845400	1287	/**
AnnaBridge	172:65be27845400	1288	* @}
AnnaBridge	172:65be27845400	1289	*/
AnnaBridge	172:65be27845400	1290
AnnaBridge	172:65be27845400	1291	/** @defgroup ETH_MAC_addresses ETH MAC addresses
AnnaBridge	172:65be27845400	1292	* @{
AnnaBridge	172:65be27845400	1293	*/
AnnaBridge	172:65be27845400	1294	#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000U)
AnnaBridge	172:65be27845400	1295	#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008U)
AnnaBridge	172:65be27845400	1296	#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010U)
AnnaBridge	172:65be27845400	1297	#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018U)
AnnaBridge	172:65be27845400	1298	/**
AnnaBridge	172:65be27845400	1299	* @}
AnnaBridge	172:65be27845400	1300	*/
AnnaBridge	172:65be27845400	1301
AnnaBridge	172:65be27845400	1302	/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
AnnaBridge	172:65be27845400	1303	* @{
AnnaBridge	172:65be27845400	1304	*/
AnnaBridge	172:65be27845400	1305	#define ETH_MAC_RX_STATUS_IT ETH_MACIER_RXSTSIE
AnnaBridge	172:65be27845400	1306	#define ETH_MAC_TX_STATUS_IT ETH_MACIER_TXSTSIE
AnnaBridge	172:65be27845400	1307	#define ETH_MAC_TIMESTAMP_IT ETH_MACIER_TSIE
AnnaBridge	172:65be27845400	1308	#define ETH_MAC_LPI_IT ETH_MACIER_LPIIE
AnnaBridge	172:65be27845400	1309	#define ETH_MAC_PMT_IT ETH_MACIER_PMTIE
AnnaBridge	172:65be27845400	1310	#define ETH_MAC_PHY_IT ETH_MACIER_PHYIE
AnnaBridge	172:65be27845400	1311	/**
AnnaBridge	172:65be27845400	1312	* @}
AnnaBridge	172:65be27845400	1313	*/
AnnaBridge	172:65be27845400	1314
AnnaBridge	172:65be27845400	1315	/** @defgroup ETH_MAC_Wake_Up_Event ETH MAC Wake Up Event
AnnaBridge	172:65be27845400	1316	* @{
AnnaBridge	172:65be27845400	1317	*/
AnnaBridge	172:65be27845400	1318	#define ETH_WAKEUP_PACKET_RECIEVED ETH_MACPCSR_RWKPRCVD
AnnaBridge	172:65be27845400	1319	#define ETH_MAGIC_PACKET_RECIEVED ETH_MACPCSR_MGKPRCVD
AnnaBridge	172:65be27845400	1320	/**
AnnaBridge	172:65be27845400	1321	* @}
AnnaBridge	172:65be27845400	1322	*/
AnnaBridge	172:65be27845400	1323
AnnaBridge	172:65be27845400	1324	/** @defgroup ETH_MAC_Rx_Tx_Status ETH MAC Rx Tx Status
AnnaBridge	172:65be27845400	1325	* @{
AnnaBridge	172:65be27845400	1326	*/
AnnaBridge	172:65be27845400	1327	#define ETH_RECEIVE_WATCHDOG_TIMEOUT ETH_MACRXTXSR_RWT
AnnaBridge	172:65be27845400	1328	#define ETH_EXECESSIVE_COLLISIONS ETH_MACRXTXSR_EXCOL
AnnaBridge	172:65be27845400	1329	#define ETH_LATE_COLLISIONS ETH_MACRXTXSR_LCOL
AnnaBridge	172:65be27845400	1330	#define ETH_EXECESSIVE_DEFERRAL ETH_MACRXTXSR_EXDEF
AnnaBridge	172:65be27845400	1331	#define ETH_LOSS_OF_CARRIER ETH_MACRXTXSR_LCARR
AnnaBridge	172:65be27845400	1332	#define ETH_NO_CARRIER ETH_MACRXTXSR_NCARR
AnnaBridge	172:65be27845400	1333	#define ETH_TRANSMIT_JABBR_TIMEOUT ETH_MACRXTXSR_TJT
AnnaBridge	172:65be27845400	1334	/**
AnnaBridge	172:65be27845400	1335	* @}
AnnaBridge	172:65be27845400	1336	*/
AnnaBridge	172:65be27845400	1337
AnnaBridge	172:65be27845400	1338	/** @defgroup HAL_ETH_StateTypeDef ETH States
AnnaBridge	172:65be27845400	1339	* @{
AnnaBridge	172:65be27845400	1340	*/
AnnaBridge	172:65be27845400	1341	#define HAL_ETH_STATE_RESET ((uint32_t)0x00000000U) /!< Peripheral not yet Initialized or disabled /
AnnaBridge	172:65be27845400	1342	#define HAL_ETH_STATE_READY ((uint32_t)0x00000010U) /!< Peripheral Communication started /
AnnaBridge	172:65be27845400	1343	#define HAL_ETH_STATE_BUSY ((uint32_t)0x00000023U) /!< an internal process is ongoing /
AnnaBridge	172:65be27845400	1344	#define HAL_ETH_STATE_BUSY_TX ((uint32_t)0x00000021U) /!< Transmission process is ongoing /
AnnaBridge	172:65be27845400	1345	#define HAL_ETH_STATE_BUSY_RX ((uint32_t)0x00000022U) /!< Reception process is ongoing /
AnnaBridge	172:65be27845400	1346	#define HAL_ETH_STATE_ERROR ((uint32_t)0x000000E0U) /!< Error State /
AnnaBridge	172:65be27845400	1347	/**
AnnaBridge	172:65be27845400	1348	* @}
AnnaBridge	172:65be27845400	1349	*/
AnnaBridge	172:65be27845400	1350	/**
AnnaBridge	172:65be27845400	1351	* @}
AnnaBridge	172:65be27845400	1352	*/
AnnaBridge	172:65be27845400	1353
AnnaBridge	172:65be27845400	1354	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	1355	/** @defgroup ETH_Exported_Macros ETH Exported Macros
AnnaBridge	172:65be27845400	1356	* @{
AnnaBridge	172:65be27845400	1357	*/
AnnaBridge	172:65be27845400	1358
AnnaBridge	172:65be27845400	1359	/** @brief Reset ETH handle state
AnnaBridge	172:65be27845400	1360	* @param __HANDLE__: specifies the ETH handle.
AnnaBridge	172:65be27845400	1361	* @retval None
AnnaBridge	172:65be27845400	1362	*/
AnnaBridge	172:65be27845400	1363	#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
AnnaBridge	172:65be27845400	1364	#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \
AnnaBridge	172:65be27845400	1365	(__HANDLE__)->gState = HAL_ETH_STATE_RESET; \
AnnaBridge	172:65be27845400	1366	(__HANDLE__)->RxState = HAL_ETH_STATE_RESET; \
AnnaBridge	172:65be27845400	1367	(__HANDLE__)->MspInitCallback = NULL; \
AnnaBridge	172:65be27845400	1368	(__HANDLE__)->MspDeInitCallback = NULL; \
AnnaBridge	172:65be27845400	1369	} while(0)
AnnaBridge	172:65be27845400	1370	#else
AnnaBridge	172:65be27845400	1371	#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \
AnnaBridge	172:65be27845400	1372	(__HANDLE__)->gState = HAL_ETH_STATE_RESET; \
AnnaBridge	172:65be27845400	1373	(__HANDLE__)->RxState = HAL_ETH_STATE_RESET; \
AnnaBridge	172:65be27845400	1374	} while(0)
AnnaBridge	172:65be27845400	1375	#endif /USE_HAL_ETH_REGISTER_CALLBACKS /
AnnaBridge	172:65be27845400	1376
AnnaBridge	172:65be27845400	1377	/**
AnnaBridge	172:65be27845400	1378	* @brief Enables the specified ETHERNET DMA interrupts.
AnnaBridge	172:65be27845400	1379	* @param __HANDLE__ : ETH Handle
AnnaBridge	172:65be27845400	1380	* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
AnnaBridge	172:65be27845400	1381	* enabled @ref ETH_DMA_Interrupts
AnnaBridge	172:65be27845400	1382	* @retval None
AnnaBridge	172:65be27845400	1383	*/
AnnaBridge	172:65be27845400	1384	#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER \|= (__INTERRUPT__))
AnnaBridge	172:65be27845400	1385
AnnaBridge	172:65be27845400	1386	/**
AnnaBridge	172:65be27845400	1387	* @brief Disables the specified ETHERNET DMA interrupts.
AnnaBridge	172:65be27845400	1388	* @param __HANDLE__ : ETH Handle
AnnaBridge	172:65be27845400	1389	* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
AnnaBridge	172:65be27845400	1390	* disabled. @ref ETH_DMA_Interrupts
AnnaBridge	172:65be27845400	1391	* @retval None
AnnaBridge	172:65be27845400	1392	*/
AnnaBridge	172:65be27845400	1393	#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER &= ~(__INTERRUPT__))
AnnaBridge	172:65be27845400	1394
AnnaBridge	172:65be27845400	1395	/**
AnnaBridge	172:65be27845400	1396	* @brief Gets the ETHERNET DMA IT source enabled or disabled.
AnnaBridge	172:65be27845400	1397	* @param __HANDLE__ : ETH Handle
AnnaBridge	172:65be27845400	1398	* @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts
AnnaBridge	172:65be27845400	1399	* @retval The ETH DMA IT Source enabled or disabled
AnnaBridge	172:65be27845400	1400	*/
AnnaBridge	172:65be27845400	1401	#define __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMACIER & (__INTERRUPT__)) == (__INTERRUPT__))
AnnaBridge	172:65be27845400	1402
AnnaBridge	172:65be27845400	1403	/**
AnnaBridge	172:65be27845400	1404	* @brief Gets the ETHERNET DMA IT pending bit.
AnnaBridge	172:65be27845400	1405	* @param __HANDLE__ : ETH Handle
AnnaBridge	172:65be27845400	1406	* @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts
AnnaBridge	172:65be27845400	1407	* @retval The state of ETH DMA IT (SET or RESET)
AnnaBridge	172:65be27845400	1408	*/
AnnaBridge	172:65be27845400	1409	#define __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMACSR & (__INTERRUPT__)) == (__INTERRUPT__))
AnnaBridge	172:65be27845400	1410
AnnaBridge	172:65be27845400	1411	/**
AnnaBridge	172:65be27845400	1412	* @brief Clears the ETHERNET DMA IT pending bit.
AnnaBridge	172:65be27845400	1413	* @param __HANDLE__ : ETH Handle
AnnaBridge	172:65be27845400	1414	* @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
AnnaBridge	172:65be27845400	1415	* @retval None
AnnaBridge	172:65be27845400	1416	*/
AnnaBridge	172:65be27845400	1417	#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACSR = (__INTERRUPT__))
AnnaBridge	172:65be27845400	1418
AnnaBridge	172:65be27845400	1419	/**
AnnaBridge	172:65be27845400	1420	* @brief Checks whether the specified ETHERNET DMA flag is set or not.
AnnaBridge	172:65be27845400	1421	* @param __HANDLE__: ETH Handle
AnnaBridge	172:65be27845400	1422	* @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
AnnaBridge	172:65be27845400	1423	* @retval The state of ETH DMA FLAG (SET or RESET).
AnnaBridge	172:65be27845400	1424	*/
AnnaBridge	172:65be27845400	1425	#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMACSR &( __FLAG__)) == ( __FLAG__))
AnnaBridge	172:65be27845400	1426
AnnaBridge	172:65be27845400	1427	/**
AnnaBridge	172:65be27845400	1428	* @brief Clears the specified ETHERNET DMA flag.
AnnaBridge	172:65be27845400	1429	* @param __HANDLE__: ETH Handle
AnnaBridge	172:65be27845400	1430	* @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
AnnaBridge	172:65be27845400	1431	* @retval The state of ETH DMA FLAG (SET or RESET).
AnnaBridge	172:65be27845400	1432	*/
AnnaBridge	172:65be27845400	1433	#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMACSR = ( __FLAG__))
AnnaBridge	172:65be27845400	1434
AnnaBridge	172:65be27845400	1435	/**
AnnaBridge	172:65be27845400	1436	* @brief Enables the specified ETHERNET MAC interrupts.
AnnaBridge	172:65be27845400	1437	* @param __HANDLE__ : ETH Handle
AnnaBridge	172:65be27845400	1438	* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
AnnaBridge	172:65be27845400	1439	* enabled @ref ETH_MAC_Interrupts
AnnaBridge	172:65be27845400	1440	* @retval None
AnnaBridge	172:65be27845400	1441	*/
AnnaBridge	172:65be27845400	1442	#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER \|= (__INTERRUPT__))
AnnaBridge	172:65be27845400	1443
AnnaBridge	172:65be27845400	1444	/**
AnnaBridge	172:65be27845400	1445	* @brief Disables the specified ETHERNET MAC interrupts.
AnnaBridge	172:65be27845400	1446	* @param __HANDLE__ : ETH Handle
AnnaBridge	172:65be27845400	1447	* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
AnnaBridge	172:65be27845400	1448	* enabled @ref ETH_MAC_Interrupts
AnnaBridge	172:65be27845400	1449	* @retval None
AnnaBridge	172:65be27845400	1450	*/
AnnaBridge	172:65be27845400	1451	#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER &= ~(__INTERRUPT__))
AnnaBridge	172:65be27845400	1452
AnnaBridge	172:65be27845400	1453	/**
AnnaBridge	172:65be27845400	1454	* @brief Checks whether the specified ETHERNET MAC flag is set or not.
AnnaBridge	172:65be27845400	1455	* @param __HANDLE__: ETH Handle
AnnaBridge	172:65be27845400	1456	* @param __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts
AnnaBridge	172:65be27845400	1457	* @retval The state of ETH MAC IT (SET or RESET).
AnnaBridge	172:65be27845400	1458	*/
AnnaBridge	172:65be27845400	1459	#define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MACISR &( __INTERRUPT__)) == ( __INTERRUPT__))
AnnaBridge	172:65be27845400	1460
AnnaBridge	172:65be27845400	1461	/!< External interrupt line 86 Connected to the ETH wakeup EXTI Line /
AnnaBridge	172:65be27845400	1462	#define ETH_WAKEUP_EXTI_LINE ((uint32_t)0x00400000U) /* !< 86 - 64 = 22 */
AnnaBridge	172:65be27845400	1463
AnnaBridge	172:65be27845400	1464	/**
AnnaBridge	172:65be27845400	1465	* @brief Enable the ETH WAKEUP Exti Line.
AnnaBridge	172:65be27845400	1466	* @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled.
AnnaBridge	172:65be27845400	1467	* @arg ETH_WAKEUP_EXTI_LINE
AnnaBridge	172:65be27845400	1468	* @retval None.
AnnaBridge	172:65be27845400	1469	*/
AnnaBridge	172:65be27845400	1470	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__) (EXTI_D1->IMR3 \|= (__EXTI_LINE__))
AnnaBridge	172:65be27845400	1471
AnnaBridge	172:65be27845400	1472	/**
AnnaBridge	172:65be27845400	1473	* @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not.
AnnaBridge	172:65be27845400	1474	* @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
AnnaBridge	172:65be27845400	1475	* @arg ETH_WAKEUP_EXTI_LINE
AnnaBridge	172:65be27845400	1476	* @retval EXTI ETH WAKEUP Line Status.
AnnaBridge	172:65be27845400	1477	*/
AnnaBridge	172:65be27845400	1478	#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 & (__EXTI_LINE__))
AnnaBridge	172:65be27845400	1479
AnnaBridge	172:65be27845400	1480	/**
AnnaBridge	172:65be27845400	1481	* @brief Clear the ETH WAKEUP Exti flag.
AnnaBridge	172:65be27845400	1482	* @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
AnnaBridge	172:65be27845400	1483	* @arg ETH_WAKEUP_EXTI_LINE
AnnaBridge	172:65be27845400	1484	* @retval None.
AnnaBridge	172:65be27845400	1485	*/
AnnaBridge	172:65be27845400	1486	#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 = (__EXTI_LINE__))
AnnaBridge	172:65be27845400	1487
AnnaBridge	172:65be27845400	1488	/**
AnnaBridge	172:65be27845400	1489	* @brief enable rising edge interrupt on selected EXTI line.
AnnaBridge	172:65be27845400	1490	* @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
AnnaBridge	172:65be27845400	1491	* @arg ETH_WAKEUP_EXTI_LINE
AnnaBridge	172:65be27845400	1492	* @retval None
AnnaBridge	172:65be27845400	1493	*/
AnnaBridge	172:65be27845400	1494	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR3 &= ~(__EXTI_LINE__)); \
AnnaBridge	172:65be27845400	1495	(EXTI->RTSR3 \|= (__EXTI_LINE__))
AnnaBridge	172:65be27845400	1496
AnnaBridge	172:65be27845400	1497	/**
AnnaBridge	172:65be27845400	1498	* @brief enable falling edge interrupt on selected EXTI line.
AnnaBridge	172:65be27845400	1499	* @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
AnnaBridge	172:65be27845400	1500	* @arg ETH_WAKEUP_EXTI_LINE
AnnaBridge	172:65be27845400	1501	* @retval None
AnnaBridge	172:65be27845400	1502	*/
AnnaBridge	172:65be27845400	1503	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 &= ~(__EXTI_LINE__));\
AnnaBridge	172:65be27845400	1504	(EXTI->FTSR3 \|= (__EXTI_LINE__))
AnnaBridge	172:65be27845400	1505
AnnaBridge	172:65be27845400	1506	/**
AnnaBridge	172:65be27845400	1507	* @brief enable falling edge interrupt on selected EXTI line.
AnnaBridge	172:65be27845400	1508	* @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
AnnaBridge	172:65be27845400	1509	* @arg ETH_WAKEUP_EXTI_LINE
AnnaBridge	172:65be27845400	1510	* @retval None
AnnaBridge	172:65be27845400	1511	*/
AnnaBridge	172:65be27845400	1512	#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 \|= (__EXTI_LINE__));\
AnnaBridge	172:65be27845400	1513	(EXTI->FTSR3 \|= (__EXTI_LINE__))
AnnaBridge	172:65be27845400	1514
AnnaBridge	172:65be27845400	1515	/**
AnnaBridge	172:65be27845400	1516	* @brief Generates a Software interrupt on selected EXTI line.
AnnaBridge	172:65be27845400	1517	* @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
AnnaBridge	172:65be27845400	1518	* @arg ETH_WAKEUP_EXTI_LINE
AnnaBridge	172:65be27845400	1519	* @retval None
AnnaBridge	172:65be27845400	1520	*/
AnnaBridge	172:65be27845400	1521	#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER3 \|= (__EXTI_LINE__))
AnnaBridge	172:65be27845400	1522
AnnaBridge	172:65be27845400	1523	/**
AnnaBridge	172:65be27845400	1524	* @}
AnnaBridge	172:65be27845400	1525	*/
AnnaBridge	172:65be27845400	1526
AnnaBridge	172:65be27845400	1527	/* Include ETH HAL Extension module */
AnnaBridge	172:65be27845400	1528	#include "stm32h7xx_hal_eth_ex.h"
AnnaBridge	172:65be27845400	1529
AnnaBridge	172:65be27845400	1530	/* Exported functions --------------------------------------------------------*/
AnnaBridge	172:65be27845400	1531
AnnaBridge	172:65be27845400	1532	/** @addtogroup ETH_Exported_Functions
AnnaBridge	172:65be27845400	1533	* @{
AnnaBridge	172:65be27845400	1534	*/
AnnaBridge	172:65be27845400	1535
AnnaBridge	172:65be27845400	1536	/** @addtogroup ETH_Exported_Functions_Group1
AnnaBridge	172:65be27845400	1537	* @{
AnnaBridge	172:65be27845400	1538	*/
AnnaBridge	172:65be27845400	1539	/* Initialization and de initialization functions **********************************/
AnnaBridge	172:65be27845400	1540	HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
AnnaBridge	172:65be27845400	1541	HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
AnnaBridge	172:65be27845400	1542	void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
AnnaBridge	172:65be27845400	1543	void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
AnnaBridge	172:65be27845400	1544	HAL_StatusTypeDef HAL_ETH_DescAssignMemory(ETH_HandleTypeDef heth, uint32_t Index, uint8_t pBuffer1,uint8_t *pBuffer2);
AnnaBridge	172:65be27845400	1545
AnnaBridge	172:65be27845400	1546	/* Callbacks Register/UnRegister functions ***********************************/
AnnaBridge	172:65be27845400	1547	#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
AnnaBridge	172:65be27845400	1548	HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback);
AnnaBridge	172:65be27845400	1549	HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID);
AnnaBridge	172:65be27845400	1550	#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
AnnaBridge	172:65be27845400	1551
AnnaBridge	172:65be27845400	1552	/**
AnnaBridge	172:65be27845400	1553	* @}
AnnaBridge	172:65be27845400	1554	*/
AnnaBridge	172:65be27845400	1555
AnnaBridge	172:65be27845400	1556	/** @addtogroup ETH_Exported_Functions_Group2
AnnaBridge	172:65be27845400	1557	* @{
AnnaBridge	172:65be27845400	1558	*/
AnnaBridge	172:65be27845400	1559	/* IO operation functions *******************************************************/
AnnaBridge	172:65be27845400	1560	HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
AnnaBridge	172:65be27845400	1561	HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth);
AnnaBridge	172:65be27845400	1562	HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
AnnaBridge	172:65be27845400	1563	HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth);
AnnaBridge	172:65be27845400	1564
AnnaBridge	172:65be27845400	1565	uint8_t HAL_ETH_IsRxDataAvailable(ETH_HandleTypeDef *heth);
AnnaBridge	172:65be27845400	1566	HAL_StatusTypeDef HAL_ETH_GetRxDataBuffer(ETH_HandleTypeDef heth, ETH_BufferTypeDef RxBuffer);
AnnaBridge	172:65be27845400	1567	HAL_StatusTypeDef HAL_ETH_GetRxDataLength(ETH_HandleTypeDef heth, uint32_t Length);
AnnaBridge	172:65be27845400	1568	HAL_StatusTypeDef HAL_ETH_GetRxDataInfo(ETH_HandleTypeDef heth, ETH_RxPacketInfo RxPacketInfo);
AnnaBridge	172:65be27845400	1569	HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors(ETH_HandleTypeDef *heth);
AnnaBridge	172:65be27845400	1570
AnnaBridge	172:65be27845400	1571	HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef heth, ETH_TxPacketConfig pTxConfig, uint32_t Timeout);
AnnaBridge	172:65be27845400	1572	HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef heth, ETH_TxPacketConfig pTxConfig);
AnnaBridge	172:65be27845400	1573
AnnaBridge	172:65be27845400	1574	HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue);
AnnaBridge	172:65be27845400	1575	HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t pRegValue);
AnnaBridge	172:65be27845400	1576
AnnaBridge	172:65be27845400	1577	void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
AnnaBridge	172:65be27845400	1578	void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
AnnaBridge	172:65be27845400	1579	void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
AnnaBridge	172:65be27845400	1580	void HAL_ETH_DMAErrorCallback(ETH_HandleTypeDef *heth);
AnnaBridge	172:65be27845400	1581	void HAL_ETH_MACErrorCallback(ETH_HandleTypeDef *heth);
AnnaBridge	172:65be27845400	1582	void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth);
AnnaBridge	172:65be27845400	1583	void HAL_ETH_EEECallback(ETH_HandleTypeDef *heth);
AnnaBridge	172:65be27845400	1584	void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth);
AnnaBridge	172:65be27845400	1585	/**
AnnaBridge	172:65be27845400	1586	* @}
AnnaBridge	172:65be27845400	1587	*/
AnnaBridge	172:65be27845400	1588
AnnaBridge	172:65be27845400	1589	/** @addtogroup ETH_Exported_Functions_Group3
AnnaBridge	172:65be27845400	1590	* @{
AnnaBridge	172:65be27845400	1591	*/
AnnaBridge	172:65be27845400	1592	/* Peripheral Control functions **********************************************/
AnnaBridge	172:65be27845400	1593	/* MAC & DMA Configuration APIs **********************************************/
AnnaBridge	172:65be27845400	1594	HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef heth, ETH_MACConfigTypeDef macconf);
AnnaBridge	172:65be27845400	1595	HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef heth, ETH_DMAConfigTypeDef dmaconf);
AnnaBridge	172:65be27845400	1596	HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef heth, ETH_MACConfigTypeDef macconf);
AnnaBridge	172:65be27845400	1597	HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef heth, ETH_DMAConfigTypeDef dmaconf);
AnnaBridge	172:65be27845400	1598	void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth);
AnnaBridge	172:65be27845400	1599
AnnaBridge	172:65be27845400	1600	/* MAC VLAN Processing APIs ************************************************/
AnnaBridge	172:65be27845400	1601	void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier);
AnnaBridge	172:65be27845400	1602
AnnaBridge	172:65be27845400	1603	/* MAC L2 Packet Filtering APIs **********************************************/
AnnaBridge	172:65be27845400	1604	HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef heth, ETH_MACFilterConfigTypeDef pFilterConfig);
AnnaBridge	172:65be27845400	1605	HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef heth, ETH_MACFilterConfigTypeDef pFilterConfig);
AnnaBridge	172:65be27845400	1606	HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef heth, uint32_t pHashTable);
AnnaBridge	172:65be27845400	1607	HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef heth, uint32_t AddrNbr, uint8_t pMACAddr);
AnnaBridge	172:65be27845400	1608
AnnaBridge	172:65be27845400	1609	/* MAC Power Down APIs *****************************************************/
AnnaBridge	172:65be27845400	1610	void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef heth, ETH_PowerDownConfigTypeDef pPowerDownConfig);
AnnaBridge	172:65be27845400	1611	void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth);
AnnaBridge	172:65be27845400	1612	HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef heth, uint32_t pFilter, uint32_t Count);
AnnaBridge	172:65be27845400	1613
AnnaBridge	172:65be27845400	1614	/**
AnnaBridge	172:65be27845400	1615	* @}
AnnaBridge	172:65be27845400	1616	*/
AnnaBridge	172:65be27845400	1617
AnnaBridge	172:65be27845400	1618	/** @addtogroup ETH_Exported_Functions_Group4
AnnaBridge	172:65be27845400	1619	* @{
AnnaBridge	172:65be27845400	1620	*/
AnnaBridge	172:65be27845400	1621	/* Peripheral State functions **************************************************/
AnnaBridge	172:65be27845400	1622	HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
AnnaBridge	172:65be27845400	1623	uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth);
AnnaBridge	172:65be27845400	1624	uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth);
AnnaBridge	172:65be27845400	1625	uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth);
AnnaBridge	172:65be27845400	1626	uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth);
AnnaBridge	172:65be27845400	1627	/**
AnnaBridge	172:65be27845400	1628	* @}
AnnaBridge	172:65be27845400	1629	*/
AnnaBridge	172:65be27845400	1630
AnnaBridge	172:65be27845400	1631	/**
AnnaBridge	172:65be27845400	1632	* @}
AnnaBridge	172:65be27845400	1633	*/
AnnaBridge	172:65be27845400	1634
AnnaBridge	172:65be27845400	1635	/**
AnnaBridge	172:65be27845400	1636	* @}
AnnaBridge	172:65be27845400	1637	*/
AnnaBridge	172:65be27845400	1638
AnnaBridge	172:65be27845400	1639	/**
AnnaBridge	172:65be27845400	1640	* @}
AnnaBridge	172:65be27845400	1641	*/
AnnaBridge	172:65be27845400	1642
AnnaBridge	172:65be27845400	1643	#ifdef __cplusplus
AnnaBridge	172:65be27845400	1644	}
AnnaBridge	172:65be27845400	1645	#endif
AnnaBridge	172:65be27845400	1646
AnnaBridge	172:65be27845400	1647	#endif /* STM32H7xx_HAL_ETH_H */
AnnaBridge	172:65be27845400	1648
AnnaBridge	172:65be27845400	1649
AnnaBridge	172:65be27845400	1650
AnnaBridge	172:65be27845400	1651	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/