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TARGET_NUCLEO_H743ZI/TOOLCHAIN_ARM_MICRO/stm32h7xx_hal_dma.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 172:65be27845400 1 /**
AnnaBridge 172:65be27845400 2 ******************************************************************************
AnnaBridge 172:65be27845400 3 * @file stm32h7xx_hal_dma.h
AnnaBridge 172:65be27845400 4 * @author MCD Application Team
AnnaBridge 172:65be27845400 5 * @brief Header file of DMA HAL module.
AnnaBridge 172:65be27845400 6 ******************************************************************************
AnnaBridge 172:65be27845400 7 * @attention
AnnaBridge 172:65be27845400 8 *
AnnaBridge 172:65be27845400 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
AnnaBridge 172:65be27845400 10 * All rights reserved.</center></h2>
AnnaBridge 172:65be27845400 11 *
AnnaBridge 172:65be27845400 12 * This software component is licensed by ST under BSD 3-Clause license,
AnnaBridge 172:65be27845400 13 * the "License"; You may not use this file except in compliance with the
AnnaBridge 172:65be27845400 14 * License. You may obtain a copy of the License at:
AnnaBridge 172:65be27845400 15 * opensource.org/licenses/BSD-3-Clause
AnnaBridge 172:65be27845400 16 *
AnnaBridge 172:65be27845400 17 ******************************************************************************
AnnaBridge 172:65be27845400 18 */
AnnaBridge 172:65be27845400 19
AnnaBridge 172:65be27845400 20 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 172:65be27845400 21 #ifndef STM32H7xx_HAL_DMA_H
AnnaBridge 172:65be27845400 22 #define STM32H7xx_HAL_DMA_H
AnnaBridge 172:65be27845400 23
AnnaBridge 172:65be27845400 24 #ifdef __cplusplus
AnnaBridge 172:65be27845400 25 extern "C" {
AnnaBridge 172:65be27845400 26 #endif
AnnaBridge 172:65be27845400 27
AnnaBridge 172:65be27845400 28 /* Includes ------------------------------------------------------------------*/
AnnaBridge 172:65be27845400 29 #include "stm32h7xx_hal_def.h"
AnnaBridge 172:65be27845400 30
AnnaBridge 172:65be27845400 31 /** @addtogroup STM32H7xx_HAL_Driver
AnnaBridge 172:65be27845400 32 * @{
AnnaBridge 172:65be27845400 33 */
AnnaBridge 172:65be27845400 34
AnnaBridge 172:65be27845400 35 /** @addtogroup DMA
AnnaBridge 172:65be27845400 36 * @{
AnnaBridge 172:65be27845400 37 */
AnnaBridge 172:65be27845400 38
AnnaBridge 172:65be27845400 39 /* Exported types ------------------------------------------------------------*/
AnnaBridge 172:65be27845400 40
AnnaBridge 172:65be27845400 41 /** @defgroup DMA_Exported_Types DMA Exported Types
AnnaBridge 172:65be27845400 42 * @brief DMA Exported Types
AnnaBridge 172:65be27845400 43 * @{
AnnaBridge 172:65be27845400 44 */
AnnaBridge 172:65be27845400 45
AnnaBridge 172:65be27845400 46 /**
AnnaBridge 172:65be27845400 47 * @brief DMA Configuration Structure definition
AnnaBridge 172:65be27845400 48 */
AnnaBridge 172:65be27845400 49 typedef struct
AnnaBridge 172:65be27845400 50 {
AnnaBridge 172:65be27845400 51 uint32_t Request; /*!< Specifies the request selected for the specified stream.
AnnaBridge 172:65be27845400 52 This parameter can be a value of @ref DMA_Request_selection */
AnnaBridge 172:65be27845400 53
AnnaBridge 172:65be27845400 54 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
AnnaBridge 172:65be27845400 55 from memory to memory or from peripheral to memory.
AnnaBridge 172:65be27845400 56 This parameter can be a value of @ref DMA_Data_transfer_direction */
AnnaBridge 172:65be27845400 57
AnnaBridge 172:65be27845400 58 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
AnnaBridge 172:65be27845400 59 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
AnnaBridge 172:65be27845400 60
AnnaBridge 172:65be27845400 61 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
AnnaBridge 172:65be27845400 62 This parameter can be a value of @ref DMA_Memory_incremented_mode */
AnnaBridge 172:65be27845400 63
AnnaBridge 172:65be27845400 64 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
AnnaBridge 172:65be27845400 65 This parameter can be a value of @ref DMA_Peripheral_data_size */
AnnaBridge 172:65be27845400 66
AnnaBridge 172:65be27845400 67 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
AnnaBridge 172:65be27845400 68 This parameter can be a value of @ref DMA_Memory_data_size */
AnnaBridge 172:65be27845400 69
AnnaBridge 172:65be27845400 70 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
AnnaBridge 172:65be27845400 71 This parameter can be a value of @ref DMA_mode
AnnaBridge 172:65be27845400 72 @note The circular buffer mode cannot be used if the memory-to-memory
AnnaBridge 172:65be27845400 73 data transfer is configured on the selected Stream */
AnnaBridge 172:65be27845400 74
AnnaBridge 172:65be27845400 75 uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
AnnaBridge 172:65be27845400 76 This parameter can be a value of @ref DMA_Priority_level */
AnnaBridge 172:65be27845400 77
AnnaBridge 172:65be27845400 78 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
AnnaBridge 172:65be27845400 79 This parameter can be a value of @ref DMA_FIFO_direct_mode
AnnaBridge 172:65be27845400 80 @note The Direct mode (FIFO mode disabled) cannot be used if the
AnnaBridge 172:65be27845400 81 memory-to-memory data transfer is configured on the selected stream */
AnnaBridge 172:65be27845400 82
AnnaBridge 172:65be27845400 83 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
AnnaBridge 172:65be27845400 84 This parameter can be a value of @ref DMA_FIFO_threshold_level */
AnnaBridge 172:65be27845400 85
AnnaBridge 172:65be27845400 86 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
AnnaBridge 172:65be27845400 87 It specifies the amount of data to be transferred in a single non interruptible
AnnaBridge 172:65be27845400 88 transaction.
AnnaBridge 172:65be27845400 89 This parameter can be a value of @ref DMA_Memory_burst
AnnaBridge 172:65be27845400 90 @note The burst mode is possible only if the address Increment mode is enabled. */
AnnaBridge 172:65be27845400 91
AnnaBridge 172:65be27845400 92 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
AnnaBridge 172:65be27845400 93 It specifies the amount of data to be transferred in a single non interruptible
AnnaBridge 172:65be27845400 94 transaction.
AnnaBridge 172:65be27845400 95 This parameter can be a value of @ref DMA_Peripheral_burst
AnnaBridge 172:65be27845400 96 @note The burst mode is possible only if the address Increment mode is enabled. */
AnnaBridge 172:65be27845400 97 }DMA_InitTypeDef;
AnnaBridge 172:65be27845400 98
AnnaBridge 172:65be27845400 99 /**
AnnaBridge 172:65be27845400 100 * @brief HAL DMA State structures definition
AnnaBridge 172:65be27845400 101 */
AnnaBridge 172:65be27845400 102 typedef enum
AnnaBridge 172:65be27845400 103 {
AnnaBridge 172:65be27845400 104 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
AnnaBridge 172:65be27845400 105 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
AnnaBridge 172:65be27845400 106 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
AnnaBridge 172:65be27845400 107 HAL_DMA_STATE_ERROR = 0x03U, /*!< DMA error state */
AnnaBridge 172:65be27845400 108 HAL_DMA_STATE_ABORT = 0x04U, /*!< DMA Abort state */
AnnaBridge 172:65be27845400 109 }HAL_DMA_StateTypeDef;
AnnaBridge 172:65be27845400 110
AnnaBridge 172:65be27845400 111 /**
AnnaBridge 172:65be27845400 112 * @brief HAL DMA Transfer complete level structure definition
AnnaBridge 172:65be27845400 113 */
AnnaBridge 172:65be27845400 114 typedef enum
AnnaBridge 172:65be27845400 115 {
AnnaBridge 172:65be27845400 116 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
AnnaBridge 172:65be27845400 117 HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half Transfer */
AnnaBridge 172:65be27845400 118 }HAL_DMA_LevelCompleteTypeDef;
AnnaBridge 172:65be27845400 119
AnnaBridge 172:65be27845400 120 /**
AnnaBridge 172:65be27845400 121 * @brief HAL DMA Callbacks IDs structure definition
AnnaBridge 172:65be27845400 122 */
AnnaBridge 172:65be27845400 123 typedef enum
AnnaBridge 172:65be27845400 124 {
AnnaBridge 172:65be27845400 125 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
AnnaBridge 172:65be27845400 126 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */
AnnaBridge 172:65be27845400 127 HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */
AnnaBridge 172:65be27845400 128 HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */
AnnaBridge 172:65be27845400 129 HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */
AnnaBridge 172:65be27845400 130 HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */
AnnaBridge 172:65be27845400 131 HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */
AnnaBridge 172:65be27845400 132 }HAL_DMA_CallbackIDTypeDef;
AnnaBridge 172:65be27845400 133
AnnaBridge 172:65be27845400 134 /**
AnnaBridge 172:65be27845400 135 * @brief DMA handle Structure definition
AnnaBridge 172:65be27845400 136 */
AnnaBridge 172:65be27845400 137 typedef struct __DMA_HandleTypeDef
AnnaBridge 172:65be27845400 138 {
AnnaBridge 172:65be27845400 139 void *Instance; /*!< Register base address */
AnnaBridge 172:65be27845400 140
AnnaBridge 172:65be27845400 141 DMA_InitTypeDef Init; /*!< DMA communication parameters */
AnnaBridge 172:65be27845400 142
AnnaBridge 172:65be27845400 143 HAL_LockTypeDef Lock; /*!< DMA locking object */
AnnaBridge 172:65be27845400 144
AnnaBridge 172:65be27845400 145 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
AnnaBridge 172:65be27845400 146
AnnaBridge 172:65be27845400 147 void *Parent; /*!< Parent object state */
AnnaBridge 172:65be27845400 148
AnnaBridge 172:65be27845400 149 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
AnnaBridge 172:65be27845400 150
AnnaBridge 172:65be27845400 151 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
AnnaBridge 172:65be27845400 152
AnnaBridge 172:65be27845400 153 void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
AnnaBridge 172:65be27845400 154
AnnaBridge 172:65be27845400 155 void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */
AnnaBridge 172:65be27845400 156
AnnaBridge 172:65be27845400 157 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
AnnaBridge 172:65be27845400 158
AnnaBridge 172:65be27845400 159 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */
AnnaBridge 172:65be27845400 160
AnnaBridge 172:65be27845400 161 __IO uint32_t ErrorCode; /*!< DMA Error code */
AnnaBridge 172:65be27845400 162
AnnaBridge 172:65be27845400 163 uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */
AnnaBridge 172:65be27845400 164
AnnaBridge 172:65be27845400 165 uint32_t StreamIndex; /*!< DMA Stream Index */
AnnaBridge 172:65be27845400 166
AnnaBridge 172:65be27845400 167 DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< DMAMUX Channel Base Address */
AnnaBridge 172:65be27845400 168
AnnaBridge 172:65be27845400 169 DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */
AnnaBridge 172:65be27845400 170
AnnaBridge 172:65be27845400 171 uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */
AnnaBridge 172:65be27845400 172
AnnaBridge 172:65be27845400 173
AnnaBridge 172:65be27845400 174 DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */
AnnaBridge 172:65be27845400 175
AnnaBridge 172:65be27845400 176 DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Status Address */
AnnaBridge 172:65be27845400 177
AnnaBridge 172:65be27845400 178 uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */
AnnaBridge 172:65be27845400 179
AnnaBridge 172:65be27845400 180 }DMA_HandleTypeDef;
AnnaBridge 172:65be27845400 181
AnnaBridge 172:65be27845400 182 /**
AnnaBridge 172:65be27845400 183 * @}
AnnaBridge 172:65be27845400 184 */
AnnaBridge 172:65be27845400 185
AnnaBridge 172:65be27845400 186
AnnaBridge 172:65be27845400 187 /* Exported constants --------------------------------------------------------*/
AnnaBridge 172:65be27845400 188
AnnaBridge 172:65be27845400 189 /** @defgroup DMA_Exported_Constants DMA Exported Constants
AnnaBridge 172:65be27845400 190 * @brief DMA Exported constants
AnnaBridge 172:65be27845400 191 * @{
AnnaBridge 172:65be27845400 192 */
AnnaBridge 172:65be27845400 193
AnnaBridge 172:65be27845400 194 /** @defgroup DMA_Error_Code DMA Error Code
AnnaBridge 172:65be27845400 195 * @brief DMA Error Code
AnnaBridge 172:65be27845400 196 * @{
AnnaBridge 172:65be27845400 197 */
AnnaBridge 172:65be27845400 198 #define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */
AnnaBridge 172:65be27845400 199 #define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */
AnnaBridge 172:65be27845400 200 #define HAL_DMA_ERROR_FE (0x00000002U) /*!< FIFO error */
AnnaBridge 172:65be27845400 201 #define HAL_DMA_ERROR_DME (0x00000004U) /*!< Direct Mode error */
AnnaBridge 172:65be27845400 202 #define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
AnnaBridge 172:65be27845400 203 #define HAL_DMA_ERROR_PARAM (0x00000040U) /*!< Parameter error */
AnnaBridge 172:65be27845400 204 #define HAL_DMA_ERROR_NO_XFER (0x00000080U) /*!< Abort requested with no Xfer ongoing */
AnnaBridge 172:65be27845400 205 #define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */
AnnaBridge 172:65be27845400 206 #define HAL_DMA_ERROR_SYNC (0x00000200U) /*!< DMAMUX sync overrun error */
AnnaBridge 172:65be27845400 207 #define HAL_DMA_ERROR_REQGEN (0x00000400U) /*!< DMAMUX request generator overrun error */
AnnaBridge 172:65be27845400 208 #define HAL_DMA_ERROR_BUSY (0x00000800U) /*!< DMA Busy error */
AnnaBridge 172:65be27845400 209
AnnaBridge 172:65be27845400 210 /**
AnnaBridge 172:65be27845400 211 * @}
AnnaBridge 172:65be27845400 212 */
AnnaBridge 172:65be27845400 213
AnnaBridge 172:65be27845400 214 /** @defgroup DMA_Request_selection DMA Request selection
AnnaBridge 172:65be27845400 215 * @brief DMA Request selection
AnnaBridge 172:65be27845400 216 * @{
AnnaBridge 172:65be27845400 217 */
AnnaBridge 172:65be27845400 218 /* DMAMUX1 requests */
AnnaBridge 172:65be27845400 219 #define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */
AnnaBridge 172:65be27845400 220
AnnaBridge 172:65be27845400 221 #define DMA_REQUEST_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */
AnnaBridge 172:65be27845400 222 #define DMA_REQUEST_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */
AnnaBridge 172:65be27845400 223 #define DMA_REQUEST_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */
AnnaBridge 172:65be27845400 224 #define DMA_REQUEST_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */
AnnaBridge 172:65be27845400 225 #define DMA_REQUEST_GENERATOR4 5U /*!< DMAMUX1 request generator 4 */
AnnaBridge 172:65be27845400 226 #define DMA_REQUEST_GENERATOR5 6U /*!< DMAMUX1 request generator 5 */
AnnaBridge 172:65be27845400 227 #define DMA_REQUEST_GENERATOR6 7U /*!< DMAMUX1 request generator 6 */
AnnaBridge 172:65be27845400 228 #define DMA_REQUEST_GENERATOR7 8U /*!< DMAMUX1 request generator 7 */
AnnaBridge 172:65be27845400 229
AnnaBridge 172:65be27845400 230 #define DMA_REQUEST_ADC1 9U /*!< DMAMUX1 ADC1 request */
AnnaBridge 172:65be27845400 231 #define DMA_REQUEST_ADC2 10U /*!< DMAMUX1 ADC2 request */
AnnaBridge 172:65be27845400 232
AnnaBridge 172:65be27845400 233 #define DMA_REQUEST_TIM1_CH1 11U /*!< DMAMUX1 TIM1 CH1 request */
AnnaBridge 172:65be27845400 234 #define DMA_REQUEST_TIM1_CH2 12U /*!< DMAMUX1 TIM1 CH2 request */
AnnaBridge 172:65be27845400 235 #define DMA_REQUEST_TIM1_CH3 13U /*!< DMAMUX1 TIM1 CH3 request */
AnnaBridge 172:65be27845400 236 #define DMA_REQUEST_TIM1_CH4 14U /*!< DMAMUX1 TIM1 CH4 request */
AnnaBridge 172:65be27845400 237 #define DMA_REQUEST_TIM1_UP 15U /*!< DMAMUX1 TIM1 UP request */
AnnaBridge 172:65be27845400 238 #define DMA_REQUEST_TIM1_TRIG 16U /*!< DMAMUX1 TIM1 TRIG request */
AnnaBridge 172:65be27845400 239 #define DMA_REQUEST_TIM1_COM 17U /*!< DMAMUX1 TIM1 COM request */
AnnaBridge 172:65be27845400 240
AnnaBridge 172:65be27845400 241 #define DMA_REQUEST_TIM2_CH1 18U /*!< DMAMUX1 TIM2 CH1 request */
AnnaBridge 172:65be27845400 242 #define DMA_REQUEST_TIM2_CH2 19U /*!< DMAMUX1 TIM2 CH2 request */
AnnaBridge 172:65be27845400 243 #define DMA_REQUEST_TIM2_CH3 20U /*!< DMAMUX1 TIM2 CH3 request */
AnnaBridge 172:65be27845400 244 #define DMA_REQUEST_TIM2_CH4 21U /*!< DMAMUX1 TIM2 CH4 request */
AnnaBridge 172:65be27845400 245 #define DMA_REQUEST_TIM2_UP 22U /*!< DMAMUX1 TIM2 UP request */
AnnaBridge 172:65be27845400 246
AnnaBridge 172:65be27845400 247 #define DMA_REQUEST_TIM3_CH1 23U /*!< DMAMUX1 TIM3 CH1 request */
AnnaBridge 172:65be27845400 248 #define DMA_REQUEST_TIM3_CH2 24U /*!< DMAMUX1 TIM3 CH2 request */
AnnaBridge 172:65be27845400 249 #define DMA_REQUEST_TIM3_CH3 25U /*!< DMAMUX1 TIM3 CH3 request */
AnnaBridge 172:65be27845400 250 #define DMA_REQUEST_TIM3_CH4 26U /*!< DMAMUX1 TIM3 CH4 request */
AnnaBridge 172:65be27845400 251 #define DMA_REQUEST_TIM3_UP 27U /*!< DMAMUX1 TIM3 UP request */
AnnaBridge 172:65be27845400 252 #define DMA_REQUEST_TIM3_TRIG 28U /*!< DMAMUX1 TIM3 TRIG request */
AnnaBridge 172:65be27845400 253
AnnaBridge 172:65be27845400 254 #define DMA_REQUEST_TIM4_CH1 29U /*!< DMAMUX1 TIM4 CH1 request */
AnnaBridge 172:65be27845400 255 #define DMA_REQUEST_TIM4_CH2 30U /*!< DMAMUX1 TIM4 CH2 request */
AnnaBridge 172:65be27845400 256 #define DMA_REQUEST_TIM4_CH3 31U /*!< DMAMUX1 TIM4 CH3 request */
AnnaBridge 172:65be27845400 257 #define DMA_REQUEST_TIM4_UP 32U /*!< DMAMUX1 TIM4 UP request */
AnnaBridge 172:65be27845400 258
AnnaBridge 172:65be27845400 259 #define DMA_REQUEST_I2C1_RX 33U /*!< DMAMUX1 I2C1 RX request */
AnnaBridge 172:65be27845400 260 #define DMA_REQUEST_I2C1_TX 34U /*!< DMAMUX1 I2C1 TX request */
AnnaBridge 172:65be27845400 261 #define DMA_REQUEST_I2C2_RX 35U /*!< DMAMUX1 I2C2 RX request */
AnnaBridge 172:65be27845400 262 #define DMA_REQUEST_I2C2_TX 36U /*!< DMAMUX1 I2C2 TX request */
AnnaBridge 172:65be27845400 263
AnnaBridge 172:65be27845400 264 #define DMA_REQUEST_SPI1_RX 37U /*!< DMAMUX1 SPI1 RX request */
AnnaBridge 172:65be27845400 265 #define DMA_REQUEST_SPI1_TX 38U /*!< DMAMUX1 SPI1 TX request */
AnnaBridge 172:65be27845400 266 #define DMA_REQUEST_SPI2_RX 39U /*!< DMAMUX1 SPI2 RX request */
AnnaBridge 172:65be27845400 267 #define DMA_REQUEST_SPI2_TX 40U /*!< DMAMUX1 SPI2 TX request */
AnnaBridge 172:65be27845400 268
AnnaBridge 172:65be27845400 269 #define DMA_REQUEST_USART1_RX 41U /*!< DMAMUX1 USART1 RX request */
AnnaBridge 172:65be27845400 270 #define DMA_REQUEST_USART1_TX 42U /*!< DMAMUX1 USART1 TX request */
AnnaBridge 172:65be27845400 271 #define DMA_REQUEST_USART2_RX 43U /*!< DMAMUX1 USART2 RX request */
AnnaBridge 172:65be27845400 272 #define DMA_REQUEST_USART2_TX 44U /*!< DMAMUX1 USART2 TX request */
AnnaBridge 172:65be27845400 273 #define DMA_REQUEST_USART3_RX 45U /*!< DMAMUX1 USART3 RX request */
AnnaBridge 172:65be27845400 274 #define DMA_REQUEST_USART3_TX 46U /*!< DMAMUX1 USART3 TX request */
AnnaBridge 172:65be27845400 275
AnnaBridge 172:65be27845400 276 #define DMA_REQUEST_TIM8_CH1 47U /*!< DMAMUX1 TIM8 CH1 request */
AnnaBridge 172:65be27845400 277 #define DMA_REQUEST_TIM8_CH2 48U /*!< DMAMUX1 TIM8 CH2 request */
AnnaBridge 172:65be27845400 278 #define DMA_REQUEST_TIM8_CH3 49U /*!< DMAMUX1 TIM8 CH3 request */
AnnaBridge 172:65be27845400 279 #define DMA_REQUEST_TIM8_CH4 50U /*!< DMAMUX1 TIM8 CH4 request */
AnnaBridge 172:65be27845400 280 #define DMA_REQUEST_TIM8_UP 51U /*!< DMAMUX1 TIM8 UP request */
AnnaBridge 172:65be27845400 281 #define DMA_REQUEST_TIM8_TRIG 52U /*!< DMAMUX1 TIM8 TRIG request */
AnnaBridge 172:65be27845400 282 #define DMA_REQUEST_TIM8_COM 53U /*!< DMAMUX1 TIM8 COM request */
AnnaBridge 172:65be27845400 283
AnnaBridge 172:65be27845400 284 #define DMA_REQUEST_TIM5_CH1 55U /*!< DMAMUX1 TIM5 CH1 request */
AnnaBridge 172:65be27845400 285 #define DMA_REQUEST_TIM5_CH2 56U /*!< DMAMUX1 TIM5 CH2 request */
AnnaBridge 172:65be27845400 286 #define DMA_REQUEST_TIM5_CH3 57U /*!< DMAMUX1 TIM5 CH3 request */
AnnaBridge 172:65be27845400 287 #define DMA_REQUEST_TIM5_CH4 58U /*!< DMAMUX1 TIM5 CH4 request */
AnnaBridge 172:65be27845400 288 #define DMA_REQUEST_TIM5_UP 59U /*!< DMAMUX1 TIM5 UP request */
AnnaBridge 172:65be27845400 289 #define DMA_REQUEST_TIM5_TRIG 60U /*!< DMAMUX1 TIM5 TRIG request */
AnnaBridge 172:65be27845400 290
AnnaBridge 172:65be27845400 291 #define DMA_REQUEST_SPI3_RX 61U /*!< DMAMUX1 SPI3 RX request */
AnnaBridge 172:65be27845400 292 #define DMA_REQUEST_SPI3_TX 62U /*!< DMAMUX1 SPI3 TX request */
AnnaBridge 172:65be27845400 293
AnnaBridge 172:65be27845400 294 #define DMA_REQUEST_UART4_RX 63U /*!< DMAMUX1 UART4 RX request */
AnnaBridge 172:65be27845400 295 #define DMA_REQUEST_UART4_TX 64U /*!< DMAMUX1 UART4 TX request */
AnnaBridge 172:65be27845400 296 #define DMA_REQUEST_UART5_RX 65U /*!< DMAMUX1 UART5 RX request */
AnnaBridge 172:65be27845400 297 #define DMA_REQUEST_UART5_TX 66U /*!< DMAMUX1 UART5 TX request */
AnnaBridge 172:65be27845400 298
AnnaBridge 172:65be27845400 299 #define DMA_REQUEST_DAC1_CH1 67U /*!< DMAMUX1 DAC1 Channel 1 request */
AnnaBridge 172:65be27845400 300 #define DMA_REQUEST_DAC1_CH2 68U /*!< DMAMUX1 DAC1 Channel 2 request */
AnnaBridge 172:65be27845400 301
AnnaBridge 172:65be27845400 302 #define DMA_REQUEST_TIM6_UP 69U /*!< DMAMUX1 TIM6 UP request */
AnnaBridge 172:65be27845400 303 #define DMA_REQUEST_TIM7_UP 70U /*!< DMAMUX1 TIM7 UP request */
AnnaBridge 172:65be27845400 304
AnnaBridge 172:65be27845400 305 #define DMA_REQUEST_USART6_RX 71U /*!< DMAMUX1 USART6 RX request */
AnnaBridge 172:65be27845400 306 #define DMA_REQUEST_USART6_TX 72U /*!< DMAMUX1 USART6 TX request */
AnnaBridge 172:65be27845400 307
AnnaBridge 172:65be27845400 308 #define DMA_REQUEST_I2C3_RX 73U /*!< DMAMUX1 I2C3 RX request */
AnnaBridge 172:65be27845400 309 #define DMA_REQUEST_I2C3_TX 74U /*!< DMAMUX1 I2C3 TX request */
AnnaBridge 172:65be27845400 310
AnnaBridge 172:65be27845400 311 #define DMA_REQUEST_DCMI 75U /*!< DMAMUX1 DCMI request */
AnnaBridge 172:65be27845400 312
AnnaBridge 172:65be27845400 313 #define DMA_REQUEST_CRYP_IN 76U /*!< DMAMUX1 CRYP IN request */
AnnaBridge 172:65be27845400 314 #define DMA_REQUEST_CRYP_OUT 77U /*!< DMAMUX1 CRYP OUT request */
AnnaBridge 172:65be27845400 315
AnnaBridge 172:65be27845400 316 #define DMA_REQUEST_HASH_IN 78U /*!< DMAMUX1 HASH IN request */
AnnaBridge 172:65be27845400 317
AnnaBridge 172:65be27845400 318 #define DMA_REQUEST_UART7_RX 79U /*!< DMAMUX1 UART7 RX request */
AnnaBridge 172:65be27845400 319 #define DMA_REQUEST_UART7_TX 80U /*!< DMAMUX1 UART7 TX request */
AnnaBridge 172:65be27845400 320 #define DMA_REQUEST_UART8_RX 81U /*!< DMAMUX1 UART8 RX request */
AnnaBridge 172:65be27845400 321 #define DMA_REQUEST_UART8_TX 82U /*!< DMAMUX1 UART8 TX request */
AnnaBridge 172:65be27845400 322
AnnaBridge 172:65be27845400 323 #define DMA_REQUEST_SPI4_RX 83U /*!< DMAMUX1 SPI4 RX request */
AnnaBridge 172:65be27845400 324 #define DMA_REQUEST_SPI4_TX 84U /*!< DMAMUX1 SPI4 TX request */
AnnaBridge 172:65be27845400 325 #define DMA_REQUEST_SPI5_RX 85U /*!< DMAMUX1 SPI5 RX request */
AnnaBridge 172:65be27845400 326 #define DMA_REQUEST_SPI5_TX 86U /*!< DMAMUX1 SPI5 TX request */
AnnaBridge 172:65be27845400 327
AnnaBridge 172:65be27845400 328 #define DMA_REQUEST_SAI1_A 87U /*!< DMAMUX1 SAI1 A request */
AnnaBridge 172:65be27845400 329 #define DMA_REQUEST_SAI1_B 88U /*!< DMAMUX1 SAI1 B request */
AnnaBridge 172:65be27845400 330 #define DMA_REQUEST_SAI2_A 89U /*!< DMAMUX1 SAI2 A request */
AnnaBridge 172:65be27845400 331 #define DMA_REQUEST_SAI2_B 90U /*!< DMAMUX1 SAI2 B request */
AnnaBridge 172:65be27845400 332
AnnaBridge 172:65be27845400 333 #define DMA_REQUEST_SWPMI_RX 91U /*!< DMAMUX1 SWPMI RX request */
AnnaBridge 172:65be27845400 334 #define DMA_REQUEST_SWPMI_TX 92U /*!< DMAMUX1 SWPMI TX request */
AnnaBridge 172:65be27845400 335
AnnaBridge 172:65be27845400 336 #define DMA_REQUEST_SPDIF_RX_DT 93U /*!< DMAMUX1 SPDIF RXDT request*/
AnnaBridge 172:65be27845400 337 #define DMA_REQUEST_SPDIF_RX_CS 94U /*!< DMAMUX1 SPDIF RXCS request*/
AnnaBridge 172:65be27845400 338
AnnaBridge 172:65be27845400 339 #define DMA_REQUEST_HRTIM_MASTER 95U /*!< DMAMUX1 HRTIM1 Master request 1 */
AnnaBridge 172:65be27845400 340 #define DMA_REQUEST_HRTIM_TIMER_A 96U /*!< DMAMUX1 HRTIM1 TimerA request 2 */
AnnaBridge 172:65be27845400 341 #define DMA_REQUEST_HRTIM_TIMER_B 97U /*!< DMAMUX1 HRTIM1 TimerB request 3 */
AnnaBridge 172:65be27845400 342 #define DMA_REQUEST_HRTIM_TIMER_C 98U /*!< DMAMUX1 HRTIM1 TimerC request 4 */
AnnaBridge 172:65be27845400 343 #define DMA_REQUEST_HRTIM_TIMER_D 99U /*!< DMAMUX1 HRTIM1 TimerD request 5 */
AnnaBridge 172:65be27845400 344 #define DMA_REQUEST_HRTIM_TIMER_E 100U /*!< DMAMUX1 HRTIM1 TimerE request 6 */
AnnaBridge 172:65be27845400 345
AnnaBridge 172:65be27845400 346 #define DMA_REQUEST_DFSDM1_FLT0 101U /*!< DMAMUX1 DFSDM Filter0 request */
AnnaBridge 172:65be27845400 347 #define DMA_REQUEST_DFSDM1_FLT1 102U /*!< DMAMUX1 DFSDM Filter1 request */
AnnaBridge 172:65be27845400 348 #define DMA_REQUEST_DFSDM1_FLT2 103U /*!< DMAMUX1 DFSDM Filter2 request */
AnnaBridge 172:65be27845400 349 #define DMA_REQUEST_DFSDM1_FLT3 104U /*!< DMAMUX1 DFSDM Filter3 request */
AnnaBridge 172:65be27845400 350
AnnaBridge 172:65be27845400 351 #define DMA_REQUEST_TIM15_CH1 105U /*!< DMAMUX1 TIM15 CH1 request */
AnnaBridge 172:65be27845400 352 #define DMA_REQUEST_TIM15_UP 106U /*!< DMAMUX1 TIM15 UP request */
AnnaBridge 172:65be27845400 353 #define DMA_REQUEST_TIM15_TRIG 107U /*!< DMAMUX1 TIM15 TRIG request */
AnnaBridge 172:65be27845400 354 #define DMA_REQUEST_TIM15_COM 108U /*!< DMAMUX1 TIM15 COM request */
AnnaBridge 172:65be27845400 355
AnnaBridge 172:65be27845400 356 #define DMA_REQUEST_TIM16_CH1 109U /*!< DMAMUX1 TIM16 CH1 request */
AnnaBridge 172:65be27845400 357 #define DMA_REQUEST_TIM16_UP 110U /*!< DMAMUX1 TIM16 UP request */
AnnaBridge 172:65be27845400 358
AnnaBridge 172:65be27845400 359 #define DMA_REQUEST_TIM17_CH1 111U /*!< DMAMUX1 TIM17 CH1 request */
AnnaBridge 172:65be27845400 360 #define DMA_REQUEST_TIM17_UP 112U /*!< DMAMUX1 TIM17 UP request */
AnnaBridge 172:65be27845400 361
AnnaBridge 172:65be27845400 362 #define DMA_REQUEST_SAI3_A 113U /*!< DMAMUX1 SAI3 A request */
AnnaBridge 172:65be27845400 363 #define DMA_REQUEST_SAI3_B 114U /*!< DMAMUX1 SAI3 B request */
AnnaBridge 172:65be27845400 364
AnnaBridge 172:65be27845400 365 #define DMA_REQUEST_ADC3 115U /*!< DMAMUX1 ADC3 request */
AnnaBridge 172:65be27845400 366
AnnaBridge 172:65be27845400 367
AnnaBridge 172:65be27845400 368 /* DMAMUX2 requests */
AnnaBridge 172:65be27845400 369 #define BDMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */
AnnaBridge 172:65be27845400 370 #define BDMA_REQUEST_GENERATOR0 1U /*!< DMAMUX2 request generator 0 */
AnnaBridge 172:65be27845400 371 #define BDMA_REQUEST_GENERATOR1 2U /*!< DMAMUX2 request generator 1 */
AnnaBridge 172:65be27845400 372 #define BDMA_REQUEST_GENERATOR2 3U /*!< DMAMUX2 request generator 2 */
AnnaBridge 172:65be27845400 373 #define BDMA_REQUEST_GENERATOR3 4U /*!< DMAMUX2 request generator 3 */
AnnaBridge 172:65be27845400 374 #define BDMA_REQUEST_GENERATOR4 5U /*!< DMAMUX2 request generator 4 */
AnnaBridge 172:65be27845400 375 #define BDMA_REQUEST_GENERATOR5 6U /*!< DMAMUX2 request generator 5 */
AnnaBridge 172:65be27845400 376 #define BDMA_REQUEST_GENERATOR6 7U /*!< DMAMUX2 request generator 6 */
AnnaBridge 172:65be27845400 377 #define BDMA_REQUEST_GENERATOR7 8U /*!< DMAMUX2 request generator 7 */
AnnaBridge 172:65be27845400 378 #define BDMA_REQUEST_LPUART1_RX 9U /*!< DMAMUX2 LP_UART1_RX request */
AnnaBridge 172:65be27845400 379 #define BDMA_REQUEST_LPUART1_TX 10U /*!< DMAMUX2 LP_UART1_TX request */
AnnaBridge 172:65be27845400 380 #define BDMA_REQUEST_SPI6_RX 11U /*!< DMAMUX2 SPI6 RX request */
AnnaBridge 172:65be27845400 381 #define BDMA_REQUEST_SPI6_TX 12U /*!< DMAMUX2 SPI6 TX request */
AnnaBridge 172:65be27845400 382 #define BDMA_REQUEST_I2C4_RX 13U /*!< DMAMUX2 I2C4 RX request */
AnnaBridge 172:65be27845400 383 #define BDMA_REQUEST_I2C4_TX 14U /*!< DMAMUX2 I2C4 TX request */
AnnaBridge 172:65be27845400 384 #define BDMA_REQUEST_SAI4_A 15U /*!< DMAMUX2 SAI4 A request */
AnnaBridge 172:65be27845400 385 #define BDMA_REQUEST_SAI4_B 16U /*!< DMAMUX2 SAI4 B request */
AnnaBridge 172:65be27845400 386 #define BDMA_REQUEST_ADC3 17U /*!< DMAMUX2 ADC3 request */
AnnaBridge 172:65be27845400 387
AnnaBridge 172:65be27845400 388 /**
AnnaBridge 172:65be27845400 389 * @}
AnnaBridge 172:65be27845400 390 */
AnnaBridge 172:65be27845400 391
AnnaBridge 172:65be27845400 392 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
AnnaBridge 172:65be27845400 393 * @brief DMA data transfer direction
AnnaBridge 172:65be27845400 394 * @{
AnnaBridge 172:65be27845400 395 */
AnnaBridge 172:65be27845400 396 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */
AnnaBridge 172:65be27845400 397 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
AnnaBridge 172:65be27845400 398 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
AnnaBridge 172:65be27845400 399 /**
AnnaBridge 172:65be27845400 400 * @}
AnnaBridge 172:65be27845400 401 */
AnnaBridge 172:65be27845400 402
AnnaBridge 172:65be27845400 403 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
AnnaBridge 172:65be27845400 404 * @brief DMA peripheral incremented mode
AnnaBridge 172:65be27845400 405 * @{
AnnaBridge 172:65be27845400 406 */
AnnaBridge 172:65be27845400 407 #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
AnnaBridge 172:65be27845400 408 #define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode disable */
AnnaBridge 172:65be27845400 409 /**
AnnaBridge 172:65be27845400 410 * @}
AnnaBridge 172:65be27845400 411 */
AnnaBridge 172:65be27845400 412
AnnaBridge 172:65be27845400 413 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
AnnaBridge 172:65be27845400 414 * @brief DMA memory incremented mode
AnnaBridge 172:65be27845400 415 * @{
AnnaBridge 172:65be27845400 416 */
AnnaBridge 172:65be27845400 417 #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
AnnaBridge 172:65be27845400 418 #define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode disable */
AnnaBridge 172:65be27845400 419 /**
AnnaBridge 172:65be27845400 420 * @}
AnnaBridge 172:65be27845400 421 */
AnnaBridge 172:65be27845400 422
AnnaBridge 172:65be27845400 423 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
AnnaBridge 172:65be27845400 424 * @brief DMA peripheral data size
AnnaBridge 172:65be27845400 425 * @{
AnnaBridge 172:65be27845400 426 */
AnnaBridge 172:65be27845400 427 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment: Byte */
AnnaBridge 172:65be27845400 428 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
AnnaBridge 172:65be27845400 429 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
AnnaBridge 172:65be27845400 430 /**
AnnaBridge 172:65be27845400 431 * @}
AnnaBridge 172:65be27845400 432 */
AnnaBridge 172:65be27845400 433
AnnaBridge 172:65be27845400 434 /** @defgroup DMA_Memory_data_size DMA Memory data size
AnnaBridge 172:65be27845400 435 * @brief DMA memory data size
AnnaBridge 172:65be27845400 436 * @{
AnnaBridge 172:65be27845400 437 */
AnnaBridge 172:65be27845400 438 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment: Byte */
AnnaBridge 172:65be27845400 439 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
AnnaBridge 172:65be27845400 440 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
AnnaBridge 172:65be27845400 441 /**
AnnaBridge 172:65be27845400 442 * @}
AnnaBridge 172:65be27845400 443 */
AnnaBridge 172:65be27845400 444
AnnaBridge 172:65be27845400 445 /** @defgroup DMA_mode DMA mode
AnnaBridge 172:65be27845400 446 * @brief DMA mode
AnnaBridge 172:65be27845400 447 * @{
AnnaBridge 172:65be27845400 448 */
AnnaBridge 172:65be27845400 449 #define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */
AnnaBridge 172:65be27845400 450 #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
AnnaBridge 172:65be27845400 451 #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
AnnaBridge 172:65be27845400 452 #define DMA_DOUBLE_BUFFER_M0 ((uint32_t)DMA_SxCR_DBM) /*!< Double buffer mode with first target memory M0 */
AnnaBridge 172:65be27845400 453 #define DMA_DOUBLE_BUFFER_M1 ((uint32_t)(DMA_SxCR_DBM | DMA_SxCR_CT)) /*!< Double buffer mode with first target memory M1 */
AnnaBridge 172:65be27845400 454 /**
AnnaBridge 172:65be27845400 455 * @}
AnnaBridge 172:65be27845400 456 */
AnnaBridge 172:65be27845400 457
AnnaBridge 172:65be27845400 458 /** @defgroup DMA_Priority_level DMA Priority level
AnnaBridge 172:65be27845400 459 * @brief DMA priority levels
AnnaBridge 172:65be27845400 460 * @{
AnnaBridge 172:65be27845400 461 */
AnnaBridge 172:65be27845400 462 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */
AnnaBridge 172:65be27845400 463 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
AnnaBridge 172:65be27845400 464 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
AnnaBridge 172:65be27845400 465 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
AnnaBridge 172:65be27845400 466 /**
AnnaBridge 172:65be27845400 467 * @}
AnnaBridge 172:65be27845400 468 */
AnnaBridge 172:65be27845400 469
AnnaBridge 172:65be27845400 470 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
AnnaBridge 172:65be27845400 471 * @brief DMA FIFO direct mode
AnnaBridge 172:65be27845400 472 * @{
AnnaBridge 172:65be27845400 473 */
AnnaBridge 172:65be27845400 474 #define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U) /*!< FIFO mode disable */
AnnaBridge 172:65be27845400 475 #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
AnnaBridge 172:65be27845400 476 /**
AnnaBridge 172:65be27845400 477 * @}
AnnaBridge 172:65be27845400 478 */
AnnaBridge 172:65be27845400 479
AnnaBridge 172:65be27845400 480 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
AnnaBridge 172:65be27845400 481 * @brief DMA FIFO level
AnnaBridge 172:65be27845400 482 * @{
AnnaBridge 172:65be27845400 483 */
AnnaBridge 172:65be27845400 484 #define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U) /*!< FIFO threshold 1 quart full configuration */
AnnaBridge 172:65be27845400 485 #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
AnnaBridge 172:65be27845400 486 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
AnnaBridge 172:65be27845400 487 #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
AnnaBridge 172:65be27845400 488 /**
AnnaBridge 172:65be27845400 489 * @}
AnnaBridge 172:65be27845400 490 */
AnnaBridge 172:65be27845400 491
AnnaBridge 172:65be27845400 492 /** @defgroup DMA_Memory_burst DMA Memory burst
AnnaBridge 172:65be27845400 493 * @brief DMA memory burst
AnnaBridge 172:65be27845400 494 * @{
AnnaBridge 172:65be27845400 495 */
AnnaBridge 172:65be27845400 496 #define DMA_MBURST_SINGLE ((uint32_t)0x00000000U)
AnnaBridge 172:65be27845400 497 #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
AnnaBridge 172:65be27845400 498 #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
AnnaBridge 172:65be27845400 499 #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
AnnaBridge 172:65be27845400 500 /**
AnnaBridge 172:65be27845400 501 * @}
AnnaBridge 172:65be27845400 502 */
AnnaBridge 172:65be27845400 503
AnnaBridge 172:65be27845400 504 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst
AnnaBridge 172:65be27845400 505 * @brief DMA peripheral burst
AnnaBridge 172:65be27845400 506 * @{
AnnaBridge 172:65be27845400 507 */
AnnaBridge 172:65be27845400 508 #define DMA_PBURST_SINGLE ((uint32_t)0x00000000U)
AnnaBridge 172:65be27845400 509 #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
AnnaBridge 172:65be27845400 510 #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
AnnaBridge 172:65be27845400 511 #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
AnnaBridge 172:65be27845400 512 /**
AnnaBridge 172:65be27845400 513 * @}
AnnaBridge 172:65be27845400 514 */
AnnaBridge 172:65be27845400 515
AnnaBridge 172:65be27845400 516 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
AnnaBridge 172:65be27845400 517 * @brief DMA interrupts definition
AnnaBridge 172:65be27845400 518 * @{
AnnaBridge 172:65be27845400 519 */
AnnaBridge 172:65be27845400 520 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
AnnaBridge 172:65be27845400 521 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
AnnaBridge 172:65be27845400 522 #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
AnnaBridge 172:65be27845400 523 #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
AnnaBridge 172:65be27845400 524 #define DMA_IT_FE ((uint32_t)0x00000080U)
AnnaBridge 172:65be27845400 525 /**
AnnaBridge 172:65be27845400 526 * @}
AnnaBridge 172:65be27845400 527 */
AnnaBridge 172:65be27845400 528
AnnaBridge 172:65be27845400 529 /** @defgroup DMA_flag_definitions DMA flag definitions
AnnaBridge 172:65be27845400 530 * @brief DMA flag definitions
AnnaBridge 172:65be27845400 531 * @{
AnnaBridge 172:65be27845400 532 */
AnnaBridge 172:65be27845400 533 #define DMA_FLAG_FEIF0_4 ((uint32_t)0x00000001U)
AnnaBridge 172:65be27845400 534 #define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00000004U)
AnnaBridge 172:65be27845400 535 #define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U)
AnnaBridge 172:65be27845400 536 #define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U)
AnnaBridge 172:65be27845400 537 #define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U)
AnnaBridge 172:65be27845400 538 #define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U)
AnnaBridge 172:65be27845400 539 #define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U)
AnnaBridge 172:65be27845400 540 #define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U)
AnnaBridge 172:65be27845400 541 #define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U)
AnnaBridge 172:65be27845400 542 #define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U)
AnnaBridge 172:65be27845400 543 #define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U)
AnnaBridge 172:65be27845400 544 #define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U)
AnnaBridge 172:65be27845400 545 #define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U)
AnnaBridge 172:65be27845400 546 #define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U)
AnnaBridge 172:65be27845400 547 #define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U)
AnnaBridge 172:65be27845400 548 #define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U)
AnnaBridge 172:65be27845400 549 #define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U)
AnnaBridge 172:65be27845400 550 #define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U)
AnnaBridge 172:65be27845400 551 #define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U)
AnnaBridge 172:65be27845400 552 #define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U)
AnnaBridge 172:65be27845400 553 /**
AnnaBridge 172:65be27845400 554 * @}
AnnaBridge 172:65be27845400 555 */
AnnaBridge 172:65be27845400 556
AnnaBridge 172:65be27845400 557 /** @defgroup BDMA_flag_definitions BDMA flag definitions
AnnaBridge 172:65be27845400 558 * @brief BDMA flag definitions
AnnaBridge 172:65be27845400 559 * @{
AnnaBridge 172:65be27845400 560 */
AnnaBridge 172:65be27845400 561 #define BDMA_FLAG_GL0 ((uint32_t)0x00000001)
AnnaBridge 172:65be27845400 562 #define BDMA_FLAG_TC0 ((uint32_t)0x00000002)
AnnaBridge 172:65be27845400 563 #define BDMA_FLAG_HT0 ((uint32_t)0x00000004)
AnnaBridge 172:65be27845400 564 #define BDMA_FLAG_TE0 ((uint32_t)0x00000008)
AnnaBridge 172:65be27845400 565 #define BDMA_FLAG_GL1 ((uint32_t)0x00000010)
AnnaBridge 172:65be27845400 566 #define BDMA_FLAG_TC1 ((uint32_t)0x00000020)
AnnaBridge 172:65be27845400 567 #define BDMA_FLAG_HT1 ((uint32_t)0x00000040)
AnnaBridge 172:65be27845400 568 #define BDMA_FLAG_TE1 ((uint32_t)0x00000080)
AnnaBridge 172:65be27845400 569 #define BDMA_FLAG_GL2 ((uint32_t)0x00000100)
AnnaBridge 172:65be27845400 570 #define BDMA_FLAG_TC2 ((uint32_t)0x00000200)
AnnaBridge 172:65be27845400 571 #define BDMA_FLAG_HT2 ((uint32_t)0x00000400)
AnnaBridge 172:65be27845400 572 #define BDMA_FLAG_TE2 ((uint32_t)0x00000800)
AnnaBridge 172:65be27845400 573 #define BDMA_FLAG_GL3 ((uint32_t)0x00001000)
AnnaBridge 172:65be27845400 574 #define BDMA_FLAG_TC3 ((uint32_t)0x00002000)
AnnaBridge 172:65be27845400 575 #define BDMA_FLAG_HT3 ((uint32_t)0x00004000)
AnnaBridge 172:65be27845400 576 #define BDMA_FLAG_TE3 ((uint32_t)0x00008000)
AnnaBridge 172:65be27845400 577 #define BDMA_FLAG_GL4 ((uint32_t)0x00010000)
AnnaBridge 172:65be27845400 578 #define BDMA_FLAG_TC4 ((uint32_t)0x00020000)
AnnaBridge 172:65be27845400 579 #define BDMA_FLAG_HT4 ((uint32_t)0x00040000)
AnnaBridge 172:65be27845400 580 #define BDMA_FLAG_TE4 ((uint32_t)0x00080000)
AnnaBridge 172:65be27845400 581 #define BDMA_FLAG_GL5 ((uint32_t)0x00100000)
AnnaBridge 172:65be27845400 582 #define BDMA_FLAG_TC5 ((uint32_t)0x00200000)
AnnaBridge 172:65be27845400 583 #define BDMA_FLAG_HT5 ((uint32_t)0x00400000)
AnnaBridge 172:65be27845400 584 #define BDMA_FLAG_TE5 ((uint32_t)0x00800000)
AnnaBridge 172:65be27845400 585 #define BDMA_FLAG_GL6 ((uint32_t)0x01000000)
AnnaBridge 172:65be27845400 586 #define BDMA_FLAG_TC6 ((uint32_t)0x02000000)
AnnaBridge 172:65be27845400 587 #define BDMA_FLAG_HT6 ((uint32_t)0x04000000)
AnnaBridge 172:65be27845400 588 #define BDMA_FLAG_TE6 ((uint32_t)0x08000000)
AnnaBridge 172:65be27845400 589 #define BDMA_FLAG_GL7 ((uint32_t)0x10000000)
AnnaBridge 172:65be27845400 590 #define BDMA_FLAG_TC7 ((uint32_t)0x20000000)
AnnaBridge 172:65be27845400 591 #define BDMA_FLAG_HT7 ((uint32_t)0x40000000)
AnnaBridge 172:65be27845400 592 #define BDMA_FLAG_TE7 ((uint32_t)0x80000000)
AnnaBridge 172:65be27845400 593
AnnaBridge 172:65be27845400 594 /**
AnnaBridge 172:65be27845400 595 * @}
AnnaBridge 172:65be27845400 596 */
AnnaBridge 172:65be27845400 597
AnnaBridge 172:65be27845400 598 /**
AnnaBridge 172:65be27845400 599 * @}
AnnaBridge 172:65be27845400 600 */
AnnaBridge 172:65be27845400 601
AnnaBridge 172:65be27845400 602 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 172:65be27845400 603 /** @defgroup DMA_Exported_Macros DMA Exported Macros
AnnaBridge 172:65be27845400 604 * @{
AnnaBridge 172:65be27845400 605 */
AnnaBridge 172:65be27845400 606
AnnaBridge 172:65be27845400 607 /** @brief Reset DMA handle state
AnnaBridge 172:65be27845400 608 * @param __HANDLE__: specifies the DMA handle.
AnnaBridge 172:65be27845400 609 * @retval None
AnnaBridge 172:65be27845400 610 */
AnnaBridge 172:65be27845400 611 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
AnnaBridge 172:65be27845400 612
AnnaBridge 172:65be27845400 613 /**
AnnaBridge 172:65be27845400 614 * @brief Return the current DMA Stream FIFO filled level.
AnnaBridge 172:65be27845400 615 * @param __HANDLE__: DMA handle
AnnaBridge 172:65be27845400 616 * @retval The FIFO filling state.
AnnaBridge 172:65be27845400 617 * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
AnnaBridge 172:65be27845400 618 * and not empty.
AnnaBridge 172:65be27845400 619 * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
AnnaBridge 172:65be27845400 620 * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
AnnaBridge 172:65be27845400 621 * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
AnnaBridge 172:65be27845400 622 * - DMA_FIFOStatus_Empty: when FIFO is empty
AnnaBridge 172:65be27845400 623 * - DMA_FIFOStatus_Full: when FIFO is full
AnnaBridge 172:65be27845400 624 */
AnnaBridge 172:65be27845400 625 #define __HAL_DMA_GET_FS(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (DMA_SxFCR_FS)) : 0)
AnnaBridge 172:65be27845400 626
AnnaBridge 172:65be27845400 627 /**
AnnaBridge 172:65be27845400 628 * @brief Enable the specified DMA Stream.
AnnaBridge 172:65be27845400 629 * @param __HANDLE__: DMA handle
AnnaBridge 172:65be27845400 630 * @retval None
AnnaBridge 172:65be27845400 631 */
AnnaBridge 172:65be27845400 632 #define __HAL_DMA_ENABLE(__HANDLE__) \
AnnaBridge 172:65be27845400 633 ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= DMA_SxCR_EN) : \
AnnaBridge 172:65be27845400 634 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= BDMA_CCR_EN))
AnnaBridge 172:65be27845400 635
AnnaBridge 172:65be27845400 636 /**
AnnaBridge 172:65be27845400 637 * @brief Disable the specified DMA Stream.
AnnaBridge 172:65be27845400 638 * @param __HANDLE__: DMA handle
AnnaBridge 172:65be27845400 639 * @retval None
AnnaBridge 172:65be27845400 640 */
AnnaBridge 172:65be27845400 641 #define __HAL_DMA_DISABLE(__HANDLE__) \
AnnaBridge 172:65be27845400 642 ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~DMA_SxCR_EN) : \
AnnaBridge 172:65be27845400 643 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~BDMA_CCR_EN))
AnnaBridge 172:65be27845400 644
AnnaBridge 172:65be27845400 645 /* Interrupt & Flag management */
AnnaBridge 172:65be27845400 646
AnnaBridge 172:65be27845400 647 /**
AnnaBridge 172:65be27845400 648 * @brief Return the current DMA Stream transfer complete flag.
AnnaBridge 172:65be27845400 649 * @param __HANDLE__: DMA handle
AnnaBridge 172:65be27845400 650 * @retval The specified transfer complete flag index.
AnnaBridge 172:65be27845400 651 */
AnnaBridge 172:65be27845400 652 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
AnnaBridge 172:65be27845400 653 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
AnnaBridge 172:65be27845400 654 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
AnnaBridge 172:65be27845400 655 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
AnnaBridge 172:65be27845400 656 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
AnnaBridge 172:65be27845400 657 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
AnnaBridge 172:65be27845400 658 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
AnnaBridge 172:65be27845400 659 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
AnnaBridge 172:65be27845400 660 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
AnnaBridge 172:65be27845400 661 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
AnnaBridge 172:65be27845400 662 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
AnnaBridge 172:65be27845400 663 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
AnnaBridge 172:65be27845400 664 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
AnnaBridge 172:65be27845400 665 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\
AnnaBridge 172:65be27845400 666 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\
AnnaBridge 172:65be27845400 667 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\
AnnaBridge 172:65be27845400 668 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\
AnnaBridge 172:65be27845400 669 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TC0 :\
AnnaBridge 172:65be27845400 670 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TC1 :\
AnnaBridge 172:65be27845400 671 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TC2 :\
AnnaBridge 172:65be27845400 672 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TC3 :\
AnnaBridge 172:65be27845400 673 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TC4 :\
AnnaBridge 172:65be27845400 674 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TC5 :\
AnnaBridge 172:65be27845400 675 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TC6 :\
AnnaBridge 172:65be27845400 676 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TC7 :\
AnnaBridge 172:65be27845400 677 (uint32_t)0x00000000)
AnnaBridge 172:65be27845400 678
AnnaBridge 172:65be27845400 679 /**
AnnaBridge 172:65be27845400 680 * @brief Return the current DMA Stream half transfer complete flag.
AnnaBridge 172:65be27845400 681 * @param __HANDLE__: DMA handle
AnnaBridge 172:65be27845400 682 * @retval The specified half transfer complete flag index.
AnnaBridge 172:65be27845400 683 */
AnnaBridge 172:65be27845400 684 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
AnnaBridge 172:65be27845400 685 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
AnnaBridge 172:65be27845400 686 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
AnnaBridge 172:65be27845400 687 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
AnnaBridge 172:65be27845400 688 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
AnnaBridge 172:65be27845400 689 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
AnnaBridge 172:65be27845400 690 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
AnnaBridge 172:65be27845400 691 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
AnnaBridge 172:65be27845400 692 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
AnnaBridge 172:65be27845400 693 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
AnnaBridge 172:65be27845400 694 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
AnnaBridge 172:65be27845400 695 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
AnnaBridge 172:65be27845400 696 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
AnnaBridge 172:65be27845400 697 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\
AnnaBridge 172:65be27845400 698 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\
AnnaBridge 172:65be27845400 699 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\
AnnaBridge 172:65be27845400 700 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\
AnnaBridge 172:65be27845400 701 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_HT0 :\
AnnaBridge 172:65be27845400 702 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_HT1 :\
AnnaBridge 172:65be27845400 703 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_HT2 :\
AnnaBridge 172:65be27845400 704 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_HT3 :\
AnnaBridge 172:65be27845400 705 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_HT4 :\
AnnaBridge 172:65be27845400 706 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_HT5 :\
AnnaBridge 172:65be27845400 707 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_HT6 :\
AnnaBridge 172:65be27845400 708 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_HT7 :\
AnnaBridge 172:65be27845400 709 (uint32_t)0x00000000)
AnnaBridge 172:65be27845400 710
AnnaBridge 172:65be27845400 711 /**
AnnaBridge 172:65be27845400 712 * @brief Return the current DMA Stream transfer error flag.
AnnaBridge 172:65be27845400 713 * @param __HANDLE__: DMA handle
AnnaBridge 172:65be27845400 714 * @retval The specified transfer error flag index.
AnnaBridge 172:65be27845400 715 */
AnnaBridge 172:65be27845400 716 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
AnnaBridge 172:65be27845400 717 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
AnnaBridge 172:65be27845400 718 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
AnnaBridge 172:65be27845400 719 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
AnnaBridge 172:65be27845400 720 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
AnnaBridge 172:65be27845400 721 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
AnnaBridge 172:65be27845400 722 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
AnnaBridge 172:65be27845400 723 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
AnnaBridge 172:65be27845400 724 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
AnnaBridge 172:65be27845400 725 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
AnnaBridge 172:65be27845400 726 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
AnnaBridge 172:65be27845400 727 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
AnnaBridge 172:65be27845400 728 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
AnnaBridge 172:65be27845400 729 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\
AnnaBridge 172:65be27845400 730 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\
AnnaBridge 172:65be27845400 731 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\
AnnaBridge 172:65be27845400 732 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\
AnnaBridge 172:65be27845400 733 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TE0 :\
AnnaBridge 172:65be27845400 734 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TE1 :\
AnnaBridge 172:65be27845400 735 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TE2 :\
AnnaBridge 172:65be27845400 736 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TE3 :\
AnnaBridge 172:65be27845400 737 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TE4 :\
AnnaBridge 172:65be27845400 738 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TE5 :\
AnnaBridge 172:65be27845400 739 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TE6 :\
AnnaBridge 172:65be27845400 740 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TE7 :\
AnnaBridge 172:65be27845400 741 (uint32_t)0x00000000)
AnnaBridge 172:65be27845400 742
AnnaBridge 172:65be27845400 743 /**
AnnaBridge 172:65be27845400 744 * @brief Return the current DMA Stream FIFO error flag.
AnnaBridge 172:65be27845400 745 * @param __HANDLE__: DMA handle
AnnaBridge 172:65be27845400 746 * @retval The specified FIFO error flag index.
AnnaBridge 172:65be27845400 747 */
AnnaBridge 172:65be27845400 748 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
AnnaBridge 172:65be27845400 749 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
AnnaBridge 172:65be27845400 750 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
AnnaBridge 172:65be27845400 751 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
AnnaBridge 172:65be27845400 752 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
AnnaBridge 172:65be27845400 753 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
AnnaBridge 172:65be27845400 754 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
AnnaBridge 172:65be27845400 755 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
AnnaBridge 172:65be27845400 756 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
AnnaBridge 172:65be27845400 757 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
AnnaBridge 172:65be27845400 758 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
AnnaBridge 172:65be27845400 759 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
AnnaBridge 172:65be27845400 760 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
AnnaBridge 172:65be27845400 761 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_FEIF3_7 :\
AnnaBridge 172:65be27845400 762 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_FEIF3_7 :\
AnnaBridge 172:65be27845400 763 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_FEIF3_7 :\
AnnaBridge 172:65be27845400 764 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_FEIF3_7 :\
AnnaBridge 172:65be27845400 765 (uint32_t)0x00000000)
AnnaBridge 172:65be27845400 766
AnnaBridge 172:65be27845400 767 /**
AnnaBridge 172:65be27845400 768 * @brief Return the current DMA Stream direct mode error flag.
AnnaBridge 172:65be27845400 769 * @param __HANDLE__: DMA handle
AnnaBridge 172:65be27845400 770 * @retval The specified direct mode error flag index.
AnnaBridge 172:65be27845400 771 */
AnnaBridge 172:65be27845400 772 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
AnnaBridge 172:65be27845400 773 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
AnnaBridge 172:65be27845400 774 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
AnnaBridge 172:65be27845400 775 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
AnnaBridge 172:65be27845400 776 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
AnnaBridge 172:65be27845400 777 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
AnnaBridge 172:65be27845400 778 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
AnnaBridge 172:65be27845400 779 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
AnnaBridge 172:65be27845400 780 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
AnnaBridge 172:65be27845400 781 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
AnnaBridge 172:65be27845400 782 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
AnnaBridge 172:65be27845400 783 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
AnnaBridge 172:65be27845400 784 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
AnnaBridge 172:65be27845400 785 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_DMEIF3_7 :\
AnnaBridge 172:65be27845400 786 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_DMEIF3_7 :\
AnnaBridge 172:65be27845400 787 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_DMEIF3_7 :\
AnnaBridge 172:65be27845400 788 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_DMEIF3_7 :\
AnnaBridge 172:65be27845400 789 (uint32_t)0x00000000)
AnnaBridge 172:65be27845400 790
AnnaBridge 172:65be27845400 791 /**
AnnaBridge 172:65be27845400 792 * @brief Returns the current BDMA Channel Global interrupt flag.
AnnaBridge 172:65be27845400 793 * @param __HANDLE__: DMA handle
AnnaBridge 172:65be27845400 794 * @retval The specified transfer error flag index.
AnnaBridge 172:65be27845400 795 */
AnnaBridge 172:65be27845400 796 #define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\
AnnaBridge 172:65be27845400 797 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_ISR_GIF0 :\
AnnaBridge 172:65be27845400 798 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_ISR_GIF1 :\
AnnaBridge 172:65be27845400 799 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_ISR_GIF2 :\
AnnaBridge 172:65be27845400 800 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_ISR_GIF3 :\
AnnaBridge 172:65be27845400 801 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_ISR_GIF4 :\
AnnaBridge 172:65be27845400 802 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_ISR_GIF5 :\
AnnaBridge 172:65be27845400 803 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_ISR_GIF6 :\
AnnaBridge 172:65be27845400 804 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_ISR_GIF7 :\
AnnaBridge 172:65be27845400 805 (uint32_t)0x00000000)
AnnaBridge 172:65be27845400 806
AnnaBridge 172:65be27845400 807 /**
AnnaBridge 172:65be27845400 808 * @brief Get the DMA Stream pending flags.
AnnaBridge 172:65be27845400 809 * @param __HANDLE__: DMA handle
AnnaBridge 172:65be27845400 810 * @param __FLAG__: Get the specified flag.
AnnaBridge 172:65be27845400 811 * This parameter can be any combination of the following values:
AnnaBridge 172:65be27845400 812 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
AnnaBridge 172:65be27845400 813 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
AnnaBridge 172:65be27845400 814 * @arg DMA_FLAG_TEIFx: Transfer error flag.
AnnaBridge 172:65be27845400 815 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
AnnaBridge 172:65be27845400 816 * @arg DMA_FLAG_FEIFx: FIFO error flag.
AnnaBridge 172:65be27845400 817 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
AnnaBridge 172:65be27845400 818 * @retval The state of FLAG (SET or RESET).
AnnaBridge 172:65be27845400 819 */
AnnaBridge 172:65be27845400 820 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
AnnaBridge 172:65be27845400 821 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->ISR & (__FLAG__)) :\
AnnaBridge 172:65be27845400 822 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
AnnaBridge 172:65be27845400 823 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
AnnaBridge 172:65be27845400 824 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
AnnaBridge 172:65be27845400 825
AnnaBridge 172:65be27845400 826 /**
AnnaBridge 172:65be27845400 827 * @brief Clear the DMA Stream pending flags.
AnnaBridge 172:65be27845400 828 * @param __HANDLE__: DMA handle
AnnaBridge 172:65be27845400 829 * @param __FLAG__: specifies the flag to clear.
AnnaBridge 172:65be27845400 830 * This parameter can be any combination of the following values:
AnnaBridge 172:65be27845400 831 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
AnnaBridge 172:65be27845400 832 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
AnnaBridge 172:65be27845400 833 * @arg DMA_FLAG_TEIFx: Transfer error flag.
AnnaBridge 172:65be27845400 834 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
AnnaBridge 172:65be27845400 835 * @arg DMA_FLAG_FEIFx: FIFO error flag.
AnnaBridge 172:65be27845400 836 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
AnnaBridge 172:65be27845400 837 * @retval None
AnnaBridge 172:65be27845400 838 */
AnnaBridge 172:65be27845400 839 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
AnnaBridge 172:65be27845400 840 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->IFCR = (__FLAG__)) :\
AnnaBridge 172:65be27845400 841 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
AnnaBridge 172:65be27845400 842 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
AnnaBridge 172:65be27845400 843 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
AnnaBridge 172:65be27845400 844
AnnaBridge 172:65be27845400 845 #define DMA_TO_BDMA_IT(__DMA_IT__) \
AnnaBridge 172:65be27845400 846 ((((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\
AnnaBridge 172:65be27845400 847 (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT)) == (DMA_IT_TC | DMA_IT_HT)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE) :\
AnnaBridge 172:65be27845400 848 (((__DMA_IT__) & (DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\
AnnaBridge 172:65be27845400 849 (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_TE)) ? (BDMA_CCR_TCIE |BDMA_CCR_TEIE) :\
AnnaBridge 172:65be27845400 850 ((__DMA_IT__) == DMA_IT_TC) ? BDMA_CCR_TCIE :\
AnnaBridge 172:65be27845400 851 ((__DMA_IT__) == DMA_IT_HT) ? BDMA_CCR_HTIE :\
AnnaBridge 172:65be27845400 852 ((__DMA_IT__) == DMA_IT_TE) ? BDMA_CCR_TEIE :\
AnnaBridge 172:65be27845400 853 (uint32_t)0x00000000)
AnnaBridge 172:65be27845400 854
AnnaBridge 172:65be27845400 855
AnnaBridge 172:65be27845400 856 #define __HAL_BDMA_CHANNEL_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
AnnaBridge 172:65be27845400 857 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= (DMA_TO_BDMA_IT(__INTERRUPT__)))
AnnaBridge 172:65be27845400 858
AnnaBridge 172:65be27845400 859 #define __HAL_DMA_STREAM_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
AnnaBridge 172:65be27845400 860 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= (__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR |= (__INTERRUPT__)))
AnnaBridge 172:65be27845400 861
AnnaBridge 172:65be27845400 862 /**
AnnaBridge 172:65be27845400 863 * @brief Enable the specified DMA Stream interrupts.
AnnaBridge 172:65be27845400 864 * @param __HANDLE__: DMA handle
AnnaBridge 172:65be27845400 865 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
AnnaBridge 172:65be27845400 866 * This parameter can be one of the following values:
AnnaBridge 172:65be27845400 867 * @arg DMA_IT_TC: Transfer complete interrupt mask.
AnnaBridge 172:65be27845400 868 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
AnnaBridge 172:65be27845400 869 * @arg DMA_IT_TE: Transfer error interrupt mask.
AnnaBridge 172:65be27845400 870 * @arg DMA_IT_FE: FIFO error interrupt mask.
AnnaBridge 172:65be27845400 871 * @arg DMA_IT_DME: Direct mode error interrupt.
AnnaBridge 172:65be27845400 872 * @retval None
AnnaBridge 172:65be27845400 873 */
AnnaBridge 172:65be27845400 874 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\
AnnaBridge 172:65be27845400 875 (__HAL_DMA_STREAM_ENABLE_IT((__HANDLE__), (__INTERRUPT__))) :\
AnnaBridge 172:65be27845400 876 (__HAL_BDMA_CHANNEL_ENABLE_IT((__HANDLE__), (__INTERRUPT__))))
AnnaBridge 172:65be27845400 877
AnnaBridge 172:65be27845400 878
AnnaBridge 172:65be27845400 879 #define __HAL_BDMA_CHANNEL_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~(DMA_TO_BDMA_IT(__INTERRUPT__)))
AnnaBridge 172:65be27845400 880
AnnaBridge 172:65be27845400 881 #define __HAL_DMA_STREAM_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
AnnaBridge 172:65be27845400 882 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~(__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR &= ~(__INTERRUPT__)))
AnnaBridge 172:65be27845400 883
AnnaBridge 172:65be27845400 884 /**
AnnaBridge 172:65be27845400 885 * @brief Disable the specified DMA Stream interrupts.
AnnaBridge 172:65be27845400 886 * @param __HANDLE__: DMA handle
AnnaBridge 172:65be27845400 887 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
AnnaBridge 172:65be27845400 888 * This parameter can be one of the following values:
AnnaBridge 172:65be27845400 889 * @arg DMA_IT_TC: Transfer complete interrupt mask.
AnnaBridge 172:65be27845400 890 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
AnnaBridge 172:65be27845400 891 * @arg DMA_IT_TE: Transfer error interrupt mask.
AnnaBridge 172:65be27845400 892 * @arg DMA_IT_FE: FIFO error interrupt mask.
AnnaBridge 172:65be27845400 893 * @arg DMA_IT_DME: Direct mode error interrupt.
AnnaBridge 172:65be27845400 894 * @retval None
AnnaBridge 172:65be27845400 895 */
AnnaBridge 172:65be27845400 896 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\
AnnaBridge 172:65be27845400 897 (__HAL_DMA_STREAM_DISABLE_IT((__HANDLE__), (__INTERRUPT__))) :\
AnnaBridge 172:65be27845400 898 (__HAL_BDMA_CHANNEL_DISABLE_IT((__HANDLE__), (__INTERRUPT__))))
AnnaBridge 172:65be27845400 899
AnnaBridge 172:65be27845400 900
AnnaBridge 172:65be27845400 901 #define __HAL_BDMA_CHANNEL_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR & (DMA_TO_BDMA_IT(__INTERRUPT__))))
AnnaBridge 172:65be27845400 902
AnnaBridge 172:65be27845400 903 #define __HAL_DMA_STREAM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
AnnaBridge 172:65be27845400 904 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR & (__INTERRUPT__)) : \
AnnaBridge 172:65be27845400 905 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (__INTERRUPT__)))
AnnaBridge 172:65be27845400 906
AnnaBridge 172:65be27845400 907 /**
AnnaBridge 172:65be27845400 908 * @brief Check whether the specified DMA Stream interrupt is enabled or not.
AnnaBridge 172:65be27845400 909 * @param __HANDLE__: DMA handle
AnnaBridge 172:65be27845400 910 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
AnnaBridge 172:65be27845400 911 * This parameter can be one of the following values:
AnnaBridge 172:65be27845400 912 * @arg DMA_IT_TC: Transfer complete interrupt mask.
AnnaBridge 172:65be27845400 913 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
AnnaBridge 172:65be27845400 914 * @arg DMA_IT_TE: Transfer error interrupt mask.
AnnaBridge 172:65be27845400 915 * @arg DMA_IT_FE: FIFO error interrupt mask.
AnnaBridge 172:65be27845400 916 * @arg DMA_IT_DME: Direct mode error interrupt.
AnnaBridge 172:65be27845400 917 * @retval The state of DMA_IT.
AnnaBridge 172:65be27845400 918 */
AnnaBridge 172:65be27845400 919 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \
AnnaBridge 172:65be27845400 920 (__HAL_DMA_STREAM_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))) :\
AnnaBridge 172:65be27845400 921 (__HAL_BDMA_CHANNEL_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))))
AnnaBridge 172:65be27845400 922
AnnaBridge 172:65be27845400 923 /**
AnnaBridge 172:65be27845400 924 * @brief Writes the number of data units to be transferred on the DMA Stream.
AnnaBridge 172:65be27845400 925 * @param __HANDLE__: DMA handle
AnnaBridge 172:65be27845400 926 * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535)
AnnaBridge 172:65be27845400 927 * Number of data items depends only on the Peripheral data format.
AnnaBridge 172:65be27845400 928 *
AnnaBridge 172:65be27845400 929 * @note If Peripheral data format is Bytes: number of data units is equal
AnnaBridge 172:65be27845400 930 * to total number of bytes to be transferred.
AnnaBridge 172:65be27845400 931 *
AnnaBridge 172:65be27845400 932 * @note If Peripheral data format is Half-Word: number of data units is
AnnaBridge 172:65be27845400 933 * equal to total number of bytes to be transferred / 2.
AnnaBridge 172:65be27845400 934 *
AnnaBridge 172:65be27845400 935 * @note If Peripheral data format is Word: number of data units is equal
AnnaBridge 172:65be27845400 936 * to total number of bytes to be transferred / 4.
AnnaBridge 172:65be27845400 937 *
AnnaBridge 172:65be27845400 938 * @retval The number of remaining data units in the current DMAy Streamx transfer.
AnnaBridge 172:65be27845400 939 */
AnnaBridge 172:65be27845400 940 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \
AnnaBridge 172:65be27845400 941 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR = (uint16_t)(__COUNTER__)) :\
AnnaBridge 172:65be27845400 942 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR = (uint16_t)(__COUNTER__)))
AnnaBridge 172:65be27845400 943
AnnaBridge 172:65be27845400 944 /**
AnnaBridge 172:65be27845400 945 * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
AnnaBridge 172:65be27845400 946 * @param __HANDLE__: DMA handle
AnnaBridge 172:65be27845400 947 *
AnnaBridge 172:65be27845400 948 * @retval The number of remaining data units in the current DMA Stream transfer.
AnnaBridge 172:65be27845400 949 */
AnnaBridge 172:65be27845400 950 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \
AnnaBridge 172:65be27845400 951 (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR) :\
AnnaBridge 172:65be27845400 952 (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR))
AnnaBridge 172:65be27845400 953
AnnaBridge 172:65be27845400 954 /**
AnnaBridge 172:65be27845400 955 * @}
AnnaBridge 172:65be27845400 956 */
AnnaBridge 172:65be27845400 957
AnnaBridge 172:65be27845400 958 /* Include DMA HAL Extension module */
AnnaBridge 172:65be27845400 959 #include "stm32h7xx_hal_dma_ex.h"
AnnaBridge 172:65be27845400 960
AnnaBridge 172:65be27845400 961 /* Exported functions --------------------------------------------------------*/
AnnaBridge 172:65be27845400 962
AnnaBridge 172:65be27845400 963 /** @defgroup DMA_Exported_Functions DMA Exported Functions
AnnaBridge 172:65be27845400 964 * @brief DMA Exported functions
AnnaBridge 172:65be27845400 965 * @{
AnnaBridge 172:65be27845400 966 */
AnnaBridge 172:65be27845400 967
AnnaBridge 172:65be27845400 968 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
AnnaBridge 172:65be27845400 969 * @brief Initialization and de-initialization functions
AnnaBridge 172:65be27845400 970 * @{
AnnaBridge 172:65be27845400 971 */
AnnaBridge 172:65be27845400 972 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
AnnaBridge 172:65be27845400 973 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
AnnaBridge 172:65be27845400 974 /**
AnnaBridge 172:65be27845400 975 * @}
AnnaBridge 172:65be27845400 976 */
AnnaBridge 172:65be27845400 977
AnnaBridge 172:65be27845400 978 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
AnnaBridge 172:65be27845400 979 * @brief I/O operation functions
AnnaBridge 172:65be27845400 980 * @{
AnnaBridge 172:65be27845400 981 */
AnnaBridge 172:65be27845400 982 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
AnnaBridge 172:65be27845400 983 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
AnnaBridge 172:65be27845400 984 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
AnnaBridge 172:65be27845400 985 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
AnnaBridge 172:65be27845400 986 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
AnnaBridge 172:65be27845400 987 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
AnnaBridge 172:65be27845400 988 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
AnnaBridge 172:65be27845400 989 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
AnnaBridge 172:65be27845400 990
AnnaBridge 172:65be27845400 991 /**
AnnaBridge 172:65be27845400 992 * @}
AnnaBridge 172:65be27845400 993 */
AnnaBridge 172:65be27845400 994
AnnaBridge 172:65be27845400 995 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
AnnaBridge 172:65be27845400 996 * @brief Peripheral State functions
AnnaBridge 172:65be27845400 997 * @{
AnnaBridge 172:65be27845400 998 */
AnnaBridge 172:65be27845400 999 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
AnnaBridge 172:65be27845400 1000 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
AnnaBridge 172:65be27845400 1001 /**
AnnaBridge 172:65be27845400 1002 * @}
AnnaBridge 172:65be27845400 1003 */
AnnaBridge 172:65be27845400 1004 /**
AnnaBridge 172:65be27845400 1005 * @}
AnnaBridge 172:65be27845400 1006 */
AnnaBridge 172:65be27845400 1007 /* Private Constants -------------------------------------------------------------*/
AnnaBridge 172:65be27845400 1008 /** @defgroup DMA_Private_Constants DMA Private Constants
AnnaBridge 172:65be27845400 1009 * @brief DMA private defines and constants
AnnaBridge 172:65be27845400 1010 * @{
AnnaBridge 172:65be27845400 1011 */
AnnaBridge 172:65be27845400 1012 /**
AnnaBridge 172:65be27845400 1013 * @}
AnnaBridge 172:65be27845400 1014 */
AnnaBridge 172:65be27845400 1015
AnnaBridge 172:65be27845400 1016 /* Private macros ------------------------------------------------------------*/
AnnaBridge 172:65be27845400 1017 /** @defgroup DMA_Private_Macros DMA Private Macros
AnnaBridge 172:65be27845400 1018 * @brief DMA private macros
AnnaBridge 172:65be27845400 1019 * @{
AnnaBridge 172:65be27845400 1020 */
AnnaBridge 172:65be27845400 1021
AnnaBridge 172:65be27845400 1022 #define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_ADC3))
AnnaBridge 172:65be27845400 1023
AnnaBridge 172:65be27845400 1024 #define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_ADC3))
AnnaBridge 172:65be27845400 1025
AnnaBridge 172:65be27845400 1026 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
AnnaBridge 172:65be27845400 1027 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
AnnaBridge 172:65be27845400 1028 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
AnnaBridge 172:65be27845400 1029
AnnaBridge 172:65be27845400 1030 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
AnnaBridge 172:65be27845400 1031
AnnaBridge 172:65be27845400 1032 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
AnnaBridge 172:65be27845400 1033 ((STATE) == DMA_PINC_DISABLE))
AnnaBridge 172:65be27845400 1034
AnnaBridge 172:65be27845400 1035 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
AnnaBridge 172:65be27845400 1036 ((STATE) == DMA_MINC_DISABLE))
AnnaBridge 172:65be27845400 1037
AnnaBridge 172:65be27845400 1038 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
AnnaBridge 172:65be27845400 1039 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
AnnaBridge 172:65be27845400 1040 ((SIZE) == DMA_PDATAALIGN_WORD))
AnnaBridge 172:65be27845400 1041
AnnaBridge 172:65be27845400 1042 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
AnnaBridge 172:65be27845400 1043 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
AnnaBridge 172:65be27845400 1044 ((SIZE) == DMA_MDATAALIGN_WORD ))
AnnaBridge 172:65be27845400 1045
AnnaBridge 172:65be27845400 1046 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
AnnaBridge 172:65be27845400 1047 ((MODE) == DMA_CIRCULAR) || \
AnnaBridge 172:65be27845400 1048 ((MODE) == DMA_PFCTRL) || \
AnnaBridge 172:65be27845400 1049 ((MODE) == DMA_DOUBLE_BUFFER_M0) || \
AnnaBridge 172:65be27845400 1050 ((MODE) == DMA_DOUBLE_BUFFER_M1))
AnnaBridge 172:65be27845400 1051
AnnaBridge 172:65be27845400 1052 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
AnnaBridge 172:65be27845400 1053 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
AnnaBridge 172:65be27845400 1054 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
AnnaBridge 172:65be27845400 1055 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
AnnaBridge 172:65be27845400 1056
AnnaBridge 172:65be27845400 1057 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
AnnaBridge 172:65be27845400 1058 ((STATE) == DMA_FIFOMODE_ENABLE))
AnnaBridge 172:65be27845400 1059
AnnaBridge 172:65be27845400 1060 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
AnnaBridge 172:65be27845400 1061 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
AnnaBridge 172:65be27845400 1062 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
AnnaBridge 172:65be27845400 1063 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
AnnaBridge 172:65be27845400 1064
AnnaBridge 172:65be27845400 1065 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
AnnaBridge 172:65be27845400 1066 ((BURST) == DMA_MBURST_INC4) || \
AnnaBridge 172:65be27845400 1067 ((BURST) == DMA_MBURST_INC8) || \
AnnaBridge 172:65be27845400 1068 ((BURST) == DMA_MBURST_INC16))
AnnaBridge 172:65be27845400 1069
AnnaBridge 172:65be27845400 1070 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
AnnaBridge 172:65be27845400 1071 ((BURST) == DMA_PBURST_INC4) || \
AnnaBridge 172:65be27845400 1072 ((BURST) == DMA_PBURST_INC8) || \
AnnaBridge 172:65be27845400 1073 ((BURST) == DMA_PBURST_INC16))
AnnaBridge 172:65be27845400 1074 /**
AnnaBridge 172:65be27845400 1075 * @}
AnnaBridge 172:65be27845400 1076 */
AnnaBridge 172:65be27845400 1077
AnnaBridge 172:65be27845400 1078 /* Private functions ---------------------------------------------------------*/
AnnaBridge 172:65be27845400 1079 /** @defgroup DMA_Private_Functions DMA Private Functions
AnnaBridge 172:65be27845400 1080 * @brief DMA private functions
AnnaBridge 172:65be27845400 1081 * @{
AnnaBridge 172:65be27845400 1082 */
AnnaBridge 172:65be27845400 1083 /**
AnnaBridge 172:65be27845400 1084 * @}
AnnaBridge 172:65be27845400 1085 */
AnnaBridge 172:65be27845400 1086
AnnaBridge 172:65be27845400 1087 /**
AnnaBridge 172:65be27845400 1088 * @}
AnnaBridge 172:65be27845400 1089 */
AnnaBridge 172:65be27845400 1090
AnnaBridge 172:65be27845400 1091 /**
AnnaBridge 172:65be27845400 1092 * @}
AnnaBridge 172:65be27845400 1093 */
AnnaBridge 172:65be27845400 1094
AnnaBridge 172:65be27845400 1095 #ifdef __cplusplus
AnnaBridge 172:65be27845400 1096 }
AnnaBridge 172:65be27845400 1097 #endif
AnnaBridge 172:65be27845400 1098
AnnaBridge 172:65be27845400 1099 #endif /* STM32H7xx_HAL_DMA_H */
AnnaBridge 172:65be27845400 1100
AnnaBridge 172:65be27845400 1101 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/