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TARGET_NUCLEO_H743ZI/TOOLCHAIN_ARM_MICRO/stm32_hal_legacy.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	172:65be27845400	1	/**
AnnaBridge	172:65be27845400	2	******************************************************************************
AnnaBridge	172:65be27845400	3	* @file stm32_hal_legacy.h
AnnaBridge	172:65be27845400	4	* @author MCD Application Team
AnnaBridge	172:65be27845400	5	* @brief This file contains aliases definition for the STM32Cube HAL constants
AnnaBridge	172:65be27845400	6	* macros and functions maintained for legacy purpose.
AnnaBridge	172:65be27845400	7	******************************************************************************
AnnaBridge	172:65be27845400	8	* @attention
AnnaBridge	172:65be27845400	9	*
AnnaBridge	172:65be27845400	10	* <h2><center>© Copyright (c) 2018 STMicroelectronics.
AnnaBridge	172:65be27845400	11	* All rights reserved.</center></h2>
AnnaBridge	172:65be27845400	12	*
AnnaBridge	172:65be27845400	13	* This software component is licensed by ST under BSD 3-Clause license,
AnnaBridge	172:65be27845400	14	* the "License"; You may not use this file except in compliance with the
AnnaBridge	172:65be27845400	15	* License. You may obtain a copy of the License at:
AnnaBridge	172:65be27845400	16	* opensource.org/licenses/BSD-3-Clause
AnnaBridge	172:65be27845400	17	*
AnnaBridge	172:65be27845400	18	******************************************************************************
AnnaBridge	172:65be27845400	19	*/
AnnaBridge	172:65be27845400	20
AnnaBridge	172:65be27845400	21	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	172:65be27845400	22	#ifndef STM32_HAL_LEGACY
AnnaBridge	172:65be27845400	23	#define STM32_HAL_LEGACY
AnnaBridge	172:65be27845400	24
AnnaBridge	172:65be27845400	25	#ifdef __cplusplus
AnnaBridge	172:65be27845400	26	extern "C" {
AnnaBridge	172:65be27845400	27	#endif
AnnaBridge	172:65be27845400	28
AnnaBridge	172:65be27845400	29	/* Includes ------------------------------------------------------------------*/
AnnaBridge	172:65be27845400	30	/* Exported types ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	31	/* Exported constants --------------------------------------------------------*/
AnnaBridge	172:65be27845400	32
AnnaBridge	172:65be27845400	33	/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
AnnaBridge	172:65be27845400	34	* @{
AnnaBridge	172:65be27845400	35	*/
AnnaBridge	172:65be27845400	36	#define AES_FLAG_RDERR CRYP_FLAG_RDERR
AnnaBridge	172:65be27845400	37	#define AES_FLAG_WRERR CRYP_FLAG_WRERR
AnnaBridge	172:65be27845400	38	#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
AnnaBridge	172:65be27845400	39	#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
AnnaBridge	172:65be27845400	40	#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
AnnaBridge	172:65be27845400	41
AnnaBridge	172:65be27845400	42	/**
AnnaBridge	172:65be27845400	43	* @}
AnnaBridge	172:65be27845400	44	*/
AnnaBridge	172:65be27845400	45
AnnaBridge	172:65be27845400	46	/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
AnnaBridge	172:65be27845400	47	* @{
AnnaBridge	172:65be27845400	48	*/
AnnaBridge	172:65be27845400	49	#define ADC_RESOLUTION12b ADC_RESOLUTION_12B
AnnaBridge	172:65be27845400	50	#define ADC_RESOLUTION10b ADC_RESOLUTION_10B
AnnaBridge	172:65be27845400	51	#define ADC_RESOLUTION8b ADC_RESOLUTION_8B
AnnaBridge	172:65be27845400	52	#define ADC_RESOLUTION6b ADC_RESOLUTION_6B
AnnaBridge	172:65be27845400	53	#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
AnnaBridge	172:65be27845400	54	#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
AnnaBridge	172:65be27845400	55	#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
AnnaBridge	172:65be27845400	56	#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
AnnaBridge	172:65be27845400	57	#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
AnnaBridge	172:65be27845400	58	#define REGULAR_GROUP ADC_REGULAR_GROUP
AnnaBridge	172:65be27845400	59	#define INJECTED_GROUP ADC_INJECTED_GROUP
AnnaBridge	172:65be27845400	60	#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
AnnaBridge	172:65be27845400	61	#define AWD_EVENT ADC_AWD_EVENT
AnnaBridge	172:65be27845400	62	#define AWD1_EVENT ADC_AWD1_EVENT
AnnaBridge	172:65be27845400	63	#define AWD2_EVENT ADC_AWD2_EVENT
AnnaBridge	172:65be27845400	64	#define AWD3_EVENT ADC_AWD3_EVENT
AnnaBridge	172:65be27845400	65	#define OVR_EVENT ADC_OVR_EVENT
AnnaBridge	172:65be27845400	66	#define JQOVF_EVENT ADC_JQOVF_EVENT
AnnaBridge	172:65be27845400	67	#define ALL_CHANNELS ADC_ALL_CHANNELS
AnnaBridge	172:65be27845400	68	#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
AnnaBridge	172:65be27845400	69	#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
AnnaBridge	172:65be27845400	70	#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
AnnaBridge	172:65be27845400	71	#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
AnnaBridge	172:65be27845400	72	#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
AnnaBridge	172:65be27845400	73	#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
AnnaBridge	172:65be27845400	74	#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
AnnaBridge	172:65be27845400	75	#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
AnnaBridge	172:65be27845400	76	#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
AnnaBridge	172:65be27845400	77	#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
AnnaBridge	172:65be27845400	78	#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
AnnaBridge	172:65be27845400	79	#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
AnnaBridge	172:65be27845400	80	#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
AnnaBridge	172:65be27845400	81	#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
AnnaBridge	172:65be27845400	82	#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
AnnaBridge	172:65be27845400	83	#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
AnnaBridge	172:65be27845400	84	#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
AnnaBridge	172:65be27845400	85	#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
AnnaBridge	172:65be27845400	86	#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
AnnaBridge	172:65be27845400	87	#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
AnnaBridge	172:65be27845400	88	#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
AnnaBridge	172:65be27845400	89
AnnaBridge	172:65be27845400	90	#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
AnnaBridge	172:65be27845400	91	#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
AnnaBridge	172:65be27845400	92	#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
AnnaBridge	172:65be27845400	93	#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
AnnaBridge	172:65be27845400	94	#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
AnnaBridge	172:65be27845400	95	#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
AnnaBridge	172:65be27845400	96	#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
AnnaBridge	172:65be27845400	97
AnnaBridge	172:65be27845400	98	#if defined(STM32H7)
AnnaBridge	172:65be27845400	99	#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT
AnnaBridge	172:65be27845400	100	#endif /* STM32H7 */
AnnaBridge	172:65be27845400	101	/**
AnnaBridge	172:65be27845400	102	* @}
AnnaBridge	172:65be27845400	103	*/
AnnaBridge	172:65be27845400	104
AnnaBridge	172:65be27845400	105	/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
AnnaBridge	172:65be27845400	106	* @{
AnnaBridge	172:65be27845400	107	*/
AnnaBridge	172:65be27845400	108
AnnaBridge	172:65be27845400	109	#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
AnnaBridge	172:65be27845400	110
AnnaBridge	172:65be27845400	111	/**
AnnaBridge	172:65be27845400	112	* @}
AnnaBridge	172:65be27845400	113	*/
AnnaBridge	172:65be27845400	114
AnnaBridge	172:65be27845400	115	/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
AnnaBridge	172:65be27845400	116	* @{
AnnaBridge	172:65be27845400	117	*/
AnnaBridge	172:65be27845400	118	#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
AnnaBridge	172:65be27845400	119	#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
AnnaBridge	172:65be27845400	120	#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
AnnaBridge	172:65be27845400	121	#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
AnnaBridge	172:65be27845400	122	#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
AnnaBridge	172:65be27845400	123	#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
AnnaBridge	172:65be27845400	124	#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
AnnaBridge	172:65be27845400	125	#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
AnnaBridge	172:65be27845400	126	#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
AnnaBridge	172:65be27845400	127	#if defined(STM32L0)
AnnaBridge	172:65be27845400	128	#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 /
AnnaBridge	172:65be27845400	129	#endif
AnnaBridge	172:65be27845400	130	#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
AnnaBridge	172:65be27845400	131	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
AnnaBridge	172:65be27845400	132	#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
AnnaBridge	172:65be27845400	133	#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
AnnaBridge	172:65be27845400	134	#endif /* STM32F373xC \|\| STM32F378xx */
AnnaBridge	172:65be27845400	135
AnnaBridge	172:65be27845400	136	#if defined(STM32L0) \|\| defined(STM32L4)
AnnaBridge	172:65be27845400	137	#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
AnnaBridge	172:65be27845400	138
AnnaBridge	172:65be27845400	139	#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
AnnaBridge	172:65be27845400	140	#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
AnnaBridge	172:65be27845400	141	#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
AnnaBridge	172:65be27845400	142	#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
AnnaBridge	172:65be27845400	143	#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
AnnaBridge	172:65be27845400	144	#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
AnnaBridge	172:65be27845400	145
AnnaBridge	172:65be27845400	146	#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
AnnaBridge	172:65be27845400	147	#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
AnnaBridge	172:65be27845400	148	#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
AnnaBridge	172:65be27845400	149	#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
AnnaBridge	172:65be27845400	150	#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
AnnaBridge	172:65be27845400	151	#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
AnnaBridge	172:65be27845400	152	#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
AnnaBridge	172:65be27845400	153	#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
AnnaBridge	172:65be27845400	154	#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
AnnaBridge	172:65be27845400	155	#if defined(STM32L0)
AnnaBridge	172:65be27845400	156	/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
AnnaBridge	172:65be27845400	157	/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
AnnaBridge	172:65be27845400	158	/* to the second dedicated IO (only for COMP2). */
AnnaBridge	172:65be27845400	159	#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
AnnaBridge	172:65be27845400	160	#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
AnnaBridge	172:65be27845400	161	#else
AnnaBridge	172:65be27845400	162	#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
AnnaBridge	172:65be27845400	163	#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
AnnaBridge	172:65be27845400	164	#endif
AnnaBridge	172:65be27845400	165	#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
AnnaBridge	172:65be27845400	166	#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
AnnaBridge	172:65be27845400	167
AnnaBridge	172:65be27845400	168	#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
AnnaBridge	172:65be27845400	169	#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
AnnaBridge	172:65be27845400	170
AnnaBridge	172:65be27845400	171	/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
AnnaBridge	172:65be27845400	172	/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
AnnaBridge	172:65be27845400	173	#if defined(COMP_CSR_LOCK)
AnnaBridge	172:65be27845400	174	#define COMP_FLAG_LOCK COMP_CSR_LOCK
AnnaBridge	172:65be27845400	175	#elif defined(COMP_CSR_COMP1LOCK)
AnnaBridge	172:65be27845400	176	#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
AnnaBridge	172:65be27845400	177	#elif defined(COMP_CSR_COMPxLOCK)
AnnaBridge	172:65be27845400	178	#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
AnnaBridge	172:65be27845400	179	#endif
AnnaBridge	172:65be27845400	180
AnnaBridge	172:65be27845400	181	#if defined(STM32L4)
AnnaBridge	172:65be27845400	182	#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
AnnaBridge	172:65be27845400	183	#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
AnnaBridge	172:65be27845400	184	#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
AnnaBridge	172:65be27845400	185	#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
AnnaBridge	172:65be27845400	186	#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
AnnaBridge	172:65be27845400	187	#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
AnnaBridge	172:65be27845400	188	#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
AnnaBridge	172:65be27845400	189	#endif
AnnaBridge	172:65be27845400	190
AnnaBridge	172:65be27845400	191	#if defined(STM32L0)
AnnaBridge	172:65be27845400	192	#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
AnnaBridge	172:65be27845400	193	#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
AnnaBridge	172:65be27845400	194	#else
AnnaBridge	172:65be27845400	195	#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
AnnaBridge	172:65be27845400	196	#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
AnnaBridge	172:65be27845400	197	#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
AnnaBridge	172:65be27845400	198	#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
AnnaBridge	172:65be27845400	199	#endif
AnnaBridge	172:65be27845400	200
AnnaBridge	172:65be27845400	201	#endif
AnnaBridge	172:65be27845400	202	/**
AnnaBridge	172:65be27845400	203	* @}
AnnaBridge	172:65be27845400	204	*/
AnnaBridge	172:65be27845400	205
AnnaBridge	172:65be27845400	206	/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
AnnaBridge	172:65be27845400	207	* @{
AnnaBridge	172:65be27845400	208	*/
AnnaBridge	172:65be27845400	209	#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
AnnaBridge	172:65be27845400	210	/**
AnnaBridge	172:65be27845400	211	* @}
AnnaBridge	172:65be27845400	212	*/
AnnaBridge	172:65be27845400	213
AnnaBridge	172:65be27845400	214	/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
AnnaBridge	172:65be27845400	215	* @{
AnnaBridge	172:65be27845400	216	*/
AnnaBridge	172:65be27845400	217
AnnaBridge	172:65be27845400	218	#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
AnnaBridge	172:65be27845400	219	#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
AnnaBridge	172:65be27845400	220
AnnaBridge	172:65be27845400	221	/**
AnnaBridge	172:65be27845400	222	* @}
AnnaBridge	172:65be27845400	223	*/
AnnaBridge	172:65be27845400	224
AnnaBridge	172:65be27845400	225	/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
AnnaBridge	172:65be27845400	226	* @{
AnnaBridge	172:65be27845400	227	*/
AnnaBridge	172:65be27845400	228
AnnaBridge	172:65be27845400	229	#define DAC1_CHANNEL_1 DAC_CHANNEL_1
AnnaBridge	172:65be27845400	230	#define DAC1_CHANNEL_2 DAC_CHANNEL_2
AnnaBridge	172:65be27845400	231	#define DAC2_CHANNEL_1 DAC_CHANNEL_1
AnnaBridge	172:65be27845400	232	#define DAC_WAVE_NONE 0x00000000U
AnnaBridge	172:65be27845400	233	#define DAC_WAVE_NOISE DAC_CR_WAVE1_0
AnnaBridge	172:65be27845400	234	#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
AnnaBridge	172:65be27845400	235	#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
AnnaBridge	172:65be27845400	236	#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
AnnaBridge	172:65be27845400	237	#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
AnnaBridge	172:65be27845400	238
AnnaBridge	172:65be27845400	239	/**
AnnaBridge	172:65be27845400	240	* @}
AnnaBridge	172:65be27845400	241	*/
AnnaBridge	172:65be27845400	242
AnnaBridge	172:65be27845400	243	/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
AnnaBridge	172:65be27845400	244	* @{
AnnaBridge	172:65be27845400	245	*/
AnnaBridge	172:65be27845400	246	#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
AnnaBridge	172:65be27845400	247	#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
AnnaBridge	172:65be27845400	248	#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
AnnaBridge	172:65be27845400	249	#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
AnnaBridge	172:65be27845400	250	#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
AnnaBridge	172:65be27845400	251	#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
AnnaBridge	172:65be27845400	252	#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
AnnaBridge	172:65be27845400	253	#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
AnnaBridge	172:65be27845400	254	#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
AnnaBridge	172:65be27845400	255	#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
AnnaBridge	172:65be27845400	256	#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
AnnaBridge	172:65be27845400	257	#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
AnnaBridge	172:65be27845400	258	#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
AnnaBridge	172:65be27845400	259	#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
AnnaBridge	172:65be27845400	260
AnnaBridge	172:65be27845400	261	#define IS_HAL_REMAPDMA IS_DMA_REMAP
AnnaBridge	172:65be27845400	262	#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
AnnaBridge	172:65be27845400	263	#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
AnnaBridge	172:65be27845400	264
AnnaBridge	172:65be27845400	265	#if defined(STM32L4)
AnnaBridge	172:65be27845400	266
AnnaBridge	172:65be27845400	267	#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
AnnaBridge	172:65be27845400	268	#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1
AnnaBridge	172:65be27845400	269	#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2
AnnaBridge	172:65be27845400	270	#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3
AnnaBridge	172:65be27845400	271	#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4
AnnaBridge	172:65be27845400	272	#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5
AnnaBridge	172:65be27845400	273	#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6
AnnaBridge	172:65be27845400	274	#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7
AnnaBridge	172:65be27845400	275	#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8
AnnaBridge	172:65be27845400	276	#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9
AnnaBridge	172:65be27845400	277	#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10
AnnaBridge	172:65be27845400	278	#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11
AnnaBridge	172:65be27845400	279	#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12
AnnaBridge	172:65be27845400	280	#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13
AnnaBridge	172:65be27845400	281	#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14
AnnaBridge	172:65be27845400	282	#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15
AnnaBridge	172:65be27845400	283	#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
AnnaBridge	172:65be27845400	284	#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
AnnaBridge	172:65be27845400	285	#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
AnnaBridge	172:65be27845400	286	#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
AnnaBridge	172:65be27845400	287	#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
AnnaBridge	172:65be27845400	288	#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
AnnaBridge	172:65be27845400	289	#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE
AnnaBridge	172:65be27845400	290	#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT
AnnaBridge	172:65be27845400	291	#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
AnnaBridge	172:65be27845400	292	#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT
AnnaBridge	172:65be27845400	293
AnnaBridge	172:65be27845400	294	#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
AnnaBridge	172:65be27845400	295	#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
AnnaBridge	172:65be27845400	296	#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
AnnaBridge	172:65be27845400	297	#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
AnnaBridge	172:65be27845400	298
AnnaBridge	172:65be27845400	299	#endif /* STM32L4 */
AnnaBridge	172:65be27845400	300
AnnaBridge	172:65be27845400	301	#if defined(STM32H7)
AnnaBridge	172:65be27845400	302
AnnaBridge	172:65be27845400	303	#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
AnnaBridge	172:65be27845400	304	#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
AnnaBridge	172:65be27845400	305
AnnaBridge	172:65be27845400	306	#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
AnnaBridge	172:65be27845400	307	#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
AnnaBridge	172:65be27845400	308
AnnaBridge	172:65be27845400	309	#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
AnnaBridge	172:65be27845400	310	#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
AnnaBridge	172:65be27845400	311	#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
AnnaBridge	172:65be27845400	312	#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
AnnaBridge	172:65be27845400	313	#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
AnnaBridge	172:65be27845400	314	#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
AnnaBridge	172:65be27845400	315	#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
AnnaBridge	172:65be27845400	316	#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
AnnaBridge	172:65be27845400	317
AnnaBridge	172:65be27845400	318	#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
AnnaBridge	172:65be27845400	319	#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
AnnaBridge	172:65be27845400	320	#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
AnnaBridge	172:65be27845400	321	#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
AnnaBridge	172:65be27845400	322	#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
AnnaBridge	172:65be27845400	323	#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
AnnaBridge	172:65be27845400	324	#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
AnnaBridge	172:65be27845400	325	#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
AnnaBridge	172:65be27845400	326	#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
AnnaBridge	172:65be27845400	327	#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
AnnaBridge	172:65be27845400	328	#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
AnnaBridge	172:65be27845400	329	#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
AnnaBridge	172:65be27845400	330	#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
AnnaBridge	172:65be27845400	331	#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
AnnaBridge	172:65be27845400	332	#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
AnnaBridge	172:65be27845400	333	#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
AnnaBridge	172:65be27845400	334	#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
AnnaBridge	172:65be27845400	335	#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
AnnaBridge	172:65be27845400	336	#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
AnnaBridge	172:65be27845400	337	#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
AnnaBridge	172:65be27845400	338	#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
AnnaBridge	172:65be27845400	339	#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
AnnaBridge	172:65be27845400	340	#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
AnnaBridge	172:65be27845400	341	#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
AnnaBridge	172:65be27845400	342	#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
AnnaBridge	172:65be27845400	343	#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
AnnaBridge	172:65be27845400	344	#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
AnnaBridge	172:65be27845400	345	#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
AnnaBridge	172:65be27845400	346	#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
AnnaBridge	172:65be27845400	347	#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
AnnaBridge	172:65be27845400	348
AnnaBridge	172:65be27845400	349	#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
AnnaBridge	172:65be27845400	350	#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
AnnaBridge	172:65be27845400	351	#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
AnnaBridge	172:65be27845400	352	#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
AnnaBridge	172:65be27845400	353
AnnaBridge	172:65be27845400	354	#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT
AnnaBridge	172:65be27845400	355	#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
AnnaBridge	172:65be27845400	356	#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
AnnaBridge	172:65be27845400	357
AnnaBridge	172:65be27845400	358	#endif /* STM32H7 */
AnnaBridge	172:65be27845400	359
AnnaBridge	172:65be27845400	360	/**
AnnaBridge	172:65be27845400	361	* @}
AnnaBridge	172:65be27845400	362	*/
AnnaBridge	172:65be27845400	363
AnnaBridge	172:65be27845400	364	/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
AnnaBridge	172:65be27845400	365	* @{
AnnaBridge	172:65be27845400	366	*/
AnnaBridge	172:65be27845400	367
AnnaBridge	172:65be27845400	368	#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
AnnaBridge	172:65be27845400	369	#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
AnnaBridge	172:65be27845400	370	#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
AnnaBridge	172:65be27845400	371	#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
AnnaBridge	172:65be27845400	372	#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
AnnaBridge	172:65be27845400	373	#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
AnnaBridge	172:65be27845400	374	#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
AnnaBridge	172:65be27845400	375	#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
AnnaBridge	172:65be27845400	376	#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
AnnaBridge	172:65be27845400	377	#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
AnnaBridge	172:65be27845400	378	#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
AnnaBridge	172:65be27845400	379	#define OBEX_PCROP OPTIONBYTE_PCROP
AnnaBridge	172:65be27845400	380	#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
AnnaBridge	172:65be27845400	381	#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
AnnaBridge	172:65be27845400	382	#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
AnnaBridge	172:65be27845400	383	#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
AnnaBridge	172:65be27845400	384	#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
AnnaBridge	172:65be27845400	385	#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
AnnaBridge	172:65be27845400	386	#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
AnnaBridge	172:65be27845400	387	#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
AnnaBridge	172:65be27845400	388	#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
AnnaBridge	172:65be27845400	389	#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
AnnaBridge	172:65be27845400	390	#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
AnnaBridge	172:65be27845400	391	#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
AnnaBridge	172:65be27845400	392	#define PAGESIZE FLASH_PAGE_SIZE
AnnaBridge	172:65be27845400	393	#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
AnnaBridge	172:65be27845400	394	#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
AnnaBridge	172:65be27845400	395	#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
AnnaBridge	172:65be27845400	396	#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
AnnaBridge	172:65be27845400	397	#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
AnnaBridge	172:65be27845400	398	#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
AnnaBridge	172:65be27845400	399	#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
AnnaBridge	172:65be27845400	400	#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
AnnaBridge	172:65be27845400	401	#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
AnnaBridge	172:65be27845400	402	#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
AnnaBridge	172:65be27845400	403	#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
AnnaBridge	172:65be27845400	404	#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
AnnaBridge	172:65be27845400	405	#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
AnnaBridge	172:65be27845400	406	#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
AnnaBridge	172:65be27845400	407	#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
AnnaBridge	172:65be27845400	408	#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
AnnaBridge	172:65be27845400	409	#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
AnnaBridge	172:65be27845400	410	#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
AnnaBridge	172:65be27845400	411	#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
AnnaBridge	172:65be27845400	412	#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
AnnaBridge	172:65be27845400	413	#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
AnnaBridge	172:65be27845400	414	#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
AnnaBridge	172:65be27845400	415	#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
AnnaBridge	172:65be27845400	416	#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
AnnaBridge	172:65be27845400	417	#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
AnnaBridge	172:65be27845400	418	#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
AnnaBridge	172:65be27845400	419	#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
AnnaBridge	172:65be27845400	420	#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
AnnaBridge	172:65be27845400	421	#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
AnnaBridge	172:65be27845400	422	#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
AnnaBridge	172:65be27845400	423	#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
AnnaBridge	172:65be27845400	424	#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
AnnaBridge	172:65be27845400	425	#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
AnnaBridge	172:65be27845400	426	#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
AnnaBridge	172:65be27845400	427	#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
AnnaBridge	172:65be27845400	428	#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
AnnaBridge	172:65be27845400	429	#define OB_WDG_SW OB_IWDG_SW
AnnaBridge	172:65be27845400	430	#define OB_WDG_HW OB_IWDG_HW
AnnaBridge	172:65be27845400	431	#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
AnnaBridge	172:65be27845400	432	#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
AnnaBridge	172:65be27845400	433	#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
AnnaBridge	172:65be27845400	434	#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
AnnaBridge	172:65be27845400	435	#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
AnnaBridge	172:65be27845400	436	#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
AnnaBridge	172:65be27845400	437	#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
AnnaBridge	172:65be27845400	438	#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
AnnaBridge	172:65be27845400	439	#if defined(STM32G0)
AnnaBridge	172:65be27845400	440	#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
AnnaBridge	172:65be27845400	441	#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
AnnaBridge	172:65be27845400	442	#else
AnnaBridge	172:65be27845400	443	#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE
AnnaBridge	172:65be27845400	444	#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE
AnnaBridge	172:65be27845400	445	#endif
AnnaBridge	172:65be27845400	446	#if defined(STM32H7)
AnnaBridge	172:65be27845400	447	#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
AnnaBridge	172:65be27845400	448	#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
AnnaBridge	172:65be27845400	449	#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1
AnnaBridge	172:65be27845400	450	#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
AnnaBridge	172:65be27845400	451	#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
AnnaBridge	172:65be27845400	452	#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
AnnaBridge	172:65be27845400	453	#endif
AnnaBridge	172:65be27845400	454
AnnaBridge	172:65be27845400	455	/**
AnnaBridge	172:65be27845400	456	* @}
AnnaBridge	172:65be27845400	457	*/
AnnaBridge	172:65be27845400	458
AnnaBridge	172:65be27845400	459	/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
AnnaBridge	172:65be27845400	460	* @{
AnnaBridge	172:65be27845400	461	*/
AnnaBridge	172:65be27845400	462
AnnaBridge	172:65be27845400	463	#if defined(STM32H7)
AnnaBridge	172:65be27845400	464	#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
AnnaBridge	172:65be27845400	465	#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
AnnaBridge	172:65be27845400	466	#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
AnnaBridge	172:65be27845400	467	#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
AnnaBridge	172:65be27845400	468	#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	469	#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	470	#endif /* STM32H7 */
AnnaBridge	172:65be27845400	471
AnnaBridge	172:65be27845400	472	/**
AnnaBridge	172:65be27845400	473	* @}
AnnaBridge	172:65be27845400	474	*/
AnnaBridge	172:65be27845400	475
AnnaBridge	172:65be27845400	476	/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
AnnaBridge	172:65be27845400	477	* @{
AnnaBridge	172:65be27845400	478	*/
AnnaBridge	172:65be27845400	479
AnnaBridge	172:65be27845400	480	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
AnnaBridge	172:65be27845400	481	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
AnnaBridge	172:65be27845400	482	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
AnnaBridge	172:65be27845400	483	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
AnnaBridge	172:65be27845400	484	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
AnnaBridge	172:65be27845400	485	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
AnnaBridge	172:65be27845400	486	#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
AnnaBridge	172:65be27845400	487	#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
AnnaBridge	172:65be27845400	488	#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
AnnaBridge	172:65be27845400	489	/**
AnnaBridge	172:65be27845400	490	* @}
AnnaBridge	172:65be27845400	491	*/
AnnaBridge	172:65be27845400	492
AnnaBridge	172:65be27845400	493
AnnaBridge	172:65be27845400	494	/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
AnnaBridge	172:65be27845400	495	* @{
AnnaBridge	172:65be27845400	496	*/
AnnaBridge	172:65be27845400	497	#if defined(STM32L4) \|\| defined(STM32F7) \|\| defined(STM32H7)
AnnaBridge	172:65be27845400	498	#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
AnnaBridge	172:65be27845400	499	#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
AnnaBridge	172:65be27845400	500	#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
AnnaBridge	172:65be27845400	501	#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
AnnaBridge	172:65be27845400	502	#elif defined(STM32F1) \|\| defined(STM32F2) \|\| defined(STM32F3) \|\| defined(STM32F4)
AnnaBridge	172:65be27845400	503	#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
AnnaBridge	172:65be27845400	504	#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
AnnaBridge	172:65be27845400	505	#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
AnnaBridge	172:65be27845400	506	#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
AnnaBridge	172:65be27845400	507	#endif
AnnaBridge	172:65be27845400	508	/**
AnnaBridge	172:65be27845400	509	* @}
AnnaBridge	172:65be27845400	510	*/
AnnaBridge	172:65be27845400	511
AnnaBridge	172:65be27845400	512	/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
AnnaBridge	172:65be27845400	513	* @{
AnnaBridge	172:65be27845400	514	*/
AnnaBridge	172:65be27845400	515
AnnaBridge	172:65be27845400	516	#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
AnnaBridge	172:65be27845400	517	#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
AnnaBridge	172:65be27845400	518	/**
AnnaBridge	172:65be27845400	519	* @}
AnnaBridge	172:65be27845400	520	*/
AnnaBridge	172:65be27845400	521
AnnaBridge	172:65be27845400	522	/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
AnnaBridge	172:65be27845400	523	* @{
AnnaBridge	172:65be27845400	524	*/
AnnaBridge	172:65be27845400	525	#define GET_GPIO_SOURCE GPIO_GET_INDEX
AnnaBridge	172:65be27845400	526	#define GET_GPIO_INDEX GPIO_GET_INDEX
AnnaBridge	172:65be27845400	527
AnnaBridge	172:65be27845400	528	#if defined(STM32F4)
AnnaBridge	172:65be27845400	529	#define GPIO_AF12_SDMMC GPIO_AF12_SDIO
AnnaBridge	172:65be27845400	530	#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
AnnaBridge	172:65be27845400	531	#endif
AnnaBridge	172:65be27845400	532
AnnaBridge	172:65be27845400	533	#if defined(STM32F7)
AnnaBridge	172:65be27845400	534	#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
AnnaBridge	172:65be27845400	535	#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
AnnaBridge	172:65be27845400	536	#endif
AnnaBridge	172:65be27845400	537
AnnaBridge	172:65be27845400	538	#if defined(STM32L4)
AnnaBridge	172:65be27845400	539	#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
AnnaBridge	172:65be27845400	540	#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
AnnaBridge	172:65be27845400	541	#endif
AnnaBridge	172:65be27845400	542
AnnaBridge	172:65be27845400	543	#if defined(STM32H7)
AnnaBridge	172:65be27845400	544	#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1
AnnaBridge	172:65be27845400	545	#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1
AnnaBridge	172:65be27845400	546	#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1
AnnaBridge	172:65be27845400	547	#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
AnnaBridge	172:65be27845400	548	#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
AnnaBridge	172:65be27845400	549	#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
AnnaBridge	172:65be27845400	550	#endif
AnnaBridge	172:65be27845400	551
AnnaBridge	172:65be27845400	552	#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
AnnaBridge	172:65be27845400	553	#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
AnnaBridge	172:65be27845400	554	#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
AnnaBridge	172:65be27845400	555
AnnaBridge	172:65be27845400	556	#if defined(STM32L0) \|\| defined(STM32L4) \|\| defined(STM32F4) \|\| defined(STM32F2) \|\| defined(STM32F7) \|\| defined(STM32H7)
AnnaBridge	172:65be27845400	557	#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
AnnaBridge	172:65be27845400	558	#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
AnnaBridge	172:65be27845400	559	#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
AnnaBridge	172:65be27845400	560	#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
AnnaBridge	172:65be27845400	561	#endif /* STM32L0 \|\| STM32L4 \|\| STM32F4 \|\| STM32F2 \|\| STM32F7 \|\| STM32H7*/
AnnaBridge	172:65be27845400	562
AnnaBridge	172:65be27845400	563	#if defined(STM32L1)
AnnaBridge	172:65be27845400	564	#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
AnnaBridge	172:65be27845400	565	#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
AnnaBridge	172:65be27845400	566	#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
AnnaBridge	172:65be27845400	567	#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
AnnaBridge	172:65be27845400	568	#endif /* STM32L1 */
AnnaBridge	172:65be27845400	569
AnnaBridge	172:65be27845400	570	#if defined(STM32F0) \|\| defined(STM32F3) \|\| defined(STM32F1)
AnnaBridge	172:65be27845400	571	#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
AnnaBridge	172:65be27845400	572	#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
AnnaBridge	172:65be27845400	573	#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
AnnaBridge	172:65be27845400	574	#endif /* STM32F0 \|\| STM32F3 \|\| STM32F1 */
AnnaBridge	172:65be27845400	575
AnnaBridge	172:65be27845400	576	#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
AnnaBridge	172:65be27845400	577	/**
AnnaBridge	172:65be27845400	578	* @}
AnnaBridge	172:65be27845400	579	*/
AnnaBridge	172:65be27845400	580
AnnaBridge	172:65be27845400	581	/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
AnnaBridge	172:65be27845400	582	* @{
AnnaBridge	172:65be27845400	583	*/
AnnaBridge	172:65be27845400	584	#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
AnnaBridge	172:65be27845400	585	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
AnnaBridge	172:65be27845400	586	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
AnnaBridge	172:65be27845400	587	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
AnnaBridge	172:65be27845400	588	#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
AnnaBridge	172:65be27845400	589	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
AnnaBridge	172:65be27845400	590	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
AnnaBridge	172:65be27845400	591	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
AnnaBridge	172:65be27845400	592	#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
AnnaBridge	172:65be27845400	593
AnnaBridge	172:65be27845400	594	#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
AnnaBridge	172:65be27845400	595	#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
AnnaBridge	172:65be27845400	596	#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
AnnaBridge	172:65be27845400	597	#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
AnnaBridge	172:65be27845400	598	#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
AnnaBridge	172:65be27845400	599	#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
AnnaBridge	172:65be27845400	600	#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
AnnaBridge	172:65be27845400	601	#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
AnnaBridge	172:65be27845400	602	/**
AnnaBridge	172:65be27845400	603	* @}
AnnaBridge	172:65be27845400	604	*/
AnnaBridge	172:65be27845400	605
AnnaBridge	172:65be27845400	606	/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
AnnaBridge	172:65be27845400	607	* @{
AnnaBridge	172:65be27845400	608	*/
AnnaBridge	172:65be27845400	609	#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
AnnaBridge	172:65be27845400	610	#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
AnnaBridge	172:65be27845400	611	#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
AnnaBridge	172:65be27845400	612	#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
AnnaBridge	172:65be27845400	613	#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
AnnaBridge	172:65be27845400	614	#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
AnnaBridge	172:65be27845400	615	#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
AnnaBridge	172:65be27845400	616	#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
AnnaBridge	172:65be27845400	617	#if defined(STM32F0) \|\| defined(STM32F1) \|\| defined(STM32F3) \|\| defined(STM32G0) \|\| defined(STM32L4) \|\| defined(STM32L1) \|\| defined(STM32F7)
AnnaBridge	172:65be27845400	618	#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
AnnaBridge	172:65be27845400	619	#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
AnnaBridge	172:65be27845400	620	#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
AnnaBridge	172:65be27845400	621	#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
AnnaBridge	172:65be27845400	622	#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
AnnaBridge	172:65be27845400	623	#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
AnnaBridge	172:65be27845400	624	#endif
AnnaBridge	172:65be27845400	625	/**
AnnaBridge	172:65be27845400	626	* @}
AnnaBridge	172:65be27845400	627	*/
AnnaBridge	172:65be27845400	628
AnnaBridge	172:65be27845400	629	/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
AnnaBridge	172:65be27845400	630	* @{
AnnaBridge	172:65be27845400	631	*/
AnnaBridge	172:65be27845400	632	#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
AnnaBridge	172:65be27845400	633	#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
AnnaBridge	172:65be27845400	634
AnnaBridge	172:65be27845400	635	/**
AnnaBridge	172:65be27845400	636	* @}
AnnaBridge	172:65be27845400	637	*/
AnnaBridge	172:65be27845400	638
AnnaBridge	172:65be27845400	639	/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
AnnaBridge	172:65be27845400	640	* @{
AnnaBridge	172:65be27845400	641	*/
AnnaBridge	172:65be27845400	642	#define KR_KEY_RELOAD IWDG_KEY_RELOAD
AnnaBridge	172:65be27845400	643	#define KR_KEY_ENABLE IWDG_KEY_ENABLE
AnnaBridge	172:65be27845400	644	#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
AnnaBridge	172:65be27845400	645	#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
AnnaBridge	172:65be27845400	646	/**
AnnaBridge	172:65be27845400	647	* @}
AnnaBridge	172:65be27845400	648	*/
AnnaBridge	172:65be27845400	649
AnnaBridge	172:65be27845400	650	/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
AnnaBridge	172:65be27845400	651	* @{
AnnaBridge	172:65be27845400	652	*/
AnnaBridge	172:65be27845400	653
AnnaBridge	172:65be27845400	654	#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
AnnaBridge	172:65be27845400	655	#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
AnnaBridge	172:65be27845400	656	#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
AnnaBridge	172:65be27845400	657	#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
AnnaBridge	172:65be27845400	658
AnnaBridge	172:65be27845400	659	#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
AnnaBridge	172:65be27845400	660	#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
AnnaBridge	172:65be27845400	661	#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
AnnaBridge	172:65be27845400	662
AnnaBridge	172:65be27845400	663	#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
AnnaBridge	172:65be27845400	664	#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
AnnaBridge	172:65be27845400	665	#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
AnnaBridge	172:65be27845400	666	#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
AnnaBridge	172:65be27845400	667
AnnaBridge	172:65be27845400	668	/* The following 3 definition have also been present in a temporary version of lptim.h */
AnnaBridge	172:65be27845400	669	/* They need to be renamed also to the right name, just in case */
AnnaBridge	172:65be27845400	670	#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
AnnaBridge	172:65be27845400	671	#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
AnnaBridge	172:65be27845400	672	#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
AnnaBridge	172:65be27845400	673
AnnaBridge	172:65be27845400	674	/**
AnnaBridge	172:65be27845400	675	* @}
AnnaBridge	172:65be27845400	676	*/
AnnaBridge	172:65be27845400	677
AnnaBridge	172:65be27845400	678	/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
AnnaBridge	172:65be27845400	679	* @{
AnnaBridge	172:65be27845400	680	*/
AnnaBridge	172:65be27845400	681	#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
AnnaBridge	172:65be27845400	682	#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
AnnaBridge	172:65be27845400	683	#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
AnnaBridge	172:65be27845400	684	#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
AnnaBridge	172:65be27845400	685
AnnaBridge	172:65be27845400	686	#define NAND_AddressTypedef NAND_AddressTypeDef
AnnaBridge	172:65be27845400	687
AnnaBridge	172:65be27845400	688	#define __ARRAY_ADDRESS ARRAY_ADDRESS
AnnaBridge	172:65be27845400	689	#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
AnnaBridge	172:65be27845400	690	#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
AnnaBridge	172:65be27845400	691	#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
AnnaBridge	172:65be27845400	692	#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
AnnaBridge	172:65be27845400	693	/**
AnnaBridge	172:65be27845400	694	* @}
AnnaBridge	172:65be27845400	695	*/
AnnaBridge	172:65be27845400	696
AnnaBridge	172:65be27845400	697	/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
AnnaBridge	172:65be27845400	698	* @{
AnnaBridge	172:65be27845400	699	*/
AnnaBridge	172:65be27845400	700	#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
AnnaBridge	172:65be27845400	701	#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
AnnaBridge	172:65be27845400	702	#define NOR_ONGOING HAL_NOR_STATUS_ONGOING
AnnaBridge	172:65be27845400	703	#define NOR_ERROR HAL_NOR_STATUS_ERROR
AnnaBridge	172:65be27845400	704	#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
AnnaBridge	172:65be27845400	705
AnnaBridge	172:65be27845400	706	#define __NOR_WRITE NOR_WRITE
AnnaBridge	172:65be27845400	707	#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
AnnaBridge	172:65be27845400	708	/**
AnnaBridge	172:65be27845400	709	* @}
AnnaBridge	172:65be27845400	710	*/
AnnaBridge	172:65be27845400	711
AnnaBridge	172:65be27845400	712	/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
AnnaBridge	172:65be27845400	713	* @{
AnnaBridge	172:65be27845400	714	*/
AnnaBridge	172:65be27845400	715
AnnaBridge	172:65be27845400	716	#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
AnnaBridge	172:65be27845400	717	#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
AnnaBridge	172:65be27845400	718	#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
AnnaBridge	172:65be27845400	719	#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
AnnaBridge	172:65be27845400	720
AnnaBridge	172:65be27845400	721	#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
AnnaBridge	172:65be27845400	722	#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
AnnaBridge	172:65be27845400	723	#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
AnnaBridge	172:65be27845400	724	#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
AnnaBridge	172:65be27845400	725
AnnaBridge	172:65be27845400	726	#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
AnnaBridge	172:65be27845400	727	#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
AnnaBridge	172:65be27845400	728
AnnaBridge	172:65be27845400	729	#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
AnnaBridge	172:65be27845400	730	#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
AnnaBridge	172:65be27845400	731
AnnaBridge	172:65be27845400	732	#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
AnnaBridge	172:65be27845400	733	#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
AnnaBridge	172:65be27845400	734
AnnaBridge	172:65be27845400	735	#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
AnnaBridge	172:65be27845400	736
AnnaBridge	172:65be27845400	737	#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
AnnaBridge	172:65be27845400	738	#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
AnnaBridge	172:65be27845400	739	#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
AnnaBridge	172:65be27845400	740
AnnaBridge	172:65be27845400	741	/**
AnnaBridge	172:65be27845400	742	* @}
AnnaBridge	172:65be27845400	743	*/
AnnaBridge	172:65be27845400	744
AnnaBridge	172:65be27845400	745	/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
AnnaBridge	172:65be27845400	746	* @{
AnnaBridge	172:65be27845400	747	*/
AnnaBridge	172:65be27845400	748	#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
AnnaBridge	172:65be27845400	749
AnnaBridge	172:65be27845400	750	#if defined(STM32H7)
AnnaBridge	172:65be27845400	751	#define I2S_IT_TXE I2S_IT_TXP
AnnaBridge	172:65be27845400	752	#define I2S_IT_RXNE I2S_IT_RXP
AnnaBridge	172:65be27845400	753
AnnaBridge	172:65be27845400	754	#define I2S_FLAG_TXE I2S_FLAG_TXP
AnnaBridge	172:65be27845400	755	#define I2S_FLAG_RXNE I2S_FLAG_RXP
AnnaBridge	172:65be27845400	756	#define I2S_FLAG_FRE I2S_FLAG_TIFRE
AnnaBridge	172:65be27845400	757	#endif
AnnaBridge	172:65be27845400	758
AnnaBridge	172:65be27845400	759	#if defined(STM32F7)
AnnaBridge	172:65be27845400	760	#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
AnnaBridge	172:65be27845400	761	#endif
AnnaBridge	172:65be27845400	762	/**
AnnaBridge	172:65be27845400	763	* @}
AnnaBridge	172:65be27845400	764	*/
AnnaBridge	172:65be27845400	765
AnnaBridge	172:65be27845400	766	/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
AnnaBridge	172:65be27845400	767	* @{
AnnaBridge	172:65be27845400	768	*/
AnnaBridge	172:65be27845400	769
AnnaBridge	172:65be27845400	770	/* Compact Flash-ATA registers description */
AnnaBridge	172:65be27845400	771	#define CF_DATA ATA_DATA
AnnaBridge	172:65be27845400	772	#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
AnnaBridge	172:65be27845400	773	#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
AnnaBridge	172:65be27845400	774	#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
AnnaBridge	172:65be27845400	775	#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
AnnaBridge	172:65be27845400	776	#define CF_CARD_HEAD ATA_CARD_HEAD
AnnaBridge	172:65be27845400	777	#define CF_STATUS_CMD ATA_STATUS_CMD
AnnaBridge	172:65be27845400	778	#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
AnnaBridge	172:65be27845400	779	#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
AnnaBridge	172:65be27845400	780
AnnaBridge	172:65be27845400	781	/* Compact Flash-ATA commands */
AnnaBridge	172:65be27845400	782	#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
AnnaBridge	172:65be27845400	783	#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
AnnaBridge	172:65be27845400	784	#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
AnnaBridge	172:65be27845400	785	#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
AnnaBridge	172:65be27845400	786
AnnaBridge	172:65be27845400	787	#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
AnnaBridge	172:65be27845400	788	#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
AnnaBridge	172:65be27845400	789	#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
AnnaBridge	172:65be27845400	790	#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
AnnaBridge	172:65be27845400	791	#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
AnnaBridge	172:65be27845400	792	/**
AnnaBridge	172:65be27845400	793	* @}
AnnaBridge	172:65be27845400	794	*/
AnnaBridge	172:65be27845400	795
AnnaBridge	172:65be27845400	796	/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
AnnaBridge	172:65be27845400	797	* @{
AnnaBridge	172:65be27845400	798	*/
AnnaBridge	172:65be27845400	799
AnnaBridge	172:65be27845400	800	#define FORMAT_BIN RTC_FORMAT_BIN
AnnaBridge	172:65be27845400	801	#define FORMAT_BCD RTC_FORMAT_BCD
AnnaBridge	172:65be27845400	802
AnnaBridge	172:65be27845400	803	#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
AnnaBridge	172:65be27845400	804	#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
AnnaBridge	172:65be27845400	805	#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
AnnaBridge	172:65be27845400	806	#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
AnnaBridge	172:65be27845400	807
AnnaBridge	172:65be27845400	808	#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
AnnaBridge	172:65be27845400	809	#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
AnnaBridge	172:65be27845400	810	#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
AnnaBridge	172:65be27845400	811	#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
AnnaBridge	172:65be27845400	812	#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
AnnaBridge	172:65be27845400	813
AnnaBridge	172:65be27845400	814	#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
AnnaBridge	172:65be27845400	815	#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
AnnaBridge	172:65be27845400	816	#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
AnnaBridge	172:65be27845400	817	#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
AnnaBridge	172:65be27845400	818
AnnaBridge	172:65be27845400	819	#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
AnnaBridge	172:65be27845400	820	#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
AnnaBridge	172:65be27845400	821	#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
AnnaBridge	172:65be27845400	822
AnnaBridge	172:65be27845400	823	#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
AnnaBridge	172:65be27845400	824	#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
AnnaBridge	172:65be27845400	825	#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
AnnaBridge	172:65be27845400	826
AnnaBridge	172:65be27845400	827	/**
AnnaBridge	172:65be27845400	828	* @}
AnnaBridge	172:65be27845400	829	*/
AnnaBridge	172:65be27845400	830
AnnaBridge	172:65be27845400	831
AnnaBridge	172:65be27845400	832	/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
AnnaBridge	172:65be27845400	833	* @{
AnnaBridge	172:65be27845400	834	*/
AnnaBridge	172:65be27845400	835	#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
AnnaBridge	172:65be27845400	836	#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
AnnaBridge	172:65be27845400	837
AnnaBridge	172:65be27845400	838	#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
AnnaBridge	172:65be27845400	839	#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
AnnaBridge	172:65be27845400	840	#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
AnnaBridge	172:65be27845400	841	#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
AnnaBridge	172:65be27845400	842
AnnaBridge	172:65be27845400	843	#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
AnnaBridge	172:65be27845400	844	#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
AnnaBridge	172:65be27845400	845
AnnaBridge	172:65be27845400	846	#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
AnnaBridge	172:65be27845400	847	#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
AnnaBridge	172:65be27845400	848	/**
AnnaBridge	172:65be27845400	849	* @}
AnnaBridge	172:65be27845400	850	*/
AnnaBridge	172:65be27845400	851
AnnaBridge	172:65be27845400	852
AnnaBridge	172:65be27845400	853	/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
AnnaBridge	172:65be27845400	854	* @{
AnnaBridge	172:65be27845400	855	*/
AnnaBridge	172:65be27845400	856	#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
AnnaBridge	172:65be27845400	857	#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
AnnaBridge	172:65be27845400	858	#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
AnnaBridge	172:65be27845400	859	#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
AnnaBridge	172:65be27845400	860	#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
AnnaBridge	172:65be27845400	861	#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
AnnaBridge	172:65be27845400	862	#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
AnnaBridge	172:65be27845400	863	#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
AnnaBridge	172:65be27845400	864	#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
AnnaBridge	172:65be27845400	865	#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
AnnaBridge	172:65be27845400	866	#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
AnnaBridge	172:65be27845400	867	/**
AnnaBridge	172:65be27845400	868	* @}
AnnaBridge	172:65be27845400	869	*/
AnnaBridge	172:65be27845400	870
AnnaBridge	172:65be27845400	871	/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
AnnaBridge	172:65be27845400	872	* @{
AnnaBridge	172:65be27845400	873	*/
AnnaBridge	172:65be27845400	874	#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
AnnaBridge	172:65be27845400	875	#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
AnnaBridge	172:65be27845400	876
AnnaBridge	172:65be27845400	877	#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
AnnaBridge	172:65be27845400	878	#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
AnnaBridge	172:65be27845400	879
AnnaBridge	172:65be27845400	880	#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
AnnaBridge	172:65be27845400	881	#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
AnnaBridge	172:65be27845400	882
AnnaBridge	172:65be27845400	883	#if defined(STM32H7)
AnnaBridge	172:65be27845400	884
AnnaBridge	172:65be27845400	885	#define SPI_FLAG_TXE SPI_FLAG_TXP
AnnaBridge	172:65be27845400	886	#define SPI_FLAG_RXNE SPI_FLAG_RXP
AnnaBridge	172:65be27845400	887
AnnaBridge	172:65be27845400	888	#define SPI_IT_TXE SPI_IT_TXP
AnnaBridge	172:65be27845400	889	#define SPI_IT_RXNE SPI_IT_RXP
AnnaBridge	172:65be27845400	890
AnnaBridge	172:65be27845400	891	#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
AnnaBridge	172:65be27845400	892	#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
AnnaBridge	172:65be27845400	893	#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
AnnaBridge	172:65be27845400	894	#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
AnnaBridge	172:65be27845400	895
AnnaBridge	172:65be27845400	896	#endif /* STM32H7 */
AnnaBridge	172:65be27845400	897
AnnaBridge	172:65be27845400	898	/**
AnnaBridge	172:65be27845400	899	* @}
AnnaBridge	172:65be27845400	900	*/
AnnaBridge	172:65be27845400	901
AnnaBridge	172:65be27845400	902	/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
AnnaBridge	172:65be27845400	903	* @{
AnnaBridge	172:65be27845400	904	*/
AnnaBridge	172:65be27845400	905	#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
AnnaBridge	172:65be27845400	906	#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
AnnaBridge	172:65be27845400	907
AnnaBridge	172:65be27845400	908	#define TIM_DMABase_CR1 TIM_DMABASE_CR1
AnnaBridge	172:65be27845400	909	#define TIM_DMABase_CR2 TIM_DMABASE_CR2
AnnaBridge	172:65be27845400	910	#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
AnnaBridge	172:65be27845400	911	#define TIM_DMABase_DIER TIM_DMABASE_DIER
AnnaBridge	172:65be27845400	912	#define TIM_DMABase_SR TIM_DMABASE_SR
AnnaBridge	172:65be27845400	913	#define TIM_DMABase_EGR TIM_DMABASE_EGR
AnnaBridge	172:65be27845400	914	#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
AnnaBridge	172:65be27845400	915	#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
AnnaBridge	172:65be27845400	916	#define TIM_DMABase_CCER TIM_DMABASE_CCER
AnnaBridge	172:65be27845400	917	#define TIM_DMABase_CNT TIM_DMABASE_CNT
AnnaBridge	172:65be27845400	918	#define TIM_DMABase_PSC TIM_DMABASE_PSC
AnnaBridge	172:65be27845400	919	#define TIM_DMABase_ARR TIM_DMABASE_ARR
AnnaBridge	172:65be27845400	920	#define TIM_DMABase_RCR TIM_DMABASE_RCR
AnnaBridge	172:65be27845400	921	#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
AnnaBridge	172:65be27845400	922	#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
AnnaBridge	172:65be27845400	923	#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
AnnaBridge	172:65be27845400	924	#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
AnnaBridge	172:65be27845400	925	#define TIM_DMABase_BDTR TIM_DMABASE_BDTR
AnnaBridge	172:65be27845400	926	#define TIM_DMABase_DCR TIM_DMABASE_DCR
AnnaBridge	172:65be27845400	927	#define TIM_DMABase_DMAR TIM_DMABASE_DMAR
AnnaBridge	172:65be27845400	928	#define TIM_DMABase_OR1 TIM_DMABASE_OR1
AnnaBridge	172:65be27845400	929	#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
AnnaBridge	172:65be27845400	930	#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
AnnaBridge	172:65be27845400	931	#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
AnnaBridge	172:65be27845400	932	#define TIM_DMABase_OR2 TIM_DMABASE_OR2
AnnaBridge	172:65be27845400	933	#define TIM_DMABase_OR3 TIM_DMABASE_OR3
AnnaBridge	172:65be27845400	934	#define TIM_DMABase_OR TIM_DMABASE_OR
AnnaBridge	172:65be27845400	935
AnnaBridge	172:65be27845400	936	#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
AnnaBridge	172:65be27845400	937	#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
AnnaBridge	172:65be27845400	938	#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
AnnaBridge	172:65be27845400	939	#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
AnnaBridge	172:65be27845400	940	#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
AnnaBridge	172:65be27845400	941	#define TIM_EventSource_COM TIM_EVENTSOURCE_COM
AnnaBridge	172:65be27845400	942	#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
AnnaBridge	172:65be27845400	943	#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
AnnaBridge	172:65be27845400	944	#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
AnnaBridge	172:65be27845400	945
AnnaBridge	172:65be27845400	946	#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
AnnaBridge	172:65be27845400	947	#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
AnnaBridge	172:65be27845400	948	#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
AnnaBridge	172:65be27845400	949	#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
AnnaBridge	172:65be27845400	950	#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
AnnaBridge	172:65be27845400	951	#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
AnnaBridge	172:65be27845400	952	#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
AnnaBridge	172:65be27845400	953	#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
AnnaBridge	172:65be27845400	954	#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
AnnaBridge	172:65be27845400	955	#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
AnnaBridge	172:65be27845400	956	#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
AnnaBridge	172:65be27845400	957	#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
AnnaBridge	172:65be27845400	958	#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
AnnaBridge	172:65be27845400	959	#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
AnnaBridge	172:65be27845400	960	#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
AnnaBridge	172:65be27845400	961	#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
AnnaBridge	172:65be27845400	962	#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
AnnaBridge	172:65be27845400	963	#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
AnnaBridge	172:65be27845400	964
AnnaBridge	172:65be27845400	965	#if defined(STM32L0)
AnnaBridge	172:65be27845400	966	#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO
AnnaBridge	172:65be27845400	967	#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO
AnnaBridge	172:65be27845400	968	#endif
AnnaBridge	172:65be27845400	969
AnnaBridge	172:65be27845400	970	#if defined(STM32F3)
AnnaBridge	172:65be27845400	971	#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
AnnaBridge	172:65be27845400	972	#endif
AnnaBridge	172:65be27845400	973
AnnaBridge	172:65be27845400	974	/**
AnnaBridge	172:65be27845400	975	* @}
AnnaBridge	172:65be27845400	976	*/
AnnaBridge	172:65be27845400	977
AnnaBridge	172:65be27845400	978	/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
AnnaBridge	172:65be27845400	979	* @{
AnnaBridge	172:65be27845400	980	*/
AnnaBridge	172:65be27845400	981	#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
AnnaBridge	172:65be27845400	982	#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
AnnaBridge	172:65be27845400	983	/**
AnnaBridge	172:65be27845400	984	* @}
AnnaBridge	172:65be27845400	985	*/
AnnaBridge	172:65be27845400	986
AnnaBridge	172:65be27845400	987	/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
AnnaBridge	172:65be27845400	988	* @{
AnnaBridge	172:65be27845400	989	*/
AnnaBridge	172:65be27845400	990	#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
AnnaBridge	172:65be27845400	991	#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
AnnaBridge	172:65be27845400	992	#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
AnnaBridge	172:65be27845400	993	#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
AnnaBridge	172:65be27845400	994
AnnaBridge	172:65be27845400	995	#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
AnnaBridge	172:65be27845400	996	#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
AnnaBridge	172:65be27845400	997
AnnaBridge	172:65be27845400	998	#define __DIV_SAMPLING16 UART_DIV_SAMPLING16
AnnaBridge	172:65be27845400	999	#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
AnnaBridge	172:65be27845400	1000	#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
AnnaBridge	172:65be27845400	1001	#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
AnnaBridge	172:65be27845400	1002
AnnaBridge	172:65be27845400	1003	#define __DIV_SAMPLING8 UART_DIV_SAMPLING8
AnnaBridge	172:65be27845400	1004	#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
AnnaBridge	172:65be27845400	1005	#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
AnnaBridge	172:65be27845400	1006	#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
AnnaBridge	172:65be27845400	1007
AnnaBridge	172:65be27845400	1008	#define __DIV_LPUART UART_DIV_LPUART
AnnaBridge	172:65be27845400	1009
AnnaBridge	172:65be27845400	1010	#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
AnnaBridge	172:65be27845400	1011	#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
AnnaBridge	172:65be27845400	1012
AnnaBridge	172:65be27845400	1013	/**
AnnaBridge	172:65be27845400	1014	* @}
AnnaBridge	172:65be27845400	1015	*/
AnnaBridge	172:65be27845400	1016
AnnaBridge	172:65be27845400	1017
AnnaBridge	172:65be27845400	1018	/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
AnnaBridge	172:65be27845400	1019	* @{
AnnaBridge	172:65be27845400	1020	*/
AnnaBridge	172:65be27845400	1021
AnnaBridge	172:65be27845400	1022	#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
AnnaBridge	172:65be27845400	1023	#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
AnnaBridge	172:65be27845400	1024
AnnaBridge	172:65be27845400	1025	#define USARTNACK_ENABLED USART_NACK_ENABLE
AnnaBridge	172:65be27845400	1026	#define USARTNACK_DISABLED USART_NACK_DISABLE
AnnaBridge	172:65be27845400	1027	/**
AnnaBridge	172:65be27845400	1028	* @}
AnnaBridge	172:65be27845400	1029	*/
AnnaBridge	172:65be27845400	1030
AnnaBridge	172:65be27845400	1031	/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
AnnaBridge	172:65be27845400	1032	* @{
AnnaBridge	172:65be27845400	1033	*/
AnnaBridge	172:65be27845400	1034	#define CFR_BASE WWDG_CFR_BASE
AnnaBridge	172:65be27845400	1035
AnnaBridge	172:65be27845400	1036	/**
AnnaBridge	172:65be27845400	1037	* @}
AnnaBridge	172:65be27845400	1038	*/
AnnaBridge	172:65be27845400	1039
AnnaBridge	172:65be27845400	1040	/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
AnnaBridge	172:65be27845400	1041	* @{
AnnaBridge	172:65be27845400	1042	*/
AnnaBridge	172:65be27845400	1043	#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
AnnaBridge	172:65be27845400	1044	#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
AnnaBridge	172:65be27845400	1045	#define CAN_IT_RQCP0 CAN_IT_TME
AnnaBridge	172:65be27845400	1046	#define CAN_IT_RQCP1 CAN_IT_TME
AnnaBridge	172:65be27845400	1047	#define CAN_IT_RQCP2 CAN_IT_TME
AnnaBridge	172:65be27845400	1048	#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
AnnaBridge	172:65be27845400	1049	#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
AnnaBridge	172:65be27845400	1050	#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
AnnaBridge	172:65be27845400	1051	#define CAN_TXSTATUS_OK ((uint8_t)0x01U)
AnnaBridge	172:65be27845400	1052	#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
AnnaBridge	172:65be27845400	1053
AnnaBridge	172:65be27845400	1054	/**
AnnaBridge	172:65be27845400	1055	* @}
AnnaBridge	172:65be27845400	1056	*/
AnnaBridge	172:65be27845400	1057
AnnaBridge	172:65be27845400	1058	/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
AnnaBridge	172:65be27845400	1059	* @{
AnnaBridge	172:65be27845400	1060	*/
AnnaBridge	172:65be27845400	1061
AnnaBridge	172:65be27845400	1062	#define VLAN_TAG ETH_VLAN_TAG
AnnaBridge	172:65be27845400	1063	#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
AnnaBridge	172:65be27845400	1064	#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
AnnaBridge	172:65be27845400	1065	#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
AnnaBridge	172:65be27845400	1066	#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
AnnaBridge	172:65be27845400	1067	#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
AnnaBridge	172:65be27845400	1068	#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
AnnaBridge	172:65be27845400	1069	#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
AnnaBridge	172:65be27845400	1070
AnnaBridge	172:65be27845400	1071	#define ETH_MMCCR 0x00000100U
AnnaBridge	172:65be27845400	1072	#define ETH_MMCRIR 0x00000104U
AnnaBridge	172:65be27845400	1073	#define ETH_MMCTIR 0x00000108U
AnnaBridge	172:65be27845400	1074	#define ETH_MMCRIMR 0x0000010CU
AnnaBridge	172:65be27845400	1075	#define ETH_MMCTIMR 0x00000110U
AnnaBridge	172:65be27845400	1076	#define ETH_MMCTGFSCCR 0x0000014CU
AnnaBridge	172:65be27845400	1077	#define ETH_MMCTGFMSCCR 0x00000150U
AnnaBridge	172:65be27845400	1078	#define ETH_MMCTGFCR 0x00000168U
AnnaBridge	172:65be27845400	1079	#define ETH_MMCRFCECR 0x00000194U
AnnaBridge	172:65be27845400	1080	#define ETH_MMCRFAECR 0x00000198U
AnnaBridge	172:65be27845400	1081	#define ETH_MMCRGUFCR 0x000001C4U
AnnaBridge	172:65be27845400	1082
AnnaBridge	172:65be27845400	1083	#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
AnnaBridge	172:65be27845400	1084	#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
AnnaBridge	172:65be27845400	1085	#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
AnnaBridge	172:65be27845400	1086	#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
AnnaBridge	172:65be27845400	1087	#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
AnnaBridge	172:65be27845400	1088	#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
AnnaBridge	172:65be27845400	1089	#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
AnnaBridge	172:65be27845400	1090	#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
AnnaBridge	172:65be27845400	1091	#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
AnnaBridge	172:65be27845400	1092	#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
AnnaBridge	172:65be27845400	1093	#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
AnnaBridge	172:65be27845400	1094	#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
AnnaBridge	172:65be27845400	1095	#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
AnnaBridge	172:65be27845400	1096	#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
AnnaBridge	172:65be27845400	1097	#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
AnnaBridge	172:65be27845400	1098	#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
AnnaBridge	172:65be27845400	1099	#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
AnnaBridge	172:65be27845400	1100	#if defined(STM32F1)
AnnaBridge	172:65be27845400	1101	#else
AnnaBridge	172:65be27845400	1102	#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
AnnaBridge	172:65be27845400	1103	#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
AnnaBridge	172:65be27845400	1104	#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
AnnaBridge	172:65be27845400	1105	#endif
AnnaBridge	172:65be27845400	1106	#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
AnnaBridge	172:65be27845400	1107	#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
AnnaBridge	172:65be27845400	1108	#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
AnnaBridge	172:65be27845400	1109	#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
AnnaBridge	172:65be27845400	1110	#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */
AnnaBridge	172:65be27845400	1111	#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
AnnaBridge	172:65be27845400	1112	#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
AnnaBridge	172:65be27845400	1113
AnnaBridge	172:65be27845400	1114	/**
AnnaBridge	172:65be27845400	1115	* @}
AnnaBridge	172:65be27845400	1116	*/
AnnaBridge	172:65be27845400	1117
AnnaBridge	172:65be27845400	1118	/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
AnnaBridge	172:65be27845400	1119	* @{
AnnaBridge	172:65be27845400	1120	*/
AnnaBridge	172:65be27845400	1121	#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
AnnaBridge	172:65be27845400	1122	#define DCMI_IT_OVF DCMI_IT_OVR
AnnaBridge	172:65be27845400	1123	#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
AnnaBridge	172:65be27845400	1124	#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
AnnaBridge	172:65be27845400	1125
AnnaBridge	172:65be27845400	1126	#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
AnnaBridge	172:65be27845400	1127	#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
AnnaBridge	172:65be27845400	1128	#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
AnnaBridge	172:65be27845400	1129
AnnaBridge	172:65be27845400	1130	/**
AnnaBridge	172:65be27845400	1131	* @}
AnnaBridge	172:65be27845400	1132	*/
AnnaBridge	172:65be27845400	1133
AnnaBridge	172:65be27845400	1134	#if defined(STM32L4) \|\| defined(STM32F7) \|\| defined(STM32F427xx) \|\| defined(STM32F437xx) \
AnnaBridge	172:65be27845400	1135	\|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) \
AnnaBridge	172:65be27845400	1136	\|\| defined(STM32H7)
AnnaBridge	172:65be27845400	1137	/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
AnnaBridge	172:65be27845400	1138	* @{
AnnaBridge	172:65be27845400	1139	*/
AnnaBridge	172:65be27845400	1140	#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
AnnaBridge	172:65be27845400	1141	#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
AnnaBridge	172:65be27845400	1142	#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
AnnaBridge	172:65be27845400	1143	#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
AnnaBridge	172:65be27845400	1144	#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
AnnaBridge	172:65be27845400	1145
AnnaBridge	172:65be27845400	1146	#define CM_ARGB8888 DMA2D_INPUT_ARGB8888
AnnaBridge	172:65be27845400	1147	#define CM_RGB888 DMA2D_INPUT_RGB888
AnnaBridge	172:65be27845400	1148	#define CM_RGB565 DMA2D_INPUT_RGB565
AnnaBridge	172:65be27845400	1149	#define CM_ARGB1555 DMA2D_INPUT_ARGB1555
AnnaBridge	172:65be27845400	1150	#define CM_ARGB4444 DMA2D_INPUT_ARGB4444
AnnaBridge	172:65be27845400	1151	#define CM_L8 DMA2D_INPUT_L8
AnnaBridge	172:65be27845400	1152	#define CM_AL44 DMA2D_INPUT_AL44
AnnaBridge	172:65be27845400	1153	#define CM_AL88 DMA2D_INPUT_AL88
AnnaBridge	172:65be27845400	1154	#define CM_L4 DMA2D_INPUT_L4
AnnaBridge	172:65be27845400	1155	#define CM_A8 DMA2D_INPUT_A8
AnnaBridge	172:65be27845400	1156	#define CM_A4 DMA2D_INPUT_A4
AnnaBridge	172:65be27845400	1157	/**
AnnaBridge	172:65be27845400	1158	* @}
AnnaBridge	172:65be27845400	1159	*/
AnnaBridge	172:65be27845400	1160	#endif /* STM32L4 \|\| STM32F7 \|\| STM32F4 \|\| STM32H7 */
AnnaBridge	172:65be27845400	1161
AnnaBridge	172:65be27845400	1162	/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
AnnaBridge	172:65be27845400	1163	* @{
AnnaBridge	172:65be27845400	1164	*/
AnnaBridge	172:65be27845400	1165
AnnaBridge	172:65be27845400	1166	/**
AnnaBridge	172:65be27845400	1167	* @}
AnnaBridge	172:65be27845400	1168	*/
AnnaBridge	172:65be27845400	1169
AnnaBridge	172:65be27845400	1170	/* Exported functions --------------------------------------------------------*/
AnnaBridge	172:65be27845400	1171
AnnaBridge	172:65be27845400	1172	/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
AnnaBridge	172:65be27845400	1173	* @{
AnnaBridge	172:65be27845400	1174	*/
AnnaBridge	172:65be27845400	1175	#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
AnnaBridge	172:65be27845400	1176	/**
AnnaBridge	172:65be27845400	1177	* @}
AnnaBridge	172:65be27845400	1178	*/
AnnaBridge	172:65be27845400	1179
AnnaBridge	172:65be27845400	1180	/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
AnnaBridge	172:65be27845400	1181	* @{
AnnaBridge	172:65be27845400	1182	*/
AnnaBridge	172:65be27845400	1183	#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
AnnaBridge	172:65be27845400	1184	#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
AnnaBridge	172:65be27845400	1185	#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
AnnaBridge	172:65be27845400	1186	#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
AnnaBridge	172:65be27845400	1187	#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
AnnaBridge	172:65be27845400	1188	#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
AnnaBridge	172:65be27845400	1189
AnnaBridge	172:65be27845400	1190	/HASH Algorithm Selection/
AnnaBridge	172:65be27845400	1191
AnnaBridge	172:65be27845400	1192	#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
AnnaBridge	172:65be27845400	1193	#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
AnnaBridge	172:65be27845400	1194	#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
AnnaBridge	172:65be27845400	1195	#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
AnnaBridge	172:65be27845400	1196
AnnaBridge	172:65be27845400	1197	#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
AnnaBridge	172:65be27845400	1198	#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
AnnaBridge	172:65be27845400	1199
AnnaBridge	172:65be27845400	1200	#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
AnnaBridge	172:65be27845400	1201	#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
AnnaBridge	172:65be27845400	1202	/**
AnnaBridge	172:65be27845400	1203	* @}
AnnaBridge	172:65be27845400	1204	*/
AnnaBridge	172:65be27845400	1205
AnnaBridge	172:65be27845400	1206	/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
AnnaBridge	172:65be27845400	1207	* @{
AnnaBridge	172:65be27845400	1208	*/
AnnaBridge	172:65be27845400	1209	#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
AnnaBridge	172:65be27845400	1210	#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
AnnaBridge	172:65be27845400	1211	#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
AnnaBridge	172:65be27845400	1212	#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
AnnaBridge	172:65be27845400	1213	#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
AnnaBridge	172:65be27845400	1214	#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
AnnaBridge	172:65be27845400	1215	#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
AnnaBridge	172:65be27845400	1216	#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
AnnaBridge	172:65be27845400	1217	#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
AnnaBridge	172:65be27845400	1218	#if defined(STM32L0)
AnnaBridge	172:65be27845400	1219	#else
AnnaBridge	172:65be27845400	1220	#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
AnnaBridge	172:65be27845400	1221	#endif
AnnaBridge	172:65be27845400	1222	#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
AnnaBridge	172:65be27845400	1223	#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
AnnaBridge	172:65be27845400	1224	/**
AnnaBridge	172:65be27845400	1225	* @}
AnnaBridge	172:65be27845400	1226	*/
AnnaBridge	172:65be27845400	1227
AnnaBridge	172:65be27845400	1228	/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
AnnaBridge	172:65be27845400	1229	* @{
AnnaBridge	172:65be27845400	1230	*/
AnnaBridge	172:65be27845400	1231	#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
AnnaBridge	172:65be27845400	1232	#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
AnnaBridge	172:65be27845400	1233	#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
AnnaBridge	172:65be27845400	1234	#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
AnnaBridge	172:65be27845400	1235	#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
AnnaBridge	172:65be27845400	1236	#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
AnnaBridge	172:65be27845400	1237	#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
AnnaBridge	172:65be27845400	1238
AnnaBridge	172:65be27845400	1239	/**
AnnaBridge	172:65be27845400	1240	* @}
AnnaBridge	172:65be27845400	1241	*/
AnnaBridge	172:65be27845400	1242
AnnaBridge	172:65be27845400	1243	/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
AnnaBridge	172:65be27845400	1244	* @{
AnnaBridge	172:65be27845400	1245	*/
AnnaBridge	172:65be27845400	1246	#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
AnnaBridge	172:65be27845400	1247	#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
AnnaBridge	172:65be27845400	1248	#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
AnnaBridge	172:65be27845400	1249	#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
AnnaBridge	172:65be27845400	1250
AnnaBridge	172:65be27845400	1251	#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
AnnaBridge	172:65be27845400	1252
AnnaBridge	172:65be27845400	1253	#if defined(STM32H7) \|\| defined(STM32G0)
AnnaBridge	172:65be27845400	1254	#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
AnnaBridge	172:65be27845400	1255	#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
AnnaBridge	172:65be27845400	1256	#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
AnnaBridge	172:65be27845400	1257	#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
AnnaBridge	172:65be27845400	1258	#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
AnnaBridge	172:65be27845400	1259	#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
AnnaBridge	172:65be27845400	1260	#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
AnnaBridge	172:65be27845400	1261	#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
AnnaBridge	172:65be27845400	1262	#endif /* STM32H7 \|\| STM32G0 */
AnnaBridge	172:65be27845400	1263	/**
AnnaBridge	172:65be27845400	1264	* @}
AnnaBridge	172:65be27845400	1265	*/
AnnaBridge	172:65be27845400	1266
AnnaBridge	172:65be27845400	1267	/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
AnnaBridge	172:65be27845400	1268	* @{
AnnaBridge	172:65be27845400	1269	*/
AnnaBridge	172:65be27845400	1270	#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
AnnaBridge	172:65be27845400	1271	#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
AnnaBridge	172:65be27845400	1272	#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
AnnaBridge	172:65be27845400	1273	#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
AnnaBridge	172:65be27845400	1274	#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
AnnaBridge	172:65be27845400	1275	#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
AnnaBridge	172:65be27845400	1276	#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
AnnaBridge	172:65be27845400	1277	#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
AnnaBridge	172:65be27845400	1278	#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
AnnaBridge	172:65be27845400	1279	#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
AnnaBridge	172:65be27845400	1280	#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
AnnaBridge	172:65be27845400	1281	#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
AnnaBridge	172:65be27845400	1282	#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
AnnaBridge	172:65be27845400	1283	#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
AnnaBridge	172:65be27845400	1284	#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
AnnaBridge	172:65be27845400	1285	#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
AnnaBridge	172:65be27845400	1286
AnnaBridge	172:65be27845400	1287	#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
AnnaBridge	172:65be27845400	1288	#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
AnnaBridge	172:65be27845400	1289	#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
AnnaBridge	172:65be27845400	1290	#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
AnnaBridge	172:65be27845400	1291	#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
AnnaBridge	172:65be27845400	1292	#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
AnnaBridge	172:65be27845400	1293	#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
AnnaBridge	172:65be27845400	1294
AnnaBridge	172:65be27845400	1295	#define CR_OFFSET_BB PWR_CR_OFFSET_BB
AnnaBridge	172:65be27845400	1296	#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
AnnaBridge	172:65be27845400	1297	#define PMODE_BIT_NUMBER VOS_BIT_NUMBER
AnnaBridge	172:65be27845400	1298	#define CR_PMODE_BB CR_VOS_BB
AnnaBridge	172:65be27845400	1299
AnnaBridge	172:65be27845400	1300	#define DBP_BitNumber DBP_BIT_NUMBER
AnnaBridge	172:65be27845400	1301	#define PVDE_BitNumber PVDE_BIT_NUMBER
AnnaBridge	172:65be27845400	1302	#define PMODE_BitNumber PMODE_BIT_NUMBER
AnnaBridge	172:65be27845400	1303	#define EWUP_BitNumber EWUP_BIT_NUMBER
AnnaBridge	172:65be27845400	1304	#define FPDS_BitNumber FPDS_BIT_NUMBER
AnnaBridge	172:65be27845400	1305	#define ODEN_BitNumber ODEN_BIT_NUMBER
AnnaBridge	172:65be27845400	1306	#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
AnnaBridge	172:65be27845400	1307	#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
AnnaBridge	172:65be27845400	1308	#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
AnnaBridge	172:65be27845400	1309	#define BRE_BitNumber BRE_BIT_NUMBER
AnnaBridge	172:65be27845400	1310
AnnaBridge	172:65be27845400	1311	#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
AnnaBridge	172:65be27845400	1312
AnnaBridge	172:65be27845400	1313	/**
AnnaBridge	172:65be27845400	1314	* @}
AnnaBridge	172:65be27845400	1315	*/
AnnaBridge	172:65be27845400	1316
AnnaBridge	172:65be27845400	1317	/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
AnnaBridge	172:65be27845400	1318	* @{
AnnaBridge	172:65be27845400	1319	*/
AnnaBridge	172:65be27845400	1320	#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
AnnaBridge	172:65be27845400	1321	#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
AnnaBridge	172:65be27845400	1322	#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
AnnaBridge	172:65be27845400	1323	/**
AnnaBridge	172:65be27845400	1324	* @}
AnnaBridge	172:65be27845400	1325	*/
AnnaBridge	172:65be27845400	1326
AnnaBridge	172:65be27845400	1327	/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
AnnaBridge	172:65be27845400	1328	* @{
AnnaBridge	172:65be27845400	1329	*/
AnnaBridge	172:65be27845400	1330	#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
AnnaBridge	172:65be27845400	1331	/**
AnnaBridge	172:65be27845400	1332	* @}
AnnaBridge	172:65be27845400	1333	*/
AnnaBridge	172:65be27845400	1334
AnnaBridge	172:65be27845400	1335	/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
AnnaBridge	172:65be27845400	1336	* @{
AnnaBridge	172:65be27845400	1337	*/
AnnaBridge	172:65be27845400	1338	#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
AnnaBridge	172:65be27845400	1339	#define HAL_TIM_DMAError TIM_DMAError
AnnaBridge	172:65be27845400	1340	#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
AnnaBridge	172:65be27845400	1341	#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
AnnaBridge	172:65be27845400	1342	#if defined(STM32H7) \|\| defined(STM32G0) \|\| defined(STM32F7) \|\| defined(STM32F4) \|\| defined(STM32L0)
AnnaBridge	172:65be27845400	1343	#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
AnnaBridge	172:65be27845400	1344	#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
AnnaBridge	172:65be27845400	1345	#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
AnnaBridge	172:65be27845400	1346	#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
AnnaBridge	172:65be27845400	1347	#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
AnnaBridge	172:65be27845400	1348	#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
AnnaBridge	172:65be27845400	1349	#endif /* STM32H7 \|\| STM32G0 \|\| STM32F7 \|\| STM32F4 \|\| STM32L0 */
AnnaBridge	172:65be27845400	1350	/**
AnnaBridge	172:65be27845400	1351	* @}
AnnaBridge	172:65be27845400	1352	*/
AnnaBridge	172:65be27845400	1353
AnnaBridge	172:65be27845400	1354	/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
AnnaBridge	172:65be27845400	1355	* @{
AnnaBridge	172:65be27845400	1356	*/
AnnaBridge	172:65be27845400	1357	#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
AnnaBridge	172:65be27845400	1358	/**
AnnaBridge	172:65be27845400	1359	* @}
AnnaBridge	172:65be27845400	1360	*/
AnnaBridge	172:65be27845400	1361
AnnaBridge	172:65be27845400	1362	/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
AnnaBridge	172:65be27845400	1363	* @{
AnnaBridge	172:65be27845400	1364	*/
AnnaBridge	172:65be27845400	1365	#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
AnnaBridge	172:65be27845400	1366	#define HAL_LTDC_Relaod HAL_LTDC_Reload
AnnaBridge	172:65be27845400	1367	#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig
AnnaBridge	172:65be27845400	1368	#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig
AnnaBridge	172:65be27845400	1369	/**
AnnaBridge	172:65be27845400	1370	* @}
AnnaBridge	172:65be27845400	1371	*/
AnnaBridge	172:65be27845400	1372
AnnaBridge	172:65be27845400	1373
AnnaBridge	172:65be27845400	1374	/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
AnnaBridge	172:65be27845400	1375	* @{
AnnaBridge	172:65be27845400	1376	*/
AnnaBridge	172:65be27845400	1377
AnnaBridge	172:65be27845400	1378	/**
AnnaBridge	172:65be27845400	1379	* @}
AnnaBridge	172:65be27845400	1380	*/
AnnaBridge	172:65be27845400	1381
AnnaBridge	172:65be27845400	1382	/* Exported macros ------------------------------------------------------------*/
AnnaBridge	172:65be27845400	1383
AnnaBridge	172:65be27845400	1384	/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
AnnaBridge	172:65be27845400	1385	* @{
AnnaBridge	172:65be27845400	1386	*/
AnnaBridge	172:65be27845400	1387	#define AES_IT_CC CRYP_IT_CC
AnnaBridge	172:65be27845400	1388	#define AES_IT_ERR CRYP_IT_ERR
AnnaBridge	172:65be27845400	1389	#define AES_FLAG_CCF CRYP_FLAG_CCF
AnnaBridge	172:65be27845400	1390	/**
AnnaBridge	172:65be27845400	1391	* @}
AnnaBridge	172:65be27845400	1392	*/
AnnaBridge	172:65be27845400	1393
AnnaBridge	172:65be27845400	1394	/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
AnnaBridge	172:65be27845400	1395	* @{
AnnaBridge	172:65be27845400	1396	*/
AnnaBridge	172:65be27845400	1397	#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
AnnaBridge	172:65be27845400	1398	#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
AnnaBridge	172:65be27845400	1399	#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
AnnaBridge	172:65be27845400	1400	#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
AnnaBridge	172:65be27845400	1401	#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
AnnaBridge	172:65be27845400	1402	#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
AnnaBridge	172:65be27845400	1403	#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
AnnaBridge	172:65be27845400	1404	#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
AnnaBridge	172:65be27845400	1405	#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
AnnaBridge	172:65be27845400	1406	#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
AnnaBridge	172:65be27845400	1407	#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
AnnaBridge	172:65be27845400	1408	#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
AnnaBridge	172:65be27845400	1409	#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
AnnaBridge	172:65be27845400	1410	#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
AnnaBridge	172:65be27845400	1411
AnnaBridge	172:65be27845400	1412	#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
AnnaBridge	172:65be27845400	1413	#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
AnnaBridge	172:65be27845400	1414	#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
AnnaBridge	172:65be27845400	1415	#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
AnnaBridge	172:65be27845400	1416	#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
AnnaBridge	172:65be27845400	1417
AnnaBridge	172:65be27845400	1418	/**
AnnaBridge	172:65be27845400	1419	* @}
AnnaBridge	172:65be27845400	1420	*/
AnnaBridge	172:65be27845400	1421
AnnaBridge	172:65be27845400	1422
AnnaBridge	172:65be27845400	1423	/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
AnnaBridge	172:65be27845400	1424	* @{
AnnaBridge	172:65be27845400	1425	*/
AnnaBridge	172:65be27845400	1426	#define __ADC_ENABLE __HAL_ADC_ENABLE
AnnaBridge	172:65be27845400	1427	#define __ADC_DISABLE __HAL_ADC_DISABLE
AnnaBridge	172:65be27845400	1428	#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
AnnaBridge	172:65be27845400	1429	#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
AnnaBridge	172:65be27845400	1430	#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
AnnaBridge	172:65be27845400	1431	#define __ADC_IS_ENABLED ADC_IS_ENABLE
AnnaBridge	172:65be27845400	1432	#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
AnnaBridge	172:65be27845400	1433	#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
AnnaBridge	172:65be27845400	1434	#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
AnnaBridge	172:65be27845400	1435	#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
AnnaBridge	172:65be27845400	1436	#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
AnnaBridge	172:65be27845400	1437	#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
AnnaBridge	172:65be27845400	1438	#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
AnnaBridge	172:65be27845400	1439
AnnaBridge	172:65be27845400	1440	#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
AnnaBridge	172:65be27845400	1441	#define __HAL_ADC_JSQR_RK ADC_JSQR_RK
AnnaBridge	172:65be27845400	1442	#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
AnnaBridge	172:65be27845400	1443	#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
AnnaBridge	172:65be27845400	1444	#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
AnnaBridge	172:65be27845400	1445	#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
AnnaBridge	172:65be27845400	1446	#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
AnnaBridge	172:65be27845400	1447	#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
AnnaBridge	172:65be27845400	1448	#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
AnnaBridge	172:65be27845400	1449	#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
AnnaBridge	172:65be27845400	1450	#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
AnnaBridge	172:65be27845400	1451	#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
AnnaBridge	172:65be27845400	1452	#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
AnnaBridge	172:65be27845400	1453	#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
AnnaBridge	172:65be27845400	1454	#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
AnnaBridge	172:65be27845400	1455	#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
AnnaBridge	172:65be27845400	1456	#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
AnnaBridge	172:65be27845400	1457	#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
AnnaBridge	172:65be27845400	1458	#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
AnnaBridge	172:65be27845400	1459	#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
AnnaBridge	172:65be27845400	1460
AnnaBridge	172:65be27845400	1461	#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
AnnaBridge	172:65be27845400	1462	#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
AnnaBridge	172:65be27845400	1463	#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
AnnaBridge	172:65be27845400	1464	#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
AnnaBridge	172:65be27845400	1465	#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
AnnaBridge	172:65be27845400	1466	#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
AnnaBridge	172:65be27845400	1467	#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
AnnaBridge	172:65be27845400	1468	#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
AnnaBridge	172:65be27845400	1469	#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
AnnaBridge	172:65be27845400	1470	#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
AnnaBridge	172:65be27845400	1471
AnnaBridge	172:65be27845400	1472	#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
AnnaBridge	172:65be27845400	1473	#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
AnnaBridge	172:65be27845400	1474	#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
AnnaBridge	172:65be27845400	1475	#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
AnnaBridge	172:65be27845400	1476	#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
AnnaBridge	172:65be27845400	1477	#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
AnnaBridge	172:65be27845400	1478	#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
AnnaBridge	172:65be27845400	1479	#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
AnnaBridge	172:65be27845400	1480
AnnaBridge	172:65be27845400	1481	#define __HAL_ADC_SQR1 ADC_SQR1
AnnaBridge	172:65be27845400	1482	#define __HAL_ADC_SMPR1 ADC_SMPR1
AnnaBridge	172:65be27845400	1483	#define __HAL_ADC_SMPR2 ADC_SMPR2
AnnaBridge	172:65be27845400	1484	#define __HAL_ADC_SQR3_RK ADC_SQR3_RK
AnnaBridge	172:65be27845400	1485	#define __HAL_ADC_SQR2_RK ADC_SQR2_RK
AnnaBridge	172:65be27845400	1486	#define __HAL_ADC_SQR1_RK ADC_SQR1_RK
AnnaBridge	172:65be27845400	1487	#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
AnnaBridge	172:65be27845400	1488	#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
AnnaBridge	172:65be27845400	1489	#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
AnnaBridge	172:65be27845400	1490	#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
AnnaBridge	172:65be27845400	1491	#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
AnnaBridge	172:65be27845400	1492	#define __HAL_ADC_JSQR ADC_JSQR
AnnaBridge	172:65be27845400	1493
AnnaBridge	172:65be27845400	1494	#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
AnnaBridge	172:65be27845400	1495	#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
AnnaBridge	172:65be27845400	1496	#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
AnnaBridge	172:65be27845400	1497	#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
AnnaBridge	172:65be27845400	1498	#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
AnnaBridge	172:65be27845400	1499	#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
AnnaBridge	172:65be27845400	1500	#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
AnnaBridge	172:65be27845400	1501	#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
AnnaBridge	172:65be27845400	1502
AnnaBridge	172:65be27845400	1503	/**
AnnaBridge	172:65be27845400	1504	* @}
AnnaBridge	172:65be27845400	1505	*/
AnnaBridge	172:65be27845400	1506
AnnaBridge	172:65be27845400	1507	/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
AnnaBridge	172:65be27845400	1508	* @{
AnnaBridge	172:65be27845400	1509	*/
AnnaBridge	172:65be27845400	1510	#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
AnnaBridge	172:65be27845400	1511	#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
AnnaBridge	172:65be27845400	1512	#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
AnnaBridge	172:65be27845400	1513	#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
AnnaBridge	172:65be27845400	1514
AnnaBridge	172:65be27845400	1515	/**
AnnaBridge	172:65be27845400	1516	* @}
AnnaBridge	172:65be27845400	1517	*/
AnnaBridge	172:65be27845400	1518
AnnaBridge	172:65be27845400	1519	/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
AnnaBridge	172:65be27845400	1520	* @{
AnnaBridge	172:65be27845400	1521	*/
AnnaBridge	172:65be27845400	1522	#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
AnnaBridge	172:65be27845400	1523	#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
AnnaBridge	172:65be27845400	1524	#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
AnnaBridge	172:65be27845400	1525	#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
AnnaBridge	172:65be27845400	1526	#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
AnnaBridge	172:65be27845400	1527	#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
AnnaBridge	172:65be27845400	1528	#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
AnnaBridge	172:65be27845400	1529	#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
AnnaBridge	172:65be27845400	1530	#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
AnnaBridge	172:65be27845400	1531	#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
AnnaBridge	172:65be27845400	1532	#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
AnnaBridge	172:65be27845400	1533	#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
AnnaBridge	172:65be27845400	1534	#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
AnnaBridge	172:65be27845400	1535	#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
AnnaBridge	172:65be27845400	1536	#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
AnnaBridge	172:65be27845400	1537	#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
AnnaBridge	172:65be27845400	1538
AnnaBridge	172:65be27845400	1539	#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
AnnaBridge	172:65be27845400	1540	#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
AnnaBridge	172:65be27845400	1541	#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
AnnaBridge	172:65be27845400	1542	#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
AnnaBridge	172:65be27845400	1543	#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
AnnaBridge	172:65be27845400	1544	#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
AnnaBridge	172:65be27845400	1545	#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
AnnaBridge	172:65be27845400	1546	#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
AnnaBridge	172:65be27845400	1547	#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
AnnaBridge	172:65be27845400	1548	#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
AnnaBridge	172:65be27845400	1549	#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
AnnaBridge	172:65be27845400	1550	#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
AnnaBridge	172:65be27845400	1551	#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
AnnaBridge	172:65be27845400	1552	#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
AnnaBridge	172:65be27845400	1553
AnnaBridge	172:65be27845400	1554
AnnaBridge	172:65be27845400	1555	#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
AnnaBridge	172:65be27845400	1556	#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
AnnaBridge	172:65be27845400	1557	#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
AnnaBridge	172:65be27845400	1558	#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
AnnaBridge	172:65be27845400	1559	#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
AnnaBridge	172:65be27845400	1560	#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
AnnaBridge	172:65be27845400	1561	#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
AnnaBridge	172:65be27845400	1562	#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
AnnaBridge	172:65be27845400	1563	#if defined(STM32H7)
AnnaBridge	172:65be27845400	1564	#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
AnnaBridge	172:65be27845400	1565	#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
AnnaBridge	172:65be27845400	1566	#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
AnnaBridge	172:65be27845400	1567	#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
AnnaBridge	172:65be27845400	1568	#else
AnnaBridge	172:65be27845400	1569	#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
AnnaBridge	172:65be27845400	1570	#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
AnnaBridge	172:65be27845400	1571	#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
AnnaBridge	172:65be27845400	1572	#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
AnnaBridge	172:65be27845400	1573	#endif /* STM32H7 */
AnnaBridge	172:65be27845400	1574	#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
AnnaBridge	172:65be27845400	1575	#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
AnnaBridge	172:65be27845400	1576	#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
AnnaBridge	172:65be27845400	1577	#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
AnnaBridge	172:65be27845400	1578	#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
AnnaBridge	172:65be27845400	1579	#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
AnnaBridge	172:65be27845400	1580	#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
AnnaBridge	172:65be27845400	1581	#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
AnnaBridge	172:65be27845400	1582	#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
AnnaBridge	172:65be27845400	1583	#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
AnnaBridge	172:65be27845400	1584	#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
AnnaBridge	172:65be27845400	1585	#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
AnnaBridge	172:65be27845400	1586
AnnaBridge	172:65be27845400	1587	/**
AnnaBridge	172:65be27845400	1588	* @}
AnnaBridge	172:65be27845400	1589	*/
AnnaBridge	172:65be27845400	1590
AnnaBridge	172:65be27845400	1591	/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
AnnaBridge	172:65be27845400	1592	* @{
AnnaBridge	172:65be27845400	1593	*/
AnnaBridge	172:65be27845400	1594	#if defined(STM32F3)
AnnaBridge	172:65be27845400	1595	#define COMP_START __HAL_COMP_ENABLE
AnnaBridge	172:65be27845400	1596	#define COMP_STOP __HAL_COMP_DISABLE
AnnaBridge	172:65be27845400	1597	#define COMP_LOCK __HAL_COMP_LOCK
AnnaBridge	172:65be27845400	1598
AnnaBridge	172:65be27845400	1599	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx) \|\| defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
AnnaBridge	172:65be27845400	1600	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge	172:65be27845400	1601	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge	172:65be27845400	1602	__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
AnnaBridge	172:65be27845400	1603	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge	172:65be27845400	1604	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge	172:65be27845400	1605	__HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
AnnaBridge	172:65be27845400	1606	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge	172:65be27845400	1607	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge	172:65be27845400	1608	__HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
AnnaBridge	172:65be27845400	1609	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge	172:65be27845400	1610	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge	172:65be27845400	1611	__HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
AnnaBridge	172:65be27845400	1612	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
AnnaBridge	172:65be27845400	1613	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
AnnaBridge	172:65be27845400	1614	__HAL_COMP_COMP6_EXTI_ENABLE_IT())
AnnaBridge	172:65be27845400	1615	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
AnnaBridge	172:65be27845400	1616	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
AnnaBridge	172:65be27845400	1617	__HAL_COMP_COMP6_EXTI_DISABLE_IT())
AnnaBridge	172:65be27845400	1618	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
AnnaBridge	172:65be27845400	1619	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
AnnaBridge	172:65be27845400	1620	__HAL_COMP_COMP6_EXTI_GET_FLAG())
AnnaBridge	172:65be27845400	1621	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
AnnaBridge	172:65be27845400	1622	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
AnnaBridge	172:65be27845400	1623	__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
AnnaBridge	172:65be27845400	1624	# endif
AnnaBridge	172:65be27845400	1625	# if defined(STM32F302xE) \|\| defined(STM32F302xC)
AnnaBridge	172:65be27845400	1626	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge	172:65be27845400	1627	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge	172:65be27845400	1628	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge	172:65be27845400	1629	__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
AnnaBridge	172:65be27845400	1630	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge	172:65be27845400	1631	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge	172:65be27845400	1632	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge	172:65be27845400	1633	__HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
AnnaBridge	172:65be27845400	1634	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge	172:65be27845400	1635	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge	172:65be27845400	1636	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge	172:65be27845400	1637	__HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
AnnaBridge	172:65be27845400	1638	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge	172:65be27845400	1639	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge	172:65be27845400	1640	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge	172:65be27845400	1641	__HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
AnnaBridge	172:65be27845400	1642	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
AnnaBridge	172:65be27845400	1643	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
AnnaBridge	172:65be27845400	1644	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
AnnaBridge	172:65be27845400	1645	__HAL_COMP_COMP6_EXTI_ENABLE_IT())
AnnaBridge	172:65be27845400	1646	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
AnnaBridge	172:65be27845400	1647	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
AnnaBridge	172:65be27845400	1648	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
AnnaBridge	172:65be27845400	1649	__HAL_COMP_COMP6_EXTI_DISABLE_IT())
AnnaBridge	172:65be27845400	1650	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
AnnaBridge	172:65be27845400	1651	((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
AnnaBridge	172:65be27845400	1652	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
AnnaBridge	172:65be27845400	1653	__HAL_COMP_COMP6_EXTI_GET_FLAG())
AnnaBridge	172:65be27845400	1654	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
AnnaBridge	172:65be27845400	1655	((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
AnnaBridge	172:65be27845400	1656	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
AnnaBridge	172:65be27845400	1657	__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
AnnaBridge	172:65be27845400	1658	# endif
AnnaBridge	172:65be27845400	1659	# if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
AnnaBridge	172:65be27845400	1660	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge	172:65be27845400	1661	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge	172:65be27845400	1662	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge	172:65be27845400	1663	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge	172:65be27845400	1664	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge	172:65be27845400	1665	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge	172:65be27845400	1666	__HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
AnnaBridge	172:65be27845400	1667	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge	172:65be27845400	1668	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge	172:65be27845400	1669	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge	172:65be27845400	1670	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge	172:65be27845400	1671	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge	172:65be27845400	1672	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge	172:65be27845400	1673	__HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
AnnaBridge	172:65be27845400	1674	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge	172:65be27845400	1675	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge	172:65be27845400	1676	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge	172:65be27845400	1677	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge	172:65be27845400	1678	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge	172:65be27845400	1679	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge	172:65be27845400	1680	__HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
AnnaBridge	172:65be27845400	1681	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge	172:65be27845400	1682	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge	172:65be27845400	1683	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge	172:65be27845400	1684	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge	172:65be27845400	1685	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge	172:65be27845400	1686	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge	172:65be27845400	1687	__HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
AnnaBridge	172:65be27845400	1688	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
AnnaBridge	172:65be27845400	1689	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
AnnaBridge	172:65be27845400	1690	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
AnnaBridge	172:65be27845400	1691	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
AnnaBridge	172:65be27845400	1692	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
AnnaBridge	172:65be27845400	1693	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
AnnaBridge	172:65be27845400	1694	__HAL_COMP_COMP7_EXTI_ENABLE_IT())
AnnaBridge	172:65be27845400	1695	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
AnnaBridge	172:65be27845400	1696	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
AnnaBridge	172:65be27845400	1697	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
AnnaBridge	172:65be27845400	1698	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
AnnaBridge	172:65be27845400	1699	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
AnnaBridge	172:65be27845400	1700	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
AnnaBridge	172:65be27845400	1701	__HAL_COMP_COMP7_EXTI_DISABLE_IT())
AnnaBridge	172:65be27845400	1702	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
AnnaBridge	172:65be27845400	1703	((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
AnnaBridge	172:65be27845400	1704	((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
AnnaBridge	172:65be27845400	1705	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
AnnaBridge	172:65be27845400	1706	((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
AnnaBridge	172:65be27845400	1707	((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
AnnaBridge	172:65be27845400	1708	__HAL_COMP_COMP7_EXTI_GET_FLAG())
AnnaBridge	172:65be27845400	1709	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
AnnaBridge	172:65be27845400	1710	((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
AnnaBridge	172:65be27845400	1711	((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
AnnaBridge	172:65be27845400	1712	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
AnnaBridge	172:65be27845400	1713	((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
AnnaBridge	172:65be27845400	1714	((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
AnnaBridge	172:65be27845400	1715	__HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
AnnaBridge	172:65be27845400	1716	# endif
AnnaBridge	172:65be27845400	1717	# if defined(STM32F373xC) \|\|defined(STM32F378xx)
AnnaBridge	172:65be27845400	1718	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge	172:65be27845400	1719	__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
AnnaBridge	172:65be27845400	1720	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge	172:65be27845400	1721	__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
AnnaBridge	172:65be27845400	1722	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge	172:65be27845400	1723	__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
AnnaBridge	172:65be27845400	1724	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge	172:65be27845400	1725	__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
AnnaBridge	172:65be27845400	1726	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
AnnaBridge	172:65be27845400	1727	__HAL_COMP_COMP2_EXTI_ENABLE_IT())
AnnaBridge	172:65be27845400	1728	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
AnnaBridge	172:65be27845400	1729	__HAL_COMP_COMP2_EXTI_DISABLE_IT())
AnnaBridge	172:65be27845400	1730	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
AnnaBridge	172:65be27845400	1731	__HAL_COMP_COMP2_EXTI_GET_FLAG())
AnnaBridge	172:65be27845400	1732	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
AnnaBridge	172:65be27845400	1733	__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
AnnaBridge	172:65be27845400	1734	# endif
AnnaBridge	172:65be27845400	1735	#else
AnnaBridge	172:65be27845400	1736	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
AnnaBridge	172:65be27845400	1737	__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
AnnaBridge	172:65be27845400	1738	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
AnnaBridge	172:65be27845400	1739	__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
AnnaBridge	172:65be27845400	1740	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
AnnaBridge	172:65be27845400	1741	__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
AnnaBridge	172:65be27845400	1742	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
AnnaBridge	172:65be27845400	1743	__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
AnnaBridge	172:65be27845400	1744	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
AnnaBridge	172:65be27845400	1745	__HAL_COMP_COMP2_EXTI_ENABLE_IT())
AnnaBridge	172:65be27845400	1746	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
AnnaBridge	172:65be27845400	1747	__HAL_COMP_COMP2_EXTI_DISABLE_IT())
AnnaBridge	172:65be27845400	1748	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
AnnaBridge	172:65be27845400	1749	__HAL_COMP_COMP2_EXTI_GET_FLAG())
AnnaBridge	172:65be27845400	1750	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
AnnaBridge	172:65be27845400	1751	__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
AnnaBridge	172:65be27845400	1752	#endif
AnnaBridge	172:65be27845400	1753
AnnaBridge	172:65be27845400	1754	#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
AnnaBridge	172:65be27845400	1755
AnnaBridge	172:65be27845400	1756	#if defined(STM32L0) \|\| defined(STM32L4)
AnnaBridge	172:65be27845400	1757	/* Note: On these STM32 families, the only argument of this macro */
AnnaBridge	172:65be27845400	1758	/* is COMP_FLAG_LOCK. */
AnnaBridge	172:65be27845400	1759	/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
AnnaBridge	172:65be27845400	1760	/* argument. */
AnnaBridge	172:65be27845400	1761	#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
AnnaBridge	172:65be27845400	1762	#endif
AnnaBridge	172:65be27845400	1763	/**
AnnaBridge	172:65be27845400	1764	* @}
AnnaBridge	172:65be27845400	1765	*/
AnnaBridge	172:65be27845400	1766
AnnaBridge	172:65be27845400	1767	#if defined(STM32L0) \|\| defined(STM32L4)
AnnaBridge	172:65be27845400	1768	/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
AnnaBridge	172:65be27845400	1769	* @{
AnnaBridge	172:65be27845400	1770	*/
AnnaBridge	172:65be27845400	1771	#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
AnnaBridge	172:65be27845400	1772	#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
AnnaBridge	172:65be27845400	1773	/**
AnnaBridge	172:65be27845400	1774	* @}
AnnaBridge	172:65be27845400	1775	*/
AnnaBridge	172:65be27845400	1776	#endif
AnnaBridge	172:65be27845400	1777
AnnaBridge	172:65be27845400	1778	/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
AnnaBridge	172:65be27845400	1779	* @{
AnnaBridge	172:65be27845400	1780	*/
AnnaBridge	172:65be27845400	1781
AnnaBridge	172:65be27845400	1782	#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) \|\| \
AnnaBridge	172:65be27845400	1783	((WAVE) == DAC_WAVE_NOISE)\|\| \
AnnaBridge	172:65be27845400	1784	((WAVE) == DAC_WAVE_TRIANGLE))
AnnaBridge	172:65be27845400	1785
AnnaBridge	172:65be27845400	1786	/**
AnnaBridge	172:65be27845400	1787	* @}
AnnaBridge	172:65be27845400	1788	*/
AnnaBridge	172:65be27845400	1789
AnnaBridge	172:65be27845400	1790	/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
AnnaBridge	172:65be27845400	1791	* @{
AnnaBridge	172:65be27845400	1792	*/
AnnaBridge	172:65be27845400	1793
AnnaBridge	172:65be27845400	1794	#define IS_WRPAREA IS_OB_WRPAREA
AnnaBridge	172:65be27845400	1795	#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
AnnaBridge	172:65be27845400	1796	#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
AnnaBridge	172:65be27845400	1797	#define IS_TYPEERASE IS_FLASH_TYPEERASE
AnnaBridge	172:65be27845400	1798	#define IS_NBSECTORS IS_FLASH_NBSECTORS
AnnaBridge	172:65be27845400	1799	#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
AnnaBridge	172:65be27845400	1800
AnnaBridge	172:65be27845400	1801	/**
AnnaBridge	172:65be27845400	1802	* @}
AnnaBridge	172:65be27845400	1803	*/
AnnaBridge	172:65be27845400	1804
AnnaBridge	172:65be27845400	1805	/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
AnnaBridge	172:65be27845400	1806	* @{
AnnaBridge	172:65be27845400	1807	*/
AnnaBridge	172:65be27845400	1808
AnnaBridge	172:65be27845400	1809	#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
AnnaBridge	172:65be27845400	1810	#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
AnnaBridge	172:65be27845400	1811	#if defined(STM32F1)
AnnaBridge	172:65be27845400	1812	#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE
AnnaBridge	172:65be27845400	1813	#else
AnnaBridge	172:65be27845400	1814	#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
AnnaBridge	172:65be27845400	1815	#endif /* STM32F1 */
AnnaBridge	172:65be27845400	1816	#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
AnnaBridge	172:65be27845400	1817	#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
AnnaBridge	172:65be27845400	1818	#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
AnnaBridge	172:65be27845400	1819	#define __HAL_I2C_SPEED I2C_SPEED
AnnaBridge	172:65be27845400	1820	#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
AnnaBridge	172:65be27845400	1821	#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
AnnaBridge	172:65be27845400	1822	#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
AnnaBridge	172:65be27845400	1823	#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
AnnaBridge	172:65be27845400	1824	#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
AnnaBridge	172:65be27845400	1825	#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
AnnaBridge	172:65be27845400	1826	#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
AnnaBridge	172:65be27845400	1827	#define __HAL_I2C_FREQRANGE I2C_FREQRANGE
AnnaBridge	172:65be27845400	1828	/**
AnnaBridge	172:65be27845400	1829	* @}
AnnaBridge	172:65be27845400	1830	*/
AnnaBridge	172:65be27845400	1831
AnnaBridge	172:65be27845400	1832	/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
AnnaBridge	172:65be27845400	1833	* @{
AnnaBridge	172:65be27845400	1834	*/
AnnaBridge	172:65be27845400	1835
AnnaBridge	172:65be27845400	1836	#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
AnnaBridge	172:65be27845400	1837	#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
AnnaBridge	172:65be27845400	1838
AnnaBridge	172:65be27845400	1839	#if defined(STM32H7)
AnnaBridge	172:65be27845400	1840	#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
AnnaBridge	172:65be27845400	1841	#endif
AnnaBridge	172:65be27845400	1842
AnnaBridge	172:65be27845400	1843	/**
AnnaBridge	172:65be27845400	1844	* @}
AnnaBridge	172:65be27845400	1845	*/
AnnaBridge	172:65be27845400	1846
AnnaBridge	172:65be27845400	1847	/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
AnnaBridge	172:65be27845400	1848	* @{
AnnaBridge	172:65be27845400	1849	*/
AnnaBridge	172:65be27845400	1850
AnnaBridge	172:65be27845400	1851	#define __IRDA_DISABLE __HAL_IRDA_DISABLE
AnnaBridge	172:65be27845400	1852	#define __IRDA_ENABLE __HAL_IRDA_ENABLE
AnnaBridge	172:65be27845400	1853
AnnaBridge	172:65be27845400	1854	#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
AnnaBridge	172:65be27845400	1855	#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
AnnaBridge	172:65be27845400	1856	#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
AnnaBridge	172:65be27845400	1857	#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
AnnaBridge	172:65be27845400	1858
AnnaBridge	172:65be27845400	1859	#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
AnnaBridge	172:65be27845400	1860
AnnaBridge	172:65be27845400	1861
AnnaBridge	172:65be27845400	1862	/**
AnnaBridge	172:65be27845400	1863	* @}
AnnaBridge	172:65be27845400	1864	*/
AnnaBridge	172:65be27845400	1865
AnnaBridge	172:65be27845400	1866
AnnaBridge	172:65be27845400	1867	/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
AnnaBridge	172:65be27845400	1868	* @{
AnnaBridge	172:65be27845400	1869	*/
AnnaBridge	172:65be27845400	1870	#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
AnnaBridge	172:65be27845400	1871	#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
AnnaBridge	172:65be27845400	1872	/**
AnnaBridge	172:65be27845400	1873	* @}
AnnaBridge	172:65be27845400	1874	*/
AnnaBridge	172:65be27845400	1875
AnnaBridge	172:65be27845400	1876
AnnaBridge	172:65be27845400	1877	/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
AnnaBridge	172:65be27845400	1878	* @{
AnnaBridge	172:65be27845400	1879	*/
AnnaBridge	172:65be27845400	1880
AnnaBridge	172:65be27845400	1881	#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
AnnaBridge	172:65be27845400	1882	#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
AnnaBridge	172:65be27845400	1883	#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
AnnaBridge	172:65be27845400	1884
AnnaBridge	172:65be27845400	1885	/**
AnnaBridge	172:65be27845400	1886	* @}
AnnaBridge	172:65be27845400	1887	*/
AnnaBridge	172:65be27845400	1888
AnnaBridge	172:65be27845400	1889
AnnaBridge	172:65be27845400	1890	/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
AnnaBridge	172:65be27845400	1891	* @{
AnnaBridge	172:65be27845400	1892	*/
AnnaBridge	172:65be27845400	1893	#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
AnnaBridge	172:65be27845400	1894	#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
AnnaBridge	172:65be27845400	1895	#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
AnnaBridge	172:65be27845400	1896	#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
AnnaBridge	172:65be27845400	1897	#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
AnnaBridge	172:65be27845400	1898	#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
AnnaBridge	172:65be27845400	1899	#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
AnnaBridge	172:65be27845400	1900	#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
AnnaBridge	172:65be27845400	1901	#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
AnnaBridge	172:65be27845400	1902	#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
AnnaBridge	172:65be27845400	1903	#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
AnnaBridge	172:65be27845400	1904	#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
AnnaBridge	172:65be27845400	1905	#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
AnnaBridge	172:65be27845400	1906
AnnaBridge	172:65be27845400	1907	/**
AnnaBridge	172:65be27845400	1908	* @}
AnnaBridge	172:65be27845400	1909	*/
AnnaBridge	172:65be27845400	1910
AnnaBridge	172:65be27845400	1911
AnnaBridge	172:65be27845400	1912	/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
AnnaBridge	172:65be27845400	1913	* @{
AnnaBridge	172:65be27845400	1914	*/
AnnaBridge	172:65be27845400	1915	#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
AnnaBridge	172:65be27845400	1916	#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
AnnaBridge	172:65be27845400	1917	#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
AnnaBridge	172:65be27845400	1918	#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
AnnaBridge	172:65be27845400	1919	#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
AnnaBridge	172:65be27845400	1920	#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
AnnaBridge	172:65be27845400	1921	#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
AnnaBridge	172:65be27845400	1922	#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
AnnaBridge	172:65be27845400	1923	#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
AnnaBridge	172:65be27845400	1924	#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
AnnaBridge	172:65be27845400	1925	#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
AnnaBridge	172:65be27845400	1926	#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
AnnaBridge	172:65be27845400	1927	#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
AnnaBridge	172:65be27845400	1928	#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
AnnaBridge	172:65be27845400	1929	#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
AnnaBridge	172:65be27845400	1930	#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
AnnaBridge	172:65be27845400	1931	#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
AnnaBridge	172:65be27845400	1932	#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
AnnaBridge	172:65be27845400	1933	#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
AnnaBridge	172:65be27845400	1934	#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
AnnaBridge	172:65be27845400	1935	#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
AnnaBridge	172:65be27845400	1936	#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
AnnaBridge	172:65be27845400	1937	#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
AnnaBridge	172:65be27845400	1938	#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
AnnaBridge	172:65be27845400	1939	#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
AnnaBridge	172:65be27845400	1940	#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
AnnaBridge	172:65be27845400	1941	#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
AnnaBridge	172:65be27845400	1942	#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
AnnaBridge	172:65be27845400	1943	#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
AnnaBridge	172:65be27845400	1944	#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
AnnaBridge	172:65be27845400	1945	#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
AnnaBridge	172:65be27845400	1946	#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
AnnaBridge	172:65be27845400	1947	#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
AnnaBridge	172:65be27845400	1948	#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
AnnaBridge	172:65be27845400	1949	#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
AnnaBridge	172:65be27845400	1950
AnnaBridge	172:65be27845400	1951	#if defined (STM32F4)
AnnaBridge	172:65be27845400	1952	#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
AnnaBridge	172:65be27845400	1953	#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
AnnaBridge	172:65be27845400	1954	#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
AnnaBridge	172:65be27845400	1955	#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
AnnaBridge	172:65be27845400	1956	#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
AnnaBridge	172:65be27845400	1957	#else
AnnaBridge	172:65be27845400	1958	#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
AnnaBridge	172:65be27845400	1959	#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
AnnaBridge	172:65be27845400	1960	#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
AnnaBridge	172:65be27845400	1961	#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
AnnaBridge	172:65be27845400	1962	#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
AnnaBridge	172:65be27845400	1963	#endif /* STM32F4 */
AnnaBridge	172:65be27845400	1964	/**
AnnaBridge	172:65be27845400	1965	* @}
AnnaBridge	172:65be27845400	1966	*/
AnnaBridge	172:65be27845400	1967
AnnaBridge	172:65be27845400	1968
AnnaBridge	172:65be27845400	1969	/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
AnnaBridge	172:65be27845400	1970	* @{
AnnaBridge	172:65be27845400	1971	*/
AnnaBridge	172:65be27845400	1972
AnnaBridge	172:65be27845400	1973	#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
AnnaBridge	172:65be27845400	1974	#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
AnnaBridge	172:65be27845400	1975
AnnaBridge	172:65be27845400	1976	#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
AnnaBridge	172:65be27845400	1977	#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
AnnaBridge	172:65be27845400	1978
AnnaBridge	172:65be27845400	1979	#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
AnnaBridge	172:65be27845400	1980	#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
AnnaBridge	172:65be27845400	1981	#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	1982	#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	1983	#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
AnnaBridge	172:65be27845400	1984	#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
AnnaBridge	172:65be27845400	1985	#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
AnnaBridge	172:65be27845400	1986	#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
AnnaBridge	172:65be27845400	1987	#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
AnnaBridge	172:65be27845400	1988	#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
AnnaBridge	172:65be27845400	1989	#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	1990	#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	1991	#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
AnnaBridge	172:65be27845400	1992	#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
AnnaBridge	172:65be27845400	1993	#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
AnnaBridge	172:65be27845400	1994	#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
AnnaBridge	172:65be27845400	1995	#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
AnnaBridge	172:65be27845400	1996	#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
AnnaBridge	172:65be27845400	1997	#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
AnnaBridge	172:65be27845400	1998	#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
AnnaBridge	172:65be27845400	1999	#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
AnnaBridge	172:65be27845400	2000	#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
AnnaBridge	172:65be27845400	2001	#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2002	#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2003	#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
AnnaBridge	172:65be27845400	2004	#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
AnnaBridge	172:65be27845400	2005	#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2006	#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2007	#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
AnnaBridge	172:65be27845400	2008	#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
AnnaBridge	172:65be27845400	2009	#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
AnnaBridge	172:65be27845400	2010	#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
AnnaBridge	172:65be27845400	2011	#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
AnnaBridge	172:65be27845400	2012	#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
AnnaBridge	172:65be27845400	2013	#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
AnnaBridge	172:65be27845400	2014	#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
AnnaBridge	172:65be27845400	2015	#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
AnnaBridge	172:65be27845400	2016	#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
AnnaBridge	172:65be27845400	2017	#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
AnnaBridge	172:65be27845400	2018	#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
AnnaBridge	172:65be27845400	2019	#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
AnnaBridge	172:65be27845400	2020	#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
AnnaBridge	172:65be27845400	2021	#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
AnnaBridge	172:65be27845400	2022	#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
AnnaBridge	172:65be27845400	2023	#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
AnnaBridge	172:65be27845400	2024	#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
AnnaBridge	172:65be27845400	2025	#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
AnnaBridge	172:65be27845400	2026	#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
AnnaBridge	172:65be27845400	2027	#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
AnnaBridge	172:65be27845400	2028	#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
AnnaBridge	172:65be27845400	2029	#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
AnnaBridge	172:65be27845400	2030	#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
AnnaBridge	172:65be27845400	2031	#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
AnnaBridge	172:65be27845400	2032	#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
AnnaBridge	172:65be27845400	2033	#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2034	#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2035	#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
AnnaBridge	172:65be27845400	2036	#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
AnnaBridge	172:65be27845400	2037	#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
AnnaBridge	172:65be27845400	2038	#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
AnnaBridge	172:65be27845400	2039	#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
AnnaBridge	172:65be27845400	2040	#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
AnnaBridge	172:65be27845400	2041	#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
AnnaBridge	172:65be27845400	2042	#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
AnnaBridge	172:65be27845400	2043	#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
AnnaBridge	172:65be27845400	2044	#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
AnnaBridge	172:65be27845400	2045	#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
AnnaBridge	172:65be27845400	2046	#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
AnnaBridge	172:65be27845400	2047	#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
AnnaBridge	172:65be27845400	2048	#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
AnnaBridge	172:65be27845400	2049	#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
AnnaBridge	172:65be27845400	2050	#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
AnnaBridge	172:65be27845400	2051	#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2052	#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2053	#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
AnnaBridge	172:65be27845400	2054	#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
AnnaBridge	172:65be27845400	2055	#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
AnnaBridge	172:65be27845400	2056	#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
AnnaBridge	172:65be27845400	2057	#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2058	#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2059	#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
AnnaBridge	172:65be27845400	2060	#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
AnnaBridge	172:65be27845400	2061	#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
AnnaBridge	172:65be27845400	2062	#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
AnnaBridge	172:65be27845400	2063	#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
AnnaBridge	172:65be27845400	2064	#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
AnnaBridge	172:65be27845400	2065	#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
AnnaBridge	172:65be27845400	2066	#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
AnnaBridge	172:65be27845400	2067	#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2068	#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2069	#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
AnnaBridge	172:65be27845400	2070	#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
AnnaBridge	172:65be27845400	2071	#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
AnnaBridge	172:65be27845400	2072	#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
AnnaBridge	172:65be27845400	2073	#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
AnnaBridge	172:65be27845400	2074	#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
AnnaBridge	172:65be27845400	2075	#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
AnnaBridge	172:65be27845400	2076	#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
AnnaBridge	172:65be27845400	2077	#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2078	#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2079	#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
AnnaBridge	172:65be27845400	2080	#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
AnnaBridge	172:65be27845400	2081	#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
AnnaBridge	172:65be27845400	2082	#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
AnnaBridge	172:65be27845400	2083	#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2084	#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2085	#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
AnnaBridge	172:65be27845400	2086	#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
AnnaBridge	172:65be27845400	2087	#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
AnnaBridge	172:65be27845400	2088	#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
AnnaBridge	172:65be27845400	2089	#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2090	#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2091	#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
AnnaBridge	172:65be27845400	2092	#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
AnnaBridge	172:65be27845400	2093	#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
AnnaBridge	172:65be27845400	2094	#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
AnnaBridge	172:65be27845400	2095	#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
AnnaBridge	172:65be27845400	2096	#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
AnnaBridge	172:65be27845400	2097	#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
AnnaBridge	172:65be27845400	2098	#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
AnnaBridge	172:65be27845400	2099	#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
AnnaBridge	172:65be27845400	2100	#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
AnnaBridge	172:65be27845400	2101	#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
AnnaBridge	172:65be27845400	2102	#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
AnnaBridge	172:65be27845400	2103	#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
AnnaBridge	172:65be27845400	2104	#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
AnnaBridge	172:65be27845400	2105	#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2106	#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2107	#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
AnnaBridge	172:65be27845400	2108	#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
AnnaBridge	172:65be27845400	2109	#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
AnnaBridge	172:65be27845400	2110	#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
AnnaBridge	172:65be27845400	2111	#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
AnnaBridge	172:65be27845400	2112	#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
AnnaBridge	172:65be27845400	2113	#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2114	#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2115	#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
AnnaBridge	172:65be27845400	2116	#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
AnnaBridge	172:65be27845400	2117	#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2118	#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2119	#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
AnnaBridge	172:65be27845400	2120	#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
AnnaBridge	172:65be27845400	2121	#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
AnnaBridge	172:65be27845400	2122	#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
AnnaBridge	172:65be27845400	2123	#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
AnnaBridge	172:65be27845400	2124	#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
AnnaBridge	172:65be27845400	2125	#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2126	#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2127	#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
AnnaBridge	172:65be27845400	2128	#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
AnnaBridge	172:65be27845400	2129	#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
AnnaBridge	172:65be27845400	2130	#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
AnnaBridge	172:65be27845400	2131	#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2132	#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2133	#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
AnnaBridge	172:65be27845400	2134	#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
AnnaBridge	172:65be27845400	2135	#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
AnnaBridge	172:65be27845400	2136	#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
AnnaBridge	172:65be27845400	2137	#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2138	#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2139	#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
AnnaBridge	172:65be27845400	2140	#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
AnnaBridge	172:65be27845400	2141	#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
AnnaBridge	172:65be27845400	2142	#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
AnnaBridge	172:65be27845400	2143	#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2144	#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2145	#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
AnnaBridge	172:65be27845400	2146	#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
AnnaBridge	172:65be27845400	2147	#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
AnnaBridge	172:65be27845400	2148	#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
AnnaBridge	172:65be27845400	2149	#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2150	#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2151	#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
AnnaBridge	172:65be27845400	2152	#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
AnnaBridge	172:65be27845400	2153	#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
AnnaBridge	172:65be27845400	2154	#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
AnnaBridge	172:65be27845400	2155	#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2156	#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2157	#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
AnnaBridge	172:65be27845400	2158	#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
AnnaBridge	172:65be27845400	2159	#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
AnnaBridge	172:65be27845400	2160	#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
AnnaBridge	172:65be27845400	2161	#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2162	#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2163	#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
AnnaBridge	172:65be27845400	2164	#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
AnnaBridge	172:65be27845400	2165	#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
AnnaBridge	172:65be27845400	2166	#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
AnnaBridge	172:65be27845400	2167	#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2168	#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2169	#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
AnnaBridge	172:65be27845400	2170	#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
AnnaBridge	172:65be27845400	2171	#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
AnnaBridge	172:65be27845400	2172	#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
AnnaBridge	172:65be27845400	2173	#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2174	#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2175	#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
AnnaBridge	172:65be27845400	2176	#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
AnnaBridge	172:65be27845400	2177	#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
AnnaBridge	172:65be27845400	2178	#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
AnnaBridge	172:65be27845400	2179	#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2180	#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2181	#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
AnnaBridge	172:65be27845400	2182	#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
AnnaBridge	172:65be27845400	2183	#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
AnnaBridge	172:65be27845400	2184	#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
AnnaBridge	172:65be27845400	2185	#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2186	#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2187	#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
AnnaBridge	172:65be27845400	2188	#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
AnnaBridge	172:65be27845400	2189	#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
AnnaBridge	172:65be27845400	2190	#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
AnnaBridge	172:65be27845400	2191	#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2192	#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2193	#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
AnnaBridge	172:65be27845400	2194	#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
AnnaBridge	172:65be27845400	2195	#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
AnnaBridge	172:65be27845400	2196	#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
AnnaBridge	172:65be27845400	2197	#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2198	#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2199	#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
AnnaBridge	172:65be27845400	2200	#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
AnnaBridge	172:65be27845400	2201	#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
AnnaBridge	172:65be27845400	2202	#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
AnnaBridge	172:65be27845400	2203	#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2204	#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2205	#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
AnnaBridge	172:65be27845400	2206	#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
AnnaBridge	172:65be27845400	2207	#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
AnnaBridge	172:65be27845400	2208	#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
AnnaBridge	172:65be27845400	2209	#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2210	#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2211	#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
AnnaBridge	172:65be27845400	2212	#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
AnnaBridge	172:65be27845400	2213	#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
AnnaBridge	172:65be27845400	2214	#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
AnnaBridge	172:65be27845400	2215	#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2216	#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2217	#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
AnnaBridge	172:65be27845400	2218	#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
AnnaBridge	172:65be27845400	2219	#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
AnnaBridge	172:65be27845400	2220	#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
AnnaBridge	172:65be27845400	2221	#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2222	#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2223	#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
AnnaBridge	172:65be27845400	2224	#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
AnnaBridge	172:65be27845400	2225	#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
AnnaBridge	172:65be27845400	2226	#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
AnnaBridge	172:65be27845400	2227	#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2228	#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2229	#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
AnnaBridge	172:65be27845400	2230	#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
AnnaBridge	172:65be27845400	2231	#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
AnnaBridge	172:65be27845400	2232	#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
AnnaBridge	172:65be27845400	2233	#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2234	#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2235	#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
AnnaBridge	172:65be27845400	2236	#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
AnnaBridge	172:65be27845400	2237
AnnaBridge	172:65be27845400	2238	#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
AnnaBridge	172:65be27845400	2239	#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
AnnaBridge	172:65be27845400	2240	#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2241	#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2242	#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
AnnaBridge	172:65be27845400	2243	#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
AnnaBridge	172:65be27845400	2244	#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
AnnaBridge	172:65be27845400	2245	#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
AnnaBridge	172:65be27845400	2246	#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2247	#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2248	#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
AnnaBridge	172:65be27845400	2249	#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
AnnaBridge	172:65be27845400	2250	#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
AnnaBridge	172:65be27845400	2251	#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
AnnaBridge	172:65be27845400	2252	#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2253	#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2254	#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
AnnaBridge	172:65be27845400	2255	#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
AnnaBridge	172:65be27845400	2256	#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
AnnaBridge	172:65be27845400	2257	#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
AnnaBridge	172:65be27845400	2258	#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
AnnaBridge	172:65be27845400	2259	#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
AnnaBridge	172:65be27845400	2260	#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2261	#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2262	#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
AnnaBridge	172:65be27845400	2263	#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
AnnaBridge	172:65be27845400	2264	#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
AnnaBridge	172:65be27845400	2265	#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
AnnaBridge	172:65be27845400	2266	#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2267	#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2268	#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
AnnaBridge	172:65be27845400	2269	#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
AnnaBridge	172:65be27845400	2270	#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
AnnaBridge	172:65be27845400	2271	#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
AnnaBridge	172:65be27845400	2272	#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2273	#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2274	#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
AnnaBridge	172:65be27845400	2275	#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
AnnaBridge	172:65be27845400	2276	#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
AnnaBridge	172:65be27845400	2277	#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
AnnaBridge	172:65be27845400	2278	#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2279	#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2280	#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
AnnaBridge	172:65be27845400	2281	#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
AnnaBridge	172:65be27845400	2282	#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
AnnaBridge	172:65be27845400	2283	#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
AnnaBridge	172:65be27845400	2284	#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2285	#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2286	#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2287	#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2288	#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
AnnaBridge	172:65be27845400	2289	#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
AnnaBridge	172:65be27845400	2290	#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2291	#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2292	#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
AnnaBridge	172:65be27845400	2293	#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
AnnaBridge	172:65be27845400	2294	#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
AnnaBridge	172:65be27845400	2295	#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
AnnaBridge	172:65be27845400	2296	#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2297	#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2298	#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
AnnaBridge	172:65be27845400	2299	#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
AnnaBridge	172:65be27845400	2300	#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
AnnaBridge	172:65be27845400	2301	#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
AnnaBridge	172:65be27845400	2302	#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2303	#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2304	#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
AnnaBridge	172:65be27845400	2305	#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
AnnaBridge	172:65be27845400	2306	#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
AnnaBridge	172:65be27845400	2307	#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
AnnaBridge	172:65be27845400	2308	#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
AnnaBridge	172:65be27845400	2309	#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
AnnaBridge	172:65be27845400	2310	#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
AnnaBridge	172:65be27845400	2311	#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
AnnaBridge	172:65be27845400	2312	#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
AnnaBridge	172:65be27845400	2313	#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
AnnaBridge	172:65be27845400	2314	#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
AnnaBridge	172:65be27845400	2315	#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
AnnaBridge	172:65be27845400	2316	#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
AnnaBridge	172:65be27845400	2317	#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
AnnaBridge	172:65be27845400	2318	#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
AnnaBridge	172:65be27845400	2319	#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
AnnaBridge	172:65be27845400	2320	#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
AnnaBridge	172:65be27845400	2321	#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
AnnaBridge	172:65be27845400	2322	#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
AnnaBridge	172:65be27845400	2323	#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
AnnaBridge	172:65be27845400	2324	#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
AnnaBridge	172:65be27845400	2325	#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
AnnaBridge	172:65be27845400	2326	#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
AnnaBridge	172:65be27845400	2327	#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
AnnaBridge	172:65be27845400	2328	#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2329	#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2330	#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
AnnaBridge	172:65be27845400	2331	#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
AnnaBridge	172:65be27845400	2332	#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
AnnaBridge	172:65be27845400	2333	#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
AnnaBridge	172:65be27845400	2334	#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2335	#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2336	#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
AnnaBridge	172:65be27845400	2337	#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
AnnaBridge	172:65be27845400	2338	#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
AnnaBridge	172:65be27845400	2339	#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
AnnaBridge	172:65be27845400	2340	#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2341	#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2342	#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
AnnaBridge	172:65be27845400	2343	#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
AnnaBridge	172:65be27845400	2344	#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
AnnaBridge	172:65be27845400	2345	#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
AnnaBridge	172:65be27845400	2346	#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2347	#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2348	#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
AnnaBridge	172:65be27845400	2349	#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
AnnaBridge	172:65be27845400	2350	#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
AnnaBridge	172:65be27845400	2351	#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
AnnaBridge	172:65be27845400	2352	#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2353	#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2354	#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
AnnaBridge	172:65be27845400	2355	#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
AnnaBridge	172:65be27845400	2356	#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
AnnaBridge	172:65be27845400	2357	#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
AnnaBridge	172:65be27845400	2358	#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2359	#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2360	#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
AnnaBridge	172:65be27845400	2361	#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
AnnaBridge	172:65be27845400	2362	#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
AnnaBridge	172:65be27845400	2363	#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
AnnaBridge	172:65be27845400	2364	#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2365	#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2366	#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
AnnaBridge	172:65be27845400	2367	#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
AnnaBridge	172:65be27845400	2368	#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
AnnaBridge	172:65be27845400	2369	#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
AnnaBridge	172:65be27845400	2370	#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2371	#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2372	#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
AnnaBridge	172:65be27845400	2373	#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
AnnaBridge	172:65be27845400	2374	#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
AnnaBridge	172:65be27845400	2375	#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
AnnaBridge	172:65be27845400	2376	#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2377	#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2378	#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
AnnaBridge	172:65be27845400	2379	#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
AnnaBridge	172:65be27845400	2380	#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
AnnaBridge	172:65be27845400	2381	#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
AnnaBridge	172:65be27845400	2382	#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2383	#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2384	#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
AnnaBridge	172:65be27845400	2385	#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
AnnaBridge	172:65be27845400	2386	#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
AnnaBridge	172:65be27845400	2387	#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
AnnaBridge	172:65be27845400	2388	#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
AnnaBridge	172:65be27845400	2389	#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
AnnaBridge	172:65be27845400	2390	#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
AnnaBridge	172:65be27845400	2391	#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
AnnaBridge	172:65be27845400	2392	#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2393	#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2394	#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
AnnaBridge	172:65be27845400	2395	#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
AnnaBridge	172:65be27845400	2396	#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
AnnaBridge	172:65be27845400	2397	#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
AnnaBridge	172:65be27845400	2398	#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2399	#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2400	#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
AnnaBridge	172:65be27845400	2401	#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
AnnaBridge	172:65be27845400	2402	#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
AnnaBridge	172:65be27845400	2403	#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
AnnaBridge	172:65be27845400	2404	#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2405	#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2406	#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
AnnaBridge	172:65be27845400	2407	#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
AnnaBridge	172:65be27845400	2408	#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
AnnaBridge	172:65be27845400	2409	#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
AnnaBridge	172:65be27845400	2410	#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2411	#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2412	#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
AnnaBridge	172:65be27845400	2413	#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
AnnaBridge	172:65be27845400	2414	#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
AnnaBridge	172:65be27845400	2415	#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
AnnaBridge	172:65be27845400	2416	#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2417	#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2418	#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
AnnaBridge	172:65be27845400	2419	#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
AnnaBridge	172:65be27845400	2420	#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
AnnaBridge	172:65be27845400	2421	#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
AnnaBridge	172:65be27845400	2422	#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2423	#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2424	#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
AnnaBridge	172:65be27845400	2425	#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
AnnaBridge	172:65be27845400	2426	#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
AnnaBridge	172:65be27845400	2427	#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
AnnaBridge	172:65be27845400	2428	#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2429	#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2430	#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
AnnaBridge	172:65be27845400	2431	#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
AnnaBridge	172:65be27845400	2432	#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
AnnaBridge	172:65be27845400	2433	#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
AnnaBridge	172:65be27845400	2434	#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2435	#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2436	#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
AnnaBridge	172:65be27845400	2437	#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
AnnaBridge	172:65be27845400	2438	#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
AnnaBridge	172:65be27845400	2439	#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
AnnaBridge	172:65be27845400	2440	#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
AnnaBridge	172:65be27845400	2441	#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
AnnaBridge	172:65be27845400	2442	#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
AnnaBridge	172:65be27845400	2443	#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
AnnaBridge	172:65be27845400	2444	#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
AnnaBridge	172:65be27845400	2445	#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
AnnaBridge	172:65be27845400	2446	#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
AnnaBridge	172:65be27845400	2447	#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
AnnaBridge	172:65be27845400	2448	#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
AnnaBridge	172:65be27845400	2449	#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2450	#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2451	#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
AnnaBridge	172:65be27845400	2452	#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
AnnaBridge	172:65be27845400	2453	#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
AnnaBridge	172:65be27845400	2454	#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
AnnaBridge	172:65be27845400	2455	#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
AnnaBridge	172:65be27845400	2456	#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2457	#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2458	#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
AnnaBridge	172:65be27845400	2459	#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
AnnaBridge	172:65be27845400	2460	#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
AnnaBridge	172:65be27845400	2461	#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
AnnaBridge	172:65be27845400	2462	#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
AnnaBridge	172:65be27845400	2463	#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
AnnaBridge	172:65be27845400	2464	#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2465	#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2466	#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
AnnaBridge	172:65be27845400	2467	#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
AnnaBridge	172:65be27845400	2468	#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
AnnaBridge	172:65be27845400	2469	#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
AnnaBridge	172:65be27845400	2470	#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2471	#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2472	#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
AnnaBridge	172:65be27845400	2473	#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
AnnaBridge	172:65be27845400	2474	#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2475	#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2476	#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
AnnaBridge	172:65be27845400	2477	#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
AnnaBridge	172:65be27845400	2478	#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
AnnaBridge	172:65be27845400	2479	#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
AnnaBridge	172:65be27845400	2480
AnnaBridge	172:65be27845400	2481	#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
AnnaBridge	172:65be27845400	2482	#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
AnnaBridge	172:65be27845400	2483	#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2484	#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2485	#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
AnnaBridge	172:65be27845400	2486	#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
AnnaBridge	172:65be27845400	2487	#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
AnnaBridge	172:65be27845400	2488	#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
AnnaBridge	172:65be27845400	2489	#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2490	#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2491	#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2492	#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2493	#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2494	#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2495	#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2496	#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2497	#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
AnnaBridge	172:65be27845400	2498	#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
AnnaBridge	172:65be27845400	2499	#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
AnnaBridge	172:65be27845400	2500	#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
AnnaBridge	172:65be27845400	2501	#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
AnnaBridge	172:65be27845400	2502	#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2503	#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2504	#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
AnnaBridge	172:65be27845400	2505	#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
AnnaBridge	172:65be27845400	2506	#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
AnnaBridge	172:65be27845400	2507	#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
AnnaBridge	172:65be27845400	2508	#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
AnnaBridge	172:65be27845400	2509	#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2510	#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2511	#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
AnnaBridge	172:65be27845400	2512	#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
AnnaBridge	172:65be27845400	2513	#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
AnnaBridge	172:65be27845400	2514	#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
AnnaBridge	172:65be27845400	2515	#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2516	#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2517	#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
AnnaBridge	172:65be27845400	2518	#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
AnnaBridge	172:65be27845400	2519	#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
AnnaBridge	172:65be27845400	2520	#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
AnnaBridge	172:65be27845400	2521	#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2522	#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2523	#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2524	#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2525	#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2526	#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2527	#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2528	#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2529	#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2530	#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2531	#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2532	#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2533	#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2534	#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
AnnaBridge	172:65be27845400	2535	#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
AnnaBridge	172:65be27845400	2536	#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2537	#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2538	#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
AnnaBridge	172:65be27845400	2539	#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
AnnaBridge	172:65be27845400	2540	#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
AnnaBridge	172:65be27845400	2541	#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
AnnaBridge	172:65be27845400	2542	#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
AnnaBridge	172:65be27845400	2543	#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
AnnaBridge	172:65be27845400	2544	#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2545	#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2546	#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
AnnaBridge	172:65be27845400	2547	#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
AnnaBridge	172:65be27845400	2548	#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
AnnaBridge	172:65be27845400	2549	#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
AnnaBridge	172:65be27845400	2550	#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2551	#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2552	#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
AnnaBridge	172:65be27845400	2553	#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
AnnaBridge	172:65be27845400	2554	#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
AnnaBridge	172:65be27845400	2555	#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
AnnaBridge	172:65be27845400	2556	#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2557	#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2558	#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
AnnaBridge	172:65be27845400	2559	#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
AnnaBridge	172:65be27845400	2560	#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
AnnaBridge	172:65be27845400	2561	#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
AnnaBridge	172:65be27845400	2562	#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2563	#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2564	#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
AnnaBridge	172:65be27845400	2565	#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
AnnaBridge	172:65be27845400	2566	#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
AnnaBridge	172:65be27845400	2567	#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2568	#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2569	#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
AnnaBridge	172:65be27845400	2570	#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
AnnaBridge	172:65be27845400	2571	#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
AnnaBridge	172:65be27845400	2572	#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
AnnaBridge	172:65be27845400	2573	#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
AnnaBridge	172:65be27845400	2574	#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
AnnaBridge	172:65be27845400	2575	#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2576	#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2577	#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
AnnaBridge	172:65be27845400	2578	#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
AnnaBridge	172:65be27845400	2579	#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
AnnaBridge	172:65be27845400	2580	#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
AnnaBridge	172:65be27845400	2581	#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2582	#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2583	#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
AnnaBridge	172:65be27845400	2584	#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
AnnaBridge	172:65be27845400	2585	#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
AnnaBridge	172:65be27845400	2586	#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
AnnaBridge	172:65be27845400	2587	#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2588	#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2589	#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2590	#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2591	#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
AnnaBridge	172:65be27845400	2592	#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
AnnaBridge	172:65be27845400	2593	#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2594	#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2595	#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2596	#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2597	#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
AnnaBridge	172:65be27845400	2598	#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
AnnaBridge	172:65be27845400	2599	#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
AnnaBridge	172:65be27845400	2600	#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
AnnaBridge	172:65be27845400	2601	#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2602	#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2603	#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
AnnaBridge	172:65be27845400	2604	#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
AnnaBridge	172:65be27845400	2605	#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2606	#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2607	#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2608	#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2609	#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2610	#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2611	#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2612	#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2613	#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2614	#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
AnnaBridge	172:65be27845400	2615	#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
AnnaBridge	172:65be27845400	2616	#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2617	#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2618	#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
AnnaBridge	172:65be27845400	2619	#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
AnnaBridge	172:65be27845400	2620	#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2621	#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2622	#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
AnnaBridge	172:65be27845400	2623	#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
AnnaBridge	172:65be27845400	2624	#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
AnnaBridge	172:65be27845400	2625	#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
AnnaBridge	172:65be27845400	2626	#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2627	#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2628
AnnaBridge	172:65be27845400	2629	/* alias define maintained for legacy */
AnnaBridge	172:65be27845400	2630	#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
AnnaBridge	172:65be27845400	2631	#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
AnnaBridge	172:65be27845400	2632
AnnaBridge	172:65be27845400	2633	#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
AnnaBridge	172:65be27845400	2634	#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
AnnaBridge	172:65be27845400	2635	#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
AnnaBridge	172:65be27845400	2636	#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
AnnaBridge	172:65be27845400	2637	#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
AnnaBridge	172:65be27845400	2638	#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
AnnaBridge	172:65be27845400	2639	#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
AnnaBridge	172:65be27845400	2640	#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
AnnaBridge	172:65be27845400	2641	#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
AnnaBridge	172:65be27845400	2642	#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
AnnaBridge	172:65be27845400	2643	#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
AnnaBridge	172:65be27845400	2644	#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
AnnaBridge	172:65be27845400	2645	#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
AnnaBridge	172:65be27845400	2646	#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
AnnaBridge	172:65be27845400	2647	#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
AnnaBridge	172:65be27845400	2648	#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
AnnaBridge	172:65be27845400	2649	#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
AnnaBridge	172:65be27845400	2650	#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
AnnaBridge	172:65be27845400	2651	#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
AnnaBridge	172:65be27845400	2652	#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
AnnaBridge	172:65be27845400	2653
AnnaBridge	172:65be27845400	2654	#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
AnnaBridge	172:65be27845400	2655	#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
AnnaBridge	172:65be27845400	2656	#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
AnnaBridge	172:65be27845400	2657	#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
AnnaBridge	172:65be27845400	2658	#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
AnnaBridge	172:65be27845400	2659	#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
AnnaBridge	172:65be27845400	2660	#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
AnnaBridge	172:65be27845400	2661	#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
AnnaBridge	172:65be27845400	2662	#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
AnnaBridge	172:65be27845400	2663	#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
AnnaBridge	172:65be27845400	2664	#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
AnnaBridge	172:65be27845400	2665	#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
AnnaBridge	172:65be27845400	2666	#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
AnnaBridge	172:65be27845400	2667	#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
AnnaBridge	172:65be27845400	2668	#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
AnnaBridge	172:65be27845400	2669	#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
AnnaBridge	172:65be27845400	2670	#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
AnnaBridge	172:65be27845400	2671	#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
AnnaBridge	172:65be27845400	2672	#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
AnnaBridge	172:65be27845400	2673	#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
AnnaBridge	172:65be27845400	2674
AnnaBridge	172:65be27845400	2675	#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2676	#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2677	#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2678	#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2679	#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2680	#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2681	#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2682	#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2683	#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2684	#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2685	#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2686	#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2687	#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2688	#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2689	#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2690	#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2691	#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2692	#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2693	#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2694	#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2695	#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2696	#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2697	#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2698	#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2699	#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2700	#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2701	#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2702	#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2703	#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2704	#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2705	#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2706	#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2707	#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2708	#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2709	#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2710	#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2711	#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2712	#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2713	#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2714	#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2715	#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2716	#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2717	#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2718	#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2719	#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2720	#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2721	#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2722	#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2723	#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2724	#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2725	#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2726	#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2727	#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2728	#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2729	#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2730	#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2731	#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2732	#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2733	#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2734	#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2735	#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2736	#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2737	#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2738	#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2739	#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2740	#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2741	#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2742	#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2743	#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2744	#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2745	#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2746	#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2747	#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2748	#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2749	#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2750	#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2751	#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2752	#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2753	#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2754	#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2755	#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2756	#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2757	#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2758	#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2759	#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2760	#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2761	#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2762	#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2763	#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2764	#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2765	#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2766	#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2767	#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2768	#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2769	#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2770	#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2771	#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2772	#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2773	#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2774	#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2775	#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2776	#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2777	#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2778	#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2779	#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2780	#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2781	#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2782	#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2783	#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2784	#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2785	#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2786	#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2787	#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2788	#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2789	#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2790	#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2791
AnnaBridge	172:65be27845400	2792	#if defined(STM32F4)
AnnaBridge	172:65be27845400	2793	#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
AnnaBridge	172:65be27845400	2794	#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
AnnaBridge	172:65be27845400	2795	#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2796	#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2797	#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
AnnaBridge	172:65be27845400	2798	#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
AnnaBridge	172:65be27845400	2799	#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2800	#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2801	#define Sdmmc1ClockSelection SdioClockSelection
AnnaBridge	172:65be27845400	2802	#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
AnnaBridge	172:65be27845400	2803	#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
AnnaBridge	172:65be27845400	2804	#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
AnnaBridge	172:65be27845400	2805	#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
AnnaBridge	172:65be27845400	2806	#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
AnnaBridge	172:65be27845400	2807	#endif
AnnaBridge	172:65be27845400	2808
AnnaBridge	172:65be27845400	2809	#if defined(STM32F7) \|\| defined(STM32L4)
AnnaBridge	172:65be27845400	2810	#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
AnnaBridge	172:65be27845400	2811	#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
AnnaBridge	172:65be27845400	2812	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2813	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2814	#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
AnnaBridge	172:65be27845400	2815	#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
AnnaBridge	172:65be27845400	2816	#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2817	#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2818	#define SdioClockSelection Sdmmc1ClockSelection
AnnaBridge	172:65be27845400	2819	#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
AnnaBridge	172:65be27845400	2820	#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
AnnaBridge	172:65be27845400	2821	#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
AnnaBridge	172:65be27845400	2822	#endif
AnnaBridge	172:65be27845400	2823
AnnaBridge	172:65be27845400	2824	#if defined(STM32F7)
AnnaBridge	172:65be27845400	2825	#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
AnnaBridge	172:65be27845400	2826	#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
AnnaBridge	172:65be27845400	2827	#endif
AnnaBridge	172:65be27845400	2828
AnnaBridge	172:65be27845400	2829	#if defined(STM32H7)
AnnaBridge	172:65be27845400	2830	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
AnnaBridge	172:65be27845400	2831	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
AnnaBridge	172:65be27845400	2832	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
AnnaBridge	172:65be27845400	2833	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
AnnaBridge	172:65be27845400	2834	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
AnnaBridge	172:65be27845400	2835	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
AnnaBridge	172:65be27845400	2836	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
AnnaBridge	172:65be27845400	2837	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
AnnaBridge	172:65be27845400	2838	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
AnnaBridge	172:65be27845400	2839	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
AnnaBridge	172:65be27845400	2840
AnnaBridge	172:65be27845400	2841	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
AnnaBridge	172:65be27845400	2842	#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
AnnaBridge	172:65be27845400	2843	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
AnnaBridge	172:65be27845400	2844	#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
AnnaBridge	172:65be27845400	2845	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
AnnaBridge	172:65be27845400	2846	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
AnnaBridge	172:65be27845400	2847	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
AnnaBridge	172:65be27845400	2848	#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
AnnaBridge	172:65be27845400	2849	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
AnnaBridge	172:65be27845400	2850	#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
AnnaBridge	172:65be27845400	2851	#endif
AnnaBridge	172:65be27845400	2852
AnnaBridge	172:65be27845400	2853	#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
AnnaBridge	172:65be27845400	2854	#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
AnnaBridge	172:65be27845400	2855
AnnaBridge	172:65be27845400	2856	#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
AnnaBridge	172:65be27845400	2857
AnnaBridge	172:65be27845400	2858	#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
AnnaBridge	172:65be27845400	2859	#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
AnnaBridge	172:65be27845400	2860	#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
AnnaBridge	172:65be27845400	2861	#define IS_RCC_HCLK_DIV IS_RCC_PCLK
AnnaBridge	172:65be27845400	2862	#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
AnnaBridge	172:65be27845400	2863
AnnaBridge	172:65be27845400	2864	#define RCC_IT_HSI14 RCC_IT_HSI14RDY
AnnaBridge	172:65be27845400	2865
AnnaBridge	172:65be27845400	2866	#define RCC_IT_CSSLSE RCC_IT_LSECSS
AnnaBridge	172:65be27845400	2867	#define RCC_IT_CSSHSE RCC_IT_CSS
AnnaBridge	172:65be27845400	2868
AnnaBridge	172:65be27845400	2869	#define RCC_PLLMUL_3 RCC_PLL_MUL3
AnnaBridge	172:65be27845400	2870	#define RCC_PLLMUL_4 RCC_PLL_MUL4
AnnaBridge	172:65be27845400	2871	#define RCC_PLLMUL_6 RCC_PLL_MUL6
AnnaBridge	172:65be27845400	2872	#define RCC_PLLMUL_8 RCC_PLL_MUL8
AnnaBridge	172:65be27845400	2873	#define RCC_PLLMUL_12 RCC_PLL_MUL12
AnnaBridge	172:65be27845400	2874	#define RCC_PLLMUL_16 RCC_PLL_MUL16
AnnaBridge	172:65be27845400	2875	#define RCC_PLLMUL_24 RCC_PLL_MUL24
AnnaBridge	172:65be27845400	2876	#define RCC_PLLMUL_32 RCC_PLL_MUL32
AnnaBridge	172:65be27845400	2877	#define RCC_PLLMUL_48 RCC_PLL_MUL48
AnnaBridge	172:65be27845400	2878
AnnaBridge	172:65be27845400	2879	#define RCC_PLLDIV_2 RCC_PLL_DIV2
AnnaBridge	172:65be27845400	2880	#define RCC_PLLDIV_3 RCC_PLL_DIV3
AnnaBridge	172:65be27845400	2881	#define RCC_PLLDIV_4 RCC_PLL_DIV4
AnnaBridge	172:65be27845400	2882
AnnaBridge	172:65be27845400	2883	#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
AnnaBridge	172:65be27845400	2884	#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
AnnaBridge	172:65be27845400	2885	#define RCC_MCO_NODIV RCC_MCODIV_1
AnnaBridge	172:65be27845400	2886	#define RCC_MCO_DIV1 RCC_MCODIV_1
AnnaBridge	172:65be27845400	2887	#define RCC_MCO_DIV2 RCC_MCODIV_2
AnnaBridge	172:65be27845400	2888	#define RCC_MCO_DIV4 RCC_MCODIV_4
AnnaBridge	172:65be27845400	2889	#define RCC_MCO_DIV8 RCC_MCODIV_8
AnnaBridge	172:65be27845400	2890	#define RCC_MCO_DIV16 RCC_MCODIV_16
AnnaBridge	172:65be27845400	2891	#define RCC_MCO_DIV32 RCC_MCODIV_32
AnnaBridge	172:65be27845400	2892	#define RCC_MCO_DIV64 RCC_MCODIV_64
AnnaBridge	172:65be27845400	2893	#define RCC_MCO_DIV128 RCC_MCODIV_128
AnnaBridge	172:65be27845400	2894	#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
AnnaBridge	172:65be27845400	2895	#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
AnnaBridge	172:65be27845400	2896	#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
AnnaBridge	172:65be27845400	2897	#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
AnnaBridge	172:65be27845400	2898	#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
AnnaBridge	172:65be27845400	2899	#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
AnnaBridge	172:65be27845400	2900	#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
AnnaBridge	172:65be27845400	2901	#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
AnnaBridge	172:65be27845400	2902	#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
AnnaBridge	172:65be27845400	2903	#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
AnnaBridge	172:65be27845400	2904	#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
AnnaBridge	172:65be27845400	2905
AnnaBridge	172:65be27845400	2906	#if defined(STM32L4)
AnnaBridge	172:65be27845400	2907	#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
AnnaBridge	172:65be27845400	2908	#elif defined(STM32G0)
AnnaBridge	172:65be27845400	2909	#else
AnnaBridge	172:65be27845400	2910	#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
AnnaBridge	172:65be27845400	2911	#endif
AnnaBridge	172:65be27845400	2912
AnnaBridge	172:65be27845400	2913	#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
AnnaBridge	172:65be27845400	2914	#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
AnnaBridge	172:65be27845400	2915	#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
AnnaBridge	172:65be27845400	2916	#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
AnnaBridge	172:65be27845400	2917	#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
AnnaBridge	172:65be27845400	2918	#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
AnnaBridge	172:65be27845400	2919	#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
AnnaBridge	172:65be27845400	2920	#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
AnnaBridge	172:65be27845400	2921
AnnaBridge	172:65be27845400	2922	#define HSION_BitNumber RCC_HSION_BIT_NUMBER
AnnaBridge	172:65be27845400	2923	#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
AnnaBridge	172:65be27845400	2924	#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
AnnaBridge	172:65be27845400	2925	#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
AnnaBridge	172:65be27845400	2926	#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
AnnaBridge	172:65be27845400	2927	#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
AnnaBridge	172:65be27845400	2928	#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
AnnaBridge	172:65be27845400	2929	#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
AnnaBridge	172:65be27845400	2930	#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
AnnaBridge	172:65be27845400	2931	#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
AnnaBridge	172:65be27845400	2932	#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
AnnaBridge	172:65be27845400	2933	#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
AnnaBridge	172:65be27845400	2934	#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
AnnaBridge	172:65be27845400	2935	#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
AnnaBridge	172:65be27845400	2936	#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
AnnaBridge	172:65be27845400	2937	#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
AnnaBridge	172:65be27845400	2938	#define LSION_BitNumber RCC_LSION_BIT_NUMBER
AnnaBridge	172:65be27845400	2939	#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
AnnaBridge	172:65be27845400	2940	#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
AnnaBridge	172:65be27845400	2941	#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
AnnaBridge	172:65be27845400	2942	#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
AnnaBridge	172:65be27845400	2943	#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
AnnaBridge	172:65be27845400	2944	#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
AnnaBridge	172:65be27845400	2945	#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
AnnaBridge	172:65be27845400	2946	#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
AnnaBridge	172:65be27845400	2947	#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
AnnaBridge	172:65be27845400	2948	#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
AnnaBridge	172:65be27845400	2949	#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
AnnaBridge	172:65be27845400	2950	#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
AnnaBridge	172:65be27845400	2951	#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
AnnaBridge	172:65be27845400	2952	#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
AnnaBridge	172:65be27845400	2953	#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
AnnaBridge	172:65be27845400	2954
AnnaBridge	172:65be27845400	2955	#define CR_HSION_BB RCC_CR_HSION_BB
AnnaBridge	172:65be27845400	2956	#define CR_CSSON_BB RCC_CR_CSSON_BB
AnnaBridge	172:65be27845400	2957	#define CR_PLLON_BB RCC_CR_PLLON_BB
AnnaBridge	172:65be27845400	2958	#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
AnnaBridge	172:65be27845400	2959	#define CR_MSION_BB RCC_CR_MSION_BB
AnnaBridge	172:65be27845400	2960	#define CSR_LSION_BB RCC_CSR_LSION_BB
AnnaBridge	172:65be27845400	2961	#define CSR_LSEON_BB RCC_CSR_LSEON_BB
AnnaBridge	172:65be27845400	2962	#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
AnnaBridge	172:65be27845400	2963	#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
AnnaBridge	172:65be27845400	2964	#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
AnnaBridge	172:65be27845400	2965	#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
AnnaBridge	172:65be27845400	2966	#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
AnnaBridge	172:65be27845400	2967	#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
AnnaBridge	172:65be27845400	2968	#define CR_HSEON_BB RCC_CR_HSEON_BB
AnnaBridge	172:65be27845400	2969	#define CSR_RMVF_BB RCC_CSR_RMVF_BB
AnnaBridge	172:65be27845400	2970	#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
AnnaBridge	172:65be27845400	2971	#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
AnnaBridge	172:65be27845400	2972
AnnaBridge	172:65be27845400	2973	#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
AnnaBridge	172:65be27845400	2974	#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
AnnaBridge	172:65be27845400	2975	#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
AnnaBridge	172:65be27845400	2976	#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
AnnaBridge	172:65be27845400	2977	#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
AnnaBridge	172:65be27845400	2978
AnnaBridge	172:65be27845400	2979	#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
AnnaBridge	172:65be27845400	2980
AnnaBridge	172:65be27845400	2981	#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
AnnaBridge	172:65be27845400	2982	#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
AnnaBridge	172:65be27845400	2983
AnnaBridge	172:65be27845400	2984	#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
AnnaBridge	172:65be27845400	2985	#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
AnnaBridge	172:65be27845400	2986	#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
AnnaBridge	172:65be27845400	2987	#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
AnnaBridge	172:65be27845400	2988	#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
AnnaBridge	172:65be27845400	2989	#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
AnnaBridge	172:65be27845400	2990
AnnaBridge	172:65be27845400	2991	#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
AnnaBridge	172:65be27845400	2992	#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
AnnaBridge	172:65be27845400	2993	#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
AnnaBridge	172:65be27845400	2994	#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
AnnaBridge	172:65be27845400	2995	#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
AnnaBridge	172:65be27845400	2996	#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
AnnaBridge	172:65be27845400	2997	#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
AnnaBridge	172:65be27845400	2998	#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
AnnaBridge	172:65be27845400	2999	#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
AnnaBridge	172:65be27845400	3000	#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
AnnaBridge	172:65be27845400	3001	#define DfsdmClockSelection Dfsdm1ClockSelection
AnnaBridge	172:65be27845400	3002	#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
AnnaBridge	172:65be27845400	3003	#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
AnnaBridge	172:65be27845400	3004	#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
AnnaBridge	172:65be27845400	3005	#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
AnnaBridge	172:65be27845400	3006	#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
AnnaBridge	172:65be27845400	3007	#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
AnnaBridge	172:65be27845400	3008	#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
AnnaBridge	172:65be27845400	3009	#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
AnnaBridge	172:65be27845400	3010	#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
AnnaBridge	172:65be27845400	3011
AnnaBridge	172:65be27845400	3012	#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
AnnaBridge	172:65be27845400	3013	#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
AnnaBridge	172:65be27845400	3014	#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1
AnnaBridge	172:65be27845400	3015	#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2
AnnaBridge	172:65be27845400	3016	#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
AnnaBridge	172:65be27845400	3017	#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
AnnaBridge	172:65be27845400	3018	#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
AnnaBridge	172:65be27845400	3019
AnnaBridge	172:65be27845400	3020	/**
AnnaBridge	172:65be27845400	3021	* @}
AnnaBridge	172:65be27845400	3022	*/
AnnaBridge	172:65be27845400	3023
AnnaBridge	172:65be27845400	3024	/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
AnnaBridge	172:65be27845400	3025	* @{
AnnaBridge	172:65be27845400	3026	*/
AnnaBridge	172:65be27845400	3027	#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
AnnaBridge	172:65be27845400	3028
AnnaBridge	172:65be27845400	3029	/**
AnnaBridge	172:65be27845400	3030	* @}
AnnaBridge	172:65be27845400	3031	*/
AnnaBridge	172:65be27845400	3032
AnnaBridge	172:65be27845400	3033	/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
AnnaBridge	172:65be27845400	3034	* @{
AnnaBridge	172:65be27845400	3035	*/
AnnaBridge	172:65be27845400	3036	#if defined (STM32G0) \|\| defined (STM32L412xx) \|\| defined (STM32L422xx)
AnnaBridge	172:65be27845400	3037	#else
AnnaBridge	172:65be27845400	3038	#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
AnnaBridge	172:65be27845400	3039	#endif
AnnaBridge	172:65be27845400	3040	#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
AnnaBridge	172:65be27845400	3041	#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
AnnaBridge	172:65be27845400	3042
AnnaBridge	172:65be27845400	3043	#if defined (STM32F1)
AnnaBridge	172:65be27845400	3044	#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
AnnaBridge	172:65be27845400	3045
AnnaBridge	172:65be27845400	3046	#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
AnnaBridge	172:65be27845400	3047
AnnaBridge	172:65be27845400	3048	#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
AnnaBridge	172:65be27845400	3049
AnnaBridge	172:65be27845400	3050	#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
AnnaBridge	172:65be27845400	3051
AnnaBridge	172:65be27845400	3052	#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
AnnaBridge	172:65be27845400	3053	#else
AnnaBridge	172:65be27845400	3054	#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
AnnaBridge	172:65be27845400	3055	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
AnnaBridge	172:65be27845400	3056	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
AnnaBridge	172:65be27845400	3057	#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
AnnaBridge	172:65be27845400	3058	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
AnnaBridge	172:65be27845400	3059	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
AnnaBridge	172:65be27845400	3060	#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
AnnaBridge	172:65be27845400	3061	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
AnnaBridge	172:65be27845400	3062	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
AnnaBridge	172:65be27845400	3063	#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
AnnaBridge	172:65be27845400	3064	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
AnnaBridge	172:65be27845400	3065	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
AnnaBridge	172:65be27845400	3066	#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
AnnaBridge	172:65be27845400	3067	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
AnnaBridge	172:65be27845400	3068	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
AnnaBridge	172:65be27845400	3069	#endif /* STM32F1 */
AnnaBridge	172:65be27845400	3070
AnnaBridge	172:65be27845400	3071	#define IS_ALARM IS_RTC_ALARM
AnnaBridge	172:65be27845400	3072	#define IS_ALARM_MASK IS_RTC_ALARM_MASK
AnnaBridge	172:65be27845400	3073	#define IS_TAMPER IS_RTC_TAMPER
AnnaBridge	172:65be27845400	3074	#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
AnnaBridge	172:65be27845400	3075	#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
AnnaBridge	172:65be27845400	3076	#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
AnnaBridge	172:65be27845400	3077	#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
AnnaBridge	172:65be27845400	3078	#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
AnnaBridge	172:65be27845400	3079	#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
AnnaBridge	172:65be27845400	3080	#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
AnnaBridge	172:65be27845400	3081	#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
AnnaBridge	172:65be27845400	3082	#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
AnnaBridge	172:65be27845400	3083	#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
AnnaBridge	172:65be27845400	3084	#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
AnnaBridge	172:65be27845400	3085
AnnaBridge	172:65be27845400	3086	#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
AnnaBridge	172:65be27845400	3087	#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
AnnaBridge	172:65be27845400	3088
AnnaBridge	172:65be27845400	3089	/**
AnnaBridge	172:65be27845400	3090	* @}
AnnaBridge	172:65be27845400	3091	*/
AnnaBridge	172:65be27845400	3092
AnnaBridge	172:65be27845400	3093	/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
AnnaBridge	172:65be27845400	3094	* @{
AnnaBridge	172:65be27845400	3095	*/
AnnaBridge	172:65be27845400	3096
AnnaBridge	172:65be27845400	3097	#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
AnnaBridge	172:65be27845400	3098	#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
AnnaBridge	172:65be27845400	3099
AnnaBridge	172:65be27845400	3100	#if defined(STM32F4) \|\| defined(STM32F2)
AnnaBridge	172:65be27845400	3101	#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
AnnaBridge	172:65be27845400	3102	#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
AnnaBridge	172:65be27845400	3103	#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
AnnaBridge	172:65be27845400	3104	#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
AnnaBridge	172:65be27845400	3105	#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
AnnaBridge	172:65be27845400	3106	#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
AnnaBridge	172:65be27845400	3107	#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
AnnaBridge	172:65be27845400	3108	#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
AnnaBridge	172:65be27845400	3109	#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
AnnaBridge	172:65be27845400	3110	#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
AnnaBridge	172:65be27845400	3111	#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
AnnaBridge	172:65be27845400	3112	#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
AnnaBridge	172:65be27845400	3113	#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
AnnaBridge	172:65be27845400	3114	#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
AnnaBridge	172:65be27845400	3115	#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
AnnaBridge	172:65be27845400	3116	#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
AnnaBridge	172:65be27845400	3117	#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
AnnaBridge	172:65be27845400	3118	#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
AnnaBridge	172:65be27845400	3119	#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
AnnaBridge	172:65be27845400	3120	#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
AnnaBridge	172:65be27845400	3121	/* alias CMSIS */
AnnaBridge	172:65be27845400	3122	#define SDMMC1_IRQn SDIO_IRQn
AnnaBridge	172:65be27845400	3123	#define SDMMC1_IRQHandler SDIO_IRQHandler
AnnaBridge	172:65be27845400	3124	#endif
AnnaBridge	172:65be27845400	3125
AnnaBridge	172:65be27845400	3126	#if defined(STM32F7) \|\| defined(STM32L4)
AnnaBridge	172:65be27845400	3127	#define SD_SDIO_DISABLED SD_SDMMC_DISABLED
AnnaBridge	172:65be27845400	3128	#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
AnnaBridge	172:65be27845400	3129	#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
AnnaBridge	172:65be27845400	3130	#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
AnnaBridge	172:65be27845400	3131	#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
AnnaBridge	172:65be27845400	3132	#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
AnnaBridge	172:65be27845400	3133	#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
AnnaBridge	172:65be27845400	3134	#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
AnnaBridge	172:65be27845400	3135	#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
AnnaBridge	172:65be27845400	3136	#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
AnnaBridge	172:65be27845400	3137	#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
AnnaBridge	172:65be27845400	3138	#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
AnnaBridge	172:65be27845400	3139	#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
AnnaBridge	172:65be27845400	3140	#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
AnnaBridge	172:65be27845400	3141	#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
AnnaBridge	172:65be27845400	3142	#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
AnnaBridge	172:65be27845400	3143	#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
AnnaBridge	172:65be27845400	3144	#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
AnnaBridge	172:65be27845400	3145	#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
AnnaBridge	172:65be27845400	3146	#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
AnnaBridge	172:65be27845400	3147	/* alias CMSIS for compatibilities */
AnnaBridge	172:65be27845400	3148	#define SDIO_IRQn SDMMC1_IRQn
AnnaBridge	172:65be27845400	3149	#define SDIO_IRQHandler SDMMC1_IRQHandler
AnnaBridge	172:65be27845400	3150	#endif
AnnaBridge	172:65be27845400	3151
AnnaBridge	172:65be27845400	3152	#if defined(STM32F7) \|\| defined(STM32F4) \|\| defined(STM32F2)
AnnaBridge	172:65be27845400	3153	#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
AnnaBridge	172:65be27845400	3154	#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
AnnaBridge	172:65be27845400	3155	#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
AnnaBridge	172:65be27845400	3156	#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
AnnaBridge	172:65be27845400	3157	#endif
AnnaBridge	172:65be27845400	3158
AnnaBridge	172:65be27845400	3159	#if defined(STM32H7)
AnnaBridge	172:65be27845400	3160	#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
AnnaBridge	172:65be27845400	3161	#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
AnnaBridge	172:65be27845400	3162	#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
AnnaBridge	172:65be27845400	3163	#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
AnnaBridge	172:65be27845400	3164	#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback
AnnaBridge	172:65be27845400	3165	#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback
AnnaBridge	172:65be27845400	3166	#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback
AnnaBridge	172:65be27845400	3167	#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback
AnnaBridge	172:65be27845400	3168	#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback
AnnaBridge	172:65be27845400	3169	#endif
AnnaBridge	172:65be27845400	3170	/**
AnnaBridge	172:65be27845400	3171	* @}
AnnaBridge	172:65be27845400	3172	*/
AnnaBridge	172:65be27845400	3173
AnnaBridge	172:65be27845400	3174	/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
AnnaBridge	172:65be27845400	3175	* @{
AnnaBridge	172:65be27845400	3176	*/
AnnaBridge	172:65be27845400	3177
AnnaBridge	172:65be27845400	3178	#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
AnnaBridge	172:65be27845400	3179	#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
AnnaBridge	172:65be27845400	3180	#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
AnnaBridge	172:65be27845400	3181	#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
AnnaBridge	172:65be27845400	3182	#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
AnnaBridge	172:65be27845400	3183	#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
AnnaBridge	172:65be27845400	3184
AnnaBridge	172:65be27845400	3185	#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
AnnaBridge	172:65be27845400	3186	#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
AnnaBridge	172:65be27845400	3187
AnnaBridge	172:65be27845400	3188	#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
AnnaBridge	172:65be27845400	3189
AnnaBridge	172:65be27845400	3190	/**
AnnaBridge	172:65be27845400	3191	* @}
AnnaBridge	172:65be27845400	3192	*/
AnnaBridge	172:65be27845400	3193
AnnaBridge	172:65be27845400	3194	/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
AnnaBridge	172:65be27845400	3195	* @{
AnnaBridge	172:65be27845400	3196	*/
AnnaBridge	172:65be27845400	3197	#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
AnnaBridge	172:65be27845400	3198	#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
AnnaBridge	172:65be27845400	3199	#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
AnnaBridge	172:65be27845400	3200	#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
AnnaBridge	172:65be27845400	3201	#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
AnnaBridge	172:65be27845400	3202	#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
AnnaBridge	172:65be27845400	3203	#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
AnnaBridge	172:65be27845400	3204	#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
AnnaBridge	172:65be27845400	3205	/**
AnnaBridge	172:65be27845400	3206	* @}
AnnaBridge	172:65be27845400	3207	*/
AnnaBridge	172:65be27845400	3208
AnnaBridge	172:65be27845400	3209	/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
AnnaBridge	172:65be27845400	3210	* @{
AnnaBridge	172:65be27845400	3211	*/
AnnaBridge	172:65be27845400	3212
AnnaBridge	172:65be27845400	3213	#define __HAL_SPI_1LINE_TX SPI_1LINE_TX
AnnaBridge	172:65be27845400	3214	#define __HAL_SPI_1LINE_RX SPI_1LINE_RX
AnnaBridge	172:65be27845400	3215	#define __HAL_SPI_RESET_CRC SPI_RESET_CRC
AnnaBridge	172:65be27845400	3216
AnnaBridge	172:65be27845400	3217	/**
AnnaBridge	172:65be27845400	3218	* @}
AnnaBridge	172:65be27845400	3219	*/
AnnaBridge	172:65be27845400	3220
AnnaBridge	172:65be27845400	3221	/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
AnnaBridge	172:65be27845400	3222	* @{
AnnaBridge	172:65be27845400	3223	*/
AnnaBridge	172:65be27845400	3224
AnnaBridge	172:65be27845400	3225	#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
AnnaBridge	172:65be27845400	3226	#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
AnnaBridge	172:65be27845400	3227	#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
AnnaBridge	172:65be27845400	3228	#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
AnnaBridge	172:65be27845400	3229
AnnaBridge	172:65be27845400	3230	#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
AnnaBridge	172:65be27845400	3231
AnnaBridge	172:65be27845400	3232	#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
AnnaBridge	172:65be27845400	3233	#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
AnnaBridge	172:65be27845400	3234
AnnaBridge	172:65be27845400	3235	/**
AnnaBridge	172:65be27845400	3236	* @}
AnnaBridge	172:65be27845400	3237	*/
AnnaBridge	172:65be27845400	3238
AnnaBridge	172:65be27845400	3239
AnnaBridge	172:65be27845400	3240	/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
AnnaBridge	172:65be27845400	3241	* @{
AnnaBridge	172:65be27845400	3242	*/
AnnaBridge	172:65be27845400	3243
AnnaBridge	172:65be27845400	3244	#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
AnnaBridge	172:65be27845400	3245	#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
AnnaBridge	172:65be27845400	3246	#define __USART_ENABLE __HAL_USART_ENABLE
AnnaBridge	172:65be27845400	3247	#define __USART_DISABLE __HAL_USART_DISABLE
AnnaBridge	172:65be27845400	3248
AnnaBridge	172:65be27845400	3249	#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
AnnaBridge	172:65be27845400	3250	#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
AnnaBridge	172:65be27845400	3251
AnnaBridge	172:65be27845400	3252	/**
AnnaBridge	172:65be27845400	3253	* @}
AnnaBridge	172:65be27845400	3254	*/
AnnaBridge	172:65be27845400	3255
AnnaBridge	172:65be27845400	3256	/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
AnnaBridge	172:65be27845400	3257	* @{
AnnaBridge	172:65be27845400	3258	*/
AnnaBridge	172:65be27845400	3259	#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
AnnaBridge	172:65be27845400	3260
AnnaBridge	172:65be27845400	3261	#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
AnnaBridge	172:65be27845400	3262	#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
AnnaBridge	172:65be27845400	3263	#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
AnnaBridge	172:65be27845400	3264	#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
AnnaBridge	172:65be27845400	3265
AnnaBridge	172:65be27845400	3266	#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
AnnaBridge	172:65be27845400	3267	#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
AnnaBridge	172:65be27845400	3268	#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
AnnaBridge	172:65be27845400	3269	#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
AnnaBridge	172:65be27845400	3270
AnnaBridge	172:65be27845400	3271	#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
AnnaBridge	172:65be27845400	3272	#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
AnnaBridge	172:65be27845400	3273	#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
AnnaBridge	172:65be27845400	3274	#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
AnnaBridge	172:65be27845400	3275	#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
AnnaBridge	172:65be27845400	3276	#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
AnnaBridge	172:65be27845400	3277	#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
AnnaBridge	172:65be27845400	3278
AnnaBridge	172:65be27845400	3279	#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
AnnaBridge	172:65be27845400	3280	#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
AnnaBridge	172:65be27845400	3281	#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
AnnaBridge	172:65be27845400	3282	#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
AnnaBridge	172:65be27845400	3283	#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
AnnaBridge	172:65be27845400	3284	#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
AnnaBridge	172:65be27845400	3285	#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
AnnaBridge	172:65be27845400	3286	#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
AnnaBridge	172:65be27845400	3287
AnnaBridge	172:65be27845400	3288	#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
AnnaBridge	172:65be27845400	3289	#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
AnnaBridge	172:65be27845400	3290	#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
AnnaBridge	172:65be27845400	3291	#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
AnnaBridge	172:65be27845400	3292	#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
AnnaBridge	172:65be27845400	3293	#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
AnnaBridge	172:65be27845400	3294	#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
AnnaBridge	172:65be27845400	3295	#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
AnnaBridge	172:65be27845400	3296
AnnaBridge	172:65be27845400	3297	#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
AnnaBridge	172:65be27845400	3298	#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
AnnaBridge	172:65be27845400	3299
AnnaBridge	172:65be27845400	3300	#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
AnnaBridge	172:65be27845400	3301	#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
AnnaBridge	172:65be27845400	3302	/**
AnnaBridge	172:65be27845400	3303	* @}
AnnaBridge	172:65be27845400	3304	*/
AnnaBridge	172:65be27845400	3305
AnnaBridge	172:65be27845400	3306	/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
AnnaBridge	172:65be27845400	3307	* @{
AnnaBridge	172:65be27845400	3308	*/
AnnaBridge	172:65be27845400	3309	#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
AnnaBridge	172:65be27845400	3310	#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
AnnaBridge	172:65be27845400	3311
AnnaBridge	172:65be27845400	3312	#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
AnnaBridge	172:65be27845400	3313	#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
AnnaBridge	172:65be27845400	3314
AnnaBridge	172:65be27845400	3315	#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
AnnaBridge	172:65be27845400	3316
AnnaBridge	172:65be27845400	3317	#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
AnnaBridge	172:65be27845400	3318	#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
AnnaBridge	172:65be27845400	3319	#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
AnnaBridge	172:65be27845400	3320	#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
AnnaBridge	172:65be27845400	3321	#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
AnnaBridge	172:65be27845400	3322	#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
AnnaBridge	172:65be27845400	3323	#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
AnnaBridge	172:65be27845400	3324	#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
AnnaBridge	172:65be27845400	3325	#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
AnnaBridge	172:65be27845400	3326	#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
AnnaBridge	172:65be27845400	3327	#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
AnnaBridge	172:65be27845400	3328	#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
AnnaBridge	172:65be27845400	3329
AnnaBridge	172:65be27845400	3330	#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
AnnaBridge	172:65be27845400	3331	/**
AnnaBridge	172:65be27845400	3332	* @}
AnnaBridge	172:65be27845400	3333	*/
AnnaBridge	172:65be27845400	3334
AnnaBridge	172:65be27845400	3335	/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
AnnaBridge	172:65be27845400	3336	* @{
AnnaBridge	172:65be27845400	3337	*/
AnnaBridge	172:65be27845400	3338
AnnaBridge	172:65be27845400	3339	#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
AnnaBridge	172:65be27845400	3340	#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
AnnaBridge	172:65be27845400	3341	#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
AnnaBridge	172:65be27845400	3342	#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
AnnaBridge	172:65be27845400	3343	#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
AnnaBridge	172:65be27845400	3344	#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
AnnaBridge	172:65be27845400	3345	#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
AnnaBridge	172:65be27845400	3346
AnnaBridge	172:65be27845400	3347	#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
AnnaBridge	172:65be27845400	3348	#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
AnnaBridge	172:65be27845400	3349	#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
AnnaBridge	172:65be27845400	3350	/**
AnnaBridge	172:65be27845400	3351	* @}
AnnaBridge	172:65be27845400	3352	*/
AnnaBridge	172:65be27845400	3353
AnnaBridge	172:65be27845400	3354	/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
AnnaBridge	172:65be27845400	3355	* @{
AnnaBridge	172:65be27845400	3356	*/
AnnaBridge	172:65be27845400	3357	#define __HAL_LTDC_LAYER LTDC_LAYER
AnnaBridge	172:65be27845400	3358	#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
AnnaBridge	172:65be27845400	3359	/**
AnnaBridge	172:65be27845400	3360	* @}
AnnaBridge	172:65be27845400	3361	*/
AnnaBridge	172:65be27845400	3362
AnnaBridge	172:65be27845400	3363	/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
AnnaBridge	172:65be27845400	3364	* @{
AnnaBridge	172:65be27845400	3365	*/
AnnaBridge	172:65be27845400	3366	#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
AnnaBridge	172:65be27845400	3367	#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
AnnaBridge	172:65be27845400	3368	#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
AnnaBridge	172:65be27845400	3369	#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
AnnaBridge	172:65be27845400	3370	#define SAI_STREOMODE SAI_STEREOMODE
AnnaBridge	172:65be27845400	3371	#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
AnnaBridge	172:65be27845400	3372	#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
AnnaBridge	172:65be27845400	3373	#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
AnnaBridge	172:65be27845400	3374	#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
AnnaBridge	172:65be27845400	3375	#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
AnnaBridge	172:65be27845400	3376	#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
AnnaBridge	172:65be27845400	3377	#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
AnnaBridge	172:65be27845400	3378	#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
AnnaBridge	172:65be27845400	3379	#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
AnnaBridge	172:65be27845400	3380	/**
AnnaBridge	172:65be27845400	3381	* @}
AnnaBridge	172:65be27845400	3382	*/
AnnaBridge	172:65be27845400	3383
AnnaBridge	172:65be27845400	3384	/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
AnnaBridge	172:65be27845400	3385	* @{
AnnaBridge	172:65be27845400	3386	*/
AnnaBridge	172:65be27845400	3387	#if defined(STM32H7)
AnnaBridge	172:65be27845400	3388	#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow
AnnaBridge	172:65be27845400	3389	#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT
AnnaBridge	172:65be27845400	3390	#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA
AnnaBridge	172:65be27845400	3391	#endif
AnnaBridge	172:65be27845400	3392	/**
AnnaBridge	172:65be27845400	3393	* @}
AnnaBridge	172:65be27845400	3394	*/
AnnaBridge	172:65be27845400	3395
AnnaBridge	172:65be27845400	3396	/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
AnnaBridge	172:65be27845400	3397	* @{
AnnaBridge	172:65be27845400	3398	*/
AnnaBridge	172:65be27845400	3399	#if defined (STM32H7) \|\| defined (STM32F3)
AnnaBridge	172:65be27845400	3400	#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
AnnaBridge	172:65be27845400	3401	#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
AnnaBridge	172:65be27845400	3402	#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
AnnaBridge	172:65be27845400	3403	#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
AnnaBridge	172:65be27845400	3404	#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
AnnaBridge	172:65be27845400	3405	#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
AnnaBridge	172:65be27845400	3406	#endif
AnnaBridge	172:65be27845400	3407	/**
AnnaBridge	172:65be27845400	3408	* @}
AnnaBridge	172:65be27845400	3409	*/
AnnaBridge	172:65be27845400	3410
AnnaBridge	172:65be27845400	3411	/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
AnnaBridge	172:65be27845400	3412	* @{
AnnaBridge	172:65be27845400	3413	*/
AnnaBridge	172:65be27845400	3414
AnnaBridge	172:65be27845400	3415	/**
AnnaBridge	172:65be27845400	3416	* @}
AnnaBridge	172:65be27845400	3417	*/
AnnaBridge	172:65be27845400	3418
AnnaBridge	172:65be27845400	3419	#ifdef __cplusplus
AnnaBridge	172:65be27845400	3420	}
AnnaBridge	172:65be27845400	3421	#endif
AnnaBridge	172:65be27845400	3422
AnnaBridge	172:65be27845400	3423	#endif /* STM32_HAL_LEGACY */
AnnaBridge	172:65be27845400	3424
AnnaBridge	172:65be27845400	3425	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
AnnaBridge	172:65be27845400	3426