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TARGET_NUCLEO_H743ZI/TOOLCHAIN_ARM_MICRO/core_sc000.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 172:65be27845400 1 /**************************************************************************//**
AnnaBridge 172:65be27845400 2 * @file core_sc000.h
AnnaBridge 172:65be27845400 3 * @brief CMSIS SC000 Core Peripheral Access Layer Header File
AnnaBridge 172:65be27845400 4 * @version V5.0.5
AnnaBridge 172:65be27845400 5 * @date 28. May 2018
AnnaBridge 172:65be27845400 6 ******************************************************************************/
AnnaBridge 172:65be27845400 7 /*
AnnaBridge 172:65be27845400 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
AnnaBridge 172:65be27845400 9 *
AnnaBridge 172:65be27845400 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 172:65be27845400 11 *
AnnaBridge 172:65be27845400 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 172:65be27845400 13 * not use this file except in compliance with the License.
AnnaBridge 172:65be27845400 14 * You may obtain a copy of the License at
AnnaBridge 172:65be27845400 15 *
AnnaBridge 172:65be27845400 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 172:65be27845400 17 *
AnnaBridge 172:65be27845400 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 172:65be27845400 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 172:65be27845400 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 172:65be27845400 21 * See the License for the specific language governing permissions and
AnnaBridge 172:65be27845400 22 * limitations under the License.
AnnaBridge 172:65be27845400 23 */
AnnaBridge 172:65be27845400 24
AnnaBridge 172:65be27845400 25 #if defined ( __ICCARM__ )
AnnaBridge 172:65be27845400 26 #pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge 172:65be27845400 27 #elif defined (__clang__)
AnnaBridge 172:65be27845400 28 #pragma clang system_header /* treat file as system include file */
AnnaBridge 172:65be27845400 29 #endif
AnnaBridge 172:65be27845400 30
AnnaBridge 172:65be27845400 31 #ifndef __CORE_SC000_H_GENERIC
AnnaBridge 172:65be27845400 32 #define __CORE_SC000_H_GENERIC
AnnaBridge 172:65be27845400 33
AnnaBridge 172:65be27845400 34 #include <stdint.h>
AnnaBridge 172:65be27845400 35
AnnaBridge 172:65be27845400 36 #ifdef __cplusplus
AnnaBridge 172:65be27845400 37 extern "C" {
AnnaBridge 172:65be27845400 38 #endif
AnnaBridge 172:65be27845400 39
AnnaBridge 172:65be27845400 40 /**
AnnaBridge 172:65be27845400 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge 172:65be27845400 42 CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge 172:65be27845400 43
AnnaBridge 172:65be27845400 44 \li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge 172:65be27845400 45 Function definitions in header files are used to allow 'inlining'.
AnnaBridge 172:65be27845400 46
AnnaBridge 172:65be27845400 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge 172:65be27845400 48 Unions are used for effective representation of core registers.
AnnaBridge 172:65be27845400 49
AnnaBridge 172:65be27845400 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge 172:65be27845400 51 Function-like macros are used to allow more efficient code.
AnnaBridge 172:65be27845400 52 */
AnnaBridge 172:65be27845400 53
AnnaBridge 172:65be27845400 54
AnnaBridge 172:65be27845400 55 /*******************************************************************************
AnnaBridge 172:65be27845400 56 * CMSIS definitions
AnnaBridge 172:65be27845400 57 ******************************************************************************/
AnnaBridge 172:65be27845400 58 /**
AnnaBridge 172:65be27845400 59 \ingroup SC000
AnnaBridge 172:65be27845400 60 @{
AnnaBridge 172:65be27845400 61 */
AnnaBridge 172:65be27845400 62
AnnaBridge 172:65be27845400 63 #include "cmsis_version.h"
AnnaBridge 172:65be27845400 64
AnnaBridge 172:65be27845400 65 /* CMSIS SC000 definitions */
AnnaBridge 172:65be27845400 66 #define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
AnnaBridge 172:65be27845400 67 #define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
AnnaBridge 172:65be27845400 68 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
AnnaBridge 172:65be27845400 69 __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
AnnaBridge 172:65be27845400 70
AnnaBridge 172:65be27845400 71 #define __CORTEX_SC (000U) /*!< Cortex secure core */
AnnaBridge 172:65be27845400 72
AnnaBridge 172:65be27845400 73 /** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge 172:65be27845400 74 This core does not support an FPU at all
AnnaBridge 172:65be27845400 75 */
AnnaBridge 172:65be27845400 76 #define __FPU_USED 0U
AnnaBridge 172:65be27845400 77
AnnaBridge 172:65be27845400 78 #if defined ( __CC_ARM )
AnnaBridge 172:65be27845400 79 #if defined __TARGET_FPU_VFP
AnnaBridge 172:65be27845400 80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 172:65be27845400 81 #endif
AnnaBridge 172:65be27845400 82
AnnaBridge 172:65be27845400 83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 172:65be27845400 84 #if defined __ARM_FP
AnnaBridge 172:65be27845400 85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 172:65be27845400 86 #endif
AnnaBridge 172:65be27845400 87
AnnaBridge 172:65be27845400 88 #elif defined ( __GNUC__ )
AnnaBridge 172:65be27845400 89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge 172:65be27845400 90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 172:65be27845400 91 #endif
AnnaBridge 172:65be27845400 92
AnnaBridge 172:65be27845400 93 #elif defined ( __ICCARM__ )
AnnaBridge 172:65be27845400 94 #if defined __ARMVFP__
AnnaBridge 172:65be27845400 95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 172:65be27845400 96 #endif
AnnaBridge 172:65be27845400 97
AnnaBridge 172:65be27845400 98 #elif defined ( __TI_ARM__ )
AnnaBridge 172:65be27845400 99 #if defined __TI_VFP_SUPPORT__
AnnaBridge 172:65be27845400 100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 172:65be27845400 101 #endif
AnnaBridge 172:65be27845400 102
AnnaBridge 172:65be27845400 103 #elif defined ( __TASKING__ )
AnnaBridge 172:65be27845400 104 #if defined __FPU_VFP__
AnnaBridge 172:65be27845400 105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 172:65be27845400 106 #endif
AnnaBridge 172:65be27845400 107
AnnaBridge 172:65be27845400 108 #elif defined ( __CSMC__ )
AnnaBridge 172:65be27845400 109 #if ( __CSMC__ & 0x400U)
AnnaBridge 172:65be27845400 110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge 172:65be27845400 111 #endif
AnnaBridge 172:65be27845400 112
AnnaBridge 172:65be27845400 113 #endif
AnnaBridge 172:65be27845400 114
AnnaBridge 172:65be27845400 115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge 172:65be27845400 116
AnnaBridge 172:65be27845400 117
AnnaBridge 172:65be27845400 118 #ifdef __cplusplus
AnnaBridge 172:65be27845400 119 }
AnnaBridge 172:65be27845400 120 #endif
AnnaBridge 172:65be27845400 121
AnnaBridge 172:65be27845400 122 #endif /* __CORE_SC000_H_GENERIC */
AnnaBridge 172:65be27845400 123
AnnaBridge 172:65be27845400 124 #ifndef __CMSIS_GENERIC
AnnaBridge 172:65be27845400 125
AnnaBridge 172:65be27845400 126 #ifndef __CORE_SC000_H_DEPENDANT
AnnaBridge 172:65be27845400 127 #define __CORE_SC000_H_DEPENDANT
AnnaBridge 172:65be27845400 128
AnnaBridge 172:65be27845400 129 #ifdef __cplusplus
AnnaBridge 172:65be27845400 130 extern "C" {
AnnaBridge 172:65be27845400 131 #endif
AnnaBridge 172:65be27845400 132
AnnaBridge 172:65be27845400 133 /* check device defines and use defaults */
AnnaBridge 172:65be27845400 134 #if defined __CHECK_DEVICE_DEFINES
AnnaBridge 172:65be27845400 135 #ifndef __SC000_REV
AnnaBridge 172:65be27845400 136 #define __SC000_REV 0x0000U
AnnaBridge 172:65be27845400 137 #warning "__SC000_REV not defined in device header file; using default!"
AnnaBridge 172:65be27845400 138 #endif
AnnaBridge 172:65be27845400 139
AnnaBridge 172:65be27845400 140 #ifndef __MPU_PRESENT
AnnaBridge 172:65be27845400 141 #define __MPU_PRESENT 0U
AnnaBridge 172:65be27845400 142 #warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge 172:65be27845400 143 #endif
AnnaBridge 172:65be27845400 144
AnnaBridge 172:65be27845400 145 #ifndef __NVIC_PRIO_BITS
AnnaBridge 172:65be27845400 146 #define __NVIC_PRIO_BITS 2U
AnnaBridge 172:65be27845400 147 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge 172:65be27845400 148 #endif
AnnaBridge 172:65be27845400 149
AnnaBridge 172:65be27845400 150 #ifndef __Vendor_SysTickConfig
AnnaBridge 172:65be27845400 151 #define __Vendor_SysTickConfig 0U
AnnaBridge 172:65be27845400 152 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge 172:65be27845400 153 #endif
AnnaBridge 172:65be27845400 154 #endif
AnnaBridge 172:65be27845400 155
AnnaBridge 172:65be27845400 156 /* IO definitions (access restrictions to peripheral registers) */
AnnaBridge 172:65be27845400 157 /**
AnnaBridge 172:65be27845400 158 \defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge 172:65be27845400 159
AnnaBridge 172:65be27845400 160 <strong>IO Type Qualifiers</strong> are used
AnnaBridge 172:65be27845400 161 \li to specify the access to peripheral variables.
AnnaBridge 172:65be27845400 162 \li for automatic generation of peripheral register debug information.
AnnaBridge 172:65be27845400 163 */
AnnaBridge 172:65be27845400 164 #ifdef __cplusplus
AnnaBridge 172:65be27845400 165 #define __I volatile /*!< Defines 'read only' permissions */
AnnaBridge 172:65be27845400 166 #else
AnnaBridge 172:65be27845400 167 #define __I volatile const /*!< Defines 'read only' permissions */
AnnaBridge 172:65be27845400 168 #endif
AnnaBridge 172:65be27845400 169 #define __O volatile /*!< Defines 'write only' permissions */
AnnaBridge 172:65be27845400 170 #define __IO volatile /*!< Defines 'read / write' permissions */
AnnaBridge 172:65be27845400 171
AnnaBridge 172:65be27845400 172 /* following defines should be used for structure members */
AnnaBridge 172:65be27845400 173 #define __IM volatile const /*! Defines 'read only' structure member permissions */
AnnaBridge 172:65be27845400 174 #define __OM volatile /*! Defines 'write only' structure member permissions */
AnnaBridge 172:65be27845400 175 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
AnnaBridge 172:65be27845400 176
AnnaBridge 172:65be27845400 177 /*@} end of group SC000 */
AnnaBridge 172:65be27845400 178
AnnaBridge 172:65be27845400 179
AnnaBridge 172:65be27845400 180
AnnaBridge 172:65be27845400 181 /*******************************************************************************
AnnaBridge 172:65be27845400 182 * Register Abstraction
AnnaBridge 172:65be27845400 183 Core Register contain:
AnnaBridge 172:65be27845400 184 - Core Register
AnnaBridge 172:65be27845400 185 - Core NVIC Register
AnnaBridge 172:65be27845400 186 - Core SCB Register
AnnaBridge 172:65be27845400 187 - Core SysTick Register
AnnaBridge 172:65be27845400 188 - Core MPU Register
AnnaBridge 172:65be27845400 189 ******************************************************************************/
AnnaBridge 172:65be27845400 190 /**
AnnaBridge 172:65be27845400 191 \defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge 172:65be27845400 192 \brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge 172:65be27845400 193 */
AnnaBridge 172:65be27845400 194
AnnaBridge 172:65be27845400 195 /**
AnnaBridge 172:65be27845400 196 \ingroup CMSIS_core_register
AnnaBridge 172:65be27845400 197 \defgroup CMSIS_CORE Status and Control Registers
AnnaBridge 172:65be27845400 198 \brief Core Register type definitions.
AnnaBridge 172:65be27845400 199 @{
AnnaBridge 172:65be27845400 200 */
AnnaBridge 172:65be27845400 201
AnnaBridge 172:65be27845400 202 /**
AnnaBridge 172:65be27845400 203 \brief Union type to access the Application Program Status Register (APSR).
AnnaBridge 172:65be27845400 204 */
AnnaBridge 172:65be27845400 205 typedef union
AnnaBridge 172:65be27845400 206 {
AnnaBridge 172:65be27845400 207 struct
AnnaBridge 172:65be27845400 208 {
AnnaBridge 172:65be27845400 209 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
AnnaBridge 172:65be27845400 210 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 172:65be27845400 211 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 172:65be27845400 212 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 172:65be27845400 213 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 172:65be27845400 214 } b; /*!< Structure used for bit access */
AnnaBridge 172:65be27845400 215 uint32_t w; /*!< Type used for word access */
AnnaBridge 172:65be27845400 216 } APSR_Type;
AnnaBridge 172:65be27845400 217
AnnaBridge 172:65be27845400 218 /* APSR Register Definitions */
AnnaBridge 172:65be27845400 219 #define APSR_N_Pos 31U /*!< APSR: N Position */
AnnaBridge 172:65be27845400 220 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
AnnaBridge 172:65be27845400 221
AnnaBridge 172:65be27845400 222 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
AnnaBridge 172:65be27845400 223 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
AnnaBridge 172:65be27845400 224
AnnaBridge 172:65be27845400 225 #define APSR_C_Pos 29U /*!< APSR: C Position */
AnnaBridge 172:65be27845400 226 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
AnnaBridge 172:65be27845400 227
AnnaBridge 172:65be27845400 228 #define APSR_V_Pos 28U /*!< APSR: V Position */
AnnaBridge 172:65be27845400 229 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
AnnaBridge 172:65be27845400 230
AnnaBridge 172:65be27845400 231
AnnaBridge 172:65be27845400 232 /**
AnnaBridge 172:65be27845400 233 \brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge 172:65be27845400 234 */
AnnaBridge 172:65be27845400 235 typedef union
AnnaBridge 172:65be27845400 236 {
AnnaBridge 172:65be27845400 237 struct
AnnaBridge 172:65be27845400 238 {
AnnaBridge 172:65be27845400 239 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 172:65be27845400 240 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
AnnaBridge 172:65be27845400 241 } b; /*!< Structure used for bit access */
AnnaBridge 172:65be27845400 242 uint32_t w; /*!< Type used for word access */
AnnaBridge 172:65be27845400 243 } IPSR_Type;
AnnaBridge 172:65be27845400 244
AnnaBridge 172:65be27845400 245 /* IPSR Register Definitions */
AnnaBridge 172:65be27845400 246 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
AnnaBridge 172:65be27845400 247 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
AnnaBridge 172:65be27845400 248
AnnaBridge 172:65be27845400 249
AnnaBridge 172:65be27845400 250 /**
AnnaBridge 172:65be27845400 251 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge 172:65be27845400 252 */
AnnaBridge 172:65be27845400 253 typedef union
AnnaBridge 172:65be27845400 254 {
AnnaBridge 172:65be27845400 255 struct
AnnaBridge 172:65be27845400 256 {
AnnaBridge 172:65be27845400 257 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
AnnaBridge 172:65be27845400 258 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
AnnaBridge 172:65be27845400 259 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
AnnaBridge 172:65be27845400 260 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
AnnaBridge 172:65be27845400 261 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
AnnaBridge 172:65be27845400 262 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
AnnaBridge 172:65be27845400 263 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
AnnaBridge 172:65be27845400 264 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
AnnaBridge 172:65be27845400 265 } b; /*!< Structure used for bit access */
AnnaBridge 172:65be27845400 266 uint32_t w; /*!< Type used for word access */
AnnaBridge 172:65be27845400 267 } xPSR_Type;
AnnaBridge 172:65be27845400 268
AnnaBridge 172:65be27845400 269 /* xPSR Register Definitions */
AnnaBridge 172:65be27845400 270 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
AnnaBridge 172:65be27845400 271 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
AnnaBridge 172:65be27845400 272
AnnaBridge 172:65be27845400 273 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
AnnaBridge 172:65be27845400 274 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
AnnaBridge 172:65be27845400 275
AnnaBridge 172:65be27845400 276 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
AnnaBridge 172:65be27845400 277 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
AnnaBridge 172:65be27845400 278
AnnaBridge 172:65be27845400 279 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
AnnaBridge 172:65be27845400 280 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
AnnaBridge 172:65be27845400 281
AnnaBridge 172:65be27845400 282 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
AnnaBridge 172:65be27845400 283 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
AnnaBridge 172:65be27845400 284
AnnaBridge 172:65be27845400 285 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
AnnaBridge 172:65be27845400 286 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
AnnaBridge 172:65be27845400 287
AnnaBridge 172:65be27845400 288
AnnaBridge 172:65be27845400 289 /**
AnnaBridge 172:65be27845400 290 \brief Union type to access the Control Registers (CONTROL).
AnnaBridge 172:65be27845400 291 */
AnnaBridge 172:65be27845400 292 typedef union
AnnaBridge 172:65be27845400 293 {
AnnaBridge 172:65be27845400 294 struct
AnnaBridge 172:65be27845400 295 {
AnnaBridge 172:65be27845400 296 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
AnnaBridge 172:65be27845400 297 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
AnnaBridge 172:65be27845400 298 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
AnnaBridge 172:65be27845400 299 } b; /*!< Structure used for bit access */
AnnaBridge 172:65be27845400 300 uint32_t w; /*!< Type used for word access */
AnnaBridge 172:65be27845400 301 } CONTROL_Type;
AnnaBridge 172:65be27845400 302
AnnaBridge 172:65be27845400 303 /* CONTROL Register Definitions */
AnnaBridge 172:65be27845400 304 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
AnnaBridge 172:65be27845400 305 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
AnnaBridge 172:65be27845400 306
AnnaBridge 172:65be27845400 307 /*@} end of group CMSIS_CORE */
AnnaBridge 172:65be27845400 308
AnnaBridge 172:65be27845400 309
AnnaBridge 172:65be27845400 310 /**
AnnaBridge 172:65be27845400 311 \ingroup CMSIS_core_register
AnnaBridge 172:65be27845400 312 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge 172:65be27845400 313 \brief Type definitions for the NVIC Registers
AnnaBridge 172:65be27845400 314 @{
AnnaBridge 172:65be27845400 315 */
AnnaBridge 172:65be27845400 316
AnnaBridge 172:65be27845400 317 /**
AnnaBridge 172:65be27845400 318 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge 172:65be27845400 319 */
AnnaBridge 172:65be27845400 320 typedef struct
AnnaBridge 172:65be27845400 321 {
AnnaBridge 172:65be27845400 322 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
AnnaBridge 172:65be27845400 323 uint32_t RESERVED0[31U];
AnnaBridge 172:65be27845400 324 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
AnnaBridge 172:65be27845400 325 uint32_t RSERVED1[31U];
AnnaBridge 172:65be27845400 326 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
AnnaBridge 172:65be27845400 327 uint32_t RESERVED2[31U];
AnnaBridge 172:65be27845400 328 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
AnnaBridge 172:65be27845400 329 uint32_t RESERVED3[31U];
AnnaBridge 172:65be27845400 330 uint32_t RESERVED4[64U];
AnnaBridge 172:65be27845400 331 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
AnnaBridge 172:65be27845400 332 } NVIC_Type;
AnnaBridge 172:65be27845400 333
AnnaBridge 172:65be27845400 334 /*@} end of group CMSIS_NVIC */
AnnaBridge 172:65be27845400 335
AnnaBridge 172:65be27845400 336
AnnaBridge 172:65be27845400 337 /**
AnnaBridge 172:65be27845400 338 \ingroup CMSIS_core_register
AnnaBridge 172:65be27845400 339 \defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge 172:65be27845400 340 \brief Type definitions for the System Control Block Registers
AnnaBridge 172:65be27845400 341 @{
AnnaBridge 172:65be27845400 342 */
AnnaBridge 172:65be27845400 343
AnnaBridge 172:65be27845400 344 /**
AnnaBridge 172:65be27845400 345 \brief Structure type to access the System Control Block (SCB).
AnnaBridge 172:65be27845400 346 */
AnnaBridge 172:65be27845400 347 typedef struct
AnnaBridge 172:65be27845400 348 {
AnnaBridge 172:65be27845400 349 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
AnnaBridge 172:65be27845400 350 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
AnnaBridge 172:65be27845400 351 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
AnnaBridge 172:65be27845400 352 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
AnnaBridge 172:65be27845400 353 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
AnnaBridge 172:65be27845400 354 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
AnnaBridge 172:65be27845400 355 uint32_t RESERVED0[1U];
AnnaBridge 172:65be27845400 356 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
AnnaBridge 172:65be27845400 357 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
AnnaBridge 172:65be27845400 358 uint32_t RESERVED1[154U];
AnnaBridge 172:65be27845400 359 __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
AnnaBridge 172:65be27845400 360 } SCB_Type;
AnnaBridge 172:65be27845400 361
AnnaBridge 172:65be27845400 362 /* SCB CPUID Register Definitions */
AnnaBridge 172:65be27845400 363 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
AnnaBridge 172:65be27845400 364 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
AnnaBridge 172:65be27845400 365
AnnaBridge 172:65be27845400 366 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
AnnaBridge 172:65be27845400 367 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
AnnaBridge 172:65be27845400 368
AnnaBridge 172:65be27845400 369 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
AnnaBridge 172:65be27845400 370 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
AnnaBridge 172:65be27845400 371
AnnaBridge 172:65be27845400 372 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
AnnaBridge 172:65be27845400 373 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
AnnaBridge 172:65be27845400 374
AnnaBridge 172:65be27845400 375 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
AnnaBridge 172:65be27845400 376 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
AnnaBridge 172:65be27845400 377
AnnaBridge 172:65be27845400 378 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 172:65be27845400 379 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
AnnaBridge 172:65be27845400 380 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
AnnaBridge 172:65be27845400 381
AnnaBridge 172:65be27845400 382 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
AnnaBridge 172:65be27845400 383 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
AnnaBridge 172:65be27845400 384
AnnaBridge 172:65be27845400 385 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
AnnaBridge 172:65be27845400 386 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
AnnaBridge 172:65be27845400 387
AnnaBridge 172:65be27845400 388 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
AnnaBridge 172:65be27845400 389 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
AnnaBridge 172:65be27845400 390
AnnaBridge 172:65be27845400 391 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
AnnaBridge 172:65be27845400 392 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
AnnaBridge 172:65be27845400 393
AnnaBridge 172:65be27845400 394 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
AnnaBridge 172:65be27845400 395 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
AnnaBridge 172:65be27845400 396
AnnaBridge 172:65be27845400 397 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
AnnaBridge 172:65be27845400 398 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
AnnaBridge 172:65be27845400 399
AnnaBridge 172:65be27845400 400 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
AnnaBridge 172:65be27845400 401 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
AnnaBridge 172:65be27845400 402
AnnaBridge 172:65be27845400 403 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
AnnaBridge 172:65be27845400 404 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
AnnaBridge 172:65be27845400 405
AnnaBridge 172:65be27845400 406 /* SCB Interrupt Control State Register Definitions */
AnnaBridge 172:65be27845400 407 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
AnnaBridge 172:65be27845400 408 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
AnnaBridge 172:65be27845400 409
AnnaBridge 172:65be27845400 410 /* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge 172:65be27845400 411 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
AnnaBridge 172:65be27845400 412 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
AnnaBridge 172:65be27845400 413
AnnaBridge 172:65be27845400 414 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
AnnaBridge 172:65be27845400 415 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
AnnaBridge 172:65be27845400 416
AnnaBridge 172:65be27845400 417 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
AnnaBridge 172:65be27845400 418 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
AnnaBridge 172:65be27845400 419
AnnaBridge 172:65be27845400 420 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
AnnaBridge 172:65be27845400 421 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
AnnaBridge 172:65be27845400 422
AnnaBridge 172:65be27845400 423 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
AnnaBridge 172:65be27845400 424 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
AnnaBridge 172:65be27845400 425
AnnaBridge 172:65be27845400 426 /* SCB System Control Register Definitions */
AnnaBridge 172:65be27845400 427 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
AnnaBridge 172:65be27845400 428 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
AnnaBridge 172:65be27845400 429
AnnaBridge 172:65be27845400 430 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
AnnaBridge 172:65be27845400 431 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
AnnaBridge 172:65be27845400 432
AnnaBridge 172:65be27845400 433 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
AnnaBridge 172:65be27845400 434 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
AnnaBridge 172:65be27845400 435
AnnaBridge 172:65be27845400 436 /* SCB Configuration Control Register Definitions */
AnnaBridge 172:65be27845400 437 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
AnnaBridge 172:65be27845400 438 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
AnnaBridge 172:65be27845400 439
AnnaBridge 172:65be27845400 440 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
AnnaBridge 172:65be27845400 441 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
AnnaBridge 172:65be27845400 442
AnnaBridge 172:65be27845400 443 /* SCB System Handler Control and State Register Definitions */
AnnaBridge 172:65be27845400 444 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
AnnaBridge 172:65be27845400 445 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
AnnaBridge 172:65be27845400 446
AnnaBridge 172:65be27845400 447 /*@} end of group CMSIS_SCB */
AnnaBridge 172:65be27845400 448
AnnaBridge 172:65be27845400 449
AnnaBridge 172:65be27845400 450 /**
AnnaBridge 172:65be27845400 451 \ingroup CMSIS_core_register
AnnaBridge 172:65be27845400 452 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
AnnaBridge 172:65be27845400 453 \brief Type definitions for the System Control and ID Register not in the SCB
AnnaBridge 172:65be27845400 454 @{
AnnaBridge 172:65be27845400 455 */
AnnaBridge 172:65be27845400 456
AnnaBridge 172:65be27845400 457 /**
AnnaBridge 172:65be27845400 458 \brief Structure type to access the System Control and ID Register not in the SCB.
AnnaBridge 172:65be27845400 459 */
AnnaBridge 172:65be27845400 460 typedef struct
AnnaBridge 172:65be27845400 461 {
AnnaBridge 172:65be27845400 462 uint32_t RESERVED0[2U];
AnnaBridge 172:65be27845400 463 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
AnnaBridge 172:65be27845400 464 } SCnSCB_Type;
AnnaBridge 172:65be27845400 465
AnnaBridge 172:65be27845400 466 /* Auxiliary Control Register Definitions */
AnnaBridge 172:65be27845400 467 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
AnnaBridge 172:65be27845400 468 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
AnnaBridge 172:65be27845400 469
AnnaBridge 172:65be27845400 470 /*@} end of group CMSIS_SCnotSCB */
AnnaBridge 172:65be27845400 471
AnnaBridge 172:65be27845400 472
AnnaBridge 172:65be27845400 473 /**
AnnaBridge 172:65be27845400 474 \ingroup CMSIS_core_register
AnnaBridge 172:65be27845400 475 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge 172:65be27845400 476 \brief Type definitions for the System Timer Registers.
AnnaBridge 172:65be27845400 477 @{
AnnaBridge 172:65be27845400 478 */
AnnaBridge 172:65be27845400 479
AnnaBridge 172:65be27845400 480 /**
AnnaBridge 172:65be27845400 481 \brief Structure type to access the System Timer (SysTick).
AnnaBridge 172:65be27845400 482 */
AnnaBridge 172:65be27845400 483 typedef struct
AnnaBridge 172:65be27845400 484 {
AnnaBridge 172:65be27845400 485 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
AnnaBridge 172:65be27845400 486 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
AnnaBridge 172:65be27845400 487 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
AnnaBridge 172:65be27845400 488 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
AnnaBridge 172:65be27845400 489 } SysTick_Type;
AnnaBridge 172:65be27845400 490
AnnaBridge 172:65be27845400 491 /* SysTick Control / Status Register Definitions */
AnnaBridge 172:65be27845400 492 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
AnnaBridge 172:65be27845400 493 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
AnnaBridge 172:65be27845400 494
AnnaBridge 172:65be27845400 495 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
AnnaBridge 172:65be27845400 496 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
AnnaBridge 172:65be27845400 497
AnnaBridge 172:65be27845400 498 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
AnnaBridge 172:65be27845400 499 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
AnnaBridge 172:65be27845400 500
AnnaBridge 172:65be27845400 501 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
AnnaBridge 172:65be27845400 502 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
AnnaBridge 172:65be27845400 503
AnnaBridge 172:65be27845400 504 /* SysTick Reload Register Definitions */
AnnaBridge 172:65be27845400 505 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
AnnaBridge 172:65be27845400 506 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
AnnaBridge 172:65be27845400 507
AnnaBridge 172:65be27845400 508 /* SysTick Current Register Definitions */
AnnaBridge 172:65be27845400 509 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
AnnaBridge 172:65be27845400 510 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
AnnaBridge 172:65be27845400 511
AnnaBridge 172:65be27845400 512 /* SysTick Calibration Register Definitions */
AnnaBridge 172:65be27845400 513 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
AnnaBridge 172:65be27845400 514 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
AnnaBridge 172:65be27845400 515
AnnaBridge 172:65be27845400 516 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
AnnaBridge 172:65be27845400 517 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
AnnaBridge 172:65be27845400 518
AnnaBridge 172:65be27845400 519 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
AnnaBridge 172:65be27845400 520 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
AnnaBridge 172:65be27845400 521
AnnaBridge 172:65be27845400 522 /*@} end of group CMSIS_SysTick */
AnnaBridge 172:65be27845400 523
AnnaBridge 172:65be27845400 524 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 172:65be27845400 525 /**
AnnaBridge 172:65be27845400 526 \ingroup CMSIS_core_register
AnnaBridge 172:65be27845400 527 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge 172:65be27845400 528 \brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge 172:65be27845400 529 @{
AnnaBridge 172:65be27845400 530 */
AnnaBridge 172:65be27845400 531
AnnaBridge 172:65be27845400 532 /**
AnnaBridge 172:65be27845400 533 \brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge 172:65be27845400 534 */
AnnaBridge 172:65be27845400 535 typedef struct
AnnaBridge 172:65be27845400 536 {
AnnaBridge 172:65be27845400 537 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
AnnaBridge 172:65be27845400 538 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
AnnaBridge 172:65be27845400 539 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
AnnaBridge 172:65be27845400 540 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
AnnaBridge 172:65be27845400 541 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
AnnaBridge 172:65be27845400 542 } MPU_Type;
AnnaBridge 172:65be27845400 543
AnnaBridge 172:65be27845400 544 /* MPU Type Register Definitions */
AnnaBridge 172:65be27845400 545 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
AnnaBridge 172:65be27845400 546 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
AnnaBridge 172:65be27845400 547
AnnaBridge 172:65be27845400 548 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
AnnaBridge 172:65be27845400 549 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
AnnaBridge 172:65be27845400 550
AnnaBridge 172:65be27845400 551 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
AnnaBridge 172:65be27845400 552 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
AnnaBridge 172:65be27845400 553
AnnaBridge 172:65be27845400 554 /* MPU Control Register Definitions */
AnnaBridge 172:65be27845400 555 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
AnnaBridge 172:65be27845400 556 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
AnnaBridge 172:65be27845400 557
AnnaBridge 172:65be27845400 558 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
AnnaBridge 172:65be27845400 559 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
AnnaBridge 172:65be27845400 560
AnnaBridge 172:65be27845400 561 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
AnnaBridge 172:65be27845400 562 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
AnnaBridge 172:65be27845400 563
AnnaBridge 172:65be27845400 564 /* MPU Region Number Register Definitions */
AnnaBridge 172:65be27845400 565 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
AnnaBridge 172:65be27845400 566 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
AnnaBridge 172:65be27845400 567
AnnaBridge 172:65be27845400 568 /* MPU Region Base Address Register Definitions */
AnnaBridge 172:65be27845400 569 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
AnnaBridge 172:65be27845400 570 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
AnnaBridge 172:65be27845400 571
AnnaBridge 172:65be27845400 572 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
AnnaBridge 172:65be27845400 573 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
AnnaBridge 172:65be27845400 574
AnnaBridge 172:65be27845400 575 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
AnnaBridge 172:65be27845400 576 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
AnnaBridge 172:65be27845400 577
AnnaBridge 172:65be27845400 578 /* MPU Region Attribute and Size Register Definitions */
AnnaBridge 172:65be27845400 579 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
AnnaBridge 172:65be27845400 580 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
AnnaBridge 172:65be27845400 581
AnnaBridge 172:65be27845400 582 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
AnnaBridge 172:65be27845400 583 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
AnnaBridge 172:65be27845400 584
AnnaBridge 172:65be27845400 585 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
AnnaBridge 172:65be27845400 586 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
AnnaBridge 172:65be27845400 587
AnnaBridge 172:65be27845400 588 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
AnnaBridge 172:65be27845400 589 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
AnnaBridge 172:65be27845400 590
AnnaBridge 172:65be27845400 591 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
AnnaBridge 172:65be27845400 592 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
AnnaBridge 172:65be27845400 593
AnnaBridge 172:65be27845400 594 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
AnnaBridge 172:65be27845400 595 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
AnnaBridge 172:65be27845400 596
AnnaBridge 172:65be27845400 597 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
AnnaBridge 172:65be27845400 598 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
AnnaBridge 172:65be27845400 599
AnnaBridge 172:65be27845400 600 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
AnnaBridge 172:65be27845400 601 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
AnnaBridge 172:65be27845400 602
AnnaBridge 172:65be27845400 603 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
AnnaBridge 172:65be27845400 604 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
AnnaBridge 172:65be27845400 605
AnnaBridge 172:65be27845400 606 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
AnnaBridge 172:65be27845400 607 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
AnnaBridge 172:65be27845400 608
AnnaBridge 172:65be27845400 609 /*@} end of group CMSIS_MPU */
AnnaBridge 172:65be27845400 610 #endif
AnnaBridge 172:65be27845400 611
AnnaBridge 172:65be27845400 612
AnnaBridge 172:65be27845400 613 /**
AnnaBridge 172:65be27845400 614 \ingroup CMSIS_core_register
AnnaBridge 172:65be27845400 615 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge 172:65be27845400 616 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
AnnaBridge 172:65be27845400 617 Therefore they are not covered by the SC000 header file.
AnnaBridge 172:65be27845400 618 @{
AnnaBridge 172:65be27845400 619 */
AnnaBridge 172:65be27845400 620 /*@} end of group CMSIS_CoreDebug */
AnnaBridge 172:65be27845400 621
AnnaBridge 172:65be27845400 622
AnnaBridge 172:65be27845400 623 /**
AnnaBridge 172:65be27845400 624 \ingroup CMSIS_core_register
AnnaBridge 172:65be27845400 625 \defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge 172:65be27845400 626 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
AnnaBridge 172:65be27845400 627 @{
AnnaBridge 172:65be27845400 628 */
AnnaBridge 172:65be27845400 629
AnnaBridge 172:65be27845400 630 /**
AnnaBridge 172:65be27845400 631 \brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge 172:65be27845400 632 \param[in] field Name of the register bit field.
AnnaBridge 172:65be27845400 633 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge 172:65be27845400 634 \return Masked and shifted value.
AnnaBridge 172:65be27845400 635 */
AnnaBridge 172:65be27845400 636 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge 172:65be27845400 637
AnnaBridge 172:65be27845400 638 /**
AnnaBridge 172:65be27845400 639 \brief Mask and shift a register value to extract a bit filed value.
AnnaBridge 172:65be27845400 640 \param[in] field Name of the register bit field.
AnnaBridge 172:65be27845400 641 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge 172:65be27845400 642 \return Masked and shifted bit field value.
AnnaBridge 172:65be27845400 643 */
AnnaBridge 172:65be27845400 644 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge 172:65be27845400 645
AnnaBridge 172:65be27845400 646 /*@} end of group CMSIS_core_bitfield */
AnnaBridge 172:65be27845400 647
AnnaBridge 172:65be27845400 648
AnnaBridge 172:65be27845400 649 /**
AnnaBridge 172:65be27845400 650 \ingroup CMSIS_core_register
AnnaBridge 172:65be27845400 651 \defgroup CMSIS_core_base Core Definitions
AnnaBridge 172:65be27845400 652 \brief Definitions for base addresses, unions, and structures.
AnnaBridge 172:65be27845400 653 @{
AnnaBridge 172:65be27845400 654 */
AnnaBridge 172:65be27845400 655
AnnaBridge 172:65be27845400 656 /* Memory mapping of Core Hardware */
AnnaBridge 172:65be27845400 657 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
AnnaBridge 172:65be27845400 658 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
AnnaBridge 172:65be27845400 659 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
AnnaBridge 172:65be27845400 660 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
AnnaBridge 172:65be27845400 661
AnnaBridge 172:65be27845400 662 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
AnnaBridge 172:65be27845400 663 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
AnnaBridge 172:65be27845400 664 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
AnnaBridge 172:65be27845400 665 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
AnnaBridge 172:65be27845400 666
AnnaBridge 172:65be27845400 667 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge 172:65be27845400 668 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
AnnaBridge 172:65be27845400 669 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
AnnaBridge 172:65be27845400 670 #endif
AnnaBridge 172:65be27845400 671
AnnaBridge 172:65be27845400 672 /*@} */
AnnaBridge 172:65be27845400 673
AnnaBridge 172:65be27845400 674
AnnaBridge 172:65be27845400 675
AnnaBridge 172:65be27845400 676 /*******************************************************************************
AnnaBridge 172:65be27845400 677 * Hardware Abstraction Layer
AnnaBridge 172:65be27845400 678 Core Function Interface contains:
AnnaBridge 172:65be27845400 679 - Core NVIC Functions
AnnaBridge 172:65be27845400 680 - Core SysTick Functions
AnnaBridge 172:65be27845400 681 - Core Register Access Functions
AnnaBridge 172:65be27845400 682 ******************************************************************************/
AnnaBridge 172:65be27845400 683 /**
AnnaBridge 172:65be27845400 684 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge 172:65be27845400 685 */
AnnaBridge 172:65be27845400 686
AnnaBridge 172:65be27845400 687
AnnaBridge 172:65be27845400 688
AnnaBridge 172:65be27845400 689 /* ########################## NVIC functions #################################### */
AnnaBridge 172:65be27845400 690 /**
AnnaBridge 172:65be27845400 691 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 172:65be27845400 692 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge 172:65be27845400 693 \brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge 172:65be27845400 694 @{
AnnaBridge 172:65be27845400 695 */
AnnaBridge 172:65be27845400 696
AnnaBridge 172:65be27845400 697 #ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge 172:65be27845400 698 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 172:65be27845400 699 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge 172:65be27845400 700 #endif
AnnaBridge 172:65be27845400 701 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge 172:65be27845400 702 #else
AnnaBridge 172:65be27845400 703 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
AnnaBridge 172:65be27845400 704 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
AnnaBridge 172:65be27845400 705 #define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge 172:65be27845400 706 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge 172:65be27845400 707 #define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge 172:65be27845400 708 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge 172:65be27845400 709 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge 172:65be27845400 710 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge 172:65be27845400 711 /*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
AnnaBridge 172:65be27845400 712 #define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge 172:65be27845400 713 #define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge 172:65be27845400 714 #define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge 172:65be27845400 715 #endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge 172:65be27845400 716
AnnaBridge 172:65be27845400 717 #ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge 172:65be27845400 718 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 172:65be27845400 719 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge 172:65be27845400 720 #endif
AnnaBridge 172:65be27845400 721 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge 172:65be27845400 722 #else
AnnaBridge 172:65be27845400 723 #define NVIC_SetVector __NVIC_SetVector
AnnaBridge 172:65be27845400 724 #define NVIC_GetVector __NVIC_GetVector
AnnaBridge 172:65be27845400 725 #endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge 172:65be27845400 726
AnnaBridge 172:65be27845400 727 #define NVIC_USER_IRQ_OFFSET 16
AnnaBridge 172:65be27845400 728
AnnaBridge 172:65be27845400 729
AnnaBridge 172:65be27845400 730 /* The following EXC_RETURN values are saved the LR on exception entry */
AnnaBridge 172:65be27845400 731 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
AnnaBridge 172:65be27845400 732 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
AnnaBridge 172:65be27845400 733 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
AnnaBridge 172:65be27845400 734
AnnaBridge 172:65be27845400 735
AnnaBridge 172:65be27845400 736 /* Interrupt Priorities are WORD accessible only under Armv6-M */
AnnaBridge 172:65be27845400 737 /* The following MACROS handle generation of the register offset and byte masks */
AnnaBridge 172:65be27845400 738 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
AnnaBridge 172:65be27845400 739 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
AnnaBridge 172:65be27845400 740 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
AnnaBridge 172:65be27845400 741
AnnaBridge 172:65be27845400 742
AnnaBridge 172:65be27845400 743 /**
AnnaBridge 172:65be27845400 744 \brief Enable Interrupt
AnnaBridge 172:65be27845400 745 \details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 172:65be27845400 746 \param [in] IRQn Device specific interrupt number.
AnnaBridge 172:65be27845400 747 \note IRQn must not be negative.
AnnaBridge 172:65be27845400 748 */
AnnaBridge 172:65be27845400 749 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge 172:65be27845400 750 {
AnnaBridge 172:65be27845400 751 if ((int32_t)(IRQn) >= 0)
AnnaBridge 172:65be27845400 752 {
AnnaBridge 172:65be27845400 753 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 172:65be27845400 754 }
AnnaBridge 172:65be27845400 755 }
AnnaBridge 172:65be27845400 756
AnnaBridge 172:65be27845400 757
AnnaBridge 172:65be27845400 758 /**
AnnaBridge 172:65be27845400 759 \brief Get Interrupt Enable status
AnnaBridge 172:65be27845400 760 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge 172:65be27845400 761 \param [in] IRQn Device specific interrupt number.
AnnaBridge 172:65be27845400 762 \return 0 Interrupt is not enabled.
AnnaBridge 172:65be27845400 763 \return 1 Interrupt is enabled.
AnnaBridge 172:65be27845400 764 \note IRQn must not be negative.
AnnaBridge 172:65be27845400 765 */
AnnaBridge 172:65be27845400 766 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge 172:65be27845400 767 {
AnnaBridge 172:65be27845400 768 if ((int32_t)(IRQn) >= 0)
AnnaBridge 172:65be27845400 769 {
AnnaBridge 172:65be27845400 770 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 172:65be27845400 771 }
AnnaBridge 172:65be27845400 772 else
AnnaBridge 172:65be27845400 773 {
AnnaBridge 172:65be27845400 774 return(0U);
AnnaBridge 172:65be27845400 775 }
AnnaBridge 172:65be27845400 776 }
AnnaBridge 172:65be27845400 777
AnnaBridge 172:65be27845400 778
AnnaBridge 172:65be27845400 779 /**
AnnaBridge 172:65be27845400 780 \brief Disable Interrupt
AnnaBridge 172:65be27845400 781 \details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge 172:65be27845400 782 \param [in] IRQn Device specific interrupt number.
AnnaBridge 172:65be27845400 783 \note IRQn must not be negative.
AnnaBridge 172:65be27845400 784 */
AnnaBridge 172:65be27845400 785 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge 172:65be27845400 786 {
AnnaBridge 172:65be27845400 787 if ((int32_t)(IRQn) >= 0)
AnnaBridge 172:65be27845400 788 {
AnnaBridge 172:65be27845400 789 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 172:65be27845400 790 __DSB();
AnnaBridge 172:65be27845400 791 __ISB();
AnnaBridge 172:65be27845400 792 }
AnnaBridge 172:65be27845400 793 }
AnnaBridge 172:65be27845400 794
AnnaBridge 172:65be27845400 795
AnnaBridge 172:65be27845400 796 /**
AnnaBridge 172:65be27845400 797 \brief Get Pending Interrupt
AnnaBridge 172:65be27845400 798 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge 172:65be27845400 799 \param [in] IRQn Device specific interrupt number.
AnnaBridge 172:65be27845400 800 \return 0 Interrupt status is not pending.
AnnaBridge 172:65be27845400 801 \return 1 Interrupt status is pending.
AnnaBridge 172:65be27845400 802 \note IRQn must not be negative.
AnnaBridge 172:65be27845400 803 */
AnnaBridge 172:65be27845400 804 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 172:65be27845400 805 {
AnnaBridge 172:65be27845400 806 if ((int32_t)(IRQn) >= 0)
AnnaBridge 172:65be27845400 807 {
AnnaBridge 172:65be27845400 808 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge 172:65be27845400 809 }
AnnaBridge 172:65be27845400 810 else
AnnaBridge 172:65be27845400 811 {
AnnaBridge 172:65be27845400 812 return(0U);
AnnaBridge 172:65be27845400 813 }
AnnaBridge 172:65be27845400 814 }
AnnaBridge 172:65be27845400 815
AnnaBridge 172:65be27845400 816
AnnaBridge 172:65be27845400 817 /**
AnnaBridge 172:65be27845400 818 \brief Set Pending Interrupt
AnnaBridge 172:65be27845400 819 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 172:65be27845400 820 \param [in] IRQn Device specific interrupt number.
AnnaBridge 172:65be27845400 821 \note IRQn must not be negative.
AnnaBridge 172:65be27845400 822 */
AnnaBridge 172:65be27845400 823 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge 172:65be27845400 824 {
AnnaBridge 172:65be27845400 825 if ((int32_t)(IRQn) >= 0)
AnnaBridge 172:65be27845400 826 {
AnnaBridge 172:65be27845400 827 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 172:65be27845400 828 }
AnnaBridge 172:65be27845400 829 }
AnnaBridge 172:65be27845400 830
AnnaBridge 172:65be27845400 831
AnnaBridge 172:65be27845400 832 /**
AnnaBridge 172:65be27845400 833 \brief Clear Pending Interrupt
AnnaBridge 172:65be27845400 834 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge 172:65be27845400 835 \param [in] IRQn Device specific interrupt number.
AnnaBridge 172:65be27845400 836 \note IRQn must not be negative.
AnnaBridge 172:65be27845400 837 */
AnnaBridge 172:65be27845400 838 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge 172:65be27845400 839 {
AnnaBridge 172:65be27845400 840 if ((int32_t)(IRQn) >= 0)
AnnaBridge 172:65be27845400 841 {
AnnaBridge 172:65be27845400 842 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge 172:65be27845400 843 }
AnnaBridge 172:65be27845400 844 }
AnnaBridge 172:65be27845400 845
AnnaBridge 172:65be27845400 846
AnnaBridge 172:65be27845400 847 /**
AnnaBridge 172:65be27845400 848 \brief Set Interrupt Priority
AnnaBridge 172:65be27845400 849 \details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge 172:65be27845400 850 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 172:65be27845400 851 or negative to specify a processor exception.
AnnaBridge 172:65be27845400 852 \param [in] IRQn Interrupt number.
AnnaBridge 172:65be27845400 853 \param [in] priority Priority to set.
AnnaBridge 172:65be27845400 854 \note The priority cannot be set for every processor exception.
AnnaBridge 172:65be27845400 855 */
AnnaBridge 172:65be27845400 856 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge 172:65be27845400 857 {
AnnaBridge 172:65be27845400 858 if ((int32_t)(IRQn) >= 0)
AnnaBridge 172:65be27845400 859 {
AnnaBridge 172:65be27845400 860 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 172:65be27845400 861 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 172:65be27845400 862 }
AnnaBridge 172:65be27845400 863 else
AnnaBridge 172:65be27845400 864 {
AnnaBridge 172:65be27845400 865 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
AnnaBridge 172:65be27845400 866 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge 172:65be27845400 867 }
AnnaBridge 172:65be27845400 868 }
AnnaBridge 172:65be27845400 869
AnnaBridge 172:65be27845400 870
AnnaBridge 172:65be27845400 871 /**
AnnaBridge 172:65be27845400 872 \brief Get Interrupt Priority
AnnaBridge 172:65be27845400 873 \details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge 172:65be27845400 874 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 172:65be27845400 875 or negative to specify a processor exception.
AnnaBridge 172:65be27845400 876 \param [in] IRQn Interrupt number.
AnnaBridge 172:65be27845400 877 \return Interrupt Priority.
AnnaBridge 172:65be27845400 878 Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge 172:65be27845400 879 */
AnnaBridge 172:65be27845400 880 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge 172:65be27845400 881 {
AnnaBridge 172:65be27845400 882
AnnaBridge 172:65be27845400 883 if ((int32_t)(IRQn) >= 0)
AnnaBridge 172:65be27845400 884 {
AnnaBridge 172:65be27845400 885 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 172:65be27845400 886 }
AnnaBridge 172:65be27845400 887 else
AnnaBridge 172:65be27845400 888 {
AnnaBridge 172:65be27845400 889 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge 172:65be27845400 890 }
AnnaBridge 172:65be27845400 891 }
AnnaBridge 172:65be27845400 892
AnnaBridge 172:65be27845400 893
AnnaBridge 172:65be27845400 894 /**
AnnaBridge 172:65be27845400 895 \brief Set Interrupt Vector
AnnaBridge 172:65be27845400 896 \details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge 172:65be27845400 897 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 172:65be27845400 898 or negative to specify a processor exception.
AnnaBridge 172:65be27845400 899 VTOR must been relocated to SRAM before.
AnnaBridge 172:65be27845400 900 \param [in] IRQn Interrupt number
AnnaBridge 172:65be27845400 901 \param [in] vector Address of interrupt handler function
AnnaBridge 172:65be27845400 902 */
AnnaBridge 172:65be27845400 903 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge 172:65be27845400 904 {
AnnaBridge 172:65be27845400 905 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 172:65be27845400 906 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge 172:65be27845400 907 }
AnnaBridge 172:65be27845400 908
AnnaBridge 172:65be27845400 909
AnnaBridge 172:65be27845400 910 /**
AnnaBridge 172:65be27845400 911 \brief Get Interrupt Vector
AnnaBridge 172:65be27845400 912 \details Reads an interrupt vector from interrupt vector table.
AnnaBridge 172:65be27845400 913 The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge 172:65be27845400 914 or negative to specify a processor exception.
AnnaBridge 172:65be27845400 915 \param [in] IRQn Interrupt number.
AnnaBridge 172:65be27845400 916 \return Address of interrupt handler function
AnnaBridge 172:65be27845400 917 */
AnnaBridge 172:65be27845400 918 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge 172:65be27845400 919 {
AnnaBridge 172:65be27845400 920 uint32_t *vectors = (uint32_t *)SCB->VTOR;
AnnaBridge 172:65be27845400 921 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge 172:65be27845400 922 }
AnnaBridge 172:65be27845400 923
AnnaBridge 172:65be27845400 924
AnnaBridge 172:65be27845400 925 /**
AnnaBridge 172:65be27845400 926 \brief System Reset
AnnaBridge 172:65be27845400 927 \details Initiates a system reset request to reset the MCU.
AnnaBridge 172:65be27845400 928 */
AnnaBridge 172:65be27845400 929 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge 172:65be27845400 930 {
AnnaBridge 172:65be27845400 931 __DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge 172:65be27845400 932 buffered write are completed before reset */
AnnaBridge 172:65be27845400 933 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
AnnaBridge 172:65be27845400 934 SCB_AIRCR_SYSRESETREQ_Msk);
AnnaBridge 172:65be27845400 935 __DSB(); /* Ensure completion of memory access */
AnnaBridge 172:65be27845400 936
AnnaBridge 172:65be27845400 937 for(;;) /* wait until reset */
AnnaBridge 172:65be27845400 938 {
AnnaBridge 172:65be27845400 939 __NOP();
AnnaBridge 172:65be27845400 940 }
AnnaBridge 172:65be27845400 941 }
AnnaBridge 172:65be27845400 942
AnnaBridge 172:65be27845400 943 /*@} end of CMSIS_Core_NVICFunctions */
AnnaBridge 172:65be27845400 944
AnnaBridge 172:65be27845400 945
AnnaBridge 172:65be27845400 946 /* ########################## FPU functions #################################### */
AnnaBridge 172:65be27845400 947 /**
AnnaBridge 172:65be27845400 948 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 172:65be27845400 949 \defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge 172:65be27845400 950 \brief Function that provides FPU type.
AnnaBridge 172:65be27845400 951 @{
AnnaBridge 172:65be27845400 952 */
AnnaBridge 172:65be27845400 953
AnnaBridge 172:65be27845400 954 /**
AnnaBridge 172:65be27845400 955 \brief get FPU type
AnnaBridge 172:65be27845400 956 \details returns the FPU type
AnnaBridge 172:65be27845400 957 \returns
AnnaBridge 172:65be27845400 958 - \b 0: No FPU
AnnaBridge 172:65be27845400 959 - \b 1: Single precision FPU
AnnaBridge 172:65be27845400 960 - \b 2: Double + Single precision FPU
AnnaBridge 172:65be27845400 961 */
AnnaBridge 172:65be27845400 962 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge 172:65be27845400 963 {
AnnaBridge 172:65be27845400 964 return 0U; /* No FPU */
AnnaBridge 172:65be27845400 965 }
AnnaBridge 172:65be27845400 966
AnnaBridge 172:65be27845400 967
AnnaBridge 172:65be27845400 968 /*@} end of CMSIS_Core_FpuFunctions */
AnnaBridge 172:65be27845400 969
AnnaBridge 172:65be27845400 970
AnnaBridge 172:65be27845400 971
AnnaBridge 172:65be27845400 972 /* ################################## SysTick function ############################################ */
AnnaBridge 172:65be27845400 973 /**
AnnaBridge 172:65be27845400 974 \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 172:65be27845400 975 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge 172:65be27845400 976 \brief Functions that configure the System.
AnnaBridge 172:65be27845400 977 @{
AnnaBridge 172:65be27845400 978 */
AnnaBridge 172:65be27845400 979
AnnaBridge 172:65be27845400 980 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge 172:65be27845400 981
AnnaBridge 172:65be27845400 982 /**
AnnaBridge 172:65be27845400 983 \brief System Tick Configuration
AnnaBridge 172:65be27845400 984 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge 172:65be27845400 985 Counter is in free running mode to generate periodic interrupts.
AnnaBridge 172:65be27845400 986 \param [in] ticks Number of ticks between two interrupts.
AnnaBridge 172:65be27845400 987 \return 0 Function succeeded.
AnnaBridge 172:65be27845400 988 \return 1 Function failed.
AnnaBridge 172:65be27845400 989 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge 172:65be27845400 990 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge 172:65be27845400 991 must contain a vendor-specific implementation of this function.
AnnaBridge 172:65be27845400 992 */
AnnaBridge 172:65be27845400 993 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge 172:65be27845400 994 {
AnnaBridge 172:65be27845400 995 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge 172:65be27845400 996 {
AnnaBridge 172:65be27845400 997 return (1UL); /* Reload value impossible */
AnnaBridge 172:65be27845400 998 }
AnnaBridge 172:65be27845400 999
AnnaBridge 172:65be27845400 1000 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge 172:65be27845400 1001 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge 172:65be27845400 1002 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge 172:65be27845400 1003 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
AnnaBridge 172:65be27845400 1004 SysTick_CTRL_TICKINT_Msk |
AnnaBridge 172:65be27845400 1005 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge 172:65be27845400 1006 return (0UL); /* Function successful */
AnnaBridge 172:65be27845400 1007 }
AnnaBridge 172:65be27845400 1008
AnnaBridge 172:65be27845400 1009 #endif
AnnaBridge 172:65be27845400 1010
AnnaBridge 172:65be27845400 1011 /*@} end of CMSIS_Core_SysTickFunctions */
AnnaBridge 172:65be27845400 1012
AnnaBridge 172:65be27845400 1013
AnnaBridge 172:65be27845400 1014
AnnaBridge 172:65be27845400 1015
AnnaBridge 172:65be27845400 1016 #ifdef __cplusplus
AnnaBridge 172:65be27845400 1017 }
AnnaBridge 172:65be27845400 1018 #endif
AnnaBridge 172:65be27845400 1019
AnnaBridge 172:65be27845400 1020 #endif /* __CORE_SC000_H_DEPENDANT */
AnnaBridge 172:65be27845400 1021
AnnaBridge 172:65be27845400 1022 #endif /* __CMSIS_GENERIC */