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TARGET_NUCLEO_H743ZI/TOOLCHAIN_ARM_MICRO/core_cm23.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	172:65be27845400	1	/************************************************************************//
AnnaBridge	172:65be27845400	2	* @file core_cm23.h
AnnaBridge	172:65be27845400	3	* @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
AnnaBridge	172:65be27845400	4	* @version V5.0.7
AnnaBridge	172:65be27845400	5	* @date 22. June 2018
AnnaBridge	172:65be27845400	6	******************************************************************************/
AnnaBridge	172:65be27845400	7	/*
AnnaBridge	172:65be27845400	8	* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
AnnaBridge	172:65be27845400	9	*
AnnaBridge	172:65be27845400	10	* SPDX-License-Identifier: Apache-2.0
AnnaBridge	172:65be27845400	11	*
AnnaBridge	172:65be27845400	12	* Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge	172:65be27845400	13	* not use this file except in compliance with the License.
AnnaBridge	172:65be27845400	14	* You may obtain a copy of the License at
AnnaBridge	172:65be27845400	15	*
AnnaBridge	172:65be27845400	16	* www.apache.org/licenses/LICENSE-2.0
AnnaBridge	172:65be27845400	17	*
AnnaBridge	172:65be27845400	18	* Unless required by applicable law or agreed to in writing, software
AnnaBridge	172:65be27845400	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge	172:65be27845400	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge	172:65be27845400	21	* See the License for the specific language governing permissions and
AnnaBridge	172:65be27845400	22	* limitations under the License.
AnnaBridge	172:65be27845400	23	*/
AnnaBridge	172:65be27845400	24
AnnaBridge	172:65be27845400	25	#if defined ( __ICCARM__ )
AnnaBridge	172:65be27845400	26	#pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge	172:65be27845400	27	#elif defined (__clang__)
AnnaBridge	172:65be27845400	28	#pragma clang system_header /* treat file as system include file */
AnnaBridge	172:65be27845400	29	#endif
AnnaBridge	172:65be27845400	30
AnnaBridge	172:65be27845400	31	#ifndef __CORE_CM23_H_GENERIC
AnnaBridge	172:65be27845400	32	#define __CORE_CM23_H_GENERIC
AnnaBridge	172:65be27845400	33
AnnaBridge	172:65be27845400	34	#include <stdint.h>
AnnaBridge	172:65be27845400	35
AnnaBridge	172:65be27845400	36	#ifdef __cplusplus
AnnaBridge	172:65be27845400	37	extern "C" {
AnnaBridge	172:65be27845400	38	#endif
AnnaBridge	172:65be27845400	39
AnnaBridge	172:65be27845400	40	/**
AnnaBridge	172:65be27845400	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
AnnaBridge	172:65be27845400	42	CMSIS violates the following MISRA-C:2004 rules:
AnnaBridge	172:65be27845400	43
AnnaBridge	172:65be27845400	44	\li Required Rule 8.5, object/function definition in header file.<br>
AnnaBridge	172:65be27845400	45	Function definitions in header files are used to allow 'inlining'.
AnnaBridge	172:65be27845400	46
AnnaBridge	172:65be27845400	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
AnnaBridge	172:65be27845400	48	Unions are used for effective representation of core registers.
AnnaBridge	172:65be27845400	49
AnnaBridge	172:65be27845400	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
AnnaBridge	172:65be27845400	51	Function-like macros are used to allow more efficient code.
AnnaBridge	172:65be27845400	52	*/
AnnaBridge	172:65be27845400	53
AnnaBridge	172:65be27845400	54
AnnaBridge	172:65be27845400	55	/*******************************************************************************
AnnaBridge	172:65be27845400	56	* CMSIS definitions
AnnaBridge	172:65be27845400	57	******************************************************************************/
AnnaBridge	172:65be27845400	58	/**
AnnaBridge	172:65be27845400	59	\ingroup Cortex_M23
AnnaBridge	172:65be27845400	60	@{
AnnaBridge	172:65be27845400	61	*/
AnnaBridge	172:65be27845400	62
AnnaBridge	172:65be27845400	63	#include "cmsis_version.h"
AnnaBridge	172:65be27845400	64
AnnaBridge	172:65be27845400	65	/* CMSIS definitions */
AnnaBridge	172:65be27845400	66	#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /!< \deprecated [31:16] CMSIS HAL main version /
AnnaBridge	172:65be27845400	67	#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /!< \deprecated [15:0] CMSIS HAL sub version /
AnnaBridge	172:65be27845400	68	#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) \| \
AnnaBridge	172:65be27845400	69	__CM23_CMSIS_VERSION_SUB ) /!< \deprecated CMSIS HAL version number /
AnnaBridge	172:65be27845400	70
AnnaBridge	172:65be27845400	71	#define __CORTEX_M (23U) /!< Cortex-M Core /
AnnaBridge	172:65be27845400	72
AnnaBridge	172:65be27845400	73	/** __FPU_USED indicates whether an FPU is used or not.
AnnaBridge	172:65be27845400	74	This core does not support an FPU at all
AnnaBridge	172:65be27845400	75	*/
AnnaBridge	172:65be27845400	76	#define __FPU_USED 0U
AnnaBridge	172:65be27845400	77
AnnaBridge	172:65be27845400	78	#if defined ( __CC_ARM )
AnnaBridge	172:65be27845400	79	#if defined __TARGET_FPU_VFP
AnnaBridge	172:65be27845400	80	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	172:65be27845400	81	#endif
AnnaBridge	172:65be27845400	82
AnnaBridge	172:65be27845400	83	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge	172:65be27845400	84	#if defined __ARM_FP
AnnaBridge	172:65be27845400	85	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	172:65be27845400	86	#endif
AnnaBridge	172:65be27845400	87
AnnaBridge	172:65be27845400	88	#elif defined ( __GNUC__ )
AnnaBridge	172:65be27845400	89	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge	172:65be27845400	90	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	172:65be27845400	91	#endif
AnnaBridge	172:65be27845400	92
AnnaBridge	172:65be27845400	93	#elif defined ( __ICCARM__ )
AnnaBridge	172:65be27845400	94	#if defined __ARMVFP__
AnnaBridge	172:65be27845400	95	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	172:65be27845400	96	#endif
AnnaBridge	172:65be27845400	97
AnnaBridge	172:65be27845400	98	#elif defined ( __TI_ARM__ )
AnnaBridge	172:65be27845400	99	#if defined __TI_VFP_SUPPORT__
AnnaBridge	172:65be27845400	100	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	172:65be27845400	101	#endif
AnnaBridge	172:65be27845400	102
AnnaBridge	172:65be27845400	103	#elif defined ( __TASKING__ )
AnnaBridge	172:65be27845400	104	#if defined __FPU_VFP__
AnnaBridge	172:65be27845400	105	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	172:65be27845400	106	#endif
AnnaBridge	172:65be27845400	107
AnnaBridge	172:65be27845400	108	#elif defined ( __CSMC__ )
AnnaBridge	172:65be27845400	109	#if ( __CSMC__ & 0x400U)
AnnaBridge	172:65be27845400	110	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	172:65be27845400	111	#endif
AnnaBridge	172:65be27845400	112
AnnaBridge	172:65be27845400	113	#endif
AnnaBridge	172:65be27845400	114
AnnaBridge	172:65be27845400	115	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge	172:65be27845400	116
AnnaBridge	172:65be27845400	117
AnnaBridge	172:65be27845400	118	#ifdef __cplusplus
AnnaBridge	172:65be27845400	119	}
AnnaBridge	172:65be27845400	120	#endif
AnnaBridge	172:65be27845400	121
AnnaBridge	172:65be27845400	122	#endif /* __CORE_CM23_H_GENERIC */
AnnaBridge	172:65be27845400	123
AnnaBridge	172:65be27845400	124	#ifndef __CMSIS_GENERIC
AnnaBridge	172:65be27845400	125
AnnaBridge	172:65be27845400	126	#ifndef __CORE_CM23_H_DEPENDANT
AnnaBridge	172:65be27845400	127	#define __CORE_CM23_H_DEPENDANT
AnnaBridge	172:65be27845400	128
AnnaBridge	172:65be27845400	129	#ifdef __cplusplus
AnnaBridge	172:65be27845400	130	extern "C" {
AnnaBridge	172:65be27845400	131	#endif
AnnaBridge	172:65be27845400	132
AnnaBridge	172:65be27845400	133	/* check device defines and use defaults */
AnnaBridge	172:65be27845400	134	#if defined __CHECK_DEVICE_DEFINES
AnnaBridge	172:65be27845400	135	#ifndef __CM23_REV
AnnaBridge	172:65be27845400	136	#define __CM23_REV 0x0000U
AnnaBridge	172:65be27845400	137	#warning "__CM23_REV not defined in device header file; using default!"
AnnaBridge	172:65be27845400	138	#endif
AnnaBridge	172:65be27845400	139
AnnaBridge	172:65be27845400	140	#ifndef __FPU_PRESENT
AnnaBridge	172:65be27845400	141	#define __FPU_PRESENT 0U
AnnaBridge	172:65be27845400	142	#warning "__FPU_PRESENT not defined in device header file; using default!"
AnnaBridge	172:65be27845400	143	#endif
AnnaBridge	172:65be27845400	144
AnnaBridge	172:65be27845400	145	#ifndef __MPU_PRESENT
AnnaBridge	172:65be27845400	146	#define __MPU_PRESENT 0U
AnnaBridge	172:65be27845400	147	#warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge	172:65be27845400	148	#endif
AnnaBridge	172:65be27845400	149
AnnaBridge	172:65be27845400	150	#ifndef __SAUREGION_PRESENT
AnnaBridge	172:65be27845400	151	#define __SAUREGION_PRESENT 0U
AnnaBridge	172:65be27845400	152	#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
AnnaBridge	172:65be27845400	153	#endif
AnnaBridge	172:65be27845400	154
AnnaBridge	172:65be27845400	155	#ifndef __VTOR_PRESENT
AnnaBridge	172:65be27845400	156	#define __VTOR_PRESENT 0U
AnnaBridge	172:65be27845400	157	#warning "__VTOR_PRESENT not defined in device header file; using default!"
AnnaBridge	172:65be27845400	158	#endif
AnnaBridge	172:65be27845400	159
AnnaBridge	172:65be27845400	160	#ifndef __NVIC_PRIO_BITS
AnnaBridge	172:65be27845400	161	#define __NVIC_PRIO_BITS 2U
AnnaBridge	172:65be27845400	162	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
AnnaBridge	172:65be27845400	163	#endif
AnnaBridge	172:65be27845400	164
AnnaBridge	172:65be27845400	165	#ifndef __Vendor_SysTickConfig
AnnaBridge	172:65be27845400	166	#define __Vendor_SysTickConfig 0U
AnnaBridge	172:65be27845400	167	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
AnnaBridge	172:65be27845400	168	#endif
AnnaBridge	172:65be27845400	169
AnnaBridge	172:65be27845400	170	#ifndef __ETM_PRESENT
AnnaBridge	172:65be27845400	171	#define __ETM_PRESENT 0U
AnnaBridge	172:65be27845400	172	#warning "__ETM_PRESENT not defined in device header file; using default!"
AnnaBridge	172:65be27845400	173	#endif
AnnaBridge	172:65be27845400	174
AnnaBridge	172:65be27845400	175	#ifndef __MTB_PRESENT
AnnaBridge	172:65be27845400	176	#define __MTB_PRESENT 0U
AnnaBridge	172:65be27845400	177	#warning "__MTB_PRESENT not defined in device header file; using default!"
AnnaBridge	172:65be27845400	178	#endif
AnnaBridge	172:65be27845400	179
AnnaBridge	172:65be27845400	180	#endif
AnnaBridge	172:65be27845400	181
AnnaBridge	172:65be27845400	182	/* IO definitions (access restrictions to peripheral registers) */
AnnaBridge	172:65be27845400	183	/**
AnnaBridge	172:65be27845400	184	\defgroup CMSIS_glob_defs CMSIS Global Defines
AnnaBridge	172:65be27845400	185
AnnaBridge	172:65be27845400	186	<strong>IO Type Qualifiers</strong> are used
AnnaBridge	172:65be27845400	187	\li to specify the access to peripheral variables.
AnnaBridge	172:65be27845400	188	\li for automatic generation of peripheral register debug information.
AnnaBridge	172:65be27845400	189	*/
AnnaBridge	172:65be27845400	190	#ifdef __cplusplus
AnnaBridge	172:65be27845400	191	#define __I volatile /!< Defines 'read only' permissions /
AnnaBridge	172:65be27845400	192	#else
AnnaBridge	172:65be27845400	193	#define __I volatile const /!< Defines 'read only' permissions /
AnnaBridge	172:65be27845400	194	#endif
AnnaBridge	172:65be27845400	195	#define __O volatile /!< Defines 'write only' permissions /
AnnaBridge	172:65be27845400	196	#define __IO volatile /!< Defines 'read / write' permissions /
AnnaBridge	172:65be27845400	197
AnnaBridge	172:65be27845400	198	/* following defines should be used for structure members */
AnnaBridge	172:65be27845400	199	#define __IM volatile const /! Defines 'read only' structure member permissions /
AnnaBridge	172:65be27845400	200	#define __OM volatile /! Defines 'write only' structure member permissions /
AnnaBridge	172:65be27845400	201	#define __IOM volatile /! Defines 'read / write' structure member permissions /
AnnaBridge	172:65be27845400	202
AnnaBridge	172:65be27845400	203	/@} end of group Cortex_M23 /
AnnaBridge	172:65be27845400	204
AnnaBridge	172:65be27845400	205
AnnaBridge	172:65be27845400	206
AnnaBridge	172:65be27845400	207	/*******************************************************************************
AnnaBridge	172:65be27845400	208	* Register Abstraction
AnnaBridge	172:65be27845400	209	Core Register contain:
AnnaBridge	172:65be27845400	210	- Core Register
AnnaBridge	172:65be27845400	211	- Core NVIC Register
AnnaBridge	172:65be27845400	212	- Core SCB Register
AnnaBridge	172:65be27845400	213	- Core SysTick Register
AnnaBridge	172:65be27845400	214	- Core Debug Register
AnnaBridge	172:65be27845400	215	- Core MPU Register
AnnaBridge	172:65be27845400	216	- Core SAU Register
AnnaBridge	172:65be27845400	217	******************************************************************************/
AnnaBridge	172:65be27845400	218	/**
AnnaBridge	172:65be27845400	219	\defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge	172:65be27845400	220	\brief Type definitions and defines for Cortex-M processor based devices.
AnnaBridge	172:65be27845400	221	*/
AnnaBridge	172:65be27845400	222
AnnaBridge	172:65be27845400	223	/**
AnnaBridge	172:65be27845400	224	\ingroup CMSIS_core_register
AnnaBridge	172:65be27845400	225	\defgroup CMSIS_CORE Status and Control Registers
AnnaBridge	172:65be27845400	226	\brief Core Register type definitions.
AnnaBridge	172:65be27845400	227	@{
AnnaBridge	172:65be27845400	228	*/
AnnaBridge	172:65be27845400	229
AnnaBridge	172:65be27845400	230	/**
AnnaBridge	172:65be27845400	231	\brief Union type to access the Application Program Status Register (APSR).
AnnaBridge	172:65be27845400	232	*/
AnnaBridge	172:65be27845400	233	typedef union
AnnaBridge	172:65be27845400	234	{
AnnaBridge	172:65be27845400	235	struct
AnnaBridge	172:65be27845400	236	{
AnnaBridge	172:65be27845400	237	uint32_t _reserved0:28; /!< bit: 0..27 Reserved /
AnnaBridge	172:65be27845400	238	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	172:65be27845400	239	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	172:65be27845400	240	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	172:65be27845400	241	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	172:65be27845400	242	} b; /!< Structure used for bit access /
AnnaBridge	172:65be27845400	243	uint32_t w; /!< Type used for word access /
AnnaBridge	172:65be27845400	244	} APSR_Type;
AnnaBridge	172:65be27845400	245
AnnaBridge	172:65be27845400	246	/* APSR Register Definitions */
AnnaBridge	172:65be27845400	247	#define APSR_N_Pos 31U /!< APSR: N Position /
AnnaBridge	172:65be27845400	248	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
AnnaBridge	172:65be27845400	249
AnnaBridge	172:65be27845400	250	#define APSR_Z_Pos 30U /!< APSR: Z Position /
AnnaBridge	172:65be27845400	251	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
AnnaBridge	172:65be27845400	252
AnnaBridge	172:65be27845400	253	#define APSR_C_Pos 29U /!< APSR: C Position /
AnnaBridge	172:65be27845400	254	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
AnnaBridge	172:65be27845400	255
AnnaBridge	172:65be27845400	256	#define APSR_V_Pos 28U /!< APSR: V Position /
AnnaBridge	172:65be27845400	257	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
AnnaBridge	172:65be27845400	258
AnnaBridge	172:65be27845400	259
AnnaBridge	172:65be27845400	260	/**
AnnaBridge	172:65be27845400	261	\brief Union type to access the Interrupt Program Status Register (IPSR).
AnnaBridge	172:65be27845400	262	*/
AnnaBridge	172:65be27845400	263	typedef union
AnnaBridge	172:65be27845400	264	{
AnnaBridge	172:65be27845400	265	struct
AnnaBridge	172:65be27845400	266	{
AnnaBridge	172:65be27845400	267	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	172:65be27845400	268	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
AnnaBridge	172:65be27845400	269	} b; /!< Structure used for bit access /
AnnaBridge	172:65be27845400	270	uint32_t w; /!< Type used for word access /
AnnaBridge	172:65be27845400	271	} IPSR_Type;
AnnaBridge	172:65be27845400	272
AnnaBridge	172:65be27845400	273	/* IPSR Register Definitions */
AnnaBridge	172:65be27845400	274	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
AnnaBridge	172:65be27845400	275	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
AnnaBridge	172:65be27845400	276
AnnaBridge	172:65be27845400	277
AnnaBridge	172:65be27845400	278	/**
AnnaBridge	172:65be27845400	279	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
AnnaBridge	172:65be27845400	280	*/
AnnaBridge	172:65be27845400	281	typedef union
AnnaBridge	172:65be27845400	282	{
AnnaBridge	172:65be27845400	283	struct
AnnaBridge	172:65be27845400	284	{
AnnaBridge	172:65be27845400	285	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	172:65be27845400	286	uint32_t _reserved0:15; /!< bit: 9..23 Reserved /
AnnaBridge	172:65be27845400	287	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
AnnaBridge	172:65be27845400	288	uint32_t _reserved1:3; /!< bit: 25..27 Reserved /
AnnaBridge	172:65be27845400	289	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	172:65be27845400	290	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	172:65be27845400	291	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	172:65be27845400	292	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	172:65be27845400	293	} b; /!< Structure used for bit access /
AnnaBridge	172:65be27845400	294	uint32_t w; /!< Type used for word access /
AnnaBridge	172:65be27845400	295	} xPSR_Type;
AnnaBridge	172:65be27845400	296
AnnaBridge	172:65be27845400	297	/* xPSR Register Definitions */
AnnaBridge	172:65be27845400	298	#define xPSR_N_Pos 31U /!< xPSR: N Position /
AnnaBridge	172:65be27845400	299	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
AnnaBridge	172:65be27845400	300
AnnaBridge	172:65be27845400	301	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
AnnaBridge	172:65be27845400	302	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
AnnaBridge	172:65be27845400	303
AnnaBridge	172:65be27845400	304	#define xPSR_C_Pos 29U /!< xPSR: C Position /
AnnaBridge	172:65be27845400	305	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
AnnaBridge	172:65be27845400	306
AnnaBridge	172:65be27845400	307	#define xPSR_V_Pos 28U /!< xPSR: V Position /
AnnaBridge	172:65be27845400	308	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
AnnaBridge	172:65be27845400	309
AnnaBridge	172:65be27845400	310	#define xPSR_T_Pos 24U /!< xPSR: T Position /
AnnaBridge	172:65be27845400	311	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
AnnaBridge	172:65be27845400	312
AnnaBridge	172:65be27845400	313	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
AnnaBridge	172:65be27845400	314	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
AnnaBridge	172:65be27845400	315
AnnaBridge	172:65be27845400	316
AnnaBridge	172:65be27845400	317	/**
AnnaBridge	172:65be27845400	318	\brief Union type to access the Control Registers (CONTROL).
AnnaBridge	172:65be27845400	319	*/
AnnaBridge	172:65be27845400	320	typedef union
AnnaBridge	172:65be27845400	321	{
AnnaBridge	172:65be27845400	322	struct
AnnaBridge	172:65be27845400	323	{
AnnaBridge	172:65be27845400	324	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
AnnaBridge	172:65be27845400	325	uint32_t SPSEL:1; /!< bit: 1 Stack-pointer select /
AnnaBridge	172:65be27845400	326	uint32_t _reserved1:30; /!< bit: 2..31 Reserved /
AnnaBridge	172:65be27845400	327	} b; /!< Structure used for bit access /
AnnaBridge	172:65be27845400	328	uint32_t w; /!< Type used for word access /
AnnaBridge	172:65be27845400	329	} CONTROL_Type;
AnnaBridge	172:65be27845400	330
AnnaBridge	172:65be27845400	331	/* CONTROL Register Definitions */
AnnaBridge	172:65be27845400	332	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
AnnaBridge	172:65be27845400	333	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
AnnaBridge	172:65be27845400	334
AnnaBridge	172:65be27845400	335	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
AnnaBridge	172:65be27845400	336	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
AnnaBridge	172:65be27845400	337
AnnaBridge	172:65be27845400	338	/@} end of group CMSIS_CORE /
AnnaBridge	172:65be27845400	339
AnnaBridge	172:65be27845400	340
AnnaBridge	172:65be27845400	341	/**
AnnaBridge	172:65be27845400	342	\ingroup CMSIS_core_register
AnnaBridge	172:65be27845400	343	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge	172:65be27845400	344	\brief Type definitions for the NVIC Registers
AnnaBridge	172:65be27845400	345	@{
AnnaBridge	172:65be27845400	346	*/
AnnaBridge	172:65be27845400	347
AnnaBridge	172:65be27845400	348	/**
AnnaBridge	172:65be27845400	349	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
AnnaBridge	172:65be27845400	350	*/
AnnaBridge	172:65be27845400	351	typedef struct
AnnaBridge	172:65be27845400	352	{
AnnaBridge	172:65be27845400	353	__IOM uint32_t ISER[16U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
AnnaBridge	172:65be27845400	354	uint32_t RESERVED0[16U];
AnnaBridge	172:65be27845400	355	__IOM uint32_t ICER[16U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
AnnaBridge	172:65be27845400	356	uint32_t RSERVED1[16U];
AnnaBridge	172:65be27845400	357	__IOM uint32_t ISPR[16U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
AnnaBridge	172:65be27845400	358	uint32_t RESERVED2[16U];
AnnaBridge	172:65be27845400	359	__IOM uint32_t ICPR[16U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
AnnaBridge	172:65be27845400	360	uint32_t RESERVED3[16U];
AnnaBridge	172:65be27845400	361	__IOM uint32_t IABR[16U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
AnnaBridge	172:65be27845400	362	uint32_t RESERVED4[16U];
AnnaBridge	172:65be27845400	363	__IOM uint32_t ITNS[16U]; /!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register /
AnnaBridge	172:65be27845400	364	uint32_t RESERVED5[16U];
AnnaBridge	172:65be27845400	365	__IOM uint32_t IPR[124U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register /
AnnaBridge	172:65be27845400	366	} NVIC_Type;
AnnaBridge	172:65be27845400	367
AnnaBridge	172:65be27845400	368	/@} end of group CMSIS_NVIC /
AnnaBridge	172:65be27845400	369
AnnaBridge	172:65be27845400	370
AnnaBridge	172:65be27845400	371	/**
AnnaBridge	172:65be27845400	372	\ingroup CMSIS_core_register
AnnaBridge	172:65be27845400	373	\defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge	172:65be27845400	374	\brief Type definitions for the System Control Block Registers
AnnaBridge	172:65be27845400	375	@{
AnnaBridge	172:65be27845400	376	*/
AnnaBridge	172:65be27845400	377
AnnaBridge	172:65be27845400	378	/**
AnnaBridge	172:65be27845400	379	\brief Structure type to access the System Control Block (SCB).
AnnaBridge	172:65be27845400	380	*/
AnnaBridge	172:65be27845400	381	typedef struct
AnnaBridge	172:65be27845400	382	{
AnnaBridge	172:65be27845400	383	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
AnnaBridge	172:65be27845400	384	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
AnnaBridge	172:65be27845400	385	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge	172:65be27845400	386	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
AnnaBridge	172:65be27845400	387	#else
AnnaBridge	172:65be27845400	388	uint32_t RESERVED0;
AnnaBridge	172:65be27845400	389	#endif
AnnaBridge	172:65be27845400	390	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
AnnaBridge	172:65be27845400	391	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
AnnaBridge	172:65be27845400	392	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
AnnaBridge	172:65be27845400	393	uint32_t RESERVED1;
AnnaBridge	172:65be27845400	394	__IOM uint32_t SHPR[2U]; /!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED /
AnnaBridge	172:65be27845400	395	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
AnnaBridge	172:65be27845400	396	} SCB_Type;
AnnaBridge	172:65be27845400	397
AnnaBridge	172:65be27845400	398	/* SCB CPUID Register Definitions */
AnnaBridge	172:65be27845400	399	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
AnnaBridge	172:65be27845400	400	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
AnnaBridge	172:65be27845400	401
AnnaBridge	172:65be27845400	402	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
AnnaBridge	172:65be27845400	403	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
AnnaBridge	172:65be27845400	404
AnnaBridge	172:65be27845400	405	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
AnnaBridge	172:65be27845400	406	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
AnnaBridge	172:65be27845400	407
AnnaBridge	172:65be27845400	408	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
AnnaBridge	172:65be27845400	409	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
AnnaBridge	172:65be27845400	410
AnnaBridge	172:65be27845400	411	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
AnnaBridge	172:65be27845400	412	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
AnnaBridge	172:65be27845400	413
AnnaBridge	172:65be27845400	414	/* SCB Interrupt Control State Register Definitions */
AnnaBridge	172:65be27845400	415	#define SCB_ICSR_PENDNMISET_Pos 31U /!< SCB ICSR: PENDNMISET Position /
AnnaBridge	172:65be27845400	416	#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /!< SCB ICSR: PENDNMISET Mask /
AnnaBridge	172:65be27845400	417
AnnaBridge	172:65be27845400	418	#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /!< SCB ICSR: NMIPENDSET Position, backward compatibility /
AnnaBridge	172:65be27845400	419	#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /!< SCB ICSR: NMIPENDSET Mask, backward compatibility /
AnnaBridge	172:65be27845400	420
AnnaBridge	172:65be27845400	421	#define SCB_ICSR_PENDNMICLR_Pos 30U /!< SCB ICSR: PENDNMICLR Position /
AnnaBridge	172:65be27845400	422	#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /!< SCB ICSR: PENDNMICLR Mask /
AnnaBridge	172:65be27845400	423
AnnaBridge	172:65be27845400	424	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
AnnaBridge	172:65be27845400	425	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
AnnaBridge	172:65be27845400	426
AnnaBridge	172:65be27845400	427	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
AnnaBridge	172:65be27845400	428	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
AnnaBridge	172:65be27845400	429
AnnaBridge	172:65be27845400	430	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
AnnaBridge	172:65be27845400	431	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
AnnaBridge	172:65be27845400	432
AnnaBridge	172:65be27845400	433	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
AnnaBridge	172:65be27845400	434	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
AnnaBridge	172:65be27845400	435
AnnaBridge	172:65be27845400	436	#define SCB_ICSR_STTNS_Pos 24U /!< SCB ICSR: STTNS Position (Security Extension) /
AnnaBridge	172:65be27845400	437	#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /!< SCB ICSR: STTNS Mask (Security Extension) /
AnnaBridge	172:65be27845400	438
AnnaBridge	172:65be27845400	439	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
AnnaBridge	172:65be27845400	440	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
AnnaBridge	172:65be27845400	441
AnnaBridge	172:65be27845400	442	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
AnnaBridge	172:65be27845400	443	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
AnnaBridge	172:65be27845400	444
AnnaBridge	172:65be27845400	445	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
AnnaBridge	172:65be27845400	446	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
AnnaBridge	172:65be27845400	447
AnnaBridge	172:65be27845400	448	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
AnnaBridge	172:65be27845400	449	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
AnnaBridge	172:65be27845400	450
AnnaBridge	172:65be27845400	451	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
AnnaBridge	172:65be27845400	452	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
AnnaBridge	172:65be27845400	453
AnnaBridge	172:65be27845400	454	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge	172:65be27845400	455	/* SCB Vector Table Offset Register Definitions */
AnnaBridge	172:65be27845400	456	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
AnnaBridge	172:65be27845400	457	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
AnnaBridge	172:65be27845400	458	#endif
AnnaBridge	172:65be27845400	459
AnnaBridge	172:65be27845400	460	/* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge	172:65be27845400	461	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
AnnaBridge	172:65be27845400	462	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
AnnaBridge	172:65be27845400	463
AnnaBridge	172:65be27845400	464	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
AnnaBridge	172:65be27845400	465	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
AnnaBridge	172:65be27845400	466
AnnaBridge	172:65be27845400	467	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
AnnaBridge	172:65be27845400	468	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
AnnaBridge	172:65be27845400	469
AnnaBridge	172:65be27845400	470	#define SCB_AIRCR_PRIS_Pos 14U /!< SCB AIRCR: PRIS Position /
AnnaBridge	172:65be27845400	471	#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /!< SCB AIRCR: PRIS Mask /
AnnaBridge	172:65be27845400	472
AnnaBridge	172:65be27845400	473	#define SCB_AIRCR_BFHFNMINS_Pos 13U /!< SCB AIRCR: BFHFNMINS Position /
AnnaBridge	172:65be27845400	474	#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /!< SCB AIRCR: BFHFNMINS Mask /
AnnaBridge	172:65be27845400	475
AnnaBridge	172:65be27845400	476	#define SCB_AIRCR_SYSRESETREQS_Pos 3U /!< SCB AIRCR: SYSRESETREQS Position /
AnnaBridge	172:65be27845400	477	#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /!< SCB AIRCR: SYSRESETREQS Mask /
AnnaBridge	172:65be27845400	478
AnnaBridge	172:65be27845400	479	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
AnnaBridge	172:65be27845400	480	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
AnnaBridge	172:65be27845400	481
AnnaBridge	172:65be27845400	482	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
AnnaBridge	172:65be27845400	483	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
AnnaBridge	172:65be27845400	484
AnnaBridge	172:65be27845400	485	/* SCB System Control Register Definitions */
AnnaBridge	172:65be27845400	486	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
AnnaBridge	172:65be27845400	487	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
AnnaBridge	172:65be27845400	488
AnnaBridge	172:65be27845400	489	#define SCB_SCR_SLEEPDEEPS_Pos 3U /!< SCB SCR: SLEEPDEEPS Position /
AnnaBridge	172:65be27845400	490	#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /!< SCB SCR: SLEEPDEEPS Mask /
AnnaBridge	172:65be27845400	491
AnnaBridge	172:65be27845400	492	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
AnnaBridge	172:65be27845400	493	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
AnnaBridge	172:65be27845400	494
AnnaBridge	172:65be27845400	495	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
AnnaBridge	172:65be27845400	496	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
AnnaBridge	172:65be27845400	497
AnnaBridge	172:65be27845400	498	/* SCB Configuration Control Register Definitions */
AnnaBridge	172:65be27845400	499	#define SCB_CCR_BP_Pos 18U /!< SCB CCR: BP Position /
AnnaBridge	172:65be27845400	500	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: BP Mask /
AnnaBridge	172:65be27845400	501
AnnaBridge	172:65be27845400	502	#define SCB_CCR_IC_Pos 17U /!< SCB CCR: IC Position /
AnnaBridge	172:65be27845400	503	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: IC Mask /
AnnaBridge	172:65be27845400	504
AnnaBridge	172:65be27845400	505	#define SCB_CCR_DC_Pos 16U /!< SCB CCR: DC Position /
AnnaBridge	172:65be27845400	506	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: DC Mask /
AnnaBridge	172:65be27845400	507
AnnaBridge	172:65be27845400	508	#define SCB_CCR_STKOFHFNMIGN_Pos 10U /!< SCB CCR: STKOFHFNMIGN Position /
AnnaBridge	172:65be27845400	509	#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /!< SCB CCR: STKOFHFNMIGN Mask /
AnnaBridge	172:65be27845400	510
AnnaBridge	172:65be27845400	511	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
AnnaBridge	172:65be27845400	512	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
AnnaBridge	172:65be27845400	513
AnnaBridge	172:65be27845400	514	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
AnnaBridge	172:65be27845400	515	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
AnnaBridge	172:65be27845400	516
AnnaBridge	172:65be27845400	517	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
AnnaBridge	172:65be27845400	518	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
AnnaBridge	172:65be27845400	519
AnnaBridge	172:65be27845400	520	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
AnnaBridge	172:65be27845400	521	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
AnnaBridge	172:65be27845400	522
AnnaBridge	172:65be27845400	523	/* SCB System Handler Control and State Register Definitions */
AnnaBridge	172:65be27845400	524	#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /!< SCB SHCSR: HARDFAULTPENDED Position /
AnnaBridge	172:65be27845400	525	#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /!< SCB SHCSR: HARDFAULTPENDED Mask /
AnnaBridge	172:65be27845400	526
AnnaBridge	172:65be27845400	527	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
AnnaBridge	172:65be27845400	528	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
AnnaBridge	172:65be27845400	529
AnnaBridge	172:65be27845400	530	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
AnnaBridge	172:65be27845400	531	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
AnnaBridge	172:65be27845400	532
AnnaBridge	172:65be27845400	533	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
AnnaBridge	172:65be27845400	534	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
AnnaBridge	172:65be27845400	535
AnnaBridge	172:65be27845400	536	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
AnnaBridge	172:65be27845400	537	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
AnnaBridge	172:65be27845400	538
AnnaBridge	172:65be27845400	539	#define SCB_SHCSR_NMIACT_Pos 5U /!< SCB SHCSR: NMIACT Position /
AnnaBridge	172:65be27845400	540	#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /!< SCB SHCSR: NMIACT Mask /
AnnaBridge	172:65be27845400	541
AnnaBridge	172:65be27845400	542	#define SCB_SHCSR_HARDFAULTACT_Pos 2U /!< SCB SHCSR: HARDFAULTACT Position /
AnnaBridge	172:65be27845400	543	#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /!< SCB SHCSR: HARDFAULTACT Mask /
AnnaBridge	172:65be27845400	544
AnnaBridge	172:65be27845400	545	/@} end of group CMSIS_SCB /
AnnaBridge	172:65be27845400	546
AnnaBridge	172:65be27845400	547
AnnaBridge	172:65be27845400	548	/**
AnnaBridge	172:65be27845400	549	\ingroup CMSIS_core_register
AnnaBridge	172:65be27845400	550	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge	172:65be27845400	551	\brief Type definitions for the System Timer Registers.
AnnaBridge	172:65be27845400	552	@{
AnnaBridge	172:65be27845400	553	*/
AnnaBridge	172:65be27845400	554
AnnaBridge	172:65be27845400	555	/**
AnnaBridge	172:65be27845400	556	\brief Structure type to access the System Timer (SysTick).
AnnaBridge	172:65be27845400	557	*/
AnnaBridge	172:65be27845400	558	typedef struct
AnnaBridge	172:65be27845400	559	{
AnnaBridge	172:65be27845400	560	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
AnnaBridge	172:65be27845400	561	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
AnnaBridge	172:65be27845400	562	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
AnnaBridge	172:65be27845400	563	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
AnnaBridge	172:65be27845400	564	} SysTick_Type;
AnnaBridge	172:65be27845400	565
AnnaBridge	172:65be27845400	566	/* SysTick Control / Status Register Definitions */
AnnaBridge	172:65be27845400	567	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
AnnaBridge	172:65be27845400	568	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
AnnaBridge	172:65be27845400	569
AnnaBridge	172:65be27845400	570	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
AnnaBridge	172:65be27845400	571	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
AnnaBridge	172:65be27845400	572
AnnaBridge	172:65be27845400	573	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
AnnaBridge	172:65be27845400	574	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
AnnaBridge	172:65be27845400	575
AnnaBridge	172:65be27845400	576	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
AnnaBridge	172:65be27845400	577	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
AnnaBridge	172:65be27845400	578
AnnaBridge	172:65be27845400	579	/* SysTick Reload Register Definitions */
AnnaBridge	172:65be27845400	580	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
AnnaBridge	172:65be27845400	581	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
AnnaBridge	172:65be27845400	582
AnnaBridge	172:65be27845400	583	/* SysTick Current Register Definitions */
AnnaBridge	172:65be27845400	584	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
AnnaBridge	172:65be27845400	585	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
AnnaBridge	172:65be27845400	586
AnnaBridge	172:65be27845400	587	/* SysTick Calibration Register Definitions */
AnnaBridge	172:65be27845400	588	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
AnnaBridge	172:65be27845400	589	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
AnnaBridge	172:65be27845400	590
AnnaBridge	172:65be27845400	591	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
AnnaBridge	172:65be27845400	592	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
AnnaBridge	172:65be27845400	593
AnnaBridge	172:65be27845400	594	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
AnnaBridge	172:65be27845400	595	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
AnnaBridge	172:65be27845400	596
AnnaBridge	172:65be27845400	597	/@} end of group CMSIS_SysTick /
AnnaBridge	172:65be27845400	598
AnnaBridge	172:65be27845400	599
AnnaBridge	172:65be27845400	600	/**
AnnaBridge	172:65be27845400	601	\ingroup CMSIS_core_register
AnnaBridge	172:65be27845400	602	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
AnnaBridge	172:65be27845400	603	\brief Type definitions for the Data Watchpoint and Trace (DWT)
AnnaBridge	172:65be27845400	604	@{
AnnaBridge	172:65be27845400	605	*/
AnnaBridge	172:65be27845400	606
AnnaBridge	172:65be27845400	607	/**
AnnaBridge	172:65be27845400	608	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
AnnaBridge	172:65be27845400	609	*/
AnnaBridge	172:65be27845400	610	typedef struct
AnnaBridge	172:65be27845400	611	{
AnnaBridge	172:65be27845400	612	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
AnnaBridge	172:65be27845400	613	uint32_t RESERVED0[6U];
AnnaBridge	172:65be27845400	614	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
AnnaBridge	172:65be27845400	615	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
AnnaBridge	172:65be27845400	616	uint32_t RESERVED1[1U];
AnnaBridge	172:65be27845400	617	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
AnnaBridge	172:65be27845400	618	uint32_t RESERVED2[1U];
AnnaBridge	172:65be27845400	619	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
AnnaBridge	172:65be27845400	620	uint32_t RESERVED3[1U];
AnnaBridge	172:65be27845400	621	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
AnnaBridge	172:65be27845400	622	uint32_t RESERVED4[1U];
AnnaBridge	172:65be27845400	623	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
AnnaBridge	172:65be27845400	624	uint32_t RESERVED5[1U];
AnnaBridge	172:65be27845400	625	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
AnnaBridge	172:65be27845400	626	uint32_t RESERVED6[1U];
AnnaBridge	172:65be27845400	627	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
AnnaBridge	172:65be27845400	628	uint32_t RESERVED7[1U];
AnnaBridge	172:65be27845400	629	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
AnnaBridge	172:65be27845400	630	uint32_t RESERVED8[1U];
AnnaBridge	172:65be27845400	631	__IOM uint32_t COMP4; /!< Offset: 0x060 (R/W) Comparator Register 4 /
AnnaBridge	172:65be27845400	632	uint32_t RESERVED9[1U];
AnnaBridge	172:65be27845400	633	__IOM uint32_t FUNCTION4; /!< Offset: 0x068 (R/W) Function Register 4 /
AnnaBridge	172:65be27845400	634	uint32_t RESERVED10[1U];
AnnaBridge	172:65be27845400	635	__IOM uint32_t COMP5; /!< Offset: 0x070 (R/W) Comparator Register 5 /
AnnaBridge	172:65be27845400	636	uint32_t RESERVED11[1U];
AnnaBridge	172:65be27845400	637	__IOM uint32_t FUNCTION5; /!< Offset: 0x078 (R/W) Function Register 5 /
AnnaBridge	172:65be27845400	638	uint32_t RESERVED12[1U];
AnnaBridge	172:65be27845400	639	__IOM uint32_t COMP6; /!< Offset: 0x080 (R/W) Comparator Register 6 /
AnnaBridge	172:65be27845400	640	uint32_t RESERVED13[1U];
AnnaBridge	172:65be27845400	641	__IOM uint32_t FUNCTION6; /!< Offset: 0x088 (R/W) Function Register 6 /
AnnaBridge	172:65be27845400	642	uint32_t RESERVED14[1U];
AnnaBridge	172:65be27845400	643	__IOM uint32_t COMP7; /!< Offset: 0x090 (R/W) Comparator Register 7 /
AnnaBridge	172:65be27845400	644	uint32_t RESERVED15[1U];
AnnaBridge	172:65be27845400	645	__IOM uint32_t FUNCTION7; /!< Offset: 0x098 (R/W) Function Register 7 /
AnnaBridge	172:65be27845400	646	uint32_t RESERVED16[1U];
AnnaBridge	172:65be27845400	647	__IOM uint32_t COMP8; /!< Offset: 0x0A0 (R/W) Comparator Register 8 /
AnnaBridge	172:65be27845400	648	uint32_t RESERVED17[1U];
AnnaBridge	172:65be27845400	649	__IOM uint32_t FUNCTION8; /!< Offset: 0x0A8 (R/W) Function Register 8 /
AnnaBridge	172:65be27845400	650	uint32_t RESERVED18[1U];
AnnaBridge	172:65be27845400	651	__IOM uint32_t COMP9; /!< Offset: 0x0B0 (R/W) Comparator Register 9 /
AnnaBridge	172:65be27845400	652	uint32_t RESERVED19[1U];
AnnaBridge	172:65be27845400	653	__IOM uint32_t FUNCTION9; /!< Offset: 0x0B8 (R/W) Function Register 9 /
AnnaBridge	172:65be27845400	654	uint32_t RESERVED20[1U];
AnnaBridge	172:65be27845400	655	__IOM uint32_t COMP10; /!< Offset: 0x0C0 (R/W) Comparator Register 10 /
AnnaBridge	172:65be27845400	656	uint32_t RESERVED21[1U];
AnnaBridge	172:65be27845400	657	__IOM uint32_t FUNCTION10; /!< Offset: 0x0C8 (R/W) Function Register 10 /
AnnaBridge	172:65be27845400	658	uint32_t RESERVED22[1U];
AnnaBridge	172:65be27845400	659	__IOM uint32_t COMP11; /!< Offset: 0x0D0 (R/W) Comparator Register 11 /
AnnaBridge	172:65be27845400	660	uint32_t RESERVED23[1U];
AnnaBridge	172:65be27845400	661	__IOM uint32_t FUNCTION11; /!< Offset: 0x0D8 (R/W) Function Register 11 /
AnnaBridge	172:65be27845400	662	uint32_t RESERVED24[1U];
AnnaBridge	172:65be27845400	663	__IOM uint32_t COMP12; /!< Offset: 0x0E0 (R/W) Comparator Register 12 /
AnnaBridge	172:65be27845400	664	uint32_t RESERVED25[1U];
AnnaBridge	172:65be27845400	665	__IOM uint32_t FUNCTION12; /!< Offset: 0x0E8 (R/W) Function Register 12 /
AnnaBridge	172:65be27845400	666	uint32_t RESERVED26[1U];
AnnaBridge	172:65be27845400	667	__IOM uint32_t COMP13; /!< Offset: 0x0F0 (R/W) Comparator Register 13 /
AnnaBridge	172:65be27845400	668	uint32_t RESERVED27[1U];
AnnaBridge	172:65be27845400	669	__IOM uint32_t FUNCTION13; /!< Offset: 0x0F8 (R/W) Function Register 13 /
AnnaBridge	172:65be27845400	670	uint32_t RESERVED28[1U];
AnnaBridge	172:65be27845400	671	__IOM uint32_t COMP14; /!< Offset: 0x100 (R/W) Comparator Register 14 /
AnnaBridge	172:65be27845400	672	uint32_t RESERVED29[1U];
AnnaBridge	172:65be27845400	673	__IOM uint32_t FUNCTION14; /!< Offset: 0x108 (R/W) Function Register 14 /
AnnaBridge	172:65be27845400	674	uint32_t RESERVED30[1U];
AnnaBridge	172:65be27845400	675	__IOM uint32_t COMP15; /!< Offset: 0x110 (R/W) Comparator Register 15 /
AnnaBridge	172:65be27845400	676	uint32_t RESERVED31[1U];
AnnaBridge	172:65be27845400	677	__IOM uint32_t FUNCTION15; /!< Offset: 0x118 (R/W) Function Register 15 /
AnnaBridge	172:65be27845400	678	} DWT_Type;
AnnaBridge	172:65be27845400	679
AnnaBridge	172:65be27845400	680	/* DWT Control Register Definitions */
AnnaBridge	172:65be27845400	681	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
AnnaBridge	172:65be27845400	682	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
AnnaBridge	172:65be27845400	683
AnnaBridge	172:65be27845400	684	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
AnnaBridge	172:65be27845400	685	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
AnnaBridge	172:65be27845400	686
AnnaBridge	172:65be27845400	687	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
AnnaBridge	172:65be27845400	688	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
AnnaBridge	172:65be27845400	689
AnnaBridge	172:65be27845400	690	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
AnnaBridge	172:65be27845400	691	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
AnnaBridge	172:65be27845400	692
AnnaBridge	172:65be27845400	693	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
AnnaBridge	172:65be27845400	694	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
AnnaBridge	172:65be27845400	695
AnnaBridge	172:65be27845400	696	/* DWT Comparator Function Register Definitions */
AnnaBridge	172:65be27845400	697	#define DWT_FUNCTION_ID_Pos 27U /!< DWT FUNCTION: ID Position /
AnnaBridge	172:65be27845400	698	#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /!< DWT FUNCTION: ID Mask /
AnnaBridge	172:65be27845400	699
AnnaBridge	172:65be27845400	700	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
AnnaBridge	172:65be27845400	701	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
AnnaBridge	172:65be27845400	702
AnnaBridge	172:65be27845400	703	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
AnnaBridge	172:65be27845400	704	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
AnnaBridge	172:65be27845400	705
AnnaBridge	172:65be27845400	706	#define DWT_FUNCTION_ACTION_Pos 4U /!< DWT FUNCTION: ACTION Position /
AnnaBridge	172:65be27845400	707	#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /!< DWT FUNCTION: ACTION Mask /
AnnaBridge	172:65be27845400	708
AnnaBridge	172:65be27845400	709	#define DWT_FUNCTION_MATCH_Pos 0U /!< DWT FUNCTION: MATCH Position /
AnnaBridge	172:65be27845400	710	#define DWT_FUNCTION_MATCH_Msk (0xFUL /<< DWT_FUNCTION_MATCH_Pos/) /!< DWT FUNCTION: MATCH Mask /
AnnaBridge	172:65be27845400	711
AnnaBridge	172:65be27845400	712	/@}/ /* end of group CMSIS_DWT */
AnnaBridge	172:65be27845400	713
AnnaBridge	172:65be27845400	714
AnnaBridge	172:65be27845400	715	/**
AnnaBridge	172:65be27845400	716	\ingroup CMSIS_core_register
AnnaBridge	172:65be27845400	717	\defgroup CMSIS_TPI Trace Port Interface (TPI)
AnnaBridge	172:65be27845400	718	\brief Type definitions for the Trace Port Interface (TPI)
AnnaBridge	172:65be27845400	719	@{
AnnaBridge	172:65be27845400	720	*/
AnnaBridge	172:65be27845400	721
AnnaBridge	172:65be27845400	722	/**
AnnaBridge	172:65be27845400	723	\brief Structure type to access the Trace Port Interface Register (TPI).
AnnaBridge	172:65be27845400	724	*/
AnnaBridge	172:65be27845400	725	typedef struct
AnnaBridge	172:65be27845400	726	{
AnnaBridge	172:65be27845400	727	__IM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
AnnaBridge	172:65be27845400	728	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
AnnaBridge	172:65be27845400	729	uint32_t RESERVED0[2U];
AnnaBridge	172:65be27845400	730	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
AnnaBridge	172:65be27845400	731	uint32_t RESERVED1[55U];
AnnaBridge	172:65be27845400	732	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
AnnaBridge	172:65be27845400	733	uint32_t RESERVED2[131U];
AnnaBridge	172:65be27845400	734	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
AnnaBridge	172:65be27845400	735	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
AnnaBridge	172:65be27845400	736	__IOM uint32_t PSCR; /!< Offset: 0x308 (R/W) Periodic Synchronization Control Register /
AnnaBridge	172:65be27845400	737	uint32_t RESERVED3[759U];
AnnaBridge	172:65be27845400	738	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER Register /
AnnaBridge	172:65be27845400	739	__IM uint32_t ITFTTD0; /!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register /
AnnaBridge	172:65be27845400	740	__IOM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 /
AnnaBridge	172:65be27845400	741	uint32_t RESERVED4[1U];
AnnaBridge	172:65be27845400	742	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 /
AnnaBridge	172:65be27845400	743	__IM uint32_t ITFTTD1; /!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register /
AnnaBridge	172:65be27845400	744	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
AnnaBridge	172:65be27845400	745	uint32_t RESERVED5[39U];
AnnaBridge	172:65be27845400	746	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
AnnaBridge	172:65be27845400	747	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
AnnaBridge	172:65be27845400	748	uint32_t RESERVED7[8U];
AnnaBridge	172:65be27845400	749	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) Device Configuration Register /
AnnaBridge	172:65be27845400	750	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) Device Type Identifier Register /
AnnaBridge	172:65be27845400	751	} TPI_Type;
AnnaBridge	172:65be27845400	752
AnnaBridge	172:65be27845400	753	/* TPI Asynchronous Clock Prescaler Register Definitions */
AnnaBridge	172:65be27845400	754	#define TPI_ACPR_PRESCALER_Pos 0U /!< TPI ACPR: PRESCALER Position /
AnnaBridge	172:65be27845400	755	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
AnnaBridge	172:65be27845400	756
AnnaBridge	172:65be27845400	757	/* TPI Selected Pin Protocol Register Definitions */
AnnaBridge	172:65be27845400	758	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
AnnaBridge	172:65be27845400	759	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
AnnaBridge	172:65be27845400	760
AnnaBridge	172:65be27845400	761	/* TPI Formatter and Flush Status Register Definitions */
AnnaBridge	172:65be27845400	762	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
AnnaBridge	172:65be27845400	763	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
AnnaBridge	172:65be27845400	764
AnnaBridge	172:65be27845400	765	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
AnnaBridge	172:65be27845400	766	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
AnnaBridge	172:65be27845400	767
AnnaBridge	172:65be27845400	768	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
AnnaBridge	172:65be27845400	769	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
AnnaBridge	172:65be27845400	770
AnnaBridge	172:65be27845400	771	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
AnnaBridge	172:65be27845400	772	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
AnnaBridge	172:65be27845400	773
AnnaBridge	172:65be27845400	774	/* TPI Formatter and Flush Control Register Definitions */
AnnaBridge	172:65be27845400	775	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
AnnaBridge	172:65be27845400	776	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
AnnaBridge	172:65be27845400	777
AnnaBridge	172:65be27845400	778	#define TPI_FFCR_FOnMan_Pos 6U /!< TPI FFCR: FOnMan Position /
AnnaBridge	172:65be27845400	779	#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /!< TPI FFCR: FOnMan Mask /
AnnaBridge	172:65be27845400	780
AnnaBridge	172:65be27845400	781	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
AnnaBridge	172:65be27845400	782	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
AnnaBridge	172:65be27845400	783
AnnaBridge	172:65be27845400	784	/* TPI TRIGGER Register Definitions */
AnnaBridge	172:65be27845400	785	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
AnnaBridge	172:65be27845400	786	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
AnnaBridge	172:65be27845400	787
AnnaBridge	172:65be27845400	788	/* TPI Integration Test FIFO Test Data 0 Register Definitions */
AnnaBridge	172:65be27845400	789	#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition /
AnnaBridge	172:65be27845400	790	#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask /
AnnaBridge	172:65be27845400	791
AnnaBridge	172:65be27845400	792	#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /!< TPI ITFTTD0: ATB Interface 2 byte count Position /
AnnaBridge	172:65be27845400	793	#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /!< TPI ITFTTD0: ATB Interface 2 byte count Mask /
AnnaBridge	172:65be27845400	794
AnnaBridge	172:65be27845400	795	#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /!< TPI ITFTTD0: ATB Interface 1 ATVALID Position /
AnnaBridge	172:65be27845400	796	#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask /
AnnaBridge	172:65be27845400	797
AnnaBridge	172:65be27845400	798	#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /!< TPI ITFTTD0: ATB Interface 1 byte count Position /
AnnaBridge	172:65be27845400	799	#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /!< TPI ITFTTD0: ATB Interface 1 byte countt Mask /
AnnaBridge	172:65be27845400	800
AnnaBridge	172:65be27845400	801	#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /!< TPI ITFTTD0: ATB Interface 1 data2 Position /
AnnaBridge	172:65be27845400	802	#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /!< TPI ITFTTD0: ATB Interface 1 data2 Mask /
AnnaBridge	172:65be27845400	803
AnnaBridge	172:65be27845400	804	#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /!< TPI ITFTTD0: ATB Interface 1 data1 Position /
AnnaBridge	172:65be27845400	805	#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /!< TPI ITFTTD0: ATB Interface 1 data1 Mask /
AnnaBridge	172:65be27845400	806
AnnaBridge	172:65be27845400	807	#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /!< TPI ITFTTD0: ATB Interface 1 data0 Position /
AnnaBridge	172:65be27845400	808	#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /<< TPI_ITFTTD0_ATB_IF1_data0_Pos/) /!< TPI ITFTTD0: ATB Interface 1 data0 Mask /
AnnaBridge	172:65be27845400	809
AnnaBridge	172:65be27845400	810	/* TPI Integration Test ATB Control Register 2 Register Definitions */
AnnaBridge	172:65be27845400	811	#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /!< TPI ITATBCTR2: AFVALID2S Position /
AnnaBridge	172:65be27845400	812	#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /!< TPI ITATBCTR2: AFVALID2SS Mask /
AnnaBridge	172:65be27845400	813
AnnaBridge	172:65be27845400	814	#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /!< TPI ITATBCTR2: AFVALID1S Position /
AnnaBridge	172:65be27845400	815	#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /!< TPI ITATBCTR2: AFVALID1SS Mask /
AnnaBridge	172:65be27845400	816
AnnaBridge	172:65be27845400	817	#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /!< TPI ITATBCTR2: ATREADY2S Position /
AnnaBridge	172:65be27845400	818	#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2S_Pos/) /!< TPI ITATBCTR2: ATREADY2S Mask /
AnnaBridge	172:65be27845400	819
AnnaBridge	172:65be27845400	820	#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /!< TPI ITATBCTR2: ATREADY1S Position /
AnnaBridge	172:65be27845400	821	#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1S_Pos/) /!< TPI ITATBCTR2: ATREADY1S Mask /
AnnaBridge	172:65be27845400	822
AnnaBridge	172:65be27845400	823	/* TPI Integration Test FIFO Test Data 1 Register Definitions */
AnnaBridge	172:65be27845400	824	#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /!< TPI ITFTTD1: ATB Interface 2 ATVALID Position /
AnnaBridge	172:65be27845400	825	#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask /
AnnaBridge	172:65be27845400	826
AnnaBridge	172:65be27845400	827	#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /!< TPI ITFTTD1: ATB Interface 2 byte count Position /
AnnaBridge	172:65be27845400	828	#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /!< TPI ITFTTD1: ATB Interface 2 byte count Mask /
AnnaBridge	172:65be27845400	829
AnnaBridge	172:65be27845400	830	#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /!< TPI ITFTTD1: ATB Interface 1 ATVALID Position /
AnnaBridge	172:65be27845400	831	#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask /
AnnaBridge	172:65be27845400	832
AnnaBridge	172:65be27845400	833	#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /!< TPI ITFTTD1: ATB Interface 1 byte count Position /
AnnaBridge	172:65be27845400	834	#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /!< TPI ITFTTD1: ATB Interface 1 byte countt Mask /
AnnaBridge	172:65be27845400	835
AnnaBridge	172:65be27845400	836	#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /!< TPI ITFTTD1: ATB Interface 2 data2 Position /
AnnaBridge	172:65be27845400	837	#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /!< TPI ITFTTD1: ATB Interface 2 data2 Mask /
AnnaBridge	172:65be27845400	838
AnnaBridge	172:65be27845400	839	#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /!< TPI ITFTTD1: ATB Interface 2 data1 Position /
AnnaBridge	172:65be27845400	840	#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /!< TPI ITFTTD1: ATB Interface 2 data1 Mask /
AnnaBridge	172:65be27845400	841
AnnaBridge	172:65be27845400	842	#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /!< TPI ITFTTD1: ATB Interface 2 data0 Position /
AnnaBridge	172:65be27845400	843	#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /<< TPI_ITFTTD1_ATB_IF2_data0_Pos/) /!< TPI ITFTTD1: ATB Interface 2 data0 Mask /
AnnaBridge	172:65be27845400	844
AnnaBridge	172:65be27845400	845	/* TPI Integration Test ATB Control Register 0 Definitions */
AnnaBridge	172:65be27845400	846	#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /!< TPI ITATBCTR0: AFVALID2S Position /
AnnaBridge	172:65be27845400	847	#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /!< TPI ITATBCTR0: AFVALID2SS Mask /
AnnaBridge	172:65be27845400	848
AnnaBridge	172:65be27845400	849	#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /!< TPI ITATBCTR0: AFVALID1S Position /
AnnaBridge	172:65be27845400	850	#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /!< TPI ITATBCTR0: AFVALID1SS Mask /
AnnaBridge	172:65be27845400	851
AnnaBridge	172:65be27845400	852	#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /!< TPI ITATBCTR0: ATREADY2S Position /
AnnaBridge	172:65be27845400	853	#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2S_Pos/) /!< TPI ITATBCTR0: ATREADY2S Mask /
AnnaBridge	172:65be27845400	854
AnnaBridge	172:65be27845400	855	#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /!< TPI ITATBCTR0: ATREADY1S Position /
AnnaBridge	172:65be27845400	856	#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1S_Pos/) /!< TPI ITATBCTR0: ATREADY1S Mask /
AnnaBridge	172:65be27845400	857
AnnaBridge	172:65be27845400	858	/* TPI Integration Mode Control Register Definitions */
AnnaBridge	172:65be27845400	859	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
AnnaBridge	172:65be27845400	860	#define TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
AnnaBridge	172:65be27845400	861
AnnaBridge	172:65be27845400	862	/* TPI DEVID Register Definitions */
AnnaBridge	172:65be27845400	863	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
AnnaBridge	172:65be27845400	864	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
AnnaBridge	172:65be27845400	865
AnnaBridge	172:65be27845400	866	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
AnnaBridge	172:65be27845400	867	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
AnnaBridge	172:65be27845400	868
AnnaBridge	172:65be27845400	869	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
AnnaBridge	172:65be27845400	870	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
AnnaBridge	172:65be27845400	871
AnnaBridge	172:65be27845400	872	#define TPI_DEVID_FIFOSZ_Pos 6U /!< TPI DEVID: FIFOSZ Position /
AnnaBridge	172:65be27845400	873	#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /!< TPI DEVID: FIFOSZ Mask /
AnnaBridge	172:65be27845400	874
AnnaBridge	172:65be27845400	875	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
AnnaBridge	172:65be27845400	876	#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
AnnaBridge	172:65be27845400	877
AnnaBridge	172:65be27845400	878	/* TPI DEVTYPE Register Definitions */
AnnaBridge	172:65be27845400	879	#define TPI_DEVTYPE_SubType_Pos 4U /!< TPI DEVTYPE: SubType Position /
AnnaBridge	172:65be27845400	880	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
AnnaBridge	172:65be27845400	881
AnnaBridge	172:65be27845400	882	#define TPI_DEVTYPE_MajorType_Pos 0U /!< TPI DEVTYPE: MajorType Position /
AnnaBridge	172:65be27845400	883	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
AnnaBridge	172:65be27845400	884
AnnaBridge	172:65be27845400	885	/@}/ /* end of group CMSIS_TPI */
AnnaBridge	172:65be27845400	886
AnnaBridge	172:65be27845400	887
AnnaBridge	172:65be27845400	888	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	172:65be27845400	889	/**
AnnaBridge	172:65be27845400	890	\ingroup CMSIS_core_register
AnnaBridge	172:65be27845400	891	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge	172:65be27845400	892	\brief Type definitions for the Memory Protection Unit (MPU)
AnnaBridge	172:65be27845400	893	@{
AnnaBridge	172:65be27845400	894	*/
AnnaBridge	172:65be27845400	895
AnnaBridge	172:65be27845400	896	/**
AnnaBridge	172:65be27845400	897	\brief Structure type to access the Memory Protection Unit (MPU).
AnnaBridge	172:65be27845400	898	*/
AnnaBridge	172:65be27845400	899	typedef struct
AnnaBridge	172:65be27845400	900	{
AnnaBridge	172:65be27845400	901	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
AnnaBridge	172:65be27845400	902	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
AnnaBridge	172:65be27845400	903	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region Number Register /
AnnaBridge	172:65be27845400	904	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
AnnaBridge	172:65be27845400	905	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) MPU Region Limit Address Register /
AnnaBridge	172:65be27845400	906	uint32_t RESERVED0[7U];
AnnaBridge	172:65be27845400	907	union {
AnnaBridge	172:65be27845400	908	__IOM uint32_t MAIR[2];
AnnaBridge	172:65be27845400	909	struct {
AnnaBridge	172:65be27845400	910	__IOM uint32_t MAIR0; /!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 /
AnnaBridge	172:65be27845400	911	__IOM uint32_t MAIR1; /!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 /
AnnaBridge	172:65be27845400	912	};
AnnaBridge	172:65be27845400	913	};
AnnaBridge	172:65be27845400	914	} MPU_Type;
AnnaBridge	172:65be27845400	915
AnnaBridge	172:65be27845400	916	#define MPU_TYPE_RALIASES 1U
AnnaBridge	172:65be27845400	917
AnnaBridge	172:65be27845400	918	/* MPU Type Register Definitions */
AnnaBridge	172:65be27845400	919	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
AnnaBridge	172:65be27845400	920	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
AnnaBridge	172:65be27845400	921
AnnaBridge	172:65be27845400	922	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
AnnaBridge	172:65be27845400	923	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
AnnaBridge	172:65be27845400	924
AnnaBridge	172:65be27845400	925	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
AnnaBridge	172:65be27845400	926	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
AnnaBridge	172:65be27845400	927
AnnaBridge	172:65be27845400	928	/* MPU Control Register Definitions */
AnnaBridge	172:65be27845400	929	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
AnnaBridge	172:65be27845400	930	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
AnnaBridge	172:65be27845400	931
AnnaBridge	172:65be27845400	932	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
AnnaBridge	172:65be27845400	933	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
AnnaBridge	172:65be27845400	934
AnnaBridge	172:65be27845400	935	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
AnnaBridge	172:65be27845400	936	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
AnnaBridge	172:65be27845400	937
AnnaBridge	172:65be27845400	938	/* MPU Region Number Register Definitions */
AnnaBridge	172:65be27845400	939	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
AnnaBridge	172:65be27845400	940	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
AnnaBridge	172:65be27845400	941
AnnaBridge	172:65be27845400	942	/* MPU Region Base Address Register Definitions */
AnnaBridge	172:65be27845400	943	#define MPU_RBAR_BASE_Pos 5U /!< MPU RBAR: BASE Position /
AnnaBridge	172:65be27845400	944	#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /!< MPU RBAR: BASE Mask /
AnnaBridge	172:65be27845400	945
AnnaBridge	172:65be27845400	946	#define MPU_RBAR_SH_Pos 3U /!< MPU RBAR: SH Position /
AnnaBridge	172:65be27845400	947	#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /!< MPU RBAR: SH Mask /
AnnaBridge	172:65be27845400	948
AnnaBridge	172:65be27845400	949	#define MPU_RBAR_AP_Pos 1U /!< MPU RBAR: AP Position /
AnnaBridge	172:65be27845400	950	#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /!< MPU RBAR: AP Mask /
AnnaBridge	172:65be27845400	951
AnnaBridge	172:65be27845400	952	#define MPU_RBAR_XN_Pos 0U /!< MPU RBAR: XN Position /
AnnaBridge	172:65be27845400	953	#define MPU_RBAR_XN_Msk (01UL /<< MPU_RBAR_XN_Pos/) /!< MPU RBAR: XN Mask /
AnnaBridge	172:65be27845400	954
AnnaBridge	172:65be27845400	955	/* MPU Region Limit Address Register Definitions */
AnnaBridge	172:65be27845400	956	#define MPU_RLAR_LIMIT_Pos 5U /!< MPU RLAR: LIMIT Position /
AnnaBridge	172:65be27845400	957	#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /!< MPU RLAR: LIMIT Mask /
AnnaBridge	172:65be27845400	958
AnnaBridge	172:65be27845400	959	#define MPU_RLAR_AttrIndx_Pos 1U /!< MPU RLAR: AttrIndx Position /
AnnaBridge	172:65be27845400	960	#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /!< MPU RLAR: AttrIndx Mask /
AnnaBridge	172:65be27845400	961
AnnaBridge	172:65be27845400	962	#define MPU_RLAR_EN_Pos 0U /!< MPU RLAR: EN Position /
AnnaBridge	172:65be27845400	963	#define MPU_RLAR_EN_Msk (1UL /<< MPU_RLAR_EN_Pos/) /!< MPU RLAR: EN Mask /
AnnaBridge	172:65be27845400	964
AnnaBridge	172:65be27845400	965	/* MPU Memory Attribute Indirection Register 0 Definitions */
AnnaBridge	172:65be27845400	966	#define MPU_MAIR0_Attr3_Pos 24U /!< MPU MAIR0: Attr3 Position /
AnnaBridge	172:65be27845400	967	#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /!< MPU MAIR0: Attr3 Mask /
AnnaBridge	172:65be27845400	968
AnnaBridge	172:65be27845400	969	#define MPU_MAIR0_Attr2_Pos 16U /!< MPU MAIR0: Attr2 Position /
AnnaBridge	172:65be27845400	970	#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /!< MPU MAIR0: Attr2 Mask /
AnnaBridge	172:65be27845400	971
AnnaBridge	172:65be27845400	972	#define MPU_MAIR0_Attr1_Pos 8U /!< MPU MAIR0: Attr1 Position /
AnnaBridge	172:65be27845400	973	#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /!< MPU MAIR0: Attr1 Mask /
AnnaBridge	172:65be27845400	974
AnnaBridge	172:65be27845400	975	#define MPU_MAIR0_Attr0_Pos 0U /!< MPU MAIR0: Attr0 Position /
AnnaBridge	172:65be27845400	976	#define MPU_MAIR0_Attr0_Msk (0xFFUL /<< MPU_MAIR0_Attr0_Pos/) /!< MPU MAIR0: Attr0 Mask /
AnnaBridge	172:65be27845400	977
AnnaBridge	172:65be27845400	978	/* MPU Memory Attribute Indirection Register 1 Definitions */
AnnaBridge	172:65be27845400	979	#define MPU_MAIR1_Attr7_Pos 24U /!< MPU MAIR1: Attr7 Position /
AnnaBridge	172:65be27845400	980	#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /!< MPU MAIR1: Attr7 Mask /
AnnaBridge	172:65be27845400	981
AnnaBridge	172:65be27845400	982	#define MPU_MAIR1_Attr6_Pos 16U /!< MPU MAIR1: Attr6 Position /
AnnaBridge	172:65be27845400	983	#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /!< MPU MAIR1: Attr6 Mask /
AnnaBridge	172:65be27845400	984
AnnaBridge	172:65be27845400	985	#define MPU_MAIR1_Attr5_Pos 8U /!< MPU MAIR1: Attr5 Position /
AnnaBridge	172:65be27845400	986	#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /!< MPU MAIR1: Attr5 Mask /
AnnaBridge	172:65be27845400	987
AnnaBridge	172:65be27845400	988	#define MPU_MAIR1_Attr4_Pos 0U /!< MPU MAIR1: Attr4 Position /
AnnaBridge	172:65be27845400	989	#define MPU_MAIR1_Attr4_Msk (0xFFUL /<< MPU_MAIR1_Attr4_Pos/) /!< MPU MAIR1: Attr4 Mask /
AnnaBridge	172:65be27845400	990
AnnaBridge	172:65be27845400	991	/@} end of group CMSIS_MPU /
AnnaBridge	172:65be27845400	992	#endif
AnnaBridge	172:65be27845400	993
AnnaBridge	172:65be27845400	994
AnnaBridge	172:65be27845400	995	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	172:65be27845400	996	/**
AnnaBridge	172:65be27845400	997	\ingroup CMSIS_core_register
AnnaBridge	172:65be27845400	998	\defgroup CMSIS_SAU Security Attribution Unit (SAU)
AnnaBridge	172:65be27845400	999	\brief Type definitions for the Security Attribution Unit (SAU)
AnnaBridge	172:65be27845400	1000	@{
AnnaBridge	172:65be27845400	1001	*/
AnnaBridge	172:65be27845400	1002
AnnaBridge	172:65be27845400	1003	/**
AnnaBridge	172:65be27845400	1004	\brief Structure type to access the Security Attribution Unit (SAU).
AnnaBridge	172:65be27845400	1005	*/
AnnaBridge	172:65be27845400	1006	typedef struct
AnnaBridge	172:65be27845400	1007	{
AnnaBridge	172:65be27845400	1008	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SAU Control Register /
AnnaBridge	172:65be27845400	1009	__IM uint32_t TYPE; /!< Offset: 0x004 (R/ ) SAU Type Register /
AnnaBridge	172:65be27845400	1010	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
AnnaBridge	172:65be27845400	1011	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) SAU Region Number Register /
AnnaBridge	172:65be27845400	1012	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) SAU Region Base Address Register /
AnnaBridge	172:65be27845400	1013	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) SAU Region Limit Address Register /
AnnaBridge	172:65be27845400	1014	#endif
AnnaBridge	172:65be27845400	1015	} SAU_Type;
AnnaBridge	172:65be27845400	1016
AnnaBridge	172:65be27845400	1017	/* SAU Control Register Definitions */
AnnaBridge	172:65be27845400	1018	#define SAU_CTRL_ALLNS_Pos 1U /!< SAU CTRL: ALLNS Position /
AnnaBridge	172:65be27845400	1019	#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /!< SAU CTRL: ALLNS Mask /
AnnaBridge	172:65be27845400	1020
AnnaBridge	172:65be27845400	1021	#define SAU_CTRL_ENABLE_Pos 0U /!< SAU CTRL: ENABLE Position /
AnnaBridge	172:65be27845400	1022	#define SAU_CTRL_ENABLE_Msk (1UL /<< SAU_CTRL_ENABLE_Pos/) /!< SAU CTRL: ENABLE Mask /
AnnaBridge	172:65be27845400	1023
AnnaBridge	172:65be27845400	1024	/* SAU Type Register Definitions */
AnnaBridge	172:65be27845400	1025	#define SAU_TYPE_SREGION_Pos 0U /!< SAU TYPE: SREGION Position /
AnnaBridge	172:65be27845400	1026	#define SAU_TYPE_SREGION_Msk (0xFFUL /<< SAU_TYPE_SREGION_Pos/) /!< SAU TYPE: SREGION Mask /
AnnaBridge	172:65be27845400	1027
AnnaBridge	172:65be27845400	1028	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
AnnaBridge	172:65be27845400	1029	/* SAU Region Number Register Definitions */
AnnaBridge	172:65be27845400	1030	#define SAU_RNR_REGION_Pos 0U /!< SAU RNR: REGION Position /
AnnaBridge	172:65be27845400	1031	#define SAU_RNR_REGION_Msk (0xFFUL /<< SAU_RNR_REGION_Pos/) /!< SAU RNR: REGION Mask /
AnnaBridge	172:65be27845400	1032
AnnaBridge	172:65be27845400	1033	/* SAU Region Base Address Register Definitions */
AnnaBridge	172:65be27845400	1034	#define SAU_RBAR_BADDR_Pos 5U /!< SAU RBAR: BADDR Position /
AnnaBridge	172:65be27845400	1035	#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /!< SAU RBAR: BADDR Mask /
AnnaBridge	172:65be27845400	1036
AnnaBridge	172:65be27845400	1037	/* SAU Region Limit Address Register Definitions */
AnnaBridge	172:65be27845400	1038	#define SAU_RLAR_LADDR_Pos 5U /!< SAU RLAR: LADDR Position /
AnnaBridge	172:65be27845400	1039	#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /!< SAU RLAR: LADDR Mask /
AnnaBridge	172:65be27845400	1040
AnnaBridge	172:65be27845400	1041	#define SAU_RLAR_NSC_Pos 1U /!< SAU RLAR: NSC Position /
AnnaBridge	172:65be27845400	1042	#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /!< SAU RLAR: NSC Mask /
AnnaBridge	172:65be27845400	1043
AnnaBridge	172:65be27845400	1044	#define SAU_RLAR_ENABLE_Pos 0U /!< SAU RLAR: ENABLE Position /
AnnaBridge	172:65be27845400	1045	#define SAU_RLAR_ENABLE_Msk (1UL /<< SAU_RLAR_ENABLE_Pos/) /!< SAU RLAR: ENABLE Mask /
AnnaBridge	172:65be27845400	1046
AnnaBridge	172:65be27845400	1047	#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
AnnaBridge	172:65be27845400	1048
AnnaBridge	172:65be27845400	1049	/@} end of group CMSIS_SAU /
AnnaBridge	172:65be27845400	1050	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	172:65be27845400	1051
AnnaBridge	172:65be27845400	1052
AnnaBridge	172:65be27845400	1053	/**
AnnaBridge	172:65be27845400	1054	\ingroup CMSIS_core_register
AnnaBridge	172:65be27845400	1055	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge	172:65be27845400	1056	\brief Type definitions for the Core Debug Registers
AnnaBridge	172:65be27845400	1057	@{
AnnaBridge	172:65be27845400	1058	*/
AnnaBridge	172:65be27845400	1059
AnnaBridge	172:65be27845400	1060	/**
AnnaBridge	172:65be27845400	1061	\brief Structure type to access the Core Debug Register (CoreDebug).
AnnaBridge	172:65be27845400	1062	*/
AnnaBridge	172:65be27845400	1063	typedef struct
AnnaBridge	172:65be27845400	1064	{
AnnaBridge	172:65be27845400	1065	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
AnnaBridge	172:65be27845400	1066	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
AnnaBridge	172:65be27845400	1067	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
AnnaBridge	172:65be27845400	1068	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
AnnaBridge	172:65be27845400	1069	uint32_t RESERVED4[1U];
AnnaBridge	172:65be27845400	1070	__IOM uint32_t DAUTHCTRL; /!< Offset: 0x014 (R/W) Debug Authentication Control Register /
AnnaBridge	172:65be27845400	1071	__IOM uint32_t DSCSR; /!< Offset: 0x018 (R/W) Debug Security Control and Status Register /
AnnaBridge	172:65be27845400	1072	} CoreDebug_Type;
AnnaBridge	172:65be27845400	1073
AnnaBridge	172:65be27845400	1074	/* Debug Halting Control and Status Register Definitions */
AnnaBridge	172:65be27845400	1075	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
AnnaBridge	172:65be27845400	1076	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
AnnaBridge	172:65be27845400	1077
AnnaBridge	172:65be27845400	1078	#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /!< CoreDebug DHCSR: S_RESTART_ST Position /
AnnaBridge	172:65be27845400	1079	#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /!< CoreDebug DHCSR: S_RESTART_ST Mask /
AnnaBridge	172:65be27845400	1080
AnnaBridge	172:65be27845400	1081	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
AnnaBridge	172:65be27845400	1082	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
AnnaBridge	172:65be27845400	1083
AnnaBridge	172:65be27845400	1084	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
AnnaBridge	172:65be27845400	1085	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
AnnaBridge	172:65be27845400	1086
AnnaBridge	172:65be27845400	1087	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
AnnaBridge	172:65be27845400	1088	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
AnnaBridge	172:65be27845400	1089
AnnaBridge	172:65be27845400	1090	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
AnnaBridge	172:65be27845400	1091	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
AnnaBridge	172:65be27845400	1092
AnnaBridge	172:65be27845400	1093	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
AnnaBridge	172:65be27845400	1094	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
AnnaBridge	172:65be27845400	1095
AnnaBridge	172:65be27845400	1096	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
AnnaBridge	172:65be27845400	1097	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
AnnaBridge	172:65be27845400	1098
AnnaBridge	172:65be27845400	1099	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
AnnaBridge	172:65be27845400	1100	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
AnnaBridge	172:65be27845400	1101
AnnaBridge	172:65be27845400	1102	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
AnnaBridge	172:65be27845400	1103	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
AnnaBridge	172:65be27845400	1104
AnnaBridge	172:65be27845400	1105	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
AnnaBridge	172:65be27845400	1106	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
AnnaBridge	172:65be27845400	1107
AnnaBridge	172:65be27845400	1108	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
AnnaBridge	172:65be27845400	1109	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
AnnaBridge	172:65be27845400	1110
AnnaBridge	172:65be27845400	1111	/* Debug Core Register Selector Register Definitions */
AnnaBridge	172:65be27845400	1112	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
AnnaBridge	172:65be27845400	1113	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
AnnaBridge	172:65be27845400	1114
AnnaBridge	172:65be27845400	1115	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
AnnaBridge	172:65be27845400	1116	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
AnnaBridge	172:65be27845400	1117
AnnaBridge	172:65be27845400	1118	/* Debug Exception and Monitor Control Register */
AnnaBridge	172:65be27845400	1119	#define CoreDebug_DEMCR_DWTENA_Pos 24U /!< CoreDebug DEMCR: DWTENA Position /
AnnaBridge	172:65be27845400	1120	#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /!< CoreDebug DEMCR: DWTENA Mask /
AnnaBridge	172:65be27845400	1121
AnnaBridge	172:65be27845400	1122	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
AnnaBridge	172:65be27845400	1123	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
AnnaBridge	172:65be27845400	1124
AnnaBridge	172:65be27845400	1125	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
AnnaBridge	172:65be27845400	1126	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
AnnaBridge	172:65be27845400	1127
AnnaBridge	172:65be27845400	1128	/* Debug Authentication Control Register Definitions */
AnnaBridge	172:65be27845400	1129	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position /
AnnaBridge	172:65be27845400	1130	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask /
AnnaBridge	172:65be27845400	1131
AnnaBridge	172:65be27845400	1132	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /!< CoreDebug DAUTHCTRL: SPNIDENSEL Position /
AnnaBridge	172:65be27845400	1133	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask /
AnnaBridge	172:65be27845400	1134
AnnaBridge	172:65be27845400	1135	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /!< CoreDebug DAUTHCTRL: INTSPIDEN Position /
AnnaBridge	172:65be27845400	1136	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPIDEN Mask /
AnnaBridge	172:65be27845400	1137
AnnaBridge	172:65be27845400	1138	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /!< CoreDebug DAUTHCTRL: SPIDENSEL Position /
AnnaBridge	172:65be27845400	1139	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/) /!< CoreDebug DAUTHCTRL: SPIDENSEL Mask /
AnnaBridge	172:65be27845400	1140
AnnaBridge	172:65be27845400	1141	/* Debug Security Control and Status Register Definitions */
AnnaBridge	172:65be27845400	1142	#define CoreDebug_DSCSR_CDS_Pos 16U /!< CoreDebug DSCSR: CDS Position /
AnnaBridge	172:65be27845400	1143	#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /!< CoreDebug DSCSR: CDS Mask /
AnnaBridge	172:65be27845400	1144
AnnaBridge	172:65be27845400	1145	#define CoreDebug_DSCSR_SBRSEL_Pos 1U /!< CoreDebug DSCSR: SBRSEL Position /
AnnaBridge	172:65be27845400	1146	#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /!< CoreDebug DSCSR: SBRSEL Mask /
AnnaBridge	172:65be27845400	1147
AnnaBridge	172:65be27845400	1148	#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /!< CoreDebug DSCSR: SBRSELEN Position /
AnnaBridge	172:65be27845400	1149	#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/) /!< CoreDebug DSCSR: SBRSELEN Mask /
AnnaBridge	172:65be27845400	1150
AnnaBridge	172:65be27845400	1151	/@} end of group CMSIS_CoreDebug /
AnnaBridge	172:65be27845400	1152
AnnaBridge	172:65be27845400	1153
AnnaBridge	172:65be27845400	1154	/**
AnnaBridge	172:65be27845400	1155	\ingroup CMSIS_core_register
AnnaBridge	172:65be27845400	1156	\defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge	172:65be27845400	1157	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
AnnaBridge	172:65be27845400	1158	@{
AnnaBridge	172:65be27845400	1159	*/
AnnaBridge	172:65be27845400	1160
AnnaBridge	172:65be27845400	1161	/**
AnnaBridge	172:65be27845400	1162	\brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge	172:65be27845400	1163	\param[in] field Name of the register bit field.
AnnaBridge	172:65be27845400	1164	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge	172:65be27845400	1165	\return Masked and shifted value.
AnnaBridge	172:65be27845400	1166	*/
AnnaBridge	172:65be27845400	1167	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge	172:65be27845400	1168
AnnaBridge	172:65be27845400	1169	/**
AnnaBridge	172:65be27845400	1170	\brief Mask and shift a register value to extract a bit filed value.
AnnaBridge	172:65be27845400	1171	\param[in] field Name of the register bit field.
AnnaBridge	172:65be27845400	1172	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge	172:65be27845400	1173	\return Masked and shifted bit field value.
AnnaBridge	172:65be27845400	1174	*/
AnnaBridge	172:65be27845400	1175	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge	172:65be27845400	1176
AnnaBridge	172:65be27845400	1177	/@} end of group CMSIS_core_bitfield /
AnnaBridge	172:65be27845400	1178
AnnaBridge	172:65be27845400	1179
AnnaBridge	172:65be27845400	1180	/**
AnnaBridge	172:65be27845400	1181	\ingroup CMSIS_core_register
AnnaBridge	172:65be27845400	1182	\defgroup CMSIS_core_base Core Definitions
AnnaBridge	172:65be27845400	1183	\brief Definitions for base addresses, unions, and structures.
AnnaBridge	172:65be27845400	1184	@{
AnnaBridge	172:65be27845400	1185	*/
AnnaBridge	172:65be27845400	1186
AnnaBridge	172:65be27845400	1187	/* Memory mapping of Core Hardware */
AnnaBridge	172:65be27845400	1188	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
AnnaBridge	172:65be27845400	1189	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
AnnaBridge	172:65be27845400	1190	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
AnnaBridge	172:65be27845400	1191	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
AnnaBridge	172:65be27845400	1192	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
AnnaBridge	172:65be27845400	1193	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
AnnaBridge	172:65be27845400	1194	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
AnnaBridge	172:65be27845400	1195
AnnaBridge	172:65be27845400	1196
AnnaBridge	172:65be27845400	1197	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
AnnaBridge	172:65be27845400	1198	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
AnnaBridge	172:65be27845400	1199	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
AnnaBridge	172:65be27845400	1200	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
AnnaBridge	172:65be27845400	1201	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
AnnaBridge	172:65be27845400	1202	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE ) /!< Core Debug configuration struct */
AnnaBridge	172:65be27845400	1203
AnnaBridge	172:65be27845400	1204	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	172:65be27845400	1205	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
AnnaBridge	172:65be27845400	1206	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
AnnaBridge	172:65be27845400	1207	#endif
AnnaBridge	172:65be27845400	1208
AnnaBridge	172:65be27845400	1209	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	172:65be27845400	1210	#define SAU_BASE (SCS_BASE + 0x0DD0UL) /!< Security Attribution Unit /
AnnaBridge	172:65be27845400	1211	#define SAU ((SAU_Type ) SAU_BASE ) /!< Security Attribution Unit */
AnnaBridge	172:65be27845400	1212	#endif
AnnaBridge	172:65be27845400	1213
AnnaBridge	172:65be27845400	1214	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	172:65be27845400	1215	#define SCS_BASE_NS (0xE002E000UL) /!< System Control Space Base Address (non-secure address space) /
AnnaBridge	172:65be27845400	1216	#define CoreDebug_BASE_NS (0xE002EDF0UL) /!< Core Debug Base Address (non-secure address space) /
AnnaBridge	172:65be27845400	1217	#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /!< SysTick Base Address (non-secure address space) /
AnnaBridge	172:65be27845400	1218	#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /!< NVIC Base Address (non-secure address space) /
AnnaBridge	172:65be27845400	1219	#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /!< System Control Block Base Address (non-secure address space) /
AnnaBridge	172:65be27845400	1220
AnnaBridge	172:65be27845400	1221	#define SCB_NS ((SCB_Type ) SCB_BASE_NS ) /!< SCB configuration struct (non-secure address space) */
AnnaBridge	172:65be27845400	1222	#define SysTick_NS ((SysTick_Type ) SysTick_BASE_NS ) /!< SysTick configuration struct (non-secure address space) */
AnnaBridge	172:65be27845400	1223	#define NVIC_NS ((NVIC_Type ) NVIC_BASE_NS ) /!< NVIC configuration struct (non-secure address space) */
AnnaBridge	172:65be27845400	1224	#define CoreDebug_NS ((CoreDebug_Type ) CoreDebug_BASE_NS) /!< Core Debug configuration struct (non-secure address space) */
AnnaBridge	172:65be27845400	1225
AnnaBridge	172:65be27845400	1226	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	172:65be27845400	1227	#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /!< Memory Protection Unit (non-secure address space) /
AnnaBridge	172:65be27845400	1228	#define MPU_NS ((MPU_Type ) MPU_BASE_NS ) /!< Memory Protection Unit (non-secure address space) */
AnnaBridge	172:65be27845400	1229	#endif
AnnaBridge	172:65be27845400	1230
AnnaBridge	172:65be27845400	1231	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	172:65be27845400	1232	/@} /
AnnaBridge	172:65be27845400	1233
AnnaBridge	172:65be27845400	1234
AnnaBridge	172:65be27845400	1235
AnnaBridge	172:65be27845400	1236	/*******************************************************************************
AnnaBridge	172:65be27845400	1237	* Hardware Abstraction Layer
AnnaBridge	172:65be27845400	1238	Core Function Interface contains:
AnnaBridge	172:65be27845400	1239	- Core NVIC Functions
AnnaBridge	172:65be27845400	1240	- Core SysTick Functions
AnnaBridge	172:65be27845400	1241	- Core Register Access Functions
AnnaBridge	172:65be27845400	1242	******************************************************************************/
AnnaBridge	172:65be27845400	1243	/**
AnnaBridge	172:65be27845400	1244	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
AnnaBridge	172:65be27845400	1245	*/
AnnaBridge	172:65be27845400	1246
AnnaBridge	172:65be27845400	1247
AnnaBridge	172:65be27845400	1248
AnnaBridge	172:65be27845400	1249	/* ########################## NVIC functions #################################### */
AnnaBridge	172:65be27845400	1250	/**
AnnaBridge	172:65be27845400	1251	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	172:65be27845400	1252	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge	172:65be27845400	1253	\brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge	172:65be27845400	1254	@{
AnnaBridge	172:65be27845400	1255	*/
AnnaBridge	172:65be27845400	1256
AnnaBridge	172:65be27845400	1257	#ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge	172:65be27845400	1258	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge	172:65be27845400	1259	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge	172:65be27845400	1260	#endif
AnnaBridge	172:65be27845400	1261	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge	172:65be27845400	1262	#else
AnnaBridge	172:65be27845400	1263	/#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 /
AnnaBridge	172:65be27845400	1264	/#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 /
AnnaBridge	172:65be27845400	1265	#define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge	172:65be27845400	1266	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge	172:65be27845400	1267	#define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge	172:65be27845400	1268	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge	172:65be27845400	1269	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge	172:65be27845400	1270	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge	172:65be27845400	1271	#define NVIC_GetActive __NVIC_GetActive
AnnaBridge	172:65be27845400	1272	#define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge	172:65be27845400	1273	#define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge	172:65be27845400	1274	#define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge	172:65be27845400	1275	#endif /* CMSIS_NVIC_VIRTUAL */
AnnaBridge	172:65be27845400	1276
AnnaBridge	172:65be27845400	1277	#ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge	172:65be27845400	1278	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge	172:65be27845400	1279	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge	172:65be27845400	1280	#endif
AnnaBridge	172:65be27845400	1281	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge	172:65be27845400	1282	#else
AnnaBridge	172:65be27845400	1283	#define NVIC_SetVector __NVIC_SetVector
AnnaBridge	172:65be27845400	1284	#define NVIC_GetVector __NVIC_GetVector
AnnaBridge	172:65be27845400	1285	#endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge	172:65be27845400	1286
AnnaBridge	172:65be27845400	1287	#define NVIC_USER_IRQ_OFFSET 16
AnnaBridge	172:65be27845400	1288
AnnaBridge	172:65be27845400	1289
AnnaBridge	172:65be27845400	1290	/* Special LR values for Secure/Non-Secure call handling and exception handling */
AnnaBridge	172:65be27845400	1291
AnnaBridge	172:65be27845400	1292	/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
AnnaBridge	172:65be27845400	1293	#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
AnnaBridge	172:65be27845400	1294
AnnaBridge	172:65be27845400	1295	/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
AnnaBridge	172:65be27845400	1296	#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
AnnaBridge	172:65be27845400	1297	#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
AnnaBridge	172:65be27845400	1298	#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
AnnaBridge	172:65be27845400	1299	#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
AnnaBridge	172:65be27845400	1300	#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
AnnaBridge	172:65be27845400	1301	#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
AnnaBridge	172:65be27845400	1302	#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
AnnaBridge	172:65be27845400	1303
AnnaBridge	172:65be27845400	1304	/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
AnnaBridge	172:65be27845400	1305	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
AnnaBridge	172:65be27845400	1306	#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
AnnaBridge	172:65be27845400	1307	#else
AnnaBridge	172:65be27845400	1308	#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
AnnaBridge	172:65be27845400	1309	#endif
AnnaBridge	172:65be27845400	1310
AnnaBridge	172:65be27845400	1311
AnnaBridge	172:65be27845400	1312	/* Interrupt Priorities are WORD accessible only under Armv6-M */
AnnaBridge	172:65be27845400	1313	/* The following MACROS handle generation of the register offset and byte masks */
AnnaBridge	172:65be27845400	1314	#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
AnnaBridge	172:65be27845400	1315	#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
AnnaBridge	172:65be27845400	1316	#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
AnnaBridge	172:65be27845400	1317
AnnaBridge	172:65be27845400	1318	#define __NVIC_SetPriorityGrouping(X) (void)(X)
AnnaBridge	172:65be27845400	1319	#define __NVIC_GetPriorityGrouping() (0U)
AnnaBridge	172:65be27845400	1320
AnnaBridge	172:65be27845400	1321	/**
AnnaBridge	172:65be27845400	1322	\brief Enable Interrupt
AnnaBridge	172:65be27845400	1323	\details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge	172:65be27845400	1324	\param [in] IRQn Device specific interrupt number.
AnnaBridge	172:65be27845400	1325	\note IRQn must not be negative.
AnnaBridge	172:65be27845400	1326	*/
AnnaBridge	172:65be27845400	1327	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge	172:65be27845400	1328	{
AnnaBridge	172:65be27845400	1329	if ((int32_t)(IRQn) >= 0)
AnnaBridge	172:65be27845400	1330	{
AnnaBridge	172:65be27845400	1331	NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	172:65be27845400	1332	}
AnnaBridge	172:65be27845400	1333	}
AnnaBridge	172:65be27845400	1334
AnnaBridge	172:65be27845400	1335
AnnaBridge	172:65be27845400	1336	/**
AnnaBridge	172:65be27845400	1337	\brief Get Interrupt Enable status
AnnaBridge	172:65be27845400	1338	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge	172:65be27845400	1339	\param [in] IRQn Device specific interrupt number.
AnnaBridge	172:65be27845400	1340	\return 0 Interrupt is not enabled.
AnnaBridge	172:65be27845400	1341	\return 1 Interrupt is enabled.
AnnaBridge	172:65be27845400	1342	\note IRQn must not be negative.
AnnaBridge	172:65be27845400	1343	*/
AnnaBridge	172:65be27845400	1344	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
AnnaBridge	172:65be27845400	1345	{
AnnaBridge	172:65be27845400	1346	if ((int32_t)(IRQn) >= 0)
AnnaBridge	172:65be27845400	1347	{
AnnaBridge	172:65be27845400	1348	return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	172:65be27845400	1349	}
AnnaBridge	172:65be27845400	1350	else
AnnaBridge	172:65be27845400	1351	{
AnnaBridge	172:65be27845400	1352	return(0U);
AnnaBridge	172:65be27845400	1353	}
AnnaBridge	172:65be27845400	1354	}
AnnaBridge	172:65be27845400	1355
AnnaBridge	172:65be27845400	1356
AnnaBridge	172:65be27845400	1357	/**
AnnaBridge	172:65be27845400	1358	\brief Disable Interrupt
AnnaBridge	172:65be27845400	1359	\details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge	172:65be27845400	1360	\param [in] IRQn Device specific interrupt number.
AnnaBridge	172:65be27845400	1361	\note IRQn must not be negative.
AnnaBridge	172:65be27845400	1362	*/
AnnaBridge	172:65be27845400	1363	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge	172:65be27845400	1364	{
AnnaBridge	172:65be27845400	1365	if ((int32_t)(IRQn) >= 0)
AnnaBridge	172:65be27845400	1366	{
AnnaBridge	172:65be27845400	1367	NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	172:65be27845400	1368	__DSB();
AnnaBridge	172:65be27845400	1369	__ISB();
AnnaBridge	172:65be27845400	1370	}
AnnaBridge	172:65be27845400	1371	}
AnnaBridge	172:65be27845400	1372
AnnaBridge	172:65be27845400	1373
AnnaBridge	172:65be27845400	1374	/**
AnnaBridge	172:65be27845400	1375	\brief Get Pending Interrupt
AnnaBridge	172:65be27845400	1376	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge	172:65be27845400	1377	\param [in] IRQn Device specific interrupt number.
AnnaBridge	172:65be27845400	1378	\return 0 Interrupt status is not pending.
AnnaBridge	172:65be27845400	1379	\return 1 Interrupt status is pending.
AnnaBridge	172:65be27845400	1380	\note IRQn must not be negative.
AnnaBridge	172:65be27845400	1381	*/
AnnaBridge	172:65be27845400	1382	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
AnnaBridge	172:65be27845400	1383	{
AnnaBridge	172:65be27845400	1384	if ((int32_t)(IRQn) >= 0)
AnnaBridge	172:65be27845400	1385	{
AnnaBridge	172:65be27845400	1386	return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	172:65be27845400	1387	}
AnnaBridge	172:65be27845400	1388	else
AnnaBridge	172:65be27845400	1389	{
AnnaBridge	172:65be27845400	1390	return(0U);
AnnaBridge	172:65be27845400	1391	}
AnnaBridge	172:65be27845400	1392	}
AnnaBridge	172:65be27845400	1393
AnnaBridge	172:65be27845400	1394
AnnaBridge	172:65be27845400	1395	/**
AnnaBridge	172:65be27845400	1396	\brief Set Pending Interrupt
AnnaBridge	172:65be27845400	1397	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge	172:65be27845400	1398	\param [in] IRQn Device specific interrupt number.
AnnaBridge	172:65be27845400	1399	\note IRQn must not be negative.
AnnaBridge	172:65be27845400	1400	*/
AnnaBridge	172:65be27845400	1401	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge	172:65be27845400	1402	{
AnnaBridge	172:65be27845400	1403	if ((int32_t)(IRQn) >= 0)
AnnaBridge	172:65be27845400	1404	{
AnnaBridge	172:65be27845400	1405	NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	172:65be27845400	1406	}
AnnaBridge	172:65be27845400	1407	}
AnnaBridge	172:65be27845400	1408
AnnaBridge	172:65be27845400	1409
AnnaBridge	172:65be27845400	1410	/**
AnnaBridge	172:65be27845400	1411	\brief Clear Pending Interrupt
AnnaBridge	172:65be27845400	1412	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge	172:65be27845400	1413	\param [in] IRQn Device specific interrupt number.
AnnaBridge	172:65be27845400	1414	\note IRQn must not be negative.
AnnaBridge	172:65be27845400	1415	*/
AnnaBridge	172:65be27845400	1416	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge	172:65be27845400	1417	{
AnnaBridge	172:65be27845400	1418	if ((int32_t)(IRQn) >= 0)
AnnaBridge	172:65be27845400	1419	{
AnnaBridge	172:65be27845400	1420	NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	172:65be27845400	1421	}
AnnaBridge	172:65be27845400	1422	}
AnnaBridge	172:65be27845400	1423
AnnaBridge	172:65be27845400	1424
AnnaBridge	172:65be27845400	1425	/**
AnnaBridge	172:65be27845400	1426	\brief Get Active Interrupt
AnnaBridge	172:65be27845400	1427	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
AnnaBridge	172:65be27845400	1428	\param [in] IRQn Device specific interrupt number.
AnnaBridge	172:65be27845400	1429	\return 0 Interrupt status is not active.
AnnaBridge	172:65be27845400	1430	\return 1 Interrupt status is active.
AnnaBridge	172:65be27845400	1431	\note IRQn must not be negative.
AnnaBridge	172:65be27845400	1432	*/
AnnaBridge	172:65be27845400	1433	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
AnnaBridge	172:65be27845400	1434	{
AnnaBridge	172:65be27845400	1435	if ((int32_t)(IRQn) >= 0)
AnnaBridge	172:65be27845400	1436	{
AnnaBridge	172:65be27845400	1437	return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	172:65be27845400	1438	}
AnnaBridge	172:65be27845400	1439	else
AnnaBridge	172:65be27845400	1440	{
AnnaBridge	172:65be27845400	1441	return(0U);
AnnaBridge	172:65be27845400	1442	}
AnnaBridge	172:65be27845400	1443	}
AnnaBridge	172:65be27845400	1444
AnnaBridge	172:65be27845400	1445
AnnaBridge	172:65be27845400	1446	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	172:65be27845400	1447	/**
AnnaBridge	172:65be27845400	1448	\brief Get Interrupt Target State
AnnaBridge	172:65be27845400	1449	\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge	172:65be27845400	1450	\param [in] IRQn Device specific interrupt number.
AnnaBridge	172:65be27845400	1451	\return 0 if interrupt is assigned to Secure
AnnaBridge	172:65be27845400	1452	\return 1 if interrupt is assigned to Non Secure
AnnaBridge	172:65be27845400	1453	\note IRQn must not be negative.
AnnaBridge	172:65be27845400	1454	*/
AnnaBridge	172:65be27845400	1455	__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
AnnaBridge	172:65be27845400	1456	{
AnnaBridge	172:65be27845400	1457	if ((int32_t)(IRQn) >= 0)
AnnaBridge	172:65be27845400	1458	{
AnnaBridge	172:65be27845400	1459	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	172:65be27845400	1460	}
AnnaBridge	172:65be27845400	1461	else
AnnaBridge	172:65be27845400	1462	{
AnnaBridge	172:65be27845400	1463	return(0U);
AnnaBridge	172:65be27845400	1464	}
AnnaBridge	172:65be27845400	1465	}
AnnaBridge	172:65be27845400	1466
AnnaBridge	172:65be27845400	1467
AnnaBridge	172:65be27845400	1468	/**
AnnaBridge	172:65be27845400	1469	\brief Set Interrupt Target State
AnnaBridge	172:65be27845400	1470	\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge	172:65be27845400	1471	\param [in] IRQn Device specific interrupt number.
AnnaBridge	172:65be27845400	1472	\return 0 if interrupt is assigned to Secure
AnnaBridge	172:65be27845400	1473	1 if interrupt is assigned to Non Secure
AnnaBridge	172:65be27845400	1474	\note IRQn must not be negative.
AnnaBridge	172:65be27845400	1475	*/
AnnaBridge	172:65be27845400	1476	__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
AnnaBridge	172:65be27845400	1477	{
AnnaBridge	172:65be27845400	1478	if ((int32_t)(IRQn) >= 0)
AnnaBridge	172:65be27845400	1479	{
AnnaBridge	172:65be27845400	1480	NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] \|= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
AnnaBridge	172:65be27845400	1481	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	172:65be27845400	1482	}
AnnaBridge	172:65be27845400	1483	else
AnnaBridge	172:65be27845400	1484	{
AnnaBridge	172:65be27845400	1485	return(0U);
AnnaBridge	172:65be27845400	1486	}
AnnaBridge	172:65be27845400	1487	}
AnnaBridge	172:65be27845400	1488
AnnaBridge	172:65be27845400	1489
AnnaBridge	172:65be27845400	1490	/**
AnnaBridge	172:65be27845400	1491	\brief Clear Interrupt Target State
AnnaBridge	172:65be27845400	1492	\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
AnnaBridge	172:65be27845400	1493	\param [in] IRQn Device specific interrupt number.
AnnaBridge	172:65be27845400	1494	\return 0 if interrupt is assigned to Secure
AnnaBridge	172:65be27845400	1495	1 if interrupt is assigned to Non Secure
AnnaBridge	172:65be27845400	1496	\note IRQn must not be negative.
AnnaBridge	172:65be27845400	1497	*/
AnnaBridge	172:65be27845400	1498	__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
AnnaBridge	172:65be27845400	1499	{
AnnaBridge	172:65be27845400	1500	if ((int32_t)(IRQn) >= 0)
AnnaBridge	172:65be27845400	1501	{
AnnaBridge	172:65be27845400	1502	NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
AnnaBridge	172:65be27845400	1503	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	172:65be27845400	1504	}
AnnaBridge	172:65be27845400	1505	else
AnnaBridge	172:65be27845400	1506	{
AnnaBridge	172:65be27845400	1507	return(0U);
AnnaBridge	172:65be27845400	1508	}
AnnaBridge	172:65be27845400	1509	}
AnnaBridge	172:65be27845400	1510	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	172:65be27845400	1511
AnnaBridge	172:65be27845400	1512
AnnaBridge	172:65be27845400	1513	/**
AnnaBridge	172:65be27845400	1514	\brief Set Interrupt Priority
AnnaBridge	172:65be27845400	1515	\details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge	172:65be27845400	1516	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	172:65be27845400	1517	or negative to specify a processor exception.
AnnaBridge	172:65be27845400	1518	\param [in] IRQn Interrupt number.
AnnaBridge	172:65be27845400	1519	\param [in] priority Priority to set.
AnnaBridge	172:65be27845400	1520	\note The priority cannot be set for every processor exception.
AnnaBridge	172:65be27845400	1521	*/
AnnaBridge	172:65be27845400	1522	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge	172:65be27845400	1523	{
AnnaBridge	172:65be27845400	1524	if ((int32_t)(IRQn) >= 0)
AnnaBridge	172:65be27845400	1525	{
AnnaBridge	172:65be27845400	1526	NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
AnnaBridge	172:65be27845400	1527	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge	172:65be27845400	1528	}
AnnaBridge	172:65be27845400	1529	else
AnnaBridge	172:65be27845400	1530	{
AnnaBridge	172:65be27845400	1531	SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
AnnaBridge	172:65be27845400	1532	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge	172:65be27845400	1533	}
AnnaBridge	172:65be27845400	1534	}
AnnaBridge	172:65be27845400	1535
AnnaBridge	172:65be27845400	1536
AnnaBridge	172:65be27845400	1537	/**
AnnaBridge	172:65be27845400	1538	\brief Get Interrupt Priority
AnnaBridge	172:65be27845400	1539	\details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge	172:65be27845400	1540	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	172:65be27845400	1541	or negative to specify a processor exception.
AnnaBridge	172:65be27845400	1542	\param [in] IRQn Interrupt number.
AnnaBridge	172:65be27845400	1543	\return Interrupt Priority.
AnnaBridge	172:65be27845400	1544	Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge	172:65be27845400	1545	*/
AnnaBridge	172:65be27845400	1546	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge	172:65be27845400	1547	{
AnnaBridge	172:65be27845400	1548
AnnaBridge	172:65be27845400	1549	if ((int32_t)(IRQn) >= 0)
AnnaBridge	172:65be27845400	1550	{
AnnaBridge	172:65be27845400	1551	return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	172:65be27845400	1552	}
AnnaBridge	172:65be27845400	1553	else
AnnaBridge	172:65be27845400	1554	{
AnnaBridge	172:65be27845400	1555	return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	172:65be27845400	1556	}
AnnaBridge	172:65be27845400	1557	}
AnnaBridge	172:65be27845400	1558
AnnaBridge	172:65be27845400	1559
AnnaBridge	172:65be27845400	1560	/**
AnnaBridge	172:65be27845400	1561	\brief Encode Priority
AnnaBridge	172:65be27845400	1562	\details Encodes the priority for an interrupt with the given priority group,
AnnaBridge	172:65be27845400	1563	preemptive priority value, and subpriority value.
AnnaBridge	172:65be27845400	1564	In case of a conflict between priority grouping and available
AnnaBridge	172:65be27845400	1565	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge	172:65be27845400	1566	\param [in] PriorityGroup Used priority group.
AnnaBridge	172:65be27845400	1567	\param [in] PreemptPriority Preemptive priority value (starting from 0).
AnnaBridge	172:65be27845400	1568	\param [in] SubPriority Subpriority value (starting from 0).
AnnaBridge	172:65be27845400	1569	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
AnnaBridge	172:65be27845400	1570	*/
AnnaBridge	172:65be27845400	1571	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
AnnaBridge	172:65be27845400	1572	{
AnnaBridge	172:65be27845400	1573	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	172:65be27845400	1574	uint32_t PreemptPriorityBits;
AnnaBridge	172:65be27845400	1575	uint32_t SubPriorityBits;
AnnaBridge	172:65be27845400	1576
AnnaBridge	172:65be27845400	1577	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge	172:65be27845400	1578	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge	172:65be27845400	1579
AnnaBridge	172:65be27845400	1580	return (
AnnaBridge	172:65be27845400	1581	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
AnnaBridge	172:65be27845400	1582	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
AnnaBridge	172:65be27845400	1583	);
AnnaBridge	172:65be27845400	1584	}
AnnaBridge	172:65be27845400	1585
AnnaBridge	172:65be27845400	1586
AnnaBridge	172:65be27845400	1587	/**
AnnaBridge	172:65be27845400	1588	\brief Decode Priority
AnnaBridge	172:65be27845400	1589	\details Decodes an interrupt priority value with a given priority group to
AnnaBridge	172:65be27845400	1590	preemptive priority value and subpriority value.
AnnaBridge	172:65be27845400	1591	In case of a conflict between priority grouping and available
AnnaBridge	172:65be27845400	1592	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
AnnaBridge	172:65be27845400	1593	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
AnnaBridge	172:65be27845400	1594	\param [in] PriorityGroup Used priority group.
AnnaBridge	172:65be27845400	1595	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
AnnaBridge	172:65be27845400	1596	\param [out] pSubPriority Subpriority value (starting from 0).
AnnaBridge	172:65be27845400	1597	*/
AnnaBridge	172:65be27845400	1598	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
AnnaBridge	172:65be27845400	1599	{
AnnaBridge	172:65be27845400	1600	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
AnnaBridge	172:65be27845400	1601	uint32_t PreemptPriorityBits;
AnnaBridge	172:65be27845400	1602	uint32_t SubPriorityBits;
AnnaBridge	172:65be27845400	1603
AnnaBridge	172:65be27845400	1604	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
AnnaBridge	172:65be27845400	1605	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
AnnaBridge	172:65be27845400	1606
AnnaBridge	172:65be27845400	1607	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
AnnaBridge	172:65be27845400	1608	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
AnnaBridge	172:65be27845400	1609	}
AnnaBridge	172:65be27845400	1610
AnnaBridge	172:65be27845400	1611
AnnaBridge	172:65be27845400	1612	/**
AnnaBridge	172:65be27845400	1613	\brief Set Interrupt Vector
AnnaBridge	172:65be27845400	1614	\details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge	172:65be27845400	1615	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	172:65be27845400	1616	or negative to specify a processor exception.
AnnaBridge	172:65be27845400	1617	VTOR must been relocated to SRAM before.
AnnaBridge	172:65be27845400	1618	If VTOR is not present address 0 must be mapped to SRAM.
AnnaBridge	172:65be27845400	1619	\param [in] IRQn Interrupt number
AnnaBridge	172:65be27845400	1620	\param [in] vector Address of interrupt handler function
AnnaBridge	172:65be27845400	1621	*/
AnnaBridge	172:65be27845400	1622	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge	172:65be27845400	1623	{
AnnaBridge	172:65be27845400	1624	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge	172:65be27845400	1625	uint32_t vectors = (uint32_t )SCB->VTOR;
AnnaBridge	172:65be27845400	1626	#else
AnnaBridge	172:65be27845400	1627	uint32_t vectors = (uint32_t )0x0U;
AnnaBridge	172:65be27845400	1628	#endif
AnnaBridge	172:65be27845400	1629	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge	172:65be27845400	1630	}
AnnaBridge	172:65be27845400	1631
AnnaBridge	172:65be27845400	1632
AnnaBridge	172:65be27845400	1633	/**
AnnaBridge	172:65be27845400	1634	\brief Get Interrupt Vector
AnnaBridge	172:65be27845400	1635	\details Reads an interrupt vector from interrupt vector table.
AnnaBridge	172:65be27845400	1636	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	172:65be27845400	1637	or negative to specify a processor exception.
AnnaBridge	172:65be27845400	1638	\param [in] IRQn Interrupt number.
AnnaBridge	172:65be27845400	1639	\return Address of interrupt handler function
AnnaBridge	172:65be27845400	1640	*/
AnnaBridge	172:65be27845400	1641	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge	172:65be27845400	1642	{
AnnaBridge	172:65be27845400	1643	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
AnnaBridge	172:65be27845400	1644	uint32_t vectors = (uint32_t )SCB->VTOR;
AnnaBridge	172:65be27845400	1645	#else
AnnaBridge	172:65be27845400	1646	uint32_t vectors = (uint32_t )0x0U;
AnnaBridge	172:65be27845400	1647	#endif
AnnaBridge	172:65be27845400	1648	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge	172:65be27845400	1649	}
AnnaBridge	172:65be27845400	1650
AnnaBridge	172:65be27845400	1651
AnnaBridge	172:65be27845400	1652	/**
AnnaBridge	172:65be27845400	1653	\brief System Reset
AnnaBridge	172:65be27845400	1654	\details Initiates a system reset request to reset the MCU.
AnnaBridge	172:65be27845400	1655	*/
AnnaBridge	172:65be27845400	1656	__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
AnnaBridge	172:65be27845400	1657	{
AnnaBridge	172:65be27845400	1658	__DSB(); /* Ensure all outstanding memory accesses included
AnnaBridge	172:65be27845400	1659	buffered write are completed before reset */
AnnaBridge	172:65be27845400	1660	SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
AnnaBridge	172:65be27845400	1661	SCB_AIRCR_SYSRESETREQ_Msk);
AnnaBridge	172:65be27845400	1662	__DSB(); /* Ensure completion of memory access */
AnnaBridge	172:65be27845400	1663
AnnaBridge	172:65be27845400	1664	for(;;) /* wait until reset */
AnnaBridge	172:65be27845400	1665	{
AnnaBridge	172:65be27845400	1666	__NOP();
AnnaBridge	172:65be27845400	1667	}
AnnaBridge	172:65be27845400	1668	}
AnnaBridge	172:65be27845400	1669
AnnaBridge	172:65be27845400	1670	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	172:65be27845400	1671	/**
AnnaBridge	172:65be27845400	1672	\brief Enable Interrupt (non-secure)
AnnaBridge	172:65be27845400	1673	\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
AnnaBridge	172:65be27845400	1674	\param [in] IRQn Device specific interrupt number.
AnnaBridge	172:65be27845400	1675	\note IRQn must not be negative.
AnnaBridge	172:65be27845400	1676	*/
AnnaBridge	172:65be27845400	1677	__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
AnnaBridge	172:65be27845400	1678	{
AnnaBridge	172:65be27845400	1679	if ((int32_t)(IRQn) >= 0)
AnnaBridge	172:65be27845400	1680	{
AnnaBridge	172:65be27845400	1681	NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	172:65be27845400	1682	}
AnnaBridge	172:65be27845400	1683	}
AnnaBridge	172:65be27845400	1684
AnnaBridge	172:65be27845400	1685
AnnaBridge	172:65be27845400	1686	/**
AnnaBridge	172:65be27845400	1687	\brief Get Interrupt Enable status (non-secure)
AnnaBridge	172:65be27845400	1688	\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
AnnaBridge	172:65be27845400	1689	\param [in] IRQn Device specific interrupt number.
AnnaBridge	172:65be27845400	1690	\return 0 Interrupt is not enabled.
AnnaBridge	172:65be27845400	1691	\return 1 Interrupt is enabled.
AnnaBridge	172:65be27845400	1692	\note IRQn must not be negative.
AnnaBridge	172:65be27845400	1693	*/
AnnaBridge	172:65be27845400	1694	__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
AnnaBridge	172:65be27845400	1695	{
AnnaBridge	172:65be27845400	1696	if ((int32_t)(IRQn) >= 0)
AnnaBridge	172:65be27845400	1697	{
AnnaBridge	172:65be27845400	1698	return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	172:65be27845400	1699	}
AnnaBridge	172:65be27845400	1700	else
AnnaBridge	172:65be27845400	1701	{
AnnaBridge	172:65be27845400	1702	return(0U);
AnnaBridge	172:65be27845400	1703	}
AnnaBridge	172:65be27845400	1704	}
AnnaBridge	172:65be27845400	1705
AnnaBridge	172:65be27845400	1706
AnnaBridge	172:65be27845400	1707	/**
AnnaBridge	172:65be27845400	1708	\brief Disable Interrupt (non-secure)
AnnaBridge	172:65be27845400	1709	\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
AnnaBridge	172:65be27845400	1710	\param [in] IRQn Device specific interrupt number.
AnnaBridge	172:65be27845400	1711	\note IRQn must not be negative.
AnnaBridge	172:65be27845400	1712	*/
AnnaBridge	172:65be27845400	1713	__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
AnnaBridge	172:65be27845400	1714	{
AnnaBridge	172:65be27845400	1715	if ((int32_t)(IRQn) >= 0)
AnnaBridge	172:65be27845400	1716	{
AnnaBridge	172:65be27845400	1717	NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	172:65be27845400	1718	}
AnnaBridge	172:65be27845400	1719	}
AnnaBridge	172:65be27845400	1720
AnnaBridge	172:65be27845400	1721
AnnaBridge	172:65be27845400	1722	/**
AnnaBridge	172:65be27845400	1723	\brief Get Pending Interrupt (non-secure)
AnnaBridge	172:65be27845400	1724	\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
AnnaBridge	172:65be27845400	1725	\param [in] IRQn Device specific interrupt number.
AnnaBridge	172:65be27845400	1726	\return 0 Interrupt status is not pending.
AnnaBridge	172:65be27845400	1727	\return 1 Interrupt status is pending.
AnnaBridge	172:65be27845400	1728	\note IRQn must not be negative.
AnnaBridge	172:65be27845400	1729	*/
AnnaBridge	172:65be27845400	1730	__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge	172:65be27845400	1731	{
AnnaBridge	172:65be27845400	1732	if ((int32_t)(IRQn) >= 0)
AnnaBridge	172:65be27845400	1733	{
AnnaBridge	172:65be27845400	1734	return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	172:65be27845400	1735	}
AnnaBridge	172:65be27845400	1736	else
AnnaBridge	172:65be27845400	1737	{
AnnaBridge	172:65be27845400	1738	return(0U);
AnnaBridge	172:65be27845400	1739	}
AnnaBridge	172:65be27845400	1740	}
AnnaBridge	172:65be27845400	1741
AnnaBridge	172:65be27845400	1742
AnnaBridge	172:65be27845400	1743	/**
AnnaBridge	172:65be27845400	1744	\brief Set Pending Interrupt (non-secure)
AnnaBridge	172:65be27845400	1745	\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
AnnaBridge	172:65be27845400	1746	\param [in] IRQn Device specific interrupt number.
AnnaBridge	172:65be27845400	1747	\note IRQn must not be negative.
AnnaBridge	172:65be27845400	1748	*/
AnnaBridge	172:65be27845400	1749	__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge	172:65be27845400	1750	{
AnnaBridge	172:65be27845400	1751	if ((int32_t)(IRQn) >= 0)
AnnaBridge	172:65be27845400	1752	{
AnnaBridge	172:65be27845400	1753	NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	172:65be27845400	1754	}
AnnaBridge	172:65be27845400	1755	}
AnnaBridge	172:65be27845400	1756
AnnaBridge	172:65be27845400	1757
AnnaBridge	172:65be27845400	1758	/**
AnnaBridge	172:65be27845400	1759	\brief Clear Pending Interrupt (non-secure)
AnnaBridge	172:65be27845400	1760	\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
AnnaBridge	172:65be27845400	1761	\param [in] IRQn Device specific interrupt number.
AnnaBridge	172:65be27845400	1762	\note IRQn must not be negative.
AnnaBridge	172:65be27845400	1763	*/
AnnaBridge	172:65be27845400	1764	__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
AnnaBridge	172:65be27845400	1765	{
AnnaBridge	172:65be27845400	1766	if ((int32_t)(IRQn) >= 0)
AnnaBridge	172:65be27845400	1767	{
AnnaBridge	172:65be27845400	1768	NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
AnnaBridge	172:65be27845400	1769	}
AnnaBridge	172:65be27845400	1770	}
AnnaBridge	172:65be27845400	1771
AnnaBridge	172:65be27845400	1772
AnnaBridge	172:65be27845400	1773	/**
AnnaBridge	172:65be27845400	1774	\brief Get Active Interrupt (non-secure)
AnnaBridge	172:65be27845400	1775	\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
AnnaBridge	172:65be27845400	1776	\param [in] IRQn Device specific interrupt number.
AnnaBridge	172:65be27845400	1777	\return 0 Interrupt status is not active.
AnnaBridge	172:65be27845400	1778	\return 1 Interrupt status is active.
AnnaBridge	172:65be27845400	1779	\note IRQn must not be negative.
AnnaBridge	172:65be27845400	1780	*/
AnnaBridge	172:65be27845400	1781	__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
AnnaBridge	172:65be27845400	1782	{
AnnaBridge	172:65be27845400	1783	if ((int32_t)(IRQn) >= 0)
AnnaBridge	172:65be27845400	1784	{
AnnaBridge	172:65be27845400	1785	return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	172:65be27845400	1786	}
AnnaBridge	172:65be27845400	1787	else
AnnaBridge	172:65be27845400	1788	{
AnnaBridge	172:65be27845400	1789	return(0U);
AnnaBridge	172:65be27845400	1790	}
AnnaBridge	172:65be27845400	1791	}
AnnaBridge	172:65be27845400	1792
AnnaBridge	172:65be27845400	1793
AnnaBridge	172:65be27845400	1794	/**
AnnaBridge	172:65be27845400	1795	\brief Set Interrupt Priority (non-secure)
AnnaBridge	172:65be27845400	1796	\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
AnnaBridge	172:65be27845400	1797	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	172:65be27845400	1798	or negative to specify a processor exception.
AnnaBridge	172:65be27845400	1799	\param [in] IRQn Interrupt number.
AnnaBridge	172:65be27845400	1800	\param [in] priority Priority to set.
AnnaBridge	172:65be27845400	1801	\note The priority cannot be set for every non-secure processor exception.
AnnaBridge	172:65be27845400	1802	*/
AnnaBridge	172:65be27845400	1803	__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
AnnaBridge	172:65be27845400	1804	{
AnnaBridge	172:65be27845400	1805	if ((int32_t)(IRQn) >= 0)
AnnaBridge	172:65be27845400	1806	{
AnnaBridge	172:65be27845400	1807	NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
AnnaBridge	172:65be27845400	1808	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge	172:65be27845400	1809	}
AnnaBridge	172:65be27845400	1810	else
AnnaBridge	172:65be27845400	1811	{
AnnaBridge	172:65be27845400	1812	SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
AnnaBridge	172:65be27845400	1813	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
AnnaBridge	172:65be27845400	1814	}
AnnaBridge	172:65be27845400	1815	}
AnnaBridge	172:65be27845400	1816
AnnaBridge	172:65be27845400	1817
AnnaBridge	172:65be27845400	1818	/**
AnnaBridge	172:65be27845400	1819	\brief Get Interrupt Priority (non-secure)
AnnaBridge	172:65be27845400	1820	\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
AnnaBridge	172:65be27845400	1821	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	172:65be27845400	1822	or negative to specify a processor exception.
AnnaBridge	172:65be27845400	1823	\param [in] IRQn Interrupt number.
AnnaBridge	172:65be27845400	1824	\return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge	172:65be27845400	1825	*/
AnnaBridge	172:65be27845400	1826	__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
AnnaBridge	172:65be27845400	1827	{
AnnaBridge	172:65be27845400	1828
AnnaBridge	172:65be27845400	1829	if ((int32_t)(IRQn) >= 0)
AnnaBridge	172:65be27845400	1830	{
AnnaBridge	172:65be27845400	1831	return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	172:65be27845400	1832	}
AnnaBridge	172:65be27845400	1833	else
AnnaBridge	172:65be27845400	1834	{
AnnaBridge	172:65be27845400	1835	return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	172:65be27845400	1836	}
AnnaBridge	172:65be27845400	1837	}
AnnaBridge	172:65be27845400	1838	#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	172:65be27845400	1839
AnnaBridge	172:65be27845400	1840	/@} end of CMSIS_Core_NVICFunctions /
AnnaBridge	172:65be27845400	1841
AnnaBridge	172:65be27845400	1842	/* ########################## MPU functions #################################### */
AnnaBridge	172:65be27845400	1843
AnnaBridge	172:65be27845400	1844	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	172:65be27845400	1845
AnnaBridge	172:65be27845400	1846	#include "mpu_armv8.h"
AnnaBridge	172:65be27845400	1847
AnnaBridge	172:65be27845400	1848	#endif
AnnaBridge	172:65be27845400	1849
AnnaBridge	172:65be27845400	1850	/* ########################## FPU functions #################################### */
AnnaBridge	172:65be27845400	1851	/**
AnnaBridge	172:65be27845400	1852	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	172:65be27845400	1853	\defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge	172:65be27845400	1854	\brief Function that provides FPU type.
AnnaBridge	172:65be27845400	1855	@{
AnnaBridge	172:65be27845400	1856	*/
AnnaBridge	172:65be27845400	1857
AnnaBridge	172:65be27845400	1858	/**
AnnaBridge	172:65be27845400	1859	\brief get FPU type
AnnaBridge	172:65be27845400	1860	\details returns the FPU type
AnnaBridge	172:65be27845400	1861	\returns
AnnaBridge	172:65be27845400	1862	- \b 0: No FPU
AnnaBridge	172:65be27845400	1863	- \b 1: Single precision FPU
AnnaBridge	172:65be27845400	1864	- \b 2: Double + Single precision FPU
AnnaBridge	172:65be27845400	1865	*/
AnnaBridge	172:65be27845400	1866	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge	172:65be27845400	1867	{
AnnaBridge	172:65be27845400	1868	return 0U; /* No FPU */
AnnaBridge	172:65be27845400	1869	}
AnnaBridge	172:65be27845400	1870
AnnaBridge	172:65be27845400	1871
AnnaBridge	172:65be27845400	1872	/@} end of CMSIS_Core_FpuFunctions /
AnnaBridge	172:65be27845400	1873
AnnaBridge	172:65be27845400	1874
AnnaBridge	172:65be27845400	1875
AnnaBridge	172:65be27845400	1876	/* ########################## SAU functions #################################### */
AnnaBridge	172:65be27845400	1877	/**
AnnaBridge	172:65be27845400	1878	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	172:65be27845400	1879	\defgroup CMSIS_Core_SAUFunctions SAU Functions
AnnaBridge	172:65be27845400	1880	\brief Functions that configure the SAU.
AnnaBridge	172:65be27845400	1881	@{
AnnaBridge	172:65be27845400	1882	*/
AnnaBridge	172:65be27845400	1883
AnnaBridge	172:65be27845400	1884	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	172:65be27845400	1885
AnnaBridge	172:65be27845400	1886	/**
AnnaBridge	172:65be27845400	1887	\brief Enable SAU
AnnaBridge	172:65be27845400	1888	\details Enables the Security Attribution Unit (SAU).
AnnaBridge	172:65be27845400	1889	*/
AnnaBridge	172:65be27845400	1890	__STATIC_INLINE void TZ_SAU_Enable(void)
AnnaBridge	172:65be27845400	1891	{
AnnaBridge	172:65be27845400	1892	SAU->CTRL \|= (SAU_CTRL_ENABLE_Msk);
AnnaBridge	172:65be27845400	1893	}
AnnaBridge	172:65be27845400	1894
AnnaBridge	172:65be27845400	1895
AnnaBridge	172:65be27845400	1896
AnnaBridge	172:65be27845400	1897	/**
AnnaBridge	172:65be27845400	1898	\brief Disable SAU
AnnaBridge	172:65be27845400	1899	\details Disables the Security Attribution Unit (SAU).
AnnaBridge	172:65be27845400	1900	*/
AnnaBridge	172:65be27845400	1901	__STATIC_INLINE void TZ_SAU_Disable(void)
AnnaBridge	172:65be27845400	1902	{
AnnaBridge	172:65be27845400	1903	SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
AnnaBridge	172:65be27845400	1904	}
AnnaBridge	172:65be27845400	1905
AnnaBridge	172:65be27845400	1906	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	172:65be27845400	1907
AnnaBridge	172:65be27845400	1908	/@} end of CMSIS_Core_SAUFunctions /
AnnaBridge	172:65be27845400	1909
AnnaBridge	172:65be27845400	1910
AnnaBridge	172:65be27845400	1911
AnnaBridge	172:65be27845400	1912
AnnaBridge	172:65be27845400	1913	/* ################################## SysTick function ############################################ */
AnnaBridge	172:65be27845400	1914	/**
AnnaBridge	172:65be27845400	1915	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	172:65be27845400	1916	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge	172:65be27845400	1917	\brief Functions that configure the System.
AnnaBridge	172:65be27845400	1918	@{
AnnaBridge	172:65be27845400	1919	*/
AnnaBridge	172:65be27845400	1920
AnnaBridge	172:65be27845400	1921	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
AnnaBridge	172:65be27845400	1922
AnnaBridge	172:65be27845400	1923	/**
AnnaBridge	172:65be27845400	1924	\brief System Tick Configuration
AnnaBridge	172:65be27845400	1925	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge	172:65be27845400	1926	Counter is in free running mode to generate periodic interrupts.
AnnaBridge	172:65be27845400	1927	\param [in] ticks Number of ticks between two interrupts.
AnnaBridge	172:65be27845400	1928	\return 0 Function succeeded.
AnnaBridge	172:65be27845400	1929	\return 1 Function failed.
AnnaBridge	172:65be27845400	1930	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge	172:65be27845400	1931	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge	172:65be27845400	1932	must contain a vendor-specific implementation of this function.
AnnaBridge	172:65be27845400	1933	*/
AnnaBridge	172:65be27845400	1934	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
AnnaBridge	172:65be27845400	1935	{
AnnaBridge	172:65be27845400	1936	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge	172:65be27845400	1937	{
AnnaBridge	172:65be27845400	1938	return (1UL); /* Reload value impossible */
AnnaBridge	172:65be27845400	1939	}
AnnaBridge	172:65be27845400	1940
AnnaBridge	172:65be27845400	1941	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge	172:65be27845400	1942	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge	172:65be27845400	1943	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge	172:65be27845400	1944	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
AnnaBridge	172:65be27845400	1945	SysTick_CTRL_TICKINT_Msk \|
AnnaBridge	172:65be27845400	1946	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge	172:65be27845400	1947	return (0UL); /* Function successful */
AnnaBridge	172:65be27845400	1948	}
AnnaBridge	172:65be27845400	1949
AnnaBridge	172:65be27845400	1950	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
AnnaBridge	172:65be27845400	1951	/**
AnnaBridge	172:65be27845400	1952	\brief System Tick Configuration (non-secure)
AnnaBridge	172:65be27845400	1953	\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
AnnaBridge	172:65be27845400	1954	Counter is in free running mode to generate periodic interrupts.
AnnaBridge	172:65be27845400	1955	\param [in] ticks Number of ticks between two interrupts.
AnnaBridge	172:65be27845400	1956	\return 0 Function succeeded.
AnnaBridge	172:65be27845400	1957	\return 1 Function failed.
AnnaBridge	172:65be27845400	1958	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge	172:65be27845400	1959	function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge	172:65be27845400	1960	must contain a vendor-specific implementation of this function.
AnnaBridge	172:65be27845400	1961
AnnaBridge	172:65be27845400	1962	*/
AnnaBridge	172:65be27845400	1963	__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
AnnaBridge	172:65be27845400	1964	{
AnnaBridge	172:65be27845400	1965	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge	172:65be27845400	1966	{
AnnaBridge	172:65be27845400	1967	return (1UL); /* Reload value impossible */
AnnaBridge	172:65be27845400	1968	}
AnnaBridge	172:65be27845400	1969
AnnaBridge	172:65be27845400	1970	SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
AnnaBridge	172:65be27845400	1971	TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
AnnaBridge	172:65be27845400	1972	SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
AnnaBridge	172:65be27845400	1973	SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
AnnaBridge	172:65be27845400	1974	SysTick_CTRL_TICKINT_Msk \|
AnnaBridge	172:65be27845400	1975	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
AnnaBridge	172:65be27845400	1976	return (0UL); /* Function successful */
AnnaBridge	172:65be27845400	1977	}
AnnaBridge	172:65be27845400	1978	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
AnnaBridge	172:65be27845400	1979
AnnaBridge	172:65be27845400	1980	#endif
AnnaBridge	172:65be27845400	1981
AnnaBridge	172:65be27845400	1982	/@} end of CMSIS_Core_SysTickFunctions /
AnnaBridge	172:65be27845400	1983
AnnaBridge	172:65be27845400	1984
AnnaBridge	172:65be27845400	1985
AnnaBridge	172:65be27845400	1986
AnnaBridge	172:65be27845400	1987	#ifdef __cplusplus
AnnaBridge	172:65be27845400	1988	}
AnnaBridge	172:65be27845400	1989	#endif
AnnaBridge	172:65be27845400	1990
AnnaBridge	172:65be27845400	1991	#endif /* __CORE_CM23_H_DEPENDANT */
AnnaBridge	172:65be27845400	1992
AnnaBridge	172:65be27845400	1993	#endif /* __CMSIS_GENERIC */