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TARGET_NUCLEO_F756ZG/TOOLCHAIN_ARM_MICRO/stm32f7xx_ll_tim.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
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AnnaBridge | 171:3a7713b1edbc | 1 | /** |
AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32f7xx_ll_tim.h |
AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of TIM LL module. |
AnnaBridge | 171:3a7713b1edbc | 6 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 7 | * @attention |
AnnaBridge | 171:3a7713b1edbc | 8 | * |
AnnaBridge | 171:3a7713b1edbc | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
AnnaBridge | 171:3a7713b1edbc | 10 | * |
AnnaBridge | 171:3a7713b1edbc | 11 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 171:3a7713b1edbc | 12 | * are permitted provided that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 14 | * this list of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 171:3a7713b1edbc | 17 | * and/or other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 171:3a7713b1edbc | 19 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 171:3a7713b1edbc | 20 | * without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 21 | * |
AnnaBridge | 171:3a7713b1edbc | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 171:3a7713b1edbc | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 171:3a7713b1edbc | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 171:3a7713b1edbc | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 171:3a7713b1edbc | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 171:3a7713b1edbc | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 171:3a7713b1edbc | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 171:3a7713b1edbc | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 171:3a7713b1edbc | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 171:3a7713b1edbc | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 32 | * |
AnnaBridge | 171:3a7713b1edbc | 33 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 34 | */ |
AnnaBridge | 171:3a7713b1edbc | 35 | |
AnnaBridge | 171:3a7713b1edbc | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 37 | #ifndef __STM32F7xx_LL_TIM_H |
AnnaBridge | 171:3a7713b1edbc | 38 | #define __STM32F7xx_LL_TIM_H |
AnnaBridge | 171:3a7713b1edbc | 39 | |
AnnaBridge | 171:3a7713b1edbc | 40 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 41 | extern "C" { |
AnnaBridge | 171:3a7713b1edbc | 42 | #endif |
AnnaBridge | 171:3a7713b1edbc | 43 | |
AnnaBridge | 171:3a7713b1edbc | 44 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 45 | #include "stm32f7xx.h" |
AnnaBridge | 171:3a7713b1edbc | 46 | |
AnnaBridge | 171:3a7713b1edbc | 47 | /** @addtogroup STM32F7xx_LL_Driver |
AnnaBridge | 171:3a7713b1edbc | 48 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 49 | */ |
AnnaBridge | 171:3a7713b1edbc | 50 | |
AnnaBridge | 171:3a7713b1edbc | 51 | #if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM6) || defined (TIM7) |
AnnaBridge | 171:3a7713b1edbc | 52 | |
AnnaBridge | 171:3a7713b1edbc | 53 | /** @defgroup TIM_LL TIM |
AnnaBridge | 171:3a7713b1edbc | 54 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 55 | */ |
AnnaBridge | 171:3a7713b1edbc | 56 | |
AnnaBridge | 171:3a7713b1edbc | 57 | /* Private types -------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 58 | /* Private variables ---------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 59 | /** @defgroup TIM_LL_Private_Variables TIM Private Variables |
AnnaBridge | 171:3a7713b1edbc | 60 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 61 | */ |
AnnaBridge | 171:3a7713b1edbc | 62 | static const uint8_t OFFSET_TAB_CCMRx[] = |
AnnaBridge | 171:3a7713b1edbc | 63 | { |
AnnaBridge | 171:3a7713b1edbc | 64 | 0x00U, /* 0: TIMx_CH1 */ |
AnnaBridge | 171:3a7713b1edbc | 65 | 0x00U, /* 1: TIMx_CH1N */ |
AnnaBridge | 171:3a7713b1edbc | 66 | 0x00U, /* 2: TIMx_CH2 */ |
AnnaBridge | 171:3a7713b1edbc | 67 | 0x00U, /* 3: TIMx_CH2N */ |
AnnaBridge | 171:3a7713b1edbc | 68 | 0x04U, /* 4: TIMx_CH3 */ |
AnnaBridge | 171:3a7713b1edbc | 69 | 0x04U, /* 5: TIMx_CH3N */ |
AnnaBridge | 171:3a7713b1edbc | 70 | 0x04U, /* 6: TIMx_CH4 */ |
AnnaBridge | 171:3a7713b1edbc | 71 | 0x3CU, /* 7: TIMx_CH5 */ |
AnnaBridge | 171:3a7713b1edbc | 72 | 0x3CU /* 8: TIMx_CH6 */ |
AnnaBridge | 171:3a7713b1edbc | 73 | }; |
AnnaBridge | 171:3a7713b1edbc | 74 | |
AnnaBridge | 171:3a7713b1edbc | 75 | static const uint8_t SHIFT_TAB_OCxx[] = |
AnnaBridge | 171:3a7713b1edbc | 76 | { |
AnnaBridge | 171:3a7713b1edbc | 77 | 0U, /* 0: OC1M, OC1FE, OC1PE */ |
AnnaBridge | 171:3a7713b1edbc | 78 | 0U, /* 1: - NA */ |
AnnaBridge | 171:3a7713b1edbc | 79 | 8U, /* 2: OC2M, OC2FE, OC2PE */ |
AnnaBridge | 171:3a7713b1edbc | 80 | 0U, /* 3: - NA */ |
AnnaBridge | 171:3a7713b1edbc | 81 | 0U, /* 4: OC3M, OC3FE, OC3PE */ |
AnnaBridge | 171:3a7713b1edbc | 82 | 0U, /* 5: - NA */ |
AnnaBridge | 171:3a7713b1edbc | 83 | 8U, /* 6: OC4M, OC4FE, OC4PE */ |
AnnaBridge | 171:3a7713b1edbc | 84 | 0U, /* 7: OC5M, OC5FE, OC5PE */ |
AnnaBridge | 171:3a7713b1edbc | 85 | 8U /* 8: OC6M, OC6FE, OC6PE */ |
AnnaBridge | 171:3a7713b1edbc | 86 | }; |
AnnaBridge | 171:3a7713b1edbc | 87 | |
AnnaBridge | 171:3a7713b1edbc | 88 | static const uint8_t SHIFT_TAB_ICxx[] = |
AnnaBridge | 171:3a7713b1edbc | 89 | { |
AnnaBridge | 171:3a7713b1edbc | 90 | 0U, /* 0: CC1S, IC1PSC, IC1F */ |
AnnaBridge | 171:3a7713b1edbc | 91 | 0U, /* 1: - NA */ |
AnnaBridge | 171:3a7713b1edbc | 92 | 8U, /* 2: CC2S, IC2PSC, IC2F */ |
AnnaBridge | 171:3a7713b1edbc | 93 | 0U, /* 3: - NA */ |
AnnaBridge | 171:3a7713b1edbc | 94 | 0U, /* 4: CC3S, IC3PSC, IC3F */ |
AnnaBridge | 171:3a7713b1edbc | 95 | 0U, /* 5: - NA */ |
AnnaBridge | 171:3a7713b1edbc | 96 | 8U, /* 6: CC4S, IC4PSC, IC4F */ |
AnnaBridge | 171:3a7713b1edbc | 97 | 0U, /* 7: - NA */ |
AnnaBridge | 171:3a7713b1edbc | 98 | 0U /* 8: - NA */ |
AnnaBridge | 171:3a7713b1edbc | 99 | }; |
AnnaBridge | 171:3a7713b1edbc | 100 | |
AnnaBridge | 171:3a7713b1edbc | 101 | static const uint8_t SHIFT_TAB_CCxP[] = |
AnnaBridge | 171:3a7713b1edbc | 102 | { |
AnnaBridge | 171:3a7713b1edbc | 103 | 0U, /* 0: CC1P */ |
AnnaBridge | 171:3a7713b1edbc | 104 | 2U, /* 1: CC1NP */ |
AnnaBridge | 171:3a7713b1edbc | 105 | 4U, /* 2: CC2P */ |
AnnaBridge | 171:3a7713b1edbc | 106 | 6U, /* 3: CC2NP */ |
AnnaBridge | 171:3a7713b1edbc | 107 | 8U, /* 4: CC3P */ |
AnnaBridge | 171:3a7713b1edbc | 108 | 10U, /* 5: CC3NP */ |
AnnaBridge | 171:3a7713b1edbc | 109 | 12U, /* 6: CC4P */ |
AnnaBridge | 171:3a7713b1edbc | 110 | 16U, /* 7: CC5P */ |
AnnaBridge | 171:3a7713b1edbc | 111 | 20U /* 8: CC6P */ |
AnnaBridge | 171:3a7713b1edbc | 112 | }; |
AnnaBridge | 171:3a7713b1edbc | 113 | |
AnnaBridge | 171:3a7713b1edbc | 114 | static const uint8_t SHIFT_TAB_OISx[] = |
AnnaBridge | 171:3a7713b1edbc | 115 | { |
AnnaBridge | 171:3a7713b1edbc | 116 | 0U, /* 0: OIS1 */ |
AnnaBridge | 171:3a7713b1edbc | 117 | 1U, /* 1: OIS1N */ |
AnnaBridge | 171:3a7713b1edbc | 118 | 2U, /* 2: OIS2 */ |
AnnaBridge | 171:3a7713b1edbc | 119 | 3U, /* 3: OIS2N */ |
AnnaBridge | 171:3a7713b1edbc | 120 | 4U, /* 4: OIS3 */ |
AnnaBridge | 171:3a7713b1edbc | 121 | 5U, /* 5: OIS3N */ |
AnnaBridge | 171:3a7713b1edbc | 122 | 6U, /* 6: OIS4 */ |
AnnaBridge | 171:3a7713b1edbc | 123 | 8U, /* 7: OIS5 */ |
AnnaBridge | 171:3a7713b1edbc | 124 | 10U /* 8: OIS6 */ |
AnnaBridge | 171:3a7713b1edbc | 125 | }; |
AnnaBridge | 171:3a7713b1edbc | 126 | /** |
AnnaBridge | 171:3a7713b1edbc | 127 | * @} |
AnnaBridge | 171:3a7713b1edbc | 128 | */ |
AnnaBridge | 171:3a7713b1edbc | 129 | |
AnnaBridge | 171:3a7713b1edbc | 130 | |
AnnaBridge | 171:3a7713b1edbc | 131 | /* Private constants ---------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 132 | /** @defgroup TIM_LL_Private_Constants TIM Private Constants |
AnnaBridge | 171:3a7713b1edbc | 133 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 134 | */ |
AnnaBridge | 171:3a7713b1edbc | 135 | |
AnnaBridge | 171:3a7713b1edbc | 136 | #if defined(TIM_BREAK_INPUT_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 137 | /* Defines used for the bit position in the register and perform offsets */ |
AnnaBridge | 171:3a7713b1edbc | 138 | #define TIM_POSITION_BRK_SOURCE POSITION_VAL(Source) |
AnnaBridge | 171:3a7713b1edbc | 139 | |
AnnaBridge | 171:3a7713b1edbc | 140 | /* Generic bit definitions for TIMx_AF1 register */ |
AnnaBridge | 171:3a7713b1edbc | 141 | #define TIMx_AF1_BKINE TIM1_AF1_BKINE /*!< BRK BKINE input enable */ |
AnnaBridge | 171:3a7713b1edbc | 142 | #if defined(DFSDM1_Channel0) |
AnnaBridge | 171:3a7713b1edbc | 143 | #define TIMx_AF1_BKDFBKE TIM1_AF1_BKDFBKE /*!< BRK DFSDM1_BREAK[0] enable */ |
AnnaBridge | 171:3a7713b1edbc | 144 | #endif /* DFSDM1_Channel0 */ |
AnnaBridge | 171:3a7713b1edbc | 145 | #define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */ |
AnnaBridge | 171:3a7713b1edbc | 146 | /* Generic bit definitions for TIMx_AF2 register */ |
AnnaBridge | 171:3a7713b1edbc | 147 | #define TIMx_AF2_BK2INE TIM1_AF2_BK2INE /*!< BRK B2KINE input enable */ |
AnnaBridge | 171:3a7713b1edbc | 148 | #if defined(DFSDM1_Channel0) |
AnnaBridge | 171:3a7713b1edbc | 149 | #define TIMx_AF2_BK2DFBKE TIM1_AF2_BK2DFBKE /*!< BRK DFSDM_BREAK[0] enable */ |
AnnaBridge | 171:3a7713b1edbc | 150 | #endif /* DFSDM1_Channel0 */ |
AnnaBridge | 171:3a7713b1edbc | 151 | #define TIMx_AF2_BK2INP TIM1_AF2_BK2INP /*!< BRK BK2IN input polarity */ |
AnnaBridge | 171:3a7713b1edbc | 152 | #endif /* TIM_BREAK_INPUT_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 153 | |
AnnaBridge | 171:3a7713b1edbc | 154 | /* Remap mask definitions */ |
AnnaBridge | 171:3a7713b1edbc | 155 | #define TIMx_OR_RMP_SHIFT 16U |
AnnaBridge | 171:3a7713b1edbc | 156 | #define TIMx_OR_RMP_MASK 0x0000FFFFU |
AnnaBridge | 171:3a7713b1edbc | 157 | #define TIM2_OR_RMP_MASK (TIM2_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT) |
AnnaBridge | 171:3a7713b1edbc | 158 | #define TIM5_OR_RMP_MASK (TIM5_OR_TI4_RMP << TIMx_OR_RMP_SHIFT) |
AnnaBridge | 171:3a7713b1edbc | 159 | #define TIM11_OR_RMP_MASK (TIM11_OR_TI1_RMP << TIMx_OR_RMP_SHIFT) |
AnnaBridge | 171:3a7713b1edbc | 160 | |
AnnaBridge | 171:3a7713b1edbc | 161 | /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ |
AnnaBridge | 171:3a7713b1edbc | 162 | #define DT_DELAY_1 ((uint8_t)0x7FU) |
AnnaBridge | 171:3a7713b1edbc | 163 | #define DT_DELAY_2 ((uint8_t)0x3FU) |
AnnaBridge | 171:3a7713b1edbc | 164 | #define DT_DELAY_3 ((uint8_t)0x1FU) |
AnnaBridge | 171:3a7713b1edbc | 165 | #define DT_DELAY_4 ((uint8_t)0x1FU) |
AnnaBridge | 171:3a7713b1edbc | 166 | |
AnnaBridge | 171:3a7713b1edbc | 167 | /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ |
AnnaBridge | 171:3a7713b1edbc | 168 | #define DT_RANGE_1 ((uint8_t)0x00U) |
AnnaBridge | 171:3a7713b1edbc | 169 | #define DT_RANGE_2 ((uint8_t)0x80U) |
AnnaBridge | 171:3a7713b1edbc | 170 | #define DT_RANGE_3 ((uint8_t)0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 171 | #define DT_RANGE_4 ((uint8_t)0xE0U) |
AnnaBridge | 171:3a7713b1edbc | 172 | |
AnnaBridge | 171:3a7713b1edbc | 173 | |
AnnaBridge | 171:3a7713b1edbc | 174 | /** |
AnnaBridge | 171:3a7713b1edbc | 175 | * @} |
AnnaBridge | 171:3a7713b1edbc | 176 | */ |
AnnaBridge | 171:3a7713b1edbc | 177 | |
AnnaBridge | 171:3a7713b1edbc | 178 | /* Private macros ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 179 | /** @defgroup TIM_LL_Private_Macros TIM Private Macros |
AnnaBridge | 171:3a7713b1edbc | 180 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 181 | */ |
AnnaBridge | 171:3a7713b1edbc | 182 | /** @brief Convert channel id into channel index. |
AnnaBridge | 171:3a7713b1edbc | 183 | * @param __CHANNEL__ This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 184 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 171:3a7713b1edbc | 185 | * @arg @ref LL_TIM_CHANNEL_CH1N |
AnnaBridge | 171:3a7713b1edbc | 186 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 171:3a7713b1edbc | 187 | * @arg @ref LL_TIM_CHANNEL_CH2N |
AnnaBridge | 171:3a7713b1edbc | 188 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 171:3a7713b1edbc | 189 | * @arg @ref LL_TIM_CHANNEL_CH3N |
AnnaBridge | 171:3a7713b1edbc | 190 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 171:3a7713b1edbc | 191 | * @arg @ref LL_TIM_CHANNEL_CH5 |
AnnaBridge | 171:3a7713b1edbc | 192 | * @arg @ref LL_TIM_CHANNEL_CH6 |
AnnaBridge | 171:3a7713b1edbc | 193 | * @retval none |
AnnaBridge | 171:3a7713b1edbc | 194 | */ |
AnnaBridge | 171:3a7713b1edbc | 195 | #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ |
AnnaBridge | 171:3a7713b1edbc | 196 | (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ |
AnnaBridge | 171:3a7713b1edbc | 197 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ |
AnnaBridge | 171:3a7713b1edbc | 198 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ |
AnnaBridge | 171:3a7713b1edbc | 199 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ |
AnnaBridge | 171:3a7713b1edbc | 200 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ |
AnnaBridge | 171:3a7713b1edbc | 201 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\ |
AnnaBridge | 171:3a7713b1edbc | 202 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\ |
AnnaBridge | 171:3a7713b1edbc | 203 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U) |
AnnaBridge | 171:3a7713b1edbc | 204 | |
AnnaBridge | 171:3a7713b1edbc | 205 | /** @brief Calculate the deadtime sampling period(in ps). |
AnnaBridge | 171:3a7713b1edbc | 206 | * @param __TIMCLK__ timer input clock frequency (in Hz). |
AnnaBridge | 171:3a7713b1edbc | 207 | * @param __CKD__ This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 208 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 |
AnnaBridge | 171:3a7713b1edbc | 209 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 |
AnnaBridge | 171:3a7713b1edbc | 210 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 |
AnnaBridge | 171:3a7713b1edbc | 211 | * @retval none |
AnnaBridge | 171:3a7713b1edbc | 212 | */ |
AnnaBridge | 171:3a7713b1edbc | 213 | #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ |
AnnaBridge | 171:3a7713b1edbc | 214 | (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ |
AnnaBridge | 171:3a7713b1edbc | 215 | ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ |
AnnaBridge | 171:3a7713b1edbc | 216 | ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) |
AnnaBridge | 171:3a7713b1edbc | 217 | /** |
AnnaBridge | 171:3a7713b1edbc | 218 | * @} |
AnnaBridge | 171:3a7713b1edbc | 219 | */ |
AnnaBridge | 171:3a7713b1edbc | 220 | |
AnnaBridge | 171:3a7713b1edbc | 221 | |
AnnaBridge | 171:3a7713b1edbc | 222 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 223 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 171:3a7713b1edbc | 224 | /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure |
AnnaBridge | 171:3a7713b1edbc | 225 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 226 | */ |
AnnaBridge | 171:3a7713b1edbc | 227 | |
AnnaBridge | 171:3a7713b1edbc | 228 | /** |
AnnaBridge | 171:3a7713b1edbc | 229 | * @brief TIM Time Base configuration structure definition. |
AnnaBridge | 171:3a7713b1edbc | 230 | */ |
AnnaBridge | 171:3a7713b1edbc | 231 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 232 | { |
AnnaBridge | 171:3a7713b1edbc | 233 | uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. |
AnnaBridge | 171:3a7713b1edbc | 234 | This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. |
AnnaBridge | 171:3a7713b1edbc | 235 | |
AnnaBridge | 171:3a7713b1edbc | 236 | This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/ |
AnnaBridge | 171:3a7713b1edbc | 237 | |
AnnaBridge | 171:3a7713b1edbc | 238 | uint32_t CounterMode; /*!< Specifies the counter mode. |
AnnaBridge | 171:3a7713b1edbc | 239 | This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. |
AnnaBridge | 171:3a7713b1edbc | 240 | |
AnnaBridge | 171:3a7713b1edbc | 241 | This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/ |
AnnaBridge | 171:3a7713b1edbc | 242 | |
AnnaBridge | 171:3a7713b1edbc | 243 | uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active |
AnnaBridge | 171:3a7713b1edbc | 244 | Auto-Reload Register at the next update event. |
AnnaBridge | 171:3a7713b1edbc | 245 | This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. |
AnnaBridge | 171:3a7713b1edbc | 246 | Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF. |
AnnaBridge | 171:3a7713b1edbc | 247 | |
AnnaBridge | 171:3a7713b1edbc | 248 | This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/ |
AnnaBridge | 171:3a7713b1edbc | 249 | |
AnnaBridge | 171:3a7713b1edbc | 250 | uint32_t ClockDivision; /*!< Specifies the clock division. |
AnnaBridge | 171:3a7713b1edbc | 251 | This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. |
AnnaBridge | 171:3a7713b1edbc | 252 | |
AnnaBridge | 171:3a7713b1edbc | 253 | This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/ |
AnnaBridge | 171:3a7713b1edbc | 254 | |
AnnaBridge | 171:3a7713b1edbc | 255 | uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter |
AnnaBridge | 171:3a7713b1edbc | 256 | reaches zero, an update event is generated and counting restarts |
AnnaBridge | 171:3a7713b1edbc | 257 | from the RCR value (N). |
AnnaBridge | 171:3a7713b1edbc | 258 | This means in PWM mode that (N+1) corresponds to: |
AnnaBridge | 171:3a7713b1edbc | 259 | - the number of PWM periods in edge-aligned mode |
AnnaBridge | 171:3a7713b1edbc | 260 | - the number of half PWM period in center-aligned mode |
AnnaBridge | 171:3a7713b1edbc | 261 | This parameter must be a number between 0x00 and 0xFF. |
AnnaBridge | 171:3a7713b1edbc | 262 | |
AnnaBridge | 171:3a7713b1edbc | 263 | This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/ |
AnnaBridge | 171:3a7713b1edbc | 264 | } LL_TIM_InitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 265 | |
AnnaBridge | 171:3a7713b1edbc | 266 | /** |
AnnaBridge | 171:3a7713b1edbc | 267 | * @brief TIM Output Compare configuration structure definition. |
AnnaBridge | 171:3a7713b1edbc | 268 | */ |
AnnaBridge | 171:3a7713b1edbc | 269 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 270 | { |
AnnaBridge | 171:3a7713b1edbc | 271 | uint32_t OCMode; /*!< Specifies the output mode. |
AnnaBridge | 171:3a7713b1edbc | 272 | This parameter can be a value of @ref TIM_LL_EC_OCMODE. |
AnnaBridge | 171:3a7713b1edbc | 273 | |
AnnaBridge | 171:3a7713b1edbc | 274 | This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/ |
AnnaBridge | 171:3a7713b1edbc | 275 | |
AnnaBridge | 171:3a7713b1edbc | 276 | uint32_t OCState; /*!< Specifies the TIM Output Compare state. |
AnnaBridge | 171:3a7713b1edbc | 277 | This parameter can be a value of @ref TIM_LL_EC_OCSTATE. |
AnnaBridge | 171:3a7713b1edbc | 278 | |
AnnaBridge | 171:3a7713b1edbc | 279 | This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ |
AnnaBridge | 171:3a7713b1edbc | 280 | |
AnnaBridge | 171:3a7713b1edbc | 281 | uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. |
AnnaBridge | 171:3a7713b1edbc | 282 | This parameter can be a value of @ref TIM_LL_EC_OCSTATE. |
AnnaBridge | 171:3a7713b1edbc | 283 | |
AnnaBridge | 171:3a7713b1edbc | 284 | This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ |
AnnaBridge | 171:3a7713b1edbc | 285 | |
AnnaBridge | 171:3a7713b1edbc | 286 | uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. |
AnnaBridge | 171:3a7713b1edbc | 287 | This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. |
AnnaBridge | 171:3a7713b1edbc | 288 | |
AnnaBridge | 171:3a7713b1edbc | 289 | This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/ |
AnnaBridge | 171:3a7713b1edbc | 290 | |
AnnaBridge | 171:3a7713b1edbc | 291 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
AnnaBridge | 171:3a7713b1edbc | 292 | This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. |
AnnaBridge | 171:3a7713b1edbc | 293 | |
AnnaBridge | 171:3a7713b1edbc | 294 | This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ |
AnnaBridge | 171:3a7713b1edbc | 295 | |
AnnaBridge | 171:3a7713b1edbc | 296 | uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. |
AnnaBridge | 171:3a7713b1edbc | 297 | This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. |
AnnaBridge | 171:3a7713b1edbc | 298 | |
AnnaBridge | 171:3a7713b1edbc | 299 | This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ |
AnnaBridge | 171:3a7713b1edbc | 300 | |
AnnaBridge | 171:3a7713b1edbc | 301 | |
AnnaBridge | 171:3a7713b1edbc | 302 | uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
AnnaBridge | 171:3a7713b1edbc | 303 | This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. |
AnnaBridge | 171:3a7713b1edbc | 304 | |
AnnaBridge | 171:3a7713b1edbc | 305 | This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ |
AnnaBridge | 171:3a7713b1edbc | 306 | |
AnnaBridge | 171:3a7713b1edbc | 307 | uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
AnnaBridge | 171:3a7713b1edbc | 308 | This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. |
AnnaBridge | 171:3a7713b1edbc | 309 | |
AnnaBridge | 171:3a7713b1edbc | 310 | This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ |
AnnaBridge | 171:3a7713b1edbc | 311 | } LL_TIM_OC_InitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 312 | |
AnnaBridge | 171:3a7713b1edbc | 313 | /** |
AnnaBridge | 171:3a7713b1edbc | 314 | * @brief TIM Input Capture configuration structure definition. |
AnnaBridge | 171:3a7713b1edbc | 315 | */ |
AnnaBridge | 171:3a7713b1edbc | 316 | |
AnnaBridge | 171:3a7713b1edbc | 317 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 318 | { |
AnnaBridge | 171:3a7713b1edbc | 319 | |
AnnaBridge | 171:3a7713b1edbc | 320 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
AnnaBridge | 171:3a7713b1edbc | 321 | This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. |
AnnaBridge | 171:3a7713b1edbc | 322 | |
AnnaBridge | 171:3a7713b1edbc | 323 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ |
AnnaBridge | 171:3a7713b1edbc | 324 | |
AnnaBridge | 171:3a7713b1edbc | 325 | uint32_t ICActiveInput; /*!< Specifies the input. |
AnnaBridge | 171:3a7713b1edbc | 326 | This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. |
AnnaBridge | 171:3a7713b1edbc | 327 | |
AnnaBridge | 171:3a7713b1edbc | 328 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ |
AnnaBridge | 171:3a7713b1edbc | 329 | |
AnnaBridge | 171:3a7713b1edbc | 330 | uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. |
AnnaBridge | 171:3a7713b1edbc | 331 | This parameter can be a value of @ref TIM_LL_EC_ICPSC. |
AnnaBridge | 171:3a7713b1edbc | 332 | |
AnnaBridge | 171:3a7713b1edbc | 333 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ |
AnnaBridge | 171:3a7713b1edbc | 334 | |
AnnaBridge | 171:3a7713b1edbc | 335 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
AnnaBridge | 171:3a7713b1edbc | 336 | This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. |
AnnaBridge | 171:3a7713b1edbc | 337 | |
AnnaBridge | 171:3a7713b1edbc | 338 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ |
AnnaBridge | 171:3a7713b1edbc | 339 | } LL_TIM_IC_InitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 340 | |
AnnaBridge | 171:3a7713b1edbc | 341 | |
AnnaBridge | 171:3a7713b1edbc | 342 | /** |
AnnaBridge | 171:3a7713b1edbc | 343 | * @brief TIM Encoder interface configuration structure definition. |
AnnaBridge | 171:3a7713b1edbc | 344 | */ |
AnnaBridge | 171:3a7713b1edbc | 345 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 346 | { |
AnnaBridge | 171:3a7713b1edbc | 347 | uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). |
AnnaBridge | 171:3a7713b1edbc | 348 | This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. |
AnnaBridge | 171:3a7713b1edbc | 349 | |
AnnaBridge | 171:3a7713b1edbc | 350 | This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/ |
AnnaBridge | 171:3a7713b1edbc | 351 | |
AnnaBridge | 171:3a7713b1edbc | 352 | uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. |
AnnaBridge | 171:3a7713b1edbc | 353 | This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. |
AnnaBridge | 171:3a7713b1edbc | 354 | |
AnnaBridge | 171:3a7713b1edbc | 355 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ |
AnnaBridge | 171:3a7713b1edbc | 356 | |
AnnaBridge | 171:3a7713b1edbc | 357 | uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source |
AnnaBridge | 171:3a7713b1edbc | 358 | This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. |
AnnaBridge | 171:3a7713b1edbc | 359 | |
AnnaBridge | 171:3a7713b1edbc | 360 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ |
AnnaBridge | 171:3a7713b1edbc | 361 | |
AnnaBridge | 171:3a7713b1edbc | 362 | uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. |
AnnaBridge | 171:3a7713b1edbc | 363 | This parameter can be a value of @ref TIM_LL_EC_ICPSC. |
AnnaBridge | 171:3a7713b1edbc | 364 | |
AnnaBridge | 171:3a7713b1edbc | 365 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ |
AnnaBridge | 171:3a7713b1edbc | 366 | |
AnnaBridge | 171:3a7713b1edbc | 367 | uint32_t IC1Filter; /*!< Specifies the TI1 input filter. |
AnnaBridge | 171:3a7713b1edbc | 368 | This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. |
AnnaBridge | 171:3a7713b1edbc | 369 | |
AnnaBridge | 171:3a7713b1edbc | 370 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ |
AnnaBridge | 171:3a7713b1edbc | 371 | |
AnnaBridge | 171:3a7713b1edbc | 372 | uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. |
AnnaBridge | 171:3a7713b1edbc | 373 | This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. |
AnnaBridge | 171:3a7713b1edbc | 374 | |
AnnaBridge | 171:3a7713b1edbc | 375 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ |
AnnaBridge | 171:3a7713b1edbc | 376 | |
AnnaBridge | 171:3a7713b1edbc | 377 | uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source |
AnnaBridge | 171:3a7713b1edbc | 378 | This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. |
AnnaBridge | 171:3a7713b1edbc | 379 | |
AnnaBridge | 171:3a7713b1edbc | 380 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ |
AnnaBridge | 171:3a7713b1edbc | 381 | |
AnnaBridge | 171:3a7713b1edbc | 382 | uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. |
AnnaBridge | 171:3a7713b1edbc | 383 | This parameter can be a value of @ref TIM_LL_EC_ICPSC. |
AnnaBridge | 171:3a7713b1edbc | 384 | |
AnnaBridge | 171:3a7713b1edbc | 385 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ |
AnnaBridge | 171:3a7713b1edbc | 386 | |
AnnaBridge | 171:3a7713b1edbc | 387 | uint32_t IC2Filter; /*!< Specifies the TI2 input filter. |
AnnaBridge | 171:3a7713b1edbc | 388 | This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. |
AnnaBridge | 171:3a7713b1edbc | 389 | |
AnnaBridge | 171:3a7713b1edbc | 390 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ |
AnnaBridge | 171:3a7713b1edbc | 391 | |
AnnaBridge | 171:3a7713b1edbc | 392 | } LL_TIM_ENCODER_InitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 393 | |
AnnaBridge | 171:3a7713b1edbc | 394 | /** |
AnnaBridge | 171:3a7713b1edbc | 395 | * @brief TIM Hall sensor interface configuration structure definition. |
AnnaBridge | 171:3a7713b1edbc | 396 | */ |
AnnaBridge | 171:3a7713b1edbc | 397 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 398 | { |
AnnaBridge | 171:3a7713b1edbc | 399 | |
AnnaBridge | 171:3a7713b1edbc | 400 | uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. |
AnnaBridge | 171:3a7713b1edbc | 401 | This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. |
AnnaBridge | 171:3a7713b1edbc | 402 | |
AnnaBridge | 171:3a7713b1edbc | 403 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ |
AnnaBridge | 171:3a7713b1edbc | 404 | |
AnnaBridge | 171:3a7713b1edbc | 405 | uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. |
AnnaBridge | 171:3a7713b1edbc | 406 | Prescaler must be set to get a maximum counter period longer than the |
AnnaBridge | 171:3a7713b1edbc | 407 | time interval between 2 consecutive changes on the Hall inputs. |
AnnaBridge | 171:3a7713b1edbc | 408 | This parameter can be a value of @ref TIM_LL_EC_ICPSC. |
AnnaBridge | 171:3a7713b1edbc | 409 | |
AnnaBridge | 171:3a7713b1edbc | 410 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ |
AnnaBridge | 171:3a7713b1edbc | 411 | |
AnnaBridge | 171:3a7713b1edbc | 412 | uint32_t IC1Filter; /*!< Specifies the TI1 input filter. |
AnnaBridge | 171:3a7713b1edbc | 413 | This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. |
AnnaBridge | 171:3a7713b1edbc | 414 | |
AnnaBridge | 171:3a7713b1edbc | 415 | This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ |
AnnaBridge | 171:3a7713b1edbc | 416 | |
AnnaBridge | 171:3a7713b1edbc | 417 | uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register. |
AnnaBridge | 171:3a7713b1edbc | 418 | A positive pulse (TRGO event) is generated with a programmable delay every time |
AnnaBridge | 171:3a7713b1edbc | 419 | a change occurs on the Hall inputs. |
AnnaBridge | 171:3a7713b1edbc | 420 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. |
AnnaBridge | 171:3a7713b1edbc | 421 | |
AnnaBridge | 171:3a7713b1edbc | 422 | This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/ |
AnnaBridge | 171:3a7713b1edbc | 423 | } LL_TIM_HALLSENSOR_InitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 424 | |
AnnaBridge | 171:3a7713b1edbc | 425 | /** |
AnnaBridge | 171:3a7713b1edbc | 426 | * @brief BDTR (Break and Dead Time) structure definition |
AnnaBridge | 171:3a7713b1edbc | 427 | */ |
AnnaBridge | 171:3a7713b1edbc | 428 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 429 | { |
AnnaBridge | 171:3a7713b1edbc | 430 | uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. |
AnnaBridge | 171:3a7713b1edbc | 431 | This parameter can be a value of @ref TIM_LL_EC_OSSR |
AnnaBridge | 171:3a7713b1edbc | 432 | |
AnnaBridge | 171:3a7713b1edbc | 433 | This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() |
AnnaBridge | 171:3a7713b1edbc | 434 | |
AnnaBridge | 171:3a7713b1edbc | 435 | @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ |
AnnaBridge | 171:3a7713b1edbc | 436 | |
AnnaBridge | 171:3a7713b1edbc | 437 | uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. |
AnnaBridge | 171:3a7713b1edbc | 438 | This parameter can be a value of @ref TIM_LL_EC_OSSI |
AnnaBridge | 171:3a7713b1edbc | 439 | |
AnnaBridge | 171:3a7713b1edbc | 440 | This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() |
AnnaBridge | 171:3a7713b1edbc | 441 | |
AnnaBridge | 171:3a7713b1edbc | 442 | @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ |
AnnaBridge | 171:3a7713b1edbc | 443 | |
AnnaBridge | 171:3a7713b1edbc | 444 | uint32_t LockLevel; /*!< Specifies the LOCK level parameters. |
AnnaBridge | 171:3a7713b1edbc | 445 | This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL |
AnnaBridge | 171:3a7713b1edbc | 446 | |
AnnaBridge | 171:3a7713b1edbc | 447 | @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register |
AnnaBridge | 171:3a7713b1edbc | 448 | has been written, their content is frozen until the next reset.*/ |
AnnaBridge | 171:3a7713b1edbc | 449 | |
AnnaBridge | 171:3a7713b1edbc | 450 | uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the |
AnnaBridge | 171:3a7713b1edbc | 451 | switching-on of the outputs. |
AnnaBridge | 171:3a7713b1edbc | 452 | This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. |
AnnaBridge | 171:3a7713b1edbc | 453 | |
AnnaBridge | 171:3a7713b1edbc | 454 | This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime() |
AnnaBridge | 171:3a7713b1edbc | 455 | |
AnnaBridge | 171:3a7713b1edbc | 456 | @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */ |
AnnaBridge | 171:3a7713b1edbc | 457 | |
AnnaBridge | 171:3a7713b1edbc | 458 | uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. |
AnnaBridge | 171:3a7713b1edbc | 459 | This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE |
AnnaBridge | 171:3a7713b1edbc | 460 | |
AnnaBridge | 171:3a7713b1edbc | 461 | This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() |
AnnaBridge | 171:3a7713b1edbc | 462 | |
AnnaBridge | 171:3a7713b1edbc | 463 | @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ |
AnnaBridge | 171:3a7713b1edbc | 464 | |
AnnaBridge | 171:3a7713b1edbc | 465 | uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. |
AnnaBridge | 171:3a7713b1edbc | 466 | This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY |
AnnaBridge | 171:3a7713b1edbc | 467 | |
AnnaBridge | 171:3a7713b1edbc | 468 | This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK() |
AnnaBridge | 171:3a7713b1edbc | 469 | |
AnnaBridge | 171:3a7713b1edbc | 470 | @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ |
AnnaBridge | 171:3a7713b1edbc | 471 | |
AnnaBridge | 171:3a7713b1edbc | 472 | uint32_t BreakFilter; /*!< Specifies the TIM Break Filter. |
AnnaBridge | 171:3a7713b1edbc | 473 | This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER |
AnnaBridge | 171:3a7713b1edbc | 474 | |
AnnaBridge | 171:3a7713b1edbc | 475 | This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK() |
AnnaBridge | 171:3a7713b1edbc | 476 | |
AnnaBridge | 171:3a7713b1edbc | 477 | @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ |
AnnaBridge | 171:3a7713b1edbc | 478 | |
AnnaBridge | 171:3a7713b1edbc | 479 | uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. |
AnnaBridge | 171:3a7713b1edbc | 480 | This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE |
AnnaBridge | 171:3a7713b1edbc | 481 | |
AnnaBridge | 171:3a7713b1edbc | 482 | This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2() |
AnnaBridge | 171:3a7713b1edbc | 483 | |
AnnaBridge | 171:3a7713b1edbc | 484 | @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ |
AnnaBridge | 171:3a7713b1edbc | 485 | |
AnnaBridge | 171:3a7713b1edbc | 486 | uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity. |
AnnaBridge | 171:3a7713b1edbc | 487 | This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY |
AnnaBridge | 171:3a7713b1edbc | 488 | |
AnnaBridge | 171:3a7713b1edbc | 489 | This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2() |
AnnaBridge | 171:3a7713b1edbc | 490 | |
AnnaBridge | 171:3a7713b1edbc | 491 | @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ |
AnnaBridge | 171:3a7713b1edbc | 492 | |
AnnaBridge | 171:3a7713b1edbc | 493 | uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter. |
AnnaBridge | 171:3a7713b1edbc | 494 | This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER |
AnnaBridge | 171:3a7713b1edbc | 495 | |
AnnaBridge | 171:3a7713b1edbc | 496 | This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2() |
AnnaBridge | 171:3a7713b1edbc | 497 | |
AnnaBridge | 171:3a7713b1edbc | 498 | @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ |
AnnaBridge | 171:3a7713b1edbc | 499 | |
AnnaBridge | 171:3a7713b1edbc | 500 | uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. |
AnnaBridge | 171:3a7713b1edbc | 501 | This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE |
AnnaBridge | 171:3a7713b1edbc | 502 | |
AnnaBridge | 171:3a7713b1edbc | 503 | This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() |
AnnaBridge | 171:3a7713b1edbc | 504 | |
AnnaBridge | 171:3a7713b1edbc | 505 | @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ |
AnnaBridge | 171:3a7713b1edbc | 506 | } LL_TIM_BDTR_InitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 507 | |
AnnaBridge | 171:3a7713b1edbc | 508 | /** |
AnnaBridge | 171:3a7713b1edbc | 509 | * @} |
AnnaBridge | 171:3a7713b1edbc | 510 | */ |
AnnaBridge | 171:3a7713b1edbc | 511 | #endif /* USE_FULL_LL_DRIVER */ |
AnnaBridge | 171:3a7713b1edbc | 512 | |
AnnaBridge | 171:3a7713b1edbc | 513 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 514 | /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants |
AnnaBridge | 171:3a7713b1edbc | 515 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 516 | */ |
AnnaBridge | 171:3a7713b1edbc | 517 | |
AnnaBridge | 171:3a7713b1edbc | 518 | /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines |
AnnaBridge | 171:3a7713b1edbc | 519 | * @brief Flags defines which can be used with LL_TIM_ReadReg function. |
AnnaBridge | 171:3a7713b1edbc | 520 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 521 | */ |
AnnaBridge | 171:3a7713b1edbc | 522 | #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ |
AnnaBridge | 171:3a7713b1edbc | 523 | #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */ |
AnnaBridge | 171:3a7713b1edbc | 524 | #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */ |
AnnaBridge | 171:3a7713b1edbc | 525 | #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */ |
AnnaBridge | 171:3a7713b1edbc | 526 | #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */ |
AnnaBridge | 171:3a7713b1edbc | 527 | #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */ |
AnnaBridge | 171:3a7713b1edbc | 528 | #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */ |
AnnaBridge | 171:3a7713b1edbc | 529 | #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ |
AnnaBridge | 171:3a7713b1edbc | 530 | #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ |
AnnaBridge | 171:3a7713b1edbc | 531 | #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ |
AnnaBridge | 171:3a7713b1edbc | 532 | #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */ |
AnnaBridge | 171:3a7713b1edbc | 533 | #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */ |
AnnaBridge | 171:3a7713b1edbc | 534 | #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */ |
AnnaBridge | 171:3a7713b1edbc | 535 | #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */ |
AnnaBridge | 171:3a7713b1edbc | 536 | #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */ |
AnnaBridge | 171:3a7713b1edbc | 537 | #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */ |
AnnaBridge | 171:3a7713b1edbc | 538 | /** |
AnnaBridge | 171:3a7713b1edbc | 539 | * @} |
AnnaBridge | 171:3a7713b1edbc | 540 | */ |
AnnaBridge | 171:3a7713b1edbc | 541 | |
AnnaBridge | 171:3a7713b1edbc | 542 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 171:3a7713b1edbc | 543 | /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable |
AnnaBridge | 171:3a7713b1edbc | 544 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 545 | */ |
AnnaBridge | 171:3a7713b1edbc | 546 | #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ |
AnnaBridge | 171:3a7713b1edbc | 547 | #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ |
AnnaBridge | 171:3a7713b1edbc | 548 | /** |
AnnaBridge | 171:3a7713b1edbc | 549 | * @} |
AnnaBridge | 171:3a7713b1edbc | 550 | */ |
AnnaBridge | 171:3a7713b1edbc | 551 | |
AnnaBridge | 171:3a7713b1edbc | 552 | /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable |
AnnaBridge | 171:3a7713b1edbc | 553 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 554 | */ |
AnnaBridge | 171:3a7713b1edbc | 555 | #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */ |
AnnaBridge | 171:3a7713b1edbc | 556 | #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */ |
AnnaBridge | 171:3a7713b1edbc | 557 | /** |
AnnaBridge | 171:3a7713b1edbc | 558 | * @} |
AnnaBridge | 171:3a7713b1edbc | 559 | */ |
AnnaBridge | 171:3a7713b1edbc | 560 | |
AnnaBridge | 171:3a7713b1edbc | 561 | /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable |
AnnaBridge | 171:3a7713b1edbc | 562 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 563 | */ |
AnnaBridge | 171:3a7713b1edbc | 564 | #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ |
AnnaBridge | 171:3a7713b1edbc | 565 | #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */ |
AnnaBridge | 171:3a7713b1edbc | 566 | /** |
AnnaBridge | 171:3a7713b1edbc | 567 | * @} |
AnnaBridge | 171:3a7713b1edbc | 568 | */ |
AnnaBridge | 171:3a7713b1edbc | 569 | #endif /* USE_FULL_LL_DRIVER */ |
AnnaBridge | 171:3a7713b1edbc | 570 | |
AnnaBridge | 171:3a7713b1edbc | 571 | /** @defgroup TIM_LL_EC_IT IT Defines |
AnnaBridge | 171:3a7713b1edbc | 572 | * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. |
AnnaBridge | 171:3a7713b1edbc | 573 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 574 | */ |
AnnaBridge | 171:3a7713b1edbc | 575 | #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ |
AnnaBridge | 171:3a7713b1edbc | 576 | #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */ |
AnnaBridge | 171:3a7713b1edbc | 577 | #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */ |
AnnaBridge | 171:3a7713b1edbc | 578 | #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */ |
AnnaBridge | 171:3a7713b1edbc | 579 | #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */ |
AnnaBridge | 171:3a7713b1edbc | 580 | #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ |
AnnaBridge | 171:3a7713b1edbc | 581 | #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */ |
AnnaBridge | 171:3a7713b1edbc | 582 | #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ |
AnnaBridge | 171:3a7713b1edbc | 583 | /** |
AnnaBridge | 171:3a7713b1edbc | 584 | * @} |
AnnaBridge | 171:3a7713b1edbc | 585 | */ |
AnnaBridge | 171:3a7713b1edbc | 586 | |
AnnaBridge | 171:3a7713b1edbc | 587 | /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source |
AnnaBridge | 171:3a7713b1edbc | 588 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 589 | */ |
AnnaBridge | 171:3a7713b1edbc | 590 | #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ |
AnnaBridge | 171:3a7713b1edbc | 591 | #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ |
AnnaBridge | 171:3a7713b1edbc | 592 | /** |
AnnaBridge | 171:3a7713b1edbc | 593 | * @} |
AnnaBridge | 171:3a7713b1edbc | 594 | */ |
AnnaBridge | 171:3a7713b1edbc | 595 | |
AnnaBridge | 171:3a7713b1edbc | 596 | /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode |
AnnaBridge | 171:3a7713b1edbc | 597 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 598 | */ |
AnnaBridge | 171:3a7713b1edbc | 599 | #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */ |
AnnaBridge | 171:3a7713b1edbc | 600 | #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */ |
AnnaBridge | 171:3a7713b1edbc | 601 | /** |
AnnaBridge | 171:3a7713b1edbc | 602 | * @} |
AnnaBridge | 171:3a7713b1edbc | 603 | */ |
AnnaBridge | 171:3a7713b1edbc | 604 | |
AnnaBridge | 171:3a7713b1edbc | 605 | /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode |
AnnaBridge | 171:3a7713b1edbc | 606 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 607 | */ |
AnnaBridge | 171:3a7713b1edbc | 608 | #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */ |
AnnaBridge | 171:3a7713b1edbc | 609 | #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */ |
AnnaBridge | 171:3a7713b1edbc | 610 | #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */ |
AnnaBridge | 171:3a7713b1edbc | 611 | #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */ |
AnnaBridge | 171:3a7713b1edbc | 612 | #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */ |
AnnaBridge | 171:3a7713b1edbc | 613 | /** |
AnnaBridge | 171:3a7713b1edbc | 614 | * @} |
AnnaBridge | 171:3a7713b1edbc | 615 | */ |
AnnaBridge | 171:3a7713b1edbc | 616 | |
AnnaBridge | 171:3a7713b1edbc | 617 | /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division |
AnnaBridge | 171:3a7713b1edbc | 618 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 619 | */ |
AnnaBridge | 171:3a7713b1edbc | 620 | #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */ |
AnnaBridge | 171:3a7713b1edbc | 621 | #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */ |
AnnaBridge | 171:3a7713b1edbc | 622 | #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */ |
AnnaBridge | 171:3a7713b1edbc | 623 | /** |
AnnaBridge | 171:3a7713b1edbc | 624 | * @} |
AnnaBridge | 171:3a7713b1edbc | 625 | */ |
AnnaBridge | 171:3a7713b1edbc | 626 | |
AnnaBridge | 171:3a7713b1edbc | 627 | /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction |
AnnaBridge | 171:3a7713b1edbc | 628 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 629 | */ |
AnnaBridge | 171:3a7713b1edbc | 630 | #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */ |
AnnaBridge | 171:3a7713b1edbc | 631 | #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */ |
AnnaBridge | 171:3a7713b1edbc | 632 | /** |
AnnaBridge | 171:3a7713b1edbc | 633 | * @} |
AnnaBridge | 171:3a7713b1edbc | 634 | */ |
AnnaBridge | 171:3a7713b1edbc | 635 | |
AnnaBridge | 171:3a7713b1edbc | 636 | /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source |
AnnaBridge | 171:3a7713b1edbc | 637 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 638 | */ |
AnnaBridge | 171:3a7713b1edbc | 639 | #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */ |
AnnaBridge | 171:3a7713b1edbc | 640 | #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */ |
AnnaBridge | 171:3a7713b1edbc | 641 | /** |
AnnaBridge | 171:3a7713b1edbc | 642 | * @} |
AnnaBridge | 171:3a7713b1edbc | 643 | */ |
AnnaBridge | 171:3a7713b1edbc | 644 | |
AnnaBridge | 171:3a7713b1edbc | 645 | /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request |
AnnaBridge | 171:3a7713b1edbc | 646 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 647 | */ |
AnnaBridge | 171:3a7713b1edbc | 648 | #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */ |
AnnaBridge | 171:3a7713b1edbc | 649 | #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ |
AnnaBridge | 171:3a7713b1edbc | 650 | /** |
AnnaBridge | 171:3a7713b1edbc | 651 | * @} |
AnnaBridge | 171:3a7713b1edbc | 652 | */ |
AnnaBridge | 171:3a7713b1edbc | 653 | |
AnnaBridge | 171:3a7713b1edbc | 654 | /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level |
AnnaBridge | 171:3a7713b1edbc | 655 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 656 | */ |
AnnaBridge | 171:3a7713b1edbc | 657 | #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */ |
AnnaBridge | 171:3a7713b1edbc | 658 | #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ |
AnnaBridge | 171:3a7713b1edbc | 659 | #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ |
AnnaBridge | 171:3a7713b1edbc | 660 | #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ |
AnnaBridge | 171:3a7713b1edbc | 661 | /** |
AnnaBridge | 171:3a7713b1edbc | 662 | * @} |
AnnaBridge | 171:3a7713b1edbc | 663 | */ |
AnnaBridge | 171:3a7713b1edbc | 664 | |
AnnaBridge | 171:3a7713b1edbc | 665 | /** @defgroup TIM_LL_EC_CHANNEL Channel |
AnnaBridge | 171:3a7713b1edbc | 666 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 667 | */ |
AnnaBridge | 171:3a7713b1edbc | 668 | #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */ |
AnnaBridge | 171:3a7713b1edbc | 669 | #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */ |
AnnaBridge | 171:3a7713b1edbc | 670 | #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */ |
AnnaBridge | 171:3a7713b1edbc | 671 | #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */ |
AnnaBridge | 171:3a7713b1edbc | 672 | #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */ |
AnnaBridge | 171:3a7713b1edbc | 673 | #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */ |
AnnaBridge | 171:3a7713b1edbc | 674 | #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */ |
AnnaBridge | 171:3a7713b1edbc | 675 | #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */ |
AnnaBridge | 171:3a7713b1edbc | 676 | #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */ |
AnnaBridge | 171:3a7713b1edbc | 677 | /** |
AnnaBridge | 171:3a7713b1edbc | 678 | * @} |
AnnaBridge | 171:3a7713b1edbc | 679 | */ |
AnnaBridge | 171:3a7713b1edbc | 680 | |
AnnaBridge | 171:3a7713b1edbc | 681 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 171:3a7713b1edbc | 682 | /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State |
AnnaBridge | 171:3a7713b1edbc | 683 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 684 | */ |
AnnaBridge | 171:3a7713b1edbc | 685 | #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */ |
AnnaBridge | 171:3a7713b1edbc | 686 | #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */ |
AnnaBridge | 171:3a7713b1edbc | 687 | /** |
AnnaBridge | 171:3a7713b1edbc | 688 | * @} |
AnnaBridge | 171:3a7713b1edbc | 689 | */ |
AnnaBridge | 171:3a7713b1edbc | 690 | #endif /* USE_FULL_LL_DRIVER */ |
AnnaBridge | 171:3a7713b1edbc | 691 | |
AnnaBridge | 171:3a7713b1edbc | 692 | /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode |
AnnaBridge | 171:3a7713b1edbc | 693 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 694 | */ |
AnnaBridge | 171:3a7713b1edbc | 695 | #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */ |
AnnaBridge | 171:3a7713b1edbc | 696 | #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/ |
AnnaBridge | 171:3a7713b1edbc | 697 | #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/ |
AnnaBridge | 171:3a7713b1edbc | 698 | #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/ |
AnnaBridge | 171:3a7713b1edbc | 699 | #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/ |
AnnaBridge | 171:3a7713b1edbc | 700 | #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/ |
AnnaBridge | 171:3a7713b1edbc | 701 | #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/ |
AnnaBridge | 171:3a7713b1edbc | 702 | #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/ |
AnnaBridge | 171:3a7713b1edbc | 703 | #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/ |
AnnaBridge | 171:3a7713b1edbc | 704 | #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/ |
AnnaBridge | 171:3a7713b1edbc | 705 | #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/ |
AnnaBridge | 171:3a7713b1edbc | 706 | #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/ |
AnnaBridge | 171:3a7713b1edbc | 707 | #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/ |
AnnaBridge | 171:3a7713b1edbc | 708 | #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/ |
AnnaBridge | 171:3a7713b1edbc | 709 | /** |
AnnaBridge | 171:3a7713b1edbc | 710 | * @} |
AnnaBridge | 171:3a7713b1edbc | 711 | */ |
AnnaBridge | 171:3a7713b1edbc | 712 | |
AnnaBridge | 171:3a7713b1edbc | 713 | /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity |
AnnaBridge | 171:3a7713b1edbc | 714 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 715 | */ |
AnnaBridge | 171:3a7713b1edbc | 716 | #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/ |
AnnaBridge | 171:3a7713b1edbc | 717 | #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/ |
AnnaBridge | 171:3a7713b1edbc | 718 | /** |
AnnaBridge | 171:3a7713b1edbc | 719 | * @} |
AnnaBridge | 171:3a7713b1edbc | 720 | */ |
AnnaBridge | 171:3a7713b1edbc | 721 | |
AnnaBridge | 171:3a7713b1edbc | 722 | /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State |
AnnaBridge | 171:3a7713b1edbc | 723 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 724 | */ |
AnnaBridge | 171:3a7713b1edbc | 725 | #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/ |
AnnaBridge | 171:3a7713b1edbc | 726 | #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/ |
AnnaBridge | 171:3a7713b1edbc | 727 | /** |
AnnaBridge | 171:3a7713b1edbc | 728 | * @} |
AnnaBridge | 171:3a7713b1edbc | 729 | */ |
AnnaBridge | 171:3a7713b1edbc | 730 | |
AnnaBridge | 171:3a7713b1edbc | 731 | /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5 |
AnnaBridge | 171:3a7713b1edbc | 732 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 733 | */ |
AnnaBridge | 171:3a7713b1edbc | 734 | #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ |
AnnaBridge | 171:3a7713b1edbc | 735 | #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */ |
AnnaBridge | 171:3a7713b1edbc | 736 | #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */ |
AnnaBridge | 171:3a7713b1edbc | 737 | #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */ |
AnnaBridge | 171:3a7713b1edbc | 738 | /** |
AnnaBridge | 171:3a7713b1edbc | 739 | * @} |
AnnaBridge | 171:3a7713b1edbc | 740 | */ |
AnnaBridge | 171:3a7713b1edbc | 741 | |
AnnaBridge | 171:3a7713b1edbc | 742 | /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection |
AnnaBridge | 171:3a7713b1edbc | 743 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 744 | */ |
AnnaBridge | 171:3a7713b1edbc | 745 | #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */ |
AnnaBridge | 171:3a7713b1edbc | 746 | #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */ |
AnnaBridge | 171:3a7713b1edbc | 747 | #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */ |
AnnaBridge | 171:3a7713b1edbc | 748 | /** |
AnnaBridge | 171:3a7713b1edbc | 749 | * @} |
AnnaBridge | 171:3a7713b1edbc | 750 | */ |
AnnaBridge | 171:3a7713b1edbc | 751 | |
AnnaBridge | 171:3a7713b1edbc | 752 | /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler |
AnnaBridge | 171:3a7713b1edbc | 753 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 754 | */ |
AnnaBridge | 171:3a7713b1edbc | 755 | #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */ |
AnnaBridge | 171:3a7713b1edbc | 756 | #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */ |
AnnaBridge | 171:3a7713b1edbc | 757 | #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */ |
AnnaBridge | 171:3a7713b1edbc | 758 | #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */ |
AnnaBridge | 171:3a7713b1edbc | 759 | /** |
AnnaBridge | 171:3a7713b1edbc | 760 | * @} |
AnnaBridge | 171:3a7713b1edbc | 761 | */ |
AnnaBridge | 171:3a7713b1edbc | 762 | |
AnnaBridge | 171:3a7713b1edbc | 763 | /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter |
AnnaBridge | 171:3a7713b1edbc | 764 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 765 | */ |
AnnaBridge | 171:3a7713b1edbc | 766 | #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */ |
AnnaBridge | 171:3a7713b1edbc | 767 | #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */ |
AnnaBridge | 171:3a7713b1edbc | 768 | #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */ |
AnnaBridge | 171:3a7713b1edbc | 769 | #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */ |
AnnaBridge | 171:3a7713b1edbc | 770 | #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */ |
AnnaBridge | 171:3a7713b1edbc | 771 | #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */ |
AnnaBridge | 171:3a7713b1edbc | 772 | #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */ |
AnnaBridge | 171:3a7713b1edbc | 773 | #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */ |
AnnaBridge | 171:3a7713b1edbc | 774 | #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */ |
AnnaBridge | 171:3a7713b1edbc | 775 | #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */ |
AnnaBridge | 171:3a7713b1edbc | 776 | #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */ |
AnnaBridge | 171:3a7713b1edbc | 777 | #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */ |
AnnaBridge | 171:3a7713b1edbc | 778 | #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */ |
AnnaBridge | 171:3a7713b1edbc | 779 | #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */ |
AnnaBridge | 171:3a7713b1edbc | 780 | #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */ |
AnnaBridge | 171:3a7713b1edbc | 781 | #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */ |
AnnaBridge | 171:3a7713b1edbc | 782 | /** |
AnnaBridge | 171:3a7713b1edbc | 783 | * @} |
AnnaBridge | 171:3a7713b1edbc | 784 | */ |
AnnaBridge | 171:3a7713b1edbc | 785 | |
AnnaBridge | 171:3a7713b1edbc | 786 | /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity |
AnnaBridge | 171:3a7713b1edbc | 787 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 788 | */ |
AnnaBridge | 171:3a7713b1edbc | 789 | #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */ |
AnnaBridge | 171:3a7713b1edbc | 790 | #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */ |
AnnaBridge | 171:3a7713b1edbc | 791 | #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */ |
AnnaBridge | 171:3a7713b1edbc | 792 | /** |
AnnaBridge | 171:3a7713b1edbc | 793 | * @} |
AnnaBridge | 171:3a7713b1edbc | 794 | */ |
AnnaBridge | 171:3a7713b1edbc | 795 | |
AnnaBridge | 171:3a7713b1edbc | 796 | /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source |
AnnaBridge | 171:3a7713b1edbc | 797 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 798 | */ |
AnnaBridge | 171:3a7713b1edbc | 799 | #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */ |
AnnaBridge | 171:3a7713b1edbc | 800 | #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected inpu t*/ |
AnnaBridge | 171:3a7713b1edbc | 801 | #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */ |
AnnaBridge | 171:3a7713b1edbc | 802 | /** |
AnnaBridge | 171:3a7713b1edbc | 803 | * @} |
AnnaBridge | 171:3a7713b1edbc | 804 | */ |
AnnaBridge | 171:3a7713b1edbc | 805 | |
AnnaBridge | 171:3a7713b1edbc | 806 | /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode |
AnnaBridge | 171:3a7713b1edbc | 807 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 808 | */ |
AnnaBridge | 171:3a7713b1edbc | 809 | #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */ |
AnnaBridge | 171:3a7713b1edbc | 810 | #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */ |
AnnaBridge | 171:3a7713b1edbc | 811 | #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l */ |
AnnaBridge | 171:3a7713b1edbc | 812 | /** |
AnnaBridge | 171:3a7713b1edbc | 813 | * @} |
AnnaBridge | 171:3a7713b1edbc | 814 | */ |
AnnaBridge | 171:3a7713b1edbc | 815 | |
AnnaBridge | 171:3a7713b1edbc | 816 | /** @defgroup TIM_LL_EC_TRGO Trigger Output |
AnnaBridge | 171:3a7713b1edbc | 817 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 818 | */ |
AnnaBridge | 171:3a7713b1edbc | 819 | #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */ |
AnnaBridge | 171:3a7713b1edbc | 820 | #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */ |
AnnaBridge | 171:3a7713b1edbc | 821 | #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */ |
AnnaBridge | 171:3a7713b1edbc | 822 | #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */ |
AnnaBridge | 171:3a7713b1edbc | 823 | #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */ |
AnnaBridge | 171:3a7713b1edbc | 824 | #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */ |
AnnaBridge | 171:3a7713b1edbc | 825 | #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */ |
AnnaBridge | 171:3a7713b1edbc | 826 | #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */ |
AnnaBridge | 171:3a7713b1edbc | 827 | /** |
AnnaBridge | 171:3a7713b1edbc | 828 | * @} |
AnnaBridge | 171:3a7713b1edbc | 829 | */ |
AnnaBridge | 171:3a7713b1edbc | 830 | |
AnnaBridge | 171:3a7713b1edbc | 831 | /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2 |
AnnaBridge | 171:3a7713b1edbc | 832 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 833 | */ |
AnnaBridge | 171:3a7713b1edbc | 834 | #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */ |
AnnaBridge | 171:3a7713b1edbc | 835 | #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */ |
AnnaBridge | 171:3a7713b1edbc | 836 | #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */ |
AnnaBridge | 171:3a7713b1edbc | 837 | #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */ |
AnnaBridge | 171:3a7713b1edbc | 838 | #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */ |
AnnaBridge | 171:3a7713b1edbc | 839 | #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */ |
AnnaBridge | 171:3a7713b1edbc | 840 | #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */ |
AnnaBridge | 171:3a7713b1edbc | 841 | #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */ |
AnnaBridge | 171:3a7713b1edbc | 842 | #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */ |
AnnaBridge | 171:3a7713b1edbc | 843 | #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */ |
AnnaBridge | 171:3a7713b1edbc | 844 | #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */ |
AnnaBridge | 171:3a7713b1edbc | 845 | #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */ |
AnnaBridge | 171:3a7713b1edbc | 846 | #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */ |
AnnaBridge | 171:3a7713b1edbc | 847 | #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */ |
AnnaBridge | 171:3a7713b1edbc | 848 | #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */ |
AnnaBridge | 171:3a7713b1edbc | 849 | #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */ |
AnnaBridge | 171:3a7713b1edbc | 850 | /** |
AnnaBridge | 171:3a7713b1edbc | 851 | * @} |
AnnaBridge | 171:3a7713b1edbc | 852 | */ |
AnnaBridge | 171:3a7713b1edbc | 853 | |
AnnaBridge | 171:3a7713b1edbc | 854 | /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode |
AnnaBridge | 171:3a7713b1edbc | 855 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 856 | */ |
AnnaBridge | 171:3a7713b1edbc | 857 | #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */ |
AnnaBridge | 171:3a7713b1edbc | 858 | #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */ |
AnnaBridge | 171:3a7713b1edbc | 859 | #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */ |
AnnaBridge | 171:3a7713b1edbc | 860 | #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */ |
AnnaBridge | 171:3a7713b1edbc | 861 | #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */ |
AnnaBridge | 171:3a7713b1edbc | 862 | /** |
AnnaBridge | 171:3a7713b1edbc | 863 | * @} |
AnnaBridge | 171:3a7713b1edbc | 864 | */ |
AnnaBridge | 171:3a7713b1edbc | 865 | |
AnnaBridge | 171:3a7713b1edbc | 866 | /** @defgroup TIM_LL_EC_TS Trigger Selection |
AnnaBridge | 171:3a7713b1edbc | 867 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 868 | */ |
AnnaBridge | 171:3a7713b1edbc | 869 | #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */ |
AnnaBridge | 171:3a7713b1edbc | 870 | #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */ |
AnnaBridge | 171:3a7713b1edbc | 871 | #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */ |
AnnaBridge | 171:3a7713b1edbc | 872 | #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */ |
AnnaBridge | 171:3a7713b1edbc | 873 | #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */ |
AnnaBridge | 171:3a7713b1edbc | 874 | #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */ |
AnnaBridge | 171:3a7713b1edbc | 875 | #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */ |
AnnaBridge | 171:3a7713b1edbc | 876 | #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */ |
AnnaBridge | 171:3a7713b1edbc | 877 | /** |
AnnaBridge | 171:3a7713b1edbc | 878 | * @} |
AnnaBridge | 171:3a7713b1edbc | 879 | */ |
AnnaBridge | 171:3a7713b1edbc | 880 | |
AnnaBridge | 171:3a7713b1edbc | 881 | /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity |
AnnaBridge | 171:3a7713b1edbc | 882 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 883 | */ |
AnnaBridge | 171:3a7713b1edbc | 884 | #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */ |
AnnaBridge | 171:3a7713b1edbc | 885 | #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */ |
AnnaBridge | 171:3a7713b1edbc | 886 | /** |
AnnaBridge | 171:3a7713b1edbc | 887 | * @} |
AnnaBridge | 171:3a7713b1edbc | 888 | */ |
AnnaBridge | 171:3a7713b1edbc | 889 | |
AnnaBridge | 171:3a7713b1edbc | 890 | /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler |
AnnaBridge | 171:3a7713b1edbc | 891 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 892 | */ |
AnnaBridge | 171:3a7713b1edbc | 893 | #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */ |
AnnaBridge | 171:3a7713b1edbc | 894 | #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */ |
AnnaBridge | 171:3a7713b1edbc | 895 | #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */ |
AnnaBridge | 171:3a7713b1edbc | 896 | #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */ |
AnnaBridge | 171:3a7713b1edbc | 897 | /** |
AnnaBridge | 171:3a7713b1edbc | 898 | * @} |
AnnaBridge | 171:3a7713b1edbc | 899 | */ |
AnnaBridge | 171:3a7713b1edbc | 900 | |
AnnaBridge | 171:3a7713b1edbc | 901 | /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter |
AnnaBridge | 171:3a7713b1edbc | 902 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 903 | */ |
AnnaBridge | 171:3a7713b1edbc | 904 | #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */ |
AnnaBridge | 171:3a7713b1edbc | 905 | #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */ |
AnnaBridge | 171:3a7713b1edbc | 906 | #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */ |
AnnaBridge | 171:3a7713b1edbc | 907 | #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */ |
AnnaBridge | 171:3a7713b1edbc | 908 | #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */ |
AnnaBridge | 171:3a7713b1edbc | 909 | #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */ |
AnnaBridge | 171:3a7713b1edbc | 910 | #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */ |
AnnaBridge | 171:3a7713b1edbc | 911 | #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */ |
AnnaBridge | 171:3a7713b1edbc | 912 | #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */ |
AnnaBridge | 171:3a7713b1edbc | 913 | #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */ |
AnnaBridge | 171:3a7713b1edbc | 914 | #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */ |
AnnaBridge | 171:3a7713b1edbc | 915 | #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */ |
AnnaBridge | 171:3a7713b1edbc | 916 | #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */ |
AnnaBridge | 171:3a7713b1edbc | 917 | #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */ |
AnnaBridge | 171:3a7713b1edbc | 918 | #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */ |
AnnaBridge | 171:3a7713b1edbc | 919 | #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */ |
AnnaBridge | 171:3a7713b1edbc | 920 | /** |
AnnaBridge | 171:3a7713b1edbc | 921 | * @} |
AnnaBridge | 171:3a7713b1edbc | 922 | */ |
AnnaBridge | 171:3a7713b1edbc | 923 | |
AnnaBridge | 171:3a7713b1edbc | 924 | |
AnnaBridge | 171:3a7713b1edbc | 925 | /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity |
AnnaBridge | 171:3a7713b1edbc | 926 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 927 | */ |
AnnaBridge | 171:3a7713b1edbc | 928 | #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ |
AnnaBridge | 171:3a7713b1edbc | 929 | #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ |
AnnaBridge | 171:3a7713b1edbc | 930 | /** |
AnnaBridge | 171:3a7713b1edbc | 931 | * @} |
AnnaBridge | 171:3a7713b1edbc | 932 | */ |
AnnaBridge | 171:3a7713b1edbc | 933 | |
AnnaBridge | 171:3a7713b1edbc | 934 | /** @defgroup TIM_LL_EC_BREAK_FILTER break filter |
AnnaBridge | 171:3a7713b1edbc | 935 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 936 | */ |
AnnaBridge | 171:3a7713b1edbc | 937 | #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */ |
AnnaBridge | 171:3a7713b1edbc | 938 | #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */ |
AnnaBridge | 171:3a7713b1edbc | 939 | #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */ |
AnnaBridge | 171:3a7713b1edbc | 940 | #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */ |
AnnaBridge | 171:3a7713b1edbc | 941 | #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */ |
AnnaBridge | 171:3a7713b1edbc | 942 | #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */ |
AnnaBridge | 171:3a7713b1edbc | 943 | #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */ |
AnnaBridge | 171:3a7713b1edbc | 944 | #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */ |
AnnaBridge | 171:3a7713b1edbc | 945 | #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */ |
AnnaBridge | 171:3a7713b1edbc | 946 | #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */ |
AnnaBridge | 171:3a7713b1edbc | 947 | #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */ |
AnnaBridge | 171:3a7713b1edbc | 948 | #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */ |
AnnaBridge | 171:3a7713b1edbc | 949 | #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */ |
AnnaBridge | 171:3a7713b1edbc | 950 | #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */ |
AnnaBridge | 171:3a7713b1edbc | 951 | #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */ |
AnnaBridge | 171:3a7713b1edbc | 952 | #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */ |
AnnaBridge | 171:3a7713b1edbc | 953 | /** |
AnnaBridge | 171:3a7713b1edbc | 954 | * @} |
AnnaBridge | 171:3a7713b1edbc | 955 | */ |
AnnaBridge | 171:3a7713b1edbc | 956 | |
AnnaBridge | 171:3a7713b1edbc | 957 | /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY |
AnnaBridge | 171:3a7713b1edbc | 958 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 959 | */ |
AnnaBridge | 171:3a7713b1edbc | 960 | #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ |
AnnaBridge | 171:3a7713b1edbc | 961 | #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ |
AnnaBridge | 171:3a7713b1edbc | 962 | /** |
AnnaBridge | 171:3a7713b1edbc | 963 | * @} |
AnnaBridge | 171:3a7713b1edbc | 964 | */ |
AnnaBridge | 171:3a7713b1edbc | 965 | |
AnnaBridge | 171:3a7713b1edbc | 966 | /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER |
AnnaBridge | 171:3a7713b1edbc | 967 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 968 | */ |
AnnaBridge | 171:3a7713b1edbc | 969 | #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */ |
AnnaBridge | 171:3a7713b1edbc | 970 | #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */ |
AnnaBridge | 171:3a7713b1edbc | 971 | #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */ |
AnnaBridge | 171:3a7713b1edbc | 972 | #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */ |
AnnaBridge | 171:3a7713b1edbc | 973 | #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */ |
AnnaBridge | 171:3a7713b1edbc | 974 | #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */ |
AnnaBridge | 171:3a7713b1edbc | 975 | #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */ |
AnnaBridge | 171:3a7713b1edbc | 976 | #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */ |
AnnaBridge | 171:3a7713b1edbc | 977 | #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */ |
AnnaBridge | 171:3a7713b1edbc | 978 | #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */ |
AnnaBridge | 171:3a7713b1edbc | 979 | #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */ |
AnnaBridge | 171:3a7713b1edbc | 980 | #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */ |
AnnaBridge | 171:3a7713b1edbc | 981 | #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */ |
AnnaBridge | 171:3a7713b1edbc | 982 | #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */ |
AnnaBridge | 171:3a7713b1edbc | 983 | #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */ |
AnnaBridge | 171:3a7713b1edbc | 984 | #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */ |
AnnaBridge | 171:3a7713b1edbc | 985 | /** |
AnnaBridge | 171:3a7713b1edbc | 986 | * @} |
AnnaBridge | 171:3a7713b1edbc | 987 | */ |
AnnaBridge | 171:3a7713b1edbc | 988 | |
AnnaBridge | 171:3a7713b1edbc | 989 | /** @defgroup TIM_LL_EC_OSSI OSSI |
AnnaBridge | 171:3a7713b1edbc | 990 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 991 | */ |
AnnaBridge | 171:3a7713b1edbc | 992 | #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */ |
AnnaBridge | 171:3a7713b1edbc | 993 | #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */ |
AnnaBridge | 171:3a7713b1edbc | 994 | /** |
AnnaBridge | 171:3a7713b1edbc | 995 | * @} |
AnnaBridge | 171:3a7713b1edbc | 996 | */ |
AnnaBridge | 171:3a7713b1edbc | 997 | |
AnnaBridge | 171:3a7713b1edbc | 998 | /** @defgroup TIM_LL_EC_OSSR OSSR |
AnnaBridge | 171:3a7713b1edbc | 999 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1000 | */ |
AnnaBridge | 171:3a7713b1edbc | 1001 | #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */ |
AnnaBridge | 171:3a7713b1edbc | 1002 | #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */ |
AnnaBridge | 171:3a7713b1edbc | 1003 | /** |
AnnaBridge | 171:3a7713b1edbc | 1004 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1005 | */ |
AnnaBridge | 171:3a7713b1edbc | 1006 | |
AnnaBridge | 171:3a7713b1edbc | 1007 | #if defined(TIM_BREAK_INPUT_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 1008 | /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT |
AnnaBridge | 171:3a7713b1edbc | 1009 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1010 | */ |
AnnaBridge | 171:3a7713b1edbc | 1011 | #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */ |
AnnaBridge | 171:3a7713b1edbc | 1012 | #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */ |
AnnaBridge | 171:3a7713b1edbc | 1013 | /** |
AnnaBridge | 171:3a7713b1edbc | 1014 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1015 | */ |
AnnaBridge | 171:3a7713b1edbc | 1016 | |
AnnaBridge | 171:3a7713b1edbc | 1017 | /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE |
AnnaBridge | 171:3a7713b1edbc | 1018 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1019 | */ |
AnnaBridge | 171:3a7713b1edbc | 1020 | #define LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE /*!< BKIN input from AF controller */ |
AnnaBridge | 171:3a7713b1edbc | 1021 | #define LL_TIM_BKIN_SOURCE_DF1BK TIM1_AF1_BKDF1BKE /*!< internal signal: DFSDM1 break output */ |
AnnaBridge | 171:3a7713b1edbc | 1022 | /** |
AnnaBridge | 171:3a7713b1edbc | 1023 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1024 | */ |
AnnaBridge | 171:3a7713b1edbc | 1025 | |
AnnaBridge | 171:3a7713b1edbc | 1026 | /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY |
AnnaBridge | 171:3a7713b1edbc | 1027 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1028 | */ |
AnnaBridge | 171:3a7713b1edbc | 1029 | #define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP /*!< BRK BKIN input is active low */ |
AnnaBridge | 171:3a7713b1edbc | 1030 | #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */ |
AnnaBridge | 171:3a7713b1edbc | 1031 | /** |
AnnaBridge | 171:3a7713b1edbc | 1032 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1033 | */ |
AnnaBridge | 171:3a7713b1edbc | 1034 | #endif /* TIM_BREAK_INPUT_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 1035 | |
AnnaBridge | 171:3a7713b1edbc | 1036 | /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address |
AnnaBridge | 171:3a7713b1edbc | 1037 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1038 | */ |
AnnaBridge | 171:3a7713b1edbc | 1039 | #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */ |
AnnaBridge | 171:3a7713b1edbc | 1040 | #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */ |
AnnaBridge | 171:3a7713b1edbc | 1041 | #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */ |
AnnaBridge | 171:3a7713b1edbc | 1042 | #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */ |
AnnaBridge | 171:3a7713b1edbc | 1043 | #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */ |
AnnaBridge | 171:3a7713b1edbc | 1044 | #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */ |
AnnaBridge | 171:3a7713b1edbc | 1045 | #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */ |
AnnaBridge | 171:3a7713b1edbc | 1046 | #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */ |
AnnaBridge | 171:3a7713b1edbc | 1047 | #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */ |
AnnaBridge | 171:3a7713b1edbc | 1048 | #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */ |
AnnaBridge | 171:3a7713b1edbc | 1049 | #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */ |
AnnaBridge | 171:3a7713b1edbc | 1050 | #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */ |
AnnaBridge | 171:3a7713b1edbc | 1051 | #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */ |
AnnaBridge | 171:3a7713b1edbc | 1052 | #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */ |
AnnaBridge | 171:3a7713b1edbc | 1053 | #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */ |
AnnaBridge | 171:3a7713b1edbc | 1054 | #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */ |
AnnaBridge | 171:3a7713b1edbc | 1055 | #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */ |
AnnaBridge | 171:3a7713b1edbc | 1056 | #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */ |
AnnaBridge | 171:3a7713b1edbc | 1057 | #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */ |
AnnaBridge | 171:3a7713b1edbc | 1058 | #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */ |
AnnaBridge | 171:3a7713b1edbc | 1059 | #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */ |
AnnaBridge | 171:3a7713b1edbc | 1060 | #define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_OR register is the DMA base address for DMA burst */ |
AnnaBridge | 171:3a7713b1edbc | 1061 | #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_AF1 register is the DMA base address for DMA burst */ |
AnnaBridge | 171:3a7713b1edbc | 1062 | #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */ |
AnnaBridge | 171:3a7713b1edbc | 1063 | |
AnnaBridge | 171:3a7713b1edbc | 1064 | /** |
AnnaBridge | 171:3a7713b1edbc | 1065 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1066 | */ |
AnnaBridge | 171:3a7713b1edbc | 1067 | |
AnnaBridge | 171:3a7713b1edbc | 1068 | /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length |
AnnaBridge | 171:3a7713b1edbc | 1069 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1070 | */ |
AnnaBridge | 171:3a7713b1edbc | 1071 | #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */ |
AnnaBridge | 171:3a7713b1edbc | 1072 | #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */ |
AnnaBridge | 171:3a7713b1edbc | 1073 | #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */ |
AnnaBridge | 171:3a7713b1edbc | 1074 | #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */ |
AnnaBridge | 171:3a7713b1edbc | 1075 | #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */ |
AnnaBridge | 171:3a7713b1edbc | 1076 | #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */ |
AnnaBridge | 171:3a7713b1edbc | 1077 | #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */ |
AnnaBridge | 171:3a7713b1edbc | 1078 | #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */ |
AnnaBridge | 171:3a7713b1edbc | 1079 | #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */ |
AnnaBridge | 171:3a7713b1edbc | 1080 | #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */ |
AnnaBridge | 171:3a7713b1edbc | 1081 | #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */ |
AnnaBridge | 171:3a7713b1edbc | 1082 | #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */ |
AnnaBridge | 171:3a7713b1edbc | 1083 | #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */ |
AnnaBridge | 171:3a7713b1edbc | 1084 | #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */ |
AnnaBridge | 171:3a7713b1edbc | 1085 | #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */ |
AnnaBridge | 171:3a7713b1edbc | 1086 | #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */ |
AnnaBridge | 171:3a7713b1edbc | 1087 | #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */ |
AnnaBridge | 171:3a7713b1edbc | 1088 | #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */ |
AnnaBridge | 171:3a7713b1edbc | 1089 | /** |
AnnaBridge | 171:3a7713b1edbc | 1090 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1091 | */ |
AnnaBridge | 171:3a7713b1edbc | 1092 | |
AnnaBridge | 171:3a7713b1edbc | 1093 | |
AnnaBridge | 171:3a7713b1edbc | 1094 | /** @defgroup TIM_LL_EC_TIM2_ITR1_RMP_TIM8 TIM2 Internal Trigger1 Remap TIM8 |
AnnaBridge | 171:3a7713b1edbc | 1095 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1096 | */ |
AnnaBridge | 171:3a7713b1edbc | 1097 | #define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO TIM2_OR_RMP_MASK /*!< TIM2_ITR1 is connected to TIM8_TRGO */ |
AnnaBridge | 171:3a7713b1edbc | 1098 | #define LL_TIM_TIM2_ITR1_RMP_ETH_PTP (TIM2_OR_ITR1_RMP_0 | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to ETH_PTP */ |
AnnaBridge | 171:3a7713b1edbc | 1099 | #define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM2_OR_ITR1_RMP_1 | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_FS SOF */ |
AnnaBridge | 171:3a7713b1edbc | 1100 | #define LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF (TIM2_OR_ITR1_RMP | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_HS SOF */ |
AnnaBridge | 171:3a7713b1edbc | 1101 | /** |
AnnaBridge | 171:3a7713b1edbc | 1102 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1103 | */ |
AnnaBridge | 171:3a7713b1edbc | 1104 | |
AnnaBridge | 171:3a7713b1edbc | 1105 | /** @defgroup TIM_LL_EC_TIM5_TI4_RMP TIM5 External Input Ch4 Remap |
AnnaBridge | 171:3a7713b1edbc | 1106 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1107 | */ |
AnnaBridge | 171:3a7713b1edbc | 1108 | #define LL_TIM_TIM5_TI4_RMP_GPIO TIM5_OR_RMP_MASK /*!< TIM5 channel 4 is connected to GPIO */ |
AnnaBridge | 171:3a7713b1edbc | 1109 | #define LL_TIM_TIM5_TI4_RMP_LSI (TIM5_OR_TI4_RMP_0 | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to LSI internal clock */ |
AnnaBridge | 171:3a7713b1edbc | 1110 | #define LL_TIM_TIM5_TI4_RMP_LSE (TIM5_OR_TI4_RMP_1 | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to LSE */ |
AnnaBridge | 171:3a7713b1edbc | 1111 | #define LL_TIM_TIM5_TI4_RMP_RTC (TIM5_OR_TI4_RMP | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to RTC wakeup interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 1112 | /** |
AnnaBridge | 171:3a7713b1edbc | 1113 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1114 | */ |
AnnaBridge | 171:3a7713b1edbc | 1115 | |
AnnaBridge | 171:3a7713b1edbc | 1116 | /** @defgroup TIM_LL_EC_TIM11_TI1_RMP TIM11 External Input Capture 1 Remap |
AnnaBridge | 171:3a7713b1edbc | 1117 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1118 | */ |
AnnaBridge | 171:3a7713b1edbc | 1119 | #define LL_TIM_TIM11_TI1_RMP_GPIO TIM11_OR_RMP_MASK /*!< TIM11 channel 1 is connected to GPIO */ |
AnnaBridge | 171:3a7713b1edbc | 1120 | #define LL_TIM_TIM11_TI1_RMP_SPDIFRX (TIM11_OR_TI1_RMP_0 | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to SPDIFRX */ |
AnnaBridge | 171:3a7713b1edbc | 1121 | #define LL_TIM_TIM11_TI1_RMP_HSE (TIM11_OR_TI1_RMP_1 | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to HSE */ |
AnnaBridge | 171:3a7713b1edbc | 1122 | #define LL_TIM_TIM11_TI1_RMP_MCO1 (TIM11_OR_TI1_RMP | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to MCO1 */ |
AnnaBridge | 171:3a7713b1edbc | 1123 | /** |
AnnaBridge | 171:3a7713b1edbc | 1124 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1125 | */ |
AnnaBridge | 171:3a7713b1edbc | 1126 | |
AnnaBridge | 171:3a7713b1edbc | 1127 | /** |
AnnaBridge | 171:3a7713b1edbc | 1128 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1129 | */ |
AnnaBridge | 171:3a7713b1edbc | 1130 | |
AnnaBridge | 171:3a7713b1edbc | 1131 | |
AnnaBridge | 171:3a7713b1edbc | 1132 | /** |
AnnaBridge | 171:3a7713b1edbc | 1133 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1134 | */ |
AnnaBridge | 171:3a7713b1edbc | 1135 | |
AnnaBridge | 171:3a7713b1edbc | 1136 | /* Exported macro ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 1137 | /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros |
AnnaBridge | 171:3a7713b1edbc | 1138 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1139 | */ |
AnnaBridge | 171:3a7713b1edbc | 1140 | |
AnnaBridge | 171:3a7713b1edbc | 1141 | /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros |
AnnaBridge | 171:3a7713b1edbc | 1142 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1143 | */ |
AnnaBridge | 171:3a7713b1edbc | 1144 | /** |
AnnaBridge | 171:3a7713b1edbc | 1145 | * @brief Write a value in TIM register. |
AnnaBridge | 171:3a7713b1edbc | 1146 | * @param __INSTANCE__ TIM Instance |
AnnaBridge | 171:3a7713b1edbc | 1147 | * @param __REG__ Register to be written |
AnnaBridge | 171:3a7713b1edbc | 1148 | * @param __VALUE__ Value to be written in the register |
AnnaBridge | 171:3a7713b1edbc | 1149 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1150 | */ |
AnnaBridge | 171:3a7713b1edbc | 1151 | #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) |
AnnaBridge | 171:3a7713b1edbc | 1152 | |
AnnaBridge | 171:3a7713b1edbc | 1153 | /** |
AnnaBridge | 171:3a7713b1edbc | 1154 | * @brief Read a value in TIM register. |
AnnaBridge | 171:3a7713b1edbc | 1155 | * @param __INSTANCE__ TIM Instance |
AnnaBridge | 171:3a7713b1edbc | 1156 | * @param __REG__ Register to be read |
AnnaBridge | 171:3a7713b1edbc | 1157 | * @retval Register value |
AnnaBridge | 171:3a7713b1edbc | 1158 | */ |
AnnaBridge | 171:3a7713b1edbc | 1159 | #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) |
AnnaBridge | 171:3a7713b1edbc | 1160 | /** |
AnnaBridge | 171:3a7713b1edbc | 1161 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1162 | */ |
AnnaBridge | 171:3a7713b1edbc | 1163 | |
AnnaBridge | 171:3a7713b1edbc | 1164 | /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros |
AnnaBridge | 171:3a7713b1edbc | 1165 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1166 | */ |
AnnaBridge | 171:3a7713b1edbc | 1167 | /** |
AnnaBridge | 171:3a7713b1edbc | 1168 | * @brief HELPER macro retrieving the UIFCPY flag from the counter value. |
AnnaBridge | 171:3a7713b1edbc | 1169 | * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ()); |
AnnaBridge | 171:3a7713b1edbc | 1170 | * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied |
AnnaBridge | 171:3a7713b1edbc | 1171 | * to TIMx_CNT register bit 31) |
AnnaBridge | 171:3a7713b1edbc | 1172 | * @param __CNT__ Counter value |
AnnaBridge | 171:3a7713b1edbc | 1173 | * @retval UIF status bit |
AnnaBridge | 171:3a7713b1edbc | 1174 | */ |
AnnaBridge | 171:3a7713b1edbc | 1175 | #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \ |
AnnaBridge | 171:3a7713b1edbc | 1176 | (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1177 | |
AnnaBridge | 171:3a7713b1edbc | 1178 | /** |
AnnaBridge | 171:3a7713b1edbc | 1179 | * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration. |
AnnaBridge | 171:3a7713b1edbc | 1180 | * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); |
AnnaBridge | 171:3a7713b1edbc | 1181 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
AnnaBridge | 171:3a7713b1edbc | 1182 | * @param __CKD__ This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1183 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 |
AnnaBridge | 171:3a7713b1edbc | 1184 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 |
AnnaBridge | 171:3a7713b1edbc | 1185 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 |
AnnaBridge | 171:3a7713b1edbc | 1186 | * @param __DT__ deadtime duration (in ns) |
AnnaBridge | 171:3a7713b1edbc | 1187 | * @retval DTG[0:7] |
AnnaBridge | 171:3a7713b1edbc | 1188 | */ |
AnnaBridge | 171:3a7713b1edbc | 1189 | #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ |
AnnaBridge | 171:3a7713b1edbc | 1190 | ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ |
AnnaBridge | 171:3a7713b1edbc | 1191 | (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\ |
AnnaBridge | 171:3a7713b1edbc | 1192 | (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\ |
AnnaBridge | 171:3a7713b1edbc | 1193 | (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\ |
AnnaBridge | 171:3a7713b1edbc | 1194 | 0U) |
AnnaBridge | 171:3a7713b1edbc | 1195 | |
AnnaBridge | 171:3a7713b1edbc | 1196 | /** |
AnnaBridge | 171:3a7713b1edbc | 1197 | * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. |
AnnaBridge | 171:3a7713b1edbc | 1198 | * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); |
AnnaBridge | 171:3a7713b1edbc | 1199 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
AnnaBridge | 171:3a7713b1edbc | 1200 | * @param __CNTCLK__ counter clock frequency (in Hz) |
AnnaBridge | 171:3a7713b1edbc | 1201 | * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) |
AnnaBridge | 171:3a7713b1edbc | 1202 | */ |
AnnaBridge | 171:3a7713b1edbc | 1203 | #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ |
AnnaBridge | 171:3a7713b1edbc | 1204 | ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U |
AnnaBridge | 171:3a7713b1edbc | 1205 | |
AnnaBridge | 171:3a7713b1edbc | 1206 | /** |
AnnaBridge | 171:3a7713b1edbc | 1207 | * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. |
AnnaBridge | 171:3a7713b1edbc | 1208 | * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); |
AnnaBridge | 171:3a7713b1edbc | 1209 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
AnnaBridge | 171:3a7713b1edbc | 1210 | * @param __PSC__ prescaler |
AnnaBridge | 171:3a7713b1edbc | 1211 | * @param __FREQ__ output signal frequency (in Hz) |
AnnaBridge | 171:3a7713b1edbc | 1212 | * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) |
AnnaBridge | 171:3a7713b1edbc | 1213 | */ |
AnnaBridge | 171:3a7713b1edbc | 1214 | #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ |
AnnaBridge | 171:3a7713b1edbc | 1215 | (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U |
AnnaBridge | 171:3a7713b1edbc | 1216 | |
AnnaBridge | 171:3a7713b1edbc | 1217 | /** |
AnnaBridge | 171:3a7713b1edbc | 1218 | * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay. |
AnnaBridge | 171:3a7713b1edbc | 1219 | * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); |
AnnaBridge | 171:3a7713b1edbc | 1220 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
AnnaBridge | 171:3a7713b1edbc | 1221 | * @param __PSC__ prescaler |
AnnaBridge | 171:3a7713b1edbc | 1222 | * @param __DELAY__ timer output compare active/inactive delay (in us) |
AnnaBridge | 171:3a7713b1edbc | 1223 | * @retval Compare value (between Min_Data=0 and Max_Data=65535) |
AnnaBridge | 171:3a7713b1edbc | 1224 | */ |
AnnaBridge | 171:3a7713b1edbc | 1225 | #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ |
AnnaBridge | 171:3a7713b1edbc | 1226 | ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ |
AnnaBridge | 171:3a7713b1edbc | 1227 | / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) |
AnnaBridge | 171:3a7713b1edbc | 1228 | |
AnnaBridge | 171:3a7713b1edbc | 1229 | /** |
AnnaBridge | 171:3a7713b1edbc | 1230 | * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode). |
AnnaBridge | 171:3a7713b1edbc | 1231 | * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); |
AnnaBridge | 171:3a7713b1edbc | 1232 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
AnnaBridge | 171:3a7713b1edbc | 1233 | * @param __PSC__ prescaler |
AnnaBridge | 171:3a7713b1edbc | 1234 | * @param __DELAY__ timer output compare active/inactive delay (in us) |
AnnaBridge | 171:3a7713b1edbc | 1235 | * @param __PULSE__ pulse duration (in us) |
AnnaBridge | 171:3a7713b1edbc | 1236 | * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) |
AnnaBridge | 171:3a7713b1edbc | 1237 | */ |
AnnaBridge | 171:3a7713b1edbc | 1238 | #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ |
AnnaBridge | 171:3a7713b1edbc | 1239 | ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ |
AnnaBridge | 171:3a7713b1edbc | 1240 | + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) |
AnnaBridge | 171:3a7713b1edbc | 1241 | |
AnnaBridge | 171:3a7713b1edbc | 1242 | /** |
AnnaBridge | 171:3a7713b1edbc | 1243 | * @brief HELPER macro retrieving the ratio of the input capture prescaler |
AnnaBridge | 171:3a7713b1edbc | 1244 | * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); |
AnnaBridge | 171:3a7713b1edbc | 1245 | * @param __ICPSC__ This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1246 | * @arg @ref LL_TIM_ICPSC_DIV1 |
AnnaBridge | 171:3a7713b1edbc | 1247 | * @arg @ref LL_TIM_ICPSC_DIV2 |
AnnaBridge | 171:3a7713b1edbc | 1248 | * @arg @ref LL_TIM_ICPSC_DIV4 |
AnnaBridge | 171:3a7713b1edbc | 1249 | * @arg @ref LL_TIM_ICPSC_DIV8 |
AnnaBridge | 171:3a7713b1edbc | 1250 | * @retval Input capture prescaler ratio (1, 2, 4 or 8) |
AnnaBridge | 171:3a7713b1edbc | 1251 | */ |
AnnaBridge | 171:3a7713b1edbc | 1252 | #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ |
AnnaBridge | 171:3a7713b1edbc | 1253 | ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 1254 | |
AnnaBridge | 171:3a7713b1edbc | 1255 | |
AnnaBridge | 171:3a7713b1edbc | 1256 | /** |
AnnaBridge | 171:3a7713b1edbc | 1257 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1258 | */ |
AnnaBridge | 171:3a7713b1edbc | 1259 | |
AnnaBridge | 171:3a7713b1edbc | 1260 | |
AnnaBridge | 171:3a7713b1edbc | 1261 | /** |
AnnaBridge | 171:3a7713b1edbc | 1262 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1263 | */ |
AnnaBridge | 171:3a7713b1edbc | 1264 | |
AnnaBridge | 171:3a7713b1edbc | 1265 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 1266 | /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions |
AnnaBridge | 171:3a7713b1edbc | 1267 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1268 | */ |
AnnaBridge | 171:3a7713b1edbc | 1269 | |
AnnaBridge | 171:3a7713b1edbc | 1270 | /** @defgroup TIM_LL_EF_Time_Base Time Base configuration |
AnnaBridge | 171:3a7713b1edbc | 1271 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1272 | */ |
AnnaBridge | 171:3a7713b1edbc | 1273 | /** |
AnnaBridge | 171:3a7713b1edbc | 1274 | * @brief Enable timer counter. |
AnnaBridge | 171:3a7713b1edbc | 1275 | * @rmtoll CR1 CEN LL_TIM_EnableCounter |
AnnaBridge | 171:3a7713b1edbc | 1276 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1277 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1278 | */ |
AnnaBridge | 171:3a7713b1edbc | 1279 | __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 1280 | { |
AnnaBridge | 171:3a7713b1edbc | 1281 | SET_BIT(TIMx->CR1, TIM_CR1_CEN); |
AnnaBridge | 171:3a7713b1edbc | 1282 | } |
AnnaBridge | 171:3a7713b1edbc | 1283 | |
AnnaBridge | 171:3a7713b1edbc | 1284 | /** |
AnnaBridge | 171:3a7713b1edbc | 1285 | * @brief Disable timer counter. |
AnnaBridge | 171:3a7713b1edbc | 1286 | * @rmtoll CR1 CEN LL_TIM_DisableCounter |
AnnaBridge | 171:3a7713b1edbc | 1287 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1288 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1289 | */ |
AnnaBridge | 171:3a7713b1edbc | 1290 | __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 1291 | { |
AnnaBridge | 171:3a7713b1edbc | 1292 | CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); |
AnnaBridge | 171:3a7713b1edbc | 1293 | } |
AnnaBridge | 171:3a7713b1edbc | 1294 | |
AnnaBridge | 171:3a7713b1edbc | 1295 | /** |
AnnaBridge | 171:3a7713b1edbc | 1296 | * @brief Indicates whether the timer counter is enabled. |
AnnaBridge | 171:3a7713b1edbc | 1297 | * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter |
AnnaBridge | 171:3a7713b1edbc | 1298 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1299 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1300 | */ |
AnnaBridge | 171:3a7713b1edbc | 1301 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 1302 | { |
AnnaBridge | 171:3a7713b1edbc | 1303 | return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)); |
AnnaBridge | 171:3a7713b1edbc | 1304 | } |
AnnaBridge | 171:3a7713b1edbc | 1305 | |
AnnaBridge | 171:3a7713b1edbc | 1306 | /** |
AnnaBridge | 171:3a7713b1edbc | 1307 | * @brief Enable update event generation. |
AnnaBridge | 171:3a7713b1edbc | 1308 | * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent |
AnnaBridge | 171:3a7713b1edbc | 1309 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1310 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1311 | */ |
AnnaBridge | 171:3a7713b1edbc | 1312 | __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 1313 | { |
AnnaBridge | 171:3a7713b1edbc | 1314 | CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); |
AnnaBridge | 171:3a7713b1edbc | 1315 | } |
AnnaBridge | 171:3a7713b1edbc | 1316 | |
AnnaBridge | 171:3a7713b1edbc | 1317 | /** |
AnnaBridge | 171:3a7713b1edbc | 1318 | * @brief Disable update event generation. |
AnnaBridge | 171:3a7713b1edbc | 1319 | * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent |
AnnaBridge | 171:3a7713b1edbc | 1320 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1321 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1322 | */ |
AnnaBridge | 171:3a7713b1edbc | 1323 | __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 1324 | { |
AnnaBridge | 171:3a7713b1edbc | 1325 | SET_BIT(TIMx->CR1, TIM_CR1_UDIS); |
AnnaBridge | 171:3a7713b1edbc | 1326 | } |
AnnaBridge | 171:3a7713b1edbc | 1327 | |
AnnaBridge | 171:3a7713b1edbc | 1328 | /** |
AnnaBridge | 171:3a7713b1edbc | 1329 | * @brief Indicates whether update event generation is enabled. |
AnnaBridge | 171:3a7713b1edbc | 1330 | * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent |
AnnaBridge | 171:3a7713b1edbc | 1331 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1332 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1333 | */ |
AnnaBridge | 171:3a7713b1edbc | 1334 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 1335 | { |
AnnaBridge | 171:3a7713b1edbc | 1336 | return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS)); |
AnnaBridge | 171:3a7713b1edbc | 1337 | } |
AnnaBridge | 171:3a7713b1edbc | 1338 | |
AnnaBridge | 171:3a7713b1edbc | 1339 | /** |
AnnaBridge | 171:3a7713b1edbc | 1340 | * @brief Set update event source |
AnnaBridge | 171:3a7713b1edbc | 1341 | * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events |
AnnaBridge | 171:3a7713b1edbc | 1342 | * generate an update interrupt or DMA request if enabled: |
AnnaBridge | 171:3a7713b1edbc | 1343 | * - Counter overflow/underflow |
AnnaBridge | 171:3a7713b1edbc | 1344 | * - Setting the UG bit |
AnnaBridge | 171:3a7713b1edbc | 1345 | * - Update generation through the slave mode controller |
AnnaBridge | 171:3a7713b1edbc | 1346 | * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter |
AnnaBridge | 171:3a7713b1edbc | 1347 | * overflow/underflow generates an update interrupt or DMA request if enabled. |
AnnaBridge | 171:3a7713b1edbc | 1348 | * @rmtoll CR1 URS LL_TIM_SetUpdateSource |
AnnaBridge | 171:3a7713b1edbc | 1349 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1350 | * @param UpdateSource This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1351 | * @arg @ref LL_TIM_UPDATESOURCE_REGULAR |
AnnaBridge | 171:3a7713b1edbc | 1352 | * @arg @ref LL_TIM_UPDATESOURCE_COUNTER |
AnnaBridge | 171:3a7713b1edbc | 1353 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1354 | */ |
AnnaBridge | 171:3a7713b1edbc | 1355 | __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) |
AnnaBridge | 171:3a7713b1edbc | 1356 | { |
AnnaBridge | 171:3a7713b1edbc | 1357 | MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); |
AnnaBridge | 171:3a7713b1edbc | 1358 | } |
AnnaBridge | 171:3a7713b1edbc | 1359 | |
AnnaBridge | 171:3a7713b1edbc | 1360 | /** |
AnnaBridge | 171:3a7713b1edbc | 1361 | * @brief Get actual event update source |
AnnaBridge | 171:3a7713b1edbc | 1362 | * @rmtoll CR1 URS LL_TIM_GetUpdateSource |
AnnaBridge | 171:3a7713b1edbc | 1363 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1364 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1365 | * @arg @ref LL_TIM_UPDATESOURCE_REGULAR |
AnnaBridge | 171:3a7713b1edbc | 1366 | * @arg @ref LL_TIM_UPDATESOURCE_COUNTER |
AnnaBridge | 171:3a7713b1edbc | 1367 | */ |
AnnaBridge | 171:3a7713b1edbc | 1368 | __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 1369 | { |
AnnaBridge | 171:3a7713b1edbc | 1370 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); |
AnnaBridge | 171:3a7713b1edbc | 1371 | } |
AnnaBridge | 171:3a7713b1edbc | 1372 | |
AnnaBridge | 171:3a7713b1edbc | 1373 | /** |
AnnaBridge | 171:3a7713b1edbc | 1374 | * @brief Set one pulse mode (one shot v.s. repetitive). |
AnnaBridge | 171:3a7713b1edbc | 1375 | * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode |
AnnaBridge | 171:3a7713b1edbc | 1376 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1377 | * @param OnePulseMode This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1378 | * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE |
AnnaBridge | 171:3a7713b1edbc | 1379 | * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE |
AnnaBridge | 171:3a7713b1edbc | 1380 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1381 | */ |
AnnaBridge | 171:3a7713b1edbc | 1382 | __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) |
AnnaBridge | 171:3a7713b1edbc | 1383 | { |
AnnaBridge | 171:3a7713b1edbc | 1384 | MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); |
AnnaBridge | 171:3a7713b1edbc | 1385 | } |
AnnaBridge | 171:3a7713b1edbc | 1386 | |
AnnaBridge | 171:3a7713b1edbc | 1387 | /** |
AnnaBridge | 171:3a7713b1edbc | 1388 | * @brief Get actual one pulse mode. |
AnnaBridge | 171:3a7713b1edbc | 1389 | * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode |
AnnaBridge | 171:3a7713b1edbc | 1390 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1391 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1392 | * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE |
AnnaBridge | 171:3a7713b1edbc | 1393 | * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE |
AnnaBridge | 171:3a7713b1edbc | 1394 | */ |
AnnaBridge | 171:3a7713b1edbc | 1395 | __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 1396 | { |
AnnaBridge | 171:3a7713b1edbc | 1397 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); |
AnnaBridge | 171:3a7713b1edbc | 1398 | } |
AnnaBridge | 171:3a7713b1edbc | 1399 | |
AnnaBridge | 171:3a7713b1edbc | 1400 | /** |
AnnaBridge | 171:3a7713b1edbc | 1401 | * @brief Set the timer counter counting mode. |
AnnaBridge | 171:3a7713b1edbc | 1402 | * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to |
AnnaBridge | 171:3a7713b1edbc | 1403 | * check whether or not the counter mode selection feature is supported |
AnnaBridge | 171:3a7713b1edbc | 1404 | * by a timer instance. |
AnnaBridge | 171:3a7713b1edbc | 1405 | * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n |
AnnaBridge | 171:3a7713b1edbc | 1406 | * CR1 CMS LL_TIM_SetCounterMode |
AnnaBridge | 171:3a7713b1edbc | 1407 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1408 | * @param CounterMode This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1409 | * @arg @ref LL_TIM_COUNTERMODE_UP |
AnnaBridge | 171:3a7713b1edbc | 1410 | * @arg @ref LL_TIM_COUNTERMODE_DOWN |
AnnaBridge | 171:3a7713b1edbc | 1411 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP |
AnnaBridge | 171:3a7713b1edbc | 1412 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN |
AnnaBridge | 171:3a7713b1edbc | 1413 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN |
AnnaBridge | 171:3a7713b1edbc | 1414 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1415 | */ |
AnnaBridge | 171:3a7713b1edbc | 1416 | __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) |
AnnaBridge | 171:3a7713b1edbc | 1417 | { |
AnnaBridge | 171:3a7713b1edbc | 1418 | MODIFY_REG(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS, CounterMode); |
AnnaBridge | 171:3a7713b1edbc | 1419 | } |
AnnaBridge | 171:3a7713b1edbc | 1420 | |
AnnaBridge | 171:3a7713b1edbc | 1421 | /** |
AnnaBridge | 171:3a7713b1edbc | 1422 | * @brief Get actual counter mode. |
AnnaBridge | 171:3a7713b1edbc | 1423 | * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to |
AnnaBridge | 171:3a7713b1edbc | 1424 | * check whether or not the counter mode selection feature is supported |
AnnaBridge | 171:3a7713b1edbc | 1425 | * by a timer instance. |
AnnaBridge | 171:3a7713b1edbc | 1426 | * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n |
AnnaBridge | 171:3a7713b1edbc | 1427 | * CR1 CMS LL_TIM_GetCounterMode |
AnnaBridge | 171:3a7713b1edbc | 1428 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1429 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1430 | * @arg @ref LL_TIM_COUNTERMODE_UP |
AnnaBridge | 171:3a7713b1edbc | 1431 | * @arg @ref LL_TIM_COUNTERMODE_DOWN |
AnnaBridge | 171:3a7713b1edbc | 1432 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP |
AnnaBridge | 171:3a7713b1edbc | 1433 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN |
AnnaBridge | 171:3a7713b1edbc | 1434 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN |
AnnaBridge | 171:3a7713b1edbc | 1435 | */ |
AnnaBridge | 171:3a7713b1edbc | 1436 | __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 1437 | { |
AnnaBridge | 171:3a7713b1edbc | 1438 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS)); |
AnnaBridge | 171:3a7713b1edbc | 1439 | } |
AnnaBridge | 171:3a7713b1edbc | 1440 | |
AnnaBridge | 171:3a7713b1edbc | 1441 | /** |
AnnaBridge | 171:3a7713b1edbc | 1442 | * @brief Enable auto-reload (ARR) preload. |
AnnaBridge | 171:3a7713b1edbc | 1443 | * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload |
AnnaBridge | 171:3a7713b1edbc | 1444 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1445 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1446 | */ |
AnnaBridge | 171:3a7713b1edbc | 1447 | __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 1448 | { |
AnnaBridge | 171:3a7713b1edbc | 1449 | SET_BIT(TIMx->CR1, TIM_CR1_ARPE); |
AnnaBridge | 171:3a7713b1edbc | 1450 | } |
AnnaBridge | 171:3a7713b1edbc | 1451 | |
AnnaBridge | 171:3a7713b1edbc | 1452 | /** |
AnnaBridge | 171:3a7713b1edbc | 1453 | * @brief Disable auto-reload (ARR) preload. |
AnnaBridge | 171:3a7713b1edbc | 1454 | * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload |
AnnaBridge | 171:3a7713b1edbc | 1455 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1456 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1457 | */ |
AnnaBridge | 171:3a7713b1edbc | 1458 | __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 1459 | { |
AnnaBridge | 171:3a7713b1edbc | 1460 | CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); |
AnnaBridge | 171:3a7713b1edbc | 1461 | } |
AnnaBridge | 171:3a7713b1edbc | 1462 | |
AnnaBridge | 171:3a7713b1edbc | 1463 | /** |
AnnaBridge | 171:3a7713b1edbc | 1464 | * @brief Indicates whether auto-reload (ARR) preload is enabled. |
AnnaBridge | 171:3a7713b1edbc | 1465 | * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload |
AnnaBridge | 171:3a7713b1edbc | 1466 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1467 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1468 | */ |
AnnaBridge | 171:3a7713b1edbc | 1469 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 1470 | { |
AnnaBridge | 171:3a7713b1edbc | 1471 | return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)); |
AnnaBridge | 171:3a7713b1edbc | 1472 | } |
AnnaBridge | 171:3a7713b1edbc | 1473 | |
AnnaBridge | 171:3a7713b1edbc | 1474 | /** |
AnnaBridge | 171:3a7713b1edbc | 1475 | * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. |
AnnaBridge | 171:3a7713b1edbc | 1476 | * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check |
AnnaBridge | 171:3a7713b1edbc | 1477 | * whether or not the clock division feature is supported by the timer |
AnnaBridge | 171:3a7713b1edbc | 1478 | * instance. |
AnnaBridge | 171:3a7713b1edbc | 1479 | * @rmtoll CR1 CKD LL_TIM_SetClockDivision |
AnnaBridge | 171:3a7713b1edbc | 1480 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1481 | * @param ClockDivision This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1482 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 |
AnnaBridge | 171:3a7713b1edbc | 1483 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 |
AnnaBridge | 171:3a7713b1edbc | 1484 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 |
AnnaBridge | 171:3a7713b1edbc | 1485 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1486 | */ |
AnnaBridge | 171:3a7713b1edbc | 1487 | __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) |
AnnaBridge | 171:3a7713b1edbc | 1488 | { |
AnnaBridge | 171:3a7713b1edbc | 1489 | MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); |
AnnaBridge | 171:3a7713b1edbc | 1490 | } |
AnnaBridge | 171:3a7713b1edbc | 1491 | |
AnnaBridge | 171:3a7713b1edbc | 1492 | /** |
AnnaBridge | 171:3a7713b1edbc | 1493 | * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. |
AnnaBridge | 171:3a7713b1edbc | 1494 | * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check |
AnnaBridge | 171:3a7713b1edbc | 1495 | * whether or not the clock division feature is supported by the timer |
AnnaBridge | 171:3a7713b1edbc | 1496 | * instance. |
AnnaBridge | 171:3a7713b1edbc | 1497 | * @rmtoll CR1 CKD LL_TIM_GetClockDivision |
AnnaBridge | 171:3a7713b1edbc | 1498 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1499 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1500 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 |
AnnaBridge | 171:3a7713b1edbc | 1501 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 |
AnnaBridge | 171:3a7713b1edbc | 1502 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 |
AnnaBridge | 171:3a7713b1edbc | 1503 | */ |
AnnaBridge | 171:3a7713b1edbc | 1504 | __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 1505 | { |
AnnaBridge | 171:3a7713b1edbc | 1506 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); |
AnnaBridge | 171:3a7713b1edbc | 1507 | } |
AnnaBridge | 171:3a7713b1edbc | 1508 | |
AnnaBridge | 171:3a7713b1edbc | 1509 | /** |
AnnaBridge | 171:3a7713b1edbc | 1510 | * @brief Set the counter value. |
AnnaBridge | 171:3a7713b1edbc | 1511 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
AnnaBridge | 171:3a7713b1edbc | 1512 | * whether or not a timer instance supports a 32 bits counter. |
AnnaBridge | 171:3a7713b1edbc | 1513 | * @rmtoll CNT CNT LL_TIM_SetCounter |
AnnaBridge | 171:3a7713b1edbc | 1514 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1515 | * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) |
AnnaBridge | 171:3a7713b1edbc | 1516 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1517 | */ |
AnnaBridge | 171:3a7713b1edbc | 1518 | __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) |
AnnaBridge | 171:3a7713b1edbc | 1519 | { |
AnnaBridge | 171:3a7713b1edbc | 1520 | WRITE_REG(TIMx->CNT, Counter); |
AnnaBridge | 171:3a7713b1edbc | 1521 | } |
AnnaBridge | 171:3a7713b1edbc | 1522 | |
AnnaBridge | 171:3a7713b1edbc | 1523 | /** |
AnnaBridge | 171:3a7713b1edbc | 1524 | * @brief Get the counter value. |
AnnaBridge | 171:3a7713b1edbc | 1525 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
AnnaBridge | 171:3a7713b1edbc | 1526 | * whether or not a timer instance supports a 32 bits counter. |
AnnaBridge | 171:3a7713b1edbc | 1527 | * @rmtoll CNT CNT LL_TIM_GetCounter |
AnnaBridge | 171:3a7713b1edbc | 1528 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1529 | * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) |
AnnaBridge | 171:3a7713b1edbc | 1530 | */ |
AnnaBridge | 171:3a7713b1edbc | 1531 | __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 1532 | { |
AnnaBridge | 171:3a7713b1edbc | 1533 | return (uint32_t)(READ_REG(TIMx->CNT)); |
AnnaBridge | 171:3a7713b1edbc | 1534 | } |
AnnaBridge | 171:3a7713b1edbc | 1535 | |
AnnaBridge | 171:3a7713b1edbc | 1536 | /** |
AnnaBridge | 171:3a7713b1edbc | 1537 | * @brief Get the current direction of the counter |
AnnaBridge | 171:3a7713b1edbc | 1538 | * @rmtoll CR1 DIR LL_TIM_GetDirection |
AnnaBridge | 171:3a7713b1edbc | 1539 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1540 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1541 | * @arg @ref LL_TIM_COUNTERDIRECTION_UP |
AnnaBridge | 171:3a7713b1edbc | 1542 | * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN |
AnnaBridge | 171:3a7713b1edbc | 1543 | */ |
AnnaBridge | 171:3a7713b1edbc | 1544 | __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 1545 | { |
AnnaBridge | 171:3a7713b1edbc | 1546 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); |
AnnaBridge | 171:3a7713b1edbc | 1547 | } |
AnnaBridge | 171:3a7713b1edbc | 1548 | |
AnnaBridge | 171:3a7713b1edbc | 1549 | /** |
AnnaBridge | 171:3a7713b1edbc | 1550 | * @brief Set the prescaler value. |
AnnaBridge | 171:3a7713b1edbc | 1551 | * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). |
AnnaBridge | 171:3a7713b1edbc | 1552 | * @note The prescaler can be changed on the fly as this control register is buffered. The new |
AnnaBridge | 171:3a7713b1edbc | 1553 | * prescaler ratio is taken into account at the next update event. |
AnnaBridge | 171:3a7713b1edbc | 1554 | * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter |
AnnaBridge | 171:3a7713b1edbc | 1555 | * @rmtoll PSC PSC LL_TIM_SetPrescaler |
AnnaBridge | 171:3a7713b1edbc | 1556 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1557 | * @param Prescaler between Min_Data=0 and Max_Data=65535 |
AnnaBridge | 171:3a7713b1edbc | 1558 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1559 | */ |
AnnaBridge | 171:3a7713b1edbc | 1560 | __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) |
AnnaBridge | 171:3a7713b1edbc | 1561 | { |
AnnaBridge | 171:3a7713b1edbc | 1562 | WRITE_REG(TIMx->PSC, Prescaler); |
AnnaBridge | 171:3a7713b1edbc | 1563 | } |
AnnaBridge | 171:3a7713b1edbc | 1564 | |
AnnaBridge | 171:3a7713b1edbc | 1565 | /** |
AnnaBridge | 171:3a7713b1edbc | 1566 | * @brief Get the prescaler value. |
AnnaBridge | 171:3a7713b1edbc | 1567 | * @rmtoll PSC PSC LL_TIM_GetPrescaler |
AnnaBridge | 171:3a7713b1edbc | 1568 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1569 | * @retval Prescaler value between Min_Data=0 and Max_Data=65535 |
AnnaBridge | 171:3a7713b1edbc | 1570 | */ |
AnnaBridge | 171:3a7713b1edbc | 1571 | __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 1572 | { |
AnnaBridge | 171:3a7713b1edbc | 1573 | return (uint32_t)(READ_REG(TIMx->PSC)); |
AnnaBridge | 171:3a7713b1edbc | 1574 | } |
AnnaBridge | 171:3a7713b1edbc | 1575 | |
AnnaBridge | 171:3a7713b1edbc | 1576 | /** |
AnnaBridge | 171:3a7713b1edbc | 1577 | * @brief Set the auto-reload value. |
AnnaBridge | 171:3a7713b1edbc | 1578 | * @note The counter is blocked while the auto-reload value is null. |
AnnaBridge | 171:3a7713b1edbc | 1579 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
AnnaBridge | 171:3a7713b1edbc | 1580 | * whether or not a timer instance supports a 32 bits counter. |
AnnaBridge | 171:3a7713b1edbc | 1581 | * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter |
AnnaBridge | 171:3a7713b1edbc | 1582 | * @rmtoll ARR ARR LL_TIM_SetAutoReload |
AnnaBridge | 171:3a7713b1edbc | 1583 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1584 | * @param AutoReload between Min_Data=0 and Max_Data=65535 |
AnnaBridge | 171:3a7713b1edbc | 1585 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1586 | */ |
AnnaBridge | 171:3a7713b1edbc | 1587 | __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) |
AnnaBridge | 171:3a7713b1edbc | 1588 | { |
AnnaBridge | 171:3a7713b1edbc | 1589 | WRITE_REG(TIMx->ARR, AutoReload); |
AnnaBridge | 171:3a7713b1edbc | 1590 | } |
AnnaBridge | 171:3a7713b1edbc | 1591 | |
AnnaBridge | 171:3a7713b1edbc | 1592 | /** |
AnnaBridge | 171:3a7713b1edbc | 1593 | * @brief Get the auto-reload value. |
AnnaBridge | 171:3a7713b1edbc | 1594 | * @rmtoll ARR ARR LL_TIM_GetAutoReload |
AnnaBridge | 171:3a7713b1edbc | 1595 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
AnnaBridge | 171:3a7713b1edbc | 1596 | * whether or not a timer instance supports a 32 bits counter. |
AnnaBridge | 171:3a7713b1edbc | 1597 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1598 | * @retval Auto-reload value |
AnnaBridge | 171:3a7713b1edbc | 1599 | */ |
AnnaBridge | 171:3a7713b1edbc | 1600 | __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 1601 | { |
AnnaBridge | 171:3a7713b1edbc | 1602 | return (uint32_t)(READ_REG(TIMx->ARR)); |
AnnaBridge | 171:3a7713b1edbc | 1603 | } |
AnnaBridge | 171:3a7713b1edbc | 1604 | |
AnnaBridge | 171:3a7713b1edbc | 1605 | /** |
AnnaBridge | 171:3a7713b1edbc | 1606 | * @brief Set the repetition counter value. |
AnnaBridge | 171:3a7713b1edbc | 1607 | * @note For advanced timer instances RepetitionCounter can be up to 65535. |
AnnaBridge | 171:3a7713b1edbc | 1608 | * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check |
AnnaBridge | 171:3a7713b1edbc | 1609 | * whether or not a timer instance supports a repetition counter. |
AnnaBridge | 171:3a7713b1edbc | 1610 | * @rmtoll RCR REP LL_TIM_SetRepetitionCounter |
AnnaBridge | 171:3a7713b1edbc | 1611 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1612 | * @param RepetitionCounter between Min_Data=0 and Max_Data=255 |
AnnaBridge | 171:3a7713b1edbc | 1613 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1614 | */ |
AnnaBridge | 171:3a7713b1edbc | 1615 | __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) |
AnnaBridge | 171:3a7713b1edbc | 1616 | { |
AnnaBridge | 171:3a7713b1edbc | 1617 | WRITE_REG(TIMx->RCR, RepetitionCounter); |
AnnaBridge | 171:3a7713b1edbc | 1618 | } |
AnnaBridge | 171:3a7713b1edbc | 1619 | |
AnnaBridge | 171:3a7713b1edbc | 1620 | /** |
AnnaBridge | 171:3a7713b1edbc | 1621 | * @brief Get the repetition counter value. |
AnnaBridge | 171:3a7713b1edbc | 1622 | * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check |
AnnaBridge | 171:3a7713b1edbc | 1623 | * whether or not a timer instance supports a repetition counter. |
AnnaBridge | 171:3a7713b1edbc | 1624 | * @rmtoll RCR REP LL_TIM_GetRepetitionCounter |
AnnaBridge | 171:3a7713b1edbc | 1625 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1626 | * @retval Repetition counter value |
AnnaBridge | 171:3a7713b1edbc | 1627 | */ |
AnnaBridge | 171:3a7713b1edbc | 1628 | __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 1629 | { |
AnnaBridge | 171:3a7713b1edbc | 1630 | return (uint32_t)(READ_REG(TIMx->RCR)); |
AnnaBridge | 171:3a7713b1edbc | 1631 | } |
AnnaBridge | 171:3a7713b1edbc | 1632 | |
AnnaBridge | 171:3a7713b1edbc | 1633 | /** |
AnnaBridge | 171:3a7713b1edbc | 1634 | * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). |
AnnaBridge | 171:3a7713b1edbc | 1635 | * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way. |
AnnaBridge | 171:3a7713b1edbc | 1636 | * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap |
AnnaBridge | 171:3a7713b1edbc | 1637 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1638 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1639 | */ |
AnnaBridge | 171:3a7713b1edbc | 1640 | __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 1641 | { |
AnnaBridge | 171:3a7713b1edbc | 1642 | SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); |
AnnaBridge | 171:3a7713b1edbc | 1643 | } |
AnnaBridge | 171:3a7713b1edbc | 1644 | |
AnnaBridge | 171:3a7713b1edbc | 1645 | /** |
AnnaBridge | 171:3a7713b1edbc | 1646 | * @brief Disable update interrupt flag (UIF) remapping. |
AnnaBridge | 171:3a7713b1edbc | 1647 | * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap |
AnnaBridge | 171:3a7713b1edbc | 1648 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1649 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1650 | */ |
AnnaBridge | 171:3a7713b1edbc | 1651 | __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 1652 | { |
AnnaBridge | 171:3a7713b1edbc | 1653 | CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); |
AnnaBridge | 171:3a7713b1edbc | 1654 | } |
AnnaBridge | 171:3a7713b1edbc | 1655 | |
AnnaBridge | 171:3a7713b1edbc | 1656 | /** |
AnnaBridge | 171:3a7713b1edbc | 1657 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1658 | */ |
AnnaBridge | 171:3a7713b1edbc | 1659 | |
AnnaBridge | 171:3a7713b1edbc | 1660 | /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration |
AnnaBridge | 171:3a7713b1edbc | 1661 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1662 | */ |
AnnaBridge | 171:3a7713b1edbc | 1663 | /** |
AnnaBridge | 171:3a7713b1edbc | 1664 | * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. |
AnnaBridge | 171:3a7713b1edbc | 1665 | * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, |
AnnaBridge | 171:3a7713b1edbc | 1666 | * they are updated only when a commutation event (COM) occurs. |
AnnaBridge | 171:3a7713b1edbc | 1667 | * @note Only on channels that have a complementary output. |
AnnaBridge | 171:3a7713b1edbc | 1668 | * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check |
AnnaBridge | 171:3a7713b1edbc | 1669 | * whether or not a timer instance is able to generate a commutation event. |
AnnaBridge | 171:3a7713b1edbc | 1670 | * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload |
AnnaBridge | 171:3a7713b1edbc | 1671 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1672 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1673 | */ |
AnnaBridge | 171:3a7713b1edbc | 1674 | __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 1675 | { |
AnnaBridge | 171:3a7713b1edbc | 1676 | SET_BIT(TIMx->CR2, TIM_CR2_CCPC); |
AnnaBridge | 171:3a7713b1edbc | 1677 | } |
AnnaBridge | 171:3a7713b1edbc | 1678 | |
AnnaBridge | 171:3a7713b1edbc | 1679 | /** |
AnnaBridge | 171:3a7713b1edbc | 1680 | * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. |
AnnaBridge | 171:3a7713b1edbc | 1681 | * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check |
AnnaBridge | 171:3a7713b1edbc | 1682 | * whether or not a timer instance is able to generate a commutation event. |
AnnaBridge | 171:3a7713b1edbc | 1683 | * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload |
AnnaBridge | 171:3a7713b1edbc | 1684 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1685 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1686 | */ |
AnnaBridge | 171:3a7713b1edbc | 1687 | __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 1688 | { |
AnnaBridge | 171:3a7713b1edbc | 1689 | CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); |
AnnaBridge | 171:3a7713b1edbc | 1690 | } |
AnnaBridge | 171:3a7713b1edbc | 1691 | |
AnnaBridge | 171:3a7713b1edbc | 1692 | /** |
AnnaBridge | 171:3a7713b1edbc | 1693 | * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). |
AnnaBridge | 171:3a7713b1edbc | 1694 | * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check |
AnnaBridge | 171:3a7713b1edbc | 1695 | * whether or not a timer instance is able to generate a commutation event. |
AnnaBridge | 171:3a7713b1edbc | 1696 | * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate |
AnnaBridge | 171:3a7713b1edbc | 1697 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1698 | * @param CCUpdateSource This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1699 | * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY |
AnnaBridge | 171:3a7713b1edbc | 1700 | * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI |
AnnaBridge | 171:3a7713b1edbc | 1701 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1702 | */ |
AnnaBridge | 171:3a7713b1edbc | 1703 | __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) |
AnnaBridge | 171:3a7713b1edbc | 1704 | { |
AnnaBridge | 171:3a7713b1edbc | 1705 | MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); |
AnnaBridge | 171:3a7713b1edbc | 1706 | } |
AnnaBridge | 171:3a7713b1edbc | 1707 | |
AnnaBridge | 171:3a7713b1edbc | 1708 | /** |
AnnaBridge | 171:3a7713b1edbc | 1709 | * @brief Set the trigger of the capture/compare DMA request. |
AnnaBridge | 171:3a7713b1edbc | 1710 | * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger |
AnnaBridge | 171:3a7713b1edbc | 1711 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1712 | * @param DMAReqTrigger This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1713 | * @arg @ref LL_TIM_CCDMAREQUEST_CC |
AnnaBridge | 171:3a7713b1edbc | 1714 | * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE |
AnnaBridge | 171:3a7713b1edbc | 1715 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1716 | */ |
AnnaBridge | 171:3a7713b1edbc | 1717 | __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) |
AnnaBridge | 171:3a7713b1edbc | 1718 | { |
AnnaBridge | 171:3a7713b1edbc | 1719 | MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); |
AnnaBridge | 171:3a7713b1edbc | 1720 | } |
AnnaBridge | 171:3a7713b1edbc | 1721 | |
AnnaBridge | 171:3a7713b1edbc | 1722 | /** |
AnnaBridge | 171:3a7713b1edbc | 1723 | * @brief Get actual trigger of the capture/compare DMA request. |
AnnaBridge | 171:3a7713b1edbc | 1724 | * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger |
AnnaBridge | 171:3a7713b1edbc | 1725 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1726 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1727 | * @arg @ref LL_TIM_CCDMAREQUEST_CC |
AnnaBridge | 171:3a7713b1edbc | 1728 | * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE |
AnnaBridge | 171:3a7713b1edbc | 1729 | */ |
AnnaBridge | 171:3a7713b1edbc | 1730 | __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 1731 | { |
AnnaBridge | 171:3a7713b1edbc | 1732 | return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); |
AnnaBridge | 171:3a7713b1edbc | 1733 | } |
AnnaBridge | 171:3a7713b1edbc | 1734 | |
AnnaBridge | 171:3a7713b1edbc | 1735 | /** |
AnnaBridge | 171:3a7713b1edbc | 1736 | * @brief Set the lock level to freeze the |
AnnaBridge | 171:3a7713b1edbc | 1737 | * configuration of several capture/compare parameters. |
AnnaBridge | 171:3a7713b1edbc | 1738 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 1739 | * the lock mechanism is supported by a timer instance. |
AnnaBridge | 171:3a7713b1edbc | 1740 | * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel |
AnnaBridge | 171:3a7713b1edbc | 1741 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1742 | * @param LockLevel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1743 | * @arg @ref LL_TIM_LOCKLEVEL_OFF |
AnnaBridge | 171:3a7713b1edbc | 1744 | * @arg @ref LL_TIM_LOCKLEVEL_1 |
AnnaBridge | 171:3a7713b1edbc | 1745 | * @arg @ref LL_TIM_LOCKLEVEL_2 |
AnnaBridge | 171:3a7713b1edbc | 1746 | * @arg @ref LL_TIM_LOCKLEVEL_3 |
AnnaBridge | 171:3a7713b1edbc | 1747 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1748 | */ |
AnnaBridge | 171:3a7713b1edbc | 1749 | __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) |
AnnaBridge | 171:3a7713b1edbc | 1750 | { |
AnnaBridge | 171:3a7713b1edbc | 1751 | MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); |
AnnaBridge | 171:3a7713b1edbc | 1752 | } |
AnnaBridge | 171:3a7713b1edbc | 1753 | |
AnnaBridge | 171:3a7713b1edbc | 1754 | /** |
AnnaBridge | 171:3a7713b1edbc | 1755 | * @brief Enable capture/compare channels. |
AnnaBridge | 171:3a7713b1edbc | 1756 | * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n |
AnnaBridge | 171:3a7713b1edbc | 1757 | * CCER CC1NE LL_TIM_CC_EnableChannel\n |
AnnaBridge | 171:3a7713b1edbc | 1758 | * CCER CC2E LL_TIM_CC_EnableChannel\n |
AnnaBridge | 171:3a7713b1edbc | 1759 | * CCER CC2NE LL_TIM_CC_EnableChannel\n |
AnnaBridge | 171:3a7713b1edbc | 1760 | * CCER CC3E LL_TIM_CC_EnableChannel\n |
AnnaBridge | 171:3a7713b1edbc | 1761 | * CCER CC3NE LL_TIM_CC_EnableChannel\n |
AnnaBridge | 171:3a7713b1edbc | 1762 | * CCER CC4E LL_TIM_CC_EnableChannel\n |
AnnaBridge | 171:3a7713b1edbc | 1763 | * CCER CC5E LL_TIM_CC_EnableChannel\n |
AnnaBridge | 171:3a7713b1edbc | 1764 | * CCER CC6E LL_TIM_CC_EnableChannel |
AnnaBridge | 171:3a7713b1edbc | 1765 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1766 | * @param Channels This parameter can be a combination of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1767 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 171:3a7713b1edbc | 1768 | * @arg @ref LL_TIM_CHANNEL_CH1N |
AnnaBridge | 171:3a7713b1edbc | 1769 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 171:3a7713b1edbc | 1770 | * @arg @ref LL_TIM_CHANNEL_CH2N |
AnnaBridge | 171:3a7713b1edbc | 1771 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 171:3a7713b1edbc | 1772 | * @arg @ref LL_TIM_CHANNEL_CH3N |
AnnaBridge | 171:3a7713b1edbc | 1773 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 171:3a7713b1edbc | 1774 | * @arg @ref LL_TIM_CHANNEL_CH5 |
AnnaBridge | 171:3a7713b1edbc | 1775 | * @arg @ref LL_TIM_CHANNEL_CH6 |
AnnaBridge | 171:3a7713b1edbc | 1776 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1777 | */ |
AnnaBridge | 171:3a7713b1edbc | 1778 | __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) |
AnnaBridge | 171:3a7713b1edbc | 1779 | { |
AnnaBridge | 171:3a7713b1edbc | 1780 | SET_BIT(TIMx->CCER, Channels); |
AnnaBridge | 171:3a7713b1edbc | 1781 | } |
AnnaBridge | 171:3a7713b1edbc | 1782 | |
AnnaBridge | 171:3a7713b1edbc | 1783 | /** |
AnnaBridge | 171:3a7713b1edbc | 1784 | * @brief Disable capture/compare channels. |
AnnaBridge | 171:3a7713b1edbc | 1785 | * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n |
AnnaBridge | 171:3a7713b1edbc | 1786 | * CCER CC1NE LL_TIM_CC_DisableChannel\n |
AnnaBridge | 171:3a7713b1edbc | 1787 | * CCER CC2E LL_TIM_CC_DisableChannel\n |
AnnaBridge | 171:3a7713b1edbc | 1788 | * CCER CC2NE LL_TIM_CC_DisableChannel\n |
AnnaBridge | 171:3a7713b1edbc | 1789 | * CCER CC3E LL_TIM_CC_DisableChannel\n |
AnnaBridge | 171:3a7713b1edbc | 1790 | * CCER CC3NE LL_TIM_CC_DisableChannel\n |
AnnaBridge | 171:3a7713b1edbc | 1791 | * CCER CC4E LL_TIM_CC_DisableChannel\n |
AnnaBridge | 171:3a7713b1edbc | 1792 | * CCER CC5E LL_TIM_CC_DisableChannel\n |
AnnaBridge | 171:3a7713b1edbc | 1793 | * CCER CC6E LL_TIM_CC_DisableChannel |
AnnaBridge | 171:3a7713b1edbc | 1794 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1795 | * @param Channels This parameter can be a combination of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1796 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 171:3a7713b1edbc | 1797 | * @arg @ref LL_TIM_CHANNEL_CH1N |
AnnaBridge | 171:3a7713b1edbc | 1798 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 171:3a7713b1edbc | 1799 | * @arg @ref LL_TIM_CHANNEL_CH2N |
AnnaBridge | 171:3a7713b1edbc | 1800 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 171:3a7713b1edbc | 1801 | * @arg @ref LL_TIM_CHANNEL_CH3N |
AnnaBridge | 171:3a7713b1edbc | 1802 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 171:3a7713b1edbc | 1803 | * @arg @ref LL_TIM_CHANNEL_CH5 |
AnnaBridge | 171:3a7713b1edbc | 1804 | * @arg @ref LL_TIM_CHANNEL_CH6 |
AnnaBridge | 171:3a7713b1edbc | 1805 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1806 | */ |
AnnaBridge | 171:3a7713b1edbc | 1807 | __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) |
AnnaBridge | 171:3a7713b1edbc | 1808 | { |
AnnaBridge | 171:3a7713b1edbc | 1809 | CLEAR_BIT(TIMx->CCER, Channels); |
AnnaBridge | 171:3a7713b1edbc | 1810 | } |
AnnaBridge | 171:3a7713b1edbc | 1811 | |
AnnaBridge | 171:3a7713b1edbc | 1812 | /** |
AnnaBridge | 171:3a7713b1edbc | 1813 | * @brief Indicate whether channel(s) is(are) enabled. |
AnnaBridge | 171:3a7713b1edbc | 1814 | * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n |
AnnaBridge | 171:3a7713b1edbc | 1815 | * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n |
AnnaBridge | 171:3a7713b1edbc | 1816 | * CCER CC2E LL_TIM_CC_IsEnabledChannel\n |
AnnaBridge | 171:3a7713b1edbc | 1817 | * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n |
AnnaBridge | 171:3a7713b1edbc | 1818 | * CCER CC3E LL_TIM_CC_IsEnabledChannel\n |
AnnaBridge | 171:3a7713b1edbc | 1819 | * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n |
AnnaBridge | 171:3a7713b1edbc | 1820 | * CCER CC4E LL_TIM_CC_IsEnabledChannel\n |
AnnaBridge | 171:3a7713b1edbc | 1821 | * CCER CC5E LL_TIM_CC_IsEnabledChannel\n |
AnnaBridge | 171:3a7713b1edbc | 1822 | * CCER CC6E LL_TIM_CC_IsEnabledChannel |
AnnaBridge | 171:3a7713b1edbc | 1823 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1824 | * @param Channels This parameter can be a combination of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1825 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 171:3a7713b1edbc | 1826 | * @arg @ref LL_TIM_CHANNEL_CH1N |
AnnaBridge | 171:3a7713b1edbc | 1827 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 171:3a7713b1edbc | 1828 | * @arg @ref LL_TIM_CHANNEL_CH2N |
AnnaBridge | 171:3a7713b1edbc | 1829 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 171:3a7713b1edbc | 1830 | * @arg @ref LL_TIM_CHANNEL_CH3N |
AnnaBridge | 171:3a7713b1edbc | 1831 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 171:3a7713b1edbc | 1832 | * @arg @ref LL_TIM_CHANNEL_CH5 |
AnnaBridge | 171:3a7713b1edbc | 1833 | * @arg @ref LL_TIM_CHANNEL_CH6 |
AnnaBridge | 171:3a7713b1edbc | 1834 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 1835 | */ |
AnnaBridge | 171:3a7713b1edbc | 1836 | __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels) |
AnnaBridge | 171:3a7713b1edbc | 1837 | { |
AnnaBridge | 171:3a7713b1edbc | 1838 | return (READ_BIT(TIMx->CCER, Channels) == (Channels)); |
AnnaBridge | 171:3a7713b1edbc | 1839 | } |
AnnaBridge | 171:3a7713b1edbc | 1840 | |
AnnaBridge | 171:3a7713b1edbc | 1841 | /** |
AnnaBridge | 171:3a7713b1edbc | 1842 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1843 | */ |
AnnaBridge | 171:3a7713b1edbc | 1844 | |
AnnaBridge | 171:3a7713b1edbc | 1845 | /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration |
AnnaBridge | 171:3a7713b1edbc | 1846 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1847 | */ |
AnnaBridge | 171:3a7713b1edbc | 1848 | /** |
AnnaBridge | 171:3a7713b1edbc | 1849 | * @brief Configure an output channel. |
AnnaBridge | 171:3a7713b1edbc | 1850 | * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n |
AnnaBridge | 171:3a7713b1edbc | 1851 | * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n |
AnnaBridge | 171:3a7713b1edbc | 1852 | * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n |
AnnaBridge | 171:3a7713b1edbc | 1853 | * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n |
AnnaBridge | 171:3a7713b1edbc | 1854 | * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n |
AnnaBridge | 171:3a7713b1edbc | 1855 | * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n |
AnnaBridge | 171:3a7713b1edbc | 1856 | * CCER CC1P LL_TIM_OC_ConfigOutput\n |
AnnaBridge | 171:3a7713b1edbc | 1857 | * CCER CC2P LL_TIM_OC_ConfigOutput\n |
AnnaBridge | 171:3a7713b1edbc | 1858 | * CCER CC3P LL_TIM_OC_ConfigOutput\n |
AnnaBridge | 171:3a7713b1edbc | 1859 | * CCER CC4P LL_TIM_OC_ConfigOutput\n |
AnnaBridge | 171:3a7713b1edbc | 1860 | * CCER CC5P LL_TIM_OC_ConfigOutput\n |
AnnaBridge | 171:3a7713b1edbc | 1861 | * CCER CC6P LL_TIM_OC_ConfigOutput\n |
AnnaBridge | 171:3a7713b1edbc | 1862 | * CR2 OIS1 LL_TIM_OC_ConfigOutput\n |
AnnaBridge | 171:3a7713b1edbc | 1863 | * CR2 OIS2 LL_TIM_OC_ConfigOutput\n |
AnnaBridge | 171:3a7713b1edbc | 1864 | * CR2 OIS3 LL_TIM_OC_ConfigOutput\n |
AnnaBridge | 171:3a7713b1edbc | 1865 | * CR2 OIS4 LL_TIM_OC_ConfigOutput\n |
AnnaBridge | 171:3a7713b1edbc | 1866 | * CR2 OIS5 LL_TIM_OC_ConfigOutput\n |
AnnaBridge | 171:3a7713b1edbc | 1867 | * CR2 OIS6 LL_TIM_OC_ConfigOutput |
AnnaBridge | 171:3a7713b1edbc | 1868 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1869 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1870 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 171:3a7713b1edbc | 1871 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 171:3a7713b1edbc | 1872 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 171:3a7713b1edbc | 1873 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 171:3a7713b1edbc | 1874 | * @arg @ref LL_TIM_CHANNEL_CH5 |
AnnaBridge | 171:3a7713b1edbc | 1875 | * @arg @ref LL_TIM_CHANNEL_CH6 |
AnnaBridge | 171:3a7713b1edbc | 1876 | * @param Configuration This parameter must be a combination of all the following values: |
AnnaBridge | 171:3a7713b1edbc | 1877 | * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW |
AnnaBridge | 171:3a7713b1edbc | 1878 | * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH |
AnnaBridge | 171:3a7713b1edbc | 1879 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1880 | */ |
AnnaBridge | 171:3a7713b1edbc | 1881 | __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) |
AnnaBridge | 171:3a7713b1edbc | 1882 | { |
AnnaBridge | 171:3a7713b1edbc | 1883 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 171:3a7713b1edbc | 1884 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 171:3a7713b1edbc | 1885 | CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); |
AnnaBridge | 171:3a7713b1edbc | 1886 | MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), |
AnnaBridge | 171:3a7713b1edbc | 1887 | (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); |
AnnaBridge | 171:3a7713b1edbc | 1888 | MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), |
AnnaBridge | 171:3a7713b1edbc | 1889 | (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); |
AnnaBridge | 171:3a7713b1edbc | 1890 | } |
AnnaBridge | 171:3a7713b1edbc | 1891 | |
AnnaBridge | 171:3a7713b1edbc | 1892 | /** |
AnnaBridge | 171:3a7713b1edbc | 1893 | * @brief Define the behavior of the output reference signal OCxREF from which |
AnnaBridge | 171:3a7713b1edbc | 1894 | * OCx and OCxN (when relevant) are derived. |
AnnaBridge | 171:3a7713b1edbc | 1895 | * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n |
AnnaBridge | 171:3a7713b1edbc | 1896 | * CCMR1 OC2M LL_TIM_OC_SetMode\n |
AnnaBridge | 171:3a7713b1edbc | 1897 | * CCMR2 OC3M LL_TIM_OC_SetMode\n |
AnnaBridge | 171:3a7713b1edbc | 1898 | * CCMR2 OC4M LL_TIM_OC_SetMode\n |
AnnaBridge | 171:3a7713b1edbc | 1899 | * CCMR3 OC5M LL_TIM_OC_SetMode\n |
AnnaBridge | 171:3a7713b1edbc | 1900 | * CCMR3 OC6M LL_TIM_OC_SetMode |
AnnaBridge | 171:3a7713b1edbc | 1901 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1902 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1903 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 171:3a7713b1edbc | 1904 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 171:3a7713b1edbc | 1905 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 171:3a7713b1edbc | 1906 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 171:3a7713b1edbc | 1907 | * @arg @ref LL_TIM_CHANNEL_CH5 |
AnnaBridge | 171:3a7713b1edbc | 1908 | * @arg @ref LL_TIM_CHANNEL_CH6 |
AnnaBridge | 171:3a7713b1edbc | 1909 | * @param Mode This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1910 | * @arg @ref LL_TIM_OCMODE_FROZEN |
AnnaBridge | 171:3a7713b1edbc | 1911 | * @arg @ref LL_TIM_OCMODE_ACTIVE |
AnnaBridge | 171:3a7713b1edbc | 1912 | * @arg @ref LL_TIM_OCMODE_INACTIVE |
AnnaBridge | 171:3a7713b1edbc | 1913 | * @arg @ref LL_TIM_OCMODE_TOGGLE |
AnnaBridge | 171:3a7713b1edbc | 1914 | * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE |
AnnaBridge | 171:3a7713b1edbc | 1915 | * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE |
AnnaBridge | 171:3a7713b1edbc | 1916 | * @arg @ref LL_TIM_OCMODE_PWM1 |
AnnaBridge | 171:3a7713b1edbc | 1917 | * @arg @ref LL_TIM_OCMODE_PWM2 |
AnnaBridge | 171:3a7713b1edbc | 1918 | * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 |
AnnaBridge | 171:3a7713b1edbc | 1919 | * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 |
AnnaBridge | 171:3a7713b1edbc | 1920 | * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 |
AnnaBridge | 171:3a7713b1edbc | 1921 | * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 |
AnnaBridge | 171:3a7713b1edbc | 1922 | * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 |
AnnaBridge | 171:3a7713b1edbc | 1923 | * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 |
AnnaBridge | 171:3a7713b1edbc | 1924 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1925 | */ |
AnnaBridge | 171:3a7713b1edbc | 1926 | __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) |
AnnaBridge | 171:3a7713b1edbc | 1927 | { |
AnnaBridge | 171:3a7713b1edbc | 1928 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 171:3a7713b1edbc | 1929 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 171:3a7713b1edbc | 1930 | MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); |
AnnaBridge | 171:3a7713b1edbc | 1931 | } |
AnnaBridge | 171:3a7713b1edbc | 1932 | |
AnnaBridge | 171:3a7713b1edbc | 1933 | /** |
AnnaBridge | 171:3a7713b1edbc | 1934 | * @brief Get the output compare mode of an output channel. |
AnnaBridge | 171:3a7713b1edbc | 1935 | * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n |
AnnaBridge | 171:3a7713b1edbc | 1936 | * CCMR1 OC2M LL_TIM_OC_GetMode\n |
AnnaBridge | 171:3a7713b1edbc | 1937 | * CCMR2 OC3M LL_TIM_OC_GetMode\n |
AnnaBridge | 171:3a7713b1edbc | 1938 | * CCMR2 OC4M LL_TIM_OC_GetMode\n |
AnnaBridge | 171:3a7713b1edbc | 1939 | * CCMR3 OC5M LL_TIM_OC_GetMode\n |
AnnaBridge | 171:3a7713b1edbc | 1940 | * CCMR3 OC6M LL_TIM_OC_GetMode |
AnnaBridge | 171:3a7713b1edbc | 1941 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1942 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1943 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 171:3a7713b1edbc | 1944 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 171:3a7713b1edbc | 1945 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 171:3a7713b1edbc | 1946 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 171:3a7713b1edbc | 1947 | * @arg @ref LL_TIM_CHANNEL_CH5 |
AnnaBridge | 171:3a7713b1edbc | 1948 | * @arg @ref LL_TIM_CHANNEL_CH6 |
AnnaBridge | 171:3a7713b1edbc | 1949 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1950 | * @arg @ref LL_TIM_OCMODE_FROZEN |
AnnaBridge | 171:3a7713b1edbc | 1951 | * @arg @ref LL_TIM_OCMODE_ACTIVE |
AnnaBridge | 171:3a7713b1edbc | 1952 | * @arg @ref LL_TIM_OCMODE_INACTIVE |
AnnaBridge | 171:3a7713b1edbc | 1953 | * @arg @ref LL_TIM_OCMODE_TOGGLE |
AnnaBridge | 171:3a7713b1edbc | 1954 | * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE |
AnnaBridge | 171:3a7713b1edbc | 1955 | * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE |
AnnaBridge | 171:3a7713b1edbc | 1956 | * @arg @ref LL_TIM_OCMODE_PWM1 |
AnnaBridge | 171:3a7713b1edbc | 1957 | * @arg @ref LL_TIM_OCMODE_PWM2 |
AnnaBridge | 171:3a7713b1edbc | 1958 | * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 |
AnnaBridge | 171:3a7713b1edbc | 1959 | * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 |
AnnaBridge | 171:3a7713b1edbc | 1960 | * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 |
AnnaBridge | 171:3a7713b1edbc | 1961 | * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 |
AnnaBridge | 171:3a7713b1edbc | 1962 | * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 |
AnnaBridge | 171:3a7713b1edbc | 1963 | * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 |
AnnaBridge | 171:3a7713b1edbc | 1964 | */ |
AnnaBridge | 171:3a7713b1edbc | 1965 | __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 1966 | { |
AnnaBridge | 171:3a7713b1edbc | 1967 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 171:3a7713b1edbc | 1968 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 171:3a7713b1edbc | 1969 | return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); |
AnnaBridge | 171:3a7713b1edbc | 1970 | } |
AnnaBridge | 171:3a7713b1edbc | 1971 | |
AnnaBridge | 171:3a7713b1edbc | 1972 | /** |
AnnaBridge | 171:3a7713b1edbc | 1973 | * @brief Set the polarity of an output channel. |
AnnaBridge | 171:3a7713b1edbc | 1974 | * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n |
AnnaBridge | 171:3a7713b1edbc | 1975 | * CCER CC1NP LL_TIM_OC_SetPolarity\n |
AnnaBridge | 171:3a7713b1edbc | 1976 | * CCER CC2P LL_TIM_OC_SetPolarity\n |
AnnaBridge | 171:3a7713b1edbc | 1977 | * CCER CC2NP LL_TIM_OC_SetPolarity\n |
AnnaBridge | 171:3a7713b1edbc | 1978 | * CCER CC3P LL_TIM_OC_SetPolarity\n |
AnnaBridge | 171:3a7713b1edbc | 1979 | * CCER CC3NP LL_TIM_OC_SetPolarity\n |
AnnaBridge | 171:3a7713b1edbc | 1980 | * CCER CC4P LL_TIM_OC_SetPolarity\n |
AnnaBridge | 171:3a7713b1edbc | 1981 | * CCER CC5P LL_TIM_OC_SetPolarity\n |
AnnaBridge | 171:3a7713b1edbc | 1982 | * CCER CC6P LL_TIM_OC_SetPolarity |
AnnaBridge | 171:3a7713b1edbc | 1983 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 1984 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1985 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 171:3a7713b1edbc | 1986 | * @arg @ref LL_TIM_CHANNEL_CH1N |
AnnaBridge | 171:3a7713b1edbc | 1987 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 171:3a7713b1edbc | 1988 | * @arg @ref LL_TIM_CHANNEL_CH2N |
AnnaBridge | 171:3a7713b1edbc | 1989 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 171:3a7713b1edbc | 1990 | * @arg @ref LL_TIM_CHANNEL_CH3N |
AnnaBridge | 171:3a7713b1edbc | 1991 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 171:3a7713b1edbc | 1992 | * @arg @ref LL_TIM_CHANNEL_CH5 |
AnnaBridge | 171:3a7713b1edbc | 1993 | * @arg @ref LL_TIM_CHANNEL_CH6 |
AnnaBridge | 171:3a7713b1edbc | 1994 | * @param Polarity This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 1995 | * @arg @ref LL_TIM_OCPOLARITY_HIGH |
AnnaBridge | 171:3a7713b1edbc | 1996 | * @arg @ref LL_TIM_OCPOLARITY_LOW |
AnnaBridge | 171:3a7713b1edbc | 1997 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 1998 | */ |
AnnaBridge | 171:3a7713b1edbc | 1999 | __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) |
AnnaBridge | 171:3a7713b1edbc | 2000 | { |
AnnaBridge | 171:3a7713b1edbc | 2001 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 171:3a7713b1edbc | 2002 | MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); |
AnnaBridge | 171:3a7713b1edbc | 2003 | } |
AnnaBridge | 171:3a7713b1edbc | 2004 | |
AnnaBridge | 171:3a7713b1edbc | 2005 | /** |
AnnaBridge | 171:3a7713b1edbc | 2006 | * @brief Get the polarity of an output channel. |
AnnaBridge | 171:3a7713b1edbc | 2007 | * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n |
AnnaBridge | 171:3a7713b1edbc | 2008 | * CCER CC1NP LL_TIM_OC_GetPolarity\n |
AnnaBridge | 171:3a7713b1edbc | 2009 | * CCER CC2P LL_TIM_OC_GetPolarity\n |
AnnaBridge | 171:3a7713b1edbc | 2010 | * CCER CC2NP LL_TIM_OC_GetPolarity\n |
AnnaBridge | 171:3a7713b1edbc | 2011 | * CCER CC3P LL_TIM_OC_GetPolarity\n |
AnnaBridge | 171:3a7713b1edbc | 2012 | * CCER CC3NP LL_TIM_OC_GetPolarity\n |
AnnaBridge | 171:3a7713b1edbc | 2013 | * CCER CC4P LL_TIM_OC_GetPolarity\n |
AnnaBridge | 171:3a7713b1edbc | 2014 | * CCER CC5P LL_TIM_OC_GetPolarity\n |
AnnaBridge | 171:3a7713b1edbc | 2015 | * CCER CC6P LL_TIM_OC_GetPolarity |
AnnaBridge | 171:3a7713b1edbc | 2016 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2017 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2018 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 171:3a7713b1edbc | 2019 | * @arg @ref LL_TIM_CHANNEL_CH1N |
AnnaBridge | 171:3a7713b1edbc | 2020 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 171:3a7713b1edbc | 2021 | * @arg @ref LL_TIM_CHANNEL_CH2N |
AnnaBridge | 171:3a7713b1edbc | 2022 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 171:3a7713b1edbc | 2023 | * @arg @ref LL_TIM_CHANNEL_CH3N |
AnnaBridge | 171:3a7713b1edbc | 2024 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 171:3a7713b1edbc | 2025 | * @arg @ref LL_TIM_CHANNEL_CH5 |
AnnaBridge | 171:3a7713b1edbc | 2026 | * @arg @ref LL_TIM_CHANNEL_CH6 |
AnnaBridge | 171:3a7713b1edbc | 2027 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2028 | * @arg @ref LL_TIM_OCPOLARITY_HIGH |
AnnaBridge | 171:3a7713b1edbc | 2029 | * @arg @ref LL_TIM_OCPOLARITY_LOW |
AnnaBridge | 171:3a7713b1edbc | 2030 | */ |
AnnaBridge | 171:3a7713b1edbc | 2031 | __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 2032 | { |
AnnaBridge | 171:3a7713b1edbc | 2033 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 171:3a7713b1edbc | 2034 | return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); |
AnnaBridge | 171:3a7713b1edbc | 2035 | } |
AnnaBridge | 171:3a7713b1edbc | 2036 | |
AnnaBridge | 171:3a7713b1edbc | 2037 | /** |
AnnaBridge | 171:3a7713b1edbc | 2038 | * @brief Set the IDLE state of an output channel |
AnnaBridge | 171:3a7713b1edbc | 2039 | * @note This function is significant only for the timer instances |
AnnaBridge | 171:3a7713b1edbc | 2040 | * supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) |
AnnaBridge | 171:3a7713b1edbc | 2041 | * can be used to check whether or not a timer instance provides |
AnnaBridge | 171:3a7713b1edbc | 2042 | * a break input. |
AnnaBridge | 171:3a7713b1edbc | 2043 | * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n |
AnnaBridge | 171:3a7713b1edbc | 2044 | * CR2 OIS2N LL_TIM_OC_SetIdleState\n |
AnnaBridge | 171:3a7713b1edbc | 2045 | * CR2 OIS2 LL_TIM_OC_SetIdleState\n |
AnnaBridge | 171:3a7713b1edbc | 2046 | * CR2 OIS2N LL_TIM_OC_SetIdleState\n |
AnnaBridge | 171:3a7713b1edbc | 2047 | * CR2 OIS3 LL_TIM_OC_SetIdleState\n |
AnnaBridge | 171:3a7713b1edbc | 2048 | * CR2 OIS3N LL_TIM_OC_SetIdleState\n |
AnnaBridge | 171:3a7713b1edbc | 2049 | * CR2 OIS4 LL_TIM_OC_SetIdleState\n |
AnnaBridge | 171:3a7713b1edbc | 2050 | * CR2 OIS5 LL_TIM_OC_SetIdleState\n |
AnnaBridge | 171:3a7713b1edbc | 2051 | * CR2 OIS6 LL_TIM_OC_SetIdleState |
AnnaBridge | 171:3a7713b1edbc | 2052 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2053 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2054 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 171:3a7713b1edbc | 2055 | * @arg @ref LL_TIM_CHANNEL_CH1N |
AnnaBridge | 171:3a7713b1edbc | 2056 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 171:3a7713b1edbc | 2057 | * @arg @ref LL_TIM_CHANNEL_CH2N |
AnnaBridge | 171:3a7713b1edbc | 2058 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 171:3a7713b1edbc | 2059 | * @arg @ref LL_TIM_CHANNEL_CH3N |
AnnaBridge | 171:3a7713b1edbc | 2060 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 171:3a7713b1edbc | 2061 | * @arg @ref LL_TIM_CHANNEL_CH5 |
AnnaBridge | 171:3a7713b1edbc | 2062 | * @arg @ref LL_TIM_CHANNEL_CH6 |
AnnaBridge | 171:3a7713b1edbc | 2063 | * @param IdleState This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2064 | * @arg @ref LL_TIM_OCIDLESTATE_LOW |
AnnaBridge | 171:3a7713b1edbc | 2065 | * @arg @ref LL_TIM_OCIDLESTATE_HIGH |
AnnaBridge | 171:3a7713b1edbc | 2066 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2067 | */ |
AnnaBridge | 171:3a7713b1edbc | 2068 | __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) |
AnnaBridge | 171:3a7713b1edbc | 2069 | { |
AnnaBridge | 171:3a7713b1edbc | 2070 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 171:3a7713b1edbc | 2071 | MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); |
AnnaBridge | 171:3a7713b1edbc | 2072 | } |
AnnaBridge | 171:3a7713b1edbc | 2073 | |
AnnaBridge | 171:3a7713b1edbc | 2074 | /** |
AnnaBridge | 171:3a7713b1edbc | 2075 | * @brief Get the IDLE state of an output channel |
AnnaBridge | 171:3a7713b1edbc | 2076 | * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n |
AnnaBridge | 171:3a7713b1edbc | 2077 | * CR2 OIS2N LL_TIM_OC_GetIdleState\n |
AnnaBridge | 171:3a7713b1edbc | 2078 | * CR2 OIS2 LL_TIM_OC_GetIdleState\n |
AnnaBridge | 171:3a7713b1edbc | 2079 | * CR2 OIS2N LL_TIM_OC_GetIdleState\n |
AnnaBridge | 171:3a7713b1edbc | 2080 | * CR2 OIS3 LL_TIM_OC_GetIdleState\n |
AnnaBridge | 171:3a7713b1edbc | 2081 | * CR2 OIS3N LL_TIM_OC_GetIdleState\n |
AnnaBridge | 171:3a7713b1edbc | 2082 | * CR2 OIS4 LL_TIM_OC_GetIdleState\n |
AnnaBridge | 171:3a7713b1edbc | 2083 | * CR2 OIS5 LL_TIM_OC_GetIdleState\n |
AnnaBridge | 171:3a7713b1edbc | 2084 | * CR2 OIS6 LL_TIM_OC_GetIdleState |
AnnaBridge | 171:3a7713b1edbc | 2085 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2086 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2087 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 171:3a7713b1edbc | 2088 | * @arg @ref LL_TIM_CHANNEL_CH1N |
AnnaBridge | 171:3a7713b1edbc | 2089 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 171:3a7713b1edbc | 2090 | * @arg @ref LL_TIM_CHANNEL_CH2N |
AnnaBridge | 171:3a7713b1edbc | 2091 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 171:3a7713b1edbc | 2092 | * @arg @ref LL_TIM_CHANNEL_CH3N |
AnnaBridge | 171:3a7713b1edbc | 2093 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 171:3a7713b1edbc | 2094 | * @arg @ref LL_TIM_CHANNEL_CH5 |
AnnaBridge | 171:3a7713b1edbc | 2095 | * @arg @ref LL_TIM_CHANNEL_CH6 |
AnnaBridge | 171:3a7713b1edbc | 2096 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2097 | * @arg @ref LL_TIM_OCIDLESTATE_LOW |
AnnaBridge | 171:3a7713b1edbc | 2098 | * @arg @ref LL_TIM_OCIDLESTATE_HIGH |
AnnaBridge | 171:3a7713b1edbc | 2099 | */ |
AnnaBridge | 171:3a7713b1edbc | 2100 | __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 2101 | { |
AnnaBridge | 171:3a7713b1edbc | 2102 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 171:3a7713b1edbc | 2103 | return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); |
AnnaBridge | 171:3a7713b1edbc | 2104 | } |
AnnaBridge | 171:3a7713b1edbc | 2105 | |
AnnaBridge | 171:3a7713b1edbc | 2106 | /** |
AnnaBridge | 171:3a7713b1edbc | 2107 | * @brief Enable fast mode for the output channel. |
AnnaBridge | 171:3a7713b1edbc | 2108 | * @note Acts only if the channel is configured in PWM1 or PWM2 mode. |
AnnaBridge | 171:3a7713b1edbc | 2109 | * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n |
AnnaBridge | 171:3a7713b1edbc | 2110 | * CCMR1 OC2FE LL_TIM_OC_EnableFast\n |
AnnaBridge | 171:3a7713b1edbc | 2111 | * CCMR2 OC3FE LL_TIM_OC_EnableFast\n |
AnnaBridge | 171:3a7713b1edbc | 2112 | * CCMR2 OC4FE LL_TIM_OC_EnableFast\n |
AnnaBridge | 171:3a7713b1edbc | 2113 | * CCMR3 OC5FE LL_TIM_OC_EnableFast\n |
AnnaBridge | 171:3a7713b1edbc | 2114 | * CCMR3 OC6FE LL_TIM_OC_EnableFast |
AnnaBridge | 171:3a7713b1edbc | 2115 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2116 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2117 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 171:3a7713b1edbc | 2118 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 171:3a7713b1edbc | 2119 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 171:3a7713b1edbc | 2120 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 171:3a7713b1edbc | 2121 | * @arg @ref LL_TIM_CHANNEL_CH5 |
AnnaBridge | 171:3a7713b1edbc | 2122 | * @arg @ref LL_TIM_CHANNEL_CH6 |
AnnaBridge | 171:3a7713b1edbc | 2123 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2124 | */ |
AnnaBridge | 171:3a7713b1edbc | 2125 | __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 2126 | { |
AnnaBridge | 171:3a7713b1edbc | 2127 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 171:3a7713b1edbc | 2128 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 171:3a7713b1edbc | 2129 | SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); |
AnnaBridge | 171:3a7713b1edbc | 2130 | |
AnnaBridge | 171:3a7713b1edbc | 2131 | } |
AnnaBridge | 171:3a7713b1edbc | 2132 | |
AnnaBridge | 171:3a7713b1edbc | 2133 | /** |
AnnaBridge | 171:3a7713b1edbc | 2134 | * @brief Disable fast mode for the output channel. |
AnnaBridge | 171:3a7713b1edbc | 2135 | * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n |
AnnaBridge | 171:3a7713b1edbc | 2136 | * CCMR1 OC2FE LL_TIM_OC_DisableFast\n |
AnnaBridge | 171:3a7713b1edbc | 2137 | * CCMR2 OC3FE LL_TIM_OC_DisableFast\n |
AnnaBridge | 171:3a7713b1edbc | 2138 | * CCMR2 OC4FE LL_TIM_OC_DisableFast\n |
AnnaBridge | 171:3a7713b1edbc | 2139 | * CCMR3 OC5FE LL_TIM_OC_DisableFast\n |
AnnaBridge | 171:3a7713b1edbc | 2140 | * CCMR3 OC6FE LL_TIM_OC_DisableFast |
AnnaBridge | 171:3a7713b1edbc | 2141 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2142 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2143 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 171:3a7713b1edbc | 2144 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 171:3a7713b1edbc | 2145 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 171:3a7713b1edbc | 2146 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 171:3a7713b1edbc | 2147 | * @arg @ref LL_TIM_CHANNEL_CH5 |
AnnaBridge | 171:3a7713b1edbc | 2148 | * @arg @ref LL_TIM_CHANNEL_CH6 |
AnnaBridge | 171:3a7713b1edbc | 2149 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2150 | */ |
AnnaBridge | 171:3a7713b1edbc | 2151 | __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 2152 | { |
AnnaBridge | 171:3a7713b1edbc | 2153 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 171:3a7713b1edbc | 2154 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 171:3a7713b1edbc | 2155 | CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); |
AnnaBridge | 171:3a7713b1edbc | 2156 | |
AnnaBridge | 171:3a7713b1edbc | 2157 | } |
AnnaBridge | 171:3a7713b1edbc | 2158 | |
AnnaBridge | 171:3a7713b1edbc | 2159 | /** |
AnnaBridge | 171:3a7713b1edbc | 2160 | * @brief Indicates whether fast mode is enabled for the output channel. |
AnnaBridge | 171:3a7713b1edbc | 2161 | * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n |
AnnaBridge | 171:3a7713b1edbc | 2162 | * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n |
AnnaBridge | 171:3a7713b1edbc | 2163 | * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n |
AnnaBridge | 171:3a7713b1edbc | 2164 | * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n |
AnnaBridge | 171:3a7713b1edbc | 2165 | * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n |
AnnaBridge | 171:3a7713b1edbc | 2166 | * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast |
AnnaBridge | 171:3a7713b1edbc | 2167 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2168 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2169 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 171:3a7713b1edbc | 2170 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 171:3a7713b1edbc | 2171 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 171:3a7713b1edbc | 2172 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 171:3a7713b1edbc | 2173 | * @arg @ref LL_TIM_CHANNEL_CH5 |
AnnaBridge | 171:3a7713b1edbc | 2174 | * @arg @ref LL_TIM_CHANNEL_CH6 |
AnnaBridge | 171:3a7713b1edbc | 2175 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2176 | */ |
AnnaBridge | 171:3a7713b1edbc | 2177 | __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 2178 | { |
AnnaBridge | 171:3a7713b1edbc | 2179 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 171:3a7713b1edbc | 2180 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 171:3a7713b1edbc | 2181 | register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; |
AnnaBridge | 171:3a7713b1edbc | 2182 | return (READ_BIT(*pReg, bitfield) == bitfield); |
AnnaBridge | 171:3a7713b1edbc | 2183 | } |
AnnaBridge | 171:3a7713b1edbc | 2184 | |
AnnaBridge | 171:3a7713b1edbc | 2185 | /** |
AnnaBridge | 171:3a7713b1edbc | 2186 | * @brief Enable compare register (TIMx_CCRx) preload for the output channel. |
AnnaBridge | 171:3a7713b1edbc | 2187 | * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n |
AnnaBridge | 171:3a7713b1edbc | 2188 | * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n |
AnnaBridge | 171:3a7713b1edbc | 2189 | * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n |
AnnaBridge | 171:3a7713b1edbc | 2190 | * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n |
AnnaBridge | 171:3a7713b1edbc | 2191 | * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n |
AnnaBridge | 171:3a7713b1edbc | 2192 | * CCMR3 OC6PE LL_TIM_OC_EnablePreload |
AnnaBridge | 171:3a7713b1edbc | 2193 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2194 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2195 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 171:3a7713b1edbc | 2196 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 171:3a7713b1edbc | 2197 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 171:3a7713b1edbc | 2198 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 171:3a7713b1edbc | 2199 | * @arg @ref LL_TIM_CHANNEL_CH5 |
AnnaBridge | 171:3a7713b1edbc | 2200 | * @arg @ref LL_TIM_CHANNEL_CH6 |
AnnaBridge | 171:3a7713b1edbc | 2201 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2202 | */ |
AnnaBridge | 171:3a7713b1edbc | 2203 | __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 2204 | { |
AnnaBridge | 171:3a7713b1edbc | 2205 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 171:3a7713b1edbc | 2206 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 171:3a7713b1edbc | 2207 | SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); |
AnnaBridge | 171:3a7713b1edbc | 2208 | } |
AnnaBridge | 171:3a7713b1edbc | 2209 | |
AnnaBridge | 171:3a7713b1edbc | 2210 | /** |
AnnaBridge | 171:3a7713b1edbc | 2211 | * @brief Disable compare register (TIMx_CCRx) preload for the output channel. |
AnnaBridge | 171:3a7713b1edbc | 2212 | * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n |
AnnaBridge | 171:3a7713b1edbc | 2213 | * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n |
AnnaBridge | 171:3a7713b1edbc | 2214 | * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n |
AnnaBridge | 171:3a7713b1edbc | 2215 | * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n |
AnnaBridge | 171:3a7713b1edbc | 2216 | * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n |
AnnaBridge | 171:3a7713b1edbc | 2217 | * CCMR3 OC6PE LL_TIM_OC_DisablePreload |
AnnaBridge | 171:3a7713b1edbc | 2218 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2219 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2220 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 171:3a7713b1edbc | 2221 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 171:3a7713b1edbc | 2222 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 171:3a7713b1edbc | 2223 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 171:3a7713b1edbc | 2224 | * @arg @ref LL_TIM_CHANNEL_CH5 |
AnnaBridge | 171:3a7713b1edbc | 2225 | * @arg @ref LL_TIM_CHANNEL_CH6 |
AnnaBridge | 171:3a7713b1edbc | 2226 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2227 | */ |
AnnaBridge | 171:3a7713b1edbc | 2228 | __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 2229 | { |
AnnaBridge | 171:3a7713b1edbc | 2230 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 171:3a7713b1edbc | 2231 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 171:3a7713b1edbc | 2232 | CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); |
AnnaBridge | 171:3a7713b1edbc | 2233 | } |
AnnaBridge | 171:3a7713b1edbc | 2234 | |
AnnaBridge | 171:3a7713b1edbc | 2235 | /** |
AnnaBridge | 171:3a7713b1edbc | 2236 | * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel. |
AnnaBridge | 171:3a7713b1edbc | 2237 | * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n |
AnnaBridge | 171:3a7713b1edbc | 2238 | * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n |
AnnaBridge | 171:3a7713b1edbc | 2239 | * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n |
AnnaBridge | 171:3a7713b1edbc | 2240 | * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n |
AnnaBridge | 171:3a7713b1edbc | 2241 | * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n |
AnnaBridge | 171:3a7713b1edbc | 2242 | * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload |
AnnaBridge | 171:3a7713b1edbc | 2243 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2244 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2245 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 171:3a7713b1edbc | 2246 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 171:3a7713b1edbc | 2247 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 171:3a7713b1edbc | 2248 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 171:3a7713b1edbc | 2249 | * @arg @ref LL_TIM_CHANNEL_CH5 |
AnnaBridge | 171:3a7713b1edbc | 2250 | * @arg @ref LL_TIM_CHANNEL_CH6 |
AnnaBridge | 171:3a7713b1edbc | 2251 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2252 | */ |
AnnaBridge | 171:3a7713b1edbc | 2253 | __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 2254 | { |
AnnaBridge | 171:3a7713b1edbc | 2255 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 171:3a7713b1edbc | 2256 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 171:3a7713b1edbc | 2257 | register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; |
AnnaBridge | 171:3a7713b1edbc | 2258 | return (READ_BIT(*pReg, bitfield) == bitfield); |
AnnaBridge | 171:3a7713b1edbc | 2259 | } |
AnnaBridge | 171:3a7713b1edbc | 2260 | |
AnnaBridge | 171:3a7713b1edbc | 2261 | /** |
AnnaBridge | 171:3a7713b1edbc | 2262 | * @brief Enable clearing the output channel on an external event. |
AnnaBridge | 171:3a7713b1edbc | 2263 | * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. |
AnnaBridge | 171:3a7713b1edbc | 2264 | * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether |
AnnaBridge | 171:3a7713b1edbc | 2265 | * or not a timer instance can clear the OCxREF signal on an external event. |
AnnaBridge | 171:3a7713b1edbc | 2266 | * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n |
AnnaBridge | 171:3a7713b1edbc | 2267 | * CCMR1 OC2CE LL_TIM_OC_EnableClear\n |
AnnaBridge | 171:3a7713b1edbc | 2268 | * CCMR2 OC3CE LL_TIM_OC_EnableClear\n |
AnnaBridge | 171:3a7713b1edbc | 2269 | * CCMR2 OC4CE LL_TIM_OC_EnableClear\n |
AnnaBridge | 171:3a7713b1edbc | 2270 | * CCMR3 OC5CE LL_TIM_OC_EnableClear\n |
AnnaBridge | 171:3a7713b1edbc | 2271 | * CCMR3 OC6CE LL_TIM_OC_EnableClear |
AnnaBridge | 171:3a7713b1edbc | 2272 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2273 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2274 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 171:3a7713b1edbc | 2275 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 171:3a7713b1edbc | 2276 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 171:3a7713b1edbc | 2277 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 171:3a7713b1edbc | 2278 | * @arg @ref LL_TIM_CHANNEL_CH5 |
AnnaBridge | 171:3a7713b1edbc | 2279 | * @arg @ref LL_TIM_CHANNEL_CH6 |
AnnaBridge | 171:3a7713b1edbc | 2280 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2281 | */ |
AnnaBridge | 171:3a7713b1edbc | 2282 | __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 2283 | { |
AnnaBridge | 171:3a7713b1edbc | 2284 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 171:3a7713b1edbc | 2285 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 171:3a7713b1edbc | 2286 | SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); |
AnnaBridge | 171:3a7713b1edbc | 2287 | } |
AnnaBridge | 171:3a7713b1edbc | 2288 | |
AnnaBridge | 171:3a7713b1edbc | 2289 | /** |
AnnaBridge | 171:3a7713b1edbc | 2290 | * @brief Disable clearing the output channel on an external event. |
AnnaBridge | 171:3a7713b1edbc | 2291 | * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether |
AnnaBridge | 171:3a7713b1edbc | 2292 | * or not a timer instance can clear the OCxREF signal on an external event. |
AnnaBridge | 171:3a7713b1edbc | 2293 | * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n |
AnnaBridge | 171:3a7713b1edbc | 2294 | * CCMR1 OC2CE LL_TIM_OC_DisableClear\n |
AnnaBridge | 171:3a7713b1edbc | 2295 | * CCMR2 OC3CE LL_TIM_OC_DisableClear\n |
AnnaBridge | 171:3a7713b1edbc | 2296 | * CCMR2 OC4CE LL_TIM_OC_DisableClear\n |
AnnaBridge | 171:3a7713b1edbc | 2297 | * CCMR3 OC5CE LL_TIM_OC_DisableClear\n |
AnnaBridge | 171:3a7713b1edbc | 2298 | * CCMR3 OC6CE LL_TIM_OC_DisableClear |
AnnaBridge | 171:3a7713b1edbc | 2299 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2300 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2301 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 171:3a7713b1edbc | 2302 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 171:3a7713b1edbc | 2303 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 171:3a7713b1edbc | 2304 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 171:3a7713b1edbc | 2305 | * @arg @ref LL_TIM_CHANNEL_CH5 |
AnnaBridge | 171:3a7713b1edbc | 2306 | * @arg @ref LL_TIM_CHANNEL_CH6 |
AnnaBridge | 171:3a7713b1edbc | 2307 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2308 | */ |
AnnaBridge | 171:3a7713b1edbc | 2309 | __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 2310 | { |
AnnaBridge | 171:3a7713b1edbc | 2311 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 171:3a7713b1edbc | 2312 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 171:3a7713b1edbc | 2313 | CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); |
AnnaBridge | 171:3a7713b1edbc | 2314 | } |
AnnaBridge | 171:3a7713b1edbc | 2315 | |
AnnaBridge | 171:3a7713b1edbc | 2316 | /** |
AnnaBridge | 171:3a7713b1edbc | 2317 | * @brief Indicates clearing the output channel on an external event is enabled for the output channel. |
AnnaBridge | 171:3a7713b1edbc | 2318 | * @note This function enables clearing the output channel on an external event. |
AnnaBridge | 171:3a7713b1edbc | 2319 | * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. |
AnnaBridge | 171:3a7713b1edbc | 2320 | * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether |
AnnaBridge | 171:3a7713b1edbc | 2321 | * or not a timer instance can clear the OCxREF signal on an external event. |
AnnaBridge | 171:3a7713b1edbc | 2322 | * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n |
AnnaBridge | 171:3a7713b1edbc | 2323 | * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n |
AnnaBridge | 171:3a7713b1edbc | 2324 | * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n |
AnnaBridge | 171:3a7713b1edbc | 2325 | * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n |
AnnaBridge | 171:3a7713b1edbc | 2326 | * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n |
AnnaBridge | 171:3a7713b1edbc | 2327 | * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear |
AnnaBridge | 171:3a7713b1edbc | 2328 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2329 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2330 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 171:3a7713b1edbc | 2331 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 171:3a7713b1edbc | 2332 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 171:3a7713b1edbc | 2333 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 171:3a7713b1edbc | 2334 | * @arg @ref LL_TIM_CHANNEL_CH5 |
AnnaBridge | 171:3a7713b1edbc | 2335 | * @arg @ref LL_TIM_CHANNEL_CH6 |
AnnaBridge | 171:3a7713b1edbc | 2336 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2337 | */ |
AnnaBridge | 171:3a7713b1edbc | 2338 | __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 2339 | { |
AnnaBridge | 171:3a7713b1edbc | 2340 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 171:3a7713b1edbc | 2341 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 171:3a7713b1edbc | 2342 | register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; |
AnnaBridge | 171:3a7713b1edbc | 2343 | return (READ_BIT(*pReg, bitfield) == bitfield); |
AnnaBridge | 171:3a7713b1edbc | 2344 | } |
AnnaBridge | 171:3a7713b1edbc | 2345 | |
AnnaBridge | 171:3a7713b1edbc | 2346 | /** |
AnnaBridge | 171:3a7713b1edbc | 2347 | * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals). |
AnnaBridge | 171:3a7713b1edbc | 2348 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 2349 | * dead-time insertion feature is supported by a timer instance. |
AnnaBridge | 171:3a7713b1edbc | 2350 | * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter |
AnnaBridge | 171:3a7713b1edbc | 2351 | * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime |
AnnaBridge | 171:3a7713b1edbc | 2352 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2353 | * @param DeadTime between Min_Data=0 and Max_Data=255 |
AnnaBridge | 171:3a7713b1edbc | 2354 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2355 | */ |
AnnaBridge | 171:3a7713b1edbc | 2356 | __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) |
AnnaBridge | 171:3a7713b1edbc | 2357 | { |
AnnaBridge | 171:3a7713b1edbc | 2358 | MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); |
AnnaBridge | 171:3a7713b1edbc | 2359 | } |
AnnaBridge | 171:3a7713b1edbc | 2360 | |
AnnaBridge | 171:3a7713b1edbc | 2361 | /** |
AnnaBridge | 171:3a7713b1edbc | 2362 | * @brief Set compare value for output channel 1 (TIMx_CCR1). |
AnnaBridge | 171:3a7713b1edbc | 2363 | * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. |
AnnaBridge | 171:3a7713b1edbc | 2364 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
AnnaBridge | 171:3a7713b1edbc | 2365 | * whether or not a timer instance supports a 32 bits counter. |
AnnaBridge | 171:3a7713b1edbc | 2366 | * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 2367 | * output channel 1 is supported by a timer instance. |
AnnaBridge | 171:3a7713b1edbc | 2368 | * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 |
AnnaBridge | 171:3a7713b1edbc | 2369 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2370 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
AnnaBridge | 171:3a7713b1edbc | 2371 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2372 | */ |
AnnaBridge | 171:3a7713b1edbc | 2373 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) |
AnnaBridge | 171:3a7713b1edbc | 2374 | { |
AnnaBridge | 171:3a7713b1edbc | 2375 | WRITE_REG(TIMx->CCR1, CompareValue); |
AnnaBridge | 171:3a7713b1edbc | 2376 | } |
AnnaBridge | 171:3a7713b1edbc | 2377 | |
AnnaBridge | 171:3a7713b1edbc | 2378 | /** |
AnnaBridge | 171:3a7713b1edbc | 2379 | * @brief Set compare value for output channel 2 (TIMx_CCR2). |
AnnaBridge | 171:3a7713b1edbc | 2380 | * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. |
AnnaBridge | 171:3a7713b1edbc | 2381 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
AnnaBridge | 171:3a7713b1edbc | 2382 | * whether or not a timer instance supports a 32 bits counter. |
AnnaBridge | 171:3a7713b1edbc | 2383 | * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 2384 | * output channel 2 is supported by a timer instance. |
AnnaBridge | 171:3a7713b1edbc | 2385 | * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 |
AnnaBridge | 171:3a7713b1edbc | 2386 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2387 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
AnnaBridge | 171:3a7713b1edbc | 2388 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2389 | */ |
AnnaBridge | 171:3a7713b1edbc | 2390 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) |
AnnaBridge | 171:3a7713b1edbc | 2391 | { |
AnnaBridge | 171:3a7713b1edbc | 2392 | WRITE_REG(TIMx->CCR2, CompareValue); |
AnnaBridge | 171:3a7713b1edbc | 2393 | } |
AnnaBridge | 171:3a7713b1edbc | 2394 | |
AnnaBridge | 171:3a7713b1edbc | 2395 | /** |
AnnaBridge | 171:3a7713b1edbc | 2396 | * @brief Set compare value for output channel 3 (TIMx_CCR3). |
AnnaBridge | 171:3a7713b1edbc | 2397 | * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. |
AnnaBridge | 171:3a7713b1edbc | 2398 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
AnnaBridge | 171:3a7713b1edbc | 2399 | * whether or not a timer instance supports a 32 bits counter. |
AnnaBridge | 171:3a7713b1edbc | 2400 | * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 2401 | * output channel is supported by a timer instance. |
AnnaBridge | 171:3a7713b1edbc | 2402 | * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 |
AnnaBridge | 171:3a7713b1edbc | 2403 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2404 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
AnnaBridge | 171:3a7713b1edbc | 2405 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2406 | */ |
AnnaBridge | 171:3a7713b1edbc | 2407 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) |
AnnaBridge | 171:3a7713b1edbc | 2408 | { |
AnnaBridge | 171:3a7713b1edbc | 2409 | WRITE_REG(TIMx->CCR3, CompareValue); |
AnnaBridge | 171:3a7713b1edbc | 2410 | } |
AnnaBridge | 171:3a7713b1edbc | 2411 | |
AnnaBridge | 171:3a7713b1edbc | 2412 | /** |
AnnaBridge | 171:3a7713b1edbc | 2413 | * @brief Set compare value for output channel 4 (TIMx_CCR4). |
AnnaBridge | 171:3a7713b1edbc | 2414 | * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. |
AnnaBridge | 171:3a7713b1edbc | 2415 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
AnnaBridge | 171:3a7713b1edbc | 2416 | * whether or not a timer instance supports a 32 bits counter. |
AnnaBridge | 171:3a7713b1edbc | 2417 | * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 2418 | * output channel 4 is supported by a timer instance. |
AnnaBridge | 171:3a7713b1edbc | 2419 | * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 |
AnnaBridge | 171:3a7713b1edbc | 2420 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2421 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
AnnaBridge | 171:3a7713b1edbc | 2422 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2423 | */ |
AnnaBridge | 171:3a7713b1edbc | 2424 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) |
AnnaBridge | 171:3a7713b1edbc | 2425 | { |
AnnaBridge | 171:3a7713b1edbc | 2426 | WRITE_REG(TIMx->CCR4, CompareValue); |
AnnaBridge | 171:3a7713b1edbc | 2427 | } |
AnnaBridge | 171:3a7713b1edbc | 2428 | |
AnnaBridge | 171:3a7713b1edbc | 2429 | /** |
AnnaBridge | 171:3a7713b1edbc | 2430 | * @brief Set compare value for output channel 5 (TIMx_CCR5). |
AnnaBridge | 171:3a7713b1edbc | 2431 | * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 2432 | * output channel 5 is supported by a timer instance. |
AnnaBridge | 171:3a7713b1edbc | 2433 | * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5 |
AnnaBridge | 171:3a7713b1edbc | 2434 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2435 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
AnnaBridge | 171:3a7713b1edbc | 2436 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2437 | */ |
AnnaBridge | 171:3a7713b1edbc | 2438 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue) |
AnnaBridge | 171:3a7713b1edbc | 2439 | { |
AnnaBridge | 171:3a7713b1edbc | 2440 | WRITE_REG(TIMx->CCR5, CompareValue); |
AnnaBridge | 171:3a7713b1edbc | 2441 | } |
AnnaBridge | 171:3a7713b1edbc | 2442 | |
AnnaBridge | 171:3a7713b1edbc | 2443 | /** |
AnnaBridge | 171:3a7713b1edbc | 2444 | * @brief Set compare value for output channel 6 (TIMx_CCR6). |
AnnaBridge | 171:3a7713b1edbc | 2445 | * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 2446 | * output channel 6 is supported by a timer instance. |
AnnaBridge | 171:3a7713b1edbc | 2447 | * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6 |
AnnaBridge | 171:3a7713b1edbc | 2448 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2449 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
AnnaBridge | 171:3a7713b1edbc | 2450 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2451 | */ |
AnnaBridge | 171:3a7713b1edbc | 2452 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue) |
AnnaBridge | 171:3a7713b1edbc | 2453 | { |
AnnaBridge | 171:3a7713b1edbc | 2454 | WRITE_REG(TIMx->CCR6, CompareValue); |
AnnaBridge | 171:3a7713b1edbc | 2455 | } |
AnnaBridge | 171:3a7713b1edbc | 2456 | |
AnnaBridge | 171:3a7713b1edbc | 2457 | /** |
AnnaBridge | 171:3a7713b1edbc | 2458 | * @brief Get compare value (TIMx_CCR1) set for output channel 1. |
AnnaBridge | 171:3a7713b1edbc | 2459 | * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. |
AnnaBridge | 171:3a7713b1edbc | 2460 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
AnnaBridge | 171:3a7713b1edbc | 2461 | * whether or not a timer instance supports a 32 bits counter. |
AnnaBridge | 171:3a7713b1edbc | 2462 | * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 2463 | * output channel 1 is supported by a timer instance. |
AnnaBridge | 171:3a7713b1edbc | 2464 | * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 |
AnnaBridge | 171:3a7713b1edbc | 2465 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2466 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
AnnaBridge | 171:3a7713b1edbc | 2467 | */ |
AnnaBridge | 171:3a7713b1edbc | 2468 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 2469 | { |
AnnaBridge | 171:3a7713b1edbc | 2470 | return (uint32_t)(READ_REG(TIMx->CCR1)); |
AnnaBridge | 171:3a7713b1edbc | 2471 | } |
AnnaBridge | 171:3a7713b1edbc | 2472 | |
AnnaBridge | 171:3a7713b1edbc | 2473 | /** |
AnnaBridge | 171:3a7713b1edbc | 2474 | * @brief Get compare value (TIMx_CCR2) set for output channel 2. |
AnnaBridge | 171:3a7713b1edbc | 2475 | * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. |
AnnaBridge | 171:3a7713b1edbc | 2476 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
AnnaBridge | 171:3a7713b1edbc | 2477 | * whether or not a timer instance supports a 32 bits counter. |
AnnaBridge | 171:3a7713b1edbc | 2478 | * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 2479 | * output channel 2 is supported by a timer instance. |
AnnaBridge | 171:3a7713b1edbc | 2480 | * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 |
AnnaBridge | 171:3a7713b1edbc | 2481 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2482 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
AnnaBridge | 171:3a7713b1edbc | 2483 | */ |
AnnaBridge | 171:3a7713b1edbc | 2484 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 2485 | { |
AnnaBridge | 171:3a7713b1edbc | 2486 | return (uint32_t)(READ_REG(TIMx->CCR2)); |
AnnaBridge | 171:3a7713b1edbc | 2487 | } |
AnnaBridge | 171:3a7713b1edbc | 2488 | |
AnnaBridge | 171:3a7713b1edbc | 2489 | /** |
AnnaBridge | 171:3a7713b1edbc | 2490 | * @brief Get compare value (TIMx_CCR3) set for output channel 3. |
AnnaBridge | 171:3a7713b1edbc | 2491 | * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. |
AnnaBridge | 171:3a7713b1edbc | 2492 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
AnnaBridge | 171:3a7713b1edbc | 2493 | * whether or not a timer instance supports a 32 bits counter. |
AnnaBridge | 171:3a7713b1edbc | 2494 | * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 2495 | * output channel 3 is supported by a timer instance. |
AnnaBridge | 171:3a7713b1edbc | 2496 | * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 |
AnnaBridge | 171:3a7713b1edbc | 2497 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2498 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
AnnaBridge | 171:3a7713b1edbc | 2499 | */ |
AnnaBridge | 171:3a7713b1edbc | 2500 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 2501 | { |
AnnaBridge | 171:3a7713b1edbc | 2502 | return (uint32_t)(READ_REG(TIMx->CCR3)); |
AnnaBridge | 171:3a7713b1edbc | 2503 | } |
AnnaBridge | 171:3a7713b1edbc | 2504 | |
AnnaBridge | 171:3a7713b1edbc | 2505 | /** |
AnnaBridge | 171:3a7713b1edbc | 2506 | * @brief Get compare value (TIMx_CCR4) set for output channel 4. |
AnnaBridge | 171:3a7713b1edbc | 2507 | * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. |
AnnaBridge | 171:3a7713b1edbc | 2508 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
AnnaBridge | 171:3a7713b1edbc | 2509 | * whether or not a timer instance supports a 32 bits counter. |
AnnaBridge | 171:3a7713b1edbc | 2510 | * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 2511 | * output channel 4 is supported by a timer instance. |
AnnaBridge | 171:3a7713b1edbc | 2512 | * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 |
AnnaBridge | 171:3a7713b1edbc | 2513 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2514 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
AnnaBridge | 171:3a7713b1edbc | 2515 | */ |
AnnaBridge | 171:3a7713b1edbc | 2516 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 2517 | { |
AnnaBridge | 171:3a7713b1edbc | 2518 | return (uint32_t)(READ_REG(TIMx->CCR4)); |
AnnaBridge | 171:3a7713b1edbc | 2519 | } |
AnnaBridge | 171:3a7713b1edbc | 2520 | |
AnnaBridge | 171:3a7713b1edbc | 2521 | /** |
AnnaBridge | 171:3a7713b1edbc | 2522 | * @brief Get compare value (TIMx_CCR5) set for output channel 5. |
AnnaBridge | 171:3a7713b1edbc | 2523 | * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 2524 | * output channel 5 is supported by a timer instance. |
AnnaBridge | 171:3a7713b1edbc | 2525 | * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5 |
AnnaBridge | 171:3a7713b1edbc | 2526 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2527 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
AnnaBridge | 171:3a7713b1edbc | 2528 | */ |
AnnaBridge | 171:3a7713b1edbc | 2529 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 2530 | { |
AnnaBridge | 171:3a7713b1edbc | 2531 | return (uint32_t)(READ_REG(TIMx->CCR5)); |
AnnaBridge | 171:3a7713b1edbc | 2532 | } |
AnnaBridge | 171:3a7713b1edbc | 2533 | |
AnnaBridge | 171:3a7713b1edbc | 2534 | /** |
AnnaBridge | 171:3a7713b1edbc | 2535 | * @brief Get compare value (TIMx_CCR6) set for output channel 6. |
AnnaBridge | 171:3a7713b1edbc | 2536 | * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 2537 | * output channel 6 is supported by a timer instance. |
AnnaBridge | 171:3a7713b1edbc | 2538 | * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6 |
AnnaBridge | 171:3a7713b1edbc | 2539 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2540 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
AnnaBridge | 171:3a7713b1edbc | 2541 | */ |
AnnaBridge | 171:3a7713b1edbc | 2542 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 2543 | { |
AnnaBridge | 171:3a7713b1edbc | 2544 | return (uint32_t)(READ_REG(TIMx->CCR6)); |
AnnaBridge | 171:3a7713b1edbc | 2545 | } |
AnnaBridge | 171:3a7713b1edbc | 2546 | |
AnnaBridge | 171:3a7713b1edbc | 2547 | /** |
AnnaBridge | 171:3a7713b1edbc | 2548 | * @brief Select on which reference signal the OC5REF is combined to. |
AnnaBridge | 171:3a7713b1edbc | 2549 | * @note Macro @ref IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check |
AnnaBridge | 171:3a7713b1edbc | 2550 | * whether or not a timer instance supports the combined 3-phase PWM mode. |
AnnaBridge | 171:3a7713b1edbc | 2551 | * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n |
AnnaBridge | 171:3a7713b1edbc | 2552 | * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n |
AnnaBridge | 171:3a7713b1edbc | 2553 | * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels |
AnnaBridge | 171:3a7713b1edbc | 2554 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2555 | * @param GroupCH5 This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2556 | * @arg @ref LL_TIM_GROUPCH5_NONE |
AnnaBridge | 171:3a7713b1edbc | 2557 | * @arg @ref LL_TIM_GROUPCH5_OC1REFC |
AnnaBridge | 171:3a7713b1edbc | 2558 | * @arg @ref LL_TIM_GROUPCH5_OC2REFC |
AnnaBridge | 171:3a7713b1edbc | 2559 | * @arg @ref LL_TIM_GROUPCH5_OC3REFC |
AnnaBridge | 171:3a7713b1edbc | 2560 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2561 | */ |
AnnaBridge | 171:3a7713b1edbc | 2562 | __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5) |
AnnaBridge | 171:3a7713b1edbc | 2563 | { |
AnnaBridge | 171:3a7713b1edbc | 2564 | MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, GroupCH5); |
AnnaBridge | 171:3a7713b1edbc | 2565 | } |
AnnaBridge | 171:3a7713b1edbc | 2566 | |
AnnaBridge | 171:3a7713b1edbc | 2567 | /** |
AnnaBridge | 171:3a7713b1edbc | 2568 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2569 | */ |
AnnaBridge | 171:3a7713b1edbc | 2570 | |
AnnaBridge | 171:3a7713b1edbc | 2571 | /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration |
AnnaBridge | 171:3a7713b1edbc | 2572 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 2573 | */ |
AnnaBridge | 171:3a7713b1edbc | 2574 | /** |
AnnaBridge | 171:3a7713b1edbc | 2575 | * @brief Configure input channel. |
AnnaBridge | 171:3a7713b1edbc | 2576 | * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n |
AnnaBridge | 171:3a7713b1edbc | 2577 | * CCMR1 IC1PSC LL_TIM_IC_Config\n |
AnnaBridge | 171:3a7713b1edbc | 2578 | * CCMR1 IC1F LL_TIM_IC_Config\n |
AnnaBridge | 171:3a7713b1edbc | 2579 | * CCMR1 CC2S LL_TIM_IC_Config\n |
AnnaBridge | 171:3a7713b1edbc | 2580 | * CCMR1 IC2PSC LL_TIM_IC_Config\n |
AnnaBridge | 171:3a7713b1edbc | 2581 | * CCMR1 IC2F LL_TIM_IC_Config\n |
AnnaBridge | 171:3a7713b1edbc | 2582 | * CCMR2 CC3S LL_TIM_IC_Config\n |
AnnaBridge | 171:3a7713b1edbc | 2583 | * CCMR2 IC3PSC LL_TIM_IC_Config\n |
AnnaBridge | 171:3a7713b1edbc | 2584 | * CCMR2 IC3F LL_TIM_IC_Config\n |
AnnaBridge | 171:3a7713b1edbc | 2585 | * CCMR2 CC4S LL_TIM_IC_Config\n |
AnnaBridge | 171:3a7713b1edbc | 2586 | * CCMR2 IC4PSC LL_TIM_IC_Config\n |
AnnaBridge | 171:3a7713b1edbc | 2587 | * CCMR2 IC4F LL_TIM_IC_Config\n |
AnnaBridge | 171:3a7713b1edbc | 2588 | * CCER CC1P LL_TIM_IC_Config\n |
AnnaBridge | 171:3a7713b1edbc | 2589 | * CCER CC1NP LL_TIM_IC_Config\n |
AnnaBridge | 171:3a7713b1edbc | 2590 | * CCER CC2P LL_TIM_IC_Config\n |
AnnaBridge | 171:3a7713b1edbc | 2591 | * CCER CC2NP LL_TIM_IC_Config\n |
AnnaBridge | 171:3a7713b1edbc | 2592 | * CCER CC3P LL_TIM_IC_Config\n |
AnnaBridge | 171:3a7713b1edbc | 2593 | * CCER CC3NP LL_TIM_IC_Config\n |
AnnaBridge | 171:3a7713b1edbc | 2594 | * CCER CC4P LL_TIM_IC_Config\n |
AnnaBridge | 171:3a7713b1edbc | 2595 | * CCER CC4NP LL_TIM_IC_Config |
AnnaBridge | 171:3a7713b1edbc | 2596 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2597 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2598 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 171:3a7713b1edbc | 2599 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 171:3a7713b1edbc | 2600 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 171:3a7713b1edbc | 2601 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 171:3a7713b1edbc | 2602 | * @param Configuration This parameter must be a combination of all the following values: |
AnnaBridge | 171:3a7713b1edbc | 2603 | * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC |
AnnaBridge | 171:3a7713b1edbc | 2604 | * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 |
AnnaBridge | 171:3a7713b1edbc | 2605 | * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 |
AnnaBridge | 171:3a7713b1edbc | 2606 | * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE |
AnnaBridge | 171:3a7713b1edbc | 2607 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2608 | */ |
AnnaBridge | 171:3a7713b1edbc | 2609 | __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) |
AnnaBridge | 171:3a7713b1edbc | 2610 | { |
AnnaBridge | 171:3a7713b1edbc | 2611 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 171:3a7713b1edbc | 2612 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 171:3a7713b1edbc | 2613 | MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), |
AnnaBridge | 171:3a7713b1edbc | 2614 | ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]); |
AnnaBridge | 171:3a7713b1edbc | 2615 | MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), |
AnnaBridge | 171:3a7713b1edbc | 2616 | (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); |
AnnaBridge | 171:3a7713b1edbc | 2617 | } |
AnnaBridge | 171:3a7713b1edbc | 2618 | |
AnnaBridge | 171:3a7713b1edbc | 2619 | /** |
AnnaBridge | 171:3a7713b1edbc | 2620 | * @brief Set the active input. |
AnnaBridge | 171:3a7713b1edbc | 2621 | * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n |
AnnaBridge | 171:3a7713b1edbc | 2622 | * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n |
AnnaBridge | 171:3a7713b1edbc | 2623 | * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n |
AnnaBridge | 171:3a7713b1edbc | 2624 | * CCMR2 CC4S LL_TIM_IC_SetActiveInput |
AnnaBridge | 171:3a7713b1edbc | 2625 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2626 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2627 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 171:3a7713b1edbc | 2628 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 171:3a7713b1edbc | 2629 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 171:3a7713b1edbc | 2630 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 171:3a7713b1edbc | 2631 | * @param ICActiveInput This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2632 | * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI |
AnnaBridge | 171:3a7713b1edbc | 2633 | * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI |
AnnaBridge | 171:3a7713b1edbc | 2634 | * @arg @ref LL_TIM_ACTIVEINPUT_TRC |
AnnaBridge | 171:3a7713b1edbc | 2635 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2636 | */ |
AnnaBridge | 171:3a7713b1edbc | 2637 | __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) |
AnnaBridge | 171:3a7713b1edbc | 2638 | { |
AnnaBridge | 171:3a7713b1edbc | 2639 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 171:3a7713b1edbc | 2640 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 171:3a7713b1edbc | 2641 | MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); |
AnnaBridge | 171:3a7713b1edbc | 2642 | } |
AnnaBridge | 171:3a7713b1edbc | 2643 | |
AnnaBridge | 171:3a7713b1edbc | 2644 | /** |
AnnaBridge | 171:3a7713b1edbc | 2645 | * @brief Get the current active input. |
AnnaBridge | 171:3a7713b1edbc | 2646 | * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n |
AnnaBridge | 171:3a7713b1edbc | 2647 | * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n |
AnnaBridge | 171:3a7713b1edbc | 2648 | * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n |
AnnaBridge | 171:3a7713b1edbc | 2649 | * CCMR2 CC4S LL_TIM_IC_GetActiveInput |
AnnaBridge | 171:3a7713b1edbc | 2650 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2651 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2652 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 171:3a7713b1edbc | 2653 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 171:3a7713b1edbc | 2654 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 171:3a7713b1edbc | 2655 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 171:3a7713b1edbc | 2656 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2657 | * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI |
AnnaBridge | 171:3a7713b1edbc | 2658 | * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI |
AnnaBridge | 171:3a7713b1edbc | 2659 | * @arg @ref LL_TIM_ACTIVEINPUT_TRC |
AnnaBridge | 171:3a7713b1edbc | 2660 | */ |
AnnaBridge | 171:3a7713b1edbc | 2661 | __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 2662 | { |
AnnaBridge | 171:3a7713b1edbc | 2663 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 171:3a7713b1edbc | 2664 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 171:3a7713b1edbc | 2665 | return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); |
AnnaBridge | 171:3a7713b1edbc | 2666 | } |
AnnaBridge | 171:3a7713b1edbc | 2667 | |
AnnaBridge | 171:3a7713b1edbc | 2668 | /** |
AnnaBridge | 171:3a7713b1edbc | 2669 | * @brief Set the prescaler of input channel. |
AnnaBridge | 171:3a7713b1edbc | 2670 | * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n |
AnnaBridge | 171:3a7713b1edbc | 2671 | * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n |
AnnaBridge | 171:3a7713b1edbc | 2672 | * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n |
AnnaBridge | 171:3a7713b1edbc | 2673 | * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler |
AnnaBridge | 171:3a7713b1edbc | 2674 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2675 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2676 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 171:3a7713b1edbc | 2677 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 171:3a7713b1edbc | 2678 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 171:3a7713b1edbc | 2679 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 171:3a7713b1edbc | 2680 | * @param ICPrescaler This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2681 | * @arg @ref LL_TIM_ICPSC_DIV1 |
AnnaBridge | 171:3a7713b1edbc | 2682 | * @arg @ref LL_TIM_ICPSC_DIV2 |
AnnaBridge | 171:3a7713b1edbc | 2683 | * @arg @ref LL_TIM_ICPSC_DIV4 |
AnnaBridge | 171:3a7713b1edbc | 2684 | * @arg @ref LL_TIM_ICPSC_DIV8 |
AnnaBridge | 171:3a7713b1edbc | 2685 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2686 | */ |
AnnaBridge | 171:3a7713b1edbc | 2687 | __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) |
AnnaBridge | 171:3a7713b1edbc | 2688 | { |
AnnaBridge | 171:3a7713b1edbc | 2689 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 171:3a7713b1edbc | 2690 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 171:3a7713b1edbc | 2691 | MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); |
AnnaBridge | 171:3a7713b1edbc | 2692 | } |
AnnaBridge | 171:3a7713b1edbc | 2693 | |
AnnaBridge | 171:3a7713b1edbc | 2694 | /** |
AnnaBridge | 171:3a7713b1edbc | 2695 | * @brief Get the current prescaler value acting on an input channel. |
AnnaBridge | 171:3a7713b1edbc | 2696 | * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n |
AnnaBridge | 171:3a7713b1edbc | 2697 | * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n |
AnnaBridge | 171:3a7713b1edbc | 2698 | * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n |
AnnaBridge | 171:3a7713b1edbc | 2699 | * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler |
AnnaBridge | 171:3a7713b1edbc | 2700 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2701 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2702 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 171:3a7713b1edbc | 2703 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 171:3a7713b1edbc | 2704 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 171:3a7713b1edbc | 2705 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 171:3a7713b1edbc | 2706 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2707 | * @arg @ref LL_TIM_ICPSC_DIV1 |
AnnaBridge | 171:3a7713b1edbc | 2708 | * @arg @ref LL_TIM_ICPSC_DIV2 |
AnnaBridge | 171:3a7713b1edbc | 2709 | * @arg @ref LL_TIM_ICPSC_DIV4 |
AnnaBridge | 171:3a7713b1edbc | 2710 | * @arg @ref LL_TIM_ICPSC_DIV8 |
AnnaBridge | 171:3a7713b1edbc | 2711 | */ |
AnnaBridge | 171:3a7713b1edbc | 2712 | __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 2713 | { |
AnnaBridge | 171:3a7713b1edbc | 2714 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 171:3a7713b1edbc | 2715 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 171:3a7713b1edbc | 2716 | return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); |
AnnaBridge | 171:3a7713b1edbc | 2717 | } |
AnnaBridge | 171:3a7713b1edbc | 2718 | |
AnnaBridge | 171:3a7713b1edbc | 2719 | /** |
AnnaBridge | 171:3a7713b1edbc | 2720 | * @brief Set the input filter duration. |
AnnaBridge | 171:3a7713b1edbc | 2721 | * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n |
AnnaBridge | 171:3a7713b1edbc | 2722 | * CCMR1 IC2F LL_TIM_IC_SetFilter\n |
AnnaBridge | 171:3a7713b1edbc | 2723 | * CCMR2 IC3F LL_TIM_IC_SetFilter\n |
AnnaBridge | 171:3a7713b1edbc | 2724 | * CCMR2 IC4F LL_TIM_IC_SetFilter |
AnnaBridge | 171:3a7713b1edbc | 2725 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2726 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2727 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 171:3a7713b1edbc | 2728 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 171:3a7713b1edbc | 2729 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 171:3a7713b1edbc | 2730 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 171:3a7713b1edbc | 2731 | * @param ICFilter This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2732 | * @arg @ref LL_TIM_IC_FILTER_FDIV1 |
AnnaBridge | 171:3a7713b1edbc | 2733 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 |
AnnaBridge | 171:3a7713b1edbc | 2734 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 |
AnnaBridge | 171:3a7713b1edbc | 2735 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 |
AnnaBridge | 171:3a7713b1edbc | 2736 | * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 |
AnnaBridge | 171:3a7713b1edbc | 2737 | * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 |
AnnaBridge | 171:3a7713b1edbc | 2738 | * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 |
AnnaBridge | 171:3a7713b1edbc | 2739 | * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 |
AnnaBridge | 171:3a7713b1edbc | 2740 | * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 |
AnnaBridge | 171:3a7713b1edbc | 2741 | * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 |
AnnaBridge | 171:3a7713b1edbc | 2742 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 |
AnnaBridge | 171:3a7713b1edbc | 2743 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 |
AnnaBridge | 171:3a7713b1edbc | 2744 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 |
AnnaBridge | 171:3a7713b1edbc | 2745 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 |
AnnaBridge | 171:3a7713b1edbc | 2746 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 |
AnnaBridge | 171:3a7713b1edbc | 2747 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 |
AnnaBridge | 171:3a7713b1edbc | 2748 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2749 | */ |
AnnaBridge | 171:3a7713b1edbc | 2750 | __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) |
AnnaBridge | 171:3a7713b1edbc | 2751 | { |
AnnaBridge | 171:3a7713b1edbc | 2752 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 171:3a7713b1edbc | 2753 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 171:3a7713b1edbc | 2754 | MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); |
AnnaBridge | 171:3a7713b1edbc | 2755 | } |
AnnaBridge | 171:3a7713b1edbc | 2756 | |
AnnaBridge | 171:3a7713b1edbc | 2757 | /** |
AnnaBridge | 171:3a7713b1edbc | 2758 | * @brief Get the input filter duration. |
AnnaBridge | 171:3a7713b1edbc | 2759 | * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n |
AnnaBridge | 171:3a7713b1edbc | 2760 | * CCMR1 IC2F LL_TIM_IC_GetFilter\n |
AnnaBridge | 171:3a7713b1edbc | 2761 | * CCMR2 IC3F LL_TIM_IC_GetFilter\n |
AnnaBridge | 171:3a7713b1edbc | 2762 | * CCMR2 IC4F LL_TIM_IC_GetFilter |
AnnaBridge | 171:3a7713b1edbc | 2763 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2764 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2765 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 171:3a7713b1edbc | 2766 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 171:3a7713b1edbc | 2767 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 171:3a7713b1edbc | 2768 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 171:3a7713b1edbc | 2769 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2770 | * @arg @ref LL_TIM_IC_FILTER_FDIV1 |
AnnaBridge | 171:3a7713b1edbc | 2771 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 |
AnnaBridge | 171:3a7713b1edbc | 2772 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 |
AnnaBridge | 171:3a7713b1edbc | 2773 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 |
AnnaBridge | 171:3a7713b1edbc | 2774 | * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 |
AnnaBridge | 171:3a7713b1edbc | 2775 | * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 |
AnnaBridge | 171:3a7713b1edbc | 2776 | * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 |
AnnaBridge | 171:3a7713b1edbc | 2777 | * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 |
AnnaBridge | 171:3a7713b1edbc | 2778 | * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 |
AnnaBridge | 171:3a7713b1edbc | 2779 | * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 |
AnnaBridge | 171:3a7713b1edbc | 2780 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 |
AnnaBridge | 171:3a7713b1edbc | 2781 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 |
AnnaBridge | 171:3a7713b1edbc | 2782 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 |
AnnaBridge | 171:3a7713b1edbc | 2783 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 |
AnnaBridge | 171:3a7713b1edbc | 2784 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 |
AnnaBridge | 171:3a7713b1edbc | 2785 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 |
AnnaBridge | 171:3a7713b1edbc | 2786 | */ |
AnnaBridge | 171:3a7713b1edbc | 2787 | __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 2788 | { |
AnnaBridge | 171:3a7713b1edbc | 2789 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 171:3a7713b1edbc | 2790 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
AnnaBridge | 171:3a7713b1edbc | 2791 | return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); |
AnnaBridge | 171:3a7713b1edbc | 2792 | } |
AnnaBridge | 171:3a7713b1edbc | 2793 | |
AnnaBridge | 171:3a7713b1edbc | 2794 | /** |
AnnaBridge | 171:3a7713b1edbc | 2795 | * @brief Set the input channel polarity. |
AnnaBridge | 171:3a7713b1edbc | 2796 | * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n |
AnnaBridge | 171:3a7713b1edbc | 2797 | * CCER CC1NP LL_TIM_IC_SetPolarity\n |
AnnaBridge | 171:3a7713b1edbc | 2798 | * CCER CC2P LL_TIM_IC_SetPolarity\n |
AnnaBridge | 171:3a7713b1edbc | 2799 | * CCER CC2NP LL_TIM_IC_SetPolarity\n |
AnnaBridge | 171:3a7713b1edbc | 2800 | * CCER CC3P LL_TIM_IC_SetPolarity\n |
AnnaBridge | 171:3a7713b1edbc | 2801 | * CCER CC3NP LL_TIM_IC_SetPolarity\n |
AnnaBridge | 171:3a7713b1edbc | 2802 | * CCER CC4P LL_TIM_IC_SetPolarity\n |
AnnaBridge | 171:3a7713b1edbc | 2803 | * CCER CC4NP LL_TIM_IC_SetPolarity |
AnnaBridge | 171:3a7713b1edbc | 2804 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2805 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2806 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 171:3a7713b1edbc | 2807 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 171:3a7713b1edbc | 2808 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 171:3a7713b1edbc | 2809 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 171:3a7713b1edbc | 2810 | * @param ICPolarity This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2811 | * @arg @ref LL_TIM_IC_POLARITY_RISING |
AnnaBridge | 171:3a7713b1edbc | 2812 | * @arg @ref LL_TIM_IC_POLARITY_FALLING |
AnnaBridge | 171:3a7713b1edbc | 2813 | * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE |
AnnaBridge | 171:3a7713b1edbc | 2814 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2815 | */ |
AnnaBridge | 171:3a7713b1edbc | 2816 | __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) |
AnnaBridge | 171:3a7713b1edbc | 2817 | { |
AnnaBridge | 171:3a7713b1edbc | 2818 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 171:3a7713b1edbc | 2819 | MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), |
AnnaBridge | 171:3a7713b1edbc | 2820 | ICPolarity << SHIFT_TAB_CCxP[iChannel]); |
AnnaBridge | 171:3a7713b1edbc | 2821 | } |
AnnaBridge | 171:3a7713b1edbc | 2822 | |
AnnaBridge | 171:3a7713b1edbc | 2823 | /** |
AnnaBridge | 171:3a7713b1edbc | 2824 | * @brief Get the current input channel polarity. |
AnnaBridge | 171:3a7713b1edbc | 2825 | * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n |
AnnaBridge | 171:3a7713b1edbc | 2826 | * CCER CC1NP LL_TIM_IC_GetPolarity\n |
AnnaBridge | 171:3a7713b1edbc | 2827 | * CCER CC2P LL_TIM_IC_GetPolarity\n |
AnnaBridge | 171:3a7713b1edbc | 2828 | * CCER CC2NP LL_TIM_IC_GetPolarity\n |
AnnaBridge | 171:3a7713b1edbc | 2829 | * CCER CC3P LL_TIM_IC_GetPolarity\n |
AnnaBridge | 171:3a7713b1edbc | 2830 | * CCER CC3NP LL_TIM_IC_GetPolarity\n |
AnnaBridge | 171:3a7713b1edbc | 2831 | * CCER CC4P LL_TIM_IC_GetPolarity\n |
AnnaBridge | 171:3a7713b1edbc | 2832 | * CCER CC4NP LL_TIM_IC_GetPolarity |
AnnaBridge | 171:3a7713b1edbc | 2833 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2834 | * @param Channel This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2835 | * @arg @ref LL_TIM_CHANNEL_CH1 |
AnnaBridge | 171:3a7713b1edbc | 2836 | * @arg @ref LL_TIM_CHANNEL_CH2 |
AnnaBridge | 171:3a7713b1edbc | 2837 | * @arg @ref LL_TIM_CHANNEL_CH3 |
AnnaBridge | 171:3a7713b1edbc | 2838 | * @arg @ref LL_TIM_CHANNEL_CH4 |
AnnaBridge | 171:3a7713b1edbc | 2839 | * @retval Returned value can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 2840 | * @arg @ref LL_TIM_IC_POLARITY_RISING |
AnnaBridge | 171:3a7713b1edbc | 2841 | * @arg @ref LL_TIM_IC_POLARITY_FALLING |
AnnaBridge | 171:3a7713b1edbc | 2842 | * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE |
AnnaBridge | 171:3a7713b1edbc | 2843 | */ |
AnnaBridge | 171:3a7713b1edbc | 2844 | __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) |
AnnaBridge | 171:3a7713b1edbc | 2845 | { |
AnnaBridge | 171:3a7713b1edbc | 2846 | register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
AnnaBridge | 171:3a7713b1edbc | 2847 | return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> |
AnnaBridge | 171:3a7713b1edbc | 2848 | SHIFT_TAB_CCxP[iChannel]); |
AnnaBridge | 171:3a7713b1edbc | 2849 | } |
AnnaBridge | 171:3a7713b1edbc | 2850 | |
AnnaBridge | 171:3a7713b1edbc | 2851 | /** |
AnnaBridge | 171:3a7713b1edbc | 2852 | * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). |
AnnaBridge | 171:3a7713b1edbc | 2853 | * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 2854 | * a timer instance provides an XOR input. |
AnnaBridge | 171:3a7713b1edbc | 2855 | * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination |
AnnaBridge | 171:3a7713b1edbc | 2856 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2857 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2858 | */ |
AnnaBridge | 171:3a7713b1edbc | 2859 | __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 2860 | { |
AnnaBridge | 171:3a7713b1edbc | 2861 | SET_BIT(TIMx->CR2, TIM_CR2_TI1S); |
AnnaBridge | 171:3a7713b1edbc | 2862 | } |
AnnaBridge | 171:3a7713b1edbc | 2863 | |
AnnaBridge | 171:3a7713b1edbc | 2864 | /** |
AnnaBridge | 171:3a7713b1edbc | 2865 | * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. |
AnnaBridge | 171:3a7713b1edbc | 2866 | * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 2867 | * a timer instance provides an XOR input. |
AnnaBridge | 171:3a7713b1edbc | 2868 | * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination |
AnnaBridge | 171:3a7713b1edbc | 2869 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2870 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2871 | */ |
AnnaBridge | 171:3a7713b1edbc | 2872 | __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 2873 | { |
AnnaBridge | 171:3a7713b1edbc | 2874 | CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); |
AnnaBridge | 171:3a7713b1edbc | 2875 | } |
AnnaBridge | 171:3a7713b1edbc | 2876 | |
AnnaBridge | 171:3a7713b1edbc | 2877 | /** |
AnnaBridge | 171:3a7713b1edbc | 2878 | * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. |
AnnaBridge | 171:3a7713b1edbc | 2879 | * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 2880 | * a timer instance provides an XOR input. |
AnnaBridge | 171:3a7713b1edbc | 2881 | * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination |
AnnaBridge | 171:3a7713b1edbc | 2882 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2883 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2884 | */ |
AnnaBridge | 171:3a7713b1edbc | 2885 | __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 2886 | { |
AnnaBridge | 171:3a7713b1edbc | 2887 | return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)); |
AnnaBridge | 171:3a7713b1edbc | 2888 | } |
AnnaBridge | 171:3a7713b1edbc | 2889 | |
AnnaBridge | 171:3a7713b1edbc | 2890 | /** |
AnnaBridge | 171:3a7713b1edbc | 2891 | * @brief Get captured value for input channel 1. |
AnnaBridge | 171:3a7713b1edbc | 2892 | * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. |
AnnaBridge | 171:3a7713b1edbc | 2893 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
AnnaBridge | 171:3a7713b1edbc | 2894 | * whether or not a timer instance supports a 32 bits counter. |
AnnaBridge | 171:3a7713b1edbc | 2895 | * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 2896 | * input channel 1 is supported by a timer instance. |
AnnaBridge | 171:3a7713b1edbc | 2897 | * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 |
AnnaBridge | 171:3a7713b1edbc | 2898 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2899 | * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) |
AnnaBridge | 171:3a7713b1edbc | 2900 | */ |
AnnaBridge | 171:3a7713b1edbc | 2901 | __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 2902 | { |
AnnaBridge | 171:3a7713b1edbc | 2903 | return (uint32_t)(READ_REG(TIMx->CCR1)); |
AnnaBridge | 171:3a7713b1edbc | 2904 | } |
AnnaBridge | 171:3a7713b1edbc | 2905 | |
AnnaBridge | 171:3a7713b1edbc | 2906 | /** |
AnnaBridge | 171:3a7713b1edbc | 2907 | * @brief Get captured value for input channel 2. |
AnnaBridge | 171:3a7713b1edbc | 2908 | * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. |
AnnaBridge | 171:3a7713b1edbc | 2909 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
AnnaBridge | 171:3a7713b1edbc | 2910 | * whether or not a timer instance supports a 32 bits counter. |
AnnaBridge | 171:3a7713b1edbc | 2911 | * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 2912 | * input channel 2 is supported by a timer instance. |
AnnaBridge | 171:3a7713b1edbc | 2913 | * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 |
AnnaBridge | 171:3a7713b1edbc | 2914 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2915 | * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) |
AnnaBridge | 171:3a7713b1edbc | 2916 | */ |
AnnaBridge | 171:3a7713b1edbc | 2917 | __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 2918 | { |
AnnaBridge | 171:3a7713b1edbc | 2919 | return (uint32_t)(READ_REG(TIMx->CCR2)); |
AnnaBridge | 171:3a7713b1edbc | 2920 | } |
AnnaBridge | 171:3a7713b1edbc | 2921 | |
AnnaBridge | 171:3a7713b1edbc | 2922 | /** |
AnnaBridge | 171:3a7713b1edbc | 2923 | * @brief Get captured value for input channel 3. |
AnnaBridge | 171:3a7713b1edbc | 2924 | * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. |
AnnaBridge | 171:3a7713b1edbc | 2925 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
AnnaBridge | 171:3a7713b1edbc | 2926 | * whether or not a timer instance supports a 32 bits counter. |
AnnaBridge | 171:3a7713b1edbc | 2927 | * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 2928 | * input channel 3 is supported by a timer instance. |
AnnaBridge | 171:3a7713b1edbc | 2929 | * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 |
AnnaBridge | 171:3a7713b1edbc | 2930 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2931 | * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) |
AnnaBridge | 171:3a7713b1edbc | 2932 | */ |
AnnaBridge | 171:3a7713b1edbc | 2933 | __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 2934 | { |
AnnaBridge | 171:3a7713b1edbc | 2935 | return (uint32_t)(READ_REG(TIMx->CCR3)); |
AnnaBridge | 171:3a7713b1edbc | 2936 | } |
AnnaBridge | 171:3a7713b1edbc | 2937 | |
AnnaBridge | 171:3a7713b1edbc | 2938 | /** |
AnnaBridge | 171:3a7713b1edbc | 2939 | * @brief Get captured value for input channel 4. |
AnnaBridge | 171:3a7713b1edbc | 2940 | * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. |
AnnaBridge | 171:3a7713b1edbc | 2941 | * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check |
AnnaBridge | 171:3a7713b1edbc | 2942 | * whether or not a timer instance supports a 32 bits counter. |
AnnaBridge | 171:3a7713b1edbc | 2943 | * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 2944 | * input channel 4 is supported by a timer instance. |
AnnaBridge | 171:3a7713b1edbc | 2945 | * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 |
AnnaBridge | 171:3a7713b1edbc | 2946 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2947 | * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) |
AnnaBridge | 171:3a7713b1edbc | 2948 | */ |
AnnaBridge | 171:3a7713b1edbc | 2949 | __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 2950 | { |
AnnaBridge | 171:3a7713b1edbc | 2951 | return (uint32_t)(READ_REG(TIMx->CCR4)); |
AnnaBridge | 171:3a7713b1edbc | 2952 | } |
AnnaBridge | 171:3a7713b1edbc | 2953 | |
AnnaBridge | 171:3a7713b1edbc | 2954 | /** |
AnnaBridge | 171:3a7713b1edbc | 2955 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2956 | */ |
AnnaBridge | 171:3a7713b1edbc | 2957 | |
AnnaBridge | 171:3a7713b1edbc | 2958 | /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection |
AnnaBridge | 171:3a7713b1edbc | 2959 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 2960 | */ |
AnnaBridge | 171:3a7713b1edbc | 2961 | /** |
AnnaBridge | 171:3a7713b1edbc | 2962 | * @brief Enable external clock mode 2. |
AnnaBridge | 171:3a7713b1edbc | 2963 | * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. |
AnnaBridge | 171:3a7713b1edbc | 2964 | * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check |
AnnaBridge | 171:3a7713b1edbc | 2965 | * whether or not a timer instance supports external clock mode2. |
AnnaBridge | 171:3a7713b1edbc | 2966 | * @rmtoll SMCR ECE LL_TIM_EnableExternalClock |
AnnaBridge | 171:3a7713b1edbc | 2967 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2968 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2969 | */ |
AnnaBridge | 171:3a7713b1edbc | 2970 | __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 2971 | { |
AnnaBridge | 171:3a7713b1edbc | 2972 | SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); |
AnnaBridge | 171:3a7713b1edbc | 2973 | } |
AnnaBridge | 171:3a7713b1edbc | 2974 | |
AnnaBridge | 171:3a7713b1edbc | 2975 | /** |
AnnaBridge | 171:3a7713b1edbc | 2976 | * @brief Disable external clock mode 2. |
AnnaBridge | 171:3a7713b1edbc | 2977 | * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check |
AnnaBridge | 171:3a7713b1edbc | 2978 | * whether or not a timer instance supports external clock mode2. |
AnnaBridge | 171:3a7713b1edbc | 2979 | * @rmtoll SMCR ECE LL_TIM_DisableExternalClock |
AnnaBridge | 171:3a7713b1edbc | 2980 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2981 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 2982 | */ |
AnnaBridge | 171:3a7713b1edbc | 2983 | __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 2984 | { |
AnnaBridge | 171:3a7713b1edbc | 2985 | CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); |
AnnaBridge | 171:3a7713b1edbc | 2986 | } |
AnnaBridge | 171:3a7713b1edbc | 2987 | |
AnnaBridge | 171:3a7713b1edbc | 2988 | /** |
AnnaBridge | 171:3a7713b1edbc | 2989 | * @brief Indicate whether external clock mode 2 is enabled. |
AnnaBridge | 171:3a7713b1edbc | 2990 | * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check |
AnnaBridge | 171:3a7713b1edbc | 2991 | * whether or not a timer instance supports external clock mode2. |
AnnaBridge | 171:3a7713b1edbc | 2992 | * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock |
AnnaBridge | 171:3a7713b1edbc | 2993 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 2994 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 2995 | */ |
AnnaBridge | 171:3a7713b1edbc | 2996 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 2997 | { |
AnnaBridge | 171:3a7713b1edbc | 2998 | return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)); |
AnnaBridge | 171:3a7713b1edbc | 2999 | } |
AnnaBridge | 171:3a7713b1edbc | 3000 | |
AnnaBridge | 171:3a7713b1edbc | 3001 | /** |
AnnaBridge | 171:3a7713b1edbc | 3002 | * @brief Set the clock source of the counter clock. |
AnnaBridge | 171:3a7713b1edbc | 3003 | * @note when selected clock source is external clock mode 1, the timer input |
AnnaBridge | 171:3a7713b1edbc | 3004 | * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() |
AnnaBridge | 171:3a7713b1edbc | 3005 | * function. This timer input must be configured by calling |
AnnaBridge | 171:3a7713b1edbc | 3006 | * the @ref LL_TIM_IC_Config() function. |
AnnaBridge | 171:3a7713b1edbc | 3007 | * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check |
AnnaBridge | 171:3a7713b1edbc | 3008 | * whether or not a timer instance supports external clock mode1. |
AnnaBridge | 171:3a7713b1edbc | 3009 | * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check |
AnnaBridge | 171:3a7713b1edbc | 3010 | * whether or not a timer instance supports external clock mode2. |
AnnaBridge | 171:3a7713b1edbc | 3011 | * @rmtoll SMCR SMS LL_TIM_SetClockSource\n |
AnnaBridge | 171:3a7713b1edbc | 3012 | * SMCR ECE LL_TIM_SetClockSource |
AnnaBridge | 171:3a7713b1edbc | 3013 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3014 | * @param ClockSource This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3015 | * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL |
AnnaBridge | 171:3a7713b1edbc | 3016 | * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 |
AnnaBridge | 171:3a7713b1edbc | 3017 | * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 |
AnnaBridge | 171:3a7713b1edbc | 3018 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3019 | */ |
AnnaBridge | 171:3a7713b1edbc | 3020 | __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) |
AnnaBridge | 171:3a7713b1edbc | 3021 | { |
AnnaBridge | 171:3a7713b1edbc | 3022 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); |
AnnaBridge | 171:3a7713b1edbc | 3023 | } |
AnnaBridge | 171:3a7713b1edbc | 3024 | |
AnnaBridge | 171:3a7713b1edbc | 3025 | /** |
AnnaBridge | 171:3a7713b1edbc | 3026 | * @brief Set the encoder interface mode. |
AnnaBridge | 171:3a7713b1edbc | 3027 | * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check |
AnnaBridge | 171:3a7713b1edbc | 3028 | * whether or not a timer instance supports the encoder mode. |
AnnaBridge | 171:3a7713b1edbc | 3029 | * @rmtoll SMCR SMS LL_TIM_SetEncoderMode |
AnnaBridge | 171:3a7713b1edbc | 3030 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3031 | * @param EncoderMode This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3032 | * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 |
AnnaBridge | 171:3a7713b1edbc | 3033 | * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 |
AnnaBridge | 171:3a7713b1edbc | 3034 | * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 |
AnnaBridge | 171:3a7713b1edbc | 3035 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3036 | */ |
AnnaBridge | 171:3a7713b1edbc | 3037 | __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) |
AnnaBridge | 171:3a7713b1edbc | 3038 | { |
AnnaBridge | 171:3a7713b1edbc | 3039 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); |
AnnaBridge | 171:3a7713b1edbc | 3040 | } |
AnnaBridge | 171:3a7713b1edbc | 3041 | |
AnnaBridge | 171:3a7713b1edbc | 3042 | /** |
AnnaBridge | 171:3a7713b1edbc | 3043 | * @} |
AnnaBridge | 171:3a7713b1edbc | 3044 | */ |
AnnaBridge | 171:3a7713b1edbc | 3045 | |
AnnaBridge | 171:3a7713b1edbc | 3046 | /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration |
AnnaBridge | 171:3a7713b1edbc | 3047 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 3048 | */ |
AnnaBridge | 171:3a7713b1edbc | 3049 | /** |
AnnaBridge | 171:3a7713b1edbc | 3050 | * @brief Set the trigger output (TRGO) used for timer synchronization . |
AnnaBridge | 171:3a7713b1edbc | 3051 | * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check |
AnnaBridge | 171:3a7713b1edbc | 3052 | * whether or not a timer instance can operate as a master timer. |
AnnaBridge | 171:3a7713b1edbc | 3053 | * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput |
AnnaBridge | 171:3a7713b1edbc | 3054 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3055 | * @param TimerSynchronization This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3056 | * @arg @ref LL_TIM_TRGO_RESET |
AnnaBridge | 171:3a7713b1edbc | 3057 | * @arg @ref LL_TIM_TRGO_ENABLE |
AnnaBridge | 171:3a7713b1edbc | 3058 | * @arg @ref LL_TIM_TRGO_UPDATE |
AnnaBridge | 171:3a7713b1edbc | 3059 | * @arg @ref LL_TIM_TRGO_CC1IF |
AnnaBridge | 171:3a7713b1edbc | 3060 | * @arg @ref LL_TIM_TRGO_OC1REF |
AnnaBridge | 171:3a7713b1edbc | 3061 | * @arg @ref LL_TIM_TRGO_OC2REF |
AnnaBridge | 171:3a7713b1edbc | 3062 | * @arg @ref LL_TIM_TRGO_OC3REF |
AnnaBridge | 171:3a7713b1edbc | 3063 | * @arg @ref LL_TIM_TRGO_OC4REF |
AnnaBridge | 171:3a7713b1edbc | 3064 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3065 | */ |
AnnaBridge | 171:3a7713b1edbc | 3066 | __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) |
AnnaBridge | 171:3a7713b1edbc | 3067 | { |
AnnaBridge | 171:3a7713b1edbc | 3068 | MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); |
AnnaBridge | 171:3a7713b1edbc | 3069 | } |
AnnaBridge | 171:3a7713b1edbc | 3070 | |
AnnaBridge | 171:3a7713b1edbc | 3071 | /** |
AnnaBridge | 171:3a7713b1edbc | 3072 | * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization . |
AnnaBridge | 171:3a7713b1edbc | 3073 | * @note Macro @ref IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check |
AnnaBridge | 171:3a7713b1edbc | 3074 | * whether or not a timer instance can be used for ADC synchronization. |
AnnaBridge | 171:3a7713b1edbc | 3075 | * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2 |
AnnaBridge | 171:3a7713b1edbc | 3076 | * @param TIMx Timer Instance |
AnnaBridge | 171:3a7713b1edbc | 3077 | * @param ADCSynchronization This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3078 | * @arg @ref LL_TIM_TRGO2_RESET |
AnnaBridge | 171:3a7713b1edbc | 3079 | * @arg @ref LL_TIM_TRGO2_ENABLE |
AnnaBridge | 171:3a7713b1edbc | 3080 | * @arg @ref LL_TIM_TRGO2_UPDATE |
AnnaBridge | 171:3a7713b1edbc | 3081 | * @arg @ref LL_TIM_TRGO2_CC1F |
AnnaBridge | 171:3a7713b1edbc | 3082 | * @arg @ref LL_TIM_TRGO2_OC1 |
AnnaBridge | 171:3a7713b1edbc | 3083 | * @arg @ref LL_TIM_TRGO2_OC2 |
AnnaBridge | 171:3a7713b1edbc | 3084 | * @arg @ref LL_TIM_TRGO2_OC3 |
AnnaBridge | 171:3a7713b1edbc | 3085 | * @arg @ref LL_TIM_TRGO2_OC4 |
AnnaBridge | 171:3a7713b1edbc | 3086 | * @arg @ref LL_TIM_TRGO2_OC5 |
AnnaBridge | 171:3a7713b1edbc | 3087 | * @arg @ref LL_TIM_TRGO2_OC6 |
AnnaBridge | 171:3a7713b1edbc | 3088 | * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING |
AnnaBridge | 171:3a7713b1edbc | 3089 | * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING |
AnnaBridge | 171:3a7713b1edbc | 3090 | * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING |
AnnaBridge | 171:3a7713b1edbc | 3091 | * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING |
AnnaBridge | 171:3a7713b1edbc | 3092 | * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING |
AnnaBridge | 171:3a7713b1edbc | 3093 | * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING |
AnnaBridge | 171:3a7713b1edbc | 3094 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3095 | */ |
AnnaBridge | 171:3a7713b1edbc | 3096 | __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization) |
AnnaBridge | 171:3a7713b1edbc | 3097 | { |
AnnaBridge | 171:3a7713b1edbc | 3098 | MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization); |
AnnaBridge | 171:3a7713b1edbc | 3099 | } |
AnnaBridge | 171:3a7713b1edbc | 3100 | |
AnnaBridge | 171:3a7713b1edbc | 3101 | /** |
AnnaBridge | 171:3a7713b1edbc | 3102 | * @brief Set the synchronization mode of a slave timer. |
AnnaBridge | 171:3a7713b1edbc | 3103 | * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 3104 | * a timer instance can operate as a slave timer. |
AnnaBridge | 171:3a7713b1edbc | 3105 | * @rmtoll SMCR SMS LL_TIM_SetSlaveMode |
AnnaBridge | 171:3a7713b1edbc | 3106 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3107 | * @param SlaveMode This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3108 | * @arg @ref LL_TIM_SLAVEMODE_DISABLED |
AnnaBridge | 171:3a7713b1edbc | 3109 | * @arg @ref LL_TIM_SLAVEMODE_RESET |
AnnaBridge | 171:3a7713b1edbc | 3110 | * @arg @ref LL_TIM_SLAVEMODE_GATED |
AnnaBridge | 171:3a7713b1edbc | 3111 | * @arg @ref LL_TIM_SLAVEMODE_TRIGGER |
AnnaBridge | 171:3a7713b1edbc | 3112 | * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER |
AnnaBridge | 171:3a7713b1edbc | 3113 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3114 | */ |
AnnaBridge | 171:3a7713b1edbc | 3115 | __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) |
AnnaBridge | 171:3a7713b1edbc | 3116 | { |
AnnaBridge | 171:3a7713b1edbc | 3117 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); |
AnnaBridge | 171:3a7713b1edbc | 3118 | } |
AnnaBridge | 171:3a7713b1edbc | 3119 | |
AnnaBridge | 171:3a7713b1edbc | 3120 | /** |
AnnaBridge | 171:3a7713b1edbc | 3121 | * @brief Set the selects the trigger input to be used to synchronize the counter. |
AnnaBridge | 171:3a7713b1edbc | 3122 | * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 3123 | * a timer instance can operate as a slave timer. |
AnnaBridge | 171:3a7713b1edbc | 3124 | * @rmtoll SMCR TS LL_TIM_SetTriggerInput |
AnnaBridge | 171:3a7713b1edbc | 3125 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3126 | * @param TriggerInput This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3127 | * @arg @ref LL_TIM_TS_ITR0 |
AnnaBridge | 171:3a7713b1edbc | 3128 | * @arg @ref LL_TIM_TS_ITR1 |
AnnaBridge | 171:3a7713b1edbc | 3129 | * @arg @ref LL_TIM_TS_ITR2 |
AnnaBridge | 171:3a7713b1edbc | 3130 | * @arg @ref LL_TIM_TS_ITR3 |
AnnaBridge | 171:3a7713b1edbc | 3131 | * @arg @ref LL_TIM_TS_TI1F_ED |
AnnaBridge | 171:3a7713b1edbc | 3132 | * @arg @ref LL_TIM_TS_TI1FP1 |
AnnaBridge | 171:3a7713b1edbc | 3133 | * @arg @ref LL_TIM_TS_TI2FP2 |
AnnaBridge | 171:3a7713b1edbc | 3134 | * @arg @ref LL_TIM_TS_ETRF |
AnnaBridge | 171:3a7713b1edbc | 3135 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3136 | */ |
AnnaBridge | 171:3a7713b1edbc | 3137 | __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) |
AnnaBridge | 171:3a7713b1edbc | 3138 | { |
AnnaBridge | 171:3a7713b1edbc | 3139 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); |
AnnaBridge | 171:3a7713b1edbc | 3140 | } |
AnnaBridge | 171:3a7713b1edbc | 3141 | |
AnnaBridge | 171:3a7713b1edbc | 3142 | /** |
AnnaBridge | 171:3a7713b1edbc | 3143 | * @brief Enable the Master/Slave mode. |
AnnaBridge | 171:3a7713b1edbc | 3144 | * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 3145 | * a timer instance can operate as a slave timer. |
AnnaBridge | 171:3a7713b1edbc | 3146 | * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode |
AnnaBridge | 171:3a7713b1edbc | 3147 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3148 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3149 | */ |
AnnaBridge | 171:3a7713b1edbc | 3150 | __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3151 | { |
AnnaBridge | 171:3a7713b1edbc | 3152 | SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); |
AnnaBridge | 171:3a7713b1edbc | 3153 | } |
AnnaBridge | 171:3a7713b1edbc | 3154 | |
AnnaBridge | 171:3a7713b1edbc | 3155 | /** |
AnnaBridge | 171:3a7713b1edbc | 3156 | * @brief Disable the Master/Slave mode. |
AnnaBridge | 171:3a7713b1edbc | 3157 | * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 3158 | * a timer instance can operate as a slave timer. |
AnnaBridge | 171:3a7713b1edbc | 3159 | * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode |
AnnaBridge | 171:3a7713b1edbc | 3160 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3161 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3162 | */ |
AnnaBridge | 171:3a7713b1edbc | 3163 | __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3164 | { |
AnnaBridge | 171:3a7713b1edbc | 3165 | CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); |
AnnaBridge | 171:3a7713b1edbc | 3166 | } |
AnnaBridge | 171:3a7713b1edbc | 3167 | |
AnnaBridge | 171:3a7713b1edbc | 3168 | /** |
AnnaBridge | 171:3a7713b1edbc | 3169 | * @brief Indicates whether the Master/Slave mode is enabled. |
AnnaBridge | 171:3a7713b1edbc | 3170 | * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 3171 | * a timer instance can operate as a slave timer. |
AnnaBridge | 171:3a7713b1edbc | 3172 | * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode |
AnnaBridge | 171:3a7713b1edbc | 3173 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3174 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 3175 | */ |
AnnaBridge | 171:3a7713b1edbc | 3176 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3177 | { |
AnnaBridge | 171:3a7713b1edbc | 3178 | return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)); |
AnnaBridge | 171:3a7713b1edbc | 3179 | } |
AnnaBridge | 171:3a7713b1edbc | 3180 | |
AnnaBridge | 171:3a7713b1edbc | 3181 | /** |
AnnaBridge | 171:3a7713b1edbc | 3182 | * @brief Configure the external trigger (ETR) input. |
AnnaBridge | 171:3a7713b1edbc | 3183 | * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 3184 | * a timer instance provides an external trigger input. |
AnnaBridge | 171:3a7713b1edbc | 3185 | * @rmtoll SMCR ETP LL_TIM_ConfigETR\n |
AnnaBridge | 171:3a7713b1edbc | 3186 | * SMCR ETPS LL_TIM_ConfigETR\n |
AnnaBridge | 171:3a7713b1edbc | 3187 | * SMCR ETF LL_TIM_ConfigETR |
AnnaBridge | 171:3a7713b1edbc | 3188 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3189 | * @param ETRPolarity This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3190 | * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED |
AnnaBridge | 171:3a7713b1edbc | 3191 | * @arg @ref LL_TIM_ETR_POLARITY_INVERTED |
AnnaBridge | 171:3a7713b1edbc | 3192 | * @param ETRPrescaler This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3193 | * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 |
AnnaBridge | 171:3a7713b1edbc | 3194 | * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 |
AnnaBridge | 171:3a7713b1edbc | 3195 | * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 |
AnnaBridge | 171:3a7713b1edbc | 3196 | * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 |
AnnaBridge | 171:3a7713b1edbc | 3197 | * @param ETRFilter This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3198 | * @arg @ref LL_TIM_ETR_FILTER_FDIV1 |
AnnaBridge | 171:3a7713b1edbc | 3199 | * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 |
AnnaBridge | 171:3a7713b1edbc | 3200 | * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 |
AnnaBridge | 171:3a7713b1edbc | 3201 | * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 |
AnnaBridge | 171:3a7713b1edbc | 3202 | * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 |
AnnaBridge | 171:3a7713b1edbc | 3203 | * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 |
AnnaBridge | 171:3a7713b1edbc | 3204 | * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 |
AnnaBridge | 171:3a7713b1edbc | 3205 | * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 |
AnnaBridge | 171:3a7713b1edbc | 3206 | * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 |
AnnaBridge | 171:3a7713b1edbc | 3207 | * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 |
AnnaBridge | 171:3a7713b1edbc | 3208 | * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 |
AnnaBridge | 171:3a7713b1edbc | 3209 | * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 |
AnnaBridge | 171:3a7713b1edbc | 3210 | * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 |
AnnaBridge | 171:3a7713b1edbc | 3211 | * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 |
AnnaBridge | 171:3a7713b1edbc | 3212 | * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 |
AnnaBridge | 171:3a7713b1edbc | 3213 | * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 |
AnnaBridge | 171:3a7713b1edbc | 3214 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3215 | */ |
AnnaBridge | 171:3a7713b1edbc | 3216 | __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, |
AnnaBridge | 171:3a7713b1edbc | 3217 | uint32_t ETRFilter) |
AnnaBridge | 171:3a7713b1edbc | 3218 | { |
AnnaBridge | 171:3a7713b1edbc | 3219 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter); |
AnnaBridge | 171:3a7713b1edbc | 3220 | } |
AnnaBridge | 171:3a7713b1edbc | 3221 | |
AnnaBridge | 171:3a7713b1edbc | 3222 | /** |
AnnaBridge | 171:3a7713b1edbc | 3223 | * @} |
AnnaBridge | 171:3a7713b1edbc | 3224 | */ |
AnnaBridge | 171:3a7713b1edbc | 3225 | |
AnnaBridge | 171:3a7713b1edbc | 3226 | /** @defgroup TIM_LL_EF_Break_Function Break function configuration |
AnnaBridge | 171:3a7713b1edbc | 3227 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 3228 | */ |
AnnaBridge | 171:3a7713b1edbc | 3229 | /** |
AnnaBridge | 171:3a7713b1edbc | 3230 | * @brief Enable the break function. |
AnnaBridge | 171:3a7713b1edbc | 3231 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 3232 | * a timer instance provides a break input. |
AnnaBridge | 171:3a7713b1edbc | 3233 | * @rmtoll BDTR BKE LL_TIM_EnableBRK |
AnnaBridge | 171:3a7713b1edbc | 3234 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3235 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3236 | */ |
AnnaBridge | 171:3a7713b1edbc | 3237 | __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3238 | { |
AnnaBridge | 171:3a7713b1edbc | 3239 | SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); |
AnnaBridge | 171:3a7713b1edbc | 3240 | } |
AnnaBridge | 171:3a7713b1edbc | 3241 | |
AnnaBridge | 171:3a7713b1edbc | 3242 | /** |
AnnaBridge | 171:3a7713b1edbc | 3243 | * @brief Disable the break function. |
AnnaBridge | 171:3a7713b1edbc | 3244 | * @rmtoll BDTR BKE LL_TIM_DisableBRK |
AnnaBridge | 171:3a7713b1edbc | 3245 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3246 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 3247 | * a timer instance provides a break input. |
AnnaBridge | 171:3a7713b1edbc | 3248 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3249 | */ |
AnnaBridge | 171:3a7713b1edbc | 3250 | __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3251 | { |
AnnaBridge | 171:3a7713b1edbc | 3252 | CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); |
AnnaBridge | 171:3a7713b1edbc | 3253 | } |
AnnaBridge | 171:3a7713b1edbc | 3254 | |
AnnaBridge | 171:3a7713b1edbc | 3255 | /** |
AnnaBridge | 171:3a7713b1edbc | 3256 | * @brief Configure the break input. |
AnnaBridge | 171:3a7713b1edbc | 3257 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 3258 | * a timer instance provides a break input. |
AnnaBridge | 171:3a7713b1edbc | 3259 | * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n |
AnnaBridge | 171:3a7713b1edbc | 3260 | * BDTR BKF LL_TIM_ConfigBRK |
AnnaBridge | 171:3a7713b1edbc | 3261 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3262 | * @param BreakPolarity This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3263 | * @arg @ref LL_TIM_BREAK_POLARITY_LOW |
AnnaBridge | 171:3a7713b1edbc | 3264 | * @arg @ref LL_TIM_BREAK_POLARITY_HIGH |
AnnaBridge | 171:3a7713b1edbc | 3265 | * @param BreakFilter This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3266 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV1 |
AnnaBridge | 171:3a7713b1edbc | 3267 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2 |
AnnaBridge | 171:3a7713b1edbc | 3268 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4 |
AnnaBridge | 171:3a7713b1edbc | 3269 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8 |
AnnaBridge | 171:3a7713b1edbc | 3270 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6 |
AnnaBridge | 171:3a7713b1edbc | 3271 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8 |
AnnaBridge | 171:3a7713b1edbc | 3272 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6 |
AnnaBridge | 171:3a7713b1edbc | 3273 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8 |
AnnaBridge | 171:3a7713b1edbc | 3274 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6 |
AnnaBridge | 171:3a7713b1edbc | 3275 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8 |
AnnaBridge | 171:3a7713b1edbc | 3276 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5 |
AnnaBridge | 171:3a7713b1edbc | 3277 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6 |
AnnaBridge | 171:3a7713b1edbc | 3278 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8 |
AnnaBridge | 171:3a7713b1edbc | 3279 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5 |
AnnaBridge | 171:3a7713b1edbc | 3280 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6 |
AnnaBridge | 171:3a7713b1edbc | 3281 | * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 |
AnnaBridge | 171:3a7713b1edbc | 3282 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3283 | */ |
AnnaBridge | 171:3a7713b1edbc | 3284 | __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter) |
AnnaBridge | 171:3a7713b1edbc | 3285 | { |
AnnaBridge | 171:3a7713b1edbc | 3286 | MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter); |
AnnaBridge | 171:3a7713b1edbc | 3287 | } |
AnnaBridge | 171:3a7713b1edbc | 3288 | |
AnnaBridge | 171:3a7713b1edbc | 3289 | /** |
AnnaBridge | 171:3a7713b1edbc | 3290 | * @brief Enable the break 2 function. |
AnnaBridge | 171:3a7713b1edbc | 3291 | * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 3292 | * a timer instance provides a second break input. |
AnnaBridge | 171:3a7713b1edbc | 3293 | * @rmtoll BDTR BK2E LL_TIM_EnableBRK2 |
AnnaBridge | 171:3a7713b1edbc | 3294 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3295 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3296 | */ |
AnnaBridge | 171:3a7713b1edbc | 3297 | __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3298 | { |
AnnaBridge | 171:3a7713b1edbc | 3299 | SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E); |
AnnaBridge | 171:3a7713b1edbc | 3300 | } |
AnnaBridge | 171:3a7713b1edbc | 3301 | |
AnnaBridge | 171:3a7713b1edbc | 3302 | /** |
AnnaBridge | 171:3a7713b1edbc | 3303 | * @brief Disable the break 2 function. |
AnnaBridge | 171:3a7713b1edbc | 3304 | * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 3305 | * a timer instance provides a second break input. |
AnnaBridge | 171:3a7713b1edbc | 3306 | * @rmtoll BDTR BK2E LL_TIM_DisableBRK2 |
AnnaBridge | 171:3a7713b1edbc | 3307 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3308 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3309 | */ |
AnnaBridge | 171:3a7713b1edbc | 3310 | __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3311 | { |
AnnaBridge | 171:3a7713b1edbc | 3312 | CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E); |
AnnaBridge | 171:3a7713b1edbc | 3313 | } |
AnnaBridge | 171:3a7713b1edbc | 3314 | |
AnnaBridge | 171:3a7713b1edbc | 3315 | /** |
AnnaBridge | 171:3a7713b1edbc | 3316 | * @brief Configure the break 2 input. |
AnnaBridge | 171:3a7713b1edbc | 3317 | * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 3318 | * a timer instance provides a second break input. |
AnnaBridge | 171:3a7713b1edbc | 3319 | * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n |
AnnaBridge | 171:3a7713b1edbc | 3320 | * BDTR BK2F LL_TIM_ConfigBRK2 |
AnnaBridge | 171:3a7713b1edbc | 3321 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3322 | * @param Break2Polarity This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3323 | * @arg @ref LL_TIM_BREAK2_POLARITY_LOW |
AnnaBridge | 171:3a7713b1edbc | 3324 | * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH |
AnnaBridge | 171:3a7713b1edbc | 3325 | * @param Break2Filter This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3326 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1 |
AnnaBridge | 171:3a7713b1edbc | 3327 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2 |
AnnaBridge | 171:3a7713b1edbc | 3328 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4 |
AnnaBridge | 171:3a7713b1edbc | 3329 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8 |
AnnaBridge | 171:3a7713b1edbc | 3330 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6 |
AnnaBridge | 171:3a7713b1edbc | 3331 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8 |
AnnaBridge | 171:3a7713b1edbc | 3332 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6 |
AnnaBridge | 171:3a7713b1edbc | 3333 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8 |
AnnaBridge | 171:3a7713b1edbc | 3334 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6 |
AnnaBridge | 171:3a7713b1edbc | 3335 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8 |
AnnaBridge | 171:3a7713b1edbc | 3336 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5 |
AnnaBridge | 171:3a7713b1edbc | 3337 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6 |
AnnaBridge | 171:3a7713b1edbc | 3338 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8 |
AnnaBridge | 171:3a7713b1edbc | 3339 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5 |
AnnaBridge | 171:3a7713b1edbc | 3340 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6 |
AnnaBridge | 171:3a7713b1edbc | 3341 | * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8 |
AnnaBridge | 171:3a7713b1edbc | 3342 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3343 | */ |
AnnaBridge | 171:3a7713b1edbc | 3344 | __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter) |
AnnaBridge | 171:3a7713b1edbc | 3345 | { |
AnnaBridge | 171:3a7713b1edbc | 3346 | MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter); |
AnnaBridge | 171:3a7713b1edbc | 3347 | } |
AnnaBridge | 171:3a7713b1edbc | 3348 | |
AnnaBridge | 171:3a7713b1edbc | 3349 | /** |
AnnaBridge | 171:3a7713b1edbc | 3350 | * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. |
AnnaBridge | 171:3a7713b1edbc | 3351 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 3352 | * a timer instance provides a break input. |
AnnaBridge | 171:3a7713b1edbc | 3353 | * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n |
AnnaBridge | 171:3a7713b1edbc | 3354 | * BDTR OSSR LL_TIM_SetOffStates |
AnnaBridge | 171:3a7713b1edbc | 3355 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3356 | * @param OffStateIdle This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3357 | * @arg @ref LL_TIM_OSSI_DISABLE |
AnnaBridge | 171:3a7713b1edbc | 3358 | * @arg @ref LL_TIM_OSSI_ENABLE |
AnnaBridge | 171:3a7713b1edbc | 3359 | * @param OffStateRun This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3360 | * @arg @ref LL_TIM_OSSR_DISABLE |
AnnaBridge | 171:3a7713b1edbc | 3361 | * @arg @ref LL_TIM_OSSR_ENABLE |
AnnaBridge | 171:3a7713b1edbc | 3362 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3363 | */ |
AnnaBridge | 171:3a7713b1edbc | 3364 | __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun) |
AnnaBridge | 171:3a7713b1edbc | 3365 | { |
AnnaBridge | 171:3a7713b1edbc | 3366 | MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); |
AnnaBridge | 171:3a7713b1edbc | 3367 | } |
AnnaBridge | 171:3a7713b1edbc | 3368 | |
AnnaBridge | 171:3a7713b1edbc | 3369 | /** |
AnnaBridge | 171:3a7713b1edbc | 3370 | * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active). |
AnnaBridge | 171:3a7713b1edbc | 3371 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 3372 | * a timer instance provides a break input. |
AnnaBridge | 171:3a7713b1edbc | 3373 | * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput |
AnnaBridge | 171:3a7713b1edbc | 3374 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3375 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3376 | */ |
AnnaBridge | 171:3a7713b1edbc | 3377 | __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3378 | { |
AnnaBridge | 171:3a7713b1edbc | 3379 | SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); |
AnnaBridge | 171:3a7713b1edbc | 3380 | } |
AnnaBridge | 171:3a7713b1edbc | 3381 | |
AnnaBridge | 171:3a7713b1edbc | 3382 | /** |
AnnaBridge | 171:3a7713b1edbc | 3383 | * @brief Disable automatic output (MOE can be set only by software). |
AnnaBridge | 171:3a7713b1edbc | 3384 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 3385 | * a timer instance provides a break input. |
AnnaBridge | 171:3a7713b1edbc | 3386 | * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput |
AnnaBridge | 171:3a7713b1edbc | 3387 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3388 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3389 | */ |
AnnaBridge | 171:3a7713b1edbc | 3390 | __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3391 | { |
AnnaBridge | 171:3a7713b1edbc | 3392 | CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); |
AnnaBridge | 171:3a7713b1edbc | 3393 | } |
AnnaBridge | 171:3a7713b1edbc | 3394 | |
AnnaBridge | 171:3a7713b1edbc | 3395 | /** |
AnnaBridge | 171:3a7713b1edbc | 3396 | * @brief Indicate whether automatic output is enabled. |
AnnaBridge | 171:3a7713b1edbc | 3397 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 3398 | * a timer instance provides a break input. |
AnnaBridge | 171:3a7713b1edbc | 3399 | * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput |
AnnaBridge | 171:3a7713b1edbc | 3400 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3401 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 3402 | */ |
AnnaBridge | 171:3a7713b1edbc | 3403 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3404 | { |
AnnaBridge | 171:3a7713b1edbc | 3405 | return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)); |
AnnaBridge | 171:3a7713b1edbc | 3406 | } |
AnnaBridge | 171:3a7713b1edbc | 3407 | |
AnnaBridge | 171:3a7713b1edbc | 3408 | /** |
AnnaBridge | 171:3a7713b1edbc | 3409 | * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). |
AnnaBridge | 171:3a7713b1edbc | 3410 | * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by |
AnnaBridge | 171:3a7713b1edbc | 3411 | * software and is reset in case of break or break2 event |
AnnaBridge | 171:3a7713b1edbc | 3412 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 3413 | * a timer instance provides a break input. |
AnnaBridge | 171:3a7713b1edbc | 3414 | * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs |
AnnaBridge | 171:3a7713b1edbc | 3415 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3416 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3417 | */ |
AnnaBridge | 171:3a7713b1edbc | 3418 | __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3419 | { |
AnnaBridge | 171:3a7713b1edbc | 3420 | SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); |
AnnaBridge | 171:3a7713b1edbc | 3421 | } |
AnnaBridge | 171:3a7713b1edbc | 3422 | |
AnnaBridge | 171:3a7713b1edbc | 3423 | /** |
AnnaBridge | 171:3a7713b1edbc | 3424 | * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). |
AnnaBridge | 171:3a7713b1edbc | 3425 | * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by |
AnnaBridge | 171:3a7713b1edbc | 3426 | * software and is reset in case of break or break2 event. |
AnnaBridge | 171:3a7713b1edbc | 3427 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 3428 | * a timer instance provides a break input. |
AnnaBridge | 171:3a7713b1edbc | 3429 | * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs |
AnnaBridge | 171:3a7713b1edbc | 3430 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3431 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3432 | */ |
AnnaBridge | 171:3a7713b1edbc | 3433 | __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3434 | { |
AnnaBridge | 171:3a7713b1edbc | 3435 | CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); |
AnnaBridge | 171:3a7713b1edbc | 3436 | } |
AnnaBridge | 171:3a7713b1edbc | 3437 | |
AnnaBridge | 171:3a7713b1edbc | 3438 | /** |
AnnaBridge | 171:3a7713b1edbc | 3439 | * @brief Indicates whether outputs are enabled. |
AnnaBridge | 171:3a7713b1edbc | 3440 | * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 3441 | * a timer instance provides a break input. |
AnnaBridge | 171:3a7713b1edbc | 3442 | * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs |
AnnaBridge | 171:3a7713b1edbc | 3443 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3444 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 3445 | */ |
AnnaBridge | 171:3a7713b1edbc | 3446 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3447 | { |
AnnaBridge | 171:3a7713b1edbc | 3448 | return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)); |
AnnaBridge | 171:3a7713b1edbc | 3449 | } |
AnnaBridge | 171:3a7713b1edbc | 3450 | |
AnnaBridge | 171:3a7713b1edbc | 3451 | #if defined(TIM_BREAK_INPUT_SUPPORT) |
AnnaBridge | 171:3a7713b1edbc | 3452 | /** |
AnnaBridge | 171:3a7713b1edbc | 3453 | * @brief Enable the signals connected to the designated timer break input. |
AnnaBridge | 171:3a7713b1edbc | 3454 | * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether |
AnnaBridge | 171:3a7713b1edbc | 3455 | * or not a timer instance allows for break input selection. |
AnnaBridge | 171:3a7713b1edbc | 3456 | * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n |
AnnaBridge | 171:3a7713b1edbc | 3457 | * AF1 BKDFBKE LL_TIM_EnableBreakInputSource\n |
AnnaBridge | 171:3a7713b1edbc | 3458 | * AF2 BK2INE LL_TIM_EnableBreakInputSource\n |
AnnaBridge | 171:3a7713b1edbc | 3459 | * AF2 BK2DFBKE LL_TIM_EnableBreakInputSource |
AnnaBridge | 171:3a7713b1edbc | 3460 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3461 | * @param BreakInput This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3462 | * @arg @ref LL_TIM_BREAK_INPUT_BKIN |
AnnaBridge | 171:3a7713b1edbc | 3463 | * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 |
AnnaBridge | 171:3a7713b1edbc | 3464 | * @param Source This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3465 | * @arg @ref LL_TIM_BKIN_SOURCE_BKIN |
AnnaBridge | 171:3a7713b1edbc | 3466 | * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK |
AnnaBridge | 171:3a7713b1edbc | 3467 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3468 | */ |
AnnaBridge | 171:3a7713b1edbc | 3469 | __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) |
AnnaBridge | 171:3a7713b1edbc | 3470 | { |
AnnaBridge | 171:3a7713b1edbc | 3471 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); |
AnnaBridge | 171:3a7713b1edbc | 3472 | SET_BIT(*pReg , Source); |
AnnaBridge | 171:3a7713b1edbc | 3473 | } |
AnnaBridge | 171:3a7713b1edbc | 3474 | |
AnnaBridge | 171:3a7713b1edbc | 3475 | /** |
AnnaBridge | 171:3a7713b1edbc | 3476 | * @brief Disable the signals connected to the designated timer break input. |
AnnaBridge | 171:3a7713b1edbc | 3477 | * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether |
AnnaBridge | 171:3a7713b1edbc | 3478 | * or not a timer instance allows for break input selection. |
AnnaBridge | 171:3a7713b1edbc | 3479 | * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n |
AnnaBridge | 171:3a7713b1edbc | 3480 | * AF1 BKDFBKE LL_TIM_DisableBreakInputSource\n |
AnnaBridge | 171:3a7713b1edbc | 3481 | * AF2 BK2INE LL_TIM_DisableBreakInputSource\n |
AnnaBridge | 171:3a7713b1edbc | 3482 | * AF2 BK2DFBKE LL_TIM_DisableBreakInputSource |
AnnaBridge | 171:3a7713b1edbc | 3483 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3484 | * @param BreakInput This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3485 | * @arg @ref LL_TIM_BREAK_INPUT_BKIN |
AnnaBridge | 171:3a7713b1edbc | 3486 | * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 |
AnnaBridge | 171:3a7713b1edbc | 3487 | * @param Source This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3488 | * @arg @ref LL_TIM_BKIN_SOURCE_BKIN |
AnnaBridge | 171:3a7713b1edbc | 3489 | * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK |
AnnaBridge | 171:3a7713b1edbc | 3490 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3491 | */ |
AnnaBridge | 171:3a7713b1edbc | 3492 | __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) |
AnnaBridge | 171:3a7713b1edbc | 3493 | { |
AnnaBridge | 171:3a7713b1edbc | 3494 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); |
AnnaBridge | 171:3a7713b1edbc | 3495 | CLEAR_BIT(*pReg, Source); |
AnnaBridge | 171:3a7713b1edbc | 3496 | } |
AnnaBridge | 171:3a7713b1edbc | 3497 | |
AnnaBridge | 171:3a7713b1edbc | 3498 | /** |
AnnaBridge | 171:3a7713b1edbc | 3499 | * @brief Set the polarity of the break signal for the timer break input. |
AnnaBridge | 171:3a7713b1edbc | 3500 | * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether |
AnnaBridge | 171:3a7713b1edbc | 3501 | * or not a timer instance allows for break input selection. |
AnnaBridge | 171:3a7713b1edbc | 3502 | * @rmtoll AF1 BKINE LL_TIM_SetBreakInputSourcePolarity\n |
AnnaBridge | 171:3a7713b1edbc | 3503 | * AF1 BKDFBKE LL_TIM_SetBreakInputSourcePolarity\n |
AnnaBridge | 171:3a7713b1edbc | 3504 | * AF2 BK2INE LL_TIM_SetBreakInputSourcePolarity\n |
AnnaBridge | 171:3a7713b1edbc | 3505 | * AF2 BK2DFBKE LL_TIM_SetBreakInputSourcePolarity |
AnnaBridge | 171:3a7713b1edbc | 3506 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3507 | * @param BreakInput This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3508 | * @arg @ref LL_TIM_BREAK_INPUT_BKIN |
AnnaBridge | 171:3a7713b1edbc | 3509 | * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 |
AnnaBridge | 171:3a7713b1edbc | 3510 | * @param Source This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3511 | * @arg @ref LL_TIM_BKIN_SOURCE_BKIN |
AnnaBridge | 171:3a7713b1edbc | 3512 | * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK |
AnnaBridge | 171:3a7713b1edbc | 3513 | * @param Polarity This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3514 | * @arg @ref LL_TIM_BKIN_POLARITY_LOW |
AnnaBridge | 171:3a7713b1edbc | 3515 | * @arg @ref LL_TIM_BKIN_POLARITY_HIGH |
AnnaBridge | 171:3a7713b1edbc | 3516 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3517 | */ |
AnnaBridge | 171:3a7713b1edbc | 3518 | __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, |
AnnaBridge | 171:3a7713b1edbc | 3519 | uint32_t Polarity) |
AnnaBridge | 171:3a7713b1edbc | 3520 | { |
AnnaBridge | 171:3a7713b1edbc | 3521 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); |
AnnaBridge | 171:3a7713b1edbc | 3522 | MODIFY_REG(*pReg, (TIMx_AF1_BKINP << (TIM_POSITION_BRK_SOURCE)) , (Polarity << (TIM_POSITION_BRK_SOURCE))); |
AnnaBridge | 171:3a7713b1edbc | 3523 | } |
AnnaBridge | 171:3a7713b1edbc | 3524 | #endif /* TIM_BREAK_INPUT_SUPPORT */ |
AnnaBridge | 171:3a7713b1edbc | 3525 | /** |
AnnaBridge | 171:3a7713b1edbc | 3526 | * @} |
AnnaBridge | 171:3a7713b1edbc | 3527 | */ |
AnnaBridge | 171:3a7713b1edbc | 3528 | |
AnnaBridge | 171:3a7713b1edbc | 3529 | /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration |
AnnaBridge | 171:3a7713b1edbc | 3530 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 3531 | */ |
AnnaBridge | 171:3a7713b1edbc | 3532 | /** |
AnnaBridge | 171:3a7713b1edbc | 3533 | * @brief Configures the timer DMA burst feature. |
AnnaBridge | 171:3a7713b1edbc | 3534 | * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or |
AnnaBridge | 171:3a7713b1edbc | 3535 | * not a timer instance supports the DMA burst mode. |
AnnaBridge | 171:3a7713b1edbc | 3536 | * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n |
AnnaBridge | 171:3a7713b1edbc | 3537 | * DCR DBA LL_TIM_ConfigDMABurst |
AnnaBridge | 171:3a7713b1edbc | 3538 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3539 | * @param DMABurstBaseAddress This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3540 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 |
AnnaBridge | 171:3a7713b1edbc | 3541 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 |
AnnaBridge | 171:3a7713b1edbc | 3542 | * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR |
AnnaBridge | 171:3a7713b1edbc | 3543 | * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER |
AnnaBridge | 171:3a7713b1edbc | 3544 | * @arg @ref LL_TIM_DMABURST_BASEADDR_SR |
AnnaBridge | 171:3a7713b1edbc | 3545 | * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR |
AnnaBridge | 171:3a7713b1edbc | 3546 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 |
AnnaBridge | 171:3a7713b1edbc | 3547 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 |
AnnaBridge | 171:3a7713b1edbc | 3548 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER |
AnnaBridge | 171:3a7713b1edbc | 3549 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT |
AnnaBridge | 171:3a7713b1edbc | 3550 | * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC |
AnnaBridge | 171:3a7713b1edbc | 3551 | * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR |
AnnaBridge | 171:3a7713b1edbc | 3552 | * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR |
AnnaBridge | 171:3a7713b1edbc | 3553 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 |
AnnaBridge | 171:3a7713b1edbc | 3554 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 |
AnnaBridge | 171:3a7713b1edbc | 3555 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 |
AnnaBridge | 171:3a7713b1edbc | 3556 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 |
AnnaBridge | 171:3a7713b1edbc | 3557 | * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR |
AnnaBridge | 171:3a7713b1edbc | 3558 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 |
AnnaBridge | 171:3a7713b1edbc | 3559 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 |
AnnaBridge | 171:3a7713b1edbc | 3560 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 |
AnnaBridge | 171:3a7713b1edbc | 3561 | * @arg @ref LL_TIM_DMABURST_BASEADDR_OR |
AnnaBridge | 171:3a7713b1edbc | 3562 | * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1 |
AnnaBridge | 171:3a7713b1edbc | 3563 | * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2 |
AnnaBridge | 171:3a7713b1edbc | 3564 | * @param DMABurstLength This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 3565 | * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER |
AnnaBridge | 171:3a7713b1edbc | 3566 | * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS |
AnnaBridge | 171:3a7713b1edbc | 3567 | * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS |
AnnaBridge | 171:3a7713b1edbc | 3568 | * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS |
AnnaBridge | 171:3a7713b1edbc | 3569 | * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS |
AnnaBridge | 171:3a7713b1edbc | 3570 | * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS |
AnnaBridge | 171:3a7713b1edbc | 3571 | * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS |
AnnaBridge | 171:3a7713b1edbc | 3572 | * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS |
AnnaBridge | 171:3a7713b1edbc | 3573 | * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS |
AnnaBridge | 171:3a7713b1edbc | 3574 | * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS |
AnnaBridge | 171:3a7713b1edbc | 3575 | * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS |
AnnaBridge | 171:3a7713b1edbc | 3576 | * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS |
AnnaBridge | 171:3a7713b1edbc | 3577 | * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS |
AnnaBridge | 171:3a7713b1edbc | 3578 | * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS |
AnnaBridge | 171:3a7713b1edbc | 3579 | * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS |
AnnaBridge | 171:3a7713b1edbc | 3580 | * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS |
AnnaBridge | 171:3a7713b1edbc | 3581 | * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS |
AnnaBridge | 171:3a7713b1edbc | 3582 | * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS |
AnnaBridge | 171:3a7713b1edbc | 3583 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3584 | */ |
AnnaBridge | 171:3a7713b1edbc | 3585 | __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength) |
AnnaBridge | 171:3a7713b1edbc | 3586 | { |
AnnaBridge | 171:3a7713b1edbc | 3587 | MODIFY_REG(TIMx->DCR, TIM_DCR_DBL | TIM_DCR_DBA, DMABurstBaseAddress | DMABurstLength); |
AnnaBridge | 171:3a7713b1edbc | 3588 | } |
AnnaBridge | 171:3a7713b1edbc | 3589 | |
AnnaBridge | 171:3a7713b1edbc | 3590 | /** |
AnnaBridge | 171:3a7713b1edbc | 3591 | * @} |
AnnaBridge | 171:3a7713b1edbc | 3592 | */ |
AnnaBridge | 171:3a7713b1edbc | 3593 | |
AnnaBridge | 171:3a7713b1edbc | 3594 | /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping |
AnnaBridge | 171:3a7713b1edbc | 3595 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 3596 | */ |
AnnaBridge | 171:3a7713b1edbc | 3597 | /** |
AnnaBridge | 171:3a7713b1edbc | 3598 | * @brief Remap TIM inputs (input channel, internal/external triggers). |
AnnaBridge | 171:3a7713b1edbc | 3599 | * @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not |
AnnaBridge | 171:3a7713b1edbc | 3600 | * a some timer inputs can be remapped. |
AnnaBridge | 171:3a7713b1edbc | 3601 | * @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n |
AnnaBridge | 171:3a7713b1edbc | 3602 | * TIM5_OR TI4_RMP LL_TIM_SetRemap\n |
AnnaBridge | 171:3a7713b1edbc | 3603 | * TIM11_OR TI1_RMP LL_TIM_SetRemap |
AnnaBridge | 171:3a7713b1edbc | 3604 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3605 | * @param Remap Remap param depends on the TIMx. Description available only |
AnnaBridge | 171:3a7713b1edbc | 3606 | * in CHM version of the User Manual (not in .pdf). |
AnnaBridge | 171:3a7713b1edbc | 3607 | * Otherwise see Reference Manual description of OR registers. |
AnnaBridge | 171:3a7713b1edbc | 3608 | * |
AnnaBridge | 171:3a7713b1edbc | 3609 | * Below description summarizes "Timer Instance" and "Remap" param combinations: |
AnnaBridge | 171:3a7713b1edbc | 3610 | * |
AnnaBridge | 171:3a7713b1edbc | 3611 | * TIM2: one of the following values |
AnnaBridge | 171:3a7713b1edbc | 3612 | * |
AnnaBridge | 171:3a7713b1edbc | 3613 | * ITR1_RMP can be one of the following values |
AnnaBridge | 171:3a7713b1edbc | 3614 | * @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO |
AnnaBridge | 171:3a7713b1edbc | 3615 | * @arg @ref LL_TIM_TIM2_ITR1_RMP_ETH_PTP |
AnnaBridge | 171:3a7713b1edbc | 3616 | * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF |
AnnaBridge | 171:3a7713b1edbc | 3617 | * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF |
AnnaBridge | 171:3a7713b1edbc | 3618 | * |
AnnaBridge | 171:3a7713b1edbc | 3619 | * TIM5: one of the following values |
AnnaBridge | 171:3a7713b1edbc | 3620 | * |
AnnaBridge | 171:3a7713b1edbc | 3621 | * @arg @ref LL_TIM_TIM5_TI4_RMP_GPIO |
AnnaBridge | 171:3a7713b1edbc | 3622 | * @arg @ref LL_TIM_TIM5_TI4_RMP_LSI |
AnnaBridge | 171:3a7713b1edbc | 3623 | * @arg @ref LL_TIM_TIM5_TI4_RMP_LSE |
AnnaBridge | 171:3a7713b1edbc | 3624 | * @arg @ref LL_TIM_TIM5_TI4_RMP_RTC |
AnnaBridge | 171:3a7713b1edbc | 3625 | * |
AnnaBridge | 171:3a7713b1edbc | 3626 | * TIM11: one of the following values |
AnnaBridge | 171:3a7713b1edbc | 3627 | * |
AnnaBridge | 171:3a7713b1edbc | 3628 | * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO |
AnnaBridge | 171:3a7713b1edbc | 3629 | * @arg @ref LL_TIM_TIM11_TI1_RMP_SPDIFRX |
AnnaBridge | 171:3a7713b1edbc | 3630 | * @arg @ref LL_TIM_TIM11_TI1_RMP_HSE |
AnnaBridge | 171:3a7713b1edbc | 3631 | * @arg @ref LL_TIM_TIM11_TI1_RMP_MCO1 |
AnnaBridge | 171:3a7713b1edbc | 3632 | * |
AnnaBridge | 171:3a7713b1edbc | 3633 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3634 | */ |
AnnaBridge | 171:3a7713b1edbc | 3635 | __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) |
AnnaBridge | 171:3a7713b1edbc | 3636 | { |
AnnaBridge | 171:3a7713b1edbc | 3637 | MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK)); |
AnnaBridge | 171:3a7713b1edbc | 3638 | } |
AnnaBridge | 171:3a7713b1edbc | 3639 | |
AnnaBridge | 171:3a7713b1edbc | 3640 | /** |
AnnaBridge | 171:3a7713b1edbc | 3641 | * @} |
AnnaBridge | 171:3a7713b1edbc | 3642 | */ |
AnnaBridge | 171:3a7713b1edbc | 3643 | |
AnnaBridge | 171:3a7713b1edbc | 3644 | |
AnnaBridge | 171:3a7713b1edbc | 3645 | /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management |
AnnaBridge | 171:3a7713b1edbc | 3646 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 3647 | */ |
AnnaBridge | 171:3a7713b1edbc | 3648 | /** |
AnnaBridge | 171:3a7713b1edbc | 3649 | * @brief Clear the update interrupt flag (UIF). |
AnnaBridge | 171:3a7713b1edbc | 3650 | * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE |
AnnaBridge | 171:3a7713b1edbc | 3651 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3652 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3653 | */ |
AnnaBridge | 171:3a7713b1edbc | 3654 | __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3655 | { |
AnnaBridge | 171:3a7713b1edbc | 3656 | WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); |
AnnaBridge | 171:3a7713b1edbc | 3657 | } |
AnnaBridge | 171:3a7713b1edbc | 3658 | |
AnnaBridge | 171:3a7713b1edbc | 3659 | /** |
AnnaBridge | 171:3a7713b1edbc | 3660 | * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). |
AnnaBridge | 171:3a7713b1edbc | 3661 | * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE |
AnnaBridge | 171:3a7713b1edbc | 3662 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3663 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 3664 | */ |
AnnaBridge | 171:3a7713b1edbc | 3665 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3666 | { |
AnnaBridge | 171:3a7713b1edbc | 3667 | return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)); |
AnnaBridge | 171:3a7713b1edbc | 3668 | } |
AnnaBridge | 171:3a7713b1edbc | 3669 | |
AnnaBridge | 171:3a7713b1edbc | 3670 | /** |
AnnaBridge | 171:3a7713b1edbc | 3671 | * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). |
AnnaBridge | 171:3a7713b1edbc | 3672 | * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 |
AnnaBridge | 171:3a7713b1edbc | 3673 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3674 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3675 | */ |
AnnaBridge | 171:3a7713b1edbc | 3676 | __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3677 | { |
AnnaBridge | 171:3a7713b1edbc | 3678 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); |
AnnaBridge | 171:3a7713b1edbc | 3679 | } |
AnnaBridge | 171:3a7713b1edbc | 3680 | |
AnnaBridge | 171:3a7713b1edbc | 3681 | /** |
AnnaBridge | 171:3a7713b1edbc | 3682 | * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending). |
AnnaBridge | 171:3a7713b1edbc | 3683 | * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 |
AnnaBridge | 171:3a7713b1edbc | 3684 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3685 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 3686 | */ |
AnnaBridge | 171:3a7713b1edbc | 3687 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3688 | { |
AnnaBridge | 171:3a7713b1edbc | 3689 | return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)); |
AnnaBridge | 171:3a7713b1edbc | 3690 | } |
AnnaBridge | 171:3a7713b1edbc | 3691 | |
AnnaBridge | 171:3a7713b1edbc | 3692 | /** |
AnnaBridge | 171:3a7713b1edbc | 3693 | * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). |
AnnaBridge | 171:3a7713b1edbc | 3694 | * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 |
AnnaBridge | 171:3a7713b1edbc | 3695 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3696 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3697 | */ |
AnnaBridge | 171:3a7713b1edbc | 3698 | __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3699 | { |
AnnaBridge | 171:3a7713b1edbc | 3700 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); |
AnnaBridge | 171:3a7713b1edbc | 3701 | } |
AnnaBridge | 171:3a7713b1edbc | 3702 | |
AnnaBridge | 171:3a7713b1edbc | 3703 | /** |
AnnaBridge | 171:3a7713b1edbc | 3704 | * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending). |
AnnaBridge | 171:3a7713b1edbc | 3705 | * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 |
AnnaBridge | 171:3a7713b1edbc | 3706 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3707 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 3708 | */ |
AnnaBridge | 171:3a7713b1edbc | 3709 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3710 | { |
AnnaBridge | 171:3a7713b1edbc | 3711 | return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)); |
AnnaBridge | 171:3a7713b1edbc | 3712 | } |
AnnaBridge | 171:3a7713b1edbc | 3713 | |
AnnaBridge | 171:3a7713b1edbc | 3714 | /** |
AnnaBridge | 171:3a7713b1edbc | 3715 | * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). |
AnnaBridge | 171:3a7713b1edbc | 3716 | * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 |
AnnaBridge | 171:3a7713b1edbc | 3717 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3718 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3719 | */ |
AnnaBridge | 171:3a7713b1edbc | 3720 | __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3721 | { |
AnnaBridge | 171:3a7713b1edbc | 3722 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); |
AnnaBridge | 171:3a7713b1edbc | 3723 | } |
AnnaBridge | 171:3a7713b1edbc | 3724 | |
AnnaBridge | 171:3a7713b1edbc | 3725 | /** |
AnnaBridge | 171:3a7713b1edbc | 3726 | * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending). |
AnnaBridge | 171:3a7713b1edbc | 3727 | * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 |
AnnaBridge | 171:3a7713b1edbc | 3728 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3729 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 3730 | */ |
AnnaBridge | 171:3a7713b1edbc | 3731 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3732 | { |
AnnaBridge | 171:3a7713b1edbc | 3733 | return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)); |
AnnaBridge | 171:3a7713b1edbc | 3734 | } |
AnnaBridge | 171:3a7713b1edbc | 3735 | |
AnnaBridge | 171:3a7713b1edbc | 3736 | /** |
AnnaBridge | 171:3a7713b1edbc | 3737 | * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). |
AnnaBridge | 171:3a7713b1edbc | 3738 | * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 |
AnnaBridge | 171:3a7713b1edbc | 3739 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3740 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3741 | */ |
AnnaBridge | 171:3a7713b1edbc | 3742 | __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3743 | { |
AnnaBridge | 171:3a7713b1edbc | 3744 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); |
AnnaBridge | 171:3a7713b1edbc | 3745 | } |
AnnaBridge | 171:3a7713b1edbc | 3746 | |
AnnaBridge | 171:3a7713b1edbc | 3747 | /** |
AnnaBridge | 171:3a7713b1edbc | 3748 | * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending). |
AnnaBridge | 171:3a7713b1edbc | 3749 | * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 |
AnnaBridge | 171:3a7713b1edbc | 3750 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3751 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 3752 | */ |
AnnaBridge | 171:3a7713b1edbc | 3753 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3754 | { |
AnnaBridge | 171:3a7713b1edbc | 3755 | return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)); |
AnnaBridge | 171:3a7713b1edbc | 3756 | } |
AnnaBridge | 171:3a7713b1edbc | 3757 | |
AnnaBridge | 171:3a7713b1edbc | 3758 | /** |
AnnaBridge | 171:3a7713b1edbc | 3759 | * @brief Clear the Capture/Compare 5 interrupt flag (CC5F). |
AnnaBridge | 171:3a7713b1edbc | 3760 | * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5 |
AnnaBridge | 171:3a7713b1edbc | 3761 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3762 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3763 | */ |
AnnaBridge | 171:3a7713b1edbc | 3764 | __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3765 | { |
AnnaBridge | 171:3a7713b1edbc | 3766 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF)); |
AnnaBridge | 171:3a7713b1edbc | 3767 | } |
AnnaBridge | 171:3a7713b1edbc | 3768 | |
AnnaBridge | 171:3a7713b1edbc | 3769 | /** |
AnnaBridge | 171:3a7713b1edbc | 3770 | * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending). |
AnnaBridge | 171:3a7713b1edbc | 3771 | * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5 |
AnnaBridge | 171:3a7713b1edbc | 3772 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3773 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 3774 | */ |
AnnaBridge | 171:3a7713b1edbc | 3775 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3776 | { |
AnnaBridge | 171:3a7713b1edbc | 3777 | return (READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)); |
AnnaBridge | 171:3a7713b1edbc | 3778 | } |
AnnaBridge | 171:3a7713b1edbc | 3779 | |
AnnaBridge | 171:3a7713b1edbc | 3780 | /** |
AnnaBridge | 171:3a7713b1edbc | 3781 | * @brief Clear the Capture/Compare 6 interrupt flag (CC6F). |
AnnaBridge | 171:3a7713b1edbc | 3782 | * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6 |
AnnaBridge | 171:3a7713b1edbc | 3783 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3784 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3785 | */ |
AnnaBridge | 171:3a7713b1edbc | 3786 | __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3787 | { |
AnnaBridge | 171:3a7713b1edbc | 3788 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF)); |
AnnaBridge | 171:3a7713b1edbc | 3789 | } |
AnnaBridge | 171:3a7713b1edbc | 3790 | |
AnnaBridge | 171:3a7713b1edbc | 3791 | /** |
AnnaBridge | 171:3a7713b1edbc | 3792 | * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending). |
AnnaBridge | 171:3a7713b1edbc | 3793 | * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6 |
AnnaBridge | 171:3a7713b1edbc | 3794 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3795 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 3796 | */ |
AnnaBridge | 171:3a7713b1edbc | 3797 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3798 | { |
AnnaBridge | 171:3a7713b1edbc | 3799 | return (READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)); |
AnnaBridge | 171:3a7713b1edbc | 3800 | } |
AnnaBridge | 171:3a7713b1edbc | 3801 | |
AnnaBridge | 171:3a7713b1edbc | 3802 | /** |
AnnaBridge | 171:3a7713b1edbc | 3803 | * @brief Clear the commutation interrupt flag (COMIF). |
AnnaBridge | 171:3a7713b1edbc | 3804 | * @rmtoll SR COMIF LL_TIM_ClearFlag_COM |
AnnaBridge | 171:3a7713b1edbc | 3805 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3806 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3807 | */ |
AnnaBridge | 171:3a7713b1edbc | 3808 | __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3809 | { |
AnnaBridge | 171:3a7713b1edbc | 3810 | WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); |
AnnaBridge | 171:3a7713b1edbc | 3811 | } |
AnnaBridge | 171:3a7713b1edbc | 3812 | |
AnnaBridge | 171:3a7713b1edbc | 3813 | /** |
AnnaBridge | 171:3a7713b1edbc | 3814 | * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending). |
AnnaBridge | 171:3a7713b1edbc | 3815 | * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM |
AnnaBridge | 171:3a7713b1edbc | 3816 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3817 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 3818 | */ |
AnnaBridge | 171:3a7713b1edbc | 3819 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3820 | { |
AnnaBridge | 171:3a7713b1edbc | 3821 | return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)); |
AnnaBridge | 171:3a7713b1edbc | 3822 | } |
AnnaBridge | 171:3a7713b1edbc | 3823 | |
AnnaBridge | 171:3a7713b1edbc | 3824 | /** |
AnnaBridge | 171:3a7713b1edbc | 3825 | * @brief Clear the trigger interrupt flag (TIF). |
AnnaBridge | 171:3a7713b1edbc | 3826 | * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG |
AnnaBridge | 171:3a7713b1edbc | 3827 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3828 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3829 | */ |
AnnaBridge | 171:3a7713b1edbc | 3830 | __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3831 | { |
AnnaBridge | 171:3a7713b1edbc | 3832 | WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); |
AnnaBridge | 171:3a7713b1edbc | 3833 | } |
AnnaBridge | 171:3a7713b1edbc | 3834 | |
AnnaBridge | 171:3a7713b1edbc | 3835 | /** |
AnnaBridge | 171:3a7713b1edbc | 3836 | * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). |
AnnaBridge | 171:3a7713b1edbc | 3837 | * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG |
AnnaBridge | 171:3a7713b1edbc | 3838 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3839 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 3840 | */ |
AnnaBridge | 171:3a7713b1edbc | 3841 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3842 | { |
AnnaBridge | 171:3a7713b1edbc | 3843 | return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)); |
AnnaBridge | 171:3a7713b1edbc | 3844 | } |
AnnaBridge | 171:3a7713b1edbc | 3845 | |
AnnaBridge | 171:3a7713b1edbc | 3846 | /** |
AnnaBridge | 171:3a7713b1edbc | 3847 | * @brief Clear the break interrupt flag (BIF). |
AnnaBridge | 171:3a7713b1edbc | 3848 | * @rmtoll SR BIF LL_TIM_ClearFlag_BRK |
AnnaBridge | 171:3a7713b1edbc | 3849 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3850 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3851 | */ |
AnnaBridge | 171:3a7713b1edbc | 3852 | __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3853 | { |
AnnaBridge | 171:3a7713b1edbc | 3854 | WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); |
AnnaBridge | 171:3a7713b1edbc | 3855 | } |
AnnaBridge | 171:3a7713b1edbc | 3856 | |
AnnaBridge | 171:3a7713b1edbc | 3857 | /** |
AnnaBridge | 171:3a7713b1edbc | 3858 | * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). |
AnnaBridge | 171:3a7713b1edbc | 3859 | * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK |
AnnaBridge | 171:3a7713b1edbc | 3860 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3861 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 3862 | */ |
AnnaBridge | 171:3a7713b1edbc | 3863 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3864 | { |
AnnaBridge | 171:3a7713b1edbc | 3865 | return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)); |
AnnaBridge | 171:3a7713b1edbc | 3866 | } |
AnnaBridge | 171:3a7713b1edbc | 3867 | |
AnnaBridge | 171:3a7713b1edbc | 3868 | /** |
AnnaBridge | 171:3a7713b1edbc | 3869 | * @brief Clear the break 2 interrupt flag (B2IF). |
AnnaBridge | 171:3a7713b1edbc | 3870 | * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2 |
AnnaBridge | 171:3a7713b1edbc | 3871 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3872 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3873 | */ |
AnnaBridge | 171:3a7713b1edbc | 3874 | __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3875 | { |
AnnaBridge | 171:3a7713b1edbc | 3876 | WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF)); |
AnnaBridge | 171:3a7713b1edbc | 3877 | } |
AnnaBridge | 171:3a7713b1edbc | 3878 | |
AnnaBridge | 171:3a7713b1edbc | 3879 | /** |
AnnaBridge | 171:3a7713b1edbc | 3880 | * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending). |
AnnaBridge | 171:3a7713b1edbc | 3881 | * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2 |
AnnaBridge | 171:3a7713b1edbc | 3882 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3883 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 3884 | */ |
AnnaBridge | 171:3a7713b1edbc | 3885 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3886 | { |
AnnaBridge | 171:3a7713b1edbc | 3887 | return (READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)); |
AnnaBridge | 171:3a7713b1edbc | 3888 | } |
AnnaBridge | 171:3a7713b1edbc | 3889 | |
AnnaBridge | 171:3a7713b1edbc | 3890 | /** |
AnnaBridge | 171:3a7713b1edbc | 3891 | * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). |
AnnaBridge | 171:3a7713b1edbc | 3892 | * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR |
AnnaBridge | 171:3a7713b1edbc | 3893 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3894 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3895 | */ |
AnnaBridge | 171:3a7713b1edbc | 3896 | __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3897 | { |
AnnaBridge | 171:3a7713b1edbc | 3898 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); |
AnnaBridge | 171:3a7713b1edbc | 3899 | } |
AnnaBridge | 171:3a7713b1edbc | 3900 | |
AnnaBridge | 171:3a7713b1edbc | 3901 | /** |
AnnaBridge | 171:3a7713b1edbc | 3902 | * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending). |
AnnaBridge | 171:3a7713b1edbc | 3903 | * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR |
AnnaBridge | 171:3a7713b1edbc | 3904 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3905 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 3906 | */ |
AnnaBridge | 171:3a7713b1edbc | 3907 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3908 | { |
AnnaBridge | 171:3a7713b1edbc | 3909 | return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)); |
AnnaBridge | 171:3a7713b1edbc | 3910 | } |
AnnaBridge | 171:3a7713b1edbc | 3911 | |
AnnaBridge | 171:3a7713b1edbc | 3912 | /** |
AnnaBridge | 171:3a7713b1edbc | 3913 | * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). |
AnnaBridge | 171:3a7713b1edbc | 3914 | * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR |
AnnaBridge | 171:3a7713b1edbc | 3915 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3916 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3917 | */ |
AnnaBridge | 171:3a7713b1edbc | 3918 | __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3919 | { |
AnnaBridge | 171:3a7713b1edbc | 3920 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); |
AnnaBridge | 171:3a7713b1edbc | 3921 | } |
AnnaBridge | 171:3a7713b1edbc | 3922 | |
AnnaBridge | 171:3a7713b1edbc | 3923 | /** |
AnnaBridge | 171:3a7713b1edbc | 3924 | * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending). |
AnnaBridge | 171:3a7713b1edbc | 3925 | * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR |
AnnaBridge | 171:3a7713b1edbc | 3926 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3927 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 3928 | */ |
AnnaBridge | 171:3a7713b1edbc | 3929 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3930 | { |
AnnaBridge | 171:3a7713b1edbc | 3931 | return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)); |
AnnaBridge | 171:3a7713b1edbc | 3932 | } |
AnnaBridge | 171:3a7713b1edbc | 3933 | |
AnnaBridge | 171:3a7713b1edbc | 3934 | /** |
AnnaBridge | 171:3a7713b1edbc | 3935 | * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). |
AnnaBridge | 171:3a7713b1edbc | 3936 | * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR |
AnnaBridge | 171:3a7713b1edbc | 3937 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3938 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3939 | */ |
AnnaBridge | 171:3a7713b1edbc | 3940 | __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3941 | { |
AnnaBridge | 171:3a7713b1edbc | 3942 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); |
AnnaBridge | 171:3a7713b1edbc | 3943 | } |
AnnaBridge | 171:3a7713b1edbc | 3944 | |
AnnaBridge | 171:3a7713b1edbc | 3945 | /** |
AnnaBridge | 171:3a7713b1edbc | 3946 | * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending). |
AnnaBridge | 171:3a7713b1edbc | 3947 | * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR |
AnnaBridge | 171:3a7713b1edbc | 3948 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3949 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 3950 | */ |
AnnaBridge | 171:3a7713b1edbc | 3951 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3952 | { |
AnnaBridge | 171:3a7713b1edbc | 3953 | return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)); |
AnnaBridge | 171:3a7713b1edbc | 3954 | } |
AnnaBridge | 171:3a7713b1edbc | 3955 | |
AnnaBridge | 171:3a7713b1edbc | 3956 | /** |
AnnaBridge | 171:3a7713b1edbc | 3957 | * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). |
AnnaBridge | 171:3a7713b1edbc | 3958 | * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR |
AnnaBridge | 171:3a7713b1edbc | 3959 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3960 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3961 | */ |
AnnaBridge | 171:3a7713b1edbc | 3962 | __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3963 | { |
AnnaBridge | 171:3a7713b1edbc | 3964 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); |
AnnaBridge | 171:3a7713b1edbc | 3965 | } |
AnnaBridge | 171:3a7713b1edbc | 3966 | |
AnnaBridge | 171:3a7713b1edbc | 3967 | /** |
AnnaBridge | 171:3a7713b1edbc | 3968 | * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending). |
AnnaBridge | 171:3a7713b1edbc | 3969 | * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR |
AnnaBridge | 171:3a7713b1edbc | 3970 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3971 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 3972 | */ |
AnnaBridge | 171:3a7713b1edbc | 3973 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3974 | { |
AnnaBridge | 171:3a7713b1edbc | 3975 | return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)); |
AnnaBridge | 171:3a7713b1edbc | 3976 | } |
AnnaBridge | 171:3a7713b1edbc | 3977 | |
AnnaBridge | 171:3a7713b1edbc | 3978 | /** |
AnnaBridge | 171:3a7713b1edbc | 3979 | * @brief Clear the system break interrupt flag (SBIF). |
AnnaBridge | 171:3a7713b1edbc | 3980 | * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK |
AnnaBridge | 171:3a7713b1edbc | 3981 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3982 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 3983 | */ |
AnnaBridge | 171:3a7713b1edbc | 3984 | __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3985 | { |
AnnaBridge | 171:3a7713b1edbc | 3986 | WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF)); |
AnnaBridge | 171:3a7713b1edbc | 3987 | } |
AnnaBridge | 171:3a7713b1edbc | 3988 | |
AnnaBridge | 171:3a7713b1edbc | 3989 | /** |
AnnaBridge | 171:3a7713b1edbc | 3990 | * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending). |
AnnaBridge | 171:3a7713b1edbc | 3991 | * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK |
AnnaBridge | 171:3a7713b1edbc | 3992 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 3993 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 3994 | */ |
AnnaBridge | 171:3a7713b1edbc | 3995 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 3996 | { |
AnnaBridge | 171:3a7713b1edbc | 3997 | return (READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)); |
AnnaBridge | 171:3a7713b1edbc | 3998 | } |
AnnaBridge | 171:3a7713b1edbc | 3999 | |
AnnaBridge | 171:3a7713b1edbc | 4000 | /** |
AnnaBridge | 171:3a7713b1edbc | 4001 | * @} |
AnnaBridge | 171:3a7713b1edbc | 4002 | */ |
AnnaBridge | 171:3a7713b1edbc | 4003 | |
AnnaBridge | 171:3a7713b1edbc | 4004 | /** @defgroup TIM_LL_EF_IT_Management IT-Management |
AnnaBridge | 171:3a7713b1edbc | 4005 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 4006 | */ |
AnnaBridge | 171:3a7713b1edbc | 4007 | /** |
AnnaBridge | 171:3a7713b1edbc | 4008 | * @brief Enable update interrupt (UIE). |
AnnaBridge | 171:3a7713b1edbc | 4009 | * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE |
AnnaBridge | 171:3a7713b1edbc | 4010 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4011 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4012 | */ |
AnnaBridge | 171:3a7713b1edbc | 4013 | __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4014 | { |
AnnaBridge | 171:3a7713b1edbc | 4015 | SET_BIT(TIMx->DIER, TIM_DIER_UIE); |
AnnaBridge | 171:3a7713b1edbc | 4016 | } |
AnnaBridge | 171:3a7713b1edbc | 4017 | |
AnnaBridge | 171:3a7713b1edbc | 4018 | /** |
AnnaBridge | 171:3a7713b1edbc | 4019 | * @brief Disable update interrupt (UIE). |
AnnaBridge | 171:3a7713b1edbc | 4020 | * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE |
AnnaBridge | 171:3a7713b1edbc | 4021 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4022 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4023 | */ |
AnnaBridge | 171:3a7713b1edbc | 4024 | __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4025 | { |
AnnaBridge | 171:3a7713b1edbc | 4026 | CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); |
AnnaBridge | 171:3a7713b1edbc | 4027 | } |
AnnaBridge | 171:3a7713b1edbc | 4028 | |
AnnaBridge | 171:3a7713b1edbc | 4029 | /** |
AnnaBridge | 171:3a7713b1edbc | 4030 | * @brief Indicates whether the update interrupt (UIE) is enabled. |
AnnaBridge | 171:3a7713b1edbc | 4031 | * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE |
AnnaBridge | 171:3a7713b1edbc | 4032 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4033 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 4034 | */ |
AnnaBridge | 171:3a7713b1edbc | 4035 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4036 | { |
AnnaBridge | 171:3a7713b1edbc | 4037 | return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)); |
AnnaBridge | 171:3a7713b1edbc | 4038 | } |
AnnaBridge | 171:3a7713b1edbc | 4039 | |
AnnaBridge | 171:3a7713b1edbc | 4040 | /** |
AnnaBridge | 171:3a7713b1edbc | 4041 | * @brief Enable capture/compare 1 interrupt (CC1IE). |
AnnaBridge | 171:3a7713b1edbc | 4042 | * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1 |
AnnaBridge | 171:3a7713b1edbc | 4043 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4044 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4045 | */ |
AnnaBridge | 171:3a7713b1edbc | 4046 | __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4047 | { |
AnnaBridge | 171:3a7713b1edbc | 4048 | SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); |
AnnaBridge | 171:3a7713b1edbc | 4049 | } |
AnnaBridge | 171:3a7713b1edbc | 4050 | |
AnnaBridge | 171:3a7713b1edbc | 4051 | /** |
AnnaBridge | 171:3a7713b1edbc | 4052 | * @brief Disable capture/compare 1 interrupt (CC1IE). |
AnnaBridge | 171:3a7713b1edbc | 4053 | * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1 |
AnnaBridge | 171:3a7713b1edbc | 4054 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4055 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4056 | */ |
AnnaBridge | 171:3a7713b1edbc | 4057 | __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4058 | { |
AnnaBridge | 171:3a7713b1edbc | 4059 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); |
AnnaBridge | 171:3a7713b1edbc | 4060 | } |
AnnaBridge | 171:3a7713b1edbc | 4061 | |
AnnaBridge | 171:3a7713b1edbc | 4062 | /** |
AnnaBridge | 171:3a7713b1edbc | 4063 | * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. |
AnnaBridge | 171:3a7713b1edbc | 4064 | * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1 |
AnnaBridge | 171:3a7713b1edbc | 4065 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4066 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 4067 | */ |
AnnaBridge | 171:3a7713b1edbc | 4068 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4069 | { |
AnnaBridge | 171:3a7713b1edbc | 4070 | return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)); |
AnnaBridge | 171:3a7713b1edbc | 4071 | } |
AnnaBridge | 171:3a7713b1edbc | 4072 | |
AnnaBridge | 171:3a7713b1edbc | 4073 | /** |
AnnaBridge | 171:3a7713b1edbc | 4074 | * @brief Enable capture/compare 2 interrupt (CC2IE). |
AnnaBridge | 171:3a7713b1edbc | 4075 | * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2 |
AnnaBridge | 171:3a7713b1edbc | 4076 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4077 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4078 | */ |
AnnaBridge | 171:3a7713b1edbc | 4079 | __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4080 | { |
AnnaBridge | 171:3a7713b1edbc | 4081 | SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); |
AnnaBridge | 171:3a7713b1edbc | 4082 | } |
AnnaBridge | 171:3a7713b1edbc | 4083 | |
AnnaBridge | 171:3a7713b1edbc | 4084 | /** |
AnnaBridge | 171:3a7713b1edbc | 4085 | * @brief Disable capture/compare 2 interrupt (CC2IE). |
AnnaBridge | 171:3a7713b1edbc | 4086 | * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2 |
AnnaBridge | 171:3a7713b1edbc | 4087 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4088 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4089 | */ |
AnnaBridge | 171:3a7713b1edbc | 4090 | __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4091 | { |
AnnaBridge | 171:3a7713b1edbc | 4092 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); |
AnnaBridge | 171:3a7713b1edbc | 4093 | } |
AnnaBridge | 171:3a7713b1edbc | 4094 | |
AnnaBridge | 171:3a7713b1edbc | 4095 | /** |
AnnaBridge | 171:3a7713b1edbc | 4096 | * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. |
AnnaBridge | 171:3a7713b1edbc | 4097 | * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2 |
AnnaBridge | 171:3a7713b1edbc | 4098 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4099 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 4100 | */ |
AnnaBridge | 171:3a7713b1edbc | 4101 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4102 | { |
AnnaBridge | 171:3a7713b1edbc | 4103 | return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)); |
AnnaBridge | 171:3a7713b1edbc | 4104 | } |
AnnaBridge | 171:3a7713b1edbc | 4105 | |
AnnaBridge | 171:3a7713b1edbc | 4106 | /** |
AnnaBridge | 171:3a7713b1edbc | 4107 | * @brief Enable capture/compare 3 interrupt (CC3IE). |
AnnaBridge | 171:3a7713b1edbc | 4108 | * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3 |
AnnaBridge | 171:3a7713b1edbc | 4109 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4110 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4111 | */ |
AnnaBridge | 171:3a7713b1edbc | 4112 | __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4113 | { |
AnnaBridge | 171:3a7713b1edbc | 4114 | SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); |
AnnaBridge | 171:3a7713b1edbc | 4115 | } |
AnnaBridge | 171:3a7713b1edbc | 4116 | |
AnnaBridge | 171:3a7713b1edbc | 4117 | /** |
AnnaBridge | 171:3a7713b1edbc | 4118 | * @brief Disable capture/compare 3 interrupt (CC3IE). |
AnnaBridge | 171:3a7713b1edbc | 4119 | * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3 |
AnnaBridge | 171:3a7713b1edbc | 4120 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4121 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4122 | */ |
AnnaBridge | 171:3a7713b1edbc | 4123 | __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4124 | { |
AnnaBridge | 171:3a7713b1edbc | 4125 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); |
AnnaBridge | 171:3a7713b1edbc | 4126 | } |
AnnaBridge | 171:3a7713b1edbc | 4127 | |
AnnaBridge | 171:3a7713b1edbc | 4128 | /** |
AnnaBridge | 171:3a7713b1edbc | 4129 | * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. |
AnnaBridge | 171:3a7713b1edbc | 4130 | * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3 |
AnnaBridge | 171:3a7713b1edbc | 4131 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4132 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 4133 | */ |
AnnaBridge | 171:3a7713b1edbc | 4134 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4135 | { |
AnnaBridge | 171:3a7713b1edbc | 4136 | return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)); |
AnnaBridge | 171:3a7713b1edbc | 4137 | } |
AnnaBridge | 171:3a7713b1edbc | 4138 | |
AnnaBridge | 171:3a7713b1edbc | 4139 | /** |
AnnaBridge | 171:3a7713b1edbc | 4140 | * @brief Enable capture/compare 4 interrupt (CC4IE). |
AnnaBridge | 171:3a7713b1edbc | 4141 | * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4 |
AnnaBridge | 171:3a7713b1edbc | 4142 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4143 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4144 | */ |
AnnaBridge | 171:3a7713b1edbc | 4145 | __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4146 | { |
AnnaBridge | 171:3a7713b1edbc | 4147 | SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); |
AnnaBridge | 171:3a7713b1edbc | 4148 | } |
AnnaBridge | 171:3a7713b1edbc | 4149 | |
AnnaBridge | 171:3a7713b1edbc | 4150 | /** |
AnnaBridge | 171:3a7713b1edbc | 4151 | * @brief Disable capture/compare 4 interrupt (CC4IE). |
AnnaBridge | 171:3a7713b1edbc | 4152 | * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4 |
AnnaBridge | 171:3a7713b1edbc | 4153 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4154 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4155 | */ |
AnnaBridge | 171:3a7713b1edbc | 4156 | __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4157 | { |
AnnaBridge | 171:3a7713b1edbc | 4158 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); |
AnnaBridge | 171:3a7713b1edbc | 4159 | } |
AnnaBridge | 171:3a7713b1edbc | 4160 | |
AnnaBridge | 171:3a7713b1edbc | 4161 | /** |
AnnaBridge | 171:3a7713b1edbc | 4162 | * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. |
AnnaBridge | 171:3a7713b1edbc | 4163 | * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4 |
AnnaBridge | 171:3a7713b1edbc | 4164 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4165 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 4166 | */ |
AnnaBridge | 171:3a7713b1edbc | 4167 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4168 | { |
AnnaBridge | 171:3a7713b1edbc | 4169 | return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)); |
AnnaBridge | 171:3a7713b1edbc | 4170 | } |
AnnaBridge | 171:3a7713b1edbc | 4171 | |
AnnaBridge | 171:3a7713b1edbc | 4172 | /** |
AnnaBridge | 171:3a7713b1edbc | 4173 | * @brief Enable commutation interrupt (COMIE). |
AnnaBridge | 171:3a7713b1edbc | 4174 | * @rmtoll DIER COMIE LL_TIM_EnableIT_COM |
AnnaBridge | 171:3a7713b1edbc | 4175 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4176 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4177 | */ |
AnnaBridge | 171:3a7713b1edbc | 4178 | __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4179 | { |
AnnaBridge | 171:3a7713b1edbc | 4180 | SET_BIT(TIMx->DIER, TIM_DIER_COMIE); |
AnnaBridge | 171:3a7713b1edbc | 4181 | } |
AnnaBridge | 171:3a7713b1edbc | 4182 | |
AnnaBridge | 171:3a7713b1edbc | 4183 | /** |
AnnaBridge | 171:3a7713b1edbc | 4184 | * @brief Disable commutation interrupt (COMIE). |
AnnaBridge | 171:3a7713b1edbc | 4185 | * @rmtoll DIER COMIE LL_TIM_DisableIT_COM |
AnnaBridge | 171:3a7713b1edbc | 4186 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4187 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4188 | */ |
AnnaBridge | 171:3a7713b1edbc | 4189 | __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4190 | { |
AnnaBridge | 171:3a7713b1edbc | 4191 | CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE); |
AnnaBridge | 171:3a7713b1edbc | 4192 | } |
AnnaBridge | 171:3a7713b1edbc | 4193 | |
AnnaBridge | 171:3a7713b1edbc | 4194 | /** |
AnnaBridge | 171:3a7713b1edbc | 4195 | * @brief Indicates whether the commutation interrupt (COMIE) is enabled. |
AnnaBridge | 171:3a7713b1edbc | 4196 | * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM |
AnnaBridge | 171:3a7713b1edbc | 4197 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4198 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 4199 | */ |
AnnaBridge | 171:3a7713b1edbc | 4200 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4201 | { |
AnnaBridge | 171:3a7713b1edbc | 4202 | return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)); |
AnnaBridge | 171:3a7713b1edbc | 4203 | } |
AnnaBridge | 171:3a7713b1edbc | 4204 | |
AnnaBridge | 171:3a7713b1edbc | 4205 | /** |
AnnaBridge | 171:3a7713b1edbc | 4206 | * @brief Enable trigger interrupt (TIE). |
AnnaBridge | 171:3a7713b1edbc | 4207 | * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG |
AnnaBridge | 171:3a7713b1edbc | 4208 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4209 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4210 | */ |
AnnaBridge | 171:3a7713b1edbc | 4211 | __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4212 | { |
AnnaBridge | 171:3a7713b1edbc | 4213 | SET_BIT(TIMx->DIER, TIM_DIER_TIE); |
AnnaBridge | 171:3a7713b1edbc | 4214 | } |
AnnaBridge | 171:3a7713b1edbc | 4215 | |
AnnaBridge | 171:3a7713b1edbc | 4216 | /** |
AnnaBridge | 171:3a7713b1edbc | 4217 | * @brief Disable trigger interrupt (TIE). |
AnnaBridge | 171:3a7713b1edbc | 4218 | * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG |
AnnaBridge | 171:3a7713b1edbc | 4219 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4220 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4221 | */ |
AnnaBridge | 171:3a7713b1edbc | 4222 | __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4223 | { |
AnnaBridge | 171:3a7713b1edbc | 4224 | CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); |
AnnaBridge | 171:3a7713b1edbc | 4225 | } |
AnnaBridge | 171:3a7713b1edbc | 4226 | |
AnnaBridge | 171:3a7713b1edbc | 4227 | /** |
AnnaBridge | 171:3a7713b1edbc | 4228 | * @brief Indicates whether the trigger interrupt (TIE) is enabled. |
AnnaBridge | 171:3a7713b1edbc | 4229 | * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG |
AnnaBridge | 171:3a7713b1edbc | 4230 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4231 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 4232 | */ |
AnnaBridge | 171:3a7713b1edbc | 4233 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4234 | { |
AnnaBridge | 171:3a7713b1edbc | 4235 | return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)); |
AnnaBridge | 171:3a7713b1edbc | 4236 | } |
AnnaBridge | 171:3a7713b1edbc | 4237 | |
AnnaBridge | 171:3a7713b1edbc | 4238 | /** |
AnnaBridge | 171:3a7713b1edbc | 4239 | * @brief Enable break interrupt (BIE). |
AnnaBridge | 171:3a7713b1edbc | 4240 | * @rmtoll DIER BIE LL_TIM_EnableIT_BRK |
AnnaBridge | 171:3a7713b1edbc | 4241 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4242 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4243 | */ |
AnnaBridge | 171:3a7713b1edbc | 4244 | __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4245 | { |
AnnaBridge | 171:3a7713b1edbc | 4246 | SET_BIT(TIMx->DIER, TIM_DIER_BIE); |
AnnaBridge | 171:3a7713b1edbc | 4247 | } |
AnnaBridge | 171:3a7713b1edbc | 4248 | |
AnnaBridge | 171:3a7713b1edbc | 4249 | /** |
AnnaBridge | 171:3a7713b1edbc | 4250 | * @brief Disable break interrupt (BIE). |
AnnaBridge | 171:3a7713b1edbc | 4251 | * @rmtoll DIER BIE LL_TIM_DisableIT_BRK |
AnnaBridge | 171:3a7713b1edbc | 4252 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4253 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4254 | */ |
AnnaBridge | 171:3a7713b1edbc | 4255 | __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4256 | { |
AnnaBridge | 171:3a7713b1edbc | 4257 | CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE); |
AnnaBridge | 171:3a7713b1edbc | 4258 | } |
AnnaBridge | 171:3a7713b1edbc | 4259 | |
AnnaBridge | 171:3a7713b1edbc | 4260 | /** |
AnnaBridge | 171:3a7713b1edbc | 4261 | * @brief Indicates whether the break interrupt (BIE) is enabled. |
AnnaBridge | 171:3a7713b1edbc | 4262 | * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK |
AnnaBridge | 171:3a7713b1edbc | 4263 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4264 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 4265 | */ |
AnnaBridge | 171:3a7713b1edbc | 4266 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4267 | { |
AnnaBridge | 171:3a7713b1edbc | 4268 | return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)); |
AnnaBridge | 171:3a7713b1edbc | 4269 | } |
AnnaBridge | 171:3a7713b1edbc | 4270 | |
AnnaBridge | 171:3a7713b1edbc | 4271 | /** |
AnnaBridge | 171:3a7713b1edbc | 4272 | * @} |
AnnaBridge | 171:3a7713b1edbc | 4273 | */ |
AnnaBridge | 171:3a7713b1edbc | 4274 | |
AnnaBridge | 171:3a7713b1edbc | 4275 | /** @defgroup TIM_LL_EF_DMA_Management DMA-Management |
AnnaBridge | 171:3a7713b1edbc | 4276 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 4277 | */ |
AnnaBridge | 171:3a7713b1edbc | 4278 | /** |
AnnaBridge | 171:3a7713b1edbc | 4279 | * @brief Enable update DMA request (UDE). |
AnnaBridge | 171:3a7713b1edbc | 4280 | * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE |
AnnaBridge | 171:3a7713b1edbc | 4281 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4282 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4283 | */ |
AnnaBridge | 171:3a7713b1edbc | 4284 | __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4285 | { |
AnnaBridge | 171:3a7713b1edbc | 4286 | SET_BIT(TIMx->DIER, TIM_DIER_UDE); |
AnnaBridge | 171:3a7713b1edbc | 4287 | } |
AnnaBridge | 171:3a7713b1edbc | 4288 | |
AnnaBridge | 171:3a7713b1edbc | 4289 | /** |
AnnaBridge | 171:3a7713b1edbc | 4290 | * @brief Disable update DMA request (UDE). |
AnnaBridge | 171:3a7713b1edbc | 4291 | * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE |
AnnaBridge | 171:3a7713b1edbc | 4292 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4293 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4294 | */ |
AnnaBridge | 171:3a7713b1edbc | 4295 | __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4296 | { |
AnnaBridge | 171:3a7713b1edbc | 4297 | CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); |
AnnaBridge | 171:3a7713b1edbc | 4298 | } |
AnnaBridge | 171:3a7713b1edbc | 4299 | |
AnnaBridge | 171:3a7713b1edbc | 4300 | /** |
AnnaBridge | 171:3a7713b1edbc | 4301 | * @brief Indicates whether the update DMA request (UDE) is enabled. |
AnnaBridge | 171:3a7713b1edbc | 4302 | * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE |
AnnaBridge | 171:3a7713b1edbc | 4303 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4304 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 4305 | */ |
AnnaBridge | 171:3a7713b1edbc | 4306 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4307 | { |
AnnaBridge | 171:3a7713b1edbc | 4308 | return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)); |
AnnaBridge | 171:3a7713b1edbc | 4309 | } |
AnnaBridge | 171:3a7713b1edbc | 4310 | |
AnnaBridge | 171:3a7713b1edbc | 4311 | /** |
AnnaBridge | 171:3a7713b1edbc | 4312 | * @brief Enable capture/compare 1 DMA request (CC1DE). |
AnnaBridge | 171:3a7713b1edbc | 4313 | * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1 |
AnnaBridge | 171:3a7713b1edbc | 4314 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4315 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4316 | */ |
AnnaBridge | 171:3a7713b1edbc | 4317 | __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4318 | { |
AnnaBridge | 171:3a7713b1edbc | 4319 | SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); |
AnnaBridge | 171:3a7713b1edbc | 4320 | } |
AnnaBridge | 171:3a7713b1edbc | 4321 | |
AnnaBridge | 171:3a7713b1edbc | 4322 | /** |
AnnaBridge | 171:3a7713b1edbc | 4323 | * @brief Disable capture/compare 1 DMA request (CC1DE). |
AnnaBridge | 171:3a7713b1edbc | 4324 | * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1 |
AnnaBridge | 171:3a7713b1edbc | 4325 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4326 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4327 | */ |
AnnaBridge | 171:3a7713b1edbc | 4328 | __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4329 | { |
AnnaBridge | 171:3a7713b1edbc | 4330 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); |
AnnaBridge | 171:3a7713b1edbc | 4331 | } |
AnnaBridge | 171:3a7713b1edbc | 4332 | |
AnnaBridge | 171:3a7713b1edbc | 4333 | /** |
AnnaBridge | 171:3a7713b1edbc | 4334 | * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. |
AnnaBridge | 171:3a7713b1edbc | 4335 | * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1 |
AnnaBridge | 171:3a7713b1edbc | 4336 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4337 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 4338 | */ |
AnnaBridge | 171:3a7713b1edbc | 4339 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4340 | { |
AnnaBridge | 171:3a7713b1edbc | 4341 | return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)); |
AnnaBridge | 171:3a7713b1edbc | 4342 | } |
AnnaBridge | 171:3a7713b1edbc | 4343 | |
AnnaBridge | 171:3a7713b1edbc | 4344 | /** |
AnnaBridge | 171:3a7713b1edbc | 4345 | * @brief Enable capture/compare 2 DMA request (CC2DE). |
AnnaBridge | 171:3a7713b1edbc | 4346 | * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2 |
AnnaBridge | 171:3a7713b1edbc | 4347 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4348 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4349 | */ |
AnnaBridge | 171:3a7713b1edbc | 4350 | __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4351 | { |
AnnaBridge | 171:3a7713b1edbc | 4352 | SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); |
AnnaBridge | 171:3a7713b1edbc | 4353 | } |
AnnaBridge | 171:3a7713b1edbc | 4354 | |
AnnaBridge | 171:3a7713b1edbc | 4355 | /** |
AnnaBridge | 171:3a7713b1edbc | 4356 | * @brief Disable capture/compare 2 DMA request (CC2DE). |
AnnaBridge | 171:3a7713b1edbc | 4357 | * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2 |
AnnaBridge | 171:3a7713b1edbc | 4358 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4359 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4360 | */ |
AnnaBridge | 171:3a7713b1edbc | 4361 | __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4362 | { |
AnnaBridge | 171:3a7713b1edbc | 4363 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); |
AnnaBridge | 171:3a7713b1edbc | 4364 | } |
AnnaBridge | 171:3a7713b1edbc | 4365 | |
AnnaBridge | 171:3a7713b1edbc | 4366 | /** |
AnnaBridge | 171:3a7713b1edbc | 4367 | * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. |
AnnaBridge | 171:3a7713b1edbc | 4368 | * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2 |
AnnaBridge | 171:3a7713b1edbc | 4369 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4370 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 4371 | */ |
AnnaBridge | 171:3a7713b1edbc | 4372 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4373 | { |
AnnaBridge | 171:3a7713b1edbc | 4374 | return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)); |
AnnaBridge | 171:3a7713b1edbc | 4375 | } |
AnnaBridge | 171:3a7713b1edbc | 4376 | |
AnnaBridge | 171:3a7713b1edbc | 4377 | /** |
AnnaBridge | 171:3a7713b1edbc | 4378 | * @brief Enable capture/compare 3 DMA request (CC3DE). |
AnnaBridge | 171:3a7713b1edbc | 4379 | * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3 |
AnnaBridge | 171:3a7713b1edbc | 4380 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4381 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4382 | */ |
AnnaBridge | 171:3a7713b1edbc | 4383 | __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4384 | { |
AnnaBridge | 171:3a7713b1edbc | 4385 | SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); |
AnnaBridge | 171:3a7713b1edbc | 4386 | } |
AnnaBridge | 171:3a7713b1edbc | 4387 | |
AnnaBridge | 171:3a7713b1edbc | 4388 | /** |
AnnaBridge | 171:3a7713b1edbc | 4389 | * @brief Disable capture/compare 3 DMA request (CC3DE). |
AnnaBridge | 171:3a7713b1edbc | 4390 | * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3 |
AnnaBridge | 171:3a7713b1edbc | 4391 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4392 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4393 | */ |
AnnaBridge | 171:3a7713b1edbc | 4394 | __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4395 | { |
AnnaBridge | 171:3a7713b1edbc | 4396 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); |
AnnaBridge | 171:3a7713b1edbc | 4397 | } |
AnnaBridge | 171:3a7713b1edbc | 4398 | |
AnnaBridge | 171:3a7713b1edbc | 4399 | /** |
AnnaBridge | 171:3a7713b1edbc | 4400 | * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. |
AnnaBridge | 171:3a7713b1edbc | 4401 | * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3 |
AnnaBridge | 171:3a7713b1edbc | 4402 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4403 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 4404 | */ |
AnnaBridge | 171:3a7713b1edbc | 4405 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4406 | { |
AnnaBridge | 171:3a7713b1edbc | 4407 | return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)); |
AnnaBridge | 171:3a7713b1edbc | 4408 | } |
AnnaBridge | 171:3a7713b1edbc | 4409 | |
AnnaBridge | 171:3a7713b1edbc | 4410 | /** |
AnnaBridge | 171:3a7713b1edbc | 4411 | * @brief Enable capture/compare 4 DMA request (CC4DE). |
AnnaBridge | 171:3a7713b1edbc | 4412 | * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4 |
AnnaBridge | 171:3a7713b1edbc | 4413 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4414 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4415 | */ |
AnnaBridge | 171:3a7713b1edbc | 4416 | __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4417 | { |
AnnaBridge | 171:3a7713b1edbc | 4418 | SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); |
AnnaBridge | 171:3a7713b1edbc | 4419 | } |
AnnaBridge | 171:3a7713b1edbc | 4420 | |
AnnaBridge | 171:3a7713b1edbc | 4421 | /** |
AnnaBridge | 171:3a7713b1edbc | 4422 | * @brief Disable capture/compare 4 DMA request (CC4DE). |
AnnaBridge | 171:3a7713b1edbc | 4423 | * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4 |
AnnaBridge | 171:3a7713b1edbc | 4424 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4425 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4426 | */ |
AnnaBridge | 171:3a7713b1edbc | 4427 | __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4428 | { |
AnnaBridge | 171:3a7713b1edbc | 4429 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); |
AnnaBridge | 171:3a7713b1edbc | 4430 | } |
AnnaBridge | 171:3a7713b1edbc | 4431 | |
AnnaBridge | 171:3a7713b1edbc | 4432 | /** |
AnnaBridge | 171:3a7713b1edbc | 4433 | * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. |
AnnaBridge | 171:3a7713b1edbc | 4434 | * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4 |
AnnaBridge | 171:3a7713b1edbc | 4435 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4436 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 4437 | */ |
AnnaBridge | 171:3a7713b1edbc | 4438 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4439 | { |
AnnaBridge | 171:3a7713b1edbc | 4440 | return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)); |
AnnaBridge | 171:3a7713b1edbc | 4441 | } |
AnnaBridge | 171:3a7713b1edbc | 4442 | |
AnnaBridge | 171:3a7713b1edbc | 4443 | /** |
AnnaBridge | 171:3a7713b1edbc | 4444 | * @brief Enable commutation DMA request (COMDE). |
AnnaBridge | 171:3a7713b1edbc | 4445 | * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM |
AnnaBridge | 171:3a7713b1edbc | 4446 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4447 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4448 | */ |
AnnaBridge | 171:3a7713b1edbc | 4449 | __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4450 | { |
AnnaBridge | 171:3a7713b1edbc | 4451 | SET_BIT(TIMx->DIER, TIM_DIER_COMDE); |
AnnaBridge | 171:3a7713b1edbc | 4452 | } |
AnnaBridge | 171:3a7713b1edbc | 4453 | |
AnnaBridge | 171:3a7713b1edbc | 4454 | /** |
AnnaBridge | 171:3a7713b1edbc | 4455 | * @brief Disable commutation DMA request (COMDE). |
AnnaBridge | 171:3a7713b1edbc | 4456 | * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM |
AnnaBridge | 171:3a7713b1edbc | 4457 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4458 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4459 | */ |
AnnaBridge | 171:3a7713b1edbc | 4460 | __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4461 | { |
AnnaBridge | 171:3a7713b1edbc | 4462 | CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE); |
AnnaBridge | 171:3a7713b1edbc | 4463 | } |
AnnaBridge | 171:3a7713b1edbc | 4464 | |
AnnaBridge | 171:3a7713b1edbc | 4465 | /** |
AnnaBridge | 171:3a7713b1edbc | 4466 | * @brief Indicates whether the commutation DMA request (COMDE) is enabled. |
AnnaBridge | 171:3a7713b1edbc | 4467 | * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM |
AnnaBridge | 171:3a7713b1edbc | 4468 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4469 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 4470 | */ |
AnnaBridge | 171:3a7713b1edbc | 4471 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4472 | { |
AnnaBridge | 171:3a7713b1edbc | 4473 | return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)); |
AnnaBridge | 171:3a7713b1edbc | 4474 | } |
AnnaBridge | 171:3a7713b1edbc | 4475 | |
AnnaBridge | 171:3a7713b1edbc | 4476 | /** |
AnnaBridge | 171:3a7713b1edbc | 4477 | * @brief Enable trigger interrupt (TDE). |
AnnaBridge | 171:3a7713b1edbc | 4478 | * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG |
AnnaBridge | 171:3a7713b1edbc | 4479 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4480 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4481 | */ |
AnnaBridge | 171:3a7713b1edbc | 4482 | __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4483 | { |
AnnaBridge | 171:3a7713b1edbc | 4484 | SET_BIT(TIMx->DIER, TIM_DIER_TDE); |
AnnaBridge | 171:3a7713b1edbc | 4485 | } |
AnnaBridge | 171:3a7713b1edbc | 4486 | |
AnnaBridge | 171:3a7713b1edbc | 4487 | /** |
AnnaBridge | 171:3a7713b1edbc | 4488 | * @brief Disable trigger interrupt (TDE). |
AnnaBridge | 171:3a7713b1edbc | 4489 | * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG |
AnnaBridge | 171:3a7713b1edbc | 4490 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4491 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4492 | */ |
AnnaBridge | 171:3a7713b1edbc | 4493 | __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4494 | { |
AnnaBridge | 171:3a7713b1edbc | 4495 | CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); |
AnnaBridge | 171:3a7713b1edbc | 4496 | } |
AnnaBridge | 171:3a7713b1edbc | 4497 | |
AnnaBridge | 171:3a7713b1edbc | 4498 | /** |
AnnaBridge | 171:3a7713b1edbc | 4499 | * @brief Indicates whether the trigger interrupt (TDE) is enabled. |
AnnaBridge | 171:3a7713b1edbc | 4500 | * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG |
AnnaBridge | 171:3a7713b1edbc | 4501 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4502 | * @retval State of bit (1 or 0). |
AnnaBridge | 171:3a7713b1edbc | 4503 | */ |
AnnaBridge | 171:3a7713b1edbc | 4504 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4505 | { |
AnnaBridge | 171:3a7713b1edbc | 4506 | return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)); |
AnnaBridge | 171:3a7713b1edbc | 4507 | } |
AnnaBridge | 171:3a7713b1edbc | 4508 | |
AnnaBridge | 171:3a7713b1edbc | 4509 | /** |
AnnaBridge | 171:3a7713b1edbc | 4510 | * @} |
AnnaBridge | 171:3a7713b1edbc | 4511 | */ |
AnnaBridge | 171:3a7713b1edbc | 4512 | |
AnnaBridge | 171:3a7713b1edbc | 4513 | /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management |
AnnaBridge | 171:3a7713b1edbc | 4514 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 4515 | */ |
AnnaBridge | 171:3a7713b1edbc | 4516 | /** |
AnnaBridge | 171:3a7713b1edbc | 4517 | * @brief Generate an update event. |
AnnaBridge | 171:3a7713b1edbc | 4518 | * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE |
AnnaBridge | 171:3a7713b1edbc | 4519 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4520 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4521 | */ |
AnnaBridge | 171:3a7713b1edbc | 4522 | __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4523 | { |
AnnaBridge | 171:3a7713b1edbc | 4524 | SET_BIT(TIMx->EGR, TIM_EGR_UG); |
AnnaBridge | 171:3a7713b1edbc | 4525 | } |
AnnaBridge | 171:3a7713b1edbc | 4526 | |
AnnaBridge | 171:3a7713b1edbc | 4527 | /** |
AnnaBridge | 171:3a7713b1edbc | 4528 | * @brief Generate Capture/Compare 1 event. |
AnnaBridge | 171:3a7713b1edbc | 4529 | * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1 |
AnnaBridge | 171:3a7713b1edbc | 4530 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4531 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4532 | */ |
AnnaBridge | 171:3a7713b1edbc | 4533 | __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4534 | { |
AnnaBridge | 171:3a7713b1edbc | 4535 | SET_BIT(TIMx->EGR, TIM_EGR_CC1G); |
AnnaBridge | 171:3a7713b1edbc | 4536 | } |
AnnaBridge | 171:3a7713b1edbc | 4537 | |
AnnaBridge | 171:3a7713b1edbc | 4538 | /** |
AnnaBridge | 171:3a7713b1edbc | 4539 | * @brief Generate Capture/Compare 2 event. |
AnnaBridge | 171:3a7713b1edbc | 4540 | * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2 |
AnnaBridge | 171:3a7713b1edbc | 4541 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4542 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4543 | */ |
AnnaBridge | 171:3a7713b1edbc | 4544 | __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4545 | { |
AnnaBridge | 171:3a7713b1edbc | 4546 | SET_BIT(TIMx->EGR, TIM_EGR_CC2G); |
AnnaBridge | 171:3a7713b1edbc | 4547 | } |
AnnaBridge | 171:3a7713b1edbc | 4548 | |
AnnaBridge | 171:3a7713b1edbc | 4549 | /** |
AnnaBridge | 171:3a7713b1edbc | 4550 | * @brief Generate Capture/Compare 3 event. |
AnnaBridge | 171:3a7713b1edbc | 4551 | * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3 |
AnnaBridge | 171:3a7713b1edbc | 4552 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4553 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4554 | */ |
AnnaBridge | 171:3a7713b1edbc | 4555 | __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4556 | { |
AnnaBridge | 171:3a7713b1edbc | 4557 | SET_BIT(TIMx->EGR, TIM_EGR_CC3G); |
AnnaBridge | 171:3a7713b1edbc | 4558 | } |
AnnaBridge | 171:3a7713b1edbc | 4559 | |
AnnaBridge | 171:3a7713b1edbc | 4560 | /** |
AnnaBridge | 171:3a7713b1edbc | 4561 | * @brief Generate Capture/Compare 4 event. |
AnnaBridge | 171:3a7713b1edbc | 4562 | * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4 |
AnnaBridge | 171:3a7713b1edbc | 4563 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4564 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4565 | */ |
AnnaBridge | 171:3a7713b1edbc | 4566 | __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4567 | { |
AnnaBridge | 171:3a7713b1edbc | 4568 | SET_BIT(TIMx->EGR, TIM_EGR_CC4G); |
AnnaBridge | 171:3a7713b1edbc | 4569 | } |
AnnaBridge | 171:3a7713b1edbc | 4570 | |
AnnaBridge | 171:3a7713b1edbc | 4571 | /** |
AnnaBridge | 171:3a7713b1edbc | 4572 | * @brief Generate commutation event. |
AnnaBridge | 171:3a7713b1edbc | 4573 | * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM |
AnnaBridge | 171:3a7713b1edbc | 4574 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4575 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4576 | */ |
AnnaBridge | 171:3a7713b1edbc | 4577 | __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4578 | { |
AnnaBridge | 171:3a7713b1edbc | 4579 | SET_BIT(TIMx->EGR, TIM_EGR_COMG); |
AnnaBridge | 171:3a7713b1edbc | 4580 | } |
AnnaBridge | 171:3a7713b1edbc | 4581 | |
AnnaBridge | 171:3a7713b1edbc | 4582 | /** |
AnnaBridge | 171:3a7713b1edbc | 4583 | * @brief Generate trigger event. |
AnnaBridge | 171:3a7713b1edbc | 4584 | * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG |
AnnaBridge | 171:3a7713b1edbc | 4585 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4586 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4587 | */ |
AnnaBridge | 171:3a7713b1edbc | 4588 | __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4589 | { |
AnnaBridge | 171:3a7713b1edbc | 4590 | SET_BIT(TIMx->EGR, TIM_EGR_TG); |
AnnaBridge | 171:3a7713b1edbc | 4591 | } |
AnnaBridge | 171:3a7713b1edbc | 4592 | |
AnnaBridge | 171:3a7713b1edbc | 4593 | /** |
AnnaBridge | 171:3a7713b1edbc | 4594 | * @brief Generate break event. |
AnnaBridge | 171:3a7713b1edbc | 4595 | * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK |
AnnaBridge | 171:3a7713b1edbc | 4596 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4597 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4598 | */ |
AnnaBridge | 171:3a7713b1edbc | 4599 | __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4600 | { |
AnnaBridge | 171:3a7713b1edbc | 4601 | SET_BIT(TIMx->EGR, TIM_EGR_BG); |
AnnaBridge | 171:3a7713b1edbc | 4602 | } |
AnnaBridge | 171:3a7713b1edbc | 4603 | |
AnnaBridge | 171:3a7713b1edbc | 4604 | /** |
AnnaBridge | 171:3a7713b1edbc | 4605 | * @brief Generate break 2 event. |
AnnaBridge | 171:3a7713b1edbc | 4606 | * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2 |
AnnaBridge | 171:3a7713b1edbc | 4607 | * @param TIMx Timer instance |
AnnaBridge | 171:3a7713b1edbc | 4608 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 4609 | */ |
AnnaBridge | 171:3a7713b1edbc | 4610 | __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx) |
AnnaBridge | 171:3a7713b1edbc | 4611 | { |
AnnaBridge | 171:3a7713b1edbc | 4612 | SET_BIT(TIMx->EGR, TIM_EGR_B2G); |
AnnaBridge | 171:3a7713b1edbc | 4613 | } |
AnnaBridge | 171:3a7713b1edbc | 4614 | |
AnnaBridge | 171:3a7713b1edbc | 4615 | /** |
AnnaBridge | 171:3a7713b1edbc | 4616 | * @} |
AnnaBridge | 171:3a7713b1edbc | 4617 | */ |
AnnaBridge | 171:3a7713b1edbc | 4618 | |
AnnaBridge | 171:3a7713b1edbc | 4619 | #if defined(USE_FULL_LL_DRIVER) |
AnnaBridge | 171:3a7713b1edbc | 4620 | /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions |
AnnaBridge | 171:3a7713b1edbc | 4621 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 4622 | */ |
AnnaBridge | 171:3a7713b1edbc | 4623 | |
AnnaBridge | 171:3a7713b1edbc | 4624 | ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx); |
AnnaBridge | 171:3a7713b1edbc | 4625 | void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); |
AnnaBridge | 171:3a7713b1edbc | 4626 | ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct); |
AnnaBridge | 171:3a7713b1edbc | 4627 | void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); |
AnnaBridge | 171:3a7713b1edbc | 4628 | ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); |
AnnaBridge | 171:3a7713b1edbc | 4629 | void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); |
AnnaBridge | 171:3a7713b1edbc | 4630 | ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); |
AnnaBridge | 171:3a7713b1edbc | 4631 | void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); |
AnnaBridge | 171:3a7713b1edbc | 4632 | ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); |
AnnaBridge | 171:3a7713b1edbc | 4633 | void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); |
AnnaBridge | 171:3a7713b1edbc | 4634 | ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); |
AnnaBridge | 171:3a7713b1edbc | 4635 | void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); |
AnnaBridge | 171:3a7713b1edbc | 4636 | ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); |
AnnaBridge | 171:3a7713b1edbc | 4637 | /** |
AnnaBridge | 171:3a7713b1edbc | 4638 | * @} |
AnnaBridge | 171:3a7713b1edbc | 4639 | */ |
AnnaBridge | 171:3a7713b1edbc | 4640 | #endif /* USE_FULL_LL_DRIVER */ |
AnnaBridge | 171:3a7713b1edbc | 4641 | |
AnnaBridge | 171:3a7713b1edbc | 4642 | /** |
AnnaBridge | 171:3a7713b1edbc | 4643 | * @} |
AnnaBridge | 171:3a7713b1edbc | 4644 | */ |
AnnaBridge | 171:3a7713b1edbc | 4645 | |
AnnaBridge | 171:3a7713b1edbc | 4646 | /** |
AnnaBridge | 171:3a7713b1edbc | 4647 | * @} |
AnnaBridge | 171:3a7713b1edbc | 4648 | */ |
AnnaBridge | 171:3a7713b1edbc | 4649 | |
AnnaBridge | 171:3a7713b1edbc | 4650 | #endif /* TIM1 || TIM8 || TIM2 || TIM3 || TIM4 || TIM5 ||TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM6 || TIM7 */ |
AnnaBridge | 171:3a7713b1edbc | 4651 | |
AnnaBridge | 171:3a7713b1edbc | 4652 | /** |
AnnaBridge | 171:3a7713b1edbc | 4653 | * @} |
AnnaBridge | 171:3a7713b1edbc | 4654 | */ |
AnnaBridge | 171:3a7713b1edbc | 4655 | |
AnnaBridge | 171:3a7713b1edbc | 4656 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 4657 | } |
AnnaBridge | 171:3a7713b1edbc | 4658 | #endif |
AnnaBridge | 171:3a7713b1edbc | 4659 | |
AnnaBridge | 171:3a7713b1edbc | 4660 | #endif /* __STM32F7xx_LL_TIM_H */ |
AnnaBridge | 171:3a7713b1edbc | 4661 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |