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TARGET_NUCLEO_F746ZG/TOOLCHAIN_ARM_STD/stm32f7xx_ll_lptim.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file stm32f7xx_ll_lptim.h
AnnaBridge 171:3a7713b1edbc 4 * @author MCD Application Team
AnnaBridge 171:3a7713b1edbc 5 * @brief Header file of LPTIM LL module.
AnnaBridge 171:3a7713b1edbc 6 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 7 * @attention
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 12 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 14 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 17 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 171:3a7713b1edbc 19 * may be used to endorse or promote products derived from this software
AnnaBridge 171:3a7713b1edbc 20 * without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 171:3a7713b1edbc 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 171:3a7713b1edbc 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 171:3a7713b1edbc 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 171:3a7713b1edbc 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 171:3a7713b1edbc 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 171:3a7713b1edbc 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 171:3a7713b1edbc 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 32 *
AnnaBridge 171:3a7713b1edbc 33 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 34 */
AnnaBridge 171:3a7713b1edbc 35
AnnaBridge 171:3a7713b1edbc 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 171:3a7713b1edbc 37 #ifndef __STM32F7xx_LL_LPTIM_H
AnnaBridge 171:3a7713b1edbc 38 #define __STM32F7xx_LL_LPTIM_H
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 41 extern "C" {
AnnaBridge 171:3a7713b1edbc 42 #endif
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 /* Includes ------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 45 #include "stm32f7xx.h"
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /** @addtogroup STM32F7xx_LL_Driver
AnnaBridge 171:3a7713b1edbc 48 * @{
AnnaBridge 171:3a7713b1edbc 49 */
AnnaBridge 171:3a7713b1edbc 50 #if defined (LPTIM1)
AnnaBridge 171:3a7713b1edbc 51
AnnaBridge 171:3a7713b1edbc 52 /** @defgroup LPTIM_LL LPTIM
AnnaBridge 171:3a7713b1edbc 53 * @{
AnnaBridge 171:3a7713b1edbc 54 */
AnnaBridge 171:3a7713b1edbc 55
AnnaBridge 171:3a7713b1edbc 56 /* Private types -------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 57 /* Private variables ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 58
AnnaBridge 171:3a7713b1edbc 59 /* Private constants ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 60
AnnaBridge 171:3a7713b1edbc 61 /* Private macros ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 62 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 171:3a7713b1edbc 63 /** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
AnnaBridge 171:3a7713b1edbc 64 * @{
AnnaBridge 171:3a7713b1edbc 65 */
AnnaBridge 171:3a7713b1edbc 66 /**
AnnaBridge 171:3a7713b1edbc 67 * @}
AnnaBridge 171:3a7713b1edbc 68 */
AnnaBridge 171:3a7713b1edbc 69 #endif /*USE_FULL_LL_DRIVER*/
AnnaBridge 171:3a7713b1edbc 70
AnnaBridge 171:3a7713b1edbc 71 /* Exported types ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 72 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 171:3a7713b1edbc 73 /** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
AnnaBridge 171:3a7713b1edbc 74 * @{
AnnaBridge 171:3a7713b1edbc 75 */
AnnaBridge 171:3a7713b1edbc 76
AnnaBridge 171:3a7713b1edbc 77 /**
AnnaBridge 171:3a7713b1edbc 78 * @brief LPTIM Init structure definition
AnnaBridge 171:3a7713b1edbc 79 */
AnnaBridge 171:3a7713b1edbc 80 typedef struct
AnnaBridge 171:3a7713b1edbc 81 {
AnnaBridge 171:3a7713b1edbc 82 uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance.
AnnaBridge 171:3a7713b1edbc 83 This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
AnnaBridge 171:3a7713b1edbc 84
AnnaBridge 171:3a7713b1edbc 85 This feature can be modified afterwards using unitary function @ref LL_LPTIM_SetClockSource().*/
AnnaBridge 171:3a7713b1edbc 86
AnnaBridge 171:3a7713b1edbc 87 uint32_t Prescaler; /*!< Specifies the prescaler division ratio.
AnnaBridge 171:3a7713b1edbc 88 This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
AnnaBridge 171:3a7713b1edbc 89
AnnaBridge 171:3a7713b1edbc 90 This feature can be modified afterwards using using unitary function @ref LL_LPTIM_SetPrescaler().*/
AnnaBridge 171:3a7713b1edbc 91
AnnaBridge 171:3a7713b1edbc 92 uint32_t Waveform; /*!< Specifies the waveform shape.
AnnaBridge 171:3a7713b1edbc 93 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
AnnaBridge 171:3a7713b1edbc 94
AnnaBridge 171:3a7713b1edbc 95 This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/
AnnaBridge 171:3a7713b1edbc 96
AnnaBridge 171:3a7713b1edbc 97 uint32_t Polarity; /*!< Specifies waveform polarity.
AnnaBridge 171:3a7713b1edbc 98 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY.
AnnaBridge 171:3a7713b1edbc 99
AnnaBridge 171:3a7713b1edbc 100 This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/
AnnaBridge 171:3a7713b1edbc 101 } LL_LPTIM_InitTypeDef;
AnnaBridge 171:3a7713b1edbc 102
AnnaBridge 171:3a7713b1edbc 103 /**
AnnaBridge 171:3a7713b1edbc 104 * @}
AnnaBridge 171:3a7713b1edbc 105 */
AnnaBridge 171:3a7713b1edbc 106 #endif /* USE_FULL_LL_DRIVER */
AnnaBridge 171:3a7713b1edbc 107
AnnaBridge 171:3a7713b1edbc 108 /* Exported constants --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 109 /** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
AnnaBridge 171:3a7713b1edbc 110 * @{
AnnaBridge 171:3a7713b1edbc 111 */
AnnaBridge 171:3a7713b1edbc 112
AnnaBridge 171:3a7713b1edbc 113 /** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge 171:3a7713b1edbc 114 * @brief Flags defines which can be used with LL_LPTIM_ReadReg function
AnnaBridge 171:3a7713b1edbc 115 * @{
AnnaBridge 171:3a7713b1edbc 116 */
AnnaBridge 171:3a7713b1edbc 117 #define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM /*!< Compare match */
AnnaBridge 171:3a7713b1edbc 118 #define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */
AnnaBridge 171:3a7713b1edbc 119 #define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */
AnnaBridge 171:3a7713b1edbc 120 #define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */
AnnaBridge 171:3a7713b1edbc 121 #define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */
AnnaBridge 171:3a7713b1edbc 122 #define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */
AnnaBridge 171:3a7713b1edbc 123 #define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */
AnnaBridge 171:3a7713b1edbc 124 /**
AnnaBridge 171:3a7713b1edbc 125 * @}
AnnaBridge 171:3a7713b1edbc 126 */
AnnaBridge 171:3a7713b1edbc 127
AnnaBridge 171:3a7713b1edbc 128 /** @defgroup LPTIM_LL_EC_IT IT Defines
AnnaBridge 171:3a7713b1edbc 129 * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions
AnnaBridge 171:3a7713b1edbc 130 * @{
AnnaBridge 171:3a7713b1edbc 131 */
AnnaBridge 171:3a7713b1edbc 132 #define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 133 #define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 134 #define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger valid edge Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 135 #define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 136 #define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 137 #define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Direction change to UP Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 138 #define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Direction change to down Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 139 /**
AnnaBridge 171:3a7713b1edbc 140 * @}
AnnaBridge 171:3a7713b1edbc 141 */
AnnaBridge 171:3a7713b1edbc 142
AnnaBridge 171:3a7713b1edbc 143 /** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
AnnaBridge 171:3a7713b1edbc 144 * @{
AnnaBridge 171:3a7713b1edbc 145 */
AnnaBridge 171:3a7713b1edbc 146 #define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
AnnaBridge 171:3a7713b1edbc 147 #define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
AnnaBridge 171:3a7713b1edbc 148 /**
AnnaBridge 171:3a7713b1edbc 149 * @}
AnnaBridge 171:3a7713b1edbc 150 */
AnnaBridge 171:3a7713b1edbc 151
AnnaBridge 171:3a7713b1edbc 152 /** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
AnnaBridge 171:3a7713b1edbc 153 * @{
AnnaBridge 171:3a7713b1edbc 154 */
AnnaBridge 171:3a7713b1edbc 155 #define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U /*!<Preload is disabled: registers are updated after each APB bus write access*/
AnnaBridge 171:3a7713b1edbc 156 #define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
AnnaBridge 171:3a7713b1edbc 157 /**
AnnaBridge 171:3a7713b1edbc 158 * @}
AnnaBridge 171:3a7713b1edbc 159 */
AnnaBridge 171:3a7713b1edbc 160
AnnaBridge 171:3a7713b1edbc 161 /** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
AnnaBridge 171:3a7713b1edbc 162 * @{
AnnaBridge 171:3a7713b1edbc 163 */
AnnaBridge 171:3a7713b1edbc 164 #define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U /*!<The counter is incremented following each internal clock pulse*/
AnnaBridge 171:3a7713b1edbc 165 #define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
AnnaBridge 171:3a7713b1edbc 166 /**
AnnaBridge 171:3a7713b1edbc 167 * @}
AnnaBridge 171:3a7713b1edbc 168 */
AnnaBridge 171:3a7713b1edbc 169
AnnaBridge 171:3a7713b1edbc 170 /** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
AnnaBridge 171:3a7713b1edbc 171 * @{
AnnaBridge 171:3a7713b1edbc 172 */
AnnaBridge 171:3a7713b1edbc 173 #define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINOUS or SINGLE*/
AnnaBridge 171:3a7713b1edbc 174 #define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/
AnnaBridge 171:3a7713b1edbc 175 /**
AnnaBridge 171:3a7713b1edbc 176 * @}
AnnaBridge 171:3a7713b1edbc 177 */
AnnaBridge 171:3a7713b1edbc 178
AnnaBridge 171:3a7713b1edbc 179 /** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
AnnaBridge 171:3a7713b1edbc 180 * @{
AnnaBridge 171:3a7713b1edbc 181 */
AnnaBridge 171:3a7713b1edbc 182 #define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
AnnaBridge 171:3a7713b1edbc 183 #define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
AnnaBridge 171:3a7713b1edbc 184 /**
AnnaBridge 171:3a7713b1edbc 185 * @}
AnnaBridge 171:3a7713b1edbc 186 */
AnnaBridge 171:3a7713b1edbc 187
AnnaBridge 171:3a7713b1edbc 188 /** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
AnnaBridge 171:3a7713b1edbc 189 * @{
AnnaBridge 171:3a7713b1edbc 190 */
AnnaBridge 171:3a7713b1edbc 191 #define LL_LPTIM_PRESCALER_DIV1 0x00000000U /*!<Prescaler division factor is set to 1*/
AnnaBridge 171:3a7713b1edbc 192 #define LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 /*!<Prescaler division factor is set to 2*/
AnnaBridge 171:3a7713b1edbc 193 #define LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 /*!<Prescaler division factor is set to 4*/
AnnaBridge 171:3a7713b1edbc 194 #define LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/
AnnaBridge 171:3a7713b1edbc 195 #define LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 /*!<Prescaler division factor is set to 16*/
AnnaBridge 171:3a7713b1edbc 196 #define LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/
AnnaBridge 171:3a7713b1edbc 197 #define LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/
AnnaBridge 171:3a7713b1edbc 198 #define LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC /*!<Prescaler division factor is set to 128*/
AnnaBridge 171:3a7713b1edbc 199 /**
AnnaBridge 171:3a7713b1edbc 200 * @}
AnnaBridge 171:3a7713b1edbc 201 */
AnnaBridge 171:3a7713b1edbc 202
AnnaBridge 171:3a7713b1edbc 203 /** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
AnnaBridge 171:3a7713b1edbc 204 * @{
AnnaBridge 171:3a7713b1edbc 205 */
AnnaBridge 171:3a7713b1edbc 206 #define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U /*!<External input trigger is connected to TIMx_ETR input*/
AnnaBridge 171:3a7713b1edbc 207 #define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to RTC Alarm A*/
AnnaBridge 171:3a7713b1edbc 208 #define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to RTC Alarm B*/
AnnaBridge 171:3a7713b1edbc 209 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/
AnnaBridge 171:3a7713b1edbc 210 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to RTC Tamper 2*/
AnnaBridge 171:3a7713b1edbc 211 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 3*/
AnnaBridge 171:3a7713b1edbc 212 #define LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to COMP1 output*/
AnnaBridge 171:3a7713b1edbc 213 #define LL_LPTIM_TRIG_SOURCE_COMP2 LPTIM_CFGR_TRIGSEL /*!<External input trigger is connected to COMP2 output*/
AnnaBridge 171:3a7713b1edbc 214 /**
AnnaBridge 171:3a7713b1edbc 215 * @}
AnnaBridge 171:3a7713b1edbc 216 */
AnnaBridge 171:3a7713b1edbc 217
AnnaBridge 171:3a7713b1edbc 218 /** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
AnnaBridge 171:3a7713b1edbc 219 * @{
AnnaBridge 171:3a7713b1edbc 220 */
AnnaBridge 171:3a7713b1edbc 221 #define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U /*!<Any trigger active level change is considered as a valid trigger*/
AnnaBridge 171:3a7713b1edbc 222 #define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
AnnaBridge 171:3a7713b1edbc 223 #define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
AnnaBridge 171:3a7713b1edbc 224 #define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
AnnaBridge 171:3a7713b1edbc 225 /**
AnnaBridge 171:3a7713b1edbc 226 * @}
AnnaBridge 171:3a7713b1edbc 227 */
AnnaBridge 171:3a7713b1edbc 228
AnnaBridge 171:3a7713b1edbc 229 /** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
AnnaBridge 171:3a7713b1edbc 230 * @{
AnnaBridge 171:3a7713b1edbc 231 */
AnnaBridge 171:3a7713b1edbc 232 #define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
AnnaBridge 171:3a7713b1edbc 233 #define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
AnnaBridge 171:3a7713b1edbc 234 #define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN /*!<LPTIM counter starts when a rising or a falling edge is detected*/
AnnaBridge 171:3a7713b1edbc 235 /**
AnnaBridge 171:3a7713b1edbc 236 * @}
AnnaBridge 171:3a7713b1edbc 237 */
AnnaBridge 171:3a7713b1edbc 238
AnnaBridge 171:3a7713b1edbc 239 /** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
AnnaBridge 171:3a7713b1edbc 240 * @{
AnnaBridge 171:3a7713b1edbc 241 */
AnnaBridge 171:3a7713b1edbc 242 #define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
AnnaBridge 171:3a7713b1edbc 243 #define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
AnnaBridge 171:3a7713b1edbc 244 /**
AnnaBridge 171:3a7713b1edbc 245 * @}
AnnaBridge 171:3a7713b1edbc 246 */
AnnaBridge 171:3a7713b1edbc 247
AnnaBridge 171:3a7713b1edbc 248 /** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
AnnaBridge 171:3a7713b1edbc 249 * @{
AnnaBridge 171:3a7713b1edbc 250 */
AnnaBridge 171:3a7713b1edbc 251 #define LL_LPTIM_CLK_FILTER_NONE 0x00000000U /*!<Any external clock signal level change is considered as a valid transition*/
AnnaBridge 171:3a7713b1edbc 252 #define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
AnnaBridge 171:3a7713b1edbc 253 #define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
AnnaBridge 171:3a7713b1edbc 254 #define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
AnnaBridge 171:3a7713b1edbc 255 /**
AnnaBridge 171:3a7713b1edbc 256 * @}
AnnaBridge 171:3a7713b1edbc 257 */
AnnaBridge 171:3a7713b1edbc 258
AnnaBridge 171:3a7713b1edbc 259 /** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
AnnaBridge 171:3a7713b1edbc 260 * @{
AnnaBridge 171:3a7713b1edbc 261 */
AnnaBridge 171:3a7713b1edbc 262 #define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
AnnaBridge 171:3a7713b1edbc 263 #define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
AnnaBridge 171:3a7713b1edbc 264 #define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
AnnaBridge 171:3a7713b1edbc 265 /**
AnnaBridge 171:3a7713b1edbc 266 * @}
AnnaBridge 171:3a7713b1edbc 267 */
AnnaBridge 171:3a7713b1edbc 268
AnnaBridge 171:3a7713b1edbc 269 /** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
AnnaBridge 171:3a7713b1edbc 270 * @{
AnnaBridge 171:3a7713b1edbc 271 */
AnnaBridge 171:3a7713b1edbc 272 #define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
AnnaBridge 171:3a7713b1edbc 273 #define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
AnnaBridge 171:3a7713b1edbc 274 #define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
AnnaBridge 171:3a7713b1edbc 275 /**
AnnaBridge 171:3a7713b1edbc 276 * @}
AnnaBridge 171:3a7713b1edbc 277 */
AnnaBridge 171:3a7713b1edbc 278
AnnaBridge 171:3a7713b1edbc 279
AnnaBridge 171:3a7713b1edbc 280 /**
AnnaBridge 171:3a7713b1edbc 281 * @}
AnnaBridge 171:3a7713b1edbc 282 */
AnnaBridge 171:3a7713b1edbc 283
AnnaBridge 171:3a7713b1edbc 284 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 285 /** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
AnnaBridge 171:3a7713b1edbc 286 * @{
AnnaBridge 171:3a7713b1edbc 287 */
AnnaBridge 171:3a7713b1edbc 288
AnnaBridge 171:3a7713b1edbc 289 /** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge 171:3a7713b1edbc 290 * @{
AnnaBridge 171:3a7713b1edbc 291 */
AnnaBridge 171:3a7713b1edbc 292
AnnaBridge 171:3a7713b1edbc 293 /**
AnnaBridge 171:3a7713b1edbc 294 * @brief Write a value in LPTIM register
AnnaBridge 171:3a7713b1edbc 295 * @param __INSTANCE__ LPTIM Instance
AnnaBridge 171:3a7713b1edbc 296 * @param __REG__ Register to be written
AnnaBridge 171:3a7713b1edbc 297 * @param __VALUE__ Value to be written in the register
AnnaBridge 171:3a7713b1edbc 298 * @retval None
AnnaBridge 171:3a7713b1edbc 299 */
AnnaBridge 171:3a7713b1edbc 300 #define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge 171:3a7713b1edbc 301
AnnaBridge 171:3a7713b1edbc 302 /**
AnnaBridge 171:3a7713b1edbc 303 * @brief Read a value in LPTIM register
AnnaBridge 171:3a7713b1edbc 304 * @param __INSTANCE__ LPTIM Instance
AnnaBridge 171:3a7713b1edbc 305 * @param __REG__ Register to be read
AnnaBridge 171:3a7713b1edbc 306 * @retval Register value
AnnaBridge 171:3a7713b1edbc 307 */
AnnaBridge 171:3a7713b1edbc 308 #define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge 171:3a7713b1edbc 309 /**
AnnaBridge 171:3a7713b1edbc 310 * @}
AnnaBridge 171:3a7713b1edbc 311 */
AnnaBridge 171:3a7713b1edbc 312
AnnaBridge 171:3a7713b1edbc 313 /**
AnnaBridge 171:3a7713b1edbc 314 * @}
AnnaBridge 171:3a7713b1edbc 315 */
AnnaBridge 171:3a7713b1edbc 316
AnnaBridge 171:3a7713b1edbc 317
AnnaBridge 171:3a7713b1edbc 318 /* Exported functions --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 319 /** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
AnnaBridge 171:3a7713b1edbc 320 * @{
AnnaBridge 171:3a7713b1edbc 321 */
AnnaBridge 171:3a7713b1edbc 322
AnnaBridge 171:3a7713b1edbc 323 /** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
AnnaBridge 171:3a7713b1edbc 324 * @{
AnnaBridge 171:3a7713b1edbc 325 */
AnnaBridge 171:3a7713b1edbc 326
AnnaBridge 171:3a7713b1edbc 327 /**
AnnaBridge 171:3a7713b1edbc 328 * @brief Enable the LPTIM instance
AnnaBridge 171:3a7713b1edbc 329 * @note After setting the ENABLE bit, a delay of two counter clock is needed
AnnaBridge 171:3a7713b1edbc 330 * before the LPTIM instance is actually enabled.
AnnaBridge 171:3a7713b1edbc 331 * @rmtoll CR ENABLE LL_LPTIM_Enable
AnnaBridge 171:3a7713b1edbc 332 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 333 * @retval None
AnnaBridge 171:3a7713b1edbc 334 */
AnnaBridge 171:3a7713b1edbc 335 __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 336 {
AnnaBridge 171:3a7713b1edbc 337 SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
AnnaBridge 171:3a7713b1edbc 338 }
AnnaBridge 171:3a7713b1edbc 339
AnnaBridge 171:3a7713b1edbc 340 /**
AnnaBridge 171:3a7713b1edbc 341 * @brief Disable the LPTIM instance
AnnaBridge 171:3a7713b1edbc 342 * @rmtoll CR ENABLE LL_LPTIM_Disable
AnnaBridge 171:3a7713b1edbc 343 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 344 * @retval None
AnnaBridge 171:3a7713b1edbc 345 */
AnnaBridge 171:3a7713b1edbc 346 __STATIC_INLINE void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 347 {
AnnaBridge 171:3a7713b1edbc 348 CLEAR_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
AnnaBridge 171:3a7713b1edbc 349 }
AnnaBridge 171:3a7713b1edbc 350
AnnaBridge 171:3a7713b1edbc 351 /**
AnnaBridge 171:3a7713b1edbc 352 * @brief Indicates whether the LPTIM instance is enabled.
AnnaBridge 171:3a7713b1edbc 353 * @rmtoll CR ENABLE LL_LPTIM_IsEnabled
AnnaBridge 171:3a7713b1edbc 354 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 355 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 356 */
AnnaBridge 171:3a7713b1edbc 357 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 358 {
AnnaBridge 171:3a7713b1edbc 359 return (READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == (LPTIM_CR_ENABLE));
AnnaBridge 171:3a7713b1edbc 360 }
AnnaBridge 171:3a7713b1edbc 361
AnnaBridge 171:3a7713b1edbc 362 /**
AnnaBridge 171:3a7713b1edbc 363 * @brief Starts the LPTIM counter in the desired mode.
AnnaBridge 171:3a7713b1edbc 364 * @note LPTIM instance must be enabled before starting the counter.
AnnaBridge 171:3a7713b1edbc 365 * @note It is possible to change on the fly from One Shot mode to
AnnaBridge 171:3a7713b1edbc 366 * Continuous mode.
AnnaBridge 171:3a7713b1edbc 367 * @rmtoll CR CNTSTRT LL_LPTIM_StartCounter\n
AnnaBridge 171:3a7713b1edbc 368 * CR SNGSTRT LL_LPTIM_StartCounter
AnnaBridge 171:3a7713b1edbc 369 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 370 * @param OperatingMode This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 371 * @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
AnnaBridge 171:3a7713b1edbc 372 * @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
AnnaBridge 171:3a7713b1edbc 373 * @retval None
AnnaBridge 171:3a7713b1edbc 374 */
AnnaBridge 171:3a7713b1edbc 375 __STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
AnnaBridge 171:3a7713b1edbc 376 {
AnnaBridge 171:3a7713b1edbc 377 MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
AnnaBridge 171:3a7713b1edbc 378 }
AnnaBridge 171:3a7713b1edbc 379
AnnaBridge 171:3a7713b1edbc 380
AnnaBridge 171:3a7713b1edbc 381 /**
AnnaBridge 171:3a7713b1edbc 382 * @brief Set the LPTIM registers update mode (enable/disable register preload)
AnnaBridge 171:3a7713b1edbc 383 * @note This function must be called when the LPTIM instance is disabled.
AnnaBridge 171:3a7713b1edbc 384 * @rmtoll CFGR PRELOAD LL_LPTIM_SetUpdateMode
AnnaBridge 171:3a7713b1edbc 385 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 386 * @param UpdateMode This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 387 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
AnnaBridge 171:3a7713b1edbc 388 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
AnnaBridge 171:3a7713b1edbc 389 * @retval None
AnnaBridge 171:3a7713b1edbc 390 */
AnnaBridge 171:3a7713b1edbc 391 __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
AnnaBridge 171:3a7713b1edbc 392 {
AnnaBridge 171:3a7713b1edbc 393 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
AnnaBridge 171:3a7713b1edbc 394 }
AnnaBridge 171:3a7713b1edbc 395
AnnaBridge 171:3a7713b1edbc 396 /**
AnnaBridge 171:3a7713b1edbc 397 * @brief Get the LPTIM registers update mode
AnnaBridge 171:3a7713b1edbc 398 * @rmtoll CFGR PRELOAD LL_LPTIM_GetUpdateMode
AnnaBridge 171:3a7713b1edbc 399 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 400 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 401 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
AnnaBridge 171:3a7713b1edbc 402 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
AnnaBridge 171:3a7713b1edbc 403 */
AnnaBridge 171:3a7713b1edbc 404 __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 405 {
AnnaBridge 171:3a7713b1edbc 406 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
AnnaBridge 171:3a7713b1edbc 407 }
AnnaBridge 171:3a7713b1edbc 408
AnnaBridge 171:3a7713b1edbc 409 /**
AnnaBridge 171:3a7713b1edbc 410 * @brief Set the auto reload value
AnnaBridge 171:3a7713b1edbc 411 * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
AnnaBridge 171:3a7713b1edbc 412 * @note After a write to the LPTIMx_ARR register a new write operation to the
AnnaBridge 171:3a7713b1edbc 413 * same register can only be performed when the previous write operation
AnnaBridge 171:3a7713b1edbc 414 * is completed. Any successive write before the ARROK flag be set, will
AnnaBridge 171:3a7713b1edbc 415 * lead to unpredictable results.
AnnaBridge 171:3a7713b1edbc 416 * @note autoreload value be strictly greater than the compare value.
AnnaBridge 171:3a7713b1edbc 417 * @rmtoll ARR ARR LL_LPTIM_SetAutoReload
AnnaBridge 171:3a7713b1edbc 418 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 419 * @param AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
AnnaBridge 171:3a7713b1edbc 420 * @retval None
AnnaBridge 171:3a7713b1edbc 421 */
AnnaBridge 171:3a7713b1edbc 422 __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
AnnaBridge 171:3a7713b1edbc 423 {
AnnaBridge 171:3a7713b1edbc 424 MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
AnnaBridge 171:3a7713b1edbc 425 }
AnnaBridge 171:3a7713b1edbc 426
AnnaBridge 171:3a7713b1edbc 427 /**
AnnaBridge 171:3a7713b1edbc 428 * @brief Get actual auto reload value
AnnaBridge 171:3a7713b1edbc 429 * @rmtoll ARR ARR LL_LPTIM_GetAutoReload
AnnaBridge 171:3a7713b1edbc 430 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 431 * @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
AnnaBridge 171:3a7713b1edbc 432 */
AnnaBridge 171:3a7713b1edbc 433 __STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 434 {
AnnaBridge 171:3a7713b1edbc 435 return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
AnnaBridge 171:3a7713b1edbc 436 }
AnnaBridge 171:3a7713b1edbc 437
AnnaBridge 171:3a7713b1edbc 438 /**
AnnaBridge 171:3a7713b1edbc 439 * @brief Set the compare value
AnnaBridge 171:3a7713b1edbc 440 * @note After a write to the LPTIMx_CMP register a new write operation to the
AnnaBridge 171:3a7713b1edbc 441 * same register can only be performed when the previous write operation
AnnaBridge 171:3a7713b1edbc 442 * is completed. Any successive write before the CMPOK flag be set, will
AnnaBridge 171:3a7713b1edbc 443 * lead to unpredictable results.
AnnaBridge 171:3a7713b1edbc 444 * @rmtoll CMP CMP LL_LPTIM_SetCompare
AnnaBridge 171:3a7713b1edbc 445 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 446 * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
AnnaBridge 171:3a7713b1edbc 447 * @retval None
AnnaBridge 171:3a7713b1edbc 448 */
AnnaBridge 171:3a7713b1edbc 449 __STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
AnnaBridge 171:3a7713b1edbc 450 {
AnnaBridge 171:3a7713b1edbc 451 MODIFY_REG(LPTIMx->CMP, LPTIM_CMP_CMP, CompareValue);
AnnaBridge 171:3a7713b1edbc 452 }
AnnaBridge 171:3a7713b1edbc 453
AnnaBridge 171:3a7713b1edbc 454 /**
AnnaBridge 171:3a7713b1edbc 455 * @brief Get actual compare value
AnnaBridge 171:3a7713b1edbc 456 * @rmtoll CMP CMP LL_LPTIM_GetCompare
AnnaBridge 171:3a7713b1edbc 457 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 458 * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
AnnaBridge 171:3a7713b1edbc 459 */
AnnaBridge 171:3a7713b1edbc 460 __STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 461 {
AnnaBridge 171:3a7713b1edbc 462 return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP));
AnnaBridge 171:3a7713b1edbc 463 }
AnnaBridge 171:3a7713b1edbc 464
AnnaBridge 171:3a7713b1edbc 465 /**
AnnaBridge 171:3a7713b1edbc 466 * @brief Get actual counter value
AnnaBridge 171:3a7713b1edbc 467 * @note When the LPTIM instance is running with an asynchronous clock, reading
AnnaBridge 171:3a7713b1edbc 468 * the LPTIMx_CNT register may return unreliable values. So in this case
AnnaBridge 171:3a7713b1edbc 469 * it is necessary to perform two consecutive read accesses and verify
AnnaBridge 171:3a7713b1edbc 470 * that the two returned values are identical.
AnnaBridge 171:3a7713b1edbc 471 * @rmtoll CNT CNT LL_LPTIM_GetCounter
AnnaBridge 171:3a7713b1edbc 472 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 473 * @retval Counter value
AnnaBridge 171:3a7713b1edbc 474 */
AnnaBridge 171:3a7713b1edbc 475 __STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 476 {
AnnaBridge 171:3a7713b1edbc 477 return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
AnnaBridge 171:3a7713b1edbc 478 }
AnnaBridge 171:3a7713b1edbc 479
AnnaBridge 171:3a7713b1edbc 480 /**
AnnaBridge 171:3a7713b1edbc 481 * @brief Set the counter mode (selection of the LPTIM counter clock source).
AnnaBridge 171:3a7713b1edbc 482 * @note The counter mode can be set only when the LPTIM instance is disabled.
AnnaBridge 171:3a7713b1edbc 483 * @rmtoll CFGR COUNTMODE LL_LPTIM_SetCounterMode
AnnaBridge 171:3a7713b1edbc 484 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 485 * @param CounterMode This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 486 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
AnnaBridge 171:3a7713b1edbc 487 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
AnnaBridge 171:3a7713b1edbc 488 * @retval None
AnnaBridge 171:3a7713b1edbc 489 */
AnnaBridge 171:3a7713b1edbc 490 __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
AnnaBridge 171:3a7713b1edbc 491 {
AnnaBridge 171:3a7713b1edbc 492 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
AnnaBridge 171:3a7713b1edbc 493 }
AnnaBridge 171:3a7713b1edbc 494
AnnaBridge 171:3a7713b1edbc 495 /**
AnnaBridge 171:3a7713b1edbc 496 * @brief Get the counter mode
AnnaBridge 171:3a7713b1edbc 497 * @rmtoll CFGR COUNTMODE LL_LPTIM_GetCounterMode
AnnaBridge 171:3a7713b1edbc 498 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 499 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 500 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
AnnaBridge 171:3a7713b1edbc 501 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
AnnaBridge 171:3a7713b1edbc 502 */
AnnaBridge 171:3a7713b1edbc 503 __STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 504 {
AnnaBridge 171:3a7713b1edbc 505 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
AnnaBridge 171:3a7713b1edbc 506 }
AnnaBridge 171:3a7713b1edbc 507
AnnaBridge 171:3a7713b1edbc 508 /**
AnnaBridge 171:3a7713b1edbc 509 * @brief Configure the LPTIM instance output (LPTIMx_OUT)
AnnaBridge 171:3a7713b1edbc 510 * @note This function must be called when the LPTIM instance is disabled.
AnnaBridge 171:3a7713b1edbc 511 * @note Regarding the LPTIM output polarity the change takes effect
AnnaBridge 171:3a7713b1edbc 512 * immediately, so the output default value will change immediately after
AnnaBridge 171:3a7713b1edbc 513 * the polarity is re-configured, even before the timer is enabled.
AnnaBridge 171:3a7713b1edbc 514 * @rmtoll CFGR WAVE LL_LPTIM_ConfigOutput\n
AnnaBridge 171:3a7713b1edbc 515 * CFGR WAVPOL LL_LPTIM_ConfigOutput
AnnaBridge 171:3a7713b1edbc 516 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 517 * @param Waveform This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 518 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
AnnaBridge 171:3a7713b1edbc 519 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
AnnaBridge 171:3a7713b1edbc 520 * @param Polarity This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 521 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
AnnaBridge 171:3a7713b1edbc 522 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
AnnaBridge 171:3a7713b1edbc 523 * @retval None
AnnaBridge 171:3a7713b1edbc 524 */
AnnaBridge 171:3a7713b1edbc 525 __STATIC_INLINE void LL_LPTIM_ConfigOutput(LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
AnnaBridge 171:3a7713b1edbc 526 {
AnnaBridge 171:3a7713b1edbc 527 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL, Waveform | Polarity);
AnnaBridge 171:3a7713b1edbc 528 }
AnnaBridge 171:3a7713b1edbc 529
AnnaBridge 171:3a7713b1edbc 530 /**
AnnaBridge 171:3a7713b1edbc 531 * @brief Set waveform shape
AnnaBridge 171:3a7713b1edbc 532 * @rmtoll CFGR WAVE LL_LPTIM_SetWaveform
AnnaBridge 171:3a7713b1edbc 533 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 534 * @param Waveform This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 535 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
AnnaBridge 171:3a7713b1edbc 536 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
AnnaBridge 171:3a7713b1edbc 537 * @retval None
AnnaBridge 171:3a7713b1edbc 538 */
AnnaBridge 171:3a7713b1edbc 539 __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
AnnaBridge 171:3a7713b1edbc 540 {
AnnaBridge 171:3a7713b1edbc 541 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
AnnaBridge 171:3a7713b1edbc 542 }
AnnaBridge 171:3a7713b1edbc 543
AnnaBridge 171:3a7713b1edbc 544 /**
AnnaBridge 171:3a7713b1edbc 545 * @brief Get actual waveform shape
AnnaBridge 171:3a7713b1edbc 546 * @rmtoll CFGR WAVE LL_LPTIM_GetWaveform
AnnaBridge 171:3a7713b1edbc 547 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 548 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 549 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
AnnaBridge 171:3a7713b1edbc 550 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
AnnaBridge 171:3a7713b1edbc 551 */
AnnaBridge 171:3a7713b1edbc 552 __STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 553 {
AnnaBridge 171:3a7713b1edbc 554 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
AnnaBridge 171:3a7713b1edbc 555 }
AnnaBridge 171:3a7713b1edbc 556
AnnaBridge 171:3a7713b1edbc 557 /**
AnnaBridge 171:3a7713b1edbc 558 * @brief Set output polarity
AnnaBridge 171:3a7713b1edbc 559 * @rmtoll CFGR WAVPOL LL_LPTIM_SetPolarity
AnnaBridge 171:3a7713b1edbc 560 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 561 * @param Polarity This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 562 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
AnnaBridge 171:3a7713b1edbc 563 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
AnnaBridge 171:3a7713b1edbc 564 * @retval None
AnnaBridge 171:3a7713b1edbc 565 */
AnnaBridge 171:3a7713b1edbc 566 __STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
AnnaBridge 171:3a7713b1edbc 567 {
AnnaBridge 171:3a7713b1edbc 568 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, Polarity);
AnnaBridge 171:3a7713b1edbc 569 }
AnnaBridge 171:3a7713b1edbc 570
AnnaBridge 171:3a7713b1edbc 571 /**
AnnaBridge 171:3a7713b1edbc 572 * @brief Get actual output polarity
AnnaBridge 171:3a7713b1edbc 573 * @rmtoll CFGR WAVPOL LL_LPTIM_GetPolarity
AnnaBridge 171:3a7713b1edbc 574 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 575 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 576 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
AnnaBridge 171:3a7713b1edbc 577 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
AnnaBridge 171:3a7713b1edbc 578 */
AnnaBridge 171:3a7713b1edbc 579 __STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 580 {
AnnaBridge 171:3a7713b1edbc 581 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL));
AnnaBridge 171:3a7713b1edbc 582 }
AnnaBridge 171:3a7713b1edbc 583
AnnaBridge 171:3a7713b1edbc 584 /**
AnnaBridge 171:3a7713b1edbc 585 * @brief Set actual prescaler division ratio.
AnnaBridge 171:3a7713b1edbc 586 * @note This function must be called when the LPTIM instance is disabled.
AnnaBridge 171:3a7713b1edbc 587 * @note When the LPTIM is configured to be clocked by an internal clock source
AnnaBridge 171:3a7713b1edbc 588 * and the LPTIM counter is configured to be updated by active edges
AnnaBridge 171:3a7713b1edbc 589 * detected on the LPTIM external Input1, the internal clock provided to
AnnaBridge 171:3a7713b1edbc 590 * the LPTIM must be not be prescaled.
AnnaBridge 171:3a7713b1edbc 591 * @rmtoll CFGR PRESC LL_LPTIM_SetPrescaler
AnnaBridge 171:3a7713b1edbc 592 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 593 * @param Prescaler This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 594 * @arg @ref LL_LPTIM_PRESCALER_DIV1
AnnaBridge 171:3a7713b1edbc 595 * @arg @ref LL_LPTIM_PRESCALER_DIV2
AnnaBridge 171:3a7713b1edbc 596 * @arg @ref LL_LPTIM_PRESCALER_DIV4
AnnaBridge 171:3a7713b1edbc 597 * @arg @ref LL_LPTIM_PRESCALER_DIV8
AnnaBridge 171:3a7713b1edbc 598 * @arg @ref LL_LPTIM_PRESCALER_DIV16
AnnaBridge 171:3a7713b1edbc 599 * @arg @ref LL_LPTIM_PRESCALER_DIV32
AnnaBridge 171:3a7713b1edbc 600 * @arg @ref LL_LPTIM_PRESCALER_DIV64
AnnaBridge 171:3a7713b1edbc 601 * @arg @ref LL_LPTIM_PRESCALER_DIV128
AnnaBridge 171:3a7713b1edbc 602 * @retval None
AnnaBridge 171:3a7713b1edbc 603 */
AnnaBridge 171:3a7713b1edbc 604 __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
AnnaBridge 171:3a7713b1edbc 605 {
AnnaBridge 171:3a7713b1edbc 606 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
AnnaBridge 171:3a7713b1edbc 607 }
AnnaBridge 171:3a7713b1edbc 608
AnnaBridge 171:3a7713b1edbc 609 /**
AnnaBridge 171:3a7713b1edbc 610 * @brief Get actual prescaler division ratio.
AnnaBridge 171:3a7713b1edbc 611 * @rmtoll CFGR PRESC LL_LPTIM_GetPrescaler
AnnaBridge 171:3a7713b1edbc 612 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 613 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 614 * @arg @ref LL_LPTIM_PRESCALER_DIV1
AnnaBridge 171:3a7713b1edbc 615 * @arg @ref LL_LPTIM_PRESCALER_DIV2
AnnaBridge 171:3a7713b1edbc 616 * @arg @ref LL_LPTIM_PRESCALER_DIV4
AnnaBridge 171:3a7713b1edbc 617 * @arg @ref LL_LPTIM_PRESCALER_DIV8
AnnaBridge 171:3a7713b1edbc 618 * @arg @ref LL_LPTIM_PRESCALER_DIV16
AnnaBridge 171:3a7713b1edbc 619 * @arg @ref LL_LPTIM_PRESCALER_DIV32
AnnaBridge 171:3a7713b1edbc 620 * @arg @ref LL_LPTIM_PRESCALER_DIV64
AnnaBridge 171:3a7713b1edbc 621 * @arg @ref LL_LPTIM_PRESCALER_DIV128
AnnaBridge 171:3a7713b1edbc 622 */
AnnaBridge 171:3a7713b1edbc 623 __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 624 {
AnnaBridge 171:3a7713b1edbc 625 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
AnnaBridge 171:3a7713b1edbc 626 }
AnnaBridge 171:3a7713b1edbc 627
AnnaBridge 171:3a7713b1edbc 628
AnnaBridge 171:3a7713b1edbc 629 /**
AnnaBridge 171:3a7713b1edbc 630 * @}
AnnaBridge 171:3a7713b1edbc 631 */
AnnaBridge 171:3a7713b1edbc 632
AnnaBridge 171:3a7713b1edbc 633 /** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
AnnaBridge 171:3a7713b1edbc 634 * @{
AnnaBridge 171:3a7713b1edbc 635 */
AnnaBridge 171:3a7713b1edbc 636
AnnaBridge 171:3a7713b1edbc 637 /**
AnnaBridge 171:3a7713b1edbc 638 * @brief Enable the timeout function
AnnaBridge 171:3a7713b1edbc 639 * @note This function must be called when the LPTIM instance is disabled.
AnnaBridge 171:3a7713b1edbc 640 * @note The first trigger event will start the timer, any successive trigger
AnnaBridge 171:3a7713b1edbc 641 * event will reset the counter and the timer will restart.
AnnaBridge 171:3a7713b1edbc 642 * @note The timeout value corresponds to the compare value; if no trigger
AnnaBridge 171:3a7713b1edbc 643 * occurs within the expected time frame, the MCU is waked-up by the
AnnaBridge 171:3a7713b1edbc 644 * compare match event.
AnnaBridge 171:3a7713b1edbc 645 * @rmtoll CFGR TIMOUT LL_LPTIM_EnableTimeout
AnnaBridge 171:3a7713b1edbc 646 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 647 * @retval None
AnnaBridge 171:3a7713b1edbc 648 */
AnnaBridge 171:3a7713b1edbc 649 __STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 650 {
AnnaBridge 171:3a7713b1edbc 651 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
AnnaBridge 171:3a7713b1edbc 652 }
AnnaBridge 171:3a7713b1edbc 653
AnnaBridge 171:3a7713b1edbc 654 /**
AnnaBridge 171:3a7713b1edbc 655 * @brief Disable the timeout function
AnnaBridge 171:3a7713b1edbc 656 * @note This function must be called when the LPTIM instance is disabled.
AnnaBridge 171:3a7713b1edbc 657 * @note A trigger event arriving when the timer is already started will be
AnnaBridge 171:3a7713b1edbc 658 * ignored.
AnnaBridge 171:3a7713b1edbc 659 * @rmtoll CFGR TIMOUT LL_LPTIM_DisableTimeout
AnnaBridge 171:3a7713b1edbc 660 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 661 * @retval None
AnnaBridge 171:3a7713b1edbc 662 */
AnnaBridge 171:3a7713b1edbc 663 __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 664 {
AnnaBridge 171:3a7713b1edbc 665 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
AnnaBridge 171:3a7713b1edbc 666 }
AnnaBridge 171:3a7713b1edbc 667
AnnaBridge 171:3a7713b1edbc 668 /**
AnnaBridge 171:3a7713b1edbc 669 * @brief Indicate whether the timeout function is enabled.
AnnaBridge 171:3a7713b1edbc 670 * @rmtoll CFGR TIMOUT LL_LPTIM_IsEnabledTimeout
AnnaBridge 171:3a7713b1edbc 671 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 672 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 673 */
AnnaBridge 171:3a7713b1edbc 674 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 675 {
AnnaBridge 171:3a7713b1edbc 676 return (READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == (LPTIM_CFGR_TIMOUT));
AnnaBridge 171:3a7713b1edbc 677 }
AnnaBridge 171:3a7713b1edbc 678
AnnaBridge 171:3a7713b1edbc 679 /**
AnnaBridge 171:3a7713b1edbc 680 * @brief Start the LPTIM counter
AnnaBridge 171:3a7713b1edbc 681 * @note This function must be called when the LPTIM instance is disabled.
AnnaBridge 171:3a7713b1edbc 682 * @rmtoll CFGR TRIGEN LL_LPTIM_TrigSw
AnnaBridge 171:3a7713b1edbc 683 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 684 * @retval None
AnnaBridge 171:3a7713b1edbc 685 */
AnnaBridge 171:3a7713b1edbc 686 __STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 687 {
AnnaBridge 171:3a7713b1edbc 688 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
AnnaBridge 171:3a7713b1edbc 689 }
AnnaBridge 171:3a7713b1edbc 690
AnnaBridge 171:3a7713b1edbc 691 /**
AnnaBridge 171:3a7713b1edbc 692 * @brief Configure the external trigger used as a trigger event for the LPTIM.
AnnaBridge 171:3a7713b1edbc 693 * @note This function must be called when the LPTIM instance is disabled.
AnnaBridge 171:3a7713b1edbc 694 * @note An internal clock source must be present when a digital filter is
AnnaBridge 171:3a7713b1edbc 695 * required for the trigger.
AnnaBridge 171:3a7713b1edbc 696 * @rmtoll CFGR TRIGSEL LL_LPTIM_ConfigTrigger\n
AnnaBridge 171:3a7713b1edbc 697 * CFGR TRGFLT LL_LPTIM_ConfigTrigger\n
AnnaBridge 171:3a7713b1edbc 698 * CFGR TRIGEN LL_LPTIM_ConfigTrigger
AnnaBridge 171:3a7713b1edbc 699 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 700 * @param Source This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 701 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
AnnaBridge 171:3a7713b1edbc 702 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
AnnaBridge 171:3a7713b1edbc 703 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
AnnaBridge 171:3a7713b1edbc 704 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
AnnaBridge 171:3a7713b1edbc 705 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
AnnaBridge 171:3a7713b1edbc 706 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
AnnaBridge 171:3a7713b1edbc 707 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
AnnaBridge 171:3a7713b1edbc 708 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
AnnaBridge 171:3a7713b1edbc 709 * @param Filter This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 710 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
AnnaBridge 171:3a7713b1edbc 711 * @arg @ref LL_LPTIM_TRIG_FILTER_2
AnnaBridge 171:3a7713b1edbc 712 * @arg @ref LL_LPTIM_TRIG_FILTER_4
AnnaBridge 171:3a7713b1edbc 713 * @arg @ref LL_LPTIM_TRIG_FILTER_8
AnnaBridge 171:3a7713b1edbc 714 * @param Polarity This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 715 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
AnnaBridge 171:3a7713b1edbc 716 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
AnnaBridge 171:3a7713b1edbc 717 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
AnnaBridge 171:3a7713b1edbc 718 * @retval None
AnnaBridge 171:3a7713b1edbc 719 */
AnnaBridge 171:3a7713b1edbc 720 __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
AnnaBridge 171:3a7713b1edbc 721 {
AnnaBridge 171:3a7713b1edbc 722 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
AnnaBridge 171:3a7713b1edbc 723 }
AnnaBridge 171:3a7713b1edbc 724
AnnaBridge 171:3a7713b1edbc 725 /**
AnnaBridge 171:3a7713b1edbc 726 * @brief Get actual external trigger source.
AnnaBridge 171:3a7713b1edbc 727 * @rmtoll CFGR TRIGSEL LL_LPTIM_GetTriggerSource
AnnaBridge 171:3a7713b1edbc 728 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 729 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 730 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
AnnaBridge 171:3a7713b1edbc 731 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
AnnaBridge 171:3a7713b1edbc 732 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
AnnaBridge 171:3a7713b1edbc 733 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
AnnaBridge 171:3a7713b1edbc 734 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
AnnaBridge 171:3a7713b1edbc 735 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
AnnaBridge 171:3a7713b1edbc 736 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
AnnaBridge 171:3a7713b1edbc 737 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
AnnaBridge 171:3a7713b1edbc 738 */
AnnaBridge 171:3a7713b1edbc 739 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 740 {
AnnaBridge 171:3a7713b1edbc 741 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
AnnaBridge 171:3a7713b1edbc 742 }
AnnaBridge 171:3a7713b1edbc 743
AnnaBridge 171:3a7713b1edbc 744 /**
AnnaBridge 171:3a7713b1edbc 745 * @brief Get actual external trigger filter.
AnnaBridge 171:3a7713b1edbc 746 * @rmtoll CFGR TRGFLT LL_LPTIM_GetTriggerFilter
AnnaBridge 171:3a7713b1edbc 747 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 748 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 749 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
AnnaBridge 171:3a7713b1edbc 750 * @arg @ref LL_LPTIM_TRIG_FILTER_2
AnnaBridge 171:3a7713b1edbc 751 * @arg @ref LL_LPTIM_TRIG_FILTER_4
AnnaBridge 171:3a7713b1edbc 752 * @arg @ref LL_LPTIM_TRIG_FILTER_8
AnnaBridge 171:3a7713b1edbc 753 */
AnnaBridge 171:3a7713b1edbc 754 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 755 {
AnnaBridge 171:3a7713b1edbc 756 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
AnnaBridge 171:3a7713b1edbc 757 }
AnnaBridge 171:3a7713b1edbc 758
AnnaBridge 171:3a7713b1edbc 759 /**
AnnaBridge 171:3a7713b1edbc 760 * @brief Get actual external trigger polarity.
AnnaBridge 171:3a7713b1edbc 761 * @rmtoll CFGR TRIGEN LL_LPTIM_GetTriggerPolarity
AnnaBridge 171:3a7713b1edbc 762 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 763 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 764 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
AnnaBridge 171:3a7713b1edbc 765 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
AnnaBridge 171:3a7713b1edbc 766 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
AnnaBridge 171:3a7713b1edbc 767 */
AnnaBridge 171:3a7713b1edbc 768 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 769 {
AnnaBridge 171:3a7713b1edbc 770 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
AnnaBridge 171:3a7713b1edbc 771 }
AnnaBridge 171:3a7713b1edbc 772
AnnaBridge 171:3a7713b1edbc 773 /**
AnnaBridge 171:3a7713b1edbc 774 * @}
AnnaBridge 171:3a7713b1edbc 775 */
AnnaBridge 171:3a7713b1edbc 776
AnnaBridge 171:3a7713b1edbc 777 /** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
AnnaBridge 171:3a7713b1edbc 778 * @{
AnnaBridge 171:3a7713b1edbc 779 */
AnnaBridge 171:3a7713b1edbc 780
AnnaBridge 171:3a7713b1edbc 781 /**
AnnaBridge 171:3a7713b1edbc 782 * @brief Set the source of the clock used by the LPTIM instance.
AnnaBridge 171:3a7713b1edbc 783 * @note This function must be called when the LPTIM instance is disabled.
AnnaBridge 171:3a7713b1edbc 784 * @rmtoll CFGR CKSEL LL_LPTIM_SetClockSource
AnnaBridge 171:3a7713b1edbc 785 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 786 * @param ClockSource This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 787 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
AnnaBridge 171:3a7713b1edbc 788 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
AnnaBridge 171:3a7713b1edbc 789 * @retval None
AnnaBridge 171:3a7713b1edbc 790 */
AnnaBridge 171:3a7713b1edbc 791 __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
AnnaBridge 171:3a7713b1edbc 792 {
AnnaBridge 171:3a7713b1edbc 793 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
AnnaBridge 171:3a7713b1edbc 794 }
AnnaBridge 171:3a7713b1edbc 795
AnnaBridge 171:3a7713b1edbc 796 /**
AnnaBridge 171:3a7713b1edbc 797 * @brief Get actual LPTIM instance clock source.
AnnaBridge 171:3a7713b1edbc 798 * @rmtoll CFGR CKSEL LL_LPTIM_GetClockSource
AnnaBridge 171:3a7713b1edbc 799 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 800 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 801 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
AnnaBridge 171:3a7713b1edbc 802 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
AnnaBridge 171:3a7713b1edbc 803 */
AnnaBridge 171:3a7713b1edbc 804 __STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 805 {
AnnaBridge 171:3a7713b1edbc 806 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
AnnaBridge 171:3a7713b1edbc 807 }
AnnaBridge 171:3a7713b1edbc 808
AnnaBridge 171:3a7713b1edbc 809 /**
AnnaBridge 171:3a7713b1edbc 810 * @brief Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.
AnnaBridge 171:3a7713b1edbc 811 * @note This function must be called when the LPTIM instance is disabled.
AnnaBridge 171:3a7713b1edbc 812 * @note When both external clock signal edges are considered active ones,
AnnaBridge 171:3a7713b1edbc 813 * the LPTIM must also be clocked by an internal clock source with a
AnnaBridge 171:3a7713b1edbc 814 * frequency equal to at least four times the external clock frequency.
AnnaBridge 171:3a7713b1edbc 815 * @note An internal clock source must be present when a digital filter is
AnnaBridge 171:3a7713b1edbc 816 * required for external clock.
AnnaBridge 171:3a7713b1edbc 817 * @rmtoll CFGR CKFLT LL_LPTIM_ConfigClock\n
AnnaBridge 171:3a7713b1edbc 818 * CFGR CKPOL LL_LPTIM_ConfigClock
AnnaBridge 171:3a7713b1edbc 819 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 820 * @param ClockFilter This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 821 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
AnnaBridge 171:3a7713b1edbc 822 * @arg @ref LL_LPTIM_CLK_FILTER_2
AnnaBridge 171:3a7713b1edbc 823 * @arg @ref LL_LPTIM_CLK_FILTER_4
AnnaBridge 171:3a7713b1edbc 824 * @arg @ref LL_LPTIM_CLK_FILTER_8
AnnaBridge 171:3a7713b1edbc 825 * @param ClockPolarity This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 826 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
AnnaBridge 171:3a7713b1edbc 827 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
AnnaBridge 171:3a7713b1edbc 828 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
AnnaBridge 171:3a7713b1edbc 829 * @retval None
AnnaBridge 171:3a7713b1edbc 830 */
AnnaBridge 171:3a7713b1edbc 831 __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
AnnaBridge 171:3a7713b1edbc 832 {
AnnaBridge 171:3a7713b1edbc 833 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
AnnaBridge 171:3a7713b1edbc 834 }
AnnaBridge 171:3a7713b1edbc 835
AnnaBridge 171:3a7713b1edbc 836 /**
AnnaBridge 171:3a7713b1edbc 837 * @brief Get actual clock polarity
AnnaBridge 171:3a7713b1edbc 838 * @rmtoll CFGR CKPOL LL_LPTIM_GetClockPolarity
AnnaBridge 171:3a7713b1edbc 839 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 840 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 841 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
AnnaBridge 171:3a7713b1edbc 842 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
AnnaBridge 171:3a7713b1edbc 843 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
AnnaBridge 171:3a7713b1edbc 844 */
AnnaBridge 171:3a7713b1edbc 845 __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 846 {
AnnaBridge 171:3a7713b1edbc 847 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
AnnaBridge 171:3a7713b1edbc 848 }
AnnaBridge 171:3a7713b1edbc 849
AnnaBridge 171:3a7713b1edbc 850 /**
AnnaBridge 171:3a7713b1edbc 851 * @brief Get actual clock digital filter
AnnaBridge 171:3a7713b1edbc 852 * @rmtoll CFGR CKFLT LL_LPTIM_GetClockFilter
AnnaBridge 171:3a7713b1edbc 853 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 854 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 855 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
AnnaBridge 171:3a7713b1edbc 856 * @arg @ref LL_LPTIM_CLK_FILTER_2
AnnaBridge 171:3a7713b1edbc 857 * @arg @ref LL_LPTIM_CLK_FILTER_4
AnnaBridge 171:3a7713b1edbc 858 * @arg @ref LL_LPTIM_CLK_FILTER_8
AnnaBridge 171:3a7713b1edbc 859 */
AnnaBridge 171:3a7713b1edbc 860 __STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 861 {
AnnaBridge 171:3a7713b1edbc 862 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
AnnaBridge 171:3a7713b1edbc 863 }
AnnaBridge 171:3a7713b1edbc 864
AnnaBridge 171:3a7713b1edbc 865 /**
AnnaBridge 171:3a7713b1edbc 866 * @}
AnnaBridge 171:3a7713b1edbc 867 */
AnnaBridge 171:3a7713b1edbc 868
AnnaBridge 171:3a7713b1edbc 869 /** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
AnnaBridge 171:3a7713b1edbc 870 * @{
AnnaBridge 171:3a7713b1edbc 871 */
AnnaBridge 171:3a7713b1edbc 872
AnnaBridge 171:3a7713b1edbc 873 /**
AnnaBridge 171:3a7713b1edbc 874 * @brief Configure the encoder mode.
AnnaBridge 171:3a7713b1edbc 875 * @note This function must be called when the LPTIM instance is disabled.
AnnaBridge 171:3a7713b1edbc 876 * @rmtoll CFGR CKPOL LL_LPTIM_SetEncoderMode
AnnaBridge 171:3a7713b1edbc 877 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 878 * @param EncoderMode This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 879 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
AnnaBridge 171:3a7713b1edbc 880 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
AnnaBridge 171:3a7713b1edbc 881 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
AnnaBridge 171:3a7713b1edbc 882 * @retval None
AnnaBridge 171:3a7713b1edbc 883 */
AnnaBridge 171:3a7713b1edbc 884 __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
AnnaBridge 171:3a7713b1edbc 885 {
AnnaBridge 171:3a7713b1edbc 886 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
AnnaBridge 171:3a7713b1edbc 887 }
AnnaBridge 171:3a7713b1edbc 888
AnnaBridge 171:3a7713b1edbc 889 /**
AnnaBridge 171:3a7713b1edbc 890 * @brief Get actual encoder mode.
AnnaBridge 171:3a7713b1edbc 891 * @rmtoll CFGR CKPOL LL_LPTIM_GetEncoderMode
AnnaBridge 171:3a7713b1edbc 892 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 893 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 894 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
AnnaBridge 171:3a7713b1edbc 895 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
AnnaBridge 171:3a7713b1edbc 896 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
AnnaBridge 171:3a7713b1edbc 897 */
AnnaBridge 171:3a7713b1edbc 898 __STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 899 {
AnnaBridge 171:3a7713b1edbc 900 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
AnnaBridge 171:3a7713b1edbc 901 }
AnnaBridge 171:3a7713b1edbc 902
AnnaBridge 171:3a7713b1edbc 903 /**
AnnaBridge 171:3a7713b1edbc 904 * @brief Enable the encoder mode
AnnaBridge 171:3a7713b1edbc 905 * @note This function must be called when the LPTIM instance is disabled.
AnnaBridge 171:3a7713b1edbc 906 * @note In this mode the LPTIM instance must be clocked by an internal clock
AnnaBridge 171:3a7713b1edbc 907 * source. Also, the prescaler division ratio must be equal to 1.
AnnaBridge 171:3a7713b1edbc 908 * @note LPTIM instance must be configured in continuous mode prior enabling
AnnaBridge 171:3a7713b1edbc 909 * the encoder mode.
AnnaBridge 171:3a7713b1edbc 910 * @rmtoll CFGR ENC LL_LPTIM_EnableEncoderMode
AnnaBridge 171:3a7713b1edbc 911 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 912 * @retval None
AnnaBridge 171:3a7713b1edbc 913 */
AnnaBridge 171:3a7713b1edbc 914 __STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 915 {
AnnaBridge 171:3a7713b1edbc 916 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
AnnaBridge 171:3a7713b1edbc 917 }
AnnaBridge 171:3a7713b1edbc 918
AnnaBridge 171:3a7713b1edbc 919 /**
AnnaBridge 171:3a7713b1edbc 920 * @brief Disable the encoder mode
AnnaBridge 171:3a7713b1edbc 921 * @note This function must be called when the LPTIM instance is disabled.
AnnaBridge 171:3a7713b1edbc 922 * @rmtoll CFGR ENC LL_LPTIM_DisableEncoderMode
AnnaBridge 171:3a7713b1edbc 923 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 924 * @retval None
AnnaBridge 171:3a7713b1edbc 925 */
AnnaBridge 171:3a7713b1edbc 926 __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 927 {
AnnaBridge 171:3a7713b1edbc 928 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
AnnaBridge 171:3a7713b1edbc 929 }
AnnaBridge 171:3a7713b1edbc 930
AnnaBridge 171:3a7713b1edbc 931 /**
AnnaBridge 171:3a7713b1edbc 932 * @brief Indicates whether the LPTIM operates in encoder mode.
AnnaBridge 171:3a7713b1edbc 933 * @rmtoll CFGR ENC LL_LPTIM_IsEnabledEncoderMode
AnnaBridge 171:3a7713b1edbc 934 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 935 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 936 */
AnnaBridge 171:3a7713b1edbc 937 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 938 {
AnnaBridge 171:3a7713b1edbc 939 return (READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == (LPTIM_CFGR_ENC));
AnnaBridge 171:3a7713b1edbc 940 }
AnnaBridge 171:3a7713b1edbc 941
AnnaBridge 171:3a7713b1edbc 942 /**
AnnaBridge 171:3a7713b1edbc 943 * @}
AnnaBridge 171:3a7713b1edbc 944 */
AnnaBridge 171:3a7713b1edbc 945
AnnaBridge 171:3a7713b1edbc 946 /** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
AnnaBridge 171:3a7713b1edbc 947 * @{
AnnaBridge 171:3a7713b1edbc 948 */
AnnaBridge 171:3a7713b1edbc 949
AnnaBridge 171:3a7713b1edbc 950 /**
AnnaBridge 171:3a7713b1edbc 951 * @brief Clear the compare match flag (CMPMCF)
AnnaBridge 171:3a7713b1edbc 952 * @rmtoll ICR CMPMCF LL_LPTIM_ClearFLAG_CMPM
AnnaBridge 171:3a7713b1edbc 953 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 954 * @retval None
AnnaBridge 171:3a7713b1edbc 955 */
AnnaBridge 171:3a7713b1edbc 956 __STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 957 {
AnnaBridge 171:3a7713b1edbc 958 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF);
AnnaBridge 171:3a7713b1edbc 959 }
AnnaBridge 171:3a7713b1edbc 960
AnnaBridge 171:3a7713b1edbc 961 /**
AnnaBridge 171:3a7713b1edbc 962 * @brief Inform application whether a compare match interrupt has occurred.
AnnaBridge 171:3a7713b1edbc 963 * @rmtoll ISR CMPM LL_LPTIM_IsActiveFlag_CMPM
AnnaBridge 171:3a7713b1edbc 964 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 965 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 966 */
AnnaBridge 171:3a7713b1edbc 967 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 968 {
AnnaBridge 171:3a7713b1edbc 969 return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == (LPTIM_ISR_CMPM));
AnnaBridge 171:3a7713b1edbc 970 }
AnnaBridge 171:3a7713b1edbc 971
AnnaBridge 171:3a7713b1edbc 972 /**
AnnaBridge 171:3a7713b1edbc 973 * @brief Clear the autoreload match flag (ARRMCF)
AnnaBridge 171:3a7713b1edbc 974 * @rmtoll ICR ARRMCF LL_LPTIM_ClearFLAG_ARRM
AnnaBridge 171:3a7713b1edbc 975 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 976 * @retval None
AnnaBridge 171:3a7713b1edbc 977 */
AnnaBridge 171:3a7713b1edbc 978 __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 979 {
AnnaBridge 171:3a7713b1edbc 980 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
AnnaBridge 171:3a7713b1edbc 981 }
AnnaBridge 171:3a7713b1edbc 982
AnnaBridge 171:3a7713b1edbc 983 /**
AnnaBridge 171:3a7713b1edbc 984 * @brief Inform application whether a autoreload match interrupt has occured.
AnnaBridge 171:3a7713b1edbc 985 * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
AnnaBridge 171:3a7713b1edbc 986 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 987 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 988 */
AnnaBridge 171:3a7713b1edbc 989 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 990 {
AnnaBridge 171:3a7713b1edbc 991 return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == (LPTIM_ISR_ARRM));
AnnaBridge 171:3a7713b1edbc 992 }
AnnaBridge 171:3a7713b1edbc 993
AnnaBridge 171:3a7713b1edbc 994 /**
AnnaBridge 171:3a7713b1edbc 995 * @brief Clear the external trigger valid edge flag(EXTTRIGCF).
AnnaBridge 171:3a7713b1edbc 996 * @rmtoll ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG
AnnaBridge 171:3a7713b1edbc 997 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 998 * @retval None
AnnaBridge 171:3a7713b1edbc 999 */
AnnaBridge 171:3a7713b1edbc 1000 __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 1001 {
AnnaBridge 171:3a7713b1edbc 1002 SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
AnnaBridge 171:3a7713b1edbc 1003 }
AnnaBridge 171:3a7713b1edbc 1004
AnnaBridge 171:3a7713b1edbc 1005 /**
AnnaBridge 171:3a7713b1edbc 1006 * @brief Inform application whether a valid edge on the selected external trigger input has occurred.
AnnaBridge 171:3a7713b1edbc 1007 * @rmtoll ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG
AnnaBridge 171:3a7713b1edbc 1008 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 1009 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1010 */
AnnaBridge 171:3a7713b1edbc 1011 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 1012 {
AnnaBridge 171:3a7713b1edbc 1013 return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == (LPTIM_ISR_EXTTRIG));
AnnaBridge 171:3a7713b1edbc 1014 }
AnnaBridge 171:3a7713b1edbc 1015
AnnaBridge 171:3a7713b1edbc 1016 /**
AnnaBridge 171:3a7713b1edbc 1017 * @brief Clear the compare register update interrupt flag (CMPOKCF).
AnnaBridge 171:3a7713b1edbc 1018 * @rmtoll ICR CMPOKCF LL_LPTIM_ClearFlag_CMPOK
AnnaBridge 171:3a7713b1edbc 1019 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 1020 * @retval None
AnnaBridge 171:3a7713b1edbc 1021 */
AnnaBridge 171:3a7713b1edbc 1022 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 1023 {
AnnaBridge 171:3a7713b1edbc 1024 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPOKCF);
AnnaBridge 171:3a7713b1edbc 1025 }
AnnaBridge 171:3a7713b1edbc 1026
AnnaBridge 171:3a7713b1edbc 1027 /**
AnnaBridge 171:3a7713b1edbc 1028 * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed; If so, a new one can be initiated.
AnnaBridge 171:3a7713b1edbc 1029 * @rmtoll ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK
AnnaBridge 171:3a7713b1edbc 1030 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 1031 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1032 */
AnnaBridge 171:3a7713b1edbc 1033 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 1034 {
AnnaBridge 171:3a7713b1edbc 1035 return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == (LPTIM_ISR_CMPOK));
AnnaBridge 171:3a7713b1edbc 1036 }
AnnaBridge 171:3a7713b1edbc 1037
AnnaBridge 171:3a7713b1edbc 1038 /**
AnnaBridge 171:3a7713b1edbc 1039 * @brief Clear the autoreload register update interrupt flag (ARROKCF).
AnnaBridge 171:3a7713b1edbc 1040 * @rmtoll ICR ARROKCF LL_LPTIM_ClearFlag_ARROK
AnnaBridge 171:3a7713b1edbc 1041 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 1042 * @retval None
AnnaBridge 171:3a7713b1edbc 1043 */
AnnaBridge 171:3a7713b1edbc 1044 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 1045 {
AnnaBridge 171:3a7713b1edbc 1046 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
AnnaBridge 171:3a7713b1edbc 1047 }
AnnaBridge 171:3a7713b1edbc 1048
AnnaBridge 171:3a7713b1edbc 1049 /**
AnnaBridge 171:3a7713b1edbc 1050 * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed; If so, a new one can be initiated.
AnnaBridge 171:3a7713b1edbc 1051 * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
AnnaBridge 171:3a7713b1edbc 1052 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 1053 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1054 */
AnnaBridge 171:3a7713b1edbc 1055 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 1056 {
AnnaBridge 171:3a7713b1edbc 1057 return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == (LPTIM_ISR_ARROK));
AnnaBridge 171:3a7713b1edbc 1058 }
AnnaBridge 171:3a7713b1edbc 1059
AnnaBridge 171:3a7713b1edbc 1060 /**
AnnaBridge 171:3a7713b1edbc 1061 * @brief Clear the counter direction change to up interrupt flag (UPCF).
AnnaBridge 171:3a7713b1edbc 1062 * @rmtoll ICR UPCF LL_LPTIM_ClearFlag_UP
AnnaBridge 171:3a7713b1edbc 1063 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 1064 * @retval None
AnnaBridge 171:3a7713b1edbc 1065 */
AnnaBridge 171:3a7713b1edbc 1066 __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 1067 {
AnnaBridge 171:3a7713b1edbc 1068 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
AnnaBridge 171:3a7713b1edbc 1069 }
AnnaBridge 171:3a7713b1edbc 1070
AnnaBridge 171:3a7713b1edbc 1071 /**
AnnaBridge 171:3a7713b1edbc 1072 * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).
AnnaBridge 171:3a7713b1edbc 1073 * @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP
AnnaBridge 171:3a7713b1edbc 1074 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 1075 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1076 */
AnnaBridge 171:3a7713b1edbc 1077 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 1078 {
AnnaBridge 171:3a7713b1edbc 1079 return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == (LPTIM_ISR_UP));
AnnaBridge 171:3a7713b1edbc 1080 }
AnnaBridge 171:3a7713b1edbc 1081
AnnaBridge 171:3a7713b1edbc 1082 /**
AnnaBridge 171:3a7713b1edbc 1083 * @brief Clear the counter direction change to down interrupt flag (DOWNCF).
AnnaBridge 171:3a7713b1edbc 1084 * @rmtoll ICR DOWNCF LL_LPTIM_ClearFlag_DOWN
AnnaBridge 171:3a7713b1edbc 1085 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 1086 * @retval None
AnnaBridge 171:3a7713b1edbc 1087 */
AnnaBridge 171:3a7713b1edbc 1088 __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 1089 {
AnnaBridge 171:3a7713b1edbc 1090 SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
AnnaBridge 171:3a7713b1edbc 1091 }
AnnaBridge 171:3a7713b1edbc 1092
AnnaBridge 171:3a7713b1edbc 1093 /**
AnnaBridge 171:3a7713b1edbc 1094 * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).
AnnaBridge 171:3a7713b1edbc 1095 * @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
AnnaBridge 171:3a7713b1edbc 1096 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 1097 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1098 */
AnnaBridge 171:3a7713b1edbc 1099 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 1100 {
AnnaBridge 171:3a7713b1edbc 1101 return (READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == (LPTIM_ISR_DOWN));
AnnaBridge 171:3a7713b1edbc 1102 }
AnnaBridge 171:3a7713b1edbc 1103
AnnaBridge 171:3a7713b1edbc 1104 /**
AnnaBridge 171:3a7713b1edbc 1105 * @}
AnnaBridge 171:3a7713b1edbc 1106 */
AnnaBridge 171:3a7713b1edbc 1107
AnnaBridge 171:3a7713b1edbc 1108 /** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
AnnaBridge 171:3a7713b1edbc 1109 * @{
AnnaBridge 171:3a7713b1edbc 1110 */
AnnaBridge 171:3a7713b1edbc 1111
AnnaBridge 171:3a7713b1edbc 1112 /**
AnnaBridge 171:3a7713b1edbc 1113 * @brief Enable compare match interrupt (CMPMIE).
AnnaBridge 171:3a7713b1edbc 1114 * @rmtoll IER CMPMIE LL_LPTIM_EnableIT_CMPM
AnnaBridge 171:3a7713b1edbc 1115 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 1116 * @retval None
AnnaBridge 171:3a7713b1edbc 1117 */
AnnaBridge 171:3a7713b1edbc 1118 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 1119 {
AnnaBridge 171:3a7713b1edbc 1120 SET_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
AnnaBridge 171:3a7713b1edbc 1121 }
AnnaBridge 171:3a7713b1edbc 1122
AnnaBridge 171:3a7713b1edbc 1123 /**
AnnaBridge 171:3a7713b1edbc 1124 * @brief Disable compare match interrupt (CMPMIE).
AnnaBridge 171:3a7713b1edbc 1125 * @rmtoll IER CMPMIE LL_LPTIM_DisableIT_CMPM
AnnaBridge 171:3a7713b1edbc 1126 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 1127 * @retval None
AnnaBridge 171:3a7713b1edbc 1128 */
AnnaBridge 171:3a7713b1edbc 1129 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 1130 {
AnnaBridge 171:3a7713b1edbc 1131 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
AnnaBridge 171:3a7713b1edbc 1132 }
AnnaBridge 171:3a7713b1edbc 1133
AnnaBridge 171:3a7713b1edbc 1134 /**
AnnaBridge 171:3a7713b1edbc 1135 * @brief Indicates whether the compare match interrupt (CMPMIE) is enabled.
AnnaBridge 171:3a7713b1edbc 1136 * @rmtoll IER CMPMIE LL_LPTIM_IsEnabledIT_CMPM
AnnaBridge 171:3a7713b1edbc 1137 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 1138 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1139 */
AnnaBridge 171:3a7713b1edbc 1140 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 1141 {
AnnaBridge 171:3a7713b1edbc 1142 return (READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == (LPTIM_IER_CMPMIE));
AnnaBridge 171:3a7713b1edbc 1143 }
AnnaBridge 171:3a7713b1edbc 1144
AnnaBridge 171:3a7713b1edbc 1145 /**
AnnaBridge 171:3a7713b1edbc 1146 * @brief Enable autoreload match interrupt (ARRMIE).
AnnaBridge 171:3a7713b1edbc 1147 * @rmtoll IER ARRMIE LL_LPTIM_EnableIT_ARRM
AnnaBridge 171:3a7713b1edbc 1148 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 1149 * @retval None
AnnaBridge 171:3a7713b1edbc 1150 */
AnnaBridge 171:3a7713b1edbc 1151 __STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 1152 {
AnnaBridge 171:3a7713b1edbc 1153 SET_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
AnnaBridge 171:3a7713b1edbc 1154 }
AnnaBridge 171:3a7713b1edbc 1155
AnnaBridge 171:3a7713b1edbc 1156 /**
AnnaBridge 171:3a7713b1edbc 1157 * @brief Disable autoreload match interrupt (ARRMIE).
AnnaBridge 171:3a7713b1edbc 1158 * @rmtoll IER ARRMIE LL_LPTIM_DisableIT_ARRM
AnnaBridge 171:3a7713b1edbc 1159 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 1160 * @retval None
AnnaBridge 171:3a7713b1edbc 1161 */
AnnaBridge 171:3a7713b1edbc 1162 __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 1163 {
AnnaBridge 171:3a7713b1edbc 1164 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
AnnaBridge 171:3a7713b1edbc 1165 }
AnnaBridge 171:3a7713b1edbc 1166
AnnaBridge 171:3a7713b1edbc 1167 /**
AnnaBridge 171:3a7713b1edbc 1168 * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
AnnaBridge 171:3a7713b1edbc 1169 * @rmtoll IER ARRMIE LL_LPTIM_IsEnabledIT_ARRM
AnnaBridge 171:3a7713b1edbc 1170 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 1171 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1172 */
AnnaBridge 171:3a7713b1edbc 1173 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 1174 {
AnnaBridge 171:3a7713b1edbc 1175 return (READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == (LPTIM_IER_ARRMIE));
AnnaBridge 171:3a7713b1edbc 1176 }
AnnaBridge 171:3a7713b1edbc 1177
AnnaBridge 171:3a7713b1edbc 1178 /**
AnnaBridge 171:3a7713b1edbc 1179 * @brief Enable external trigger valid edge interrupt (EXTTRIGIE).
AnnaBridge 171:3a7713b1edbc 1180 * @rmtoll IER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG
AnnaBridge 171:3a7713b1edbc 1181 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 1182 * @retval None
AnnaBridge 171:3a7713b1edbc 1183 */
AnnaBridge 171:3a7713b1edbc 1184 __STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 1185 {
AnnaBridge 171:3a7713b1edbc 1186 SET_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
AnnaBridge 171:3a7713b1edbc 1187 }
AnnaBridge 171:3a7713b1edbc 1188
AnnaBridge 171:3a7713b1edbc 1189 /**
AnnaBridge 171:3a7713b1edbc 1190 * @brief Disable external trigger valid edge interrupt (EXTTRIGIE).
AnnaBridge 171:3a7713b1edbc 1191 * @rmtoll IER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG
AnnaBridge 171:3a7713b1edbc 1192 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 1193 * @retval None
AnnaBridge 171:3a7713b1edbc 1194 */
AnnaBridge 171:3a7713b1edbc 1195 __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 1196 {
AnnaBridge 171:3a7713b1edbc 1197 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
AnnaBridge 171:3a7713b1edbc 1198 }
AnnaBridge 171:3a7713b1edbc 1199
AnnaBridge 171:3a7713b1edbc 1200 /**
AnnaBridge 171:3a7713b1edbc 1201 * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
AnnaBridge 171:3a7713b1edbc 1202 * @rmtoll IER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG
AnnaBridge 171:3a7713b1edbc 1203 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 1204 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1205 */
AnnaBridge 171:3a7713b1edbc 1206 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 1207 {
AnnaBridge 171:3a7713b1edbc 1208 return (READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == (LPTIM_IER_EXTTRIGIE));
AnnaBridge 171:3a7713b1edbc 1209 }
AnnaBridge 171:3a7713b1edbc 1210
AnnaBridge 171:3a7713b1edbc 1211 /**
AnnaBridge 171:3a7713b1edbc 1212 * @brief Enable compare register write completed interrupt (CMPOKIE).
AnnaBridge 171:3a7713b1edbc 1213 * @rmtoll IER CMPOKIE LL_LPTIM_EnableIT_CMPOK
AnnaBridge 171:3a7713b1edbc 1214 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 1215 * @retval None
AnnaBridge 171:3a7713b1edbc 1216 */
AnnaBridge 171:3a7713b1edbc 1217 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 1218 {
AnnaBridge 171:3a7713b1edbc 1219 SET_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
AnnaBridge 171:3a7713b1edbc 1220 }
AnnaBridge 171:3a7713b1edbc 1221
AnnaBridge 171:3a7713b1edbc 1222 /**
AnnaBridge 171:3a7713b1edbc 1223 * @brief Disable compare register write completed interrupt (CMPOKIE).
AnnaBridge 171:3a7713b1edbc 1224 * @rmtoll IER CMPOKIE LL_LPTIM_DisableIT_CMPOK
AnnaBridge 171:3a7713b1edbc 1225 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 1226 * @retval None
AnnaBridge 171:3a7713b1edbc 1227 */
AnnaBridge 171:3a7713b1edbc 1228 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 1229 {
AnnaBridge 171:3a7713b1edbc 1230 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
AnnaBridge 171:3a7713b1edbc 1231 }
AnnaBridge 171:3a7713b1edbc 1232
AnnaBridge 171:3a7713b1edbc 1233 /**
AnnaBridge 171:3a7713b1edbc 1234 * @brief Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
AnnaBridge 171:3a7713b1edbc 1235 * @rmtoll IER CMPOKIE LL_LPTIM_IsEnabledIT_CMPOK
AnnaBridge 171:3a7713b1edbc 1236 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 1237 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1238 */
AnnaBridge 171:3a7713b1edbc 1239 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 1240 {
AnnaBridge 171:3a7713b1edbc 1241 return (READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == (LPTIM_IER_CMPOKIE));
AnnaBridge 171:3a7713b1edbc 1242 }
AnnaBridge 171:3a7713b1edbc 1243
AnnaBridge 171:3a7713b1edbc 1244 /**
AnnaBridge 171:3a7713b1edbc 1245 * @brief Enable autoreload register write completed interrupt (ARROKIE).
AnnaBridge 171:3a7713b1edbc 1246 * @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK
AnnaBridge 171:3a7713b1edbc 1247 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 1248 * @retval None
AnnaBridge 171:3a7713b1edbc 1249 */
AnnaBridge 171:3a7713b1edbc 1250 __STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 1251 {
AnnaBridge 171:3a7713b1edbc 1252 SET_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
AnnaBridge 171:3a7713b1edbc 1253 }
AnnaBridge 171:3a7713b1edbc 1254
AnnaBridge 171:3a7713b1edbc 1255 /**
AnnaBridge 171:3a7713b1edbc 1256 * @brief Disable autoreload register write completed interrupt (ARROKIE).
AnnaBridge 171:3a7713b1edbc 1257 * @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK
AnnaBridge 171:3a7713b1edbc 1258 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 1259 * @retval None
AnnaBridge 171:3a7713b1edbc 1260 */
AnnaBridge 171:3a7713b1edbc 1261 __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 1262 {
AnnaBridge 171:3a7713b1edbc 1263 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
AnnaBridge 171:3a7713b1edbc 1264 }
AnnaBridge 171:3a7713b1edbc 1265
AnnaBridge 171:3a7713b1edbc 1266 /**
AnnaBridge 171:3a7713b1edbc 1267 * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
AnnaBridge 171:3a7713b1edbc 1268 * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
AnnaBridge 171:3a7713b1edbc 1269 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 1270 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1271 */
AnnaBridge 171:3a7713b1edbc 1272 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 1273 {
AnnaBridge 171:3a7713b1edbc 1274 return (READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == (LPTIM_IER_ARROKIE));
AnnaBridge 171:3a7713b1edbc 1275 }
AnnaBridge 171:3a7713b1edbc 1276
AnnaBridge 171:3a7713b1edbc 1277 /**
AnnaBridge 171:3a7713b1edbc 1278 * @brief Enable direction change to up interrupt (UPIE).
AnnaBridge 171:3a7713b1edbc 1279 * @rmtoll IER UPIE LL_LPTIM_EnableIT_UP
AnnaBridge 171:3a7713b1edbc 1280 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 1281 * @retval None
AnnaBridge 171:3a7713b1edbc 1282 */
AnnaBridge 171:3a7713b1edbc 1283 __STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 1284 {
AnnaBridge 171:3a7713b1edbc 1285 SET_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
AnnaBridge 171:3a7713b1edbc 1286 }
AnnaBridge 171:3a7713b1edbc 1287
AnnaBridge 171:3a7713b1edbc 1288 /**
AnnaBridge 171:3a7713b1edbc 1289 * @brief Disable direction change to up interrupt (UPIE).
AnnaBridge 171:3a7713b1edbc 1290 * @rmtoll IER UPIE LL_LPTIM_DisableIT_UP
AnnaBridge 171:3a7713b1edbc 1291 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 1292 * @retval None
AnnaBridge 171:3a7713b1edbc 1293 */
AnnaBridge 171:3a7713b1edbc 1294 __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 1295 {
AnnaBridge 171:3a7713b1edbc 1296 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
AnnaBridge 171:3a7713b1edbc 1297 }
AnnaBridge 171:3a7713b1edbc 1298
AnnaBridge 171:3a7713b1edbc 1299 /**
AnnaBridge 171:3a7713b1edbc 1300 * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
AnnaBridge 171:3a7713b1edbc 1301 * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
AnnaBridge 171:3a7713b1edbc 1302 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 1303 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1304 */
AnnaBridge 171:3a7713b1edbc 1305 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 1306 {
AnnaBridge 171:3a7713b1edbc 1307 return (READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == (LPTIM_IER_UPIE));
AnnaBridge 171:3a7713b1edbc 1308 }
AnnaBridge 171:3a7713b1edbc 1309
AnnaBridge 171:3a7713b1edbc 1310 /**
AnnaBridge 171:3a7713b1edbc 1311 * @brief Enable direction change to down interrupt (DOWNIE).
AnnaBridge 171:3a7713b1edbc 1312 * @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN
AnnaBridge 171:3a7713b1edbc 1313 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 1314 * @retval None
AnnaBridge 171:3a7713b1edbc 1315 */
AnnaBridge 171:3a7713b1edbc 1316 __STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 1317 {
AnnaBridge 171:3a7713b1edbc 1318 SET_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
AnnaBridge 171:3a7713b1edbc 1319 }
AnnaBridge 171:3a7713b1edbc 1320
AnnaBridge 171:3a7713b1edbc 1321 /**
AnnaBridge 171:3a7713b1edbc 1322 * @brief Disable direction change to down interrupt (DOWNIE).
AnnaBridge 171:3a7713b1edbc 1323 * @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN
AnnaBridge 171:3a7713b1edbc 1324 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 1325 * @retval None
AnnaBridge 171:3a7713b1edbc 1326 */
AnnaBridge 171:3a7713b1edbc 1327 __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 1328 {
AnnaBridge 171:3a7713b1edbc 1329 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
AnnaBridge 171:3a7713b1edbc 1330 }
AnnaBridge 171:3a7713b1edbc 1331
AnnaBridge 171:3a7713b1edbc 1332 /**
AnnaBridge 171:3a7713b1edbc 1333 * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
AnnaBridge 171:3a7713b1edbc 1334 * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
AnnaBridge 171:3a7713b1edbc 1335 * @param LPTIMx Low-Power Timer instance
AnnaBridge 171:3a7713b1edbc 1336 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1337 */
AnnaBridge 171:3a7713b1edbc 1338 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)
AnnaBridge 171:3a7713b1edbc 1339 {
AnnaBridge 171:3a7713b1edbc 1340 return (READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == (LPTIM_IER_DOWNIE));
AnnaBridge 171:3a7713b1edbc 1341 }
AnnaBridge 171:3a7713b1edbc 1342
AnnaBridge 171:3a7713b1edbc 1343 /**
AnnaBridge 171:3a7713b1edbc 1344 * @}
AnnaBridge 171:3a7713b1edbc 1345 */
AnnaBridge 171:3a7713b1edbc 1346
AnnaBridge 171:3a7713b1edbc 1347 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 171:3a7713b1edbc 1348 /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
AnnaBridge 171:3a7713b1edbc 1349 * @{
AnnaBridge 171:3a7713b1edbc 1350 */
AnnaBridge 171:3a7713b1edbc 1351
AnnaBridge 171:3a7713b1edbc 1352 ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
AnnaBridge 171:3a7713b1edbc 1353 void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
AnnaBridge 171:3a7713b1edbc 1354 ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
AnnaBridge 171:3a7713b1edbc 1355 /**
AnnaBridge 171:3a7713b1edbc 1356 * @}
AnnaBridge 171:3a7713b1edbc 1357 */
AnnaBridge 171:3a7713b1edbc 1358 #endif /* USE_FULL_LL_DRIVER */
AnnaBridge 171:3a7713b1edbc 1359
AnnaBridge 171:3a7713b1edbc 1360 /**
AnnaBridge 171:3a7713b1edbc 1361 * @}
AnnaBridge 171:3a7713b1edbc 1362 */
AnnaBridge 171:3a7713b1edbc 1363
AnnaBridge 171:3a7713b1edbc 1364 /**
AnnaBridge 171:3a7713b1edbc 1365 * @}
AnnaBridge 171:3a7713b1edbc 1366 */
AnnaBridge 171:3a7713b1edbc 1367
AnnaBridge 171:3a7713b1edbc 1368 #endif /* LPTIM1 */
AnnaBridge 171:3a7713b1edbc 1369
AnnaBridge 171:3a7713b1edbc 1370 /**
AnnaBridge 171:3a7713b1edbc 1371 * @}
AnnaBridge 171:3a7713b1edbc 1372 */
AnnaBridge 171:3a7713b1edbc 1373
AnnaBridge 171:3a7713b1edbc 1374 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 1375 }
AnnaBridge 171:3a7713b1edbc 1376 #endif
AnnaBridge 171:3a7713b1edbc 1377
AnnaBridge 171:3a7713b1edbc 1378 #endif /* __STM32F7xx_LL_LPTIM_H */
AnnaBridge 171:3a7713b1edbc 1379
AnnaBridge 171:3a7713b1edbc 1380 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/