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TARGET_NUCLEO_F207ZG/TOOLCHAIN_GCC_ARM/stm32f2xx_ll_rcc.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	145:64910690c574	1	/**
AnnaBridge	145:64910690c574	2	******************************************************************************
AnnaBridge	145:64910690c574	3	* @file stm32f2xx_ll_rcc.h
AnnaBridge	145:64910690c574	4	* @author MCD Application Team
AnnaBridge	145:64910690c574	5	* @version V1.2.1
AnnaBridge	145:64910690c574	6	* @date 14-April-2017
AnnaBridge	145:64910690c574	7	* @brief Header file of RCC LL module.
AnnaBridge	145:64910690c574	8	******************************************************************************
AnnaBridge	145:64910690c574	9	* @attention
AnnaBridge	145:64910690c574	10	*
AnnaBridge	145:64910690c574	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	145:64910690c574	12	*
AnnaBridge	145:64910690c574	13	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	145:64910690c574	14	* are permitted provided that the following conditions are met:
AnnaBridge	145:64910690c574	15	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	145:64910690c574	16	* this list of conditions and the following disclaimer.
AnnaBridge	145:64910690c574	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	145:64910690c574	18	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	145:64910690c574	19	* and/or other materials provided with the distribution.
AnnaBridge	145:64910690c574	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	145:64910690c574	21	* may be used to endorse or promote products derived from this software
AnnaBridge	145:64910690c574	22	* without specific prior written permission.
AnnaBridge	145:64910690c574	23	*
AnnaBridge	145:64910690c574	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	145:64910690c574	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	145:64910690c574	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	145:64910690c574	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	145:64910690c574	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	145:64910690c574	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	145:64910690c574	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	145:64910690c574	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	145:64910690c574	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	145:64910690c574	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	145:64910690c574	34	*
AnnaBridge	145:64910690c574	35	******************************************************************************
AnnaBridge	145:64910690c574	36	*/
AnnaBridge	145:64910690c574	37
AnnaBridge	145:64910690c574	38	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	145:64910690c574	39	#ifndef __STM32F2xx_LL_RCC_H
AnnaBridge	145:64910690c574	40	#define __STM32F2xx_LL_RCC_H
AnnaBridge	145:64910690c574	41
AnnaBridge	145:64910690c574	42	#ifdef __cplusplus
AnnaBridge	145:64910690c574	43	extern "C" {
AnnaBridge	145:64910690c574	44	#endif
AnnaBridge	145:64910690c574	45
AnnaBridge	145:64910690c574	46	/* Includes ------------------------------------------------------------------*/
AnnaBridge	145:64910690c574	47	#include "stm32f2xx.h"
AnnaBridge	145:64910690c574	48
AnnaBridge	145:64910690c574	49	/** @addtogroup STM32F2xx_LL_Driver
AnnaBridge	145:64910690c574	50	* @{
AnnaBridge	145:64910690c574	51	*/
AnnaBridge	145:64910690c574	52
AnnaBridge	145:64910690c574	53	#if defined(RCC)
AnnaBridge	145:64910690c574	54
AnnaBridge	145:64910690c574	55	/** @defgroup RCC_LL RCC
AnnaBridge	145:64910690c574	56	* @{
AnnaBridge	145:64910690c574	57	*/
AnnaBridge	145:64910690c574	58
AnnaBridge	145:64910690c574	59	/* Private types -------------------------------------------------------------*/
AnnaBridge	145:64910690c574	60	/* Private variables ---------------------------------------------------------*/
AnnaBridge	145:64910690c574	61	/** @defgroup RCC_LL_Private_Variables RCC Private Variables
AnnaBridge	145:64910690c574	62	* @{
AnnaBridge	145:64910690c574	63	*/
AnnaBridge	145:64910690c574	64
AnnaBridge	145:64910690c574	65	/**
AnnaBridge	145:64910690c574	66	* @}
AnnaBridge	145:64910690c574	67	*/
AnnaBridge	145:64910690c574	68	/* Private constants ---------------------------------------------------------*/
AnnaBridge	145:64910690c574	69	/* Private macros ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	70	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	145:64910690c574	71	/** @defgroup RCC_LL_Private_Macros RCC Private Macros
AnnaBridge	145:64910690c574	72	* @{
AnnaBridge	145:64910690c574	73	*/
AnnaBridge	145:64910690c574	74	/**
AnnaBridge	145:64910690c574	75	* @}
AnnaBridge	145:64910690c574	76	*/
AnnaBridge	145:64910690c574	77	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	145:64910690c574	78
AnnaBridge	145:64910690c574	79	/* Exported types ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	80	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	145:64910690c574	81	/** @defgroup RCC_LL_Exported_Types RCC Exported Types
AnnaBridge	145:64910690c574	82	* @{
AnnaBridge	145:64910690c574	83	*/
AnnaBridge	145:64910690c574	84
AnnaBridge	145:64910690c574	85	/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
AnnaBridge	145:64910690c574	86	* @{
AnnaBridge	145:64910690c574	87	*/
AnnaBridge	145:64910690c574	88
AnnaBridge	145:64910690c574	89	/**
AnnaBridge	145:64910690c574	90	* @brief RCC Clocks Frequency Structure
AnnaBridge	145:64910690c574	91	*/
AnnaBridge	145:64910690c574	92	typedef struct
AnnaBridge	145:64910690c574	93	{
AnnaBridge	145:64910690c574	94	uint32_t SYSCLK_Frequency; /!< SYSCLK clock frequency /
AnnaBridge	145:64910690c574	95	uint32_t HCLK_Frequency; /!< HCLK clock frequency /
AnnaBridge	145:64910690c574	96	uint32_t PCLK1_Frequency; /!< PCLK1 clock frequency /
AnnaBridge	145:64910690c574	97	uint32_t PCLK2_Frequency; /!< PCLK2 clock frequency /
AnnaBridge	145:64910690c574	98	} LL_RCC_ClocksTypeDef;
AnnaBridge	145:64910690c574	99
AnnaBridge	145:64910690c574	100	/**
AnnaBridge	145:64910690c574	101	* @}
AnnaBridge	145:64910690c574	102	*/
AnnaBridge	145:64910690c574	103
AnnaBridge	145:64910690c574	104	/**
AnnaBridge	145:64910690c574	105	* @}
AnnaBridge	145:64910690c574	106	*/
AnnaBridge	145:64910690c574	107	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	145:64910690c574	108
AnnaBridge	145:64910690c574	109	/* Exported constants --------------------------------------------------------*/
AnnaBridge	145:64910690c574	110	/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
AnnaBridge	145:64910690c574	111	* @{
AnnaBridge	145:64910690c574	112	*/
AnnaBridge	145:64910690c574	113
AnnaBridge	145:64910690c574	114	/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
AnnaBridge	145:64910690c574	115	* @brief Defines used to adapt values of different oscillators
AnnaBridge	145:64910690c574	116	* @note These values could be modified in the user environment according to
AnnaBridge	145:64910690c574	117	* HW set-up.
AnnaBridge	145:64910690c574	118	* @{
AnnaBridge	145:64910690c574	119	*/
AnnaBridge	145:64910690c574	120	#if !defined (HSE_VALUE)
AnnaBridge	145:64910690c574	121	#define HSE_VALUE 25000000U /!< Value of the HSE oscillator in Hz /
AnnaBridge	145:64910690c574	122	#endif /* HSE_VALUE */
AnnaBridge	145:64910690c574	123
AnnaBridge	145:64910690c574	124	#if !defined (HSI_VALUE)
AnnaBridge	145:64910690c574	125	#define HSI_VALUE 16000000U /!< Value of the HSI oscillator in Hz /
AnnaBridge	145:64910690c574	126	#endif /* HSI_VALUE */
AnnaBridge	145:64910690c574	127
AnnaBridge	145:64910690c574	128	#if !defined (LSE_VALUE)
AnnaBridge	145:64910690c574	129	#define LSE_VALUE 32768U /!< Value of the LSE oscillator in Hz /
AnnaBridge	145:64910690c574	130	#endif /* LSE_VALUE */
AnnaBridge	145:64910690c574	131
AnnaBridge	145:64910690c574	132	#if !defined (LSI_VALUE)
AnnaBridge	145:64910690c574	133	#define LSI_VALUE 32000U /!< Value of the LSI oscillator in Hz /
AnnaBridge	145:64910690c574	134	#endif /* LSI_VALUE */
AnnaBridge	145:64910690c574	135
AnnaBridge	145:64910690c574	136	#if !defined (EXTERNAL_CLOCK_VALUE)
AnnaBridge	145:64910690c574	137	#define EXTERNAL_CLOCK_VALUE 12288000U /!< Value of the I2S_CKIN external oscillator in Hz /
AnnaBridge	145:64910690c574	138	#endif /* EXTERNAL_CLOCK_VALUE */
AnnaBridge	145:64910690c574	139	/**
AnnaBridge	145:64910690c574	140	* @}
AnnaBridge	145:64910690c574	141	*/
AnnaBridge	145:64910690c574	142
AnnaBridge	145:64910690c574	143	/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
AnnaBridge	145:64910690c574	144	* @brief Flags defines which can be used with LL_RCC_WriteReg function
AnnaBridge	145:64910690c574	145	* @{
AnnaBridge	145:64910690c574	146	*/
AnnaBridge	145:64910690c574	147	#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /!< LSI Ready Interrupt Clear /
AnnaBridge	145:64910690c574	148	#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /!< LSE Ready Interrupt Clear /
AnnaBridge	145:64910690c574	149	#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /!< HSI Ready Interrupt Clear /
AnnaBridge	145:64910690c574	150	#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /!< HSE Ready Interrupt Clear /
AnnaBridge	145:64910690c574	151	#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /!< PLL Ready Interrupt Clear /
AnnaBridge	145:64910690c574	152	#define LL_RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC /!< PLLI2S Ready Interrupt Clear /
AnnaBridge	145:64910690c574	153	#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /!< Clock Security System Interrupt Clear /
AnnaBridge	145:64910690c574	154	/**
AnnaBridge	145:64910690c574	155	* @}
AnnaBridge	145:64910690c574	156	*/
AnnaBridge	145:64910690c574	157
AnnaBridge	145:64910690c574	158	/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	145:64910690c574	159	* @brief Flags defines which can be used with LL_RCC_ReadReg function
AnnaBridge	145:64910690c574	160	* @{
AnnaBridge	145:64910690c574	161	*/
AnnaBridge	145:64910690c574	162	#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /!< LSI Ready Interrupt flag /
AnnaBridge	145:64910690c574	163	#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /!< LSE Ready Interrupt flag /
AnnaBridge	145:64910690c574	164	#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /!< HSI Ready Interrupt flag /
AnnaBridge	145:64910690c574	165	#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /!< HSE Ready Interrupt flag /
AnnaBridge	145:64910690c574	166	#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /!< PLL Ready Interrupt flag /
AnnaBridge	145:64910690c574	167	#define LL_RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF /!< PLLI2S Ready Interrupt flag /
AnnaBridge	145:64910690c574	168	#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /!< Clock Security System Interrupt flag /
AnnaBridge	145:64910690c574	169	#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /!< Low-Power reset flag /
AnnaBridge	145:64910690c574	170	#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /!< PIN reset flag /
AnnaBridge	145:64910690c574	171	#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /!< POR/PDR reset flag /
AnnaBridge	145:64910690c574	172	#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /!< Software Reset flag /
AnnaBridge	145:64910690c574	173	#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /!< Independent Watchdog reset flag /
AnnaBridge	145:64910690c574	174	#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /!< Window watchdog reset flag /
AnnaBridge	145:64910690c574	175	#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /!< BOR reset flag /
AnnaBridge	145:64910690c574	176	/**
AnnaBridge	145:64910690c574	177	* @}
AnnaBridge	145:64910690c574	178	*/
AnnaBridge	145:64910690c574	179
AnnaBridge	145:64910690c574	180	/** @defgroup RCC_LL_EC_IT IT Defines
AnnaBridge	145:64910690c574	181	* @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
AnnaBridge	145:64910690c574	182	* @{
AnnaBridge	145:64910690c574	183	*/
AnnaBridge	145:64910690c574	184	#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /!< LSI Ready Interrupt Enable /
AnnaBridge	145:64910690c574	185	#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /!< LSE Ready Interrupt Enable /
AnnaBridge	145:64910690c574	186	#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /!< HSI Ready Interrupt Enable /
AnnaBridge	145:64910690c574	187	#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /!< HSE Ready Interrupt Enable /
AnnaBridge	145:64910690c574	188	#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /!< PLL Ready Interrupt Enable /
AnnaBridge	145:64910690c574	189	#define LL_RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE /!< PLLI2S Ready Interrupt Enable /
AnnaBridge	145:64910690c574	190	/**
AnnaBridge	145:64910690c574	191	* @}
AnnaBridge	145:64910690c574	192	*/
AnnaBridge	145:64910690c574	193
AnnaBridge	145:64910690c574	194	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
AnnaBridge	145:64910690c574	195	* @{
AnnaBridge	145:64910690c574	196	*/
AnnaBridge	145:64910690c574	197	#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selection as system clock /
AnnaBridge	145:64910690c574	198	#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selection as system clock /
AnnaBridge	145:64910690c574	199	#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /!< PLL selection as system clock /
AnnaBridge	145:64910690c574	200	/**
AnnaBridge	145:64910690c574	201	* @}
AnnaBridge	145:64910690c574	202	*/
AnnaBridge	145:64910690c574	203
AnnaBridge	145:64910690c574	204	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
AnnaBridge	145:64910690c574	205	* @{
AnnaBridge	145:64910690c574	206	*/
AnnaBridge	145:64910690c574	207	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
AnnaBridge	145:64910690c574	208	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
AnnaBridge	145:64910690c574	209	#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /!< PLL used as system clock /
AnnaBridge	145:64910690c574	210	/**
AnnaBridge	145:64910690c574	211	* @}
AnnaBridge	145:64910690c574	212	*/
AnnaBridge	145:64910690c574	213
AnnaBridge	145:64910690c574	214	/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
AnnaBridge	145:64910690c574	215	* @{
AnnaBridge	145:64910690c574	216	*/
AnnaBridge	145:64910690c574	217	#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
AnnaBridge	145:64910690c574	218	#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
AnnaBridge	145:64910690c574	219	#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
AnnaBridge	145:64910690c574	220	#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
AnnaBridge	145:64910690c574	221	#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
AnnaBridge	145:64910690c574	222	#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
AnnaBridge	145:64910690c574	223	#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
AnnaBridge	145:64910690c574	224	#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
AnnaBridge	145:64910690c574	225	#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
AnnaBridge	145:64910690c574	226	/**
AnnaBridge	145:64910690c574	227	* @}
AnnaBridge	145:64910690c574	228	*/
AnnaBridge	145:64910690c574	229
AnnaBridge	145:64910690c574	230	/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
AnnaBridge	145:64910690c574	231	* @{
AnnaBridge	145:64910690c574	232	*/
AnnaBridge	145:64910690c574	233	#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
AnnaBridge	145:64910690c574	234	#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
AnnaBridge	145:64910690c574	235	#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
AnnaBridge	145:64910690c574	236	#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
AnnaBridge	145:64910690c574	237	#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
AnnaBridge	145:64910690c574	238	/**
AnnaBridge	145:64910690c574	239	* @}
AnnaBridge	145:64910690c574	240	*/
AnnaBridge	145:64910690c574	241
AnnaBridge	145:64910690c574	242	/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
AnnaBridge	145:64910690c574	243	* @{
AnnaBridge	145:64910690c574	244	*/
AnnaBridge	145:64910690c574	245	#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /!< HCLK not divided /
AnnaBridge	145:64910690c574	246	#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /!< HCLK divided by 2 /
AnnaBridge	145:64910690c574	247	#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /!< HCLK divided by 4 /
AnnaBridge	145:64910690c574	248	#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /!< HCLK divided by 8 /
AnnaBridge	145:64910690c574	249	#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /!< HCLK divided by 16 /
AnnaBridge	145:64910690c574	250	/**
AnnaBridge	145:64910690c574	251	* @}
AnnaBridge	145:64910690c574	252	*/
AnnaBridge	145:64910690c574	253
AnnaBridge	145:64910690c574	254	/** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection
AnnaBridge	145:64910690c574	255	* @{
AnnaBridge	145:64910690c574	256	*/
AnnaBridge	145:64910690c574	257	#define LL_RCC_MCO1SOURCE_HSI (uint32_t)(RCC_CFGR_MCO1\|0x00000000U) /!< HSI selection as MCO1 source /
AnnaBridge	145:64910690c574	258	#define LL_RCC_MCO1SOURCE_LSE (uint32_t)(RCC_CFGR_MCO1\|(RCC_CFGR_MCO1_0 >> 16U)) /!< LSE selection as MCO1 source /
AnnaBridge	145:64910690c574	259	#define LL_RCC_MCO1SOURCE_HSE (uint32_t)(RCC_CFGR_MCO1\|(RCC_CFGR_MCO1_1 >> 16U)) /!< HSE selection as MCO1 source /
AnnaBridge	145:64910690c574	260	#define LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO1\|((RCC_CFGR_MCO1_1\|RCC_CFGR_MCO1_0) >> 16U)) /!< PLLCLK selection as MCO1 source /
AnnaBridge	145:64910690c574	261	#define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)(RCC_CFGR_MCO2\|0x00000000U) /!< SYSCLK selection as MCO2 source /
AnnaBridge	145:64910690c574	262	#define LL_RCC_MCO2SOURCE_PLLI2S (uint32_t)(RCC_CFGR_MCO2\|(RCC_CFGR_MCO2_0 >> 16U)) /!< PLLI2S selection as MCO2 source /
AnnaBridge	145:64910690c574	263	#define LL_RCC_MCO2SOURCE_HSE (uint32_t)(RCC_CFGR_MCO2\|(RCC_CFGR_MCO2_1 >> 16U)) /!< HSE selection as MCO2 source /
AnnaBridge	145:64910690c574	264	#define LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO2\|((RCC_CFGR_MCO2_1\|RCC_CFGR_MCO2_0) >> 16U)) /!< PLLCLK selection as MCO2 source /
AnnaBridge	145:64910690c574	265	/**
AnnaBridge	145:64910690c574	266	* @}
AnnaBridge	145:64910690c574	267	*/
AnnaBridge	145:64910690c574	268
AnnaBridge	145:64910690c574	269	/** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler
AnnaBridge	145:64910690c574	270	* @{
AnnaBridge	145:64910690c574	271	*/
AnnaBridge	145:64910690c574	272	#define LL_RCC_MCO1_DIV_1 (uint32_t)(RCC_CFGR_MCO1PRE\|0x00000000U) /!< MCO1 not divided /
AnnaBridge	145:64910690c574	273	#define LL_RCC_MCO1_DIV_2 (uint32_t)(RCC_CFGR_MCO1PRE\|(RCC_CFGR_MCO1PRE_2 >> 16U)) /!< MCO1 divided by 2 /
AnnaBridge	145:64910690c574	274	#define LL_RCC_MCO1_DIV_3 (uint32_t)(RCC_CFGR_MCO1PRE\|((RCC_CFGR_MCO1PRE_2\|RCC_CFGR_MCO1PRE_0) >> 16U)) /!< MCO1 divided by 3 /
AnnaBridge	145:64910690c574	275	#define LL_RCC_MCO1_DIV_4 (uint32_t)(RCC_CFGR_MCO1PRE\|((RCC_CFGR_MCO1PRE_2\|RCC_CFGR_MCO1PRE_1) >> 16U)) /!< MCO1 divided by 4 /
AnnaBridge	145:64910690c574	276	#define LL_RCC_MCO1_DIV_5 (uint32_t)(RCC_CFGR_MCO1PRE\|(RCC_CFGR_MCO1PRE >> 16U)) /!< MCO1 divided by 5 /
AnnaBridge	145:64910690c574	277	#define LL_RCC_MCO2_DIV_1 (uint32_t)(RCC_CFGR_MCO2PRE\|0x00000000U) /!< MCO2 not divided /
AnnaBridge	145:64910690c574	278	#define LL_RCC_MCO2_DIV_2 (uint32_t)(RCC_CFGR_MCO2PRE\|(RCC_CFGR_MCO2PRE_2 >> 16U)) /!< MCO2 divided by 2 /
AnnaBridge	145:64910690c574	279	#define LL_RCC_MCO2_DIV_3 (uint32_t)(RCC_CFGR_MCO2PRE\|((RCC_CFGR_MCO2PRE_2\|RCC_CFGR_MCO2PRE_0) >> 16U)) /!< MCO2 divided by 3 /
AnnaBridge	145:64910690c574	280	#define LL_RCC_MCO2_DIV_4 (uint32_t)(RCC_CFGR_MCO2PRE\|((RCC_CFGR_MCO2PRE_2\|RCC_CFGR_MCO2PRE_1) >> 16U)) /!< MCO2 divided by 4 /
AnnaBridge	145:64910690c574	281	#define LL_RCC_MCO2_DIV_5 (uint32_t)(RCC_CFGR_MCO2PRE\|(RCC_CFGR_MCO2PRE >> 16U)) /!< MCO2 divided by 5 /
AnnaBridge	145:64910690c574	282	/**
AnnaBridge	145:64910690c574	283	* @}
AnnaBridge	145:64910690c574	284	*/
AnnaBridge	145:64910690c574	285
AnnaBridge	145:64910690c574	286	/** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock
AnnaBridge	145:64910690c574	287	* @{
AnnaBridge	145:64910690c574	288	*/
AnnaBridge	145:64910690c574	289	#define LL_RCC_RTC_NOCLOCK 0x00000000U /!< HSE not divided /
AnnaBridge	145:64910690c574	290	#define LL_RCC_RTC_HSE_DIV_2 RCC_CFGR_RTCPRE_1 /!< HSE clock divided by 2 /
AnnaBridge	145:64910690c574	291	#define LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 3 /
AnnaBridge	145:64910690c574	292	#define LL_RCC_RTC_HSE_DIV_4 RCC_CFGR_RTCPRE_2 /!< HSE clock divided by 4 /
AnnaBridge	145:64910690c574	293	#define LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 5 /
AnnaBridge	145:64910690c574	294	#define LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 6 /
AnnaBridge	145:64910690c574	295	#define LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 7 /
AnnaBridge	145:64910690c574	296	#define LL_RCC_RTC_HSE_DIV_8 RCC_CFGR_RTCPRE_3 /!< HSE clock divided by 8 /
AnnaBridge	145:64910690c574	297	#define LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 9 /
AnnaBridge	145:64910690c574	298	#define LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 10 /
AnnaBridge	145:64910690c574	299	#define LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 11 /
AnnaBridge	145:64910690c574	300	#define LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2) /!< HSE clock divided by 12 /
AnnaBridge	145:64910690c574	301	#define LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 13 /
AnnaBridge	145:64910690c574	302	#define LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 14 /
AnnaBridge	145:64910690c574	303	#define LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 15 /
AnnaBridge	145:64910690c574	304	#define LL_RCC_RTC_HSE_DIV_16 RCC_CFGR_RTCPRE_4 /!< HSE clock divided by 16 /
AnnaBridge	145:64910690c574	305	#define LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 17 /
AnnaBridge	145:64910690c574	306	#define LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 18 /
AnnaBridge	145:64910690c574	307	#define LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 19 /
AnnaBridge	145:64910690c574	308	#define LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2) /!< HSE clock divided by 20 /
AnnaBridge	145:64910690c574	309	#define LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 21 /
AnnaBridge	145:64910690c574	310	#define LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 22 /
AnnaBridge	145:64910690c574	311	#define LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 23 /
AnnaBridge	145:64910690c574	312	#define LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3) /!< HSE clock divided by 24 /
AnnaBridge	145:64910690c574	313	#define LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 25 /
AnnaBridge	145:64910690c574	314	#define LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 26 /
AnnaBridge	145:64910690c574	315	#define LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 27 /
AnnaBridge	145:64910690c574	316	#define LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2) /!< HSE clock divided by 28 /
AnnaBridge	145:64910690c574	317	#define LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 29 /
AnnaBridge	145:64910690c574	318	#define LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1) /!< HSE clock divided by 30 /
AnnaBridge	145:64910690c574	319	#define LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4\|RCC_CFGR_RTCPRE_3\|RCC_CFGR_RTCPRE_2\|RCC_CFGR_RTCPRE_1\|RCC_CFGR_RTCPRE_0) /!< HSE clock divided by 31 /
AnnaBridge	145:64910690c574	320	/**
AnnaBridge	145:64910690c574	321	* @}
AnnaBridge	145:64910690c574	322	*/
AnnaBridge	145:64910690c574	323
AnnaBridge	145:64910690c574	324	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	145:64910690c574	325	/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
AnnaBridge	145:64910690c574	326	* @{
AnnaBridge	145:64910690c574	327	*/
AnnaBridge	145:64910690c574	328	#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /!< No clock enabled for the peripheral /
AnnaBridge	145:64910690c574	329	#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /!< Frequency cannot be provided as external clock /
AnnaBridge	145:64910690c574	330	/**
AnnaBridge	145:64910690c574	331	* @}
AnnaBridge	145:64910690c574	332	*/
AnnaBridge	145:64910690c574	333	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	145:64910690c574	334
AnnaBridge	145:64910690c574	335	/** @defgroup RCC_LL_EC_I2S1_CLKSOURCE Peripheral I2S clock source selection
AnnaBridge	145:64910690c574	336	* @{
AnnaBridge	145:64910690c574	337	*/
AnnaBridge	145:64910690c574	338	#define LL_RCC_I2S1_CLKSOURCE_PLLI2S 0x00000000U /!< I2S oscillator clock used as I2S1 clock /
AnnaBridge	145:64910690c574	339	#define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CFGR_I2SSRC /!< External pin clock used as I2S1 clock /
AnnaBridge	145:64910690c574	340	/**
AnnaBridge	145:64910690c574	341	* @}
AnnaBridge	145:64910690c574	342	*/
AnnaBridge	145:64910690c574	343
AnnaBridge	145:64910690c574	344	/** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source
AnnaBridge	145:64910690c574	345	* @{
AnnaBridge	145:64910690c574	346	*/
AnnaBridge	145:64910690c574	347	#define LL_RCC_I2S1_CLKSOURCE RCC_CFGR_I2SSRC /!< I2S1 Clock source selection /
AnnaBridge	145:64910690c574	348	/**
AnnaBridge	145:64910690c574	349	* @}
AnnaBridge	145:64910690c574	350	*/
AnnaBridge	145:64910690c574	351
AnnaBridge	145:64910690c574	352	/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
AnnaBridge	145:64910690c574	353	* @{
AnnaBridge	145:64910690c574	354	*/
AnnaBridge	145:64910690c574	355	#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /!< No clock used as RTC clock /
AnnaBridge	145:64910690c574	356	#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /!< LSE oscillator clock used as RTC clock /
AnnaBridge	145:64910690c574	357	#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /!< LSI oscillator clock used as RTC clock /
AnnaBridge	145:64910690c574	358	#define LL_RCC_RTC_CLKSOURCE_HSE RCC_BDCR_RTCSEL /!< HSE oscillator clock divided by HSE prescaler used as RTC clock /
AnnaBridge	145:64910690c574	359	/**
AnnaBridge	145:64910690c574	360	* @}
AnnaBridge	145:64910690c574	361	*/
AnnaBridge	145:64910690c574	362
AnnaBridge	145:64910690c574	363	/** @defgroup RCC_LL_EC_PLLSOURCE PLL and PLLI2S entry clock source
AnnaBridge	145:64910690c574	364	* @{
AnnaBridge	145:64910690c574	365	*/
AnnaBridge	145:64910690c574	366	#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /!< HSI16 clock selected as PLL entry clock source /
AnnaBridge	145:64910690c574	367	#define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /!< HSE clock selected as PLL entry clock source /
AnnaBridge	145:64910690c574	368	/**
AnnaBridge	145:64910690c574	369	* @}
AnnaBridge	145:64910690c574	370	*/
AnnaBridge	145:64910690c574	371
AnnaBridge	145:64910690c574	372	/** @defgroup RCC_LL_EC_PLLM_DIV PLL and PLLI2S division factor
AnnaBridge	145:64910690c574	373	* @{
AnnaBridge	145:64910690c574	374	*/
AnnaBridge	145:64910690c574	375	#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_1) /!< PLL and PLLI2S division factor by 2 /
AnnaBridge	145:64910690c574	376	#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 3 /
AnnaBridge	145:64910690c574	377	#define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_2) /!< PLL and PLLI2S division factor by 4 /
AnnaBridge	145:64910690c574	378	#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 5 /
AnnaBridge	145:64910690c574	379	#define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL and PLLI2S division factor by 6 /
AnnaBridge	145:64910690c574	380	#define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 7 /
AnnaBridge	145:64910690c574	381	#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_3) /!< PLL and PLLI2S division factor by 8 /
AnnaBridge	145:64910690c574	382	#define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 9 /
AnnaBridge	145:64910690c574	383	#define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1) /!< PLL and PLLI2S division factor by 10 /
AnnaBridge	145:64910690c574	384	#define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 11 /
AnnaBridge	145:64910690c574	385	#define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2) /!< PLL and PLLI2S division factor by 12 /
AnnaBridge	145:64910690c574	386	#define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 13 /
AnnaBridge	145:64910690c574	387	#define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL and PLLI2S division factor by 14 /
AnnaBridge	145:64910690c574	388	#define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 15 /
AnnaBridge	145:64910690c574	389	#define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_4) /!< PLL and PLLI2S division factor by 16 /
AnnaBridge	145:64910690c574	390	#define LL_RCC_PLLM_DIV_17 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 17 /
AnnaBridge	145:64910690c574	391	#define LL_RCC_PLLM_DIV_18 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_1) /!< PLL and PLLI2S division factor by 18 /
AnnaBridge	145:64910690c574	392	#define LL_RCC_PLLM_DIV_19 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 19 /
AnnaBridge	145:64910690c574	393	#define LL_RCC_PLLM_DIV_20 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2) /!< PLL and PLLI2S division factor by 20 /
AnnaBridge	145:64910690c574	394	#define LL_RCC_PLLM_DIV_21 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 21 /
AnnaBridge	145:64910690c574	395	#define LL_RCC_PLLM_DIV_22 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL and PLLI2S division factor by 22 /
AnnaBridge	145:64910690c574	396	#define LL_RCC_PLLM_DIV_23 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 23 /
AnnaBridge	145:64910690c574	397	#define LL_RCC_PLLM_DIV_24 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3) /!< PLL and PLLI2S division factor by 24 /
AnnaBridge	145:64910690c574	398	#define LL_RCC_PLLM_DIV_25 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 25 /
AnnaBridge	145:64910690c574	399	#define LL_RCC_PLLM_DIV_26 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1) /!< PLL and PLLI2S division factor by 26 /
AnnaBridge	145:64910690c574	400	#define LL_RCC_PLLM_DIV_27 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 27 /
AnnaBridge	145:64910690c574	401	#define LL_RCC_PLLM_DIV_28 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2) /!< PLL and PLLI2S division factor by 28 /
AnnaBridge	145:64910690c574	402	#define LL_RCC_PLLM_DIV_29 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 29 /
AnnaBridge	145:64910690c574	403	#define LL_RCC_PLLM_DIV_30 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL and PLLI2S division factor by 30 /
AnnaBridge	145:64910690c574	404	#define LL_RCC_PLLM_DIV_31 (RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 31 /
AnnaBridge	145:64910690c574	405	#define LL_RCC_PLLM_DIV_32 (RCC_PLLCFGR_PLLM_5) /!< PLL and PLLI2S division factor by 32 /
AnnaBridge	145:64910690c574	406	#define LL_RCC_PLLM_DIV_33 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 33 /
AnnaBridge	145:64910690c574	407	#define LL_RCC_PLLM_DIV_34 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_1) /!< PLL and PLLI2S division factor by 34 /
AnnaBridge	145:64910690c574	408	#define LL_RCC_PLLM_DIV_35 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 35 /
AnnaBridge	145:64910690c574	409	#define LL_RCC_PLLM_DIV_36 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_2) /!< PLL and PLLI2S division factor by 36 /
AnnaBridge	145:64910690c574	410	#define LL_RCC_PLLM_DIV_37 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 37 /
AnnaBridge	145:64910690c574	411	#define LL_RCC_PLLM_DIV_38 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL and PLLI2S division factor by 38 /
AnnaBridge	145:64910690c574	412	#define LL_RCC_PLLM_DIV_39 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 39 /
AnnaBridge	145:64910690c574	413	#define LL_RCC_PLLM_DIV_40 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3) /!< PLL and PLLI2S division factor by 40 /
AnnaBridge	145:64910690c574	414	#define LL_RCC_PLLM_DIV_41 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 41 /
AnnaBridge	145:64910690c574	415	#define LL_RCC_PLLM_DIV_42 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1) /!< PLL and PLLI2S division factor by 42 /
AnnaBridge	145:64910690c574	416	#define LL_RCC_PLLM_DIV_43 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 43 /
AnnaBridge	145:64910690c574	417	#define LL_RCC_PLLM_DIV_44 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2) /!< PLL and PLLI2S division factor by 44 /
AnnaBridge	145:64910690c574	418	#define LL_RCC_PLLM_DIV_45 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 45 /
AnnaBridge	145:64910690c574	419	#define LL_RCC_PLLM_DIV_46 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL and PLLI2S division factor by 46 /
AnnaBridge	145:64910690c574	420	#define LL_RCC_PLLM_DIV_47 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 47 /
AnnaBridge	145:64910690c574	421	#define LL_RCC_PLLM_DIV_48 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4) /!< PLL and PLLI2S division factor by 48 /
AnnaBridge	145:64910690c574	422	#define LL_RCC_PLLM_DIV_49 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 49 /
AnnaBridge	145:64910690c574	423	#define LL_RCC_PLLM_DIV_50 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_1) /!< PLL and PLLI2S division factor by 50 /
AnnaBridge	145:64910690c574	424	#define LL_RCC_PLLM_DIV_51 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 51 /
AnnaBridge	145:64910690c574	425	#define LL_RCC_PLLM_DIV_52 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2) /!< PLL and PLLI2S division factor by 52 /
AnnaBridge	145:64910690c574	426	#define LL_RCC_PLLM_DIV_53 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 53 /
AnnaBridge	145:64910690c574	427	#define LL_RCC_PLLM_DIV_54 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL and PLLI2S division factor by 54 /
AnnaBridge	145:64910690c574	428	#define LL_RCC_PLLM_DIV_55 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 55 /
AnnaBridge	145:64910690c574	429	#define LL_RCC_PLLM_DIV_56 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3) /!< PLL and PLLI2S division factor by 56 /
AnnaBridge	145:64910690c574	430	#define LL_RCC_PLLM_DIV_57 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 57 /
AnnaBridge	145:64910690c574	431	#define LL_RCC_PLLM_DIV_58 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1) /!< PLL and PLLI2S division factor by 58 /
AnnaBridge	145:64910690c574	432	#define LL_RCC_PLLM_DIV_59 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 59 /
AnnaBridge	145:64910690c574	433	#define LL_RCC_PLLM_DIV_60 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2) /!< PLL and PLLI2S division factor by 60 /
AnnaBridge	145:64910690c574	434	#define LL_RCC_PLLM_DIV_61 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 61 /
AnnaBridge	145:64910690c574	435	#define LL_RCC_PLLM_DIV_62 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< PLL and PLLI2S division factor by 62 /
AnnaBridge	145:64910690c574	436	#define LL_RCC_PLLM_DIV_63 (RCC_PLLCFGR_PLLM_5 \| RCC_PLLCFGR_PLLM_4 \| RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< PLL and PLLI2S division factor by 63 /
AnnaBridge	145:64910690c574	437	/**
AnnaBridge	145:64910690c574	438	* @}
AnnaBridge	145:64910690c574	439	*/
AnnaBridge	145:64910690c574	440
AnnaBridge	145:64910690c574	441	/** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
AnnaBridge	145:64910690c574	442	* @{
AnnaBridge	145:64910690c574	443	*/
AnnaBridge	145:64910690c574	444	#define LL_RCC_PLLP_DIV_2 0x00000000U /!< Main PLL division factor for PLLP output by 2 /
AnnaBridge	145:64910690c574	445	#define LL_RCC_PLLP_DIV_4 RCC_PLLCFGR_PLLP_0 /!< Main PLL division factor for PLLP output by 4 /
AnnaBridge	145:64910690c574	446	#define LL_RCC_PLLP_DIV_6 RCC_PLLCFGR_PLLP_1 /!< Main PLL division factor for PLLP output by 6 /
AnnaBridge	145:64910690c574	447	#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_1 \| RCC_PLLCFGR_PLLP_0) /!< Main PLL division factor for PLLP output by 8 /
AnnaBridge	145:64910690c574	448	/**
AnnaBridge	145:64910690c574	449	* @}
AnnaBridge	145:64910690c574	450	*/
AnnaBridge	145:64910690c574	451
AnnaBridge	145:64910690c574	452	/** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
AnnaBridge	145:64910690c574	453	* @{
AnnaBridge	145:64910690c574	454	*/
AnnaBridge	145:64910690c574	455	#define LL_RCC_PLLQ_DIV_2 RCC_PLLCFGR_PLLQ_1 /!< Main PLL division factor for PLLQ output by 2 /
AnnaBridge	145:64910690c574	456	#define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 3 /
AnnaBridge	145:64910690c574	457	#define LL_RCC_PLLQ_DIV_4 RCC_PLLCFGR_PLLQ_2 /!< Main PLL division factor for PLLQ output by 4 /
AnnaBridge	145:64910690c574	458	#define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 5 /
AnnaBridge	145:64910690c574	459	#define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_1) /!< Main PLL division factor for PLLQ output by 6 /
AnnaBridge	145:64910690c574	460	#define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_1\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 7 /
AnnaBridge	145:64910690c574	461	#define LL_RCC_PLLQ_DIV_8 RCC_PLLCFGR_PLLQ_3 /!< Main PLL division factor for PLLQ output by 8 /
AnnaBridge	145:64910690c574	462	#define LL_RCC_PLLQ_DIV_9 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 9 /
AnnaBridge	145:64910690c574	463	#define LL_RCC_PLLQ_DIV_10 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_1) /!< Main PLL division factor for PLLQ output by 10 /
AnnaBridge	145:64910690c574	464	#define LL_RCC_PLLQ_DIV_11 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_1\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 11 /
AnnaBridge	145:64910690c574	465	#define LL_RCC_PLLQ_DIV_12 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_2) /!< Main PLL division factor for PLLQ output by 12 /
AnnaBridge	145:64910690c574	466	#define LL_RCC_PLLQ_DIV_13 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 13 /
AnnaBridge	145:64910690c574	467	#define LL_RCC_PLLQ_DIV_14 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_1) /!< Main PLL division factor for PLLQ output by 14 /
AnnaBridge	145:64910690c574	468	#define LL_RCC_PLLQ_DIV_15 (RCC_PLLCFGR_PLLQ_3\|RCC_PLLCFGR_PLLQ_2\|RCC_PLLCFGR_PLLQ_1\|RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 15 /
AnnaBridge	145:64910690c574	469	/**
AnnaBridge	145:64910690c574	470	* @}
AnnaBridge	145:64910690c574	471	*/
AnnaBridge	145:64910690c574	472
AnnaBridge	145:64910690c574	473	/** @defgroup RCC_LL_EC_PLL_SPRE_SEL PLL Spread Spectrum Selection
AnnaBridge	145:64910690c574	474	* @{
AnnaBridge	145:64910690c574	475	*/
AnnaBridge	145:64910690c574	476	#define LL_RCC_SPREAD_SELECT_CENTER 0x00000000U /!< PLL center spread spectrum selection /
AnnaBridge	145:64910690c574	477	#define LL_RCC_SPREAD_SELECT_DOWN RCC_SSCGR_SPREADSEL /!< PLL down spread spectrum selection /
AnnaBridge	145:64910690c574	478	/**
AnnaBridge	145:64910690c574	479	* @}
AnnaBridge	145:64910690c574	480	*/
AnnaBridge	145:64910690c574	481
AnnaBridge	145:64910690c574	482	/** @defgroup RCC_LL_EC_PLLI2SR PLLI2SR division factor (PLLI2SR)
AnnaBridge	145:64910690c574	483	* @{
AnnaBridge	145:64910690c574	484	*/
AnnaBridge	145:64910690c574	485	#define LL_RCC_PLLI2SR_DIV_2 RCC_PLLI2SCFGR_PLLI2SR_1 /!< PLLI2S division factor for PLLI2SR output by 2 /
AnnaBridge	145:64910690c574	486	#define LL_RCC_PLLI2SR_DIV_3 (RCC_PLLI2SCFGR_PLLI2SR_1 \| RCC_PLLI2SCFGR_PLLI2SR_0) /!< PLLI2S division factor for PLLI2SR output by 3 /
AnnaBridge	145:64910690c574	487	#define LL_RCC_PLLI2SR_DIV_4 RCC_PLLI2SCFGR_PLLI2SR_2 /!< PLLI2S division factor for PLLI2SR output by 4 /
AnnaBridge	145:64910690c574	488	#define LL_RCC_PLLI2SR_DIV_5 (RCC_PLLI2SCFGR_PLLI2SR_2 \| RCC_PLLI2SCFGR_PLLI2SR_0) /!< PLLI2S division factor for PLLI2SR output by 5 /
AnnaBridge	145:64910690c574	489	#define LL_RCC_PLLI2SR_DIV_6 (RCC_PLLI2SCFGR_PLLI2SR_2 \| RCC_PLLI2SCFGR_PLLI2SR_1) /!< PLLI2S division factor for PLLI2SR output by 6 /
AnnaBridge	145:64910690c574	490	#define LL_RCC_PLLI2SR_DIV_7 (RCC_PLLI2SCFGR_PLLI2SR_2 \| RCC_PLLI2SCFGR_PLLI2SR_1 \| RCC_PLLI2SCFGR_PLLI2SR_0) /!< PLLI2S division factor for PLLI2SR output by 7 /
AnnaBridge	145:64910690c574	491	/**
AnnaBridge	145:64910690c574	492	* @}
AnnaBridge	145:64910690c574	493	*/
AnnaBridge	145:64910690c574	494
AnnaBridge	145:64910690c574	495	/**
AnnaBridge	145:64910690c574	496	* @}
AnnaBridge	145:64910690c574	497	*/
AnnaBridge	145:64910690c574	498
AnnaBridge	145:64910690c574	499	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	500	/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
AnnaBridge	145:64910690c574	501	* @{
AnnaBridge	145:64910690c574	502	*/
AnnaBridge	145:64910690c574	503
AnnaBridge	145:64910690c574	504	/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	145:64910690c574	505	* @{
AnnaBridge	145:64910690c574	506	*/
AnnaBridge	145:64910690c574	507
AnnaBridge	145:64910690c574	508	/**
AnnaBridge	145:64910690c574	509	* @brief Write a value in RCC register
AnnaBridge	145:64910690c574	510	* @param __REG__ Register to be written
AnnaBridge	145:64910690c574	511	* @param __VALUE__ Value to be written in the register
AnnaBridge	145:64910690c574	512	* @retval None
AnnaBridge	145:64910690c574	513	*/
AnnaBridge	145:64910690c574	514	#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
AnnaBridge	145:64910690c574	515
AnnaBridge	145:64910690c574	516	/**
AnnaBridge	145:64910690c574	517	* @brief Read a value in RCC register
AnnaBridge	145:64910690c574	518	* @param __REG__ Register to be read
AnnaBridge	145:64910690c574	519	* @retval Register value
AnnaBridge	145:64910690c574	520	*/
AnnaBridge	145:64910690c574	521	#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
AnnaBridge	145:64910690c574	522	/**
AnnaBridge	145:64910690c574	523	* @}
AnnaBridge	145:64910690c574	524	*/
AnnaBridge	145:64910690c574	525
AnnaBridge	145:64910690c574	526	/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
AnnaBridge	145:64910690c574	527	* @{
AnnaBridge	145:64910690c574	528	*/
AnnaBridge	145:64910690c574	529
AnnaBridge	145:64910690c574	530	/**
AnnaBridge	145:64910690c574	531	* @brief Helper macro to calculate the PLLCLK frequency on system domain
AnnaBridge	145:64910690c574	532	* @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	145:64910690c574	533	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
AnnaBridge	145:64910690c574	534	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
AnnaBridge	145:64910690c574	535	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	536	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	145:64910690c574	537	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	145:64910690c574	538	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	145:64910690c574	539	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	145:64910690c574	540	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	145:64910690c574	541	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	145:64910690c574	542	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	145:64910690c574	543	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	145:64910690c574	544	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	145:64910690c574	545	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	145:64910690c574	546	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	145:64910690c574	547	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	145:64910690c574	548	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	145:64910690c574	549	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	145:64910690c574	550	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	145:64910690c574	551	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	145:64910690c574	552	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	145:64910690c574	553	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	145:64910690c574	554	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	145:64910690c574	555	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	145:64910690c574	556	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	145:64910690c574	557	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	145:64910690c574	558	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	145:64910690c574	559	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	145:64910690c574	560	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	145:64910690c574	561	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	145:64910690c574	562	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	145:64910690c574	563	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	145:64910690c574	564	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	145:64910690c574	565	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	145:64910690c574	566	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	145:64910690c574	567	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	145:64910690c574	568	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	145:64910690c574	569	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	145:64910690c574	570	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	145:64910690c574	571	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	145:64910690c574	572	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	145:64910690c574	573	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	145:64910690c574	574	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	145:64910690c574	575	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	145:64910690c574	576	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	145:64910690c574	577	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	145:64910690c574	578	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	145:64910690c574	579	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	145:64910690c574	580	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	145:64910690c574	581	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	145:64910690c574	582	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	145:64910690c574	583	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	145:64910690c574	584	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	145:64910690c574	585	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	145:64910690c574	586	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	145:64910690c574	587	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	145:64910690c574	588	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	145:64910690c574	589	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	145:64910690c574	590	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	145:64910690c574	591	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	145:64910690c574	592	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	145:64910690c574	593	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	145:64910690c574	594	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	145:64910690c574	595	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	145:64910690c574	596	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	145:64910690c574	597	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	145:64910690c574	598	* @param __PLLN__ Between 192 and 432
AnnaBridge	145:64910690c574	599	* @param __PLLP__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	600	* @arg @ref LL_RCC_PLLP_DIV_2
AnnaBridge	145:64910690c574	601	* @arg @ref LL_RCC_PLLP_DIV_4
AnnaBridge	145:64910690c574	602	* @arg @ref LL_RCC_PLLP_DIV_6
AnnaBridge	145:64910690c574	603	* @arg @ref LL_RCC_PLLP_DIV_8
AnnaBridge	145:64910690c574	604	* @retval PLL clock frequency (in Hz)
AnnaBridge	145:64910690c574	605	*/
AnnaBridge	145:64910690c574	606	#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
AnnaBridge	145:64910690c574	607	((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U))
AnnaBridge	145:64910690c574	608
AnnaBridge	145:64910690c574	609	/**
AnnaBridge	145:64910690c574	610	* @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
AnnaBridge	145:64910690c574	611	* @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	145:64910690c574	612	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
AnnaBridge	145:64910690c574	613	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
AnnaBridge	145:64910690c574	614	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	615	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	145:64910690c574	616	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	145:64910690c574	617	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	145:64910690c574	618	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	145:64910690c574	619	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	145:64910690c574	620	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	145:64910690c574	621	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	145:64910690c574	622	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	145:64910690c574	623	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	145:64910690c574	624	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	145:64910690c574	625	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	145:64910690c574	626	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	145:64910690c574	627	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	145:64910690c574	628	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	145:64910690c574	629	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	145:64910690c574	630	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	145:64910690c574	631	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	145:64910690c574	632	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	145:64910690c574	633	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	145:64910690c574	634	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	145:64910690c574	635	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	145:64910690c574	636	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	145:64910690c574	637	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	145:64910690c574	638	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	145:64910690c574	639	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	145:64910690c574	640	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	145:64910690c574	641	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	145:64910690c574	642	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	145:64910690c574	643	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	145:64910690c574	644	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	145:64910690c574	645	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	145:64910690c574	646	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	145:64910690c574	647	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	145:64910690c574	648	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	145:64910690c574	649	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	145:64910690c574	650	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	145:64910690c574	651	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	145:64910690c574	652	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	145:64910690c574	653	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	145:64910690c574	654	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	145:64910690c574	655	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	145:64910690c574	656	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	145:64910690c574	657	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	145:64910690c574	658	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	145:64910690c574	659	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	145:64910690c574	660	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	145:64910690c574	661	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	145:64910690c574	662	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	145:64910690c574	663	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	145:64910690c574	664	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	145:64910690c574	665	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	145:64910690c574	666	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	145:64910690c574	667	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	145:64910690c574	668	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	145:64910690c574	669	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	145:64910690c574	670	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	145:64910690c574	671	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	145:64910690c574	672	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	145:64910690c574	673	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	145:64910690c574	674	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	145:64910690c574	675	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	145:64910690c574	676	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	145:64910690c574	677	* @param __PLLN__ Between 192 and 432
AnnaBridge	145:64910690c574	678	* @param __PLLQ__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	679	* @arg @ref LL_RCC_PLLQ_DIV_2
AnnaBridge	145:64910690c574	680	* @arg @ref LL_RCC_PLLQ_DIV_3
AnnaBridge	145:64910690c574	681	* @arg @ref LL_RCC_PLLQ_DIV_4
AnnaBridge	145:64910690c574	682	* @arg @ref LL_RCC_PLLQ_DIV_5
AnnaBridge	145:64910690c574	683	* @arg @ref LL_RCC_PLLQ_DIV_6
AnnaBridge	145:64910690c574	684	* @arg @ref LL_RCC_PLLQ_DIV_7
AnnaBridge	145:64910690c574	685	* @arg @ref LL_RCC_PLLQ_DIV_8
AnnaBridge	145:64910690c574	686	* @arg @ref LL_RCC_PLLQ_DIV_9
AnnaBridge	145:64910690c574	687	* @arg @ref LL_RCC_PLLQ_DIV_10
AnnaBridge	145:64910690c574	688	* @arg @ref LL_RCC_PLLQ_DIV_11
AnnaBridge	145:64910690c574	689	* @arg @ref LL_RCC_PLLQ_DIV_12
AnnaBridge	145:64910690c574	690	* @arg @ref LL_RCC_PLLQ_DIV_13
AnnaBridge	145:64910690c574	691	* @arg @ref LL_RCC_PLLQ_DIV_14
AnnaBridge	145:64910690c574	692	* @arg @ref LL_RCC_PLLQ_DIV_15
AnnaBridge	145:64910690c574	693	* @retval PLL clock frequency (in Hz)
AnnaBridge	145:64910690c574	694	*/
AnnaBridge	145:64910690c574	695	#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
AnnaBridge	145:64910690c574	696	((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos ))
AnnaBridge	145:64910690c574	697
AnnaBridge	145:64910690c574	698	/**
AnnaBridge	145:64910690c574	699	* @retval PLLI2S clock frequency (in Hz)
AnnaBridge	145:64910690c574	700	*/
AnnaBridge	145:64910690c574	701
AnnaBridge	145:64910690c574	702	/**
AnnaBridge	145:64910690c574	703	* @brief Helper macro to calculate the PLLI2S frequency used for I2S domain
AnnaBridge	145:64910690c574	704	* @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	145:64910690c574	705	* @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ());
AnnaBridge	145:64910690c574	706	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
AnnaBridge	145:64910690c574	707	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	708	* @param __PLLI2SN__ Between 192 and 432
AnnaBridge	145:64910690c574	709	* @param __PLLI2SR__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	710	* @arg @ref LL_RCC_PLLI2SR_DIV_2
AnnaBridge	145:64910690c574	711	* @arg @ref LL_RCC_PLLI2SR_DIV_3
AnnaBridge	145:64910690c574	712	* @arg @ref LL_RCC_PLLI2SR_DIV_4
AnnaBridge	145:64910690c574	713	* @arg @ref LL_RCC_PLLI2SR_DIV_5
AnnaBridge	145:64910690c574	714	* @arg @ref LL_RCC_PLLI2SR_DIV_6
AnnaBridge	145:64910690c574	715	* @arg @ref LL_RCC_PLLI2SR_DIV_7
AnnaBridge	145:64910690c574	716	* @retval PLLI2S clock frequency (in Hz)
AnnaBridge	145:64910690c574	717	*/
AnnaBridge	145:64910690c574	718	#define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
AnnaBridge	145:64910690c574	719	((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos))
AnnaBridge	145:64910690c574	720
AnnaBridge	145:64910690c574	721	/**
AnnaBridge	145:64910690c574	722	* @brief Helper macro to calculate the HCLK frequency
AnnaBridge	145:64910690c574	723	* @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
AnnaBridge	145:64910690c574	724	* @param __AHBPRESCALER__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	725	* @arg @ref LL_RCC_SYSCLK_DIV_1
AnnaBridge	145:64910690c574	726	* @arg @ref LL_RCC_SYSCLK_DIV_2
AnnaBridge	145:64910690c574	727	* @arg @ref LL_RCC_SYSCLK_DIV_4
AnnaBridge	145:64910690c574	728	* @arg @ref LL_RCC_SYSCLK_DIV_8
AnnaBridge	145:64910690c574	729	* @arg @ref LL_RCC_SYSCLK_DIV_16
AnnaBridge	145:64910690c574	730	* @arg @ref LL_RCC_SYSCLK_DIV_64
AnnaBridge	145:64910690c574	731	* @arg @ref LL_RCC_SYSCLK_DIV_128
AnnaBridge	145:64910690c574	732	* @arg @ref LL_RCC_SYSCLK_DIV_256
AnnaBridge	145:64910690c574	733	* @arg @ref LL_RCC_SYSCLK_DIV_512
AnnaBridge	145:64910690c574	734	* @retval HCLK clock frequency (in Hz)
AnnaBridge	145:64910690c574	735	*/
AnnaBridge	145:64910690c574	736	#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
AnnaBridge	145:64910690c574	737
AnnaBridge	145:64910690c574	738	/**
AnnaBridge	145:64910690c574	739	* @brief Helper macro to calculate the PCLK1 frequency (ABP1)
AnnaBridge	145:64910690c574	740	* @param __HCLKFREQ__ HCLK frequency
AnnaBridge	145:64910690c574	741	* @param __APB1PRESCALER__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	742	* @arg @ref LL_RCC_APB1_DIV_1
AnnaBridge	145:64910690c574	743	* @arg @ref LL_RCC_APB1_DIV_2
AnnaBridge	145:64910690c574	744	* @arg @ref LL_RCC_APB1_DIV_4
AnnaBridge	145:64910690c574	745	* @arg @ref LL_RCC_APB1_DIV_8
AnnaBridge	145:64910690c574	746	* @arg @ref LL_RCC_APB1_DIV_16
AnnaBridge	145:64910690c574	747	* @retval PCLK1 clock frequency (in Hz)
AnnaBridge	145:64910690c574	748	*/
AnnaBridge	145:64910690c574	749	#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
AnnaBridge	145:64910690c574	750
AnnaBridge	145:64910690c574	751	/**
AnnaBridge	145:64910690c574	752	* @brief Helper macro to calculate the PCLK2 frequency (ABP2)
AnnaBridge	145:64910690c574	753	* @param __HCLKFREQ__ HCLK frequency
AnnaBridge	145:64910690c574	754	* @param __APB2PRESCALER__ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	755	* @arg @ref LL_RCC_APB2_DIV_1
AnnaBridge	145:64910690c574	756	* @arg @ref LL_RCC_APB2_DIV_2
AnnaBridge	145:64910690c574	757	* @arg @ref LL_RCC_APB2_DIV_4
AnnaBridge	145:64910690c574	758	* @arg @ref LL_RCC_APB2_DIV_8
AnnaBridge	145:64910690c574	759	* @arg @ref LL_RCC_APB2_DIV_16
AnnaBridge	145:64910690c574	760	* @retval PCLK2 clock frequency (in Hz)
AnnaBridge	145:64910690c574	761	*/
AnnaBridge	145:64910690c574	762	#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
AnnaBridge	145:64910690c574	763
AnnaBridge	145:64910690c574	764	/**
AnnaBridge	145:64910690c574	765	* @}
AnnaBridge	145:64910690c574	766	*/
AnnaBridge	145:64910690c574	767
AnnaBridge	145:64910690c574	768	/**
AnnaBridge	145:64910690c574	769	* @}
AnnaBridge	145:64910690c574	770	*/
AnnaBridge	145:64910690c574	771
AnnaBridge	145:64910690c574	772	/* Exported functions --------------------------------------------------------*/
AnnaBridge	145:64910690c574	773	/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
AnnaBridge	145:64910690c574	774	* @{
AnnaBridge	145:64910690c574	775	*/
AnnaBridge	145:64910690c574	776
AnnaBridge	145:64910690c574	777	/** @defgroup RCC_LL_EF_HSE HSE
AnnaBridge	145:64910690c574	778	* @{
AnnaBridge	145:64910690c574	779	*/
AnnaBridge	145:64910690c574	780
AnnaBridge	145:64910690c574	781	/**
AnnaBridge	145:64910690c574	782	* @brief Enable the Clock Security System.
AnnaBridge	145:64910690c574	783	* @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
AnnaBridge	145:64910690c574	784	* @retval None
AnnaBridge	145:64910690c574	785	*/
AnnaBridge	145:64910690c574	786	__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
AnnaBridge	145:64910690c574	787	{
AnnaBridge	145:64910690c574	788	SET_BIT(RCC->CR, RCC_CR_CSSON);
AnnaBridge	145:64910690c574	789	}
AnnaBridge	145:64910690c574	790
AnnaBridge	145:64910690c574	791	/**
AnnaBridge	145:64910690c574	792	* @brief Enable HSE external oscillator (HSE Bypass)
AnnaBridge	145:64910690c574	793	* @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
AnnaBridge	145:64910690c574	794	* @retval None
AnnaBridge	145:64910690c574	795	*/
AnnaBridge	145:64910690c574	796	__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
AnnaBridge	145:64910690c574	797	{
AnnaBridge	145:64910690c574	798	SET_BIT(RCC->CR, RCC_CR_HSEBYP);
AnnaBridge	145:64910690c574	799	}
AnnaBridge	145:64910690c574	800
AnnaBridge	145:64910690c574	801	/**
AnnaBridge	145:64910690c574	802	* @brief Disable HSE external oscillator (HSE Bypass)
AnnaBridge	145:64910690c574	803	* @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
AnnaBridge	145:64910690c574	804	* @retval None
AnnaBridge	145:64910690c574	805	*/
AnnaBridge	145:64910690c574	806	__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
AnnaBridge	145:64910690c574	807	{
AnnaBridge	145:64910690c574	808	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
AnnaBridge	145:64910690c574	809	}
AnnaBridge	145:64910690c574	810
AnnaBridge	145:64910690c574	811	/**
AnnaBridge	145:64910690c574	812	* @brief Enable HSE crystal oscillator (HSE ON)
AnnaBridge	145:64910690c574	813	* @rmtoll CR HSEON LL_RCC_HSE_Enable
AnnaBridge	145:64910690c574	814	* @retval None
AnnaBridge	145:64910690c574	815	*/
AnnaBridge	145:64910690c574	816	__STATIC_INLINE void LL_RCC_HSE_Enable(void)
AnnaBridge	145:64910690c574	817	{
AnnaBridge	145:64910690c574	818	SET_BIT(RCC->CR, RCC_CR_HSEON);
AnnaBridge	145:64910690c574	819	}
AnnaBridge	145:64910690c574	820
AnnaBridge	145:64910690c574	821	/**
AnnaBridge	145:64910690c574	822	* @brief Disable HSE crystal oscillator (HSE ON)
AnnaBridge	145:64910690c574	823	* @rmtoll CR HSEON LL_RCC_HSE_Disable
AnnaBridge	145:64910690c574	824	* @retval None
AnnaBridge	145:64910690c574	825	*/
AnnaBridge	145:64910690c574	826	__STATIC_INLINE void LL_RCC_HSE_Disable(void)
AnnaBridge	145:64910690c574	827	{
AnnaBridge	145:64910690c574	828	CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
AnnaBridge	145:64910690c574	829	}
AnnaBridge	145:64910690c574	830
AnnaBridge	145:64910690c574	831	/**
AnnaBridge	145:64910690c574	832	* @brief Check if HSE oscillator Ready
AnnaBridge	145:64910690c574	833	* @rmtoll CR HSERDY LL_RCC_HSE_IsReady
AnnaBridge	145:64910690c574	834	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	835	*/
AnnaBridge	145:64910690c574	836	__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
AnnaBridge	145:64910690c574	837	{
AnnaBridge	145:64910690c574	838	return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
AnnaBridge	145:64910690c574	839	}
AnnaBridge	145:64910690c574	840
AnnaBridge	145:64910690c574	841	/**
AnnaBridge	145:64910690c574	842	* @}
AnnaBridge	145:64910690c574	843	*/
AnnaBridge	145:64910690c574	844
AnnaBridge	145:64910690c574	845	/** @defgroup RCC_LL_EF_HSI HSI
AnnaBridge	145:64910690c574	846	* @{
AnnaBridge	145:64910690c574	847	*/
AnnaBridge	145:64910690c574	848
AnnaBridge	145:64910690c574	849	/**
AnnaBridge	145:64910690c574	850	* @brief Enable HSI oscillator
AnnaBridge	145:64910690c574	851	* @rmtoll CR HSION LL_RCC_HSI_Enable
AnnaBridge	145:64910690c574	852	* @retval None
AnnaBridge	145:64910690c574	853	*/
AnnaBridge	145:64910690c574	854	__STATIC_INLINE void LL_RCC_HSI_Enable(void)
AnnaBridge	145:64910690c574	855	{
AnnaBridge	145:64910690c574	856	SET_BIT(RCC->CR, RCC_CR_HSION);
AnnaBridge	145:64910690c574	857	}
AnnaBridge	145:64910690c574	858
AnnaBridge	145:64910690c574	859	/**
AnnaBridge	145:64910690c574	860	* @brief Disable HSI oscillator
AnnaBridge	145:64910690c574	861	* @rmtoll CR HSION LL_RCC_HSI_Disable
AnnaBridge	145:64910690c574	862	* @retval None
AnnaBridge	145:64910690c574	863	*/
AnnaBridge	145:64910690c574	864	__STATIC_INLINE void LL_RCC_HSI_Disable(void)
AnnaBridge	145:64910690c574	865	{
AnnaBridge	145:64910690c574	866	CLEAR_BIT(RCC->CR, RCC_CR_HSION);
AnnaBridge	145:64910690c574	867	}
AnnaBridge	145:64910690c574	868
AnnaBridge	145:64910690c574	869	/**
AnnaBridge	145:64910690c574	870	* @brief Check if HSI clock is ready
AnnaBridge	145:64910690c574	871	* @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
AnnaBridge	145:64910690c574	872	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	873	*/
AnnaBridge	145:64910690c574	874	__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
AnnaBridge	145:64910690c574	875	{
AnnaBridge	145:64910690c574	876	return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
AnnaBridge	145:64910690c574	877	}
AnnaBridge	145:64910690c574	878
AnnaBridge	145:64910690c574	879	/**
AnnaBridge	145:64910690c574	880	* @brief Get HSI Calibration value
AnnaBridge	145:64910690c574	881	* @note When HSITRIM is written, HSICAL is updated with the sum of
AnnaBridge	145:64910690c574	882	* HSITRIM and the factory trim value
AnnaBridge	145:64910690c574	883	* @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
AnnaBridge	145:64910690c574	884	* @retval Between Min_Data = 0x00 and Max_Data = 0xFF
AnnaBridge	145:64910690c574	885	*/
AnnaBridge	145:64910690c574	886	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
AnnaBridge	145:64910690c574	887	{
AnnaBridge	145:64910690c574	888	return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
AnnaBridge	145:64910690c574	889	}
AnnaBridge	145:64910690c574	890
AnnaBridge	145:64910690c574	891	/**
AnnaBridge	145:64910690c574	892	* @brief Set HSI Calibration trimming
AnnaBridge	145:64910690c574	893	* @note user-programmable trimming value that is added to the HSICAL
AnnaBridge	145:64910690c574	894	* @note Default value is 16, which, when added to the HSICAL value,
AnnaBridge	145:64910690c574	895	* should trim the HSI to 16 MHz +/- 1 %
AnnaBridge	145:64910690c574	896	* @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
AnnaBridge	145:64910690c574	897	* @param Value Between Min_Data = 0 and Max_Data = 31
AnnaBridge	145:64910690c574	898	* @retval None
AnnaBridge	145:64910690c574	899	*/
AnnaBridge	145:64910690c574	900	__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
AnnaBridge	145:64910690c574	901	{
AnnaBridge	145:64910690c574	902	MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
AnnaBridge	145:64910690c574	903	}
AnnaBridge	145:64910690c574	904
AnnaBridge	145:64910690c574	905	/**
AnnaBridge	145:64910690c574	906	* @brief Get HSI Calibration trimming
AnnaBridge	145:64910690c574	907	* @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
AnnaBridge	145:64910690c574	908	* @retval Between Min_Data = 0 and Max_Data = 31
AnnaBridge	145:64910690c574	909	*/
AnnaBridge	145:64910690c574	910	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
AnnaBridge	145:64910690c574	911	{
AnnaBridge	145:64910690c574	912	return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
AnnaBridge	145:64910690c574	913	}
AnnaBridge	145:64910690c574	914
AnnaBridge	145:64910690c574	915	/**
AnnaBridge	145:64910690c574	916	* @}
AnnaBridge	145:64910690c574	917	*/
AnnaBridge	145:64910690c574	918
AnnaBridge	145:64910690c574	919	/** @defgroup RCC_LL_EF_LSE LSE
AnnaBridge	145:64910690c574	920	* @{
AnnaBridge	145:64910690c574	921	*/
AnnaBridge	145:64910690c574	922
AnnaBridge	145:64910690c574	923	/**
AnnaBridge	145:64910690c574	924	* @brief Enable Low Speed External (LSE) crystal.
AnnaBridge	145:64910690c574	925	* @rmtoll BDCR LSEON LL_RCC_LSE_Enable
AnnaBridge	145:64910690c574	926	* @retval None
AnnaBridge	145:64910690c574	927	*/
AnnaBridge	145:64910690c574	928	__STATIC_INLINE void LL_RCC_LSE_Enable(void)
AnnaBridge	145:64910690c574	929	{
AnnaBridge	145:64910690c574	930	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
AnnaBridge	145:64910690c574	931	}
AnnaBridge	145:64910690c574	932
AnnaBridge	145:64910690c574	933	/**
AnnaBridge	145:64910690c574	934	* @brief Disable Low Speed External (LSE) crystal.
AnnaBridge	145:64910690c574	935	* @rmtoll BDCR LSEON LL_RCC_LSE_Disable
AnnaBridge	145:64910690c574	936	* @retval None
AnnaBridge	145:64910690c574	937	*/
AnnaBridge	145:64910690c574	938	__STATIC_INLINE void LL_RCC_LSE_Disable(void)
AnnaBridge	145:64910690c574	939	{
AnnaBridge	145:64910690c574	940	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
AnnaBridge	145:64910690c574	941	}
AnnaBridge	145:64910690c574	942
AnnaBridge	145:64910690c574	943	/**
AnnaBridge	145:64910690c574	944	* @brief Enable external clock source (LSE bypass).
AnnaBridge	145:64910690c574	945	* @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
AnnaBridge	145:64910690c574	946	* @retval None
AnnaBridge	145:64910690c574	947	*/
AnnaBridge	145:64910690c574	948	__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
AnnaBridge	145:64910690c574	949	{
AnnaBridge	145:64910690c574	950	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
AnnaBridge	145:64910690c574	951	}
AnnaBridge	145:64910690c574	952
AnnaBridge	145:64910690c574	953	/**
AnnaBridge	145:64910690c574	954	* @brief Disable external clock source (LSE bypass).
AnnaBridge	145:64910690c574	955	* @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
AnnaBridge	145:64910690c574	956	* @retval None
AnnaBridge	145:64910690c574	957	*/
AnnaBridge	145:64910690c574	958	__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
AnnaBridge	145:64910690c574	959	{
AnnaBridge	145:64910690c574	960	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
AnnaBridge	145:64910690c574	961	}
AnnaBridge	145:64910690c574	962
AnnaBridge	145:64910690c574	963	/**
AnnaBridge	145:64910690c574	964	* @brief Check if LSE oscillator Ready
AnnaBridge	145:64910690c574	965	* @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
AnnaBridge	145:64910690c574	966	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	967	*/
AnnaBridge	145:64910690c574	968	__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
AnnaBridge	145:64910690c574	969	{
AnnaBridge	145:64910690c574	970	return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
AnnaBridge	145:64910690c574	971	}
AnnaBridge	145:64910690c574	972
AnnaBridge	145:64910690c574	973	/**
AnnaBridge	145:64910690c574	974	* @}
AnnaBridge	145:64910690c574	975	*/
AnnaBridge	145:64910690c574	976
AnnaBridge	145:64910690c574	977	/** @defgroup RCC_LL_EF_LSI LSI
AnnaBridge	145:64910690c574	978	* @{
AnnaBridge	145:64910690c574	979	*/
AnnaBridge	145:64910690c574	980
AnnaBridge	145:64910690c574	981	/**
AnnaBridge	145:64910690c574	982	* @brief Enable LSI Oscillator
AnnaBridge	145:64910690c574	983	* @rmtoll CSR LSION LL_RCC_LSI_Enable
AnnaBridge	145:64910690c574	984	* @retval None
AnnaBridge	145:64910690c574	985	*/
AnnaBridge	145:64910690c574	986	__STATIC_INLINE void LL_RCC_LSI_Enable(void)
AnnaBridge	145:64910690c574	987	{
AnnaBridge	145:64910690c574	988	SET_BIT(RCC->CSR, RCC_CSR_LSION);
AnnaBridge	145:64910690c574	989	}
AnnaBridge	145:64910690c574	990
AnnaBridge	145:64910690c574	991	/**
AnnaBridge	145:64910690c574	992	* @brief Disable LSI Oscillator
AnnaBridge	145:64910690c574	993	* @rmtoll CSR LSION LL_RCC_LSI_Disable
AnnaBridge	145:64910690c574	994	* @retval None
AnnaBridge	145:64910690c574	995	*/
AnnaBridge	145:64910690c574	996	__STATIC_INLINE void LL_RCC_LSI_Disable(void)
AnnaBridge	145:64910690c574	997	{
AnnaBridge	145:64910690c574	998	CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
AnnaBridge	145:64910690c574	999	}
AnnaBridge	145:64910690c574	1000
AnnaBridge	145:64910690c574	1001	/**
AnnaBridge	145:64910690c574	1002	* @brief Check if LSI is Ready
AnnaBridge	145:64910690c574	1003	* @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
AnnaBridge	145:64910690c574	1004	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1005	*/
AnnaBridge	145:64910690c574	1006	__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
AnnaBridge	145:64910690c574	1007	{
AnnaBridge	145:64910690c574	1008	return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
AnnaBridge	145:64910690c574	1009	}
AnnaBridge	145:64910690c574	1010
AnnaBridge	145:64910690c574	1011	/**
AnnaBridge	145:64910690c574	1012	* @}
AnnaBridge	145:64910690c574	1013	*/
AnnaBridge	145:64910690c574	1014
AnnaBridge	145:64910690c574	1015	/** @defgroup RCC_LL_EF_System System
AnnaBridge	145:64910690c574	1016	* @{
AnnaBridge	145:64910690c574	1017	*/
AnnaBridge	145:64910690c574	1018
AnnaBridge	145:64910690c574	1019	/**
AnnaBridge	145:64910690c574	1020	* @brief Configure the system clock source
AnnaBridge	145:64910690c574	1021	* @rmtoll CFGR SW LL_RCC_SetSysClkSource
AnnaBridge	145:64910690c574	1022	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1023	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
AnnaBridge	145:64910690c574	1024	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
AnnaBridge	145:64910690c574	1025	* @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
AnnaBridge	145:64910690c574	1026	* @retval None
AnnaBridge	145:64910690c574	1027	*/
AnnaBridge	145:64910690c574	1028	__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
AnnaBridge	145:64910690c574	1029	{
AnnaBridge	145:64910690c574	1030	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
AnnaBridge	145:64910690c574	1031	}
AnnaBridge	145:64910690c574	1032
AnnaBridge	145:64910690c574	1033	/**
AnnaBridge	145:64910690c574	1034	* @brief Get the system clock source
AnnaBridge	145:64910690c574	1035	* @rmtoll CFGR SWS LL_RCC_GetSysClkSource
AnnaBridge	145:64910690c574	1036	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1037	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
AnnaBridge	145:64910690c574	1038	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
AnnaBridge	145:64910690c574	1039	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
AnnaBridge	145:64910690c574	1040	*/
AnnaBridge	145:64910690c574	1041	__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
AnnaBridge	145:64910690c574	1042	{
AnnaBridge	145:64910690c574	1043	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
AnnaBridge	145:64910690c574	1044	}
AnnaBridge	145:64910690c574	1045
AnnaBridge	145:64910690c574	1046	/**
AnnaBridge	145:64910690c574	1047	* @brief Set AHB prescaler
AnnaBridge	145:64910690c574	1048	* @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
AnnaBridge	145:64910690c574	1049	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1050	* @arg @ref LL_RCC_SYSCLK_DIV_1
AnnaBridge	145:64910690c574	1051	* @arg @ref LL_RCC_SYSCLK_DIV_2
AnnaBridge	145:64910690c574	1052	* @arg @ref LL_RCC_SYSCLK_DIV_4
AnnaBridge	145:64910690c574	1053	* @arg @ref LL_RCC_SYSCLK_DIV_8
AnnaBridge	145:64910690c574	1054	* @arg @ref LL_RCC_SYSCLK_DIV_16
AnnaBridge	145:64910690c574	1055	* @arg @ref LL_RCC_SYSCLK_DIV_64
AnnaBridge	145:64910690c574	1056	* @arg @ref LL_RCC_SYSCLK_DIV_128
AnnaBridge	145:64910690c574	1057	* @arg @ref LL_RCC_SYSCLK_DIV_256
AnnaBridge	145:64910690c574	1058	* @arg @ref LL_RCC_SYSCLK_DIV_512
AnnaBridge	145:64910690c574	1059	* @retval None
AnnaBridge	145:64910690c574	1060	*/
AnnaBridge	145:64910690c574	1061	__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
AnnaBridge	145:64910690c574	1062	{
AnnaBridge	145:64910690c574	1063	MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
AnnaBridge	145:64910690c574	1064	}
AnnaBridge	145:64910690c574	1065
AnnaBridge	145:64910690c574	1066	/**
AnnaBridge	145:64910690c574	1067	* @brief Set APB1 prescaler
AnnaBridge	145:64910690c574	1068	* @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
AnnaBridge	145:64910690c574	1069	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1070	* @arg @ref LL_RCC_APB1_DIV_1
AnnaBridge	145:64910690c574	1071	* @arg @ref LL_RCC_APB1_DIV_2
AnnaBridge	145:64910690c574	1072	* @arg @ref LL_RCC_APB1_DIV_4
AnnaBridge	145:64910690c574	1073	* @arg @ref LL_RCC_APB1_DIV_8
AnnaBridge	145:64910690c574	1074	* @arg @ref LL_RCC_APB1_DIV_16
AnnaBridge	145:64910690c574	1075	* @retval None
AnnaBridge	145:64910690c574	1076	*/
AnnaBridge	145:64910690c574	1077	__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
AnnaBridge	145:64910690c574	1078	{
AnnaBridge	145:64910690c574	1079	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
AnnaBridge	145:64910690c574	1080	}
AnnaBridge	145:64910690c574	1081
AnnaBridge	145:64910690c574	1082	/**
AnnaBridge	145:64910690c574	1083	* @brief Set APB2 prescaler
AnnaBridge	145:64910690c574	1084	* @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
AnnaBridge	145:64910690c574	1085	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1086	* @arg @ref LL_RCC_APB2_DIV_1
AnnaBridge	145:64910690c574	1087	* @arg @ref LL_RCC_APB2_DIV_2
AnnaBridge	145:64910690c574	1088	* @arg @ref LL_RCC_APB2_DIV_4
AnnaBridge	145:64910690c574	1089	* @arg @ref LL_RCC_APB2_DIV_8
AnnaBridge	145:64910690c574	1090	* @arg @ref LL_RCC_APB2_DIV_16
AnnaBridge	145:64910690c574	1091	* @retval None
AnnaBridge	145:64910690c574	1092	*/
AnnaBridge	145:64910690c574	1093	__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
AnnaBridge	145:64910690c574	1094	{
AnnaBridge	145:64910690c574	1095	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
AnnaBridge	145:64910690c574	1096	}
AnnaBridge	145:64910690c574	1097
AnnaBridge	145:64910690c574	1098	/**
AnnaBridge	145:64910690c574	1099	* @brief Get AHB prescaler
AnnaBridge	145:64910690c574	1100	* @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
AnnaBridge	145:64910690c574	1101	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1102	* @arg @ref LL_RCC_SYSCLK_DIV_1
AnnaBridge	145:64910690c574	1103	* @arg @ref LL_RCC_SYSCLK_DIV_2
AnnaBridge	145:64910690c574	1104	* @arg @ref LL_RCC_SYSCLK_DIV_4
AnnaBridge	145:64910690c574	1105	* @arg @ref LL_RCC_SYSCLK_DIV_8
AnnaBridge	145:64910690c574	1106	* @arg @ref LL_RCC_SYSCLK_DIV_16
AnnaBridge	145:64910690c574	1107	* @arg @ref LL_RCC_SYSCLK_DIV_64
AnnaBridge	145:64910690c574	1108	* @arg @ref LL_RCC_SYSCLK_DIV_128
AnnaBridge	145:64910690c574	1109	* @arg @ref LL_RCC_SYSCLK_DIV_256
AnnaBridge	145:64910690c574	1110	* @arg @ref LL_RCC_SYSCLK_DIV_512
AnnaBridge	145:64910690c574	1111	*/
AnnaBridge	145:64910690c574	1112	__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
AnnaBridge	145:64910690c574	1113	{
AnnaBridge	145:64910690c574	1114	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
AnnaBridge	145:64910690c574	1115	}
AnnaBridge	145:64910690c574	1116
AnnaBridge	145:64910690c574	1117	/**
AnnaBridge	145:64910690c574	1118	* @brief Get APB1 prescaler
AnnaBridge	145:64910690c574	1119	* @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
AnnaBridge	145:64910690c574	1120	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1121	* @arg @ref LL_RCC_APB1_DIV_1
AnnaBridge	145:64910690c574	1122	* @arg @ref LL_RCC_APB1_DIV_2
AnnaBridge	145:64910690c574	1123	* @arg @ref LL_RCC_APB1_DIV_4
AnnaBridge	145:64910690c574	1124	* @arg @ref LL_RCC_APB1_DIV_8
AnnaBridge	145:64910690c574	1125	* @arg @ref LL_RCC_APB1_DIV_16
AnnaBridge	145:64910690c574	1126	*/
AnnaBridge	145:64910690c574	1127	__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
AnnaBridge	145:64910690c574	1128	{
AnnaBridge	145:64910690c574	1129	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
AnnaBridge	145:64910690c574	1130	}
AnnaBridge	145:64910690c574	1131
AnnaBridge	145:64910690c574	1132	/**
AnnaBridge	145:64910690c574	1133	* @brief Get APB2 prescaler
AnnaBridge	145:64910690c574	1134	* @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
AnnaBridge	145:64910690c574	1135	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1136	* @arg @ref LL_RCC_APB2_DIV_1
AnnaBridge	145:64910690c574	1137	* @arg @ref LL_RCC_APB2_DIV_2
AnnaBridge	145:64910690c574	1138	* @arg @ref LL_RCC_APB2_DIV_4
AnnaBridge	145:64910690c574	1139	* @arg @ref LL_RCC_APB2_DIV_8
AnnaBridge	145:64910690c574	1140	* @arg @ref LL_RCC_APB2_DIV_16
AnnaBridge	145:64910690c574	1141	*/
AnnaBridge	145:64910690c574	1142	__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
AnnaBridge	145:64910690c574	1143	{
AnnaBridge	145:64910690c574	1144	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
AnnaBridge	145:64910690c574	1145	}
AnnaBridge	145:64910690c574	1146
AnnaBridge	145:64910690c574	1147	/**
AnnaBridge	145:64910690c574	1148	* @}
AnnaBridge	145:64910690c574	1149	*/
AnnaBridge	145:64910690c574	1150
AnnaBridge	145:64910690c574	1151	/** @defgroup RCC_LL_EF_MCO MCO
AnnaBridge	145:64910690c574	1152	* @{
AnnaBridge	145:64910690c574	1153	*/
AnnaBridge	145:64910690c574	1154
AnnaBridge	145:64910690c574	1155	/**
AnnaBridge	145:64910690c574	1156	* @brief Configure MCOx
AnnaBridge	145:64910690c574	1157	* @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n
AnnaBridge	145:64910690c574	1158	* CFGR MCO1PRE LL_RCC_ConfigMCO\n
AnnaBridge	145:64910690c574	1159	* CFGR MCO2 LL_RCC_ConfigMCO\n
AnnaBridge	145:64910690c574	1160	* CFGR MCO2PRE LL_RCC_ConfigMCO
AnnaBridge	145:64910690c574	1161	* @param MCOxSource This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1162	* @arg @ref LL_RCC_MCO1SOURCE_HSI
AnnaBridge	145:64910690c574	1163	* @arg @ref LL_RCC_MCO1SOURCE_LSE
AnnaBridge	145:64910690c574	1164	* @arg @ref LL_RCC_MCO1SOURCE_HSE
AnnaBridge	145:64910690c574	1165	* @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
AnnaBridge	145:64910690c574	1166	* @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
AnnaBridge	145:64910690c574	1167	* @arg @ref LL_RCC_MCO2SOURCE_PLLI2S
AnnaBridge	145:64910690c574	1168	* @arg @ref LL_RCC_MCO2SOURCE_HSE
AnnaBridge	145:64910690c574	1169	* @arg @ref LL_RCC_MCO2SOURCE_PLLCLK
AnnaBridge	145:64910690c574	1170	* @param MCOxPrescaler This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1171	* @arg @ref LL_RCC_MCO1_DIV_1
AnnaBridge	145:64910690c574	1172	* @arg @ref LL_RCC_MCO1_DIV_2
AnnaBridge	145:64910690c574	1173	* @arg @ref LL_RCC_MCO1_DIV_3
AnnaBridge	145:64910690c574	1174	* @arg @ref LL_RCC_MCO1_DIV_4
AnnaBridge	145:64910690c574	1175	* @arg @ref LL_RCC_MCO1_DIV_5
AnnaBridge	145:64910690c574	1176	* @arg @ref LL_RCC_MCO2_DIV_1
AnnaBridge	145:64910690c574	1177	* @arg @ref LL_RCC_MCO2_DIV_2
AnnaBridge	145:64910690c574	1178	* @arg @ref LL_RCC_MCO2_DIV_3
AnnaBridge	145:64910690c574	1179	* @arg @ref LL_RCC_MCO2_DIV_4
AnnaBridge	145:64910690c574	1180	* @arg @ref LL_RCC_MCO2_DIV_5
AnnaBridge	145:64910690c574	1181	* @retval None
AnnaBridge	145:64910690c574	1182	*/
AnnaBridge	145:64910690c574	1183	__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
AnnaBridge	145:64910690c574	1184	{
AnnaBridge	145:64910690c574	1185	MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) \| (MCOxPrescaler & 0xFFFF0000U), (MCOxSource << 16U) \| (MCOxPrescaler << 16U));
AnnaBridge	145:64910690c574	1186	}
AnnaBridge	145:64910690c574	1187
AnnaBridge	145:64910690c574	1188	/**
AnnaBridge	145:64910690c574	1189	* @}
AnnaBridge	145:64910690c574	1190	*/
AnnaBridge	145:64910690c574	1191
AnnaBridge	145:64910690c574	1192	/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
AnnaBridge	145:64910690c574	1193	* @{
AnnaBridge	145:64910690c574	1194	*/
AnnaBridge	145:64910690c574	1195
AnnaBridge	145:64910690c574	1196	/**
AnnaBridge	145:64910690c574	1197	* @brief Configure I2S clock source
AnnaBridge	145:64910690c574	1198	* @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource
AnnaBridge	145:64910690c574	1199	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1200	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S
AnnaBridge	145:64910690c574	1201	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
AnnaBridge	145:64910690c574	1202	* @retval None
AnnaBridge	145:64910690c574	1203	*/
AnnaBridge	145:64910690c574	1204	__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source)
AnnaBridge	145:64910690c574	1205	{
AnnaBridge	145:64910690c574	1206	MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source);
AnnaBridge	145:64910690c574	1207	}
AnnaBridge	145:64910690c574	1208
AnnaBridge	145:64910690c574	1209	/**
AnnaBridge	145:64910690c574	1210	* @brief Get I2S Clock Source
AnnaBridge	145:64910690c574	1211	* @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource
AnnaBridge	145:64910690c574	1212	* @param I2Sx This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1213	* @arg @ref LL_RCC_I2S1_CLKSOURCE
AnnaBridge	145:64910690c574	1214	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1215	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S
AnnaBridge	145:64910690c574	1216	* @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
AnnaBridge	145:64910690c574	1217	*/
AnnaBridge	145:64910690c574	1218	__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
AnnaBridge	145:64910690c574	1219	{
AnnaBridge	145:64910690c574	1220	return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));
AnnaBridge	145:64910690c574	1221	}
AnnaBridge	145:64910690c574	1222
AnnaBridge	145:64910690c574	1223	/**
AnnaBridge	145:64910690c574	1224	* @}
AnnaBridge	145:64910690c574	1225	*/
AnnaBridge	145:64910690c574	1226
AnnaBridge	145:64910690c574	1227	/** @defgroup RCC_LL_EF_RTC RTC
AnnaBridge	145:64910690c574	1228	* @{
AnnaBridge	145:64910690c574	1229	*/
AnnaBridge	145:64910690c574	1230
AnnaBridge	145:64910690c574	1231	/**
AnnaBridge	145:64910690c574	1232	* @brief Set RTC Clock Source
AnnaBridge	145:64910690c574	1233	* @note Once the RTC clock source has been selected, it cannot be changed anymore unless
AnnaBridge	145:64910690c574	1234	* the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
AnnaBridge	145:64910690c574	1235	* set). The BDRST bit can be used to reset them.
AnnaBridge	145:64910690c574	1236	* @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
AnnaBridge	145:64910690c574	1237	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1238	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
AnnaBridge	145:64910690c574	1239	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
AnnaBridge	145:64910690c574	1240	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
AnnaBridge	145:64910690c574	1241	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
AnnaBridge	145:64910690c574	1242	* @retval None
AnnaBridge	145:64910690c574	1243	*/
AnnaBridge	145:64910690c574	1244	__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
AnnaBridge	145:64910690c574	1245	{
AnnaBridge	145:64910690c574	1246	MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
AnnaBridge	145:64910690c574	1247	}
AnnaBridge	145:64910690c574	1248
AnnaBridge	145:64910690c574	1249	/**
AnnaBridge	145:64910690c574	1250	* @brief Get RTC Clock Source
AnnaBridge	145:64910690c574	1251	* @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
AnnaBridge	145:64910690c574	1252	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1253	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
AnnaBridge	145:64910690c574	1254	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
AnnaBridge	145:64910690c574	1255	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
AnnaBridge	145:64910690c574	1256	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
AnnaBridge	145:64910690c574	1257	*/
AnnaBridge	145:64910690c574	1258	__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
AnnaBridge	145:64910690c574	1259	{
AnnaBridge	145:64910690c574	1260	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
AnnaBridge	145:64910690c574	1261	}
AnnaBridge	145:64910690c574	1262
AnnaBridge	145:64910690c574	1263	/**
AnnaBridge	145:64910690c574	1264	* @brief Enable RTC
AnnaBridge	145:64910690c574	1265	* @rmtoll BDCR RTCEN LL_RCC_EnableRTC
AnnaBridge	145:64910690c574	1266	* @retval None
AnnaBridge	145:64910690c574	1267	*/
AnnaBridge	145:64910690c574	1268	__STATIC_INLINE void LL_RCC_EnableRTC(void)
AnnaBridge	145:64910690c574	1269	{
AnnaBridge	145:64910690c574	1270	SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
AnnaBridge	145:64910690c574	1271	}
AnnaBridge	145:64910690c574	1272
AnnaBridge	145:64910690c574	1273	/**
AnnaBridge	145:64910690c574	1274	* @brief Disable RTC
AnnaBridge	145:64910690c574	1275	* @rmtoll BDCR RTCEN LL_RCC_DisableRTC
AnnaBridge	145:64910690c574	1276	* @retval None
AnnaBridge	145:64910690c574	1277	*/
AnnaBridge	145:64910690c574	1278	__STATIC_INLINE void LL_RCC_DisableRTC(void)
AnnaBridge	145:64910690c574	1279	{
AnnaBridge	145:64910690c574	1280	CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
AnnaBridge	145:64910690c574	1281	}
AnnaBridge	145:64910690c574	1282
AnnaBridge	145:64910690c574	1283	/**
AnnaBridge	145:64910690c574	1284	* @brief Check if RTC has been enabled or not
AnnaBridge	145:64910690c574	1285	* @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
AnnaBridge	145:64910690c574	1286	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1287	*/
AnnaBridge	145:64910690c574	1288	__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
AnnaBridge	145:64910690c574	1289	{
AnnaBridge	145:64910690c574	1290	return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
AnnaBridge	145:64910690c574	1291	}
AnnaBridge	145:64910690c574	1292
AnnaBridge	145:64910690c574	1293	/**
AnnaBridge	145:64910690c574	1294	* @brief Force the Backup domain reset
AnnaBridge	145:64910690c574	1295	* @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
AnnaBridge	145:64910690c574	1296	* @retval None
AnnaBridge	145:64910690c574	1297	*/
AnnaBridge	145:64910690c574	1298	__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
AnnaBridge	145:64910690c574	1299	{
AnnaBridge	145:64910690c574	1300	SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
AnnaBridge	145:64910690c574	1301	}
AnnaBridge	145:64910690c574	1302
AnnaBridge	145:64910690c574	1303	/**
AnnaBridge	145:64910690c574	1304	* @brief Release the Backup domain reset
AnnaBridge	145:64910690c574	1305	* @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
AnnaBridge	145:64910690c574	1306	* @retval None
AnnaBridge	145:64910690c574	1307	*/
AnnaBridge	145:64910690c574	1308	__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
AnnaBridge	145:64910690c574	1309	{
AnnaBridge	145:64910690c574	1310	CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
AnnaBridge	145:64910690c574	1311	}
AnnaBridge	145:64910690c574	1312
AnnaBridge	145:64910690c574	1313	/**
AnnaBridge	145:64910690c574	1314	* @brief Set HSE Prescalers for RTC Clock
AnnaBridge	145:64910690c574	1315	* @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler
AnnaBridge	145:64910690c574	1316	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1317	* @arg @ref LL_RCC_RTC_NOCLOCK
AnnaBridge	145:64910690c574	1318	* @arg @ref LL_RCC_RTC_HSE_DIV_2
AnnaBridge	145:64910690c574	1319	* @arg @ref LL_RCC_RTC_HSE_DIV_3
AnnaBridge	145:64910690c574	1320	* @arg @ref LL_RCC_RTC_HSE_DIV_4
AnnaBridge	145:64910690c574	1321	* @arg @ref LL_RCC_RTC_HSE_DIV_5
AnnaBridge	145:64910690c574	1322	* @arg @ref LL_RCC_RTC_HSE_DIV_6
AnnaBridge	145:64910690c574	1323	* @arg @ref LL_RCC_RTC_HSE_DIV_7
AnnaBridge	145:64910690c574	1324	* @arg @ref LL_RCC_RTC_HSE_DIV_8
AnnaBridge	145:64910690c574	1325	* @arg @ref LL_RCC_RTC_HSE_DIV_9
AnnaBridge	145:64910690c574	1326	* @arg @ref LL_RCC_RTC_HSE_DIV_10
AnnaBridge	145:64910690c574	1327	* @arg @ref LL_RCC_RTC_HSE_DIV_11
AnnaBridge	145:64910690c574	1328	* @arg @ref LL_RCC_RTC_HSE_DIV_12
AnnaBridge	145:64910690c574	1329	* @arg @ref LL_RCC_RTC_HSE_DIV_13
AnnaBridge	145:64910690c574	1330	* @arg @ref LL_RCC_RTC_HSE_DIV_14
AnnaBridge	145:64910690c574	1331	* @arg @ref LL_RCC_RTC_HSE_DIV_15
AnnaBridge	145:64910690c574	1332	* @arg @ref LL_RCC_RTC_HSE_DIV_16
AnnaBridge	145:64910690c574	1333	* @arg @ref LL_RCC_RTC_HSE_DIV_17
AnnaBridge	145:64910690c574	1334	* @arg @ref LL_RCC_RTC_HSE_DIV_18
AnnaBridge	145:64910690c574	1335	* @arg @ref LL_RCC_RTC_HSE_DIV_19
AnnaBridge	145:64910690c574	1336	* @arg @ref LL_RCC_RTC_HSE_DIV_20
AnnaBridge	145:64910690c574	1337	* @arg @ref LL_RCC_RTC_HSE_DIV_21
AnnaBridge	145:64910690c574	1338	* @arg @ref LL_RCC_RTC_HSE_DIV_22
AnnaBridge	145:64910690c574	1339	* @arg @ref LL_RCC_RTC_HSE_DIV_23
AnnaBridge	145:64910690c574	1340	* @arg @ref LL_RCC_RTC_HSE_DIV_24
AnnaBridge	145:64910690c574	1341	* @arg @ref LL_RCC_RTC_HSE_DIV_25
AnnaBridge	145:64910690c574	1342	* @arg @ref LL_RCC_RTC_HSE_DIV_26
AnnaBridge	145:64910690c574	1343	* @arg @ref LL_RCC_RTC_HSE_DIV_27
AnnaBridge	145:64910690c574	1344	* @arg @ref LL_RCC_RTC_HSE_DIV_28
AnnaBridge	145:64910690c574	1345	* @arg @ref LL_RCC_RTC_HSE_DIV_29
AnnaBridge	145:64910690c574	1346	* @arg @ref LL_RCC_RTC_HSE_DIV_30
AnnaBridge	145:64910690c574	1347	* @arg @ref LL_RCC_RTC_HSE_DIV_31
AnnaBridge	145:64910690c574	1348	* @retval None
AnnaBridge	145:64910690c574	1349	*/
AnnaBridge	145:64910690c574	1350	__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
AnnaBridge	145:64910690c574	1351	{
AnnaBridge	145:64910690c574	1352	MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
AnnaBridge	145:64910690c574	1353	}
AnnaBridge	145:64910690c574	1354
AnnaBridge	145:64910690c574	1355	/**
AnnaBridge	145:64910690c574	1356	* @brief Get HSE Prescalers for RTC Clock
AnnaBridge	145:64910690c574	1357	* @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler
AnnaBridge	145:64910690c574	1358	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1359	* @arg @ref LL_RCC_RTC_NOCLOCK
AnnaBridge	145:64910690c574	1360	* @arg @ref LL_RCC_RTC_HSE_DIV_2
AnnaBridge	145:64910690c574	1361	* @arg @ref LL_RCC_RTC_HSE_DIV_3
AnnaBridge	145:64910690c574	1362	* @arg @ref LL_RCC_RTC_HSE_DIV_4
AnnaBridge	145:64910690c574	1363	* @arg @ref LL_RCC_RTC_HSE_DIV_5
AnnaBridge	145:64910690c574	1364	* @arg @ref LL_RCC_RTC_HSE_DIV_6
AnnaBridge	145:64910690c574	1365	* @arg @ref LL_RCC_RTC_HSE_DIV_7
AnnaBridge	145:64910690c574	1366	* @arg @ref LL_RCC_RTC_HSE_DIV_8
AnnaBridge	145:64910690c574	1367	* @arg @ref LL_RCC_RTC_HSE_DIV_9
AnnaBridge	145:64910690c574	1368	* @arg @ref LL_RCC_RTC_HSE_DIV_10
AnnaBridge	145:64910690c574	1369	* @arg @ref LL_RCC_RTC_HSE_DIV_11
AnnaBridge	145:64910690c574	1370	* @arg @ref LL_RCC_RTC_HSE_DIV_12
AnnaBridge	145:64910690c574	1371	* @arg @ref LL_RCC_RTC_HSE_DIV_13
AnnaBridge	145:64910690c574	1372	* @arg @ref LL_RCC_RTC_HSE_DIV_14
AnnaBridge	145:64910690c574	1373	* @arg @ref LL_RCC_RTC_HSE_DIV_15
AnnaBridge	145:64910690c574	1374	* @arg @ref LL_RCC_RTC_HSE_DIV_16
AnnaBridge	145:64910690c574	1375	* @arg @ref LL_RCC_RTC_HSE_DIV_17
AnnaBridge	145:64910690c574	1376	* @arg @ref LL_RCC_RTC_HSE_DIV_18
AnnaBridge	145:64910690c574	1377	* @arg @ref LL_RCC_RTC_HSE_DIV_19
AnnaBridge	145:64910690c574	1378	* @arg @ref LL_RCC_RTC_HSE_DIV_20
AnnaBridge	145:64910690c574	1379	* @arg @ref LL_RCC_RTC_HSE_DIV_21
AnnaBridge	145:64910690c574	1380	* @arg @ref LL_RCC_RTC_HSE_DIV_22
AnnaBridge	145:64910690c574	1381	* @arg @ref LL_RCC_RTC_HSE_DIV_23
AnnaBridge	145:64910690c574	1382	* @arg @ref LL_RCC_RTC_HSE_DIV_24
AnnaBridge	145:64910690c574	1383	* @arg @ref LL_RCC_RTC_HSE_DIV_25
AnnaBridge	145:64910690c574	1384	* @arg @ref LL_RCC_RTC_HSE_DIV_26
AnnaBridge	145:64910690c574	1385	* @arg @ref LL_RCC_RTC_HSE_DIV_27
AnnaBridge	145:64910690c574	1386	* @arg @ref LL_RCC_RTC_HSE_DIV_28
AnnaBridge	145:64910690c574	1387	* @arg @ref LL_RCC_RTC_HSE_DIV_29
AnnaBridge	145:64910690c574	1388	* @arg @ref LL_RCC_RTC_HSE_DIV_30
AnnaBridge	145:64910690c574	1389	* @arg @ref LL_RCC_RTC_HSE_DIV_31
AnnaBridge	145:64910690c574	1390	*/
AnnaBridge	145:64910690c574	1391	__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
AnnaBridge	145:64910690c574	1392	{
AnnaBridge	145:64910690c574	1393	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
AnnaBridge	145:64910690c574	1394	}
AnnaBridge	145:64910690c574	1395
AnnaBridge	145:64910690c574	1396	/**
AnnaBridge	145:64910690c574	1397	* @}
AnnaBridge	145:64910690c574	1398	*/
AnnaBridge	145:64910690c574	1399
AnnaBridge	145:64910690c574	1400	/** @defgroup RCC_LL_EF_PLL PLL
AnnaBridge	145:64910690c574	1401	* @{
AnnaBridge	145:64910690c574	1402	*/
AnnaBridge	145:64910690c574	1403
AnnaBridge	145:64910690c574	1404	/**
AnnaBridge	145:64910690c574	1405	* @brief Enable PLL
AnnaBridge	145:64910690c574	1406	* @rmtoll CR PLLON LL_RCC_PLL_Enable
AnnaBridge	145:64910690c574	1407	* @retval None
AnnaBridge	145:64910690c574	1408	*/
AnnaBridge	145:64910690c574	1409	__STATIC_INLINE void LL_RCC_PLL_Enable(void)
AnnaBridge	145:64910690c574	1410	{
AnnaBridge	145:64910690c574	1411	SET_BIT(RCC->CR, RCC_CR_PLLON);
AnnaBridge	145:64910690c574	1412	}
AnnaBridge	145:64910690c574	1413
AnnaBridge	145:64910690c574	1414	/**
AnnaBridge	145:64910690c574	1415	* @brief Disable PLL
AnnaBridge	145:64910690c574	1416	* @note Cannot be disabled if the PLL clock is used as the system clock
AnnaBridge	145:64910690c574	1417	* @rmtoll CR PLLON LL_RCC_PLL_Disable
AnnaBridge	145:64910690c574	1418	* @retval None
AnnaBridge	145:64910690c574	1419	*/
AnnaBridge	145:64910690c574	1420	__STATIC_INLINE void LL_RCC_PLL_Disable(void)
AnnaBridge	145:64910690c574	1421	{
AnnaBridge	145:64910690c574	1422	CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
AnnaBridge	145:64910690c574	1423	}
AnnaBridge	145:64910690c574	1424
AnnaBridge	145:64910690c574	1425	/**
AnnaBridge	145:64910690c574	1426	* @brief Check if PLL Ready
AnnaBridge	145:64910690c574	1427	* @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
AnnaBridge	145:64910690c574	1428	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1429	*/
AnnaBridge	145:64910690c574	1430	__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
AnnaBridge	145:64910690c574	1431	{
AnnaBridge	145:64910690c574	1432	return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
AnnaBridge	145:64910690c574	1433	}
AnnaBridge	145:64910690c574	1434
AnnaBridge	145:64910690c574	1435	/**
AnnaBridge	145:64910690c574	1436	* @brief Configure PLL used for SYSCLK Domain
AnnaBridge	145:64910690c574	1437	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	145:64910690c574	1438	* PLLI2S are disabled
AnnaBridge	145:64910690c574	1439	* @note PLLN/PLLP can be written only when PLL is disabled
AnnaBridge	145:64910690c574	1440	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
AnnaBridge	145:64910690c574	1441	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
AnnaBridge	145:64910690c574	1442	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
AnnaBridge	145:64910690c574	1443	* PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SYS
AnnaBridge	145:64910690c574	1444	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1445	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	145:64910690c574	1446	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	145:64910690c574	1447	* @param PLLM This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1448	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	145:64910690c574	1449	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	145:64910690c574	1450	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	145:64910690c574	1451	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	145:64910690c574	1452	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	145:64910690c574	1453	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	145:64910690c574	1454	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	145:64910690c574	1455	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	145:64910690c574	1456	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	145:64910690c574	1457	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	145:64910690c574	1458	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	145:64910690c574	1459	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	145:64910690c574	1460	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	145:64910690c574	1461	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	145:64910690c574	1462	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	145:64910690c574	1463	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	145:64910690c574	1464	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	145:64910690c574	1465	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	145:64910690c574	1466	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	145:64910690c574	1467	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	145:64910690c574	1468	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	145:64910690c574	1469	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	145:64910690c574	1470	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	145:64910690c574	1471	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	145:64910690c574	1472	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	145:64910690c574	1473	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	145:64910690c574	1474	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	145:64910690c574	1475	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	145:64910690c574	1476	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	145:64910690c574	1477	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	145:64910690c574	1478	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	145:64910690c574	1479	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	145:64910690c574	1480	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	145:64910690c574	1481	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	145:64910690c574	1482	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	145:64910690c574	1483	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	145:64910690c574	1484	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	145:64910690c574	1485	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	145:64910690c574	1486	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	145:64910690c574	1487	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	145:64910690c574	1488	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	145:64910690c574	1489	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	145:64910690c574	1490	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	145:64910690c574	1491	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	145:64910690c574	1492	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	145:64910690c574	1493	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	145:64910690c574	1494	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	145:64910690c574	1495	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	145:64910690c574	1496	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	145:64910690c574	1497	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	145:64910690c574	1498	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	145:64910690c574	1499	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	145:64910690c574	1500	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	145:64910690c574	1501	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	145:64910690c574	1502	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	145:64910690c574	1503	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	145:64910690c574	1504	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	145:64910690c574	1505	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	145:64910690c574	1506	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	145:64910690c574	1507	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	145:64910690c574	1508	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	145:64910690c574	1509	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	145:64910690c574	1510	* @param PLLN Between 192 and 432
AnnaBridge	145:64910690c574	1511	* @param PLLP This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1512	* @arg @ref LL_RCC_PLLP_DIV_2
AnnaBridge	145:64910690c574	1513	* @arg @ref LL_RCC_PLLP_DIV_4
AnnaBridge	145:64910690c574	1514	* @arg @ref LL_RCC_PLLP_DIV_6
AnnaBridge	145:64910690c574	1515	* @arg @ref LL_RCC_PLLP_DIV_8
AnnaBridge	145:64910690c574	1516	* @retval None
AnnaBridge	145:64910690c574	1517	*/
AnnaBridge	145:64910690c574	1518	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
AnnaBridge	145:64910690c574	1519	{
AnnaBridge	145:64910690c574	1520	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLP,
AnnaBridge	145:64910690c574	1521	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLP);
AnnaBridge	145:64910690c574	1522	}
AnnaBridge	145:64910690c574	1523
AnnaBridge	145:64910690c574	1524	/**
AnnaBridge	145:64910690c574	1525	* @brief Configure PLL used for 48Mhz domain clock
AnnaBridge	145:64910690c574	1526	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	145:64910690c574	1527	* PLLI2S are disabled
AnnaBridge	145:64910690c574	1528	* @note PLLN/PLLQ can be written only when PLL is disabled
AnnaBridge	145:64910690c574	1529	* @note This can be selected for USB, RNG, SDIO
AnnaBridge	145:64910690c574	1530	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
AnnaBridge	145:64910690c574	1531	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
AnnaBridge	145:64910690c574	1532	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
AnnaBridge	145:64910690c574	1533	* PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
AnnaBridge	145:64910690c574	1534	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1535	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	145:64910690c574	1536	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	145:64910690c574	1537	* @param PLLM This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1538	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	145:64910690c574	1539	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	145:64910690c574	1540	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	145:64910690c574	1541	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	145:64910690c574	1542	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	145:64910690c574	1543	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	145:64910690c574	1544	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	145:64910690c574	1545	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	145:64910690c574	1546	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	145:64910690c574	1547	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	145:64910690c574	1548	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	145:64910690c574	1549	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	145:64910690c574	1550	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	145:64910690c574	1551	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	145:64910690c574	1552	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	145:64910690c574	1553	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	145:64910690c574	1554	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	145:64910690c574	1555	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	145:64910690c574	1556	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	145:64910690c574	1557	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	145:64910690c574	1558	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	145:64910690c574	1559	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	145:64910690c574	1560	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	145:64910690c574	1561	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	145:64910690c574	1562	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	145:64910690c574	1563	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	145:64910690c574	1564	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	145:64910690c574	1565	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	145:64910690c574	1566	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	145:64910690c574	1567	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	145:64910690c574	1568	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	145:64910690c574	1569	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	145:64910690c574	1570	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	145:64910690c574	1571	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	145:64910690c574	1572	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	145:64910690c574	1573	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	145:64910690c574	1574	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	145:64910690c574	1575	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	145:64910690c574	1576	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	145:64910690c574	1577	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	145:64910690c574	1578	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	145:64910690c574	1579	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	145:64910690c574	1580	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	145:64910690c574	1581	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	145:64910690c574	1582	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	145:64910690c574	1583	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	145:64910690c574	1584	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	145:64910690c574	1585	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	145:64910690c574	1586	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	145:64910690c574	1587	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	145:64910690c574	1588	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	145:64910690c574	1589	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	145:64910690c574	1590	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	145:64910690c574	1591	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	145:64910690c574	1592	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	145:64910690c574	1593	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	145:64910690c574	1594	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	145:64910690c574	1595	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	145:64910690c574	1596	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	145:64910690c574	1597	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	145:64910690c574	1598	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	145:64910690c574	1599	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	145:64910690c574	1600	* @param PLLN Between 192 and 432
AnnaBridge	145:64910690c574	1601	* @param PLLQ This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1602	* @arg @ref LL_RCC_PLLQ_DIV_2
AnnaBridge	145:64910690c574	1603	* @arg @ref LL_RCC_PLLQ_DIV_3
AnnaBridge	145:64910690c574	1604	* @arg @ref LL_RCC_PLLQ_DIV_4
AnnaBridge	145:64910690c574	1605	* @arg @ref LL_RCC_PLLQ_DIV_5
AnnaBridge	145:64910690c574	1606	* @arg @ref LL_RCC_PLLQ_DIV_6
AnnaBridge	145:64910690c574	1607	* @arg @ref LL_RCC_PLLQ_DIV_7
AnnaBridge	145:64910690c574	1608	* @arg @ref LL_RCC_PLLQ_DIV_8
AnnaBridge	145:64910690c574	1609	* @arg @ref LL_RCC_PLLQ_DIV_9
AnnaBridge	145:64910690c574	1610	* @arg @ref LL_RCC_PLLQ_DIV_10
AnnaBridge	145:64910690c574	1611	* @arg @ref LL_RCC_PLLQ_DIV_11
AnnaBridge	145:64910690c574	1612	* @arg @ref LL_RCC_PLLQ_DIV_12
AnnaBridge	145:64910690c574	1613	* @arg @ref LL_RCC_PLLQ_DIV_13
AnnaBridge	145:64910690c574	1614	* @arg @ref LL_RCC_PLLQ_DIV_14
AnnaBridge	145:64910690c574	1615	* @arg @ref LL_RCC_PLLQ_DIV_15
AnnaBridge	145:64910690c574	1616	* @retval None
AnnaBridge	145:64910690c574	1617	*/
AnnaBridge	145:64910690c574	1618	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
AnnaBridge	145:64910690c574	1619	{
AnnaBridge	145:64910690c574	1620	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLQ,
AnnaBridge	145:64910690c574	1621	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLQ);
AnnaBridge	145:64910690c574	1622	}
AnnaBridge	145:64910690c574	1623
AnnaBridge	145:64910690c574	1624	/**
AnnaBridge	145:64910690c574	1625	* @brief Get Main PLL multiplication factor for VCO
AnnaBridge	145:64910690c574	1626	* @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
AnnaBridge	145:64910690c574	1627	* @retval Between 192 and 432
AnnaBridge	145:64910690c574	1628	*/
AnnaBridge	145:64910690c574	1629	__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
AnnaBridge	145:64910690c574	1630	{
AnnaBridge	145:64910690c574	1631	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
AnnaBridge	145:64910690c574	1632	}
AnnaBridge	145:64910690c574	1633
AnnaBridge	145:64910690c574	1634	/**
AnnaBridge	145:64910690c574	1635	* @brief Get Main PLL division factor for PLLP
AnnaBridge	145:64910690c574	1636	* @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
AnnaBridge	145:64910690c574	1637	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1638	* @arg @ref LL_RCC_PLLP_DIV_2
AnnaBridge	145:64910690c574	1639	* @arg @ref LL_RCC_PLLP_DIV_4
AnnaBridge	145:64910690c574	1640	* @arg @ref LL_RCC_PLLP_DIV_6
AnnaBridge	145:64910690c574	1641	* @arg @ref LL_RCC_PLLP_DIV_8
AnnaBridge	145:64910690c574	1642	*/
AnnaBridge	145:64910690c574	1643	__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
AnnaBridge	145:64910690c574	1644	{
AnnaBridge	145:64910690c574	1645	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
AnnaBridge	145:64910690c574	1646	}
AnnaBridge	145:64910690c574	1647
AnnaBridge	145:64910690c574	1648	/**
AnnaBridge	145:64910690c574	1649	* @brief Get Main PLL division factor for PLLQ
AnnaBridge	145:64910690c574	1650	* @note used for PLL48MCLK selected for USB, RNG, SDIO (48 MHz clock)
AnnaBridge	145:64910690c574	1651	* @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
AnnaBridge	145:64910690c574	1652	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1653	* @arg @ref LL_RCC_PLLQ_DIV_2
AnnaBridge	145:64910690c574	1654	* @arg @ref LL_RCC_PLLQ_DIV_3
AnnaBridge	145:64910690c574	1655	* @arg @ref LL_RCC_PLLQ_DIV_4
AnnaBridge	145:64910690c574	1656	* @arg @ref LL_RCC_PLLQ_DIV_5
AnnaBridge	145:64910690c574	1657	* @arg @ref LL_RCC_PLLQ_DIV_6
AnnaBridge	145:64910690c574	1658	* @arg @ref LL_RCC_PLLQ_DIV_7
AnnaBridge	145:64910690c574	1659	* @arg @ref LL_RCC_PLLQ_DIV_8
AnnaBridge	145:64910690c574	1660	* @arg @ref LL_RCC_PLLQ_DIV_9
AnnaBridge	145:64910690c574	1661	* @arg @ref LL_RCC_PLLQ_DIV_10
AnnaBridge	145:64910690c574	1662	* @arg @ref LL_RCC_PLLQ_DIV_11
AnnaBridge	145:64910690c574	1663	* @arg @ref LL_RCC_PLLQ_DIV_12
AnnaBridge	145:64910690c574	1664	* @arg @ref LL_RCC_PLLQ_DIV_13
AnnaBridge	145:64910690c574	1665	* @arg @ref LL_RCC_PLLQ_DIV_14
AnnaBridge	145:64910690c574	1666	* @arg @ref LL_RCC_PLLQ_DIV_15
AnnaBridge	145:64910690c574	1667	*/
AnnaBridge	145:64910690c574	1668	__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
AnnaBridge	145:64910690c574	1669	{
AnnaBridge	145:64910690c574	1670	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
AnnaBridge	145:64910690c574	1671	}
AnnaBridge	145:64910690c574	1672
AnnaBridge	145:64910690c574	1673	/**
AnnaBridge	145:64910690c574	1674	* @brief Get the oscillator used as PLL clock source.
AnnaBridge	145:64910690c574	1675	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
AnnaBridge	145:64910690c574	1676	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1677	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	145:64910690c574	1678	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	145:64910690c574	1679	*/
AnnaBridge	145:64910690c574	1680	__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
AnnaBridge	145:64910690c574	1681	{
AnnaBridge	145:64910690c574	1682	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
AnnaBridge	145:64910690c574	1683	}
AnnaBridge	145:64910690c574	1684
AnnaBridge	145:64910690c574	1685	/**
AnnaBridge	145:64910690c574	1686	* @brief Get Division factor for the main PLL and other PLL
AnnaBridge	145:64910690c574	1687	* @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
AnnaBridge	145:64910690c574	1688	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1689	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	145:64910690c574	1690	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	145:64910690c574	1691	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	145:64910690c574	1692	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	145:64910690c574	1693	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	145:64910690c574	1694	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	145:64910690c574	1695	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	145:64910690c574	1696	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	145:64910690c574	1697	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	145:64910690c574	1698	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	145:64910690c574	1699	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	145:64910690c574	1700	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	145:64910690c574	1701	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	145:64910690c574	1702	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	145:64910690c574	1703	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	145:64910690c574	1704	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	145:64910690c574	1705	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	145:64910690c574	1706	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	145:64910690c574	1707	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	145:64910690c574	1708	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	145:64910690c574	1709	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	145:64910690c574	1710	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	145:64910690c574	1711	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	145:64910690c574	1712	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	145:64910690c574	1713	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	145:64910690c574	1714	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	145:64910690c574	1715	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	145:64910690c574	1716	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	145:64910690c574	1717	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	145:64910690c574	1718	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	145:64910690c574	1719	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	145:64910690c574	1720	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	145:64910690c574	1721	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	145:64910690c574	1722	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	145:64910690c574	1723	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	145:64910690c574	1724	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	145:64910690c574	1725	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	145:64910690c574	1726	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	145:64910690c574	1727	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	145:64910690c574	1728	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	145:64910690c574	1729	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	145:64910690c574	1730	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	145:64910690c574	1731	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	145:64910690c574	1732	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	145:64910690c574	1733	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	145:64910690c574	1734	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	145:64910690c574	1735	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	145:64910690c574	1736	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	145:64910690c574	1737	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	145:64910690c574	1738	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	145:64910690c574	1739	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	145:64910690c574	1740	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	145:64910690c574	1741	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	145:64910690c574	1742	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	145:64910690c574	1743	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	145:64910690c574	1744	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	145:64910690c574	1745	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	145:64910690c574	1746	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	145:64910690c574	1747	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	145:64910690c574	1748	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	145:64910690c574	1749	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	145:64910690c574	1750	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	145:64910690c574	1751	*/
AnnaBridge	145:64910690c574	1752	__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
AnnaBridge	145:64910690c574	1753	{
AnnaBridge	145:64910690c574	1754	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
AnnaBridge	145:64910690c574	1755	}
AnnaBridge	145:64910690c574	1756
AnnaBridge	145:64910690c574	1757	/**
AnnaBridge	145:64910690c574	1758	* @brief Configure Spread Spectrum used for PLL
AnnaBridge	145:64910690c574	1759	* @note These bits must be written before enabling PLL
AnnaBridge	145:64910690c574	1760	* @rmtoll SSCGR MODPER LL_RCC_PLL_ConfigSpreadSpectrum\n
AnnaBridge	145:64910690c574	1761	* SSCGR INCSTEP LL_RCC_PLL_ConfigSpreadSpectrum\n
AnnaBridge	145:64910690c574	1762	* SSCGR SPREADSEL LL_RCC_PLL_ConfigSpreadSpectrum
AnnaBridge	145:64910690c574	1763	* @param Mod Between Min_Data=0 and Max_Data=8191
AnnaBridge	145:64910690c574	1764	* @param Inc Between Min_Data=0 and Max_Data=32767
AnnaBridge	145:64910690c574	1765	* @param Sel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1766	* @arg @ref LL_RCC_SPREAD_SELECT_CENTER
AnnaBridge	145:64910690c574	1767	* @arg @ref LL_RCC_SPREAD_SELECT_DOWN
AnnaBridge	145:64910690c574	1768	* @retval None
AnnaBridge	145:64910690c574	1769	*/
AnnaBridge	145:64910690c574	1770	__STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel)
AnnaBridge	145:64910690c574	1771	{
AnnaBridge	145:64910690c574	1772	MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER \| RCC_SSCGR_INCSTEP \| RCC_SSCGR_SPREADSEL, Mod \| (Inc << RCC_SSCGR_INCSTEP_Pos) \| Sel);
AnnaBridge	145:64910690c574	1773	}
AnnaBridge	145:64910690c574	1774
AnnaBridge	145:64910690c574	1775	/**
AnnaBridge	145:64910690c574	1776	* @brief Get Spread Spectrum Modulation Period for PLL
AnnaBridge	145:64910690c574	1777	* @rmtoll SSCGR MODPER LL_RCC_PLL_GetPeriodModulation
AnnaBridge	145:64910690c574	1778	* @retval Between Min_Data=0 and Max_Data=8191
AnnaBridge	145:64910690c574	1779	*/
AnnaBridge	145:64910690c574	1780	__STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void)
AnnaBridge	145:64910690c574	1781	{
AnnaBridge	145:64910690c574	1782	return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER));
AnnaBridge	145:64910690c574	1783	}
AnnaBridge	145:64910690c574	1784
AnnaBridge	145:64910690c574	1785	/**
AnnaBridge	145:64910690c574	1786	* @brief Get Spread Spectrum Incrementation Step for PLL
AnnaBridge	145:64910690c574	1787	* @note Must be written before enabling PLL
AnnaBridge	145:64910690c574	1788	* @rmtoll SSCGR INCSTEP LL_RCC_PLL_GetStepIncrementation
AnnaBridge	145:64910690c574	1789	* @retval Between Min_Data=0 and Max_Data=32767
AnnaBridge	145:64910690c574	1790	*/
AnnaBridge	145:64910690c574	1791	__STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void)
AnnaBridge	145:64910690c574	1792	{
AnnaBridge	145:64910690c574	1793	return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos);
AnnaBridge	145:64910690c574	1794	}
AnnaBridge	145:64910690c574	1795
AnnaBridge	145:64910690c574	1796	/**
AnnaBridge	145:64910690c574	1797	* @brief Get Spread Spectrum Selection for PLL
AnnaBridge	145:64910690c574	1798	* @note Must be written before enabling PLL
AnnaBridge	145:64910690c574	1799	* @rmtoll SSCGR SPREADSEL LL_RCC_PLL_GetSpreadSelection
AnnaBridge	145:64910690c574	1800	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1801	* @arg @ref LL_RCC_SPREAD_SELECT_CENTER
AnnaBridge	145:64910690c574	1802	* @arg @ref LL_RCC_SPREAD_SELECT_DOWN
AnnaBridge	145:64910690c574	1803	*/
AnnaBridge	145:64910690c574	1804	__STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void)
AnnaBridge	145:64910690c574	1805	{
AnnaBridge	145:64910690c574	1806	return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL));
AnnaBridge	145:64910690c574	1807	}
AnnaBridge	145:64910690c574	1808
AnnaBridge	145:64910690c574	1809	/**
AnnaBridge	145:64910690c574	1810	* @brief Enable Spread Spectrum for PLL.
AnnaBridge	145:64910690c574	1811	* @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Enable
AnnaBridge	145:64910690c574	1812	* @retval None
AnnaBridge	145:64910690c574	1813	*/
AnnaBridge	145:64910690c574	1814	__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void)
AnnaBridge	145:64910690c574	1815	{
AnnaBridge	145:64910690c574	1816	SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
AnnaBridge	145:64910690c574	1817	}
AnnaBridge	145:64910690c574	1818
AnnaBridge	145:64910690c574	1819	/**
AnnaBridge	145:64910690c574	1820	* @brief Disable Spread Spectrum for PLL.
AnnaBridge	145:64910690c574	1821	* @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Disable
AnnaBridge	145:64910690c574	1822	* @retval None
AnnaBridge	145:64910690c574	1823	*/
AnnaBridge	145:64910690c574	1824	__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void)
AnnaBridge	145:64910690c574	1825	{
AnnaBridge	145:64910690c574	1826	CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
AnnaBridge	145:64910690c574	1827	}
AnnaBridge	145:64910690c574	1828
AnnaBridge	145:64910690c574	1829	/**
AnnaBridge	145:64910690c574	1830	* @}
AnnaBridge	145:64910690c574	1831	*/
AnnaBridge	145:64910690c574	1832
AnnaBridge	145:64910690c574	1833	/** @defgroup RCC_LL_EF_PLLI2S PLLI2S
AnnaBridge	145:64910690c574	1834	* @{
AnnaBridge	145:64910690c574	1835	*/
AnnaBridge	145:64910690c574	1836
AnnaBridge	145:64910690c574	1837	/**
AnnaBridge	145:64910690c574	1838	* @brief Enable PLLI2S
AnnaBridge	145:64910690c574	1839	* @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Enable
AnnaBridge	145:64910690c574	1840	* @retval None
AnnaBridge	145:64910690c574	1841	*/
AnnaBridge	145:64910690c574	1842	__STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
AnnaBridge	145:64910690c574	1843	{
AnnaBridge	145:64910690c574	1844	SET_BIT(RCC->CR, RCC_CR_PLLI2SON);
AnnaBridge	145:64910690c574	1845	}
AnnaBridge	145:64910690c574	1846
AnnaBridge	145:64910690c574	1847	/**
AnnaBridge	145:64910690c574	1848	* @brief Disable PLLI2S
AnnaBridge	145:64910690c574	1849	* @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Disable
AnnaBridge	145:64910690c574	1850	* @retval None
AnnaBridge	145:64910690c574	1851	*/
AnnaBridge	145:64910690c574	1852	__STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
AnnaBridge	145:64910690c574	1853	{
AnnaBridge	145:64910690c574	1854	CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
AnnaBridge	145:64910690c574	1855	}
AnnaBridge	145:64910690c574	1856
AnnaBridge	145:64910690c574	1857	/**
AnnaBridge	145:64910690c574	1858	* @brief Check if PLLI2S Ready
AnnaBridge	145:64910690c574	1859	* @rmtoll CR PLLI2SRDY LL_RCC_PLLI2S_IsReady
AnnaBridge	145:64910690c574	1860	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1861	*/
AnnaBridge	145:64910690c574	1862	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
AnnaBridge	145:64910690c574	1863	{
AnnaBridge	145:64910690c574	1864	return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY));
AnnaBridge	145:64910690c574	1865	}
AnnaBridge	145:64910690c574	1866
AnnaBridge	145:64910690c574	1867	/**
AnnaBridge	145:64910690c574	1868	* @brief Configure PLLI2S used for I2S1 domain clock
AnnaBridge	145:64910690c574	1869	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	145:64910690c574	1870	* PLLI2S are disabled
AnnaBridge	145:64910690c574	1871	* @note PLLN/PLLR can be written only when PLLI2S is disabled
AnnaBridge	145:64910690c574	1872	* @note This can be selected for I2S
AnnaBridge	145:64910690c574	1873	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n
AnnaBridge	145:64910690c574	1874	* PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_I2S\n
AnnaBridge	145:64910690c574	1875	* PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_I2S\n
AnnaBridge	145:64910690c574	1876	* PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_I2S
AnnaBridge	145:64910690c574	1877	* @param Source This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1878	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	145:64910690c574	1879	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	145:64910690c574	1880	* @param PLLM This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1881	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	145:64910690c574	1882	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	145:64910690c574	1883	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	145:64910690c574	1884	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	145:64910690c574	1885	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	145:64910690c574	1886	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	145:64910690c574	1887	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	145:64910690c574	1888	* @arg @ref LL_RCC_PLLM_DIV_9
AnnaBridge	145:64910690c574	1889	* @arg @ref LL_RCC_PLLM_DIV_10
AnnaBridge	145:64910690c574	1890	* @arg @ref LL_RCC_PLLM_DIV_11
AnnaBridge	145:64910690c574	1891	* @arg @ref LL_RCC_PLLM_DIV_12
AnnaBridge	145:64910690c574	1892	* @arg @ref LL_RCC_PLLM_DIV_13
AnnaBridge	145:64910690c574	1893	* @arg @ref LL_RCC_PLLM_DIV_14
AnnaBridge	145:64910690c574	1894	* @arg @ref LL_RCC_PLLM_DIV_15
AnnaBridge	145:64910690c574	1895	* @arg @ref LL_RCC_PLLM_DIV_16
AnnaBridge	145:64910690c574	1896	* @arg @ref LL_RCC_PLLM_DIV_17
AnnaBridge	145:64910690c574	1897	* @arg @ref LL_RCC_PLLM_DIV_18
AnnaBridge	145:64910690c574	1898	* @arg @ref LL_RCC_PLLM_DIV_19
AnnaBridge	145:64910690c574	1899	* @arg @ref LL_RCC_PLLM_DIV_20
AnnaBridge	145:64910690c574	1900	* @arg @ref LL_RCC_PLLM_DIV_21
AnnaBridge	145:64910690c574	1901	* @arg @ref LL_RCC_PLLM_DIV_22
AnnaBridge	145:64910690c574	1902	* @arg @ref LL_RCC_PLLM_DIV_23
AnnaBridge	145:64910690c574	1903	* @arg @ref LL_RCC_PLLM_DIV_24
AnnaBridge	145:64910690c574	1904	* @arg @ref LL_RCC_PLLM_DIV_25
AnnaBridge	145:64910690c574	1905	* @arg @ref LL_RCC_PLLM_DIV_26
AnnaBridge	145:64910690c574	1906	* @arg @ref LL_RCC_PLLM_DIV_27
AnnaBridge	145:64910690c574	1907	* @arg @ref LL_RCC_PLLM_DIV_28
AnnaBridge	145:64910690c574	1908	* @arg @ref LL_RCC_PLLM_DIV_29
AnnaBridge	145:64910690c574	1909	* @arg @ref LL_RCC_PLLM_DIV_30
AnnaBridge	145:64910690c574	1910	* @arg @ref LL_RCC_PLLM_DIV_31
AnnaBridge	145:64910690c574	1911	* @arg @ref LL_RCC_PLLM_DIV_32
AnnaBridge	145:64910690c574	1912	* @arg @ref LL_RCC_PLLM_DIV_33
AnnaBridge	145:64910690c574	1913	* @arg @ref LL_RCC_PLLM_DIV_34
AnnaBridge	145:64910690c574	1914	* @arg @ref LL_RCC_PLLM_DIV_35
AnnaBridge	145:64910690c574	1915	* @arg @ref LL_RCC_PLLM_DIV_36
AnnaBridge	145:64910690c574	1916	* @arg @ref LL_RCC_PLLM_DIV_37
AnnaBridge	145:64910690c574	1917	* @arg @ref LL_RCC_PLLM_DIV_38
AnnaBridge	145:64910690c574	1918	* @arg @ref LL_RCC_PLLM_DIV_39
AnnaBridge	145:64910690c574	1919	* @arg @ref LL_RCC_PLLM_DIV_40
AnnaBridge	145:64910690c574	1920	* @arg @ref LL_RCC_PLLM_DIV_41
AnnaBridge	145:64910690c574	1921	* @arg @ref LL_RCC_PLLM_DIV_42
AnnaBridge	145:64910690c574	1922	* @arg @ref LL_RCC_PLLM_DIV_43
AnnaBridge	145:64910690c574	1923	* @arg @ref LL_RCC_PLLM_DIV_44
AnnaBridge	145:64910690c574	1924	* @arg @ref LL_RCC_PLLM_DIV_45
AnnaBridge	145:64910690c574	1925	* @arg @ref LL_RCC_PLLM_DIV_46
AnnaBridge	145:64910690c574	1926	* @arg @ref LL_RCC_PLLM_DIV_47
AnnaBridge	145:64910690c574	1927	* @arg @ref LL_RCC_PLLM_DIV_48
AnnaBridge	145:64910690c574	1928	* @arg @ref LL_RCC_PLLM_DIV_49
AnnaBridge	145:64910690c574	1929	* @arg @ref LL_RCC_PLLM_DIV_50
AnnaBridge	145:64910690c574	1930	* @arg @ref LL_RCC_PLLM_DIV_51
AnnaBridge	145:64910690c574	1931	* @arg @ref LL_RCC_PLLM_DIV_52
AnnaBridge	145:64910690c574	1932	* @arg @ref LL_RCC_PLLM_DIV_53
AnnaBridge	145:64910690c574	1933	* @arg @ref LL_RCC_PLLM_DIV_54
AnnaBridge	145:64910690c574	1934	* @arg @ref LL_RCC_PLLM_DIV_55
AnnaBridge	145:64910690c574	1935	* @arg @ref LL_RCC_PLLM_DIV_56
AnnaBridge	145:64910690c574	1936	* @arg @ref LL_RCC_PLLM_DIV_57
AnnaBridge	145:64910690c574	1937	* @arg @ref LL_RCC_PLLM_DIV_58
AnnaBridge	145:64910690c574	1938	* @arg @ref LL_RCC_PLLM_DIV_59
AnnaBridge	145:64910690c574	1939	* @arg @ref LL_RCC_PLLM_DIV_60
AnnaBridge	145:64910690c574	1940	* @arg @ref LL_RCC_PLLM_DIV_61
AnnaBridge	145:64910690c574	1941	* @arg @ref LL_RCC_PLLM_DIV_62
AnnaBridge	145:64910690c574	1942	* @arg @ref LL_RCC_PLLM_DIV_63
AnnaBridge	145:64910690c574	1943	* @param PLLN Between 192 and 432
AnnaBridge	145:64910690c574	1944	* @param PLLR This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1945	* @arg @ref LL_RCC_PLLI2SR_DIV_2
AnnaBridge	145:64910690c574	1946	* @arg @ref LL_RCC_PLLI2SR_DIV_3
AnnaBridge	145:64910690c574	1947	* @arg @ref LL_RCC_PLLI2SR_DIV_4
AnnaBridge	145:64910690c574	1948	* @arg @ref LL_RCC_PLLI2SR_DIV_5
AnnaBridge	145:64910690c574	1949	* @arg @ref LL_RCC_PLLI2SR_DIV_6
AnnaBridge	145:64910690c574	1950	* @arg @ref LL_RCC_PLLI2SR_DIV_7
AnnaBridge	145:64910690c574	1951	* @retval None
AnnaBridge	145:64910690c574	1952	*/
AnnaBridge	145:64910690c574	1953	__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
AnnaBridge	145:64910690c574	1954	{
AnnaBridge	145:64910690c574	1955	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
AnnaBridge	145:64910690c574	1956	MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN \| RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos \| PLLR);
AnnaBridge	145:64910690c574	1957	}
AnnaBridge	145:64910690c574	1958
AnnaBridge	145:64910690c574	1959	/**
AnnaBridge	145:64910690c574	1960	* @brief Get I2SPLL multiplication factor for VCO
AnnaBridge	145:64910690c574	1961	* @rmtoll PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_GetN
AnnaBridge	145:64910690c574	1962	* @retval Between 192 and 432
AnnaBridge	145:64910690c574	1963	*/
AnnaBridge	145:64910690c574	1964	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void)
AnnaBridge	145:64910690c574	1965	{
AnnaBridge	145:64910690c574	1966	return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
AnnaBridge	145:64910690c574	1967	}
AnnaBridge	145:64910690c574	1968
AnnaBridge	145:64910690c574	1969	/**
AnnaBridge	145:64910690c574	1970	* @brief Get I2SPLL division factor for PLLI2SR
AnnaBridge	145:64910690c574	1971	* @note used for PLLI2SCLK (I2S clock)
AnnaBridge	145:64910690c574	1972	* @rmtoll PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_GetR
AnnaBridge	145:64910690c574	1973	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1974	* @arg @ref LL_RCC_PLLI2SR_DIV_2
AnnaBridge	145:64910690c574	1975	* @arg @ref LL_RCC_PLLI2SR_DIV_3
AnnaBridge	145:64910690c574	1976	* @arg @ref LL_RCC_PLLI2SR_DIV_4
AnnaBridge	145:64910690c574	1977	* @arg @ref LL_RCC_PLLI2SR_DIV_5
AnnaBridge	145:64910690c574	1978	* @arg @ref LL_RCC_PLLI2SR_DIV_6
AnnaBridge	145:64910690c574	1979	* @arg @ref LL_RCC_PLLI2SR_DIV_7
AnnaBridge	145:64910690c574	1980	*/
AnnaBridge	145:64910690c574	1981	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void)
AnnaBridge	145:64910690c574	1982	{
AnnaBridge	145:64910690c574	1983	return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR));
AnnaBridge	145:64910690c574	1984	}
AnnaBridge	145:64910690c574	1985
AnnaBridge	145:64910690c574	1986	/**
AnnaBridge	145:64910690c574	1987	* @}
AnnaBridge	145:64910690c574	1988	*/
AnnaBridge	145:64910690c574	1989
AnnaBridge	145:64910690c574	1990	/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
AnnaBridge	145:64910690c574	1991	* @{
AnnaBridge	145:64910690c574	1992	*/
AnnaBridge	145:64910690c574	1993
AnnaBridge	145:64910690c574	1994	/**
AnnaBridge	145:64910690c574	1995	* @brief Clear LSI ready interrupt flag
AnnaBridge	145:64910690c574	1996	* @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
AnnaBridge	145:64910690c574	1997	* @retval None
AnnaBridge	145:64910690c574	1998	*/
AnnaBridge	145:64910690c574	1999	__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
AnnaBridge	145:64910690c574	2000	{
AnnaBridge	145:64910690c574	2001	SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
AnnaBridge	145:64910690c574	2002	}
AnnaBridge	145:64910690c574	2003
AnnaBridge	145:64910690c574	2004	/**
AnnaBridge	145:64910690c574	2005	* @brief Clear LSE ready interrupt flag
AnnaBridge	145:64910690c574	2006	* @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
AnnaBridge	145:64910690c574	2007	* @retval None
AnnaBridge	145:64910690c574	2008	*/
AnnaBridge	145:64910690c574	2009	__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
AnnaBridge	145:64910690c574	2010	{
AnnaBridge	145:64910690c574	2011	SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
AnnaBridge	145:64910690c574	2012	}
AnnaBridge	145:64910690c574	2013
AnnaBridge	145:64910690c574	2014	/**
AnnaBridge	145:64910690c574	2015	* @brief Clear HSI ready interrupt flag
AnnaBridge	145:64910690c574	2016	* @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
AnnaBridge	145:64910690c574	2017	* @retval None
AnnaBridge	145:64910690c574	2018	*/
AnnaBridge	145:64910690c574	2019	__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
AnnaBridge	145:64910690c574	2020	{
AnnaBridge	145:64910690c574	2021	SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
AnnaBridge	145:64910690c574	2022	}
AnnaBridge	145:64910690c574	2023
AnnaBridge	145:64910690c574	2024	/**
AnnaBridge	145:64910690c574	2025	* @brief Clear HSE ready interrupt flag
AnnaBridge	145:64910690c574	2026	* @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
AnnaBridge	145:64910690c574	2027	* @retval None
AnnaBridge	145:64910690c574	2028	*/
AnnaBridge	145:64910690c574	2029	__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
AnnaBridge	145:64910690c574	2030	{
AnnaBridge	145:64910690c574	2031	SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
AnnaBridge	145:64910690c574	2032	}
AnnaBridge	145:64910690c574	2033
AnnaBridge	145:64910690c574	2034	/**
AnnaBridge	145:64910690c574	2035	* @brief Clear PLL ready interrupt flag
AnnaBridge	145:64910690c574	2036	* @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
AnnaBridge	145:64910690c574	2037	* @retval None
AnnaBridge	145:64910690c574	2038	*/
AnnaBridge	145:64910690c574	2039	__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
AnnaBridge	145:64910690c574	2040	{
AnnaBridge	145:64910690c574	2041	SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
AnnaBridge	145:64910690c574	2042	}
AnnaBridge	145:64910690c574	2043
AnnaBridge	145:64910690c574	2044	/**
AnnaBridge	145:64910690c574	2045	* @brief Clear PLLI2S ready interrupt flag
AnnaBridge	145:64910690c574	2046	* @rmtoll CIR PLLI2SRDYC LL_RCC_ClearFlag_PLLI2SRDY
AnnaBridge	145:64910690c574	2047	* @retval None
AnnaBridge	145:64910690c574	2048	*/
AnnaBridge	145:64910690c574	2049	__STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)
AnnaBridge	145:64910690c574	2050	{
AnnaBridge	145:64910690c574	2051	SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
AnnaBridge	145:64910690c574	2052	}
AnnaBridge	145:64910690c574	2053
AnnaBridge	145:64910690c574	2054	/**
AnnaBridge	145:64910690c574	2055	* @brief Clear Clock security system interrupt flag
AnnaBridge	145:64910690c574	2056	* @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
AnnaBridge	145:64910690c574	2057	* @retval None
AnnaBridge	145:64910690c574	2058	*/
AnnaBridge	145:64910690c574	2059	__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
AnnaBridge	145:64910690c574	2060	{
AnnaBridge	145:64910690c574	2061	SET_BIT(RCC->CIR, RCC_CIR_CSSC);
AnnaBridge	145:64910690c574	2062	}
AnnaBridge	145:64910690c574	2063
AnnaBridge	145:64910690c574	2064	/**
AnnaBridge	145:64910690c574	2065	* @brief Check if LSI ready interrupt occurred or not
AnnaBridge	145:64910690c574	2066	* @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
AnnaBridge	145:64910690c574	2067	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2068	*/
AnnaBridge	145:64910690c574	2069	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
AnnaBridge	145:64910690c574	2070	{
AnnaBridge	145:64910690c574	2071	return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
AnnaBridge	145:64910690c574	2072	}
AnnaBridge	145:64910690c574	2073
AnnaBridge	145:64910690c574	2074	/**
AnnaBridge	145:64910690c574	2075	* @brief Check if LSE ready interrupt occurred or not
AnnaBridge	145:64910690c574	2076	* @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
AnnaBridge	145:64910690c574	2077	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2078	*/
AnnaBridge	145:64910690c574	2079	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
AnnaBridge	145:64910690c574	2080	{
AnnaBridge	145:64910690c574	2081	return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
AnnaBridge	145:64910690c574	2082	}
AnnaBridge	145:64910690c574	2083
AnnaBridge	145:64910690c574	2084	/**
AnnaBridge	145:64910690c574	2085	* @brief Check if HSI ready interrupt occurred or not
AnnaBridge	145:64910690c574	2086	* @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
AnnaBridge	145:64910690c574	2087	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2088	*/
AnnaBridge	145:64910690c574	2089	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
AnnaBridge	145:64910690c574	2090	{
AnnaBridge	145:64910690c574	2091	return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
AnnaBridge	145:64910690c574	2092	}
AnnaBridge	145:64910690c574	2093
AnnaBridge	145:64910690c574	2094	/**
AnnaBridge	145:64910690c574	2095	* @brief Check if HSE ready interrupt occurred or not
AnnaBridge	145:64910690c574	2096	* @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
AnnaBridge	145:64910690c574	2097	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2098	*/
AnnaBridge	145:64910690c574	2099	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
AnnaBridge	145:64910690c574	2100	{
AnnaBridge	145:64910690c574	2101	return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
AnnaBridge	145:64910690c574	2102	}
AnnaBridge	145:64910690c574	2103
AnnaBridge	145:64910690c574	2104	/**
AnnaBridge	145:64910690c574	2105	* @brief Check if PLL ready interrupt occurred or not
AnnaBridge	145:64910690c574	2106	* @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
AnnaBridge	145:64910690c574	2107	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2108	*/
AnnaBridge	145:64910690c574	2109	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
AnnaBridge	145:64910690c574	2110	{
AnnaBridge	145:64910690c574	2111	return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
AnnaBridge	145:64910690c574	2112	}
AnnaBridge	145:64910690c574	2113
AnnaBridge	145:64910690c574	2114	/**
AnnaBridge	145:64910690c574	2115	* @brief Check if PLLI2S ready interrupt occurred or not
AnnaBridge	145:64910690c574	2116	* @rmtoll CIR PLLI2SRDYF LL_RCC_IsActiveFlag_PLLI2SRDY
AnnaBridge	145:64910690c574	2117	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2118	*/
AnnaBridge	145:64910690c574	2119	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)
AnnaBridge	145:64910690c574	2120	{
AnnaBridge	145:64910690c574	2121	return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF));
AnnaBridge	145:64910690c574	2122	}
AnnaBridge	145:64910690c574	2123
AnnaBridge	145:64910690c574	2124	/**
AnnaBridge	145:64910690c574	2125	* @brief Check if Clock security system interrupt occurred or not
AnnaBridge	145:64910690c574	2126	* @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
AnnaBridge	145:64910690c574	2127	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2128	*/
AnnaBridge	145:64910690c574	2129	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
AnnaBridge	145:64910690c574	2130	{
AnnaBridge	145:64910690c574	2131	return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
AnnaBridge	145:64910690c574	2132	}
AnnaBridge	145:64910690c574	2133
AnnaBridge	145:64910690c574	2134	/**
AnnaBridge	145:64910690c574	2135	* @brief Check if RCC flag Independent Watchdog reset is set or not.
AnnaBridge	145:64910690c574	2136	* @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
AnnaBridge	145:64910690c574	2137	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2138	*/
AnnaBridge	145:64910690c574	2139	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
AnnaBridge	145:64910690c574	2140	{
AnnaBridge	145:64910690c574	2141	return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
AnnaBridge	145:64910690c574	2142	}
AnnaBridge	145:64910690c574	2143
AnnaBridge	145:64910690c574	2144	/**
AnnaBridge	145:64910690c574	2145	* @brief Check if RCC flag Low Power reset is set or not.
AnnaBridge	145:64910690c574	2146	* @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
AnnaBridge	145:64910690c574	2147	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2148	*/
AnnaBridge	145:64910690c574	2149	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
AnnaBridge	145:64910690c574	2150	{
AnnaBridge	145:64910690c574	2151	return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
AnnaBridge	145:64910690c574	2152	}
AnnaBridge	145:64910690c574	2153
AnnaBridge	145:64910690c574	2154	/**
AnnaBridge	145:64910690c574	2155	* @brief Check if RCC flag Pin reset is set or not.
AnnaBridge	145:64910690c574	2156	* @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
AnnaBridge	145:64910690c574	2157	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2158	*/
AnnaBridge	145:64910690c574	2159	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
AnnaBridge	145:64910690c574	2160	{
AnnaBridge	145:64910690c574	2161	return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
AnnaBridge	145:64910690c574	2162	}
AnnaBridge	145:64910690c574	2163
AnnaBridge	145:64910690c574	2164	/**
AnnaBridge	145:64910690c574	2165	* @brief Check if RCC flag POR/PDR reset is set or not.
AnnaBridge	145:64910690c574	2166	* @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
AnnaBridge	145:64910690c574	2167	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2168	*/
AnnaBridge	145:64910690c574	2169	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
AnnaBridge	145:64910690c574	2170	{
AnnaBridge	145:64910690c574	2171	return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
AnnaBridge	145:64910690c574	2172	}
AnnaBridge	145:64910690c574	2173
AnnaBridge	145:64910690c574	2174	/**
AnnaBridge	145:64910690c574	2175	* @brief Check if RCC flag Software reset is set or not.
AnnaBridge	145:64910690c574	2176	* @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
AnnaBridge	145:64910690c574	2177	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2178	*/
AnnaBridge	145:64910690c574	2179	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
AnnaBridge	145:64910690c574	2180	{
AnnaBridge	145:64910690c574	2181	return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
AnnaBridge	145:64910690c574	2182	}
AnnaBridge	145:64910690c574	2183
AnnaBridge	145:64910690c574	2184	/**
AnnaBridge	145:64910690c574	2185	* @brief Check if RCC flag Window Watchdog reset is set or not.
AnnaBridge	145:64910690c574	2186	* @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
AnnaBridge	145:64910690c574	2187	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2188	*/
AnnaBridge	145:64910690c574	2189	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
AnnaBridge	145:64910690c574	2190	{
AnnaBridge	145:64910690c574	2191	return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
AnnaBridge	145:64910690c574	2192	}
AnnaBridge	145:64910690c574	2193
AnnaBridge	145:64910690c574	2194	/**
AnnaBridge	145:64910690c574	2195	* @brief Check if RCC flag BOR reset is set or not.
AnnaBridge	145:64910690c574	2196	* @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
AnnaBridge	145:64910690c574	2197	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2198	*/
AnnaBridge	145:64910690c574	2199	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
AnnaBridge	145:64910690c574	2200	{
AnnaBridge	145:64910690c574	2201	return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));
AnnaBridge	145:64910690c574	2202	}
AnnaBridge	145:64910690c574	2203
AnnaBridge	145:64910690c574	2204	/**
AnnaBridge	145:64910690c574	2205	* @brief Set RMVF bit to clear the reset flags.
AnnaBridge	145:64910690c574	2206	* @rmtoll CSR RMVF LL_RCC_ClearResetFlags
AnnaBridge	145:64910690c574	2207	* @retval None
AnnaBridge	145:64910690c574	2208	*/
AnnaBridge	145:64910690c574	2209	__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
AnnaBridge	145:64910690c574	2210	{
AnnaBridge	145:64910690c574	2211	SET_BIT(RCC->CSR, RCC_CSR_RMVF);
AnnaBridge	145:64910690c574	2212	}
AnnaBridge	145:64910690c574	2213
AnnaBridge	145:64910690c574	2214	/**
AnnaBridge	145:64910690c574	2215	* @}
AnnaBridge	145:64910690c574	2216	*/
AnnaBridge	145:64910690c574	2217
AnnaBridge	145:64910690c574	2218	/** @defgroup RCC_LL_EF_IT_Management IT Management
AnnaBridge	145:64910690c574	2219	* @{
AnnaBridge	145:64910690c574	2220	*/
AnnaBridge	145:64910690c574	2221
AnnaBridge	145:64910690c574	2222	/**
AnnaBridge	145:64910690c574	2223	* @brief Enable LSI ready interrupt
AnnaBridge	145:64910690c574	2224	* @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
AnnaBridge	145:64910690c574	2225	* @retval None
AnnaBridge	145:64910690c574	2226	*/
AnnaBridge	145:64910690c574	2227	__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
AnnaBridge	145:64910690c574	2228	{
AnnaBridge	145:64910690c574	2229	SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
AnnaBridge	145:64910690c574	2230	}
AnnaBridge	145:64910690c574	2231
AnnaBridge	145:64910690c574	2232	/**
AnnaBridge	145:64910690c574	2233	* @brief Enable LSE ready interrupt
AnnaBridge	145:64910690c574	2234	* @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
AnnaBridge	145:64910690c574	2235	* @retval None
AnnaBridge	145:64910690c574	2236	*/
AnnaBridge	145:64910690c574	2237	__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
AnnaBridge	145:64910690c574	2238	{
AnnaBridge	145:64910690c574	2239	SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
AnnaBridge	145:64910690c574	2240	}
AnnaBridge	145:64910690c574	2241
AnnaBridge	145:64910690c574	2242	/**
AnnaBridge	145:64910690c574	2243	* @brief Enable HSI ready interrupt
AnnaBridge	145:64910690c574	2244	* @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
AnnaBridge	145:64910690c574	2245	* @retval None
AnnaBridge	145:64910690c574	2246	*/
AnnaBridge	145:64910690c574	2247	__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
AnnaBridge	145:64910690c574	2248	{
AnnaBridge	145:64910690c574	2249	SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
AnnaBridge	145:64910690c574	2250	}
AnnaBridge	145:64910690c574	2251
AnnaBridge	145:64910690c574	2252	/**
AnnaBridge	145:64910690c574	2253	* @brief Enable HSE ready interrupt
AnnaBridge	145:64910690c574	2254	* @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
AnnaBridge	145:64910690c574	2255	* @retval None
AnnaBridge	145:64910690c574	2256	*/
AnnaBridge	145:64910690c574	2257	__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
AnnaBridge	145:64910690c574	2258	{
AnnaBridge	145:64910690c574	2259	SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
AnnaBridge	145:64910690c574	2260	}
AnnaBridge	145:64910690c574	2261
AnnaBridge	145:64910690c574	2262	/**
AnnaBridge	145:64910690c574	2263	* @brief Enable PLL ready interrupt
AnnaBridge	145:64910690c574	2264	* @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
AnnaBridge	145:64910690c574	2265	* @retval None
AnnaBridge	145:64910690c574	2266	*/
AnnaBridge	145:64910690c574	2267	__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
AnnaBridge	145:64910690c574	2268	{
AnnaBridge	145:64910690c574	2269	SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
AnnaBridge	145:64910690c574	2270	}
AnnaBridge	145:64910690c574	2271
AnnaBridge	145:64910690c574	2272	/**
AnnaBridge	145:64910690c574	2273	* @brief Enable PLLI2S ready interrupt
AnnaBridge	145:64910690c574	2274	* @rmtoll CIR PLLI2SRDYIE LL_RCC_EnableIT_PLLI2SRDY
AnnaBridge	145:64910690c574	2275	* @retval None
AnnaBridge	145:64910690c574	2276	*/
AnnaBridge	145:64910690c574	2277	__STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)
AnnaBridge	145:64910690c574	2278	{
AnnaBridge	145:64910690c574	2279	SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
AnnaBridge	145:64910690c574	2280	}
AnnaBridge	145:64910690c574	2281
AnnaBridge	145:64910690c574	2282	/**
AnnaBridge	145:64910690c574	2283	* @brief Disable LSI ready interrupt
AnnaBridge	145:64910690c574	2284	* @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
AnnaBridge	145:64910690c574	2285	* @retval None
AnnaBridge	145:64910690c574	2286	*/
AnnaBridge	145:64910690c574	2287	__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
AnnaBridge	145:64910690c574	2288	{
AnnaBridge	145:64910690c574	2289	CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
AnnaBridge	145:64910690c574	2290	}
AnnaBridge	145:64910690c574	2291
AnnaBridge	145:64910690c574	2292	/**
AnnaBridge	145:64910690c574	2293	* @brief Disable LSE ready interrupt
AnnaBridge	145:64910690c574	2294	* @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
AnnaBridge	145:64910690c574	2295	* @retval None
AnnaBridge	145:64910690c574	2296	*/
AnnaBridge	145:64910690c574	2297	__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
AnnaBridge	145:64910690c574	2298	{
AnnaBridge	145:64910690c574	2299	CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
AnnaBridge	145:64910690c574	2300	}
AnnaBridge	145:64910690c574	2301
AnnaBridge	145:64910690c574	2302	/**
AnnaBridge	145:64910690c574	2303	* @brief Disable HSI ready interrupt
AnnaBridge	145:64910690c574	2304	* @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
AnnaBridge	145:64910690c574	2305	* @retval None
AnnaBridge	145:64910690c574	2306	*/
AnnaBridge	145:64910690c574	2307	__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
AnnaBridge	145:64910690c574	2308	{
AnnaBridge	145:64910690c574	2309	CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
AnnaBridge	145:64910690c574	2310	}
AnnaBridge	145:64910690c574	2311
AnnaBridge	145:64910690c574	2312	/**
AnnaBridge	145:64910690c574	2313	* @brief Disable HSE ready interrupt
AnnaBridge	145:64910690c574	2314	* @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
AnnaBridge	145:64910690c574	2315	* @retval None
AnnaBridge	145:64910690c574	2316	*/
AnnaBridge	145:64910690c574	2317	__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
AnnaBridge	145:64910690c574	2318	{
AnnaBridge	145:64910690c574	2319	CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
AnnaBridge	145:64910690c574	2320	}
AnnaBridge	145:64910690c574	2321
AnnaBridge	145:64910690c574	2322	/**
AnnaBridge	145:64910690c574	2323	* @brief Disable PLL ready interrupt
AnnaBridge	145:64910690c574	2324	* @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
AnnaBridge	145:64910690c574	2325	* @retval None
AnnaBridge	145:64910690c574	2326	*/
AnnaBridge	145:64910690c574	2327	__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
AnnaBridge	145:64910690c574	2328	{
AnnaBridge	145:64910690c574	2329	CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
AnnaBridge	145:64910690c574	2330	}
AnnaBridge	145:64910690c574	2331
AnnaBridge	145:64910690c574	2332	/**
AnnaBridge	145:64910690c574	2333	* @brief Disable PLLI2S ready interrupt
AnnaBridge	145:64910690c574	2334	* @rmtoll CIR PLLI2SRDYIE LL_RCC_DisableIT_PLLI2SRDY
AnnaBridge	145:64910690c574	2335	* @retval None
AnnaBridge	145:64910690c574	2336	*/
AnnaBridge	145:64910690c574	2337	__STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)
AnnaBridge	145:64910690c574	2338	{
AnnaBridge	145:64910690c574	2339	CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
AnnaBridge	145:64910690c574	2340	}
AnnaBridge	145:64910690c574	2341
AnnaBridge	145:64910690c574	2342	/**
AnnaBridge	145:64910690c574	2343	* @brief Checks if LSI ready interrupt source is enabled or disabled.
AnnaBridge	145:64910690c574	2344	* @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
AnnaBridge	145:64910690c574	2345	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2346	*/
AnnaBridge	145:64910690c574	2347	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
AnnaBridge	145:64910690c574	2348	{
AnnaBridge	145:64910690c574	2349	return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
AnnaBridge	145:64910690c574	2350	}
AnnaBridge	145:64910690c574	2351
AnnaBridge	145:64910690c574	2352	/**
AnnaBridge	145:64910690c574	2353	* @brief Checks if LSE ready interrupt source is enabled or disabled.
AnnaBridge	145:64910690c574	2354	* @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
AnnaBridge	145:64910690c574	2355	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2356	*/
AnnaBridge	145:64910690c574	2357	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
AnnaBridge	145:64910690c574	2358	{
AnnaBridge	145:64910690c574	2359	return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
AnnaBridge	145:64910690c574	2360	}
AnnaBridge	145:64910690c574	2361
AnnaBridge	145:64910690c574	2362	/**
AnnaBridge	145:64910690c574	2363	* @brief Checks if HSI ready interrupt source is enabled or disabled.
AnnaBridge	145:64910690c574	2364	* @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
AnnaBridge	145:64910690c574	2365	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2366	*/
AnnaBridge	145:64910690c574	2367	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
AnnaBridge	145:64910690c574	2368	{
AnnaBridge	145:64910690c574	2369	return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
AnnaBridge	145:64910690c574	2370	}
AnnaBridge	145:64910690c574	2371
AnnaBridge	145:64910690c574	2372	/**
AnnaBridge	145:64910690c574	2373	* @brief Checks if HSE ready interrupt source is enabled or disabled.
AnnaBridge	145:64910690c574	2374	* @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
AnnaBridge	145:64910690c574	2375	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2376	*/
AnnaBridge	145:64910690c574	2377	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
AnnaBridge	145:64910690c574	2378	{
AnnaBridge	145:64910690c574	2379	return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
AnnaBridge	145:64910690c574	2380	}
AnnaBridge	145:64910690c574	2381
AnnaBridge	145:64910690c574	2382	/**
AnnaBridge	145:64910690c574	2383	* @brief Checks if PLL ready interrupt source is enabled or disabled.
AnnaBridge	145:64910690c574	2384	* @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
AnnaBridge	145:64910690c574	2385	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2386	*/
AnnaBridge	145:64910690c574	2387	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
AnnaBridge	145:64910690c574	2388	{
AnnaBridge	145:64910690c574	2389	return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
AnnaBridge	145:64910690c574	2390	}
AnnaBridge	145:64910690c574	2391
AnnaBridge	145:64910690c574	2392	/**
AnnaBridge	145:64910690c574	2393	* @brief Checks if PLLI2S ready interrupt source is enabled or disabled.
AnnaBridge	145:64910690c574	2394	* @rmtoll CIR PLLI2SRDYIE LL_RCC_IsEnabledIT_PLLI2SRDY
AnnaBridge	145:64910690c574	2395	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2396	*/
AnnaBridge	145:64910690c574	2397	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)
AnnaBridge	145:64910690c574	2398	{
AnnaBridge	145:64910690c574	2399	return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE));
AnnaBridge	145:64910690c574	2400	}
AnnaBridge	145:64910690c574	2401
AnnaBridge	145:64910690c574	2402	/**
AnnaBridge	145:64910690c574	2403	* @}
AnnaBridge	145:64910690c574	2404	*/
AnnaBridge	145:64910690c574	2405
AnnaBridge	145:64910690c574	2406	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	145:64910690c574	2407	/** @defgroup RCC_LL_EF_Init De-initialization function
AnnaBridge	145:64910690c574	2408	* @{
AnnaBridge	145:64910690c574	2409	*/
AnnaBridge	145:64910690c574	2410	ErrorStatus LL_RCC_DeInit(void);
AnnaBridge	145:64910690c574	2411	/**
AnnaBridge	145:64910690c574	2412	* @}
AnnaBridge	145:64910690c574	2413	*/
AnnaBridge	145:64910690c574	2414
AnnaBridge	145:64910690c574	2415	/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
AnnaBridge	145:64910690c574	2416	* @{
AnnaBridge	145:64910690c574	2417	*/
AnnaBridge	145:64910690c574	2418	void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
AnnaBridge	145:64910690c574	2419	uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
AnnaBridge	145:64910690c574	2420	/**
AnnaBridge	145:64910690c574	2421	* @}
AnnaBridge	145:64910690c574	2422	*/
AnnaBridge	145:64910690c574	2423	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	145:64910690c574	2424
AnnaBridge	145:64910690c574	2425	/**
AnnaBridge	145:64910690c574	2426	* @}
AnnaBridge	145:64910690c574	2427	*/
AnnaBridge	145:64910690c574	2428
AnnaBridge	145:64910690c574	2429	/**
AnnaBridge	145:64910690c574	2430	* @}
AnnaBridge	145:64910690c574	2431	*/
AnnaBridge	145:64910690c574	2432
AnnaBridge	145:64910690c574	2433	#endif /* defined(RCC) */
AnnaBridge	145:64910690c574	2434
AnnaBridge	145:64910690c574	2435	/**
AnnaBridge	145:64910690c574	2436	* @}
AnnaBridge	145:64910690c574	2437	*/
AnnaBridge	145:64910690c574	2438
AnnaBridge	145:64910690c574	2439	#ifdef __cplusplus
AnnaBridge	145:64910690c574	2440	}
AnnaBridge	145:64910690c574	2441	#endif
AnnaBridge	145:64910690c574	2442
AnnaBridge	145:64910690c574	2443	#endif /* __STM32F2xx_LL_RCC_H */
AnnaBridge	145:64910690c574	2444
AnnaBridge	145:64910690c574	2445	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/