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TARGET_NUCLEO_F207ZG/TOOLCHAIN_GCC_ARM/stm32f2xx_ll_fsmc.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	171:3a7713b1edbc	1	/**
AnnaBridge	171:3a7713b1edbc	2	******************************************************************************
AnnaBridge	171:3a7713b1edbc	3	* @file stm32f2xx_ll_fsmc.h
AnnaBridge	171:3a7713b1edbc	4	* @author MCD Application Team
AnnaBridge	171:3a7713b1edbc	5	* @version V1.2.1
AnnaBridge	171:3a7713b1edbc	6	* @date 14-April-2017
AnnaBridge	171:3a7713b1edbc	7	* @brief Header file of FSMC HAL module.
AnnaBridge	171:3a7713b1edbc	8	******************************************************************************
AnnaBridge	171:3a7713b1edbc	9	* @attention
AnnaBridge	171:3a7713b1edbc	10	*
AnnaBridge	171:3a7713b1edbc	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	171:3a7713b1edbc	12	*
AnnaBridge	171:3a7713b1edbc	13	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	171:3a7713b1edbc	14	* are permitted provided that the following conditions are met:
AnnaBridge	171:3a7713b1edbc	15	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	171:3a7713b1edbc	16	* this list of conditions and the following disclaimer.
AnnaBridge	171:3a7713b1edbc	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	171:3a7713b1edbc	18	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	171:3a7713b1edbc	19	* and/or other materials provided with the distribution.
AnnaBridge	171:3a7713b1edbc	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	171:3a7713b1edbc	21	* may be used to endorse or promote products derived from this software
AnnaBridge	171:3a7713b1edbc	22	* without specific prior written permission.
AnnaBridge	171:3a7713b1edbc	23	*
AnnaBridge	171:3a7713b1edbc	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	171:3a7713b1edbc	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	171:3a7713b1edbc	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	171:3a7713b1edbc	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	171:3a7713b1edbc	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	171:3a7713b1edbc	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	171:3a7713b1edbc	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	171:3a7713b1edbc	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	171:3a7713b1edbc	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	171:3a7713b1edbc	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	171:3a7713b1edbc	34	*
AnnaBridge	171:3a7713b1edbc	35	******************************************************************************
AnnaBridge	171:3a7713b1edbc	36	*/
AnnaBridge	171:3a7713b1edbc	37
AnnaBridge	171:3a7713b1edbc	38	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	171:3a7713b1edbc	39	#ifndef __STM32F2xx_LL_FSMC_H
AnnaBridge	171:3a7713b1edbc	40	#define __STM32F2xx_LL_FSMC_H
AnnaBridge	171:3a7713b1edbc	41
AnnaBridge	171:3a7713b1edbc	42	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	43	extern "C" {
AnnaBridge	171:3a7713b1edbc	44	#endif
AnnaBridge	171:3a7713b1edbc	45
AnnaBridge	171:3a7713b1edbc	46	/* Includes ------------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	47	#include "stm32f2xx_hal_def.h"
AnnaBridge	171:3a7713b1edbc	48
AnnaBridge	171:3a7713b1edbc	49	/** @addtogroup STM32F2xx_HAL_Driver
AnnaBridge	171:3a7713b1edbc	50	* @{
AnnaBridge	171:3a7713b1edbc	51	*/
AnnaBridge	171:3a7713b1edbc	52
AnnaBridge	171:3a7713b1edbc	53	/** @addtogroup FSMC_LL
AnnaBridge	171:3a7713b1edbc	54	* @{
AnnaBridge	171:3a7713b1edbc	55	*/
AnnaBridge	171:3a7713b1edbc	56
AnnaBridge	171:3a7713b1edbc	57	/* Private types -------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	58	/** @defgroup FSMC_LL_Private_Types FSMC Private Types
AnnaBridge	171:3a7713b1edbc	59	* @{
AnnaBridge	171:3a7713b1edbc	60	*/
AnnaBridge	171:3a7713b1edbc	61
AnnaBridge	171:3a7713b1edbc	62	/**
AnnaBridge	171:3a7713b1edbc	63	* @brief FSMC NORSRAM Configuration Structure definition
AnnaBridge	171:3a7713b1edbc	64	*/
AnnaBridge	171:3a7713b1edbc	65	typedef struct
AnnaBridge	171:3a7713b1edbc	66	{
AnnaBridge	171:3a7713b1edbc	67	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
AnnaBridge	171:3a7713b1edbc	68	This parameter can be a value of @ref FSMC_NORSRAM_Bank */
AnnaBridge	171:3a7713b1edbc	69
AnnaBridge	171:3a7713b1edbc	70	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
AnnaBridge	171:3a7713b1edbc	71	multiplexed on the data bus or not.
AnnaBridge	171:3a7713b1edbc	72	This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
AnnaBridge	171:3a7713b1edbc	73
AnnaBridge	171:3a7713b1edbc	74	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
AnnaBridge	171:3a7713b1edbc	75	the corresponding memory device.
AnnaBridge	171:3a7713b1edbc	76	This parameter can be a value of @ref FSMC_Memory_Type */
AnnaBridge	171:3a7713b1edbc	77
AnnaBridge	171:3a7713b1edbc	78	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
AnnaBridge	171:3a7713b1edbc	79	This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */
AnnaBridge	171:3a7713b1edbc	80
AnnaBridge	171:3a7713b1edbc	81	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
AnnaBridge	171:3a7713b1edbc	82	valid only with synchronous burst Flash memories.
AnnaBridge	171:3a7713b1edbc	83	This parameter can be a value of @ref FSMC_Burst_Access_Mode */
AnnaBridge	171:3a7713b1edbc	84
AnnaBridge	171:3a7713b1edbc	85	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
AnnaBridge	171:3a7713b1edbc	86	the Flash memory in burst mode.
AnnaBridge	171:3a7713b1edbc	87	This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
AnnaBridge	171:3a7713b1edbc	88
AnnaBridge	171:3a7713b1edbc	89	uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
AnnaBridge	171:3a7713b1edbc	90	memory, valid only when accessing Flash memories in burst mode.
AnnaBridge	171:3a7713b1edbc	91	This parameter can be a value of @ref FSMC_Wrap_Mode */
AnnaBridge	171:3a7713b1edbc	92
AnnaBridge	171:3a7713b1edbc	93	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
AnnaBridge	171:3a7713b1edbc	94	clock cycle before the wait state or during the wait state,
AnnaBridge	171:3a7713b1edbc	95	valid only when accessing memories in burst mode.
AnnaBridge	171:3a7713b1edbc	96	This parameter can be a value of @ref FSMC_Wait_Timing */
AnnaBridge	171:3a7713b1edbc	97
AnnaBridge	171:3a7713b1edbc	98	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC.
AnnaBridge	171:3a7713b1edbc	99	This parameter can be a value of @ref FSMC_Write_Operation */
AnnaBridge	171:3a7713b1edbc	100
AnnaBridge	171:3a7713b1edbc	101	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
AnnaBridge	171:3a7713b1edbc	102	signal, valid for Flash memory access in burst mode.
AnnaBridge	171:3a7713b1edbc	103	This parameter can be a value of @ref FSMC_Wait_Signal */
AnnaBridge	171:3a7713b1edbc	104
AnnaBridge	171:3a7713b1edbc	105	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
AnnaBridge	171:3a7713b1edbc	106	This parameter can be a value of @ref FSMC_Extended_Mode */
AnnaBridge	171:3a7713b1edbc	107
AnnaBridge	171:3a7713b1edbc	108	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
AnnaBridge	171:3a7713b1edbc	109	valid only with asynchronous Flash memories.
AnnaBridge	171:3a7713b1edbc	110	This parameter can be a value of @ref FSMC_AsynchronousWait */
AnnaBridge	171:3a7713b1edbc	111
AnnaBridge	171:3a7713b1edbc	112	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
AnnaBridge	171:3a7713b1edbc	113	This parameter can be a value of @ref FSMC_Write_Burst */
AnnaBridge	171:3a7713b1edbc	114
AnnaBridge	171:3a7713b1edbc	115	}FSMC_NORSRAM_InitTypeDef;
AnnaBridge	171:3a7713b1edbc	116
AnnaBridge	171:3a7713b1edbc	117	/**
AnnaBridge	171:3a7713b1edbc	118	* @brief FSMC NORSRAM Timing parameters structure definition
AnnaBridge	171:3a7713b1edbc	119	*/
AnnaBridge	171:3a7713b1edbc	120	typedef struct
AnnaBridge	171:3a7713b1edbc	121	{
AnnaBridge	171:3a7713b1edbc	122	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
AnnaBridge	171:3a7713b1edbc	123	the duration of the address setup time.
AnnaBridge	171:3a7713b1edbc	124	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
AnnaBridge	171:3a7713b1edbc	125	@note This parameter is not used with synchronous NOR Flash memories. */
AnnaBridge	171:3a7713b1edbc	126
AnnaBridge	171:3a7713b1edbc	127	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
AnnaBridge	171:3a7713b1edbc	128	the duration of the address hold time.
AnnaBridge	171:3a7713b1edbc	129	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
AnnaBridge	171:3a7713b1edbc	130	@note This parameter is not used with synchronous NOR Flash memories. */
AnnaBridge	171:3a7713b1edbc	131
AnnaBridge	171:3a7713b1edbc	132	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
AnnaBridge	171:3a7713b1edbc	133	the duration of the data setup time.
AnnaBridge	171:3a7713b1edbc	134	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
AnnaBridge	171:3a7713b1edbc	135	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
AnnaBridge	171:3a7713b1edbc	136	NOR Flash memories. */
AnnaBridge	171:3a7713b1edbc	137
AnnaBridge	171:3a7713b1edbc	138	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
AnnaBridge	171:3a7713b1edbc	139	the duration of the bus turnaround.
AnnaBridge	171:3a7713b1edbc	140	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
AnnaBridge	171:3a7713b1edbc	141	@note This parameter is only used for multiplexed NOR Flash memories. */
AnnaBridge	171:3a7713b1edbc	142
AnnaBridge	171:3a7713b1edbc	143	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
AnnaBridge	171:3a7713b1edbc	144	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
AnnaBridge	171:3a7713b1edbc	145	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
AnnaBridge	171:3a7713b1edbc	146	accesses. */
AnnaBridge	171:3a7713b1edbc	147
AnnaBridge	171:3a7713b1edbc	148	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
AnnaBridge	171:3a7713b1edbc	149	to the memory before getting the first data.
AnnaBridge	171:3a7713b1edbc	150	The parameter value depends on the memory type as shown below:
AnnaBridge	171:3a7713b1edbc	151	- It must be set to 0 in case of a CRAM
AnnaBridge	171:3a7713b1edbc	152	- It is don't care in asynchronous NOR, SRAM or ROM accesses
AnnaBridge	171:3a7713b1edbc	153	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
AnnaBridge	171:3a7713b1edbc	154	with synchronous burst mode enable */
AnnaBridge	171:3a7713b1edbc	155
AnnaBridge	171:3a7713b1edbc	156	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
AnnaBridge	171:3a7713b1edbc	157	This parameter can be a value of @ref FSMC_Access_Mode */
AnnaBridge	171:3a7713b1edbc	158
AnnaBridge	171:3a7713b1edbc	159	}FSMC_NORSRAM_TimingTypeDef;
AnnaBridge	171:3a7713b1edbc	160
AnnaBridge	171:3a7713b1edbc	161	/**
AnnaBridge	171:3a7713b1edbc	162	* @brief FSMC NAND Configuration Structure definition
AnnaBridge	171:3a7713b1edbc	163	*/
AnnaBridge	171:3a7713b1edbc	164	typedef struct
AnnaBridge	171:3a7713b1edbc	165	{
AnnaBridge	171:3a7713b1edbc	166	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
AnnaBridge	171:3a7713b1edbc	167	This parameter can be a value of @ref FSMC_NAND_Bank */
AnnaBridge	171:3a7713b1edbc	168
AnnaBridge	171:3a7713b1edbc	169	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
AnnaBridge	171:3a7713b1edbc	170	This parameter can be any value of @ref FSMC_Wait_feature */
AnnaBridge	171:3a7713b1edbc	171
AnnaBridge	171:3a7713b1edbc	172	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
AnnaBridge	171:3a7713b1edbc	173	This parameter can be any value of @ref FSMC_NAND_Data_Width */
AnnaBridge	171:3a7713b1edbc	174
AnnaBridge	171:3a7713b1edbc	175	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
AnnaBridge	171:3a7713b1edbc	176	This parameter can be any value of @ref FSMC_ECC */
AnnaBridge	171:3a7713b1edbc	177
AnnaBridge	171:3a7713b1edbc	178	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
AnnaBridge	171:3a7713b1edbc	179	This parameter can be any value of @ref FSMC_ECC_Page_Size */
AnnaBridge	171:3a7713b1edbc	180
AnnaBridge	171:3a7713b1edbc	181	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
AnnaBridge	171:3a7713b1edbc	182	delay between CLE low and RE low.
AnnaBridge	171:3a7713b1edbc	183	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	171:3a7713b1edbc	184
AnnaBridge	171:3a7713b1edbc	185	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
AnnaBridge	171:3a7713b1edbc	186	delay between ALE low and RE low.
AnnaBridge	171:3a7713b1edbc	187	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	171:3a7713b1edbc	188
AnnaBridge	171:3a7713b1edbc	189	}FSMC_NAND_InitTypeDef;
AnnaBridge	171:3a7713b1edbc	190
AnnaBridge	171:3a7713b1edbc	191	/**
AnnaBridge	171:3a7713b1edbc	192	* @brief FSMC NAND/PCCARD Timing parameters structure definition
AnnaBridge	171:3a7713b1edbc	193	*/
AnnaBridge	171:3a7713b1edbc	194	typedef struct
AnnaBridge	171:3a7713b1edbc	195	{
AnnaBridge	171:3a7713b1edbc	196	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
AnnaBridge	171:3a7713b1edbc	197	the command assertion for NAND-Flash read or write access
AnnaBridge	171:3a7713b1edbc	198	to common/Attribute or I/O memory space (depending on
AnnaBridge	171:3a7713b1edbc	199	the memory space timing to be configured).
AnnaBridge	171:3a7713b1edbc	200	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	171:3a7713b1edbc	201
AnnaBridge	171:3a7713b1edbc	202	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
AnnaBridge	171:3a7713b1edbc	203	command for NAND-Flash read or write access to
AnnaBridge	171:3a7713b1edbc	204	common/Attribute or I/O memory space (depending on the
AnnaBridge	171:3a7713b1edbc	205	memory space timing to be configured).
AnnaBridge	171:3a7713b1edbc	206	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	171:3a7713b1edbc	207
AnnaBridge	171:3a7713b1edbc	208	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
AnnaBridge	171:3a7713b1edbc	209	(and data for write access) after the command de-assertion
AnnaBridge	171:3a7713b1edbc	210	for NAND-Flash read or write access to common/Attribute
AnnaBridge	171:3a7713b1edbc	211	or I/O memory space (depending on the memory space timing
AnnaBridge	171:3a7713b1edbc	212	to be configured).
AnnaBridge	171:3a7713b1edbc	213	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	171:3a7713b1edbc	214
AnnaBridge	171:3a7713b1edbc	215	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
AnnaBridge	171:3a7713b1edbc	216	data bus is kept in HiZ after the start of a NAND-Flash
AnnaBridge	171:3a7713b1edbc	217	write access to common/Attribute or I/O memory space (depending
AnnaBridge	171:3a7713b1edbc	218	on the memory space timing to be configured).
AnnaBridge	171:3a7713b1edbc	219	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	171:3a7713b1edbc	220
AnnaBridge	171:3a7713b1edbc	221	}FSMC_NAND_PCC_TimingTypeDef;
AnnaBridge	171:3a7713b1edbc	222
AnnaBridge	171:3a7713b1edbc	223	/**
AnnaBridge	171:3a7713b1edbc	224	* @brief FSMC NAND Configuration Structure definition
AnnaBridge	171:3a7713b1edbc	225	*/
AnnaBridge	171:3a7713b1edbc	226	typedef struct
AnnaBridge	171:3a7713b1edbc	227	{
AnnaBridge	171:3a7713b1edbc	228	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
AnnaBridge	171:3a7713b1edbc	229	This parameter can be any value of @ref FSMC_Wait_feature */
AnnaBridge	171:3a7713b1edbc	230
AnnaBridge	171:3a7713b1edbc	231	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
AnnaBridge	171:3a7713b1edbc	232	delay between CLE low and RE low.
AnnaBridge	171:3a7713b1edbc	233	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	171:3a7713b1edbc	234
AnnaBridge	171:3a7713b1edbc	235	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
AnnaBridge	171:3a7713b1edbc	236	delay between ALE low and RE low.
AnnaBridge	171:3a7713b1edbc	237	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
AnnaBridge	171:3a7713b1edbc	238
AnnaBridge	171:3a7713b1edbc	239	}FSMC_PCCARD_InitTypeDef;
AnnaBridge	171:3a7713b1edbc	240	/**
AnnaBridge	171:3a7713b1edbc	241	* @}
AnnaBridge	171:3a7713b1edbc	242	*/
AnnaBridge	171:3a7713b1edbc	243
AnnaBridge	171:3a7713b1edbc	244	/* Private constants ---------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	245	/** @defgroup FSMC_LL_Private_Constants FSMC Private Constants
AnnaBridge	171:3a7713b1edbc	246	* @{
AnnaBridge	171:3a7713b1edbc	247	*/
AnnaBridge	171:3a7713b1edbc	248
AnnaBridge	171:3a7713b1edbc	249	/** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller
AnnaBridge	171:3a7713b1edbc	250	* @{
AnnaBridge	171:3a7713b1edbc	251	*/
AnnaBridge	171:3a7713b1edbc	252	/** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
AnnaBridge	171:3a7713b1edbc	253	* @{
AnnaBridge	171:3a7713b1edbc	254	*/
AnnaBridge	171:3a7713b1edbc	255	#define FSMC_NORSRAM_BANK1 0x00000000U
AnnaBridge	171:3a7713b1edbc	256	#define FSMC_NORSRAM_BANK2 0x00000002U
AnnaBridge	171:3a7713b1edbc	257	#define FSMC_NORSRAM_BANK3 0x00000004U
AnnaBridge	171:3a7713b1edbc	258	#define FSMC_NORSRAM_BANK4 0x00000006U
AnnaBridge	171:3a7713b1edbc	259	/**
AnnaBridge	171:3a7713b1edbc	260	* @}
AnnaBridge	171:3a7713b1edbc	261	*/
AnnaBridge	171:3a7713b1edbc	262
AnnaBridge	171:3a7713b1edbc	263	/** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
AnnaBridge	171:3a7713b1edbc	264	* @{
AnnaBridge	171:3a7713b1edbc	265	*/
AnnaBridge	171:3a7713b1edbc	266	#define FSMC_DATA_ADDRESS_MUX_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	267	#define FSMC_DATA_ADDRESS_MUX_ENABLE 0x00000002U
AnnaBridge	171:3a7713b1edbc	268	/**
AnnaBridge	171:3a7713b1edbc	269	* @}
AnnaBridge	171:3a7713b1edbc	270	*/
AnnaBridge	171:3a7713b1edbc	271
AnnaBridge	171:3a7713b1edbc	272	/** @defgroup FSMC_Memory_Type FSMC Memory Type
AnnaBridge	171:3a7713b1edbc	273	* @{
AnnaBridge	171:3a7713b1edbc	274	*/
AnnaBridge	171:3a7713b1edbc	275	#define FSMC_MEMORY_TYPE_SRAM 0x00000000U
AnnaBridge	171:3a7713b1edbc	276	#define FSMC_MEMORY_TYPE_PSRAM 0x00000004U
AnnaBridge	171:3a7713b1edbc	277	#define FSMC_MEMORY_TYPE_NOR 0x00000008U
AnnaBridge	171:3a7713b1edbc	278	/**
AnnaBridge	171:3a7713b1edbc	279	* @}
AnnaBridge	171:3a7713b1edbc	280	*/
AnnaBridge	171:3a7713b1edbc	281
AnnaBridge	171:3a7713b1edbc	282	/** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width
AnnaBridge	171:3a7713b1edbc	283	* @{
AnnaBridge	171:3a7713b1edbc	284	*/
AnnaBridge	171:3a7713b1edbc	285	#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000U
AnnaBridge	171:3a7713b1edbc	286	#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 0x00000010U
AnnaBridge	171:3a7713b1edbc	287	#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 0x00000020U
AnnaBridge	171:3a7713b1edbc	288	/**
AnnaBridge	171:3a7713b1edbc	289	* @}
AnnaBridge	171:3a7713b1edbc	290	*/
AnnaBridge	171:3a7713b1edbc	291
AnnaBridge	171:3a7713b1edbc	292	/** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
AnnaBridge	171:3a7713b1edbc	293	* @{
AnnaBridge	171:3a7713b1edbc	294	*/
AnnaBridge	171:3a7713b1edbc	295	#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE 0x00000040U
AnnaBridge	171:3a7713b1edbc	296	#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	297	/**
AnnaBridge	171:3a7713b1edbc	298	* @}
AnnaBridge	171:3a7713b1edbc	299	*/
AnnaBridge	171:3a7713b1edbc	300
AnnaBridge	171:3a7713b1edbc	301	/** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
AnnaBridge	171:3a7713b1edbc	302	* @{
AnnaBridge	171:3a7713b1edbc	303	*/
AnnaBridge	171:3a7713b1edbc	304	#define FSMC_BURST_ACCESS_MODE_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	305	#define FSMC_BURST_ACCESS_MODE_ENABLE 0x00000100U
AnnaBridge	171:3a7713b1edbc	306	/**
AnnaBridge	171:3a7713b1edbc	307	* @}
AnnaBridge	171:3a7713b1edbc	308	*/
AnnaBridge	171:3a7713b1edbc	309
AnnaBridge	171:3a7713b1edbc	310	/** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
AnnaBridge	171:3a7713b1edbc	311	* @{
AnnaBridge	171:3a7713b1edbc	312	*/
AnnaBridge	171:3a7713b1edbc	313	#define FSMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000U
AnnaBridge	171:3a7713b1edbc	314	#define FSMC_WAIT_SIGNAL_POLARITY_HIGH 0x00000200U
AnnaBridge	171:3a7713b1edbc	315	/**
AnnaBridge	171:3a7713b1edbc	316	* @}
AnnaBridge	171:3a7713b1edbc	317	*/
AnnaBridge	171:3a7713b1edbc	318
AnnaBridge	171:3a7713b1edbc	319	/** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
AnnaBridge	171:3a7713b1edbc	320	* @{
AnnaBridge	171:3a7713b1edbc	321	*/
AnnaBridge	171:3a7713b1edbc	322	#define FSMC_WRAP_MODE_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	323	#define FSMC_WRAP_MODE_ENABLE 0x00000400U
AnnaBridge	171:3a7713b1edbc	324	/**
AnnaBridge	171:3a7713b1edbc	325	* @}
AnnaBridge	171:3a7713b1edbc	326	*/
AnnaBridge	171:3a7713b1edbc	327
AnnaBridge	171:3a7713b1edbc	328	/** @defgroup FSMC_Wait_Timing FSMC Wait Timing
AnnaBridge	171:3a7713b1edbc	329	* @{
AnnaBridge	171:3a7713b1edbc	330	*/
AnnaBridge	171:3a7713b1edbc	331	#define FSMC_WAIT_TIMING_BEFORE_WS 0x00000000U
AnnaBridge	171:3a7713b1edbc	332	#define FSMC_WAIT_TIMING_DURING_WS 0x00000800U
AnnaBridge	171:3a7713b1edbc	333	/**
AnnaBridge	171:3a7713b1edbc	334	* @}
AnnaBridge	171:3a7713b1edbc	335	*/
AnnaBridge	171:3a7713b1edbc	336
AnnaBridge	171:3a7713b1edbc	337	/** @defgroup FSMC_Write_Operation FSMC Write Operation
AnnaBridge	171:3a7713b1edbc	338	* @{
AnnaBridge	171:3a7713b1edbc	339	*/
AnnaBridge	171:3a7713b1edbc	340	#define FSMC_WRITE_OPERATION_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	341	#define FSMC_WRITE_OPERATION_ENABLE 0x00001000U
AnnaBridge	171:3a7713b1edbc	342	/**
AnnaBridge	171:3a7713b1edbc	343	* @}
AnnaBridge	171:3a7713b1edbc	344	*/
AnnaBridge	171:3a7713b1edbc	345
AnnaBridge	171:3a7713b1edbc	346	/** @defgroup FSMC_Wait_Signal FSMC Wait Signal
AnnaBridge	171:3a7713b1edbc	347	* @{
AnnaBridge	171:3a7713b1edbc	348	*/
AnnaBridge	171:3a7713b1edbc	349	#define FSMC_WAIT_SIGNAL_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	350	#define FSMC_WAIT_SIGNAL_ENABLE 0x00002000U
AnnaBridge	171:3a7713b1edbc	351	/**
AnnaBridge	171:3a7713b1edbc	352	* @}
AnnaBridge	171:3a7713b1edbc	353	*/
AnnaBridge	171:3a7713b1edbc	354
AnnaBridge	171:3a7713b1edbc	355	/** @defgroup FSMC_Extended_Mode FSMC Extended Mode
AnnaBridge	171:3a7713b1edbc	356	* @{
AnnaBridge	171:3a7713b1edbc	357	*/
AnnaBridge	171:3a7713b1edbc	358	#define FSMC_EXTENDED_MODE_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	359	#define FSMC_EXTENDED_MODE_ENABLE 0x00004000U
AnnaBridge	171:3a7713b1edbc	360	/**
AnnaBridge	171:3a7713b1edbc	361	* @}
AnnaBridge	171:3a7713b1edbc	362	*/
AnnaBridge	171:3a7713b1edbc	363
AnnaBridge	171:3a7713b1edbc	364	/** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
AnnaBridge	171:3a7713b1edbc	365	* @{
AnnaBridge	171:3a7713b1edbc	366	*/
AnnaBridge	171:3a7713b1edbc	367	#define FSMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	368	#define FSMC_ASYNCHRONOUS_WAIT_ENABLE 0x00008000U
AnnaBridge	171:3a7713b1edbc	369	/**
AnnaBridge	171:3a7713b1edbc	370	* @}
AnnaBridge	171:3a7713b1edbc	371	*/
AnnaBridge	171:3a7713b1edbc	372
AnnaBridge	171:3a7713b1edbc	373	/** @defgroup FSMC_Write_Burst FSMC Write Burst
AnnaBridge	171:3a7713b1edbc	374	* @{
AnnaBridge	171:3a7713b1edbc	375	*/
AnnaBridge	171:3a7713b1edbc	376	#define FSMC_WRITE_BURST_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	377	#define FSMC_WRITE_BURST_ENABLE 0x00080000U
AnnaBridge	171:3a7713b1edbc	378	/**
AnnaBridge	171:3a7713b1edbc	379	* @}
AnnaBridge	171:3a7713b1edbc	380	*/
AnnaBridge	171:3a7713b1edbc	381
AnnaBridge	171:3a7713b1edbc	382	/** @defgroup FSMC_Continuous_Clock FSMC Continuous Clock
AnnaBridge	171:3a7713b1edbc	383	* @{
AnnaBridge	171:3a7713b1edbc	384	*/
AnnaBridge	171:3a7713b1edbc	385	#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY 0x00000000U
AnnaBridge	171:3a7713b1edbc	386	#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC 0x00100000U
AnnaBridge	171:3a7713b1edbc	387	/**
AnnaBridge	171:3a7713b1edbc	388	* @}
AnnaBridge	171:3a7713b1edbc	389	*/
AnnaBridge	171:3a7713b1edbc	390
AnnaBridge	171:3a7713b1edbc	391	/** @defgroup FSMC_Access_Mode FSMC Access Mode
AnnaBridge	171:3a7713b1edbc	392	* @{
AnnaBridge	171:3a7713b1edbc	393	*/
AnnaBridge	171:3a7713b1edbc	394	#define FSMC_ACCESS_MODE_A 0x00000000U
AnnaBridge	171:3a7713b1edbc	395	#define FSMC_ACCESS_MODE_B 0x10000000U
AnnaBridge	171:3a7713b1edbc	396	#define FSMC_ACCESS_MODE_C 0x20000000U
AnnaBridge	171:3a7713b1edbc	397	#define FSMC_ACCESS_MODE_D 0x30000000U
AnnaBridge	171:3a7713b1edbc	398	/**
AnnaBridge	171:3a7713b1edbc	399	* @}
AnnaBridge	171:3a7713b1edbc	400	*/
AnnaBridge	171:3a7713b1edbc	401	/**
AnnaBridge	171:3a7713b1edbc	402	* @}
AnnaBridge	171:3a7713b1edbc	403	*/
AnnaBridge	171:3a7713b1edbc	404
AnnaBridge	171:3a7713b1edbc	405	/** @defgroup FSMC_LL_NAND_Controller FSMC NAND and PCCARD Controller
AnnaBridge	171:3a7713b1edbc	406	* @{
AnnaBridge	171:3a7713b1edbc	407	*/
AnnaBridge	171:3a7713b1edbc	408	/** @defgroup FSMC_NAND_Bank FSMC NAND Bank
AnnaBridge	171:3a7713b1edbc	409	* @{
AnnaBridge	171:3a7713b1edbc	410	*/
AnnaBridge	171:3a7713b1edbc	411	#define FSMC_NAND_BANK2 0x00000010U
AnnaBridge	171:3a7713b1edbc	412	#define FSMC_NAND_BANK3 0x00000100U
AnnaBridge	171:3a7713b1edbc	413	/**
AnnaBridge	171:3a7713b1edbc	414	* @}
AnnaBridge	171:3a7713b1edbc	415	*/
AnnaBridge	171:3a7713b1edbc	416
AnnaBridge	171:3a7713b1edbc	417	/** @defgroup FSMC_Wait_feature FSMC Wait feature
AnnaBridge	171:3a7713b1edbc	418	* @{
AnnaBridge	171:3a7713b1edbc	419	*/
AnnaBridge	171:3a7713b1edbc	420	#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	421	#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE 0x00000002U
AnnaBridge	171:3a7713b1edbc	422	/**
AnnaBridge	171:3a7713b1edbc	423	* @}
AnnaBridge	171:3a7713b1edbc	424	*/
AnnaBridge	171:3a7713b1edbc	425
AnnaBridge	171:3a7713b1edbc	426	/** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type
AnnaBridge	171:3a7713b1edbc	427	* @{
AnnaBridge	171:3a7713b1edbc	428	*/
AnnaBridge	171:3a7713b1edbc	429	#define FSMC_PCR_MEMORY_TYPE_PCCARD 0x00000000U
AnnaBridge	171:3a7713b1edbc	430	#define FSMC_PCR_MEMORY_TYPE_NAND 0x00000008U
AnnaBridge	171:3a7713b1edbc	431	/**
AnnaBridge	171:3a7713b1edbc	432	* @}
AnnaBridge	171:3a7713b1edbc	433	*/
AnnaBridge	171:3a7713b1edbc	434
AnnaBridge	171:3a7713b1edbc	435	/** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width
AnnaBridge	171:3a7713b1edbc	436	* @{
AnnaBridge	171:3a7713b1edbc	437	*/
AnnaBridge	171:3a7713b1edbc	438	#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 0x00000000U
AnnaBridge	171:3a7713b1edbc	439	#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 0x00000010U
AnnaBridge	171:3a7713b1edbc	440	/**
AnnaBridge	171:3a7713b1edbc	441	* @}
AnnaBridge	171:3a7713b1edbc	442	*/
AnnaBridge	171:3a7713b1edbc	443
AnnaBridge	171:3a7713b1edbc	444	/** @defgroup FSMC_ECC FSMC ECC
AnnaBridge	171:3a7713b1edbc	445	* @{
AnnaBridge	171:3a7713b1edbc	446	*/
AnnaBridge	171:3a7713b1edbc	447	#define FSMC_NAND_ECC_DISABLE 0x00000000U
AnnaBridge	171:3a7713b1edbc	448	#define FSMC_NAND_ECC_ENABLE 0x00000040U
AnnaBridge	171:3a7713b1edbc	449	/**
AnnaBridge	171:3a7713b1edbc	450	* @}
AnnaBridge	171:3a7713b1edbc	451	*/
AnnaBridge	171:3a7713b1edbc	452
AnnaBridge	171:3a7713b1edbc	453	/** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size
AnnaBridge	171:3a7713b1edbc	454	* @{
AnnaBridge	171:3a7713b1edbc	455	*/
AnnaBridge	171:3a7713b1edbc	456	#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE 0x00000000U
AnnaBridge	171:3a7713b1edbc	457	#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE 0x00020000U
AnnaBridge	171:3a7713b1edbc	458	#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE 0x00040000U
AnnaBridge	171:3a7713b1edbc	459	#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE 0x00060000U
AnnaBridge	171:3a7713b1edbc	460	#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE 0x00080000U
AnnaBridge	171:3a7713b1edbc	461	#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE 0x000A0000U
AnnaBridge	171:3a7713b1edbc	462	/**
AnnaBridge	171:3a7713b1edbc	463	* @}
AnnaBridge	171:3a7713b1edbc	464	*/
AnnaBridge	171:3a7713b1edbc	465	/**
AnnaBridge	171:3a7713b1edbc	466	* @}
AnnaBridge	171:3a7713b1edbc	467	*/
AnnaBridge	171:3a7713b1edbc	468
AnnaBridge	171:3a7713b1edbc	469	/** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition
AnnaBridge	171:3a7713b1edbc	470	* @{
AnnaBridge	171:3a7713b1edbc	471	*/
AnnaBridge	171:3a7713b1edbc	472	#define FSMC_IT_RISING_EDGE 0x00000008U
AnnaBridge	171:3a7713b1edbc	473	#define FSMC_IT_LEVEL 0x00000010U
AnnaBridge	171:3a7713b1edbc	474	#define FSMC_IT_FALLING_EDGE 0x00000020U
AnnaBridge	171:3a7713b1edbc	475	#define FSMC_IT_REFRESH_ERROR 0x00004000U
AnnaBridge	171:3a7713b1edbc	476	/**
AnnaBridge	171:3a7713b1edbc	477	* @}
AnnaBridge	171:3a7713b1edbc	478	*/
AnnaBridge	171:3a7713b1edbc	479
AnnaBridge	171:3a7713b1edbc	480	/** @defgroup FSMC_LL_Flag_definition FSMC Flag definition
AnnaBridge	171:3a7713b1edbc	481	* @{
AnnaBridge	171:3a7713b1edbc	482	*/
AnnaBridge	171:3a7713b1edbc	483	#define FSMC_FLAG_RISING_EDGE 0x00000001U
AnnaBridge	171:3a7713b1edbc	484	#define FSMC_FLAG_LEVEL 0x00000002U
AnnaBridge	171:3a7713b1edbc	485	#define FSMC_FLAG_FALLING_EDGE 0x00000004U
AnnaBridge	171:3a7713b1edbc	486	#define FSMC_FLAG_FEMPT 0x00000040U
AnnaBridge	171:3a7713b1edbc	487	/**
AnnaBridge	171:3a7713b1edbc	488	* @}
AnnaBridge	171:3a7713b1edbc	489	*/
AnnaBridge	171:3a7713b1edbc	490
AnnaBridge	171:3a7713b1edbc	491	/** @defgroup FSMC_LL_Alias_definition FSMC Alias definition
AnnaBridge	171:3a7713b1edbc	492	* @{
AnnaBridge	171:3a7713b1edbc	493	*/
AnnaBridge	171:3a7713b1edbc	494	#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
AnnaBridge	171:3a7713b1edbc	495	#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
AnnaBridge	171:3a7713b1edbc	496	#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
AnnaBridge	171:3a7713b1edbc	497	#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
AnnaBridge	171:3a7713b1edbc	498
AnnaBridge	171:3a7713b1edbc	499	#define FSMC_NORSRAM_DEVICE FSMC_Bank1
AnnaBridge	171:3a7713b1edbc	500	#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
AnnaBridge	171:3a7713b1edbc	501	#define FSMC_NAND_DEVICE FSMC_Bank2_3
AnnaBridge	171:3a7713b1edbc	502	#define FSMC_PCCARD_DEVICE FSMC_Bank4
AnnaBridge	171:3a7713b1edbc	503
AnnaBridge	171:3a7713b1edbc	504	/**
AnnaBridge	171:3a7713b1edbc	505	* @}
AnnaBridge	171:3a7713b1edbc	506	*/
AnnaBridge	171:3a7713b1edbc	507
AnnaBridge	171:3a7713b1edbc	508	/**
AnnaBridge	171:3a7713b1edbc	509	* @}
AnnaBridge	171:3a7713b1edbc	510	*/
AnnaBridge	171:3a7713b1edbc	511
AnnaBridge	171:3a7713b1edbc	512	/* Private macro -------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	513	/** @defgroup FSMC_LL_Private_Macros FSMC Private Macros
AnnaBridge	171:3a7713b1edbc	514	* @{
AnnaBridge	171:3a7713b1edbc	515	*/
AnnaBridge	171:3a7713b1edbc	516
AnnaBridge	171:3a7713b1edbc	517	/** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Exported Macros
AnnaBridge	171:3a7713b1edbc	518	* @brief macros to handle NOR device enable/disable and read/write operations
AnnaBridge	171:3a7713b1edbc	519	* @{
AnnaBridge	171:3a7713b1edbc	520	*/
AnnaBridge	171:3a7713b1edbc	521	/**
AnnaBridge	171:3a7713b1edbc	522	* @brief Enable the NORSRAM device access.
AnnaBridge	171:3a7713b1edbc	523	* @param __INSTANCE__: FSMC_NORSRAM Instance
AnnaBridge	171:3a7713b1edbc	524	* @param __BANK__: FSMC_NORSRAM Bank
AnnaBridge	171:3a7713b1edbc	525	* @retval none
AnnaBridge	171:3a7713b1edbc	526	*/
AnnaBridge	171:3a7713b1edbc	527	#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FSMC_BCR1_MBKEN)
AnnaBridge	171:3a7713b1edbc	528
AnnaBridge	171:3a7713b1edbc	529	/**
AnnaBridge	171:3a7713b1edbc	530	* @brief Disable the NORSRAM device access.
AnnaBridge	171:3a7713b1edbc	531	* @param __INSTANCE__: FSMC_NORSRAM Instance
AnnaBridge	171:3a7713b1edbc	532	* @param __BANK__: FSMC_NORSRAM Bank
AnnaBridge	171:3a7713b1edbc	533	* @retval none
AnnaBridge	171:3a7713b1edbc	534	*/
AnnaBridge	171:3a7713b1edbc	535	#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN)
AnnaBridge	171:3a7713b1edbc	536	/**
AnnaBridge	171:3a7713b1edbc	537	* @}
AnnaBridge	171:3a7713b1edbc	538	*/
AnnaBridge	171:3a7713b1edbc	539
AnnaBridge	171:3a7713b1edbc	540	/** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros
AnnaBridge	171:3a7713b1edbc	541	* @brief macros to handle NAND device enable/disable
AnnaBridge	171:3a7713b1edbc	542	* @{
AnnaBridge	171:3a7713b1edbc	543	*/
AnnaBridge	171:3a7713b1edbc	544	/**
AnnaBridge	171:3a7713b1edbc	545	* @brief Enable the NAND device access.
AnnaBridge	171:3a7713b1edbc	546	* @param __INSTANCE__: FSMC_NAND Instance
AnnaBridge	171:3a7713b1edbc	547	* @param __BANK__: FSMC_NAND Bank
AnnaBridge	171:3a7713b1edbc	548	* @retval none
AnnaBridge	171:3a7713b1edbc	549	*/
AnnaBridge	171:3a7713b1edbc	550	#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 \|= FSMC_PCR2_PBKEN): \
AnnaBridge	171:3a7713b1edbc	551	((__INSTANCE__)->PCR3 \|= FSMC_PCR3_PBKEN))
AnnaBridge	171:3a7713b1edbc	552
AnnaBridge	171:3a7713b1edbc	553	/**
AnnaBridge	171:3a7713b1edbc	554	* @brief Disable the NAND device access.
AnnaBridge	171:3a7713b1edbc	555	* @param __INSTANCE__: FSMC_NAND Instance
AnnaBridge	171:3a7713b1edbc	556	* @param __BANK__: FSMC_NAND Bank
AnnaBridge	171:3a7713b1edbc	557	* @retval none
AnnaBridge	171:3a7713b1edbc	558	*/
AnnaBridge	171:3a7713b1edbc	559	#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \
AnnaBridge	171:3a7713b1edbc	560	((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN))
AnnaBridge	171:3a7713b1edbc	561	/**
AnnaBridge	171:3a7713b1edbc	562	* @}
AnnaBridge	171:3a7713b1edbc	563	*/
AnnaBridge	171:3a7713b1edbc	564
AnnaBridge	171:3a7713b1edbc	565	/** @defgroup FSMC_LL_PCCARD_Macros FSMC PCCARD Macros
AnnaBridge	171:3a7713b1edbc	566	* @brief macros to handle SRAM read/write operations
AnnaBridge	171:3a7713b1edbc	567	* @{
AnnaBridge	171:3a7713b1edbc	568	*/
AnnaBridge	171:3a7713b1edbc	569	/**
AnnaBridge	171:3a7713b1edbc	570	* @brief Enable the PCCARD device access.
AnnaBridge	171:3a7713b1edbc	571	* @param __INSTANCE__: FSMC_PCCARD Instance
AnnaBridge	171:3a7713b1edbc	572	* @retval none
AnnaBridge	171:3a7713b1edbc	573	*/
AnnaBridge	171:3a7713b1edbc	574	#define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 \|= FSMC_PCR4_PBKEN)
AnnaBridge	171:3a7713b1edbc	575
AnnaBridge	171:3a7713b1edbc	576	/**
AnnaBridge	171:3a7713b1edbc	577	* @brief Disable the PCCARD device access.
AnnaBridge	171:3a7713b1edbc	578	* @param __INSTANCE__: FSMC_PCCARD Instance
AnnaBridge	171:3a7713b1edbc	579	* @retval none
AnnaBridge	171:3a7713b1edbc	580	*/
AnnaBridge	171:3a7713b1edbc	581	#define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN)
AnnaBridge	171:3a7713b1edbc	582	/**
AnnaBridge	171:3a7713b1edbc	583	* @}
AnnaBridge	171:3a7713b1edbc	584	*/
AnnaBridge	171:3a7713b1edbc	585
AnnaBridge	171:3a7713b1edbc	586	/** @defgroup FSMC_LL_Flag_Interrupt_Macros FSMC Flag&Interrupt Macros
AnnaBridge	171:3a7713b1edbc	587	* @brief macros to handle FSMC flags and interrupts
AnnaBridge	171:3a7713b1edbc	588	* @{
AnnaBridge	171:3a7713b1edbc	589	*/
AnnaBridge	171:3a7713b1edbc	590	/**
AnnaBridge	171:3a7713b1edbc	591	* @brief Enable the NAND device interrupt.
AnnaBridge	171:3a7713b1edbc	592	* @param __INSTANCE__: FSMC_NAND Instance
AnnaBridge	171:3a7713b1edbc	593	* @param __BANK__: FSMC_NAND Bank
AnnaBridge	171:3a7713b1edbc	594	* @param __INTERRUPT__: FSMC_NAND interrupt
AnnaBridge	171:3a7713b1edbc	595	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	596	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
AnnaBridge	171:3a7713b1edbc	597	* @arg FSMC_IT_LEVEL: Interrupt level.
AnnaBridge	171:3a7713b1edbc	598	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
AnnaBridge	171:3a7713b1edbc	599	* @retval None
AnnaBridge	171:3a7713b1edbc	600	*/
AnnaBridge	171:3a7713b1edbc	601	#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 \|= (__INTERRUPT__)): \
AnnaBridge	171:3a7713b1edbc	602	((__INSTANCE__)->SR3 \|= (__INTERRUPT__)))
AnnaBridge	171:3a7713b1edbc	603
AnnaBridge	171:3a7713b1edbc	604	/**
AnnaBridge	171:3a7713b1edbc	605	* @brief Disable the NAND device interrupt.
AnnaBridge	171:3a7713b1edbc	606	* @param __INSTANCE__: FSMC_NAND Instance
AnnaBridge	171:3a7713b1edbc	607	* @param __BANK__: FSMC_NAND Bank
AnnaBridge	171:3a7713b1edbc	608	* @param __INTERRUPT__: FSMC_NAND interrupt
AnnaBridge	171:3a7713b1edbc	609	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	610	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
AnnaBridge	171:3a7713b1edbc	611	* @arg FSMC_IT_LEVEL: Interrupt level.
AnnaBridge	171:3a7713b1edbc	612	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
AnnaBridge	171:3a7713b1edbc	613	* @retval None
AnnaBridge	171:3a7713b1edbc	614	*/
AnnaBridge	171:3a7713b1edbc	615	#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
AnnaBridge	171:3a7713b1edbc	616	((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
AnnaBridge	171:3a7713b1edbc	617
AnnaBridge	171:3a7713b1edbc	618	/**
AnnaBridge	171:3a7713b1edbc	619	* @brief Get flag status of the NAND device.
AnnaBridge	171:3a7713b1edbc	620	* @param __INSTANCE__: FSMC_NAND Instance
AnnaBridge	171:3a7713b1edbc	621	* @param __BANK__ : FSMC_NAND Bank
AnnaBridge	171:3a7713b1edbc	622	* @param __FLAG__ : FSMC_NAND flag
AnnaBridge	171:3a7713b1edbc	623	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	624	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
AnnaBridge	171:3a7713b1edbc	625	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
AnnaBridge	171:3a7713b1edbc	626	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
AnnaBridge	171:3a7713b1edbc	627	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
AnnaBridge	171:3a7713b1edbc	628	* @retval The state of FLAG (SET or RESET).
AnnaBridge	171:3a7713b1edbc	629	*/
AnnaBridge	171:3a7713b1edbc	630	#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
AnnaBridge	171:3a7713b1edbc	631	(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
AnnaBridge	171:3a7713b1edbc	632	/**
AnnaBridge	171:3a7713b1edbc	633	* @brief Clear flag status of the NAND device.
AnnaBridge	171:3a7713b1edbc	634	* @param __INSTANCE__: FSMC_NAND Instance
AnnaBridge	171:3a7713b1edbc	635	* @param __BANK__: FSMC_NAND Bank
AnnaBridge	171:3a7713b1edbc	636	* @param __FLAG__: FSMC_NAND flag
AnnaBridge	171:3a7713b1edbc	637	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	638	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
AnnaBridge	171:3a7713b1edbc	639	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
AnnaBridge	171:3a7713b1edbc	640	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
AnnaBridge	171:3a7713b1edbc	641	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
AnnaBridge	171:3a7713b1edbc	642	* @retval None
AnnaBridge	171:3a7713b1edbc	643	*/
AnnaBridge	171:3a7713b1edbc	644	#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
AnnaBridge	171:3a7713b1edbc	645	((__INSTANCE__)->SR3 &= ~(__FLAG__)))
AnnaBridge	171:3a7713b1edbc	646	/**
AnnaBridge	171:3a7713b1edbc	647	* @brief Enable the PCCARD device interrupt.
AnnaBridge	171:3a7713b1edbc	648	* @param __INSTANCE__: FSMC_PCCARD Instance
AnnaBridge	171:3a7713b1edbc	649	* @param __INTERRUPT__: FSMC_PCCARD interrupt
AnnaBridge	171:3a7713b1edbc	650	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	651	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
AnnaBridge	171:3a7713b1edbc	652	* @arg FSMC_IT_LEVEL: Interrupt level.
AnnaBridge	171:3a7713b1edbc	653	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
AnnaBridge	171:3a7713b1edbc	654	* @retval None
AnnaBridge	171:3a7713b1edbc	655	*/
AnnaBridge	171:3a7713b1edbc	656	#define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 \|= (__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	657
AnnaBridge	171:3a7713b1edbc	658	/**
AnnaBridge	171:3a7713b1edbc	659	* @brief Disable the PCCARD device interrupt.
AnnaBridge	171:3a7713b1edbc	660	* @param __INSTANCE__: FSMC_PCCARD Instance
AnnaBridge	171:3a7713b1edbc	661	* @param __INTERRUPT__: FSMC_PCCARD interrupt
AnnaBridge	171:3a7713b1edbc	662	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	663	* @arg FSMC_IT_RISING_EDGE: Interrupt rising edge.
AnnaBridge	171:3a7713b1edbc	664	* @arg FSMC_IT_LEVEL: Interrupt level.
AnnaBridge	171:3a7713b1edbc	665	* @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge.
AnnaBridge	171:3a7713b1edbc	666	* @retval None
AnnaBridge	171:3a7713b1edbc	667	*/
AnnaBridge	171:3a7713b1edbc	668	#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	669
AnnaBridge	171:3a7713b1edbc	670	/**
AnnaBridge	171:3a7713b1edbc	671	* @brief Get flag status of the PCCARD device.
AnnaBridge	171:3a7713b1edbc	672	* @param __INSTANCE__: FSMC_PCCARD Instance
AnnaBridge	171:3a7713b1edbc	673	* @param __FLAG__: FSMC_PCCARD flag
AnnaBridge	171:3a7713b1edbc	674	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	675	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
AnnaBridge	171:3a7713b1edbc	676	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
AnnaBridge	171:3a7713b1edbc	677	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
AnnaBridge	171:3a7713b1edbc	678	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
AnnaBridge	171:3a7713b1edbc	679	* @retval The state of FLAG (SET or RESET).
AnnaBridge	171:3a7713b1edbc	680	*/
AnnaBridge	171:3a7713b1edbc	681	#define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
AnnaBridge	171:3a7713b1edbc	682
AnnaBridge	171:3a7713b1edbc	683	/**
AnnaBridge	171:3a7713b1edbc	684	* @brief Clear flag status of the PCCARD device.
AnnaBridge	171:3a7713b1edbc	685	* @param __INSTANCE__: FSMC_PCCARD Instance
AnnaBridge	171:3a7713b1edbc	686	* @param __FLAG__: FSMC_PCCARD flag
AnnaBridge	171:3a7713b1edbc	687	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	688	* @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
AnnaBridge	171:3a7713b1edbc	689	* @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
AnnaBridge	171:3a7713b1edbc	690	* @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
AnnaBridge	171:3a7713b1edbc	691	* @arg FSMC_FLAG_FEMPT: FIFO empty flag.
AnnaBridge	171:3a7713b1edbc	692	* @retval None
AnnaBridge	171:3a7713b1edbc	693	*/
AnnaBridge	171:3a7713b1edbc	694	#define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
AnnaBridge	171:3a7713b1edbc	695	/**
AnnaBridge	171:3a7713b1edbc	696	* @}
AnnaBridge	171:3a7713b1edbc	697	*/
AnnaBridge	171:3a7713b1edbc	698
AnnaBridge	171:3a7713b1edbc	699	/** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
AnnaBridge	171:3a7713b1edbc	700	* @{
AnnaBridge	171:3a7713b1edbc	701	*/
AnnaBridge	171:3a7713b1edbc	702	#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) \|\| \
AnnaBridge	171:3a7713b1edbc	703	((__BANK__) == FSMC_NORSRAM_BANK2) \|\| \
AnnaBridge	171:3a7713b1edbc	704	((__BANK__) == FSMC_NORSRAM_BANK3) \|\| \
AnnaBridge	171:3a7713b1edbc	705	((__BANK__) == FSMC_NORSRAM_BANK4))
AnnaBridge	171:3a7713b1edbc	706
AnnaBridge	171:3a7713b1edbc	707	#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	708	((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
AnnaBridge	171:3a7713b1edbc	709
AnnaBridge	171:3a7713b1edbc	710	#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) \|\| \
AnnaBridge	171:3a7713b1edbc	711	((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)\|\| \
AnnaBridge	171:3a7713b1edbc	712	((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
AnnaBridge	171:3a7713b1edbc	713
AnnaBridge	171:3a7713b1edbc	714	#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
AnnaBridge	171:3a7713b1edbc	715	((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
AnnaBridge	171:3a7713b1edbc	716	((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
AnnaBridge	171:3a7713b1edbc	717
AnnaBridge	171:3a7713b1edbc	718	#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) \|\| \
AnnaBridge	171:3a7713b1edbc	719	((__MODE__) == FSMC_ACCESS_MODE_B) \|\| \
AnnaBridge	171:3a7713b1edbc	720	((__MODE__) == FSMC_ACCESS_MODE_C) \|\| \
AnnaBridge	171:3a7713b1edbc	721	((__MODE__) == FSMC_ACCESS_MODE_D))
AnnaBridge	171:3a7713b1edbc	722
AnnaBridge	171:3a7713b1edbc	723	#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) \|\| \
AnnaBridge	171:3a7713b1edbc	724	((BANK) == FSMC_NAND_BANK3))
AnnaBridge	171:3a7713b1edbc	725
AnnaBridge	171:3a7713b1edbc	726	#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	727	((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
AnnaBridge	171:3a7713b1edbc	728
AnnaBridge	171:3a7713b1edbc	729	#define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) \|\| \
AnnaBridge	171:3a7713b1edbc	730	((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
AnnaBridge	171:3a7713b1edbc	731
AnnaBridge	171:3a7713b1edbc	732	#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	733	((STATE) == FSMC_NAND_ECC_ENABLE))
AnnaBridge	171:3a7713b1edbc	734
AnnaBridge	171:3a7713b1edbc	735	#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
AnnaBridge	171:3a7713b1edbc	736	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
AnnaBridge	171:3a7713b1edbc	737	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
AnnaBridge	171:3a7713b1edbc	738	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
AnnaBridge	171:3a7713b1edbc	739	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
AnnaBridge	171:3a7713b1edbc	740	((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
AnnaBridge	171:3a7713b1edbc	741
AnnaBridge	171:3a7713b1edbc	742	#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255U)
AnnaBridge	171:3a7713b1edbc	743
AnnaBridge	171:3a7713b1edbc	744	#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255U)
AnnaBridge	171:3a7713b1edbc	745
AnnaBridge	171:3a7713b1edbc	746	#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255U)
AnnaBridge	171:3a7713b1edbc	747
AnnaBridge	171:3a7713b1edbc	748	#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255U)
AnnaBridge	171:3a7713b1edbc	749
AnnaBridge	171:3a7713b1edbc	750	#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255U)
AnnaBridge	171:3a7713b1edbc	751
AnnaBridge	171:3a7713b1edbc	752	#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255U)
AnnaBridge	171:3a7713b1edbc	753
AnnaBridge	171:3a7713b1edbc	754	#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
AnnaBridge	171:3a7713b1edbc	755
AnnaBridge	171:3a7713b1edbc	756	#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
AnnaBridge	171:3a7713b1edbc	757
AnnaBridge	171:3a7713b1edbc	758	#define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE)
AnnaBridge	171:3a7713b1edbc	759
AnnaBridge	171:3a7713b1edbc	760	#define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE)
AnnaBridge	171:3a7713b1edbc	761
AnnaBridge	171:3a7713b1edbc	762	#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	763	((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
AnnaBridge	171:3a7713b1edbc	764
AnnaBridge	171:3a7713b1edbc	765	#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
AnnaBridge	171:3a7713b1edbc	766	((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
AnnaBridge	171:3a7713b1edbc	767
AnnaBridge	171:3a7713b1edbc	768	#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	769	((__MODE__) == FSMC_WRAP_MODE_ENABLE))
AnnaBridge	171:3a7713b1edbc	770
AnnaBridge	171:3a7713b1edbc	771	#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) \|\| \
AnnaBridge	171:3a7713b1edbc	772	((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
AnnaBridge	171:3a7713b1edbc	773
AnnaBridge	171:3a7713b1edbc	774	#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	775	((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
AnnaBridge	171:3a7713b1edbc	776
AnnaBridge	171:3a7713b1edbc	777	#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	778	((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
AnnaBridge	171:3a7713b1edbc	779
AnnaBridge	171:3a7713b1edbc	780	#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	781	((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
AnnaBridge	171:3a7713b1edbc	782
AnnaBridge	171:3a7713b1edbc	783	#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	784	((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
AnnaBridge	171:3a7713b1edbc	785
AnnaBridge	171:3a7713b1edbc	786	#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
AnnaBridge	171:3a7713b1edbc	787
AnnaBridge	171:3a7713b1edbc	788	#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) \|\| \
AnnaBridge	171:3a7713b1edbc	789	((__BURST__) == FSMC_WRITE_BURST_ENABLE))
AnnaBridge	171:3a7713b1edbc	790
AnnaBridge	171:3a7713b1edbc	791	#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
AnnaBridge	171:3a7713b1edbc	792
AnnaBridge	171:3a7713b1edbc	793	#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
AnnaBridge	171:3a7713b1edbc	794
AnnaBridge	171:3a7713b1edbc	795	#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
AnnaBridge	171:3a7713b1edbc	796
AnnaBridge	171:3a7713b1edbc	797	#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
AnnaBridge	171:3a7713b1edbc	798
AnnaBridge	171:3a7713b1edbc	799	#define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
AnnaBridge	171:3a7713b1edbc	800	((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
AnnaBridge	171:3a7713b1edbc	801
AnnaBridge	171:3a7713b1edbc	802	#define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U))
AnnaBridge	171:3a7713b1edbc	803
AnnaBridge	171:3a7713b1edbc	804	/**
AnnaBridge	171:3a7713b1edbc	805	* @}
AnnaBridge	171:3a7713b1edbc	806	*/
AnnaBridge	171:3a7713b1edbc	807	/**
AnnaBridge	171:3a7713b1edbc	808	* @}
AnnaBridge	171:3a7713b1edbc	809	*/
AnnaBridge	171:3a7713b1edbc	810
AnnaBridge	171:3a7713b1edbc	811	/* Private functions ---------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	812	/** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions
AnnaBridge	171:3a7713b1edbc	813	* @{
AnnaBridge	171:3a7713b1edbc	814	*/
AnnaBridge	171:3a7713b1edbc	815
AnnaBridge	171:3a7713b1edbc	816	/** @defgroup FSMC_LL_NORSRAM NOR SRAM
AnnaBridge	171:3a7713b1edbc	817	* @{
AnnaBridge	171:3a7713b1edbc	818	*/
AnnaBridge	171:3a7713b1edbc	819
AnnaBridge	171:3a7713b1edbc	820	/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
AnnaBridge	171:3a7713b1edbc	821	* @{
AnnaBridge	171:3a7713b1edbc	822	*/
AnnaBridge	171:3a7713b1edbc	823	HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef Device, FSMC_NORSRAM_InitTypeDef Init);
AnnaBridge	171:3a7713b1edbc	824	HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef Device, FSMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
AnnaBridge	171:3a7713b1edbc	825	HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef Device, FSMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
AnnaBridge	171:3a7713b1edbc	826	HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef Device, FSMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
AnnaBridge	171:3a7713b1edbc	827	/**
AnnaBridge	171:3a7713b1edbc	828	* @}
AnnaBridge	171:3a7713b1edbc	829	*/
AnnaBridge	171:3a7713b1edbc	830
AnnaBridge	171:3a7713b1edbc	831	/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
AnnaBridge	171:3a7713b1edbc	832	* @{
AnnaBridge	171:3a7713b1edbc	833	*/
AnnaBridge	171:3a7713b1edbc	834	HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge	171:3a7713b1edbc	835	HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
AnnaBridge	171:3a7713b1edbc	836	/**
AnnaBridge	171:3a7713b1edbc	837	* @}
AnnaBridge	171:3a7713b1edbc	838	*/
AnnaBridge	171:3a7713b1edbc	839	/**
AnnaBridge	171:3a7713b1edbc	840	* @}
AnnaBridge	171:3a7713b1edbc	841	*/
AnnaBridge	171:3a7713b1edbc	842
AnnaBridge	171:3a7713b1edbc	843	/** @defgroup FSMC_LL_NAND NAND
AnnaBridge	171:3a7713b1edbc	844	* @{
AnnaBridge	171:3a7713b1edbc	845	*/
AnnaBridge	171:3a7713b1edbc	846	/** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
AnnaBridge	171:3a7713b1edbc	847	* @{
AnnaBridge	171:3a7713b1edbc	848	*/
AnnaBridge	171:3a7713b1edbc	849	HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef Device, FSMC_NAND_InitTypeDef Init);
AnnaBridge	171:3a7713b1edbc	850	HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
AnnaBridge	171:3a7713b1edbc	851	HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
AnnaBridge	171:3a7713b1edbc	852	HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
AnnaBridge	171:3a7713b1edbc	853	/**
AnnaBridge	171:3a7713b1edbc	854	* @}
AnnaBridge	171:3a7713b1edbc	855	*/
AnnaBridge	171:3a7713b1edbc	856
AnnaBridge	171:3a7713b1edbc	857	/** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions
AnnaBridge	171:3a7713b1edbc	858	* @{
AnnaBridge	171:3a7713b1edbc	859	*/
AnnaBridge	171:3a7713b1edbc	860	HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
AnnaBridge	171:3a7713b1edbc	861	HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
AnnaBridge	171:3a7713b1edbc	862	HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
AnnaBridge	171:3a7713b1edbc	863	/**
AnnaBridge	171:3a7713b1edbc	864	* @}
AnnaBridge	171:3a7713b1edbc	865	*/
AnnaBridge	171:3a7713b1edbc	866	/**
AnnaBridge	171:3a7713b1edbc	867	* @}
AnnaBridge	171:3a7713b1edbc	868	*/
AnnaBridge	171:3a7713b1edbc	869
AnnaBridge	171:3a7713b1edbc	870	/** @defgroup FSMC_LL_PCCARD PCCARD
AnnaBridge	171:3a7713b1edbc	871	* @{
AnnaBridge	171:3a7713b1edbc	872	*/
AnnaBridge	171:3a7713b1edbc	873	/** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
AnnaBridge	171:3a7713b1edbc	874	* @{
AnnaBridge	171:3a7713b1edbc	875	*/
AnnaBridge	171:3a7713b1edbc	876	HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef Device, FSMC_PCCARD_InitTypeDef Init);
AnnaBridge	171:3a7713b1edbc	877	HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing);
AnnaBridge	171:3a7713b1edbc	878	HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing);
AnnaBridge	171:3a7713b1edbc	879	HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef Device, FSMC_NAND_PCC_TimingTypeDef Timing);
AnnaBridge	171:3a7713b1edbc	880	HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
AnnaBridge	171:3a7713b1edbc	881	/**
AnnaBridge	171:3a7713b1edbc	882	* @}
AnnaBridge	171:3a7713b1edbc	883	*/
AnnaBridge	171:3a7713b1edbc	884	/**
AnnaBridge	171:3a7713b1edbc	885	* @}
AnnaBridge	171:3a7713b1edbc	886	*/
AnnaBridge	171:3a7713b1edbc	887
AnnaBridge	171:3a7713b1edbc	888	/**
AnnaBridge	171:3a7713b1edbc	889	* @}
AnnaBridge	171:3a7713b1edbc	890	*/
AnnaBridge	171:3a7713b1edbc	891
AnnaBridge	171:3a7713b1edbc	892
AnnaBridge	171:3a7713b1edbc	893	/**
AnnaBridge	171:3a7713b1edbc	894	* @}
AnnaBridge	171:3a7713b1edbc	895	*/
AnnaBridge	171:3a7713b1edbc	896
AnnaBridge	171:3a7713b1edbc	897	/**
AnnaBridge	171:3a7713b1edbc	898	* @}
AnnaBridge	171:3a7713b1edbc	899	*/
AnnaBridge	171:3a7713b1edbc	900
AnnaBridge	171:3a7713b1edbc	901	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	902	}
AnnaBridge	171:3a7713b1edbc	903	#endif
AnnaBridge	171:3a7713b1edbc	904
AnnaBridge	171:3a7713b1edbc	905	#endif /* __STM32F2xx_LL_FSMC_H */
AnnaBridge	171:3a7713b1edbc	906
AnnaBridge	171:3a7713b1edbc	907	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/