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TARGET_NUCLEO_F207ZG/TOOLCHAIN_GCC_ARM/stm32f2xx_ll_cortex.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 145:64910690c574 1 /**
AnnaBridge 145:64910690c574 2 ******************************************************************************
AnnaBridge 145:64910690c574 3 * @file stm32f2xx_ll_cortex.h
AnnaBridge 145:64910690c574 4 * @author MCD Application Team
AnnaBridge 145:64910690c574 5 * @version V1.2.1
AnnaBridge 145:64910690c574 6 * @date 14-April-2017
AnnaBridge 145:64910690c574 7 * @brief Header file of CORTEX LL module.
AnnaBridge 145:64910690c574 8 @verbatim
AnnaBridge 145:64910690c574 9 ==============================================================================
AnnaBridge 145:64910690c574 10 ##### How to use this driver #####
AnnaBridge 145:64910690c574 11 ==============================================================================
AnnaBridge 145:64910690c574 12 [..]
AnnaBridge 145:64910690c574 13 The LL CORTEX driver contains a set of generic APIs that can be
AnnaBridge 145:64910690c574 14 used by user:
AnnaBridge 145:64910690c574 15 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
AnnaBridge 145:64910690c574 16 functions
AnnaBridge 145:64910690c574 17 (+) Low power mode configuration (SCB register of Cortex-MCU)
AnnaBridge 145:64910690c574 18 (+) MPU API to configure and enable regions
AnnaBridge 145:64910690c574 19 (MPU services provided only on some devices)
AnnaBridge 145:64910690c574 20 (+) API to access to MCU info (CPUID register)
AnnaBridge 145:64910690c574 21 (+) API to enable fault handler (SHCSR accesses)
AnnaBridge 145:64910690c574 22
AnnaBridge 145:64910690c574 23 @endverbatim
AnnaBridge 145:64910690c574 24 ******************************************************************************
AnnaBridge 145:64910690c574 25 * @attention
AnnaBridge 145:64910690c574 26 *
AnnaBridge 145:64910690c574 27 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 145:64910690c574 28 *
AnnaBridge 145:64910690c574 29 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 145:64910690c574 30 * are permitted provided that the following conditions are met:
AnnaBridge 145:64910690c574 31 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 145:64910690c574 32 * this list of conditions and the following disclaimer.
AnnaBridge 145:64910690c574 33 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 145:64910690c574 34 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 145:64910690c574 35 * and/or other materials provided with the distribution.
AnnaBridge 145:64910690c574 36 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 145:64910690c574 37 * may be used to endorse or promote products derived from this software
AnnaBridge 145:64910690c574 38 * without specific prior written permission.
AnnaBridge 145:64910690c574 39 *
AnnaBridge 145:64910690c574 40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 145:64910690c574 41 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 145:64910690c574 42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 145:64910690c574 43 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 145:64910690c574 44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 145:64910690c574 45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 145:64910690c574 46 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 145:64910690c574 47 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 145:64910690c574 48 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 145:64910690c574 49 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 145:64910690c574 50 *
AnnaBridge 145:64910690c574 51 ******************************************************************************
AnnaBridge 145:64910690c574 52 */
AnnaBridge 145:64910690c574 53
AnnaBridge 145:64910690c574 54 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 145:64910690c574 55 #ifndef __STM32F2xx_LL_CORTEX_H
AnnaBridge 145:64910690c574 56 #define __STM32F2xx_LL_CORTEX_H
AnnaBridge 145:64910690c574 57
AnnaBridge 145:64910690c574 58 #ifdef __cplusplus
AnnaBridge 145:64910690c574 59 extern "C" {
AnnaBridge 145:64910690c574 60 #endif
AnnaBridge 145:64910690c574 61
AnnaBridge 145:64910690c574 62 /* Includes ------------------------------------------------------------------*/
AnnaBridge 145:64910690c574 63 #include "stm32f2xx.h"
AnnaBridge 145:64910690c574 64
AnnaBridge 145:64910690c574 65 /** @addtogroup STM32F2xx_LL_Driver
AnnaBridge 145:64910690c574 66 * @{
AnnaBridge 145:64910690c574 67 */
AnnaBridge 145:64910690c574 68
AnnaBridge 145:64910690c574 69 /** @defgroup CORTEX_LL CORTEX
AnnaBridge 145:64910690c574 70 * @{
AnnaBridge 145:64910690c574 71 */
AnnaBridge 145:64910690c574 72
AnnaBridge 145:64910690c574 73 /* Private types -------------------------------------------------------------*/
AnnaBridge 145:64910690c574 74 /* Private variables ---------------------------------------------------------*/
AnnaBridge 145:64910690c574 75
AnnaBridge 145:64910690c574 76 /* Private constants ---------------------------------------------------------*/
AnnaBridge 145:64910690c574 77
AnnaBridge 145:64910690c574 78 /* Private macros ------------------------------------------------------------*/
AnnaBridge 145:64910690c574 79
AnnaBridge 145:64910690c574 80 /* Exported types ------------------------------------------------------------*/
AnnaBridge 145:64910690c574 81 /* Exported constants --------------------------------------------------------*/
AnnaBridge 145:64910690c574 82 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
AnnaBridge 145:64910690c574 83 * @{
AnnaBridge 145:64910690c574 84 */
AnnaBridge 145:64910690c574 85
AnnaBridge 145:64910690c574 86 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
AnnaBridge 145:64910690c574 87 * @{
AnnaBridge 145:64910690c574 88 */
AnnaBridge 145:64910690c574 89 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
AnnaBridge 145:64910690c574 90 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
AnnaBridge 145:64910690c574 91 /**
AnnaBridge 145:64910690c574 92 * @}
AnnaBridge 145:64910690c574 93 */
AnnaBridge 145:64910690c574 94
AnnaBridge 145:64910690c574 95 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
AnnaBridge 145:64910690c574 96 * @{
AnnaBridge 145:64910690c574 97 */
AnnaBridge 145:64910690c574 98 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
AnnaBridge 145:64910690c574 99 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
AnnaBridge 145:64910690c574 100 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
AnnaBridge 145:64910690c574 101 /**
AnnaBridge 145:64910690c574 102 * @}
AnnaBridge 145:64910690c574 103 */
AnnaBridge 145:64910690c574 104
AnnaBridge 145:64910690c574 105 #if __MPU_PRESENT
AnnaBridge 145:64910690c574 106
AnnaBridge 145:64910690c574 107 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
AnnaBridge 145:64910690c574 108 * @{
AnnaBridge 145:64910690c574 109 */
AnnaBridge 145:64910690c574 110 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
AnnaBridge 145:64910690c574 111 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
AnnaBridge 145:64910690c574 112 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
AnnaBridge 145:64910690c574 113 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
AnnaBridge 145:64910690c574 114 /**
AnnaBridge 145:64910690c574 115 * @}
AnnaBridge 145:64910690c574 116 */
AnnaBridge 145:64910690c574 117
AnnaBridge 145:64910690c574 118 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
AnnaBridge 145:64910690c574 119 * @{
AnnaBridge 145:64910690c574 120 */
AnnaBridge 145:64910690c574 121 #define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
AnnaBridge 145:64910690c574 122 #define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
AnnaBridge 145:64910690c574 123 #define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
AnnaBridge 145:64910690c574 124 #define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
AnnaBridge 145:64910690c574 125 #define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
AnnaBridge 145:64910690c574 126 #define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
AnnaBridge 145:64910690c574 127 #define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
AnnaBridge 145:64910690c574 128 #define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
AnnaBridge 145:64910690c574 129 /**
AnnaBridge 145:64910690c574 130 * @}
AnnaBridge 145:64910690c574 131 */
AnnaBridge 145:64910690c574 132
AnnaBridge 145:64910690c574 133 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
AnnaBridge 145:64910690c574 134 * @{
AnnaBridge 145:64910690c574 135 */
AnnaBridge 145:64910690c574 136 #define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
AnnaBridge 145:64910690c574 137 #define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
AnnaBridge 145:64910690c574 138 #define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
AnnaBridge 145:64910690c574 139 #define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
AnnaBridge 145:64910690c574 140 #define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
AnnaBridge 145:64910690c574 141 #define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
AnnaBridge 145:64910690c574 142 #define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
AnnaBridge 145:64910690c574 143 #define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
AnnaBridge 145:64910690c574 144 #define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
AnnaBridge 145:64910690c574 145 #define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
AnnaBridge 145:64910690c574 146 #define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
AnnaBridge 145:64910690c574 147 #define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
AnnaBridge 145:64910690c574 148 #define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
AnnaBridge 145:64910690c574 149 #define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
AnnaBridge 145:64910690c574 150 #define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
AnnaBridge 145:64910690c574 151 #define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
AnnaBridge 145:64910690c574 152 #define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
AnnaBridge 145:64910690c574 153 #define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
AnnaBridge 145:64910690c574 154 #define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
AnnaBridge 145:64910690c574 155 #define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
AnnaBridge 145:64910690c574 156 #define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
AnnaBridge 145:64910690c574 157 #define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
AnnaBridge 145:64910690c574 158 #define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
AnnaBridge 145:64910690c574 159 #define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
AnnaBridge 145:64910690c574 160 #define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
AnnaBridge 145:64910690c574 161 #define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
AnnaBridge 145:64910690c574 162 #define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
AnnaBridge 145:64910690c574 163 #define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
AnnaBridge 145:64910690c574 164 /**
AnnaBridge 145:64910690c574 165 * @}
AnnaBridge 145:64910690c574 166 */
AnnaBridge 145:64910690c574 167
AnnaBridge 145:64910690c574 168 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
AnnaBridge 145:64910690c574 169 * @{
AnnaBridge 145:64910690c574 170 */
AnnaBridge 145:64910690c574 171 #define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
AnnaBridge 145:64910690c574 172 #define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
AnnaBridge 145:64910690c574 173 #define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
AnnaBridge 145:64910690c574 174 #define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
AnnaBridge 145:64910690c574 175 #define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
AnnaBridge 145:64910690c574 176 #define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
AnnaBridge 145:64910690c574 177 /**
AnnaBridge 145:64910690c574 178 * @}
AnnaBridge 145:64910690c574 179 */
AnnaBridge 145:64910690c574 180
AnnaBridge 145:64910690c574 181 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
AnnaBridge 145:64910690c574 182 * @{
AnnaBridge 145:64910690c574 183 */
AnnaBridge 145:64910690c574 184 #define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
AnnaBridge 145:64910690c574 185 #define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
AnnaBridge 145:64910690c574 186 #define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
AnnaBridge 145:64910690c574 187 #define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
AnnaBridge 145:64910690c574 188 /**
AnnaBridge 145:64910690c574 189 * @}
AnnaBridge 145:64910690c574 190 */
AnnaBridge 145:64910690c574 191
AnnaBridge 145:64910690c574 192 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
AnnaBridge 145:64910690c574 193 * @{
AnnaBridge 145:64910690c574 194 */
AnnaBridge 145:64910690c574 195 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
AnnaBridge 145:64910690c574 196 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
AnnaBridge 145:64910690c574 197 /**
AnnaBridge 145:64910690c574 198 * @}
AnnaBridge 145:64910690c574 199 */
AnnaBridge 145:64910690c574 200
AnnaBridge 145:64910690c574 201 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
AnnaBridge 145:64910690c574 202 * @{
AnnaBridge 145:64910690c574 203 */
AnnaBridge 145:64910690c574 204 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
AnnaBridge 145:64910690c574 205 #define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
AnnaBridge 145:64910690c574 206 /**
AnnaBridge 145:64910690c574 207 * @}
AnnaBridge 145:64910690c574 208 */
AnnaBridge 145:64910690c574 209
AnnaBridge 145:64910690c574 210 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
AnnaBridge 145:64910690c574 211 * @{
AnnaBridge 145:64910690c574 212 */
AnnaBridge 145:64910690c574 213 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
AnnaBridge 145:64910690c574 214 #define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
AnnaBridge 145:64910690c574 215 /**
AnnaBridge 145:64910690c574 216 * @}
AnnaBridge 145:64910690c574 217 */
AnnaBridge 145:64910690c574 218
AnnaBridge 145:64910690c574 219 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
AnnaBridge 145:64910690c574 220 * @{
AnnaBridge 145:64910690c574 221 */
AnnaBridge 145:64910690c574 222 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
AnnaBridge 145:64910690c574 223 #define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
AnnaBridge 145:64910690c574 224 /**
AnnaBridge 145:64910690c574 225 * @}
AnnaBridge 145:64910690c574 226 */
AnnaBridge 145:64910690c574 227 #endif /* __MPU_PRESENT */
AnnaBridge 145:64910690c574 228 /**
AnnaBridge 145:64910690c574 229 * @}
AnnaBridge 145:64910690c574 230 */
AnnaBridge 145:64910690c574 231
AnnaBridge 145:64910690c574 232 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 145:64910690c574 233
AnnaBridge 145:64910690c574 234 /* Exported functions --------------------------------------------------------*/
AnnaBridge 145:64910690c574 235 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
AnnaBridge 145:64910690c574 236 * @{
AnnaBridge 145:64910690c574 237 */
AnnaBridge 145:64910690c574 238
AnnaBridge 145:64910690c574 239 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
AnnaBridge 145:64910690c574 240 * @{
AnnaBridge 145:64910690c574 241 */
AnnaBridge 145:64910690c574 242
AnnaBridge 145:64910690c574 243 /**
AnnaBridge 145:64910690c574 244 * @brief This function checks if the Systick counter flag is active or not.
AnnaBridge 145:64910690c574 245 * @note It can be used in timeout function on application side.
AnnaBridge 145:64910690c574 246 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
AnnaBridge 145:64910690c574 247 * @retval State of bit (1 or 0).
AnnaBridge 145:64910690c574 248 */
AnnaBridge 145:64910690c574 249 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
AnnaBridge 145:64910690c574 250 {
AnnaBridge 145:64910690c574 251 return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
AnnaBridge 145:64910690c574 252 }
AnnaBridge 145:64910690c574 253
AnnaBridge 145:64910690c574 254 /**
AnnaBridge 145:64910690c574 255 * @brief Configures the SysTick clock source
AnnaBridge 145:64910690c574 256 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
AnnaBridge 145:64910690c574 257 * @param Source This parameter can be one of the following values:
AnnaBridge 145:64910690c574 258 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
AnnaBridge 145:64910690c574 259 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
AnnaBridge 145:64910690c574 260 * @retval None
AnnaBridge 145:64910690c574 261 */
AnnaBridge 145:64910690c574 262 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
AnnaBridge 145:64910690c574 263 {
AnnaBridge 145:64910690c574 264 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
AnnaBridge 145:64910690c574 265 {
AnnaBridge 145:64910690c574 266 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
AnnaBridge 145:64910690c574 267 }
AnnaBridge 145:64910690c574 268 else
AnnaBridge 145:64910690c574 269 {
AnnaBridge 145:64910690c574 270 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
AnnaBridge 145:64910690c574 271 }
AnnaBridge 145:64910690c574 272 }
AnnaBridge 145:64910690c574 273
AnnaBridge 145:64910690c574 274 /**
AnnaBridge 145:64910690c574 275 * @brief Get the SysTick clock source
AnnaBridge 145:64910690c574 276 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
AnnaBridge 145:64910690c574 277 * @retval Returned value can be one of the following values:
AnnaBridge 145:64910690c574 278 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
AnnaBridge 145:64910690c574 279 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
AnnaBridge 145:64910690c574 280 */
AnnaBridge 145:64910690c574 281 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
AnnaBridge 145:64910690c574 282 {
AnnaBridge 145:64910690c574 283 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
AnnaBridge 145:64910690c574 284 }
AnnaBridge 145:64910690c574 285
AnnaBridge 145:64910690c574 286 /**
AnnaBridge 145:64910690c574 287 * @brief Enable SysTick exception request
AnnaBridge 145:64910690c574 288 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
AnnaBridge 145:64910690c574 289 * @retval None
AnnaBridge 145:64910690c574 290 */
AnnaBridge 145:64910690c574 291 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
AnnaBridge 145:64910690c574 292 {
AnnaBridge 145:64910690c574 293 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
AnnaBridge 145:64910690c574 294 }
AnnaBridge 145:64910690c574 295
AnnaBridge 145:64910690c574 296 /**
AnnaBridge 145:64910690c574 297 * @brief Disable SysTick exception request
AnnaBridge 145:64910690c574 298 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
AnnaBridge 145:64910690c574 299 * @retval None
AnnaBridge 145:64910690c574 300 */
AnnaBridge 145:64910690c574 301 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
AnnaBridge 145:64910690c574 302 {
AnnaBridge 145:64910690c574 303 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
AnnaBridge 145:64910690c574 304 }
AnnaBridge 145:64910690c574 305
AnnaBridge 145:64910690c574 306 /**
AnnaBridge 145:64910690c574 307 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
AnnaBridge 145:64910690c574 308 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
AnnaBridge 145:64910690c574 309 * @retval State of bit (1 or 0).
AnnaBridge 145:64910690c574 310 */
AnnaBridge 145:64910690c574 311 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
AnnaBridge 145:64910690c574 312 {
AnnaBridge 145:64910690c574 313 return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
AnnaBridge 145:64910690c574 314 }
AnnaBridge 145:64910690c574 315
AnnaBridge 145:64910690c574 316 /**
AnnaBridge 145:64910690c574 317 * @}
AnnaBridge 145:64910690c574 318 */
AnnaBridge 145:64910690c574 319
AnnaBridge 145:64910690c574 320 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
AnnaBridge 145:64910690c574 321 * @{
AnnaBridge 145:64910690c574 322 */
AnnaBridge 145:64910690c574 323
AnnaBridge 145:64910690c574 324 /**
AnnaBridge 145:64910690c574 325 * @brief Processor uses sleep as its low power mode
AnnaBridge 145:64910690c574 326 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
AnnaBridge 145:64910690c574 327 * @retval None
AnnaBridge 145:64910690c574 328 */
AnnaBridge 145:64910690c574 329 __STATIC_INLINE void LL_LPM_EnableSleep(void)
AnnaBridge 145:64910690c574 330 {
AnnaBridge 145:64910690c574 331 /* Clear SLEEPDEEP bit of Cortex System Control Register */
AnnaBridge 145:64910690c574 332 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
AnnaBridge 145:64910690c574 333 }
AnnaBridge 145:64910690c574 334
AnnaBridge 145:64910690c574 335 /**
AnnaBridge 145:64910690c574 336 * @brief Processor uses deep sleep as its low power mode
AnnaBridge 145:64910690c574 337 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
AnnaBridge 145:64910690c574 338 * @retval None
AnnaBridge 145:64910690c574 339 */
AnnaBridge 145:64910690c574 340 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
AnnaBridge 145:64910690c574 341 {
AnnaBridge 145:64910690c574 342 /* Set SLEEPDEEP bit of Cortex System Control Register */
AnnaBridge 145:64910690c574 343 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
AnnaBridge 145:64910690c574 344 }
AnnaBridge 145:64910690c574 345
AnnaBridge 145:64910690c574 346 /**
AnnaBridge 145:64910690c574 347 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
AnnaBridge 145:64910690c574 348 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
AnnaBridge 145:64910690c574 349 * empty main application.
AnnaBridge 145:64910690c574 350 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
AnnaBridge 145:64910690c574 351 * @retval None
AnnaBridge 145:64910690c574 352 */
AnnaBridge 145:64910690c574 353 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
AnnaBridge 145:64910690c574 354 {
AnnaBridge 145:64910690c574 355 /* Set SLEEPONEXIT bit of Cortex System Control Register */
AnnaBridge 145:64910690c574 356 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
AnnaBridge 145:64910690c574 357 }
AnnaBridge 145:64910690c574 358
AnnaBridge 145:64910690c574 359 /**
AnnaBridge 145:64910690c574 360 * @brief Do not sleep when returning to Thread mode.
AnnaBridge 145:64910690c574 361 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
AnnaBridge 145:64910690c574 362 * @retval None
AnnaBridge 145:64910690c574 363 */
AnnaBridge 145:64910690c574 364 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
AnnaBridge 145:64910690c574 365 {
AnnaBridge 145:64910690c574 366 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
AnnaBridge 145:64910690c574 367 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
AnnaBridge 145:64910690c574 368 }
AnnaBridge 145:64910690c574 369
AnnaBridge 145:64910690c574 370 /**
AnnaBridge 145:64910690c574 371 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
AnnaBridge 145:64910690c574 372 * processor.
AnnaBridge 145:64910690c574 373 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
AnnaBridge 145:64910690c574 374 * @retval None
AnnaBridge 145:64910690c574 375 */
AnnaBridge 145:64910690c574 376 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
AnnaBridge 145:64910690c574 377 {
AnnaBridge 145:64910690c574 378 /* Set SEVEONPEND bit of Cortex System Control Register */
AnnaBridge 145:64910690c574 379 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
AnnaBridge 145:64910690c574 380 }
AnnaBridge 145:64910690c574 381
AnnaBridge 145:64910690c574 382 /**
AnnaBridge 145:64910690c574 383 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
AnnaBridge 145:64910690c574 384 * excluded
AnnaBridge 145:64910690c574 385 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
AnnaBridge 145:64910690c574 386 * @retval None
AnnaBridge 145:64910690c574 387 */
AnnaBridge 145:64910690c574 388 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
AnnaBridge 145:64910690c574 389 {
AnnaBridge 145:64910690c574 390 /* Clear SEVEONPEND bit of Cortex System Control Register */
AnnaBridge 145:64910690c574 391 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
AnnaBridge 145:64910690c574 392 }
AnnaBridge 145:64910690c574 393
AnnaBridge 145:64910690c574 394 /**
AnnaBridge 145:64910690c574 395 * @}
AnnaBridge 145:64910690c574 396 */
AnnaBridge 145:64910690c574 397
AnnaBridge 145:64910690c574 398 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER
AnnaBridge 145:64910690c574 399 * @{
AnnaBridge 145:64910690c574 400 */
AnnaBridge 145:64910690c574 401
AnnaBridge 145:64910690c574 402 /**
AnnaBridge 145:64910690c574 403 * @brief Enable a fault in System handler control register (SHCSR)
AnnaBridge 145:64910690c574 404 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
AnnaBridge 145:64910690c574 405 * @param Fault This parameter can be a combination of the following values:
AnnaBridge 145:64910690c574 406 * @arg @ref LL_HANDLER_FAULT_USG
AnnaBridge 145:64910690c574 407 * @arg @ref LL_HANDLER_FAULT_BUS
AnnaBridge 145:64910690c574 408 * @arg @ref LL_HANDLER_FAULT_MEM
AnnaBridge 145:64910690c574 409 * @retval None
AnnaBridge 145:64910690c574 410 */
AnnaBridge 145:64910690c574 411 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
AnnaBridge 145:64910690c574 412 {
AnnaBridge 145:64910690c574 413 /* Enable the system handler fault */
AnnaBridge 145:64910690c574 414 SET_BIT(SCB->SHCSR, Fault);
AnnaBridge 145:64910690c574 415 }
AnnaBridge 145:64910690c574 416
AnnaBridge 145:64910690c574 417 /**
AnnaBridge 145:64910690c574 418 * @brief Disable a fault in System handler control register (SHCSR)
AnnaBridge 145:64910690c574 419 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
AnnaBridge 145:64910690c574 420 * @param Fault This parameter can be a combination of the following values:
AnnaBridge 145:64910690c574 421 * @arg @ref LL_HANDLER_FAULT_USG
AnnaBridge 145:64910690c574 422 * @arg @ref LL_HANDLER_FAULT_BUS
AnnaBridge 145:64910690c574 423 * @arg @ref LL_HANDLER_FAULT_MEM
AnnaBridge 145:64910690c574 424 * @retval None
AnnaBridge 145:64910690c574 425 */
AnnaBridge 145:64910690c574 426 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
AnnaBridge 145:64910690c574 427 {
AnnaBridge 145:64910690c574 428 /* Disable the system handler fault */
AnnaBridge 145:64910690c574 429 CLEAR_BIT(SCB->SHCSR, Fault);
AnnaBridge 145:64910690c574 430 }
AnnaBridge 145:64910690c574 431
AnnaBridge 145:64910690c574 432 /**
AnnaBridge 145:64910690c574 433 * @}
AnnaBridge 145:64910690c574 434 */
AnnaBridge 145:64910690c574 435
AnnaBridge 145:64910690c574 436 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
AnnaBridge 145:64910690c574 437 * @{
AnnaBridge 145:64910690c574 438 */
AnnaBridge 145:64910690c574 439
AnnaBridge 145:64910690c574 440 /**
AnnaBridge 145:64910690c574 441 * @brief Get Implementer code
AnnaBridge 145:64910690c574 442 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
AnnaBridge 145:64910690c574 443 * @retval Value should be equal to 0x41 for ARM
AnnaBridge 145:64910690c574 444 */
AnnaBridge 145:64910690c574 445 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
AnnaBridge 145:64910690c574 446 {
AnnaBridge 145:64910690c574 447 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
AnnaBridge 145:64910690c574 448 }
AnnaBridge 145:64910690c574 449
AnnaBridge 145:64910690c574 450 /**
AnnaBridge 145:64910690c574 451 * @brief Get Variant number (The r value in the rnpn product revision identifier)
AnnaBridge 145:64910690c574 452 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
AnnaBridge 145:64910690c574 453 * @retval Value between 0 and 255 (0x1: revision 1, 0x2: revision 2)
AnnaBridge 145:64910690c574 454 */
AnnaBridge 145:64910690c574 455 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
AnnaBridge 145:64910690c574 456 {
AnnaBridge 145:64910690c574 457 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
AnnaBridge 145:64910690c574 458 }
AnnaBridge 145:64910690c574 459
AnnaBridge 145:64910690c574 460 /**
AnnaBridge 145:64910690c574 461 * @brief Get Constant number
AnnaBridge 145:64910690c574 462 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
AnnaBridge 145:64910690c574 463 * @retval Value should be equal to 0xF for Cortex-M3 devices
AnnaBridge 145:64910690c574 464 */
AnnaBridge 145:64910690c574 465 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
AnnaBridge 145:64910690c574 466 {
AnnaBridge 145:64910690c574 467 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
AnnaBridge 145:64910690c574 468 }
AnnaBridge 145:64910690c574 469
AnnaBridge 145:64910690c574 470 /**
AnnaBridge 145:64910690c574 471 * @brief Get Part number
AnnaBridge 145:64910690c574 472 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
AnnaBridge 145:64910690c574 473 * @retval Value should be equal to 0xC23 for Cortex-M3
AnnaBridge 145:64910690c574 474 */
AnnaBridge 145:64910690c574 475 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
AnnaBridge 145:64910690c574 476 {
AnnaBridge 145:64910690c574 477 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
AnnaBridge 145:64910690c574 478 }
AnnaBridge 145:64910690c574 479
AnnaBridge 145:64910690c574 480 /**
AnnaBridge 145:64910690c574 481 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
AnnaBridge 145:64910690c574 482 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
AnnaBridge 145:64910690c574 483 * @retval Value between 0 and 255 (0x0: patch 0, 0x1: patch 1)
AnnaBridge 145:64910690c574 484 */
AnnaBridge 145:64910690c574 485 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
AnnaBridge 145:64910690c574 486 {
AnnaBridge 145:64910690c574 487 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
AnnaBridge 145:64910690c574 488 }
AnnaBridge 145:64910690c574 489
AnnaBridge 145:64910690c574 490 /**
AnnaBridge 145:64910690c574 491 * @}
AnnaBridge 145:64910690c574 492 */
AnnaBridge 145:64910690c574 493
AnnaBridge 145:64910690c574 494 #if __MPU_PRESENT
AnnaBridge 145:64910690c574 495 /** @defgroup CORTEX_LL_EF_MPU MPU
AnnaBridge 145:64910690c574 496 * @{
AnnaBridge 145:64910690c574 497 */
AnnaBridge 145:64910690c574 498
AnnaBridge 145:64910690c574 499 /**
AnnaBridge 145:64910690c574 500 * @brief Enable MPU with input options
AnnaBridge 145:64910690c574 501 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
AnnaBridge 145:64910690c574 502 * @param Options This parameter can be one of the following values:
AnnaBridge 145:64910690c574 503 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
AnnaBridge 145:64910690c574 504 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
AnnaBridge 145:64910690c574 505 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
AnnaBridge 145:64910690c574 506 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
AnnaBridge 145:64910690c574 507 * @retval None
AnnaBridge 145:64910690c574 508 */
AnnaBridge 145:64910690c574 509 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
AnnaBridge 145:64910690c574 510 {
AnnaBridge 145:64910690c574 511 /* Enable the MPU*/
AnnaBridge 145:64910690c574 512 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
AnnaBridge 145:64910690c574 513 /* Ensure MPU settings take effects */
AnnaBridge 145:64910690c574 514 __DSB();
AnnaBridge 145:64910690c574 515 /* Sequence instruction fetches using update settings */
AnnaBridge 145:64910690c574 516 __ISB();
AnnaBridge 145:64910690c574 517 }
AnnaBridge 145:64910690c574 518
AnnaBridge 145:64910690c574 519 /**
AnnaBridge 145:64910690c574 520 * @brief Disable MPU
AnnaBridge 145:64910690c574 521 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
AnnaBridge 145:64910690c574 522 * @retval None
AnnaBridge 145:64910690c574 523 */
AnnaBridge 145:64910690c574 524 __STATIC_INLINE void LL_MPU_Disable(void)
AnnaBridge 145:64910690c574 525 {
AnnaBridge 145:64910690c574 526 /* Make sure outstanding transfers are done */
AnnaBridge 145:64910690c574 527 __DMB();
AnnaBridge 145:64910690c574 528 /* Disable MPU*/
AnnaBridge 145:64910690c574 529 WRITE_REG(MPU->CTRL, 0U);
AnnaBridge 145:64910690c574 530 }
AnnaBridge 145:64910690c574 531
AnnaBridge 145:64910690c574 532 /**
AnnaBridge 145:64910690c574 533 * @brief Check if MPU is enabled or not
AnnaBridge 145:64910690c574 534 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
AnnaBridge 145:64910690c574 535 * @retval State of bit (1 or 0).
AnnaBridge 145:64910690c574 536 */
AnnaBridge 145:64910690c574 537 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
AnnaBridge 145:64910690c574 538 {
AnnaBridge 145:64910690c574 539 return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
AnnaBridge 145:64910690c574 540 }
AnnaBridge 145:64910690c574 541
AnnaBridge 145:64910690c574 542 /**
AnnaBridge 145:64910690c574 543 * @brief Enable a MPU region
AnnaBridge 145:64910690c574 544 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
AnnaBridge 145:64910690c574 545 * @param Region This parameter can be one of the following values:
AnnaBridge 145:64910690c574 546 * @arg @ref LL_MPU_REGION_NUMBER0
AnnaBridge 145:64910690c574 547 * @arg @ref LL_MPU_REGION_NUMBER1
AnnaBridge 145:64910690c574 548 * @arg @ref LL_MPU_REGION_NUMBER2
AnnaBridge 145:64910690c574 549 * @arg @ref LL_MPU_REGION_NUMBER3
AnnaBridge 145:64910690c574 550 * @arg @ref LL_MPU_REGION_NUMBER4
AnnaBridge 145:64910690c574 551 * @arg @ref LL_MPU_REGION_NUMBER5
AnnaBridge 145:64910690c574 552 * @arg @ref LL_MPU_REGION_NUMBER6
AnnaBridge 145:64910690c574 553 * @arg @ref LL_MPU_REGION_NUMBER7
AnnaBridge 145:64910690c574 554 * @retval None
AnnaBridge 145:64910690c574 555 */
AnnaBridge 145:64910690c574 556 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
AnnaBridge 145:64910690c574 557 {
AnnaBridge 145:64910690c574 558 /* Set Region number */
AnnaBridge 145:64910690c574 559 WRITE_REG(MPU->RNR, Region);
AnnaBridge 145:64910690c574 560 /* Enable the MPU region */
AnnaBridge 145:64910690c574 561 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
AnnaBridge 145:64910690c574 562 }
AnnaBridge 145:64910690c574 563
AnnaBridge 145:64910690c574 564 /**
AnnaBridge 145:64910690c574 565 * @brief Configure and enable a region
AnnaBridge 145:64910690c574 566 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
AnnaBridge 145:64910690c574 567 * MPU_RBAR REGION LL_MPU_ConfigRegion\n
AnnaBridge 145:64910690c574 568 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n
AnnaBridge 145:64910690c574 569 * MPU_RASR XN LL_MPU_ConfigRegion\n
AnnaBridge 145:64910690c574 570 * MPU_RASR AP LL_MPU_ConfigRegion\n
AnnaBridge 145:64910690c574 571 * MPU_RASR S LL_MPU_ConfigRegion\n
AnnaBridge 145:64910690c574 572 * MPU_RASR C LL_MPU_ConfigRegion\n
AnnaBridge 145:64910690c574 573 * MPU_RASR B LL_MPU_ConfigRegion\n
AnnaBridge 145:64910690c574 574 * MPU_RASR SIZE LL_MPU_ConfigRegion
AnnaBridge 145:64910690c574 575 * @param Region This parameter can be one of the following values:
AnnaBridge 145:64910690c574 576 * @arg @ref LL_MPU_REGION_NUMBER0
AnnaBridge 145:64910690c574 577 * @arg @ref LL_MPU_REGION_NUMBER1
AnnaBridge 145:64910690c574 578 * @arg @ref LL_MPU_REGION_NUMBER2
AnnaBridge 145:64910690c574 579 * @arg @ref LL_MPU_REGION_NUMBER3
AnnaBridge 145:64910690c574 580 * @arg @ref LL_MPU_REGION_NUMBER4
AnnaBridge 145:64910690c574 581 * @arg @ref LL_MPU_REGION_NUMBER5
AnnaBridge 145:64910690c574 582 * @arg @ref LL_MPU_REGION_NUMBER6
AnnaBridge 145:64910690c574 583 * @arg @ref LL_MPU_REGION_NUMBER7
AnnaBridge 145:64910690c574 584 * @param Address Value of region base address
AnnaBridge 145:64910690c574 585 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
AnnaBridge 145:64910690c574 586 * @param Attributes This parameter can be a combination of the following values:
AnnaBridge 145:64910690c574 587 * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
AnnaBridge 145:64910690c574 588 * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
AnnaBridge 145:64910690c574 589 * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
AnnaBridge 145:64910690c574 590 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
AnnaBridge 145:64910690c574 591 * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
AnnaBridge 145:64910690c574 592 * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
AnnaBridge 145:64910690c574 593 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
AnnaBridge 145:64910690c574 594 * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
AnnaBridge 145:64910690c574 595 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
AnnaBridge 145:64910690c574 596 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
AnnaBridge 145:64910690c574 597 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
AnnaBridge 145:64910690c574 598 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
AnnaBridge 145:64910690c574 599 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
AnnaBridge 145:64910690c574 600 * @retval None
AnnaBridge 145:64910690c574 601 */
AnnaBridge 145:64910690c574 602 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
AnnaBridge 145:64910690c574 603 {
AnnaBridge 145:64910690c574 604 /* Set Region number */
AnnaBridge 145:64910690c574 605 WRITE_REG(MPU->RNR, Region);
AnnaBridge 145:64910690c574 606 /* Set base address */
AnnaBridge 145:64910690c574 607 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
AnnaBridge 145:64910690c574 608 /* Configure MPU */
AnnaBridge 145:64910690c574 609 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
AnnaBridge 145:64910690c574 610 }
AnnaBridge 145:64910690c574 611
AnnaBridge 145:64910690c574 612 /**
AnnaBridge 145:64910690c574 613 * @brief Disable a region
AnnaBridge 145:64910690c574 614 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
AnnaBridge 145:64910690c574 615 * MPU_RASR ENABLE LL_MPU_DisableRegion
AnnaBridge 145:64910690c574 616 * @param Region This parameter can be one of the following values:
AnnaBridge 145:64910690c574 617 * @arg @ref LL_MPU_REGION_NUMBER0
AnnaBridge 145:64910690c574 618 * @arg @ref LL_MPU_REGION_NUMBER1
AnnaBridge 145:64910690c574 619 * @arg @ref LL_MPU_REGION_NUMBER2
AnnaBridge 145:64910690c574 620 * @arg @ref LL_MPU_REGION_NUMBER3
AnnaBridge 145:64910690c574 621 * @arg @ref LL_MPU_REGION_NUMBER4
AnnaBridge 145:64910690c574 622 * @arg @ref LL_MPU_REGION_NUMBER5
AnnaBridge 145:64910690c574 623 * @arg @ref LL_MPU_REGION_NUMBER6
AnnaBridge 145:64910690c574 624 * @arg @ref LL_MPU_REGION_NUMBER7
AnnaBridge 145:64910690c574 625 * @retval None
AnnaBridge 145:64910690c574 626 */
AnnaBridge 145:64910690c574 627 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
AnnaBridge 145:64910690c574 628 {
AnnaBridge 145:64910690c574 629 /* Set Region number */
AnnaBridge 145:64910690c574 630 WRITE_REG(MPU->RNR, Region);
AnnaBridge 145:64910690c574 631 /* Disable the MPU region */
AnnaBridge 145:64910690c574 632 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
AnnaBridge 145:64910690c574 633 }
AnnaBridge 145:64910690c574 634
AnnaBridge 145:64910690c574 635 /**
AnnaBridge 145:64910690c574 636 * @}
AnnaBridge 145:64910690c574 637 */
AnnaBridge 145:64910690c574 638
AnnaBridge 145:64910690c574 639 #endif /* __MPU_PRESENT */
AnnaBridge 145:64910690c574 640 /**
AnnaBridge 145:64910690c574 641 * @}
AnnaBridge 145:64910690c574 642 */
AnnaBridge 145:64910690c574 643
AnnaBridge 145:64910690c574 644 /**
AnnaBridge 145:64910690c574 645 * @}
AnnaBridge 145:64910690c574 646 */
AnnaBridge 145:64910690c574 647
AnnaBridge 145:64910690c574 648 /**
AnnaBridge 145:64910690c574 649 * @}
AnnaBridge 145:64910690c574 650 */
AnnaBridge 145:64910690c574 651
AnnaBridge 145:64910690c574 652 #ifdef __cplusplus
AnnaBridge 145:64910690c574 653 }
AnnaBridge 145:64910690c574 654 #endif
AnnaBridge 145:64910690c574 655
AnnaBridge 145:64910690c574 656 #endif /* __STM32F2xx_LL_CORTEX_H */
AnnaBridge 145:64910690c574 657
AnnaBridge 145:64910690c574 658 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/