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TARGET_NUCLEO_F207ZG/TOOLCHAIN_GCC_ARM/stm32f2xx_hal_rcc_ex.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /** |
| AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32f2xx_hal_rcc_ex.h |
| AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
| AnnaBridge | 171:3a7713b1edbc | 5 | * @version V1.2.1 |
| AnnaBridge | 171:3a7713b1edbc | 6 | * @date 14-April-2017 |
| AnnaBridge | 171:3a7713b1edbc | 7 | * @brief Header file of RCC HAL Extension module. |
| AnnaBridge | 171:3a7713b1edbc | 8 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 9 | * @attention |
| AnnaBridge | 171:3a7713b1edbc | 10 | * |
| AnnaBridge | 171:3a7713b1edbc | 11 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 171:3a7713b1edbc | 12 | * |
| AnnaBridge | 171:3a7713b1edbc | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 171:3a7713b1edbc | 14 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 171:3a7713b1edbc | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 171:3a7713b1edbc | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 18 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 171:3a7713b1edbc | 19 | * and/or other materials provided with the distribution. |
| AnnaBridge | 171:3a7713b1edbc | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 171:3a7713b1edbc | 21 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 171:3a7713b1edbc | 22 | * without specific prior written permission. |
| AnnaBridge | 171:3a7713b1edbc | 23 | * |
| AnnaBridge | 171:3a7713b1edbc | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 171:3a7713b1edbc | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 171:3a7713b1edbc | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 171:3a7713b1edbc | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 171:3a7713b1edbc | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 171:3a7713b1edbc | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 171:3a7713b1edbc | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 171:3a7713b1edbc | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 171:3a7713b1edbc | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 171:3a7713b1edbc | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 171:3a7713b1edbc | 34 | * |
| AnnaBridge | 171:3a7713b1edbc | 35 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 36 | */ |
| AnnaBridge | 171:3a7713b1edbc | 37 | |
| AnnaBridge | 171:3a7713b1edbc | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 39 | #ifndef __STM32F2xx_HAL_RCC_EX_H |
| AnnaBridge | 171:3a7713b1edbc | 40 | #define __STM32F2xx_HAL_RCC_EX_H |
| AnnaBridge | 171:3a7713b1edbc | 41 | |
| AnnaBridge | 171:3a7713b1edbc | 42 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 43 | extern "C" { |
| AnnaBridge | 171:3a7713b1edbc | 44 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 45 | |
| AnnaBridge | 171:3a7713b1edbc | 46 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 47 | #include "stm32f2xx_hal_def.h" |
| AnnaBridge | 171:3a7713b1edbc | 48 | |
| AnnaBridge | 171:3a7713b1edbc | 49 | /** @addtogroup STM32F2xx_HAL_Driver |
| AnnaBridge | 171:3a7713b1edbc | 50 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 51 | */ |
| AnnaBridge | 171:3a7713b1edbc | 52 | |
| AnnaBridge | 171:3a7713b1edbc | 53 | /** @addtogroup RCCEx |
| AnnaBridge | 171:3a7713b1edbc | 54 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 55 | */ |
| AnnaBridge | 171:3a7713b1edbc | 56 | |
| AnnaBridge | 171:3a7713b1edbc | 57 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 58 | /** @defgroup RCCEx_Exported_Types RCCEx Exported Types |
| AnnaBridge | 171:3a7713b1edbc | 59 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 60 | */ |
| AnnaBridge | 171:3a7713b1edbc | 61 | /** |
| AnnaBridge | 171:3a7713b1edbc | 62 | * @brief PLLI2S Clock structure definition |
| AnnaBridge | 171:3a7713b1edbc | 63 | */ |
| AnnaBridge | 171:3a7713b1edbc | 64 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 65 | { |
| AnnaBridge | 171:3a7713b1edbc | 66 | uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. |
| AnnaBridge | 171:3a7713b1edbc | 67 | This parameter must be a number between Min_Data = 192 and Max_Data = 432. |
| AnnaBridge | 171:3a7713b1edbc | 68 | This parameter will be used only when PLLI2S is selected as Clock Source I2S */ |
| AnnaBridge | 171:3a7713b1edbc | 69 | |
| AnnaBridge | 171:3a7713b1edbc | 70 | uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. |
| AnnaBridge | 171:3a7713b1edbc | 71 | This parameter must be a number between Min_Data = 2 and Max_Data = 7. |
| AnnaBridge | 171:3a7713b1edbc | 72 | This parameter will be used only when PLLI2S is selected as Clock Source I2S */ |
| AnnaBridge | 171:3a7713b1edbc | 73 | |
| AnnaBridge | 171:3a7713b1edbc | 74 | }RCC_PLLI2SInitTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 75 | |
| AnnaBridge | 171:3a7713b1edbc | 76 | /** |
| AnnaBridge | 171:3a7713b1edbc | 77 | * @brief RCC extended clocks structure definition |
| AnnaBridge | 171:3a7713b1edbc | 78 | */ |
| AnnaBridge | 171:3a7713b1edbc | 79 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 80 | { |
| AnnaBridge | 171:3a7713b1edbc | 81 | uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. |
| AnnaBridge | 171:3a7713b1edbc | 82 | This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ |
| AnnaBridge | 171:3a7713b1edbc | 83 | |
| AnnaBridge | 171:3a7713b1edbc | 84 | RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. |
| AnnaBridge | 171:3a7713b1edbc | 85 | This parameter will be used only when PLLI2S is selected as Clock Source I2S */ |
| AnnaBridge | 171:3a7713b1edbc | 86 | |
| AnnaBridge | 171:3a7713b1edbc | 87 | uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection. |
| AnnaBridge | 171:3a7713b1edbc | 88 | This parameter can be a value of @ref RCC_RTC_Clock_Source */ |
| AnnaBridge | 171:3a7713b1edbc | 89 | |
| AnnaBridge | 171:3a7713b1edbc | 90 | uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. |
| AnnaBridge | 171:3a7713b1edbc | 91 | This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */ |
| AnnaBridge | 171:3a7713b1edbc | 92 | |
| AnnaBridge | 171:3a7713b1edbc | 93 | }RCC_PeriphCLKInitTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 94 | /** |
| AnnaBridge | 171:3a7713b1edbc | 95 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 96 | */ |
| AnnaBridge | 171:3a7713b1edbc | 97 | |
| AnnaBridge | 171:3a7713b1edbc | 98 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 99 | /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants |
| AnnaBridge | 171:3a7713b1edbc | 100 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 101 | */ |
| AnnaBridge | 171:3a7713b1edbc | 102 | |
| AnnaBridge | 171:3a7713b1edbc | 103 | /** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection |
| AnnaBridge | 171:3a7713b1edbc | 104 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 105 | */ |
| AnnaBridge | 171:3a7713b1edbc | 106 | #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001) |
| AnnaBridge | 171:3a7713b1edbc | 107 | #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000002) |
| AnnaBridge | 171:3a7713b1edbc | 108 | #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000004) |
| AnnaBridge | 171:3a7713b1edbc | 109 | #define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000008) |
| AnnaBridge | 171:3a7713b1edbc | 110 | |
| AnnaBridge | 171:3a7713b1edbc | 111 | /** |
| AnnaBridge | 171:3a7713b1edbc | 112 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 113 | */ |
| AnnaBridge | 171:3a7713b1edbc | 114 | |
| AnnaBridge | 171:3a7713b1edbc | 115 | /** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection |
| AnnaBridge | 171:3a7713b1edbc | 116 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 117 | */ |
| AnnaBridge | 171:3a7713b1edbc | 118 | #define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00) |
| AnnaBridge | 171:3a7713b1edbc | 119 | #define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01) |
| AnnaBridge | 171:3a7713b1edbc | 120 | /** |
| AnnaBridge | 171:3a7713b1edbc | 121 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 122 | */ |
| AnnaBridge | 171:3a7713b1edbc | 123 | |
| AnnaBridge | 171:3a7713b1edbc | 124 | /** |
| AnnaBridge | 171:3a7713b1edbc | 125 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 126 | */ |
| AnnaBridge | 171:3a7713b1edbc | 127 | |
| AnnaBridge | 171:3a7713b1edbc | 128 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 129 | /** @defgroup RCCEx_Exported_Macros RCC Exported Macros |
| AnnaBridge | 171:3a7713b1edbc | 130 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 131 | */ |
| AnnaBridge | 171:3a7713b1edbc | 132 | |
| AnnaBridge | 171:3a7713b1edbc | 133 | /** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable |
| AnnaBridge | 171:3a7713b1edbc | 134 | * @brief Enables or disables the AHB1 peripheral clock. |
| AnnaBridge | 171:3a7713b1edbc | 135 | * @note After reset, the peripheral clock (used for registers read/write access) |
| AnnaBridge | 171:3a7713b1edbc | 136 | * is disabled and the application software has to enable this clock before |
| AnnaBridge | 171:3a7713b1edbc | 137 | * using it. |
| AnnaBridge | 171:3a7713b1edbc | 138 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 139 | */ |
| AnnaBridge | 171:3a7713b1edbc | 140 | #if defined(STM32F207xx) || defined(STM32F217xx) |
| AnnaBridge | 171:3a7713b1edbc | 141 | #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ |
| AnnaBridge | 171:3a7713b1edbc | 142 | __IO uint32_t tmpreg = 0x00; \ |
| AnnaBridge | 171:3a7713b1edbc | 143 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ |
| AnnaBridge | 171:3a7713b1edbc | 144 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 171:3a7713b1edbc | 145 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ |
| AnnaBridge | 171:3a7713b1edbc | 146 | UNUSED(tmpreg); \ |
| AnnaBridge | 171:3a7713b1edbc | 147 | } while(0) |
| AnnaBridge | 171:3a7713b1edbc | 148 | #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ |
| AnnaBridge | 171:3a7713b1edbc | 149 | __IO uint32_t tmpreg = 0x00; \ |
| AnnaBridge | 171:3a7713b1edbc | 150 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ |
| AnnaBridge | 171:3a7713b1edbc | 151 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 171:3a7713b1edbc | 152 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ |
| AnnaBridge | 171:3a7713b1edbc | 153 | UNUSED(tmpreg); \ |
| AnnaBridge | 171:3a7713b1edbc | 154 | } while(0) |
| AnnaBridge | 171:3a7713b1edbc | 155 | #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ |
| AnnaBridge | 171:3a7713b1edbc | 156 | __IO uint32_t tmpreg = 0x00; \ |
| AnnaBridge | 171:3a7713b1edbc | 157 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ |
| AnnaBridge | 171:3a7713b1edbc | 158 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 171:3a7713b1edbc | 159 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ |
| AnnaBridge | 171:3a7713b1edbc | 160 | UNUSED(tmpreg); \ |
| AnnaBridge | 171:3a7713b1edbc | 161 | } while(0) |
| AnnaBridge | 171:3a7713b1edbc | 162 | #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \ |
| AnnaBridge | 171:3a7713b1edbc | 163 | __IO uint32_t tmpreg = 0x00; \ |
| AnnaBridge | 171:3a7713b1edbc | 164 | SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ |
| AnnaBridge | 171:3a7713b1edbc | 165 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 171:3a7713b1edbc | 166 | tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ |
| AnnaBridge | 171:3a7713b1edbc | 167 | UNUSED(tmpreg); \ |
| AnnaBridge | 171:3a7713b1edbc | 168 | } while(0) |
| AnnaBridge | 171:3a7713b1edbc | 169 | |
| AnnaBridge | 171:3a7713b1edbc | 170 | #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) |
| AnnaBridge | 171:3a7713b1edbc | 171 | #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) |
| AnnaBridge | 171:3a7713b1edbc | 172 | #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) |
| AnnaBridge | 171:3a7713b1edbc | 173 | #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) |
| AnnaBridge | 171:3a7713b1edbc | 174 | |
| AnnaBridge | 171:3a7713b1edbc | 175 | /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status |
| AnnaBridge | 171:3a7713b1edbc | 176 | * @brief Get the enable or disable status of the AHB1 peripheral clock. |
| AnnaBridge | 171:3a7713b1edbc | 177 | * @note After reset, the peripheral clock (used for registers read/write access) |
| AnnaBridge | 171:3a7713b1edbc | 178 | * is disabled and the application software has to enable this clock before |
| AnnaBridge | 171:3a7713b1edbc | 179 | * using it. |
| AnnaBridge | 171:3a7713b1edbc | 180 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 181 | */ |
| AnnaBridge | 171:3a7713b1edbc | 182 | #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACEN))!= RESET) |
| AnnaBridge | 171:3a7713b1edbc | 183 | #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACTXEN))!= RESET) |
| AnnaBridge | 171:3a7713b1edbc | 184 | #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACRXEN))!= RESET) |
| AnnaBridge | 171:3a7713b1edbc | 185 | #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACPTPEN))!= RESET) |
| AnnaBridge | 171:3a7713b1edbc | 186 | #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \ |
| AnnaBridge | 171:3a7713b1edbc | 187 | __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \ |
| AnnaBridge | 171:3a7713b1edbc | 188 | __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) |
| AnnaBridge | 171:3a7713b1edbc | 189 | #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACEN))== RESET) |
| AnnaBridge | 171:3a7713b1edbc | 190 | #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACTXEN))== RESET) |
| AnnaBridge | 171:3a7713b1edbc | 191 | #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACRXEN))== RESET) |
| AnnaBridge | 171:3a7713b1edbc | 192 | #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_ETHMACPTPEN))== RESET) |
| AnnaBridge | 171:3a7713b1edbc | 193 | #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ |
| AnnaBridge | 171:3a7713b1edbc | 194 | __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ |
| AnnaBridge | 171:3a7713b1edbc | 195 | __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) |
| AnnaBridge | 171:3a7713b1edbc | 196 | /** |
| AnnaBridge | 171:3a7713b1edbc | 197 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 198 | */ |
| AnnaBridge | 171:3a7713b1edbc | 199 | |
| AnnaBridge | 171:3a7713b1edbc | 200 | /** |
| AnnaBridge | 171:3a7713b1edbc | 201 | * @brief Enable ETHERNET clock. |
| AnnaBridge | 171:3a7713b1edbc | 202 | */ |
| AnnaBridge | 171:3a7713b1edbc | 203 | #define __HAL_RCC_ETH_CLK_ENABLE() do { \ |
| AnnaBridge | 171:3a7713b1edbc | 204 | __HAL_RCC_ETHMAC_CLK_ENABLE(); \ |
| AnnaBridge | 171:3a7713b1edbc | 205 | __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ |
| AnnaBridge | 171:3a7713b1edbc | 206 | __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ |
| AnnaBridge | 171:3a7713b1edbc | 207 | } while(0) |
| AnnaBridge | 171:3a7713b1edbc | 208 | /** |
| AnnaBridge | 171:3a7713b1edbc | 209 | * @brief Disable ETHERNET clock. |
| AnnaBridge | 171:3a7713b1edbc | 210 | */ |
| AnnaBridge | 171:3a7713b1edbc | 211 | #define __HAL_RCC_ETH_CLK_DISABLE() do { \ |
| AnnaBridge | 171:3a7713b1edbc | 212 | __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ |
| AnnaBridge | 171:3a7713b1edbc | 213 | __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ |
| AnnaBridge | 171:3a7713b1edbc | 214 | __HAL_RCC_ETHMAC_CLK_DISABLE(); \ |
| AnnaBridge | 171:3a7713b1edbc | 215 | } while(0) |
| AnnaBridge | 171:3a7713b1edbc | 216 | #endif /* STM32F207xx || STM32F217xx */ |
| AnnaBridge | 171:3a7713b1edbc | 217 | /** |
| AnnaBridge | 171:3a7713b1edbc | 218 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 219 | */ |
| AnnaBridge | 171:3a7713b1edbc | 220 | |
| AnnaBridge | 171:3a7713b1edbc | 221 | /** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable |
| AnnaBridge | 171:3a7713b1edbc | 222 | * @brief Enable or disable the AHB2 peripheral clock. |
| AnnaBridge | 171:3a7713b1edbc | 223 | * @note After reset, the peripheral clock (used for registers read/write access) |
| AnnaBridge | 171:3a7713b1edbc | 224 | * is disabled and the application software has to enable this clock before |
| AnnaBridge | 171:3a7713b1edbc | 225 | * using it. |
| AnnaBridge | 171:3a7713b1edbc | 226 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 227 | */ |
| AnnaBridge | 171:3a7713b1edbc | 228 | #if defined(STM32F207xx) || defined(STM32F217xx) |
| AnnaBridge | 171:3a7713b1edbc | 229 | #define __HAL_RCC_DCMI_CLK_ENABLE() do { \ |
| AnnaBridge | 171:3a7713b1edbc | 230 | __IO uint32_t tmpreg = 0x00; \ |
| AnnaBridge | 171:3a7713b1edbc | 231 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ |
| AnnaBridge | 171:3a7713b1edbc | 232 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 171:3a7713b1edbc | 233 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ |
| AnnaBridge | 171:3a7713b1edbc | 234 | UNUSED(tmpreg); \ |
| AnnaBridge | 171:3a7713b1edbc | 235 | } while(0) |
| AnnaBridge | 171:3a7713b1edbc | 236 | |
| AnnaBridge | 171:3a7713b1edbc | 237 | #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) |
| AnnaBridge | 171:3a7713b1edbc | 238 | #endif /* STM32F207xx || STM32F217xx */ |
| AnnaBridge | 171:3a7713b1edbc | 239 | |
| AnnaBridge | 171:3a7713b1edbc | 240 | #if defined(STM32F215xx) || defined(STM32F217xx) |
| AnnaBridge | 171:3a7713b1edbc | 241 | #define __HAL_RCC_CRYP_CLK_ENABLE() do { \ |
| AnnaBridge | 171:3a7713b1edbc | 242 | __IO uint32_t tmpreg = 0x00; \ |
| AnnaBridge | 171:3a7713b1edbc | 243 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ |
| AnnaBridge | 171:3a7713b1edbc | 244 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 171:3a7713b1edbc | 245 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ |
| AnnaBridge | 171:3a7713b1edbc | 246 | UNUSED(tmpreg); \ |
| AnnaBridge | 171:3a7713b1edbc | 247 | } while(0) |
| AnnaBridge | 171:3a7713b1edbc | 248 | #define __HAL_RCC_HASH_CLK_ENABLE() do { \ |
| AnnaBridge | 171:3a7713b1edbc | 249 | __IO uint32_t tmpreg = 0x00; \ |
| AnnaBridge | 171:3a7713b1edbc | 250 | SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ |
| AnnaBridge | 171:3a7713b1edbc | 251 | /* Delay after an RCC peripheral clock enabling */ \ |
| AnnaBridge | 171:3a7713b1edbc | 252 | tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ |
| AnnaBridge | 171:3a7713b1edbc | 253 | UNUSED(tmpreg); \ |
| AnnaBridge | 171:3a7713b1edbc | 254 | } while(0) |
| AnnaBridge | 171:3a7713b1edbc | 255 | |
| AnnaBridge | 171:3a7713b1edbc | 256 | #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) |
| AnnaBridge | 171:3a7713b1edbc | 257 | #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) |
| AnnaBridge | 171:3a7713b1edbc | 258 | #endif /* STM32F215xx || STM32F217xx */ |
| AnnaBridge | 171:3a7713b1edbc | 259 | /** |
| AnnaBridge | 171:3a7713b1edbc | 260 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 261 | */ |
| AnnaBridge | 171:3a7713b1edbc | 262 | |
| AnnaBridge | 171:3a7713b1edbc | 263 | /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status |
| AnnaBridge | 171:3a7713b1edbc | 264 | * @brief Get the enable or disable status of the AHB2 peripheral clock. |
| AnnaBridge | 171:3a7713b1edbc | 265 | * @note After reset, the peripheral clock (used for registers read/write access) |
| AnnaBridge | 171:3a7713b1edbc | 266 | * is disabled and the application software has to enable this clock before |
| AnnaBridge | 171:3a7713b1edbc | 267 | * using it. |
| AnnaBridge | 171:3a7713b1edbc | 268 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 269 | */ |
| AnnaBridge | 171:3a7713b1edbc | 270 | #if defined(STM32F207xx) || defined(STM32F217xx) |
| AnnaBridge | 171:3a7713b1edbc | 271 | #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_DCMIEN))!= RESET) |
| AnnaBridge | 171:3a7713b1edbc | 272 | #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_DCMIEN))== RESET) |
| AnnaBridge | 171:3a7713b1edbc | 273 | #endif /* defined(STM32F207xx) || defined(STM32F217xx) */ |
| AnnaBridge | 171:3a7713b1edbc | 274 | #if defined(STM32F215xx) || defined(STM32F217xx) |
| AnnaBridge | 171:3a7713b1edbc | 275 | #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_CRYPEN))!= RESET) |
| AnnaBridge | 171:3a7713b1edbc | 276 | #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_HASHEN))!= RESET) |
| AnnaBridge | 171:3a7713b1edbc | 277 | |
| AnnaBridge | 171:3a7713b1edbc | 278 | #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_CRYPEN))== RESET) |
| AnnaBridge | 171:3a7713b1edbc | 279 | #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_HASHEN))== RESET) |
| AnnaBridge | 171:3a7713b1edbc | 280 | #endif /* defined(STM32F215xx) || defined(STM32F217xx) */ |
| AnnaBridge | 171:3a7713b1edbc | 281 | /** |
| AnnaBridge | 171:3a7713b1edbc | 282 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 283 | */ |
| AnnaBridge | 171:3a7713b1edbc | 284 | |
| AnnaBridge | 171:3a7713b1edbc | 285 | /** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset |
| AnnaBridge | 171:3a7713b1edbc | 286 | * @brief Force or release AHB1 peripheral reset. |
| AnnaBridge | 171:3a7713b1edbc | 287 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 288 | */ |
| AnnaBridge | 171:3a7713b1edbc | 289 | #if defined(STM32F207xx) || defined(STM32F217xx) |
| AnnaBridge | 171:3a7713b1edbc | 290 | #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) |
| AnnaBridge | 171:3a7713b1edbc | 291 | #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) |
| AnnaBridge | 171:3a7713b1edbc | 292 | #endif /* STM32F207xx || STM32F217xx */ |
| AnnaBridge | 171:3a7713b1edbc | 293 | /** |
| AnnaBridge | 171:3a7713b1edbc | 294 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 295 | */ |
| AnnaBridge | 171:3a7713b1edbc | 296 | |
| AnnaBridge | 171:3a7713b1edbc | 297 | /** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset |
| AnnaBridge | 171:3a7713b1edbc | 298 | * @brief Force or release AHB2 peripheral reset. |
| AnnaBridge | 171:3a7713b1edbc | 299 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 300 | */ |
| AnnaBridge | 171:3a7713b1edbc | 301 | #if defined(STM32F207xx) || defined(STM32F217xx) |
| AnnaBridge | 171:3a7713b1edbc | 302 | #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) |
| AnnaBridge | 171:3a7713b1edbc | 303 | #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) |
| AnnaBridge | 171:3a7713b1edbc | 304 | #endif /* STM32F207xx || STM32F217xx */ |
| AnnaBridge | 171:3a7713b1edbc | 305 | |
| AnnaBridge | 171:3a7713b1edbc | 306 | #if defined(STM32F215xx) || defined(STM32F217xx) |
| AnnaBridge | 171:3a7713b1edbc | 307 | #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) |
| AnnaBridge | 171:3a7713b1edbc | 308 | #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) |
| AnnaBridge | 171:3a7713b1edbc | 309 | |
| AnnaBridge | 171:3a7713b1edbc | 310 | #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) |
| AnnaBridge | 171:3a7713b1edbc | 311 | #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) |
| AnnaBridge | 171:3a7713b1edbc | 312 | #endif /* STM32F215xx || STM32F217xx */ |
| AnnaBridge | 171:3a7713b1edbc | 313 | |
| AnnaBridge | 171:3a7713b1edbc | 314 | /** |
| AnnaBridge | 171:3a7713b1edbc | 315 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 316 | */ |
| AnnaBridge | 171:3a7713b1edbc | 317 | |
| AnnaBridge | 171:3a7713b1edbc | 318 | /** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable |
| AnnaBridge | 171:3a7713b1edbc | 319 | * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. |
| AnnaBridge | 171:3a7713b1edbc | 320 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| AnnaBridge | 171:3a7713b1edbc | 321 | * power consumption. |
| AnnaBridge | 171:3a7713b1edbc | 322 | * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. |
| AnnaBridge | 171:3a7713b1edbc | 323 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| AnnaBridge | 171:3a7713b1edbc | 324 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 325 | */ |
| AnnaBridge | 171:3a7713b1edbc | 326 | #if defined(STM32F207xx) || defined(STM32F217xx) |
| AnnaBridge | 171:3a7713b1edbc | 327 | #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) |
| AnnaBridge | 171:3a7713b1edbc | 328 | #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) |
| AnnaBridge | 171:3a7713b1edbc | 329 | #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) |
| AnnaBridge | 171:3a7713b1edbc | 330 | #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) |
| AnnaBridge | 171:3a7713b1edbc | 331 | |
| AnnaBridge | 171:3a7713b1edbc | 332 | #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) |
| AnnaBridge | 171:3a7713b1edbc | 333 | #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) |
| AnnaBridge | 171:3a7713b1edbc | 334 | #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) |
| AnnaBridge | 171:3a7713b1edbc | 335 | #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) |
| AnnaBridge | 171:3a7713b1edbc | 336 | #endif /* STM32F207xx || STM32F217xx */ |
| AnnaBridge | 171:3a7713b1edbc | 337 | /** |
| AnnaBridge | 171:3a7713b1edbc | 338 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 339 | */ |
| AnnaBridge | 171:3a7713b1edbc | 340 | |
| AnnaBridge | 171:3a7713b1edbc | 341 | /** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable |
| AnnaBridge | 171:3a7713b1edbc | 342 | * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. |
| AnnaBridge | 171:3a7713b1edbc | 343 | * @note Peripheral clock gating in SLEEP mode can be used to further reduce |
| AnnaBridge | 171:3a7713b1edbc | 344 | * power consumption. |
| AnnaBridge | 171:3a7713b1edbc | 345 | * @note After wake-up from SLEEP mode, the peripheral clock is enabled again. |
| AnnaBridge | 171:3a7713b1edbc | 346 | * @note By default, all peripheral clocks are enabled during SLEEP mode. |
| AnnaBridge | 171:3a7713b1edbc | 347 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 348 | */ |
| AnnaBridge | 171:3a7713b1edbc | 349 | #if defined(STM32F207xx) || defined(STM32F217xx) |
| AnnaBridge | 171:3a7713b1edbc | 350 | #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) |
| AnnaBridge | 171:3a7713b1edbc | 351 | #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) |
| AnnaBridge | 171:3a7713b1edbc | 352 | #endif /* STM32F207xx || STM32F217xx */ |
| AnnaBridge | 171:3a7713b1edbc | 353 | |
| AnnaBridge | 171:3a7713b1edbc | 354 | #if defined(STM32F215xx) || defined(STM32F217xx) |
| AnnaBridge | 171:3a7713b1edbc | 355 | #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) |
| AnnaBridge | 171:3a7713b1edbc | 356 | #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) |
| AnnaBridge | 171:3a7713b1edbc | 357 | |
| AnnaBridge | 171:3a7713b1edbc | 358 | #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) |
| AnnaBridge | 171:3a7713b1edbc | 359 | #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) |
| AnnaBridge | 171:3a7713b1edbc | 360 | #endif /* STM32F215xx || STM32F217xx */ |
| AnnaBridge | 171:3a7713b1edbc | 361 | /** |
| AnnaBridge | 171:3a7713b1edbc | 362 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 363 | */ |
| AnnaBridge | 171:3a7713b1edbc | 364 | |
| AnnaBridge | 171:3a7713b1edbc | 365 | /** |
| AnnaBridge | 171:3a7713b1edbc | 366 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 367 | */ |
| AnnaBridge | 171:3a7713b1edbc | 368 | |
| AnnaBridge | 171:3a7713b1edbc | 369 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 370 | /** @addtogroup RCCEx_Exported_Functions |
| AnnaBridge | 171:3a7713b1edbc | 371 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 372 | */ |
| AnnaBridge | 171:3a7713b1edbc | 373 | |
| AnnaBridge | 171:3a7713b1edbc | 374 | /** @addtogroup RCCEx_Exported_Functions_Group1 |
| AnnaBridge | 171:3a7713b1edbc | 375 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 376 | */ |
| AnnaBridge | 171:3a7713b1edbc | 377 | HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); |
| AnnaBridge | 171:3a7713b1edbc | 378 | void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); |
| AnnaBridge | 171:3a7713b1edbc | 379 | |
| AnnaBridge | 171:3a7713b1edbc | 380 | /** |
| AnnaBridge | 171:3a7713b1edbc | 381 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 382 | */ |
| AnnaBridge | 171:3a7713b1edbc | 383 | |
| AnnaBridge | 171:3a7713b1edbc | 384 | /** |
| AnnaBridge | 171:3a7713b1edbc | 385 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 386 | */ |
| AnnaBridge | 171:3a7713b1edbc | 387 | /* Private types -------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 388 | /* Private variables ---------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 389 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 390 | /** @defgroup RCCEx_Private_Constants RCC Private Constants |
| AnnaBridge | 171:3a7713b1edbc | 391 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 392 | */ |
| AnnaBridge | 171:3a7713b1edbc | 393 | |
| AnnaBridge | 171:3a7713b1edbc | 394 | /** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion |
| AnnaBridge | 171:3a7713b1edbc | 395 | * @brief RCC registers bit address in the alias region |
| AnnaBridge | 171:3a7713b1edbc | 396 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 397 | */ |
| AnnaBridge | 171:3a7713b1edbc | 398 | #define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ |
| AnnaBridge | 171:3a7713b1edbc | 399 | /** |
| AnnaBridge | 171:3a7713b1edbc | 400 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 401 | */ |
| AnnaBridge | 171:3a7713b1edbc | 402 | |
| AnnaBridge | 171:3a7713b1edbc | 403 | /** |
| AnnaBridge | 171:3a7713b1edbc | 404 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 405 | */ |
| AnnaBridge | 171:3a7713b1edbc | 406 | |
| AnnaBridge | 171:3a7713b1edbc | 407 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 408 | /** @defgroup RCCEx_Private_Macros RCC Private Macros |
| AnnaBridge | 171:3a7713b1edbc | 409 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 410 | */ |
| AnnaBridge | 171:3a7713b1edbc | 411 | /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters |
| AnnaBridge | 171:3a7713b1edbc | 412 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 413 | */ |
| AnnaBridge | 171:3a7713b1edbc | 414 | #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000000F)) |
| AnnaBridge | 171:3a7713b1edbc | 415 | #define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) |
| AnnaBridge | 171:3a7713b1edbc | 416 | #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) |
| AnnaBridge | 171:3a7713b1edbc | 417 | /** |
| AnnaBridge | 171:3a7713b1edbc | 418 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 419 | */ |
| AnnaBridge | 171:3a7713b1edbc | 420 | |
| AnnaBridge | 171:3a7713b1edbc | 421 | /** |
| AnnaBridge | 171:3a7713b1edbc | 422 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 423 | */ |
| AnnaBridge | 171:3a7713b1edbc | 424 | |
| AnnaBridge | 171:3a7713b1edbc | 425 | /** |
| AnnaBridge | 171:3a7713b1edbc | 426 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 427 | */ |
| AnnaBridge | 171:3a7713b1edbc | 428 | |
| AnnaBridge | 171:3a7713b1edbc | 429 | /** |
| AnnaBridge | 171:3a7713b1edbc | 430 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 431 | */ |
| AnnaBridge | 171:3a7713b1edbc | 432 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 433 | } |
| AnnaBridge | 171:3a7713b1edbc | 434 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 435 | |
| AnnaBridge | 171:3a7713b1edbc | 436 | #endif /* __STM32F2xx_HAL_RCC_EX_H */ |
| AnnaBridge | 171:3a7713b1edbc | 437 | |
| AnnaBridge | 171:3a7713b1edbc | 438 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
