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TARGET_NUCLEO_F207ZG/TOOLCHAIN_GCC_ARM/stm32f2xx_hal_rcc.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	171:3a7713b1edbc	1	/**
AnnaBridge	171:3a7713b1edbc	2	******************************************************************************
AnnaBridge	171:3a7713b1edbc	3	* @file stm32f2xx_hal_rcc.h
AnnaBridge	171:3a7713b1edbc	4	* @author MCD Application Team
AnnaBridge	171:3a7713b1edbc	5	* @version V1.2.1
AnnaBridge	171:3a7713b1edbc	6	* @date 14-April-2017
AnnaBridge	171:3a7713b1edbc	7	* @brief Header file of RCC HAL module.
AnnaBridge	171:3a7713b1edbc	8	******************************************************************************
AnnaBridge	171:3a7713b1edbc	9	* @attention
AnnaBridge	171:3a7713b1edbc	10	*
AnnaBridge	171:3a7713b1edbc	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	171:3a7713b1edbc	12	*
AnnaBridge	171:3a7713b1edbc	13	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	171:3a7713b1edbc	14	* are permitted provided that the following conditions are met:
AnnaBridge	171:3a7713b1edbc	15	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	171:3a7713b1edbc	16	* this list of conditions and the following disclaimer.
AnnaBridge	171:3a7713b1edbc	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	171:3a7713b1edbc	18	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	171:3a7713b1edbc	19	* and/or other materials provided with the distribution.
AnnaBridge	171:3a7713b1edbc	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	171:3a7713b1edbc	21	* may be used to endorse or promote products derived from this software
AnnaBridge	171:3a7713b1edbc	22	* without specific prior written permission.
AnnaBridge	171:3a7713b1edbc	23	*
AnnaBridge	171:3a7713b1edbc	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	171:3a7713b1edbc	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	171:3a7713b1edbc	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	171:3a7713b1edbc	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	171:3a7713b1edbc	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	171:3a7713b1edbc	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	171:3a7713b1edbc	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	171:3a7713b1edbc	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	171:3a7713b1edbc	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	171:3a7713b1edbc	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	171:3a7713b1edbc	34	*
AnnaBridge	171:3a7713b1edbc	35	******************************************************************************
AnnaBridge	171:3a7713b1edbc	36	*/
AnnaBridge	171:3a7713b1edbc	37
AnnaBridge	171:3a7713b1edbc	38	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	171:3a7713b1edbc	39	#ifndef __STM32F2xx_HAL_RCC_H
AnnaBridge	171:3a7713b1edbc	40	#define __STM32F2xx_HAL_RCC_H
AnnaBridge	171:3a7713b1edbc	41
AnnaBridge	171:3a7713b1edbc	42	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	43	extern "C" {
AnnaBridge	171:3a7713b1edbc	44	#endif
AnnaBridge	171:3a7713b1edbc	45
AnnaBridge	171:3a7713b1edbc	46	/* Includes ------------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	47	#include "stm32f2xx_hal_def.h"
AnnaBridge	171:3a7713b1edbc	48
AnnaBridge	171:3a7713b1edbc	49	/** @addtogroup STM32F2xx_HAL_Driver
AnnaBridge	171:3a7713b1edbc	50	* @{
AnnaBridge	171:3a7713b1edbc	51	*/
AnnaBridge	171:3a7713b1edbc	52
AnnaBridge	171:3a7713b1edbc	53	/** @addtogroup RCC
AnnaBridge	171:3a7713b1edbc	54	* @{
AnnaBridge	171:3a7713b1edbc	55	*/
AnnaBridge	171:3a7713b1edbc	56
AnnaBridge	171:3a7713b1edbc	57	/* Exported types ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	58	/** @defgroup RCC_Exported_Types RCC Exported Types
AnnaBridge	171:3a7713b1edbc	59	* @{
AnnaBridge	171:3a7713b1edbc	60	*/
AnnaBridge	171:3a7713b1edbc	61
AnnaBridge	171:3a7713b1edbc	62	/**
AnnaBridge	171:3a7713b1edbc	63	* @brief RCC PLL configuration structure definition
AnnaBridge	171:3a7713b1edbc	64	*/
AnnaBridge	171:3a7713b1edbc	65	typedef struct
AnnaBridge	171:3a7713b1edbc	66	{
AnnaBridge	171:3a7713b1edbc	67	uint32_t PLLState; /*!< The new state of the PLL.
AnnaBridge	171:3a7713b1edbc	68	This parameter can be a value of @ref RCC_PLL_Config */
AnnaBridge	171:3a7713b1edbc	69
AnnaBridge	171:3a7713b1edbc	70	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
AnnaBridge	171:3a7713b1edbc	71	This parameter must be a value of @ref RCC_PLL_Clock_Source */
AnnaBridge	171:3a7713b1edbc	72
AnnaBridge	171:3a7713b1edbc	73	uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
AnnaBridge	171:3a7713b1edbc	74	This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
AnnaBridge	171:3a7713b1edbc	75
AnnaBridge	171:3a7713b1edbc	76	uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
AnnaBridge	171:3a7713b1edbc	77	This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
AnnaBridge	171:3a7713b1edbc	78
AnnaBridge	171:3a7713b1edbc	79	uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
AnnaBridge	171:3a7713b1edbc	80	This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
AnnaBridge	171:3a7713b1edbc	81
AnnaBridge	171:3a7713b1edbc	82	uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
AnnaBridge	171:3a7713b1edbc	83	This parameter must be a number between Min_Data = 2 and Max_Data = 15 */
AnnaBridge	171:3a7713b1edbc	84
AnnaBridge	171:3a7713b1edbc	85	}RCC_PLLInitTypeDef;
AnnaBridge	171:3a7713b1edbc	86
AnnaBridge	171:3a7713b1edbc	87	/**
AnnaBridge	171:3a7713b1edbc	88	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
AnnaBridge	171:3a7713b1edbc	89	*/
AnnaBridge	171:3a7713b1edbc	90	typedef struct
AnnaBridge	171:3a7713b1edbc	91	{
AnnaBridge	171:3a7713b1edbc	92	uint32_t OscillatorType; /*!< The oscillators to be configured.
AnnaBridge	171:3a7713b1edbc	93	This parameter can be a value of @ref RCC_Oscillator_Type */
AnnaBridge	171:3a7713b1edbc	94
AnnaBridge	171:3a7713b1edbc	95	uint32_t HSEState; /*!< The new state of the HSE.
AnnaBridge	171:3a7713b1edbc	96	This parameter can be a value of @ref RCC_HSE_Config */
AnnaBridge	171:3a7713b1edbc	97
AnnaBridge	171:3a7713b1edbc	98	uint32_t LSEState; /*!< The new state of the LSE.
AnnaBridge	171:3a7713b1edbc	99	This parameter can be a value of @ref RCC_LSE_Config */
AnnaBridge	171:3a7713b1edbc	100
AnnaBridge	171:3a7713b1edbc	101	uint32_t HSIState; /*!< The new state of the HSI.
AnnaBridge	171:3a7713b1edbc	102	This parameter can be a value of @ref RCC_HSI_Config */
AnnaBridge	171:3a7713b1edbc	103
AnnaBridge	171:3a7713b1edbc	104	uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
AnnaBridge	171:3a7713b1edbc	105	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
AnnaBridge	171:3a7713b1edbc	106
AnnaBridge	171:3a7713b1edbc	107	uint32_t LSIState; /*!< The new state of the LSI.
AnnaBridge	171:3a7713b1edbc	108	This parameter can be a value of @ref RCC_LSI_Config */
AnnaBridge	171:3a7713b1edbc	109
AnnaBridge	171:3a7713b1edbc	110	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
AnnaBridge	171:3a7713b1edbc	111	}RCC_OscInitTypeDef;
AnnaBridge	171:3a7713b1edbc	112
AnnaBridge	171:3a7713b1edbc	113	/**
AnnaBridge	171:3a7713b1edbc	114	* @brief RCC System, AHB and APB busses clock configuration structure definition
AnnaBridge	171:3a7713b1edbc	115	*/
AnnaBridge	171:3a7713b1edbc	116	typedef struct
AnnaBridge	171:3a7713b1edbc	117	{
AnnaBridge	171:3a7713b1edbc	118	uint32_t ClockType; /*!< The clock to be configured.
AnnaBridge	171:3a7713b1edbc	119	This parameter can be a value of @ref RCC_System_Clock_Type */
AnnaBridge	171:3a7713b1edbc	120
AnnaBridge	171:3a7713b1edbc	121	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
AnnaBridge	171:3a7713b1edbc	122	This parameter can be a value of @ref RCC_System_Clock_Source */
AnnaBridge	171:3a7713b1edbc	123
AnnaBridge	171:3a7713b1edbc	124	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
AnnaBridge	171:3a7713b1edbc	125	This parameter can be a value of @ref RCC_AHB_Clock_Source */
AnnaBridge	171:3a7713b1edbc	126
AnnaBridge	171:3a7713b1edbc	127	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
AnnaBridge	171:3a7713b1edbc	128	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
AnnaBridge	171:3a7713b1edbc	129
AnnaBridge	171:3a7713b1edbc	130	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
AnnaBridge	171:3a7713b1edbc	131	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
AnnaBridge	171:3a7713b1edbc	132
AnnaBridge	171:3a7713b1edbc	133	}RCC_ClkInitTypeDef;
AnnaBridge	171:3a7713b1edbc	134
AnnaBridge	171:3a7713b1edbc	135	/**
AnnaBridge	171:3a7713b1edbc	136	* @}
AnnaBridge	171:3a7713b1edbc	137	*/
AnnaBridge	171:3a7713b1edbc	138
AnnaBridge	171:3a7713b1edbc	139	/* Exported constants --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	140	/** @defgroup RCC_Exported_Constants RCC Exported Constants
AnnaBridge	171:3a7713b1edbc	141	* @{
AnnaBridge	171:3a7713b1edbc	142	*/
AnnaBridge	171:3a7713b1edbc	143
AnnaBridge	171:3a7713b1edbc	144	/** @defgroup RCC_Oscillator_Type Oscillator Type
AnnaBridge	171:3a7713b1edbc	145	* @{
AnnaBridge	171:3a7713b1edbc	146	*/
AnnaBridge	171:3a7713b1edbc	147	#define RCC_OSCILLATORTYPE_NONE 0x00000000U
AnnaBridge	171:3a7713b1edbc	148	#define RCC_OSCILLATORTYPE_HSE 0x00000001U
AnnaBridge	171:3a7713b1edbc	149	#define RCC_OSCILLATORTYPE_HSI 0x00000002U
AnnaBridge	171:3a7713b1edbc	150	#define RCC_OSCILLATORTYPE_LSE 0x00000004U
AnnaBridge	171:3a7713b1edbc	151	#define RCC_OSCILLATORTYPE_LSI 0x00000008U
AnnaBridge	171:3a7713b1edbc	152	/**
AnnaBridge	171:3a7713b1edbc	153	* @}
AnnaBridge	171:3a7713b1edbc	154	*/
AnnaBridge	171:3a7713b1edbc	155
AnnaBridge	171:3a7713b1edbc	156	/** @defgroup RCC_HSE_Config HSE Config
AnnaBridge	171:3a7713b1edbc	157	* @{
AnnaBridge	171:3a7713b1edbc	158	*/
AnnaBridge	171:3a7713b1edbc	159	#define RCC_HSE_OFF ((uint8_t)0x00)
AnnaBridge	171:3a7713b1edbc	160	#define RCC_HSE_ON ((uint8_t)0x01)
AnnaBridge	171:3a7713b1edbc	161	#define RCC_HSE_BYPASS ((uint8_t)0x05)
AnnaBridge	171:3a7713b1edbc	162	/**
AnnaBridge	171:3a7713b1edbc	163	* @}
AnnaBridge	171:3a7713b1edbc	164	*/
AnnaBridge	171:3a7713b1edbc	165
AnnaBridge	171:3a7713b1edbc	166	/** @defgroup RCC_LSE_Config LSE Config
AnnaBridge	171:3a7713b1edbc	167	* @{
AnnaBridge	171:3a7713b1edbc	168	*/
AnnaBridge	171:3a7713b1edbc	169	#define RCC_LSE_OFF ((uint8_t)0x00)
AnnaBridge	171:3a7713b1edbc	170	#define RCC_LSE_ON ((uint8_t)0x01)
AnnaBridge	171:3a7713b1edbc	171	#define RCC_LSE_BYPASS ((uint8_t)0x05)
AnnaBridge	171:3a7713b1edbc	172	/**
AnnaBridge	171:3a7713b1edbc	173	* @}
AnnaBridge	171:3a7713b1edbc	174	*/
AnnaBridge	171:3a7713b1edbc	175
AnnaBridge	171:3a7713b1edbc	176	/** @defgroup RCC_HSI_Config HSI Config
AnnaBridge	171:3a7713b1edbc	177	* @{
AnnaBridge	171:3a7713b1edbc	178	*/
AnnaBridge	171:3a7713b1edbc	179	#define RCC_HSI_OFF ((uint8_t)0x00)
AnnaBridge	171:3a7713b1edbc	180	#define RCC_HSI_ON ((uint8_t)0x01)
AnnaBridge	171:3a7713b1edbc	181
AnnaBridge	171:3a7713b1edbc	182	#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */
AnnaBridge	171:3a7713b1edbc	183	/**
AnnaBridge	171:3a7713b1edbc	184	* @}
AnnaBridge	171:3a7713b1edbc	185	*/
AnnaBridge	171:3a7713b1edbc	186
AnnaBridge	171:3a7713b1edbc	187	/** @defgroup RCC_LSI_Config LSI Config
AnnaBridge	171:3a7713b1edbc	188	* @{
AnnaBridge	171:3a7713b1edbc	189	*/
AnnaBridge	171:3a7713b1edbc	190	#define RCC_LSI_OFF ((uint8_t)0x00)
AnnaBridge	171:3a7713b1edbc	191	#define RCC_LSI_ON ((uint8_t)0x01)
AnnaBridge	171:3a7713b1edbc	192	/**
AnnaBridge	171:3a7713b1edbc	193	* @}
AnnaBridge	171:3a7713b1edbc	194	*/
AnnaBridge	171:3a7713b1edbc	195
AnnaBridge	171:3a7713b1edbc	196	/** @defgroup RCC_PLL_Config PLL Config
AnnaBridge	171:3a7713b1edbc	197	* @{
AnnaBridge	171:3a7713b1edbc	198	*/
AnnaBridge	171:3a7713b1edbc	199	#define RCC_PLL_NONE ((uint8_t)0x00)
AnnaBridge	171:3a7713b1edbc	200	#define RCC_PLL_OFF ((uint8_t)0x01)
AnnaBridge	171:3a7713b1edbc	201	#define RCC_PLL_ON ((uint8_t)0x02)
AnnaBridge	171:3a7713b1edbc	202	/**
AnnaBridge	171:3a7713b1edbc	203	* @}
AnnaBridge	171:3a7713b1edbc	204	*/
AnnaBridge	171:3a7713b1edbc	205
AnnaBridge	171:3a7713b1edbc	206	/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
AnnaBridge	171:3a7713b1edbc	207	* @{
AnnaBridge	171:3a7713b1edbc	208	*/
AnnaBridge	171:3a7713b1edbc	209	#define RCC_PLLP_DIV2 0x00000002U
AnnaBridge	171:3a7713b1edbc	210	#define RCC_PLLP_DIV4 0x00000004U
AnnaBridge	171:3a7713b1edbc	211	#define RCC_PLLP_DIV6 0x00000006U
AnnaBridge	171:3a7713b1edbc	212	#define RCC_PLLP_DIV8 0x00000008U
AnnaBridge	171:3a7713b1edbc	213	/**
AnnaBridge	171:3a7713b1edbc	214	* @}
AnnaBridge	171:3a7713b1edbc	215	*/
AnnaBridge	171:3a7713b1edbc	216
AnnaBridge	171:3a7713b1edbc	217	/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
AnnaBridge	171:3a7713b1edbc	218	* @{
AnnaBridge	171:3a7713b1edbc	219	*/
AnnaBridge	171:3a7713b1edbc	220	#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
AnnaBridge	171:3a7713b1edbc	221	#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
AnnaBridge	171:3a7713b1edbc	222	/**
AnnaBridge	171:3a7713b1edbc	223	* @}
AnnaBridge	171:3a7713b1edbc	224	*/
AnnaBridge	171:3a7713b1edbc	225
AnnaBridge	171:3a7713b1edbc	226	/** @defgroup RCC_System_Clock_Type System Clock Type
AnnaBridge	171:3a7713b1edbc	227	* @{
AnnaBridge	171:3a7713b1edbc	228	*/
AnnaBridge	171:3a7713b1edbc	229	#define RCC_CLOCKTYPE_SYSCLK 0x00000001U
AnnaBridge	171:3a7713b1edbc	230	#define RCC_CLOCKTYPE_HCLK 0x00000002U
AnnaBridge	171:3a7713b1edbc	231	#define RCC_CLOCKTYPE_PCLK1 0x00000004U
AnnaBridge	171:3a7713b1edbc	232	#define RCC_CLOCKTYPE_PCLK2 0x00000008U
AnnaBridge	171:3a7713b1edbc	233	/**
AnnaBridge	171:3a7713b1edbc	234	* @}
AnnaBridge	171:3a7713b1edbc	235	*/
AnnaBridge	171:3a7713b1edbc	236
AnnaBridge	171:3a7713b1edbc	237	/** @defgroup RCC_System_Clock_Source System Clock Source
AnnaBridge	171:3a7713b1edbc	238	* @{
AnnaBridge	171:3a7713b1edbc	239	*/
AnnaBridge	171:3a7713b1edbc	240	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
AnnaBridge	171:3a7713b1edbc	241	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
AnnaBridge	171:3a7713b1edbc	242	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
AnnaBridge	171:3a7713b1edbc	243	/**
AnnaBridge	171:3a7713b1edbc	244	* @}
AnnaBridge	171:3a7713b1edbc	245	*/
AnnaBridge	171:3a7713b1edbc	246
AnnaBridge	171:3a7713b1edbc	247	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
AnnaBridge	171:3a7713b1edbc	248	* @{
AnnaBridge	171:3a7713b1edbc	249	*/
AnnaBridge	171:3a7713b1edbc	250	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
AnnaBridge	171:3a7713b1edbc	251	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
AnnaBridge	171:3a7713b1edbc	252	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /!< PLL used as system clock /
AnnaBridge	171:3a7713b1edbc	253	/**
AnnaBridge	171:3a7713b1edbc	254	* @}
AnnaBridge	171:3a7713b1edbc	255	*/
AnnaBridge	171:3a7713b1edbc	256
AnnaBridge	171:3a7713b1edbc	257	/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
AnnaBridge	171:3a7713b1edbc	258	* @{
AnnaBridge	171:3a7713b1edbc	259	*/
AnnaBridge	171:3a7713b1edbc	260	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
AnnaBridge	171:3a7713b1edbc	261	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
AnnaBridge	171:3a7713b1edbc	262	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
AnnaBridge	171:3a7713b1edbc	263	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
AnnaBridge	171:3a7713b1edbc	264	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
AnnaBridge	171:3a7713b1edbc	265	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
AnnaBridge	171:3a7713b1edbc	266	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
AnnaBridge	171:3a7713b1edbc	267	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
AnnaBridge	171:3a7713b1edbc	268	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
AnnaBridge	171:3a7713b1edbc	269	/**
AnnaBridge	171:3a7713b1edbc	270	* @}
AnnaBridge	171:3a7713b1edbc	271	*/
AnnaBridge	171:3a7713b1edbc	272
AnnaBridge	171:3a7713b1edbc	273	/** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source
AnnaBridge	171:3a7713b1edbc	274	* @{
AnnaBridge	171:3a7713b1edbc	275	*/
AnnaBridge	171:3a7713b1edbc	276	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
AnnaBridge	171:3a7713b1edbc	277	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
AnnaBridge	171:3a7713b1edbc	278	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
AnnaBridge	171:3a7713b1edbc	279	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
AnnaBridge	171:3a7713b1edbc	280	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
AnnaBridge	171:3a7713b1edbc	281	/**
AnnaBridge	171:3a7713b1edbc	282	* @}
AnnaBridge	171:3a7713b1edbc	283	*/
AnnaBridge	171:3a7713b1edbc	284
AnnaBridge	171:3a7713b1edbc	285	/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
AnnaBridge	171:3a7713b1edbc	286	* @{
AnnaBridge	171:3a7713b1edbc	287	*/
AnnaBridge	171:3a7713b1edbc	288	#define RCC_RTCCLKSOURCE_LSE 0x00000100U
AnnaBridge	171:3a7713b1edbc	289	#define RCC_RTCCLKSOURCE_LSI 0x00000200U
AnnaBridge	171:3a7713b1edbc	290	#define RCC_RTCCLKSOURCE_HSE_DIV2 0x00020300U
AnnaBridge	171:3a7713b1edbc	291	#define RCC_RTCCLKSOURCE_HSE_DIV3 0x00030300U
AnnaBridge	171:3a7713b1edbc	292	#define RCC_RTCCLKSOURCE_HSE_DIV4 0x00040300U
AnnaBridge	171:3a7713b1edbc	293	#define RCC_RTCCLKSOURCE_HSE_DIV5 0x00050300U
AnnaBridge	171:3a7713b1edbc	294	#define RCC_RTCCLKSOURCE_HSE_DIV6 0x00060300U
AnnaBridge	171:3a7713b1edbc	295	#define RCC_RTCCLKSOURCE_HSE_DIV7 0x00070300U
AnnaBridge	171:3a7713b1edbc	296	#define RCC_RTCCLKSOURCE_HSE_DIV8 0x00080300U
AnnaBridge	171:3a7713b1edbc	297	#define RCC_RTCCLKSOURCE_HSE_DIV9 0x00090300U
AnnaBridge	171:3a7713b1edbc	298	#define RCC_RTCCLKSOURCE_HSE_DIV10 0x000A0300U
AnnaBridge	171:3a7713b1edbc	299	#define RCC_RTCCLKSOURCE_HSE_DIV11 0x000B0300U
AnnaBridge	171:3a7713b1edbc	300	#define RCC_RTCCLKSOURCE_HSE_DIV12 0x000C0300U
AnnaBridge	171:3a7713b1edbc	301	#define RCC_RTCCLKSOURCE_HSE_DIV13 0x000D0300U
AnnaBridge	171:3a7713b1edbc	302	#define RCC_RTCCLKSOURCE_HSE_DIV14 0x000E0300U
AnnaBridge	171:3a7713b1edbc	303	#define RCC_RTCCLKSOURCE_HSE_DIV15 0x000F0300U
AnnaBridge	171:3a7713b1edbc	304	#define RCC_RTCCLKSOURCE_HSE_DIV16 0x00100300U
AnnaBridge	171:3a7713b1edbc	305	#define RCC_RTCCLKSOURCE_HSE_DIV17 0x00110300U
AnnaBridge	171:3a7713b1edbc	306	#define RCC_RTCCLKSOURCE_HSE_DIV18 0x00120300U
AnnaBridge	171:3a7713b1edbc	307	#define RCC_RTCCLKSOURCE_HSE_DIV19 0x00130300U
AnnaBridge	171:3a7713b1edbc	308	#define RCC_RTCCLKSOURCE_HSE_DIV20 0x00140300U
AnnaBridge	171:3a7713b1edbc	309	#define RCC_RTCCLKSOURCE_HSE_DIV21 0x00150300U
AnnaBridge	171:3a7713b1edbc	310	#define RCC_RTCCLKSOURCE_HSE_DIV22 0x00160300U
AnnaBridge	171:3a7713b1edbc	311	#define RCC_RTCCLKSOURCE_HSE_DIV23 0x00170300U
AnnaBridge	171:3a7713b1edbc	312	#define RCC_RTCCLKSOURCE_HSE_DIV24 0x00180300U
AnnaBridge	171:3a7713b1edbc	313	#define RCC_RTCCLKSOURCE_HSE_DIV25 0x00190300U
AnnaBridge	171:3a7713b1edbc	314	#define RCC_RTCCLKSOURCE_HSE_DIV26 0x001A0300U
AnnaBridge	171:3a7713b1edbc	315	#define RCC_RTCCLKSOURCE_HSE_DIV27 0x001B0300U
AnnaBridge	171:3a7713b1edbc	316	#define RCC_RTCCLKSOURCE_HSE_DIV28 0x001C0300U
AnnaBridge	171:3a7713b1edbc	317	#define RCC_RTCCLKSOURCE_HSE_DIV29 0x001D0300U
AnnaBridge	171:3a7713b1edbc	318	#define RCC_RTCCLKSOURCE_HSE_DIV30 0x001E0300U
AnnaBridge	171:3a7713b1edbc	319	#define RCC_RTCCLKSOURCE_HSE_DIV31 0x001F0300U
AnnaBridge	171:3a7713b1edbc	320	/**
AnnaBridge	171:3a7713b1edbc	321	* @}
AnnaBridge	171:3a7713b1edbc	322	*/
AnnaBridge	171:3a7713b1edbc	323
AnnaBridge	171:3a7713b1edbc	324	/** @defgroup RCC_MCO_Index MCO Index
AnnaBridge	171:3a7713b1edbc	325	* @{
AnnaBridge	171:3a7713b1edbc	326	*/
AnnaBridge	171:3a7713b1edbc	327	#define RCC_MCO1 0x00000000U
AnnaBridge	171:3a7713b1edbc	328	#define RCC_MCO2 0x00000001U
AnnaBridge	171:3a7713b1edbc	329	/**
AnnaBridge	171:3a7713b1edbc	330	* @}
AnnaBridge	171:3a7713b1edbc	331	*/
AnnaBridge	171:3a7713b1edbc	332
AnnaBridge	171:3a7713b1edbc	333	/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
AnnaBridge	171:3a7713b1edbc	334	* @{
AnnaBridge	171:3a7713b1edbc	335	*/
AnnaBridge	171:3a7713b1edbc	336	#define RCC_MCO1SOURCE_HSI 0x00000000U
AnnaBridge	171:3a7713b1edbc	337	#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
AnnaBridge	171:3a7713b1edbc	338	#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
AnnaBridge	171:3a7713b1edbc	339	#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
AnnaBridge	171:3a7713b1edbc	340	/**
AnnaBridge	171:3a7713b1edbc	341	* @}
AnnaBridge	171:3a7713b1edbc	342	*/
AnnaBridge	171:3a7713b1edbc	343
AnnaBridge	171:3a7713b1edbc	344	/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
AnnaBridge	171:3a7713b1edbc	345	* @{
AnnaBridge	171:3a7713b1edbc	346	*/
AnnaBridge	171:3a7713b1edbc	347	#define RCC_MCO2SOURCE_SYSCLK 0x00000000U
AnnaBridge	171:3a7713b1edbc	348	#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
AnnaBridge	171:3a7713b1edbc	349	#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
AnnaBridge	171:3a7713b1edbc	350	#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
AnnaBridge	171:3a7713b1edbc	351	/**
AnnaBridge	171:3a7713b1edbc	352	* @}
AnnaBridge	171:3a7713b1edbc	353	*/
AnnaBridge	171:3a7713b1edbc	354
AnnaBridge	171:3a7713b1edbc	355	/** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
AnnaBridge	171:3a7713b1edbc	356	* @{
AnnaBridge	171:3a7713b1edbc	357	*/
AnnaBridge	171:3a7713b1edbc	358	#define RCC_MCODIV_1 0x00000000U
AnnaBridge	171:3a7713b1edbc	359	#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
AnnaBridge	171:3a7713b1edbc	360	#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 \| RCC_CFGR_MCO1PRE_2)
AnnaBridge	171:3a7713b1edbc	361	#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 \| RCC_CFGR_MCO1PRE_2)
AnnaBridge	171:3a7713b1edbc	362	#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
AnnaBridge	171:3a7713b1edbc	363	/**
AnnaBridge	171:3a7713b1edbc	364	* @}
AnnaBridge	171:3a7713b1edbc	365	*/
AnnaBridge	171:3a7713b1edbc	366
AnnaBridge	171:3a7713b1edbc	367	/** @defgroup RCC_Interrupt Interrupts
AnnaBridge	171:3a7713b1edbc	368	* @{
AnnaBridge	171:3a7713b1edbc	369	*/
AnnaBridge	171:3a7713b1edbc	370	#define RCC_IT_LSIRDY ((uint8_t)0x01)
AnnaBridge	171:3a7713b1edbc	371	#define RCC_IT_LSERDY ((uint8_t)0x02)
AnnaBridge	171:3a7713b1edbc	372	#define RCC_IT_HSIRDY ((uint8_t)0x04)
AnnaBridge	171:3a7713b1edbc	373	#define RCC_IT_HSERDY ((uint8_t)0x08)
AnnaBridge	171:3a7713b1edbc	374	#define RCC_IT_PLLRDY ((uint8_t)0x10)
AnnaBridge	171:3a7713b1edbc	375	#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
AnnaBridge	171:3a7713b1edbc	376	#define RCC_IT_CSS ((uint8_t)0x80)
AnnaBridge	171:3a7713b1edbc	377	/**
AnnaBridge	171:3a7713b1edbc	378	* @}
AnnaBridge	171:3a7713b1edbc	379	*/
AnnaBridge	171:3a7713b1edbc	380
AnnaBridge	171:3a7713b1edbc	381	/** @defgroup RCC_Flag Flags
AnnaBridge	171:3a7713b1edbc	382	* Elements values convention: 0XXYYYYYb
AnnaBridge	171:3a7713b1edbc	383	* - YYYYY : Flag position in the register
AnnaBridge	171:3a7713b1edbc	384	* - 0XX : Register index
AnnaBridge	171:3a7713b1edbc	385	* - 01: CR register
AnnaBridge	171:3a7713b1edbc	386	* - 10: BDCR register
AnnaBridge	171:3a7713b1edbc	387	* - 11: CSR register
AnnaBridge	171:3a7713b1edbc	388	* @{
AnnaBridge	171:3a7713b1edbc	389	*/
AnnaBridge	171:3a7713b1edbc	390	/* Flags in the CR register */
AnnaBridge	171:3a7713b1edbc	391	#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
AnnaBridge	171:3a7713b1edbc	392	#define RCC_FLAG_HSERDY ((uint8_t)0x31)
AnnaBridge	171:3a7713b1edbc	393	#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
AnnaBridge	171:3a7713b1edbc	394	#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
AnnaBridge	171:3a7713b1edbc	395
AnnaBridge	171:3a7713b1edbc	396	/* Flags in the BDCR register */
AnnaBridge	171:3a7713b1edbc	397	#define RCC_FLAG_LSERDY ((uint8_t)0x41)
AnnaBridge	171:3a7713b1edbc	398
AnnaBridge	171:3a7713b1edbc	399	/* Flags in the CSR register */
AnnaBridge	171:3a7713b1edbc	400	#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
AnnaBridge	171:3a7713b1edbc	401	#define RCC_FLAG_BORRST ((uint8_t)0x79)
AnnaBridge	171:3a7713b1edbc	402	#define RCC_FLAG_PINRST ((uint8_t)0x7A)
AnnaBridge	171:3a7713b1edbc	403	#define RCC_FLAG_PORRST ((uint8_t)0x7B)
AnnaBridge	171:3a7713b1edbc	404	#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
AnnaBridge	171:3a7713b1edbc	405	#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
AnnaBridge	171:3a7713b1edbc	406	#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
AnnaBridge	171:3a7713b1edbc	407	#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
AnnaBridge	171:3a7713b1edbc	408	/**
AnnaBridge	171:3a7713b1edbc	409	* @}
AnnaBridge	171:3a7713b1edbc	410	*/
AnnaBridge	171:3a7713b1edbc	411
AnnaBridge	171:3a7713b1edbc	412	/**
AnnaBridge	171:3a7713b1edbc	413	* @}
AnnaBridge	171:3a7713b1edbc	414	*/
AnnaBridge	171:3a7713b1edbc	415
AnnaBridge	171:3a7713b1edbc	416	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	417	/** @defgroup RCC_Exported_Macros RCC Exported Macros
AnnaBridge	171:3a7713b1edbc	418	* @{
AnnaBridge	171:3a7713b1edbc	419	*/
AnnaBridge	171:3a7713b1edbc	420
AnnaBridge	171:3a7713b1edbc	421	/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
AnnaBridge	171:3a7713b1edbc	422	* @brief Enable or disable the AHB1 peripheral clock.
AnnaBridge	171:3a7713b1edbc	423	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	171:3a7713b1edbc	424	* is disabled and the application software has to enable this clock before
AnnaBridge	171:3a7713b1edbc	425	* using it.
AnnaBridge	171:3a7713b1edbc	426	* @{
AnnaBridge	171:3a7713b1edbc	427	*/
AnnaBridge	171:3a7713b1edbc	428	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	429	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	430	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
AnnaBridge	171:3a7713b1edbc	431	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	432	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
AnnaBridge	171:3a7713b1edbc	433	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	434	} while(0)
AnnaBridge	171:3a7713b1edbc	435	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	436	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	437	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
AnnaBridge	171:3a7713b1edbc	438	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	439	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
AnnaBridge	171:3a7713b1edbc	440	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	441	} while(0)
AnnaBridge	171:3a7713b1edbc	442	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	443	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	444	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
AnnaBridge	171:3a7713b1edbc	445	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	446	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
AnnaBridge	171:3a7713b1edbc	447	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	448	} while(0)
AnnaBridge	171:3a7713b1edbc	449	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	450	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	451	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
AnnaBridge	171:3a7713b1edbc	452	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	453	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
AnnaBridge	171:3a7713b1edbc	454	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	455	} while(0)
AnnaBridge	171:3a7713b1edbc	456	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	457	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	458	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
AnnaBridge	171:3a7713b1edbc	459	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	460	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
AnnaBridge	171:3a7713b1edbc	461	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	462	} while(0)
AnnaBridge	171:3a7713b1edbc	463	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	464	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	465	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
AnnaBridge	171:3a7713b1edbc	466	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	467	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
AnnaBridge	171:3a7713b1edbc	468	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	469	} while(0)
AnnaBridge	171:3a7713b1edbc	470	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	471	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	472	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
AnnaBridge	171:3a7713b1edbc	473	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	474	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
AnnaBridge	171:3a7713b1edbc	475	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	476	} while(0)
AnnaBridge	171:3a7713b1edbc	477	#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	478	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	479	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
AnnaBridge	171:3a7713b1edbc	480	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	481	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
AnnaBridge	171:3a7713b1edbc	482	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	483	} while(0)
AnnaBridge	171:3a7713b1edbc	484	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	485	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	486	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
AnnaBridge	171:3a7713b1edbc	487	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	488	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
AnnaBridge	171:3a7713b1edbc	489	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	490	} while(0)
AnnaBridge	171:3a7713b1edbc	491	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	492	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	493	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
AnnaBridge	171:3a7713b1edbc	494	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	495	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
AnnaBridge	171:3a7713b1edbc	496	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	497	} while(0)
AnnaBridge	171:3a7713b1edbc	498	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	499	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	500	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
AnnaBridge	171:3a7713b1edbc	501	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	502	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
AnnaBridge	171:3a7713b1edbc	503	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	504	} while(0)
AnnaBridge	171:3a7713b1edbc	505	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	506	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	507	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
AnnaBridge	171:3a7713b1edbc	508	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	509	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
AnnaBridge	171:3a7713b1edbc	510	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	511	} while(0)
AnnaBridge	171:3a7713b1edbc	512	#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	513	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	514	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
AnnaBridge	171:3a7713b1edbc	515	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	516	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
AnnaBridge	171:3a7713b1edbc	517	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	518	} while(0)
AnnaBridge	171:3a7713b1edbc	519	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	520	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	521	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
AnnaBridge	171:3a7713b1edbc	522	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	523	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
AnnaBridge	171:3a7713b1edbc	524	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	525	} while(0)
AnnaBridge	171:3a7713b1edbc	526	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	527	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	528	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
AnnaBridge	171:3a7713b1edbc	529	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	530	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
AnnaBridge	171:3a7713b1edbc	531	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	532	} while(0)
AnnaBridge	171:3a7713b1edbc	533	#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
AnnaBridge	171:3a7713b1edbc	534	#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
AnnaBridge	171:3a7713b1edbc	535	#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
AnnaBridge	171:3a7713b1edbc	536	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
AnnaBridge	171:3a7713b1edbc	537	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
AnnaBridge	171:3a7713b1edbc	538	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
AnnaBridge	171:3a7713b1edbc	539	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
AnnaBridge	171:3a7713b1edbc	540	#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
AnnaBridge	171:3a7713b1edbc	541	#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
AnnaBridge	171:3a7713b1edbc	542	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
AnnaBridge	171:3a7713b1edbc	543	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
AnnaBridge	171:3a7713b1edbc	544	#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
AnnaBridge	171:3a7713b1edbc	545	#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
AnnaBridge	171:3a7713b1edbc	546	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
AnnaBridge	171:3a7713b1edbc	547	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
AnnaBridge	171:3a7713b1edbc	548	/**
AnnaBridge	171:3a7713b1edbc	549	* @}
AnnaBridge	171:3a7713b1edbc	550	*/
AnnaBridge	171:3a7713b1edbc	551	/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
AnnaBridge	171:3a7713b1edbc	552	* @brief Get the enable or disable status of the AHB1 peripheral clock.
AnnaBridge	171:3a7713b1edbc	553	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	171:3a7713b1edbc	554	* is disabled and the application software has to enable this clock before
AnnaBridge	171:3a7713b1edbc	555	* using it.
AnnaBridge	171:3a7713b1edbc	556	* @{
AnnaBridge	171:3a7713b1edbc	557	*/
AnnaBridge	171:3a7713b1edbc	558	#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	559	#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	560	#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	561	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIODEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	562	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOEEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	563	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOFEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	564	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOGEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	565	#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	566	#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOIEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	567	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_CRCEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	568	#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_BKPSRAMEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	569	#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	570	#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	571	#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_OTGHSEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	572	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	573
AnnaBridge	171:3a7713b1edbc	574	#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	575	#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	576	#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	577	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIODEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	578	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOEEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	579	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOFEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	580	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOGEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	581	#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	582	#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOIEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	583	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_CRCEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	584	#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_BKPSRAMEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	585	#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	586	#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	587	#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_OTGHSEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	588	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	589	/**
AnnaBridge	171:3a7713b1edbc	590	* @}
AnnaBridge	171:3a7713b1edbc	591	*/
AnnaBridge	171:3a7713b1edbc	592
AnnaBridge	171:3a7713b1edbc	593	/** @defgroup RCC_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
AnnaBridge	171:3a7713b1edbc	594	* @brief Enable or disable the AHB2 peripheral clock.
AnnaBridge	171:3a7713b1edbc	595	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	171:3a7713b1edbc	596	* is disabled and the application software has to enable this clock before
AnnaBridge	171:3a7713b1edbc	597	* using it.
AnnaBridge	171:3a7713b1edbc	598	* @{
AnnaBridge	171:3a7713b1edbc	599	*/
AnnaBridge	171:3a7713b1edbc	600	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
AnnaBridge	171:3a7713b1edbc	601	__HAL_RCC_SYSCFG_CLK_ENABLE();\
AnnaBridge	171:3a7713b1edbc	602	}while(0)
AnnaBridge	171:3a7713b1edbc	603	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	604	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	605	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
AnnaBridge	171:3a7713b1edbc	606	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	607	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
AnnaBridge	171:3a7713b1edbc	608	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	609	} while(0)
AnnaBridge	171:3a7713b1edbc	610
AnnaBridge	171:3a7713b1edbc	611	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
AnnaBridge	171:3a7713b1edbc	612	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
AnnaBridge	171:3a7713b1edbc	613	/**
AnnaBridge	171:3a7713b1edbc	614	* @}
AnnaBridge	171:3a7713b1edbc	615	*/
AnnaBridge	171:3a7713b1edbc	616
AnnaBridge	171:3a7713b1edbc	617	/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
AnnaBridge	171:3a7713b1edbc	618	* @brief Get the enable or disable status of the AHB2 peripheral clock.
AnnaBridge	171:3a7713b1edbc	619	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	171:3a7713b1edbc	620	* is disabled and the application software has to enable this clock before
AnnaBridge	171:3a7713b1edbc	621	* using it.
AnnaBridge	171:3a7713b1edbc	622	* @{
AnnaBridge	171:3a7713b1edbc	623	*/
AnnaBridge	171:3a7713b1edbc	624	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_OTGFSEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	625	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_RNGEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	626
AnnaBridge	171:3a7713b1edbc	627	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_OTGFSEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	628	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR &(RCC_AHB2ENR_RNGEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	629	/**
AnnaBridge	171:3a7713b1edbc	630	* @}
AnnaBridge	171:3a7713b1edbc	631	*/
AnnaBridge	171:3a7713b1edbc	632
AnnaBridge	171:3a7713b1edbc	633	/** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
AnnaBridge	171:3a7713b1edbc	634	* @brief Enables or disables the AHB3 peripheral clock.
AnnaBridge	171:3a7713b1edbc	635	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	171:3a7713b1edbc	636	* is disabled and the application software has to enable this clock before
AnnaBridge	171:3a7713b1edbc	637	* using it.
AnnaBridge	171:3a7713b1edbc	638	* @{
AnnaBridge	171:3a7713b1edbc	639	*/
AnnaBridge	171:3a7713b1edbc	640	#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	641	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	642	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
AnnaBridge	171:3a7713b1edbc	643	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	644	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
AnnaBridge	171:3a7713b1edbc	645	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	646	} while(0)
AnnaBridge	171:3a7713b1edbc	647	#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
AnnaBridge	171:3a7713b1edbc	648	/**
AnnaBridge	171:3a7713b1edbc	649	* @}
AnnaBridge	171:3a7713b1edbc	650	*/
AnnaBridge	171:3a7713b1edbc	651
AnnaBridge	171:3a7713b1edbc	652	/** @defgroup RCC_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
AnnaBridge	171:3a7713b1edbc	653	* @brief Get the enable or disable status of the AHB3 peripheral clock.
AnnaBridge	171:3a7713b1edbc	654	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	171:3a7713b1edbc	655	* is disabled and the application software has to enable this clock before
AnnaBridge	171:3a7713b1edbc	656	* using it.
AnnaBridge	171:3a7713b1edbc	657	* @{
AnnaBridge	171:3a7713b1edbc	658	*/
AnnaBridge	171:3a7713b1edbc	659	#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHB3ENR &(RCC_AHB3ENR_FSMCEN))!= RESET)
AnnaBridge	171:3a7713b1edbc	660	#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR &(RCC_AHB3ENR_FSMCEN))== RESET)
AnnaBridge	171:3a7713b1edbc	661	/**
AnnaBridge	171:3a7713b1edbc	662	* @}
AnnaBridge	171:3a7713b1edbc	663	*/
AnnaBridge	171:3a7713b1edbc	664
AnnaBridge	171:3a7713b1edbc	665	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
AnnaBridge	171:3a7713b1edbc	666	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
AnnaBridge	171:3a7713b1edbc	667	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	171:3a7713b1edbc	668	* is disabled and the application software has to enable this clock before
AnnaBridge	171:3a7713b1edbc	669	* using it.
AnnaBridge	171:3a7713b1edbc	670	* @{
AnnaBridge	171:3a7713b1edbc	671	*/
AnnaBridge	171:3a7713b1edbc	672	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	673	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	674	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge	171:3a7713b1edbc	675	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	676	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge	171:3a7713b1edbc	677	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	678	} while(0)
AnnaBridge	171:3a7713b1edbc	679	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	680	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	681	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	171:3a7713b1edbc	682	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	683	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	171:3a7713b1edbc	684	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	685	} while(0)
AnnaBridge	171:3a7713b1edbc	686	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	687	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	688	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	171:3a7713b1edbc	689	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	690	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	171:3a7713b1edbc	691	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	692	} while(0)
AnnaBridge	171:3a7713b1edbc	693	#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	694	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	695	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
AnnaBridge	171:3a7713b1edbc	696	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	697	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
AnnaBridge	171:3a7713b1edbc	698	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	699	} while(0)
AnnaBridge	171:3a7713b1edbc	700	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	701	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	702	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge	171:3a7713b1edbc	703	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	704	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge	171:3a7713b1edbc	705	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	706	} while(0)
AnnaBridge	171:3a7713b1edbc	707	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	708	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	709	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
AnnaBridge	171:3a7713b1edbc	710	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	711	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
AnnaBridge	171:3a7713b1edbc	712	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	713	} while(0)
AnnaBridge	171:3a7713b1edbc	714	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	715	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	716	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
AnnaBridge	171:3a7713b1edbc	717	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	718	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
AnnaBridge	171:3a7713b1edbc	719	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	720	} while(0)
AnnaBridge	171:3a7713b1edbc	721	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	722	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	723	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
AnnaBridge	171:3a7713b1edbc	724	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	725	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
AnnaBridge	171:3a7713b1edbc	726	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	727	} while(0)
AnnaBridge	171:3a7713b1edbc	728	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	729	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	730	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge	171:3a7713b1edbc	731	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	732	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge	171:3a7713b1edbc	733	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	734	} while(0)
AnnaBridge	171:3a7713b1edbc	735	#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	736	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	737	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
AnnaBridge	171:3a7713b1edbc	738	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	739	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
AnnaBridge	171:3a7713b1edbc	740	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	741	} while(0)
AnnaBridge	171:3a7713b1edbc	742	#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	743	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	744	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
AnnaBridge	171:3a7713b1edbc	745	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	746	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
AnnaBridge	171:3a7713b1edbc	747	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	748	} while(0)
AnnaBridge	171:3a7713b1edbc	749	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	750	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	751	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	171:3a7713b1edbc	752	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	753	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	171:3a7713b1edbc	754	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	755	} while(0)
AnnaBridge	171:3a7713b1edbc	756	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	757	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	758	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
AnnaBridge	171:3a7713b1edbc	759	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	760	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
AnnaBridge	171:3a7713b1edbc	761	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	762	} while(0)
AnnaBridge	171:3a7713b1edbc	763	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	764	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	765	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
AnnaBridge	171:3a7713b1edbc	766	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	767	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
AnnaBridge	171:3a7713b1edbc	768	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	769	} while(0)
AnnaBridge	171:3a7713b1edbc	770	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	771	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	772	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
AnnaBridge	171:3a7713b1edbc	773	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	774	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
AnnaBridge	171:3a7713b1edbc	775	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	776	} while(0)
AnnaBridge	171:3a7713b1edbc	777	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	778	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	779	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
AnnaBridge	171:3a7713b1edbc	780	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	781	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
AnnaBridge	171:3a7713b1edbc	782	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	783	} while(0)
AnnaBridge	171:3a7713b1edbc	784	#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	785	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	786	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
AnnaBridge	171:3a7713b1edbc	787	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	788	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
AnnaBridge	171:3a7713b1edbc	789	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	790	} while(0)
AnnaBridge	171:3a7713b1edbc	791	#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	792	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	793	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
AnnaBridge	171:3a7713b1edbc	794	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	795	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
AnnaBridge	171:3a7713b1edbc	796	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	797	} while(0)
AnnaBridge	171:3a7713b1edbc	798	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	799	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	800	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge	171:3a7713b1edbc	801	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	802	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
AnnaBridge	171:3a7713b1edbc	803	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	804	} while(0)
AnnaBridge	171:3a7713b1edbc	805	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	806	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	807	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
AnnaBridge	171:3a7713b1edbc	808	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	809	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
AnnaBridge	171:3a7713b1edbc	810	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	811	} while(0)
AnnaBridge	171:3a7713b1edbc	812	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	813	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	814	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
AnnaBridge	171:3a7713b1edbc	815	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	816	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
AnnaBridge	171:3a7713b1edbc	817	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	818	} while(0)
AnnaBridge	171:3a7713b1edbc	819	#define __HAL_RCC_PWR_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	820	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	821	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
AnnaBridge	171:3a7713b1edbc	822	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	823	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
AnnaBridge	171:3a7713b1edbc	824	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	825	} while(0)
AnnaBridge	171:3a7713b1edbc	826	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	827	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	828	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge	171:3a7713b1edbc	829	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	830	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge	171:3a7713b1edbc	831	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	832	} while(0)
AnnaBridge	171:3a7713b1edbc	833
AnnaBridge	171:3a7713b1edbc	834	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
AnnaBridge	171:3a7713b1edbc	835	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
AnnaBridge	171:3a7713b1edbc	836	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
AnnaBridge	171:3a7713b1edbc	837	#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
AnnaBridge	171:3a7713b1edbc	838	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
AnnaBridge	171:3a7713b1edbc	839	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
AnnaBridge	171:3a7713b1edbc	840	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
AnnaBridge	171:3a7713b1edbc	841	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
AnnaBridge	171:3a7713b1edbc	842	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
AnnaBridge	171:3a7713b1edbc	843	#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
AnnaBridge	171:3a7713b1edbc	844	#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
AnnaBridge	171:3a7713b1edbc	845	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
AnnaBridge	171:3a7713b1edbc	846	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
AnnaBridge	171:3a7713b1edbc	847	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
AnnaBridge	171:3a7713b1edbc	848	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
AnnaBridge	171:3a7713b1edbc	849	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
AnnaBridge	171:3a7713b1edbc	850	#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
AnnaBridge	171:3a7713b1edbc	851	#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
AnnaBridge	171:3a7713b1edbc	852	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
AnnaBridge	171:3a7713b1edbc	853	#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
AnnaBridge	171:3a7713b1edbc	854	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
AnnaBridge	171:3a7713b1edbc	855	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
AnnaBridge	171:3a7713b1edbc	856	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
AnnaBridge	171:3a7713b1edbc	857	/**
AnnaBridge	171:3a7713b1edbc	858	* @}
AnnaBridge	171:3a7713b1edbc	859	*/
AnnaBridge	171:3a7713b1edbc	860
AnnaBridge	171:3a7713b1edbc	861	/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
AnnaBridge	171:3a7713b1edbc	862	* @brief Get the enable or disable status of the APB1 peripheral clock.
AnnaBridge	171:3a7713b1edbc	863	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	171:3a7713b1edbc	864	* is disabled and the application software has to enable this clock before
AnnaBridge	171:3a7713b1edbc	865	* using it.
AnnaBridge	171:3a7713b1edbc	866	* @{
AnnaBridge	171:3a7713b1edbc	867	*/
AnnaBridge	171:3a7713b1edbc	868	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM2EN))!= RESET)
AnnaBridge	171:3a7713b1edbc	869	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM3EN))!= RESET)
AnnaBridge	171:3a7713b1edbc	870	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM4EN))!= RESET)
AnnaBridge	171:3a7713b1edbc	871	#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM5EN))!= RESET)
AnnaBridge	171:3a7713b1edbc	872	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM6EN))!= RESET)
AnnaBridge	171:3a7713b1edbc	873	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM7EN))!= RESET)
AnnaBridge	171:3a7713b1edbc	874	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM12EN))!= RESET)
AnnaBridge	171:3a7713b1edbc	875	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM13EN))!= RESET)
AnnaBridge	171:3a7713b1edbc	876	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM14EN))!= RESET)
AnnaBridge	171:3a7713b1edbc	877	#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_WWDGEN))!= RESET)
AnnaBridge	171:3a7713b1edbc	878	#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_SPI2EN))!= RESET)
AnnaBridge	171:3a7713b1edbc	879	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_SPI3EN))!= RESET)
AnnaBridge	171:3a7713b1edbc	880	#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_USART2EN))!= RESET)
AnnaBridge	171:3a7713b1edbc	881	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_USART3EN))!= RESET)
AnnaBridge	171:3a7713b1edbc	882	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_UART4EN))!= RESET)
AnnaBridge	171:3a7713b1edbc	883	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_UART5EN))!= RESET)
AnnaBridge	171:3a7713b1edbc	884	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C1EN))!= RESET)
AnnaBridge	171:3a7713b1edbc	885	#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C2EN))!= RESET)
AnnaBridge	171:3a7713b1edbc	886	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C3EN))!= RESET)
AnnaBridge	171:3a7713b1edbc	887	#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_PWREN))!= RESET)
AnnaBridge	171:3a7713b1edbc	888	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_CAN1EN))!= RESET)
AnnaBridge	171:3a7713b1edbc	889	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_CAN2EN))!= RESET)
AnnaBridge	171:3a7713b1edbc	890	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR &(RCC_APB1ENR_DACEN))!= RESET)
AnnaBridge	171:3a7713b1edbc	891
AnnaBridge	171:3a7713b1edbc	892	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM2EN))== RESET)
AnnaBridge	171:3a7713b1edbc	893	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM3EN))== RESET)
AnnaBridge	171:3a7713b1edbc	894	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM4EN))== RESET)
AnnaBridge	171:3a7713b1edbc	895	#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM5EN))== RESET)
AnnaBridge	171:3a7713b1edbc	896	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM6EN))== RESET)
AnnaBridge	171:3a7713b1edbc	897	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM7EN))== RESET)
AnnaBridge	171:3a7713b1edbc	898	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM12EN))== RESET)
AnnaBridge	171:3a7713b1edbc	899	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM13EN))== RESET)
AnnaBridge	171:3a7713b1edbc	900	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_TIM14EN))== RESET)
AnnaBridge	171:3a7713b1edbc	901	#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_WWDGEN))== RESET)
AnnaBridge	171:3a7713b1edbc	902	#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_SPI2EN))== RESET)
AnnaBridge	171:3a7713b1edbc	903	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_SPI3EN))== RESET)
AnnaBridge	171:3a7713b1edbc	904	#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_USART2EN))== RESET)
AnnaBridge	171:3a7713b1edbc	905	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_USART3EN))== RESET)
AnnaBridge	171:3a7713b1edbc	906	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_UART4EN))== RESET)
AnnaBridge	171:3a7713b1edbc	907	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_UART5EN))== RESET)
AnnaBridge	171:3a7713b1edbc	908	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C1EN))== RESET)
AnnaBridge	171:3a7713b1edbc	909	#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C2EN))== RESET)
AnnaBridge	171:3a7713b1edbc	910	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_I2C3EN))== RESET)
AnnaBridge	171:3a7713b1edbc	911	#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_PWREN))== RESET)
AnnaBridge	171:3a7713b1edbc	912	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_CAN1EN))== RESET)
AnnaBridge	171:3a7713b1edbc	913	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_CAN2EN))== RESET)
AnnaBridge	171:3a7713b1edbc	914	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR &(RCC_APB1ENR_DACEN))== RESET)
AnnaBridge	171:3a7713b1edbc	915	/**
AnnaBridge	171:3a7713b1edbc	916	* @}
AnnaBridge	171:3a7713b1edbc	917	*/
AnnaBridge	171:3a7713b1edbc	918
AnnaBridge	171:3a7713b1edbc	919	/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
AnnaBridge	171:3a7713b1edbc	920	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
AnnaBridge	171:3a7713b1edbc	921	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	171:3a7713b1edbc	922	* is disabled and the application software has to enable this clock before
AnnaBridge	171:3a7713b1edbc	923	* using it.
AnnaBridge	171:3a7713b1edbc	924	* @{
AnnaBridge	171:3a7713b1edbc	925	*/
AnnaBridge	171:3a7713b1edbc	926	#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	927	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	928	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
AnnaBridge	171:3a7713b1edbc	929	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	930	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
AnnaBridge	171:3a7713b1edbc	931	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	932	} while(0)
AnnaBridge	171:3a7713b1edbc	933	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	934	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	935	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
AnnaBridge	171:3a7713b1edbc	936	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	937	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
AnnaBridge	171:3a7713b1edbc	938	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	939	} while(0)
AnnaBridge	171:3a7713b1edbc	940	#define __HAL_RCC_USART1_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	941	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	942	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
AnnaBridge	171:3a7713b1edbc	943	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	944	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
AnnaBridge	171:3a7713b1edbc	945	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	946	} while(0)
AnnaBridge	171:3a7713b1edbc	947	#define __HAL_RCC_USART6_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	948	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	949	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
AnnaBridge	171:3a7713b1edbc	950	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	951	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
AnnaBridge	171:3a7713b1edbc	952	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	953	} while(0)
AnnaBridge	171:3a7713b1edbc	954	#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	955	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	956	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
AnnaBridge	171:3a7713b1edbc	957	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	958	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
AnnaBridge	171:3a7713b1edbc	959	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	960	} while(0)
AnnaBridge	171:3a7713b1edbc	961	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	962	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	963	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
AnnaBridge	171:3a7713b1edbc	964	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	965	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
AnnaBridge	171:3a7713b1edbc	966	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	967	} while(0)
AnnaBridge	171:3a7713b1edbc	968	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	969	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	970	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
AnnaBridge	171:3a7713b1edbc	971	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	972	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
AnnaBridge	171:3a7713b1edbc	973	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	974	} while(0)
AnnaBridge	171:3a7713b1edbc	975	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	976	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	977	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
AnnaBridge	171:3a7713b1edbc	978	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	979	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
AnnaBridge	171:3a7713b1edbc	980	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	981	} while(0)
AnnaBridge	171:3a7713b1edbc	982	#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	983	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	984	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
AnnaBridge	171:3a7713b1edbc	985	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	986	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
AnnaBridge	171:3a7713b1edbc	987	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	988	} while(0)
AnnaBridge	171:3a7713b1edbc	989	#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	990	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	991	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
AnnaBridge	171:3a7713b1edbc	992	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	993	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
AnnaBridge	171:3a7713b1edbc	994	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	995	} while(0)
AnnaBridge	171:3a7713b1edbc	996
AnnaBridge	171:3a7713b1edbc	997	#define __HAL_RCC_TIM9_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	998	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	999	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
AnnaBridge	171:3a7713b1edbc	1000	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	1001	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
AnnaBridge	171:3a7713b1edbc	1002	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	1003	} while(0)
AnnaBridge	171:3a7713b1edbc	1004	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	1005	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	1006	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge	171:3a7713b1edbc	1007	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	1008	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge	171:3a7713b1edbc	1009	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	1010	} while(0)
AnnaBridge	171:3a7713b1edbc	1011	#define __HAL_RCC_TIM11_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	1012	__IO uint32_t tmpreg = 0x00U; \
AnnaBridge	171:3a7713b1edbc	1013	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
AnnaBridge	171:3a7713b1edbc	1014	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	1015	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
AnnaBridge	171:3a7713b1edbc	1016	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	1017	} while(0)
AnnaBridge	171:3a7713b1edbc	1018	#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
AnnaBridge	171:3a7713b1edbc	1019	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
AnnaBridge	171:3a7713b1edbc	1020	#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
AnnaBridge	171:3a7713b1edbc	1021	#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
AnnaBridge	171:3a7713b1edbc	1022	#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
AnnaBridge	171:3a7713b1edbc	1023	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
AnnaBridge	171:3a7713b1edbc	1024	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
AnnaBridge	171:3a7713b1edbc	1025	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
AnnaBridge	171:3a7713b1edbc	1026	#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
AnnaBridge	171:3a7713b1edbc	1027	#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
AnnaBridge	171:3a7713b1edbc	1028	#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
AnnaBridge	171:3a7713b1edbc	1029	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
AnnaBridge	171:3a7713b1edbc	1030	#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
AnnaBridge	171:3a7713b1edbc	1031	/**
AnnaBridge	171:3a7713b1edbc	1032	* @}
AnnaBridge	171:3a7713b1edbc	1033	*/
AnnaBridge	171:3a7713b1edbc	1034
AnnaBridge	171:3a7713b1edbc	1035	/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
AnnaBridge	171:3a7713b1edbc	1036	* @brief Get the enable or disable status of the APB2 peripheral clock.
AnnaBridge	171:3a7713b1edbc	1037	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	171:3a7713b1edbc	1038	* is disabled and the application software has to enable this clock before
AnnaBridge	171:3a7713b1edbc	1039	* using it.
AnnaBridge	171:3a7713b1edbc	1040	* @{
AnnaBridge	171:3a7713b1edbc	1041	*/
AnnaBridge	171:3a7713b1edbc	1042	#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM1EN))!= RESET)
AnnaBridge	171:3a7713b1edbc	1043	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM8EN))!= RESET)
AnnaBridge	171:3a7713b1edbc	1044	#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_USART1EN))!= RESET)
AnnaBridge	171:3a7713b1edbc	1045	#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_USART6EN))!= RESET)
AnnaBridge	171:3a7713b1edbc	1046	#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC1EN))!= RESET)
AnnaBridge	171:3a7713b1edbc	1047	#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC2EN))!= RESET)
AnnaBridge	171:3a7713b1edbc	1048	#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC3EN))!= RESET)
AnnaBridge	171:3a7713b1edbc	1049	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SDIOEN))!= RESET)
AnnaBridge	171:3a7713b1edbc	1050	#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SPI1EN))!= RESET)
AnnaBridge	171:3a7713b1edbc	1051	#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SYSCFGEN))!= RESET)
AnnaBridge	171:3a7713b1edbc	1052	#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM9EN))!= RESET)
AnnaBridge	171:3a7713b1edbc	1053	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM10EN))!= RESET)
AnnaBridge	171:3a7713b1edbc	1054	#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM11EN))!= RESET)
AnnaBridge	171:3a7713b1edbc	1055
AnnaBridge	171:3a7713b1edbc	1056	#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM1EN))== RESET)
AnnaBridge	171:3a7713b1edbc	1057	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM8EN))== RESET)
AnnaBridge	171:3a7713b1edbc	1058	#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_USART1EN))== RESET)
AnnaBridge	171:3a7713b1edbc	1059	#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_USART6EN))== RESET)
AnnaBridge	171:3a7713b1edbc	1060	#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC1EN))== RESET)
AnnaBridge	171:3a7713b1edbc	1061	#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC2EN))== RESET)
AnnaBridge	171:3a7713b1edbc	1062	#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_ADC3EN))== RESET)
AnnaBridge	171:3a7713b1edbc	1063	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SDIOEN))== RESET)
AnnaBridge	171:3a7713b1edbc	1064	#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SPI1EN))== RESET)
AnnaBridge	171:3a7713b1edbc	1065	#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_SYSCFGEN))== RESET)
AnnaBridge	171:3a7713b1edbc	1066	#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM9EN))== RESET)
AnnaBridge	171:3a7713b1edbc	1067	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM10EN))== RESET)
AnnaBridge	171:3a7713b1edbc	1068	#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR &(RCC_APB2ENR_TIM11EN))== RESET)
AnnaBridge	171:3a7713b1edbc	1069	/**
AnnaBridge	171:3a7713b1edbc	1070	* @}
AnnaBridge	171:3a7713b1edbc	1071	*/
AnnaBridge	171:3a7713b1edbc	1072
AnnaBridge	171:3a7713b1edbc	1073	/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset
AnnaBridge	171:3a7713b1edbc	1074	* @brief Force or release AHB1 peripheral reset.
AnnaBridge	171:3a7713b1edbc	1075	* @{
AnnaBridge	171:3a7713b1edbc	1076	*/
AnnaBridge	171:3a7713b1edbc	1077	#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
AnnaBridge	171:3a7713b1edbc	1078	#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOARST))
AnnaBridge	171:3a7713b1edbc	1079	#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOBRST))
AnnaBridge	171:3a7713b1edbc	1080	#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOCRST))
AnnaBridge	171:3a7713b1edbc	1081	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
AnnaBridge	171:3a7713b1edbc	1082	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
AnnaBridge	171:3a7713b1edbc	1083	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
AnnaBridge	171:3a7713b1edbc	1084	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
AnnaBridge	171:3a7713b1edbc	1085	#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOHRST))
AnnaBridge	171:3a7713b1edbc	1086	#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
AnnaBridge	171:3a7713b1edbc	1087	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
AnnaBridge	171:3a7713b1edbc	1088	#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA1RST))
AnnaBridge	171:3a7713b1edbc	1089	#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2RST))
AnnaBridge	171:3a7713b1edbc	1090	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
AnnaBridge	171:3a7713b1edbc	1091	#define __HAL_RCC_OTGHSULPI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHSULPIRST))
AnnaBridge	171:3a7713b1edbc	1092
AnnaBridge	171:3a7713b1edbc	1093	#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
AnnaBridge	171:3a7713b1edbc	1094	#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
AnnaBridge	171:3a7713b1edbc	1095	#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
AnnaBridge	171:3a7713b1edbc	1096	#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
AnnaBridge	171:3a7713b1edbc	1097	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
AnnaBridge	171:3a7713b1edbc	1098	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
AnnaBridge	171:3a7713b1edbc	1099	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
AnnaBridge	171:3a7713b1edbc	1100	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
AnnaBridge	171:3a7713b1edbc	1101	#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
AnnaBridge	171:3a7713b1edbc	1102	#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
AnnaBridge	171:3a7713b1edbc	1103	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
AnnaBridge	171:3a7713b1edbc	1104	#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
AnnaBridge	171:3a7713b1edbc	1105	#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
AnnaBridge	171:3a7713b1edbc	1106	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
AnnaBridge	171:3a7713b1edbc	1107	#define __HAL_RCC_OTGHSULPI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHSULPIRST))
AnnaBridge	171:3a7713b1edbc	1108	/**
AnnaBridge	171:3a7713b1edbc	1109	* @}
AnnaBridge	171:3a7713b1edbc	1110	*/
AnnaBridge	171:3a7713b1edbc	1111
AnnaBridge	171:3a7713b1edbc	1112	/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Force Release Reset
AnnaBridge	171:3a7713b1edbc	1113	* @brief Force or release AHB2 peripheral reset.
AnnaBridge	171:3a7713b1edbc	1114	* @{
AnnaBridge	171:3a7713b1edbc	1115	*/
AnnaBridge	171:3a7713b1edbc	1116	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
AnnaBridge	171:3a7713b1edbc	1117	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
AnnaBridge	171:3a7713b1edbc	1118	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
AnnaBridge	171:3a7713b1edbc	1119
AnnaBridge	171:3a7713b1edbc	1120	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
AnnaBridge	171:3a7713b1edbc	1121	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
AnnaBridge	171:3a7713b1edbc	1122	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
AnnaBridge	171:3a7713b1edbc	1123	/**
AnnaBridge	171:3a7713b1edbc	1124	* @}
AnnaBridge	171:3a7713b1edbc	1125	*/
AnnaBridge	171:3a7713b1edbc	1126
AnnaBridge	171:3a7713b1edbc	1127	/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
AnnaBridge	171:3a7713b1edbc	1128	* @brief Force or release APB1 peripheral reset.
AnnaBridge	171:3a7713b1edbc	1129	* @{
AnnaBridge	171:3a7713b1edbc	1130	*/
AnnaBridge	171:3a7713b1edbc	1131	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
AnnaBridge	171:3a7713b1edbc	1132	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
AnnaBridge	171:3a7713b1edbc	1133	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
AnnaBridge	171:3a7713b1edbc	1134	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
AnnaBridge	171:3a7713b1edbc	1135	#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM5RST))
AnnaBridge	171:3a7713b1edbc	1136	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
AnnaBridge	171:3a7713b1edbc	1137	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
AnnaBridge	171:3a7713b1edbc	1138	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
AnnaBridge	171:3a7713b1edbc	1139	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
AnnaBridge	171:3a7713b1edbc	1140	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
AnnaBridge	171:3a7713b1edbc	1141	#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
AnnaBridge	171:3a7713b1edbc	1142	#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
AnnaBridge	171:3a7713b1edbc	1143	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
AnnaBridge	171:3a7713b1edbc	1144	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
AnnaBridge	171:3a7713b1edbc	1145	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
AnnaBridge	171:3a7713b1edbc	1146	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
AnnaBridge	171:3a7713b1edbc	1147	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
AnnaBridge	171:3a7713b1edbc	1148	#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
AnnaBridge	171:3a7713b1edbc	1149	#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
AnnaBridge	171:3a7713b1edbc	1150	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
AnnaBridge	171:3a7713b1edbc	1151	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
AnnaBridge	171:3a7713b1edbc	1152	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
AnnaBridge	171:3a7713b1edbc	1153	#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
AnnaBridge	171:3a7713b1edbc	1154	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
AnnaBridge	171:3a7713b1edbc	1155
AnnaBridge	171:3a7713b1edbc	1156	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
AnnaBridge	171:3a7713b1edbc	1157	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
AnnaBridge	171:3a7713b1edbc	1158	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
AnnaBridge	171:3a7713b1edbc	1159	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
AnnaBridge	171:3a7713b1edbc	1160	#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
AnnaBridge	171:3a7713b1edbc	1161	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
AnnaBridge	171:3a7713b1edbc	1162	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
AnnaBridge	171:3a7713b1edbc	1163	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
AnnaBridge	171:3a7713b1edbc	1164	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
AnnaBridge	171:3a7713b1edbc	1165	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
AnnaBridge	171:3a7713b1edbc	1166	#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
AnnaBridge	171:3a7713b1edbc	1167	#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
AnnaBridge	171:3a7713b1edbc	1168	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
AnnaBridge	171:3a7713b1edbc	1169	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
AnnaBridge	171:3a7713b1edbc	1170	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
AnnaBridge	171:3a7713b1edbc	1171	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
AnnaBridge	171:3a7713b1edbc	1172	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
AnnaBridge	171:3a7713b1edbc	1173	#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
AnnaBridge	171:3a7713b1edbc	1174	#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
AnnaBridge	171:3a7713b1edbc	1175	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
AnnaBridge	171:3a7713b1edbc	1176	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
AnnaBridge	171:3a7713b1edbc	1177	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
AnnaBridge	171:3a7713b1edbc	1178	#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
AnnaBridge	171:3a7713b1edbc	1179	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
AnnaBridge	171:3a7713b1edbc	1180	/**
AnnaBridge	171:3a7713b1edbc	1181	* @}
AnnaBridge	171:3a7713b1edbc	1182	*/
AnnaBridge	171:3a7713b1edbc	1183
AnnaBridge	171:3a7713b1edbc	1184	/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
AnnaBridge	171:3a7713b1edbc	1185	* @brief Force or release APB2 peripheral reset.
AnnaBridge	171:3a7713b1edbc	1186	* @{
AnnaBridge	171:3a7713b1edbc	1187	*/
AnnaBridge	171:3a7713b1edbc	1188	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
AnnaBridge	171:3a7713b1edbc	1189	#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
AnnaBridge	171:3a7713b1edbc	1190	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
AnnaBridge	171:3a7713b1edbc	1191	#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
AnnaBridge	171:3a7713b1edbc	1192	#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART6RST))
AnnaBridge	171:3a7713b1edbc	1193	#define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADCRST))
AnnaBridge	171:3a7713b1edbc	1194	#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
AnnaBridge	171:3a7713b1edbc	1195	#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
AnnaBridge	171:3a7713b1edbc	1196	#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
AnnaBridge	171:3a7713b1edbc	1197	#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM9RST))
AnnaBridge	171:3a7713b1edbc	1198	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
AnnaBridge	171:3a7713b1edbc	1199	#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM11RST))
AnnaBridge	171:3a7713b1edbc	1200
AnnaBridge	171:3a7713b1edbc	1201	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
AnnaBridge	171:3a7713b1edbc	1202	#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
AnnaBridge	171:3a7713b1edbc	1203	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
AnnaBridge	171:3a7713b1edbc	1204	#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
AnnaBridge	171:3a7713b1edbc	1205	#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
AnnaBridge	171:3a7713b1edbc	1206	#define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
AnnaBridge	171:3a7713b1edbc	1207	#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
AnnaBridge	171:3a7713b1edbc	1208	#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
AnnaBridge	171:3a7713b1edbc	1209	#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
AnnaBridge	171:3a7713b1edbc	1210	#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
AnnaBridge	171:3a7713b1edbc	1211	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
AnnaBridge	171:3a7713b1edbc	1212	#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
AnnaBridge	171:3a7713b1edbc	1213	/**
AnnaBridge	171:3a7713b1edbc	1214	* @}
AnnaBridge	171:3a7713b1edbc	1215	*/
AnnaBridge	171:3a7713b1edbc	1216
AnnaBridge	171:3a7713b1edbc	1217	/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Force Release Reset
AnnaBridge	171:3a7713b1edbc	1218	* @brief Force or release AHB3 peripheral reset.
AnnaBridge	171:3a7713b1edbc	1219	* @{
AnnaBridge	171:3a7713b1edbc	1220	*/
AnnaBridge	171:3a7713b1edbc	1221	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
AnnaBridge	171:3a7713b1edbc	1222	#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FSMCRST))
AnnaBridge	171:3a7713b1edbc	1223
AnnaBridge	171:3a7713b1edbc	1224	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
AnnaBridge	171:3a7713b1edbc	1225	#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
AnnaBridge	171:3a7713b1edbc	1226	/**
AnnaBridge	171:3a7713b1edbc	1227	* @}
AnnaBridge	171:3a7713b1edbc	1228	*/
AnnaBridge	171:3a7713b1edbc	1229
AnnaBridge	171:3a7713b1edbc	1230	/** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
AnnaBridge	171:3a7713b1edbc	1231	* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	171:3a7713b1edbc	1232	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	171:3a7713b1edbc	1233	* power consumption.
AnnaBridge	171:3a7713b1edbc	1234	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	171:3a7713b1edbc	1235	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	171:3a7713b1edbc	1236	* @{
AnnaBridge	171:3a7713b1edbc	1237	*/
AnnaBridge	171:3a7713b1edbc	1238	#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOALPEN))
AnnaBridge	171:3a7713b1edbc	1239	#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOBLPEN))
AnnaBridge	171:3a7713b1edbc	1240	#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOCLPEN))
AnnaBridge	171:3a7713b1edbc	1241	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
AnnaBridge	171:3a7713b1edbc	1242	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
AnnaBridge	171:3a7713b1edbc	1243	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
AnnaBridge	171:3a7713b1edbc	1244	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
AnnaBridge	171:3a7713b1edbc	1245	#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOHLPEN))
AnnaBridge	171:3a7713b1edbc	1246	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
AnnaBridge	171:3a7713b1edbc	1247	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
AnnaBridge	171:3a7713b1edbc	1248	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
AnnaBridge	171:3a7713b1edbc	1249	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge	171:3a7713b1edbc	1250	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
AnnaBridge	171:3a7713b1edbc	1251	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
AnnaBridge	171:3a7713b1edbc	1252	#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA1LPEN))
AnnaBridge	171:3a7713b1edbc	1253	#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2LPEN))
AnnaBridge	171:3a7713b1edbc	1254	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
AnnaBridge	171:3a7713b1edbc	1255	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
AnnaBridge	171:3a7713b1edbc	1256
AnnaBridge	171:3a7713b1edbc	1257	#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
AnnaBridge	171:3a7713b1edbc	1258	#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
AnnaBridge	171:3a7713b1edbc	1259	#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
AnnaBridge	171:3a7713b1edbc	1260	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
AnnaBridge	171:3a7713b1edbc	1261	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
AnnaBridge	171:3a7713b1edbc	1262	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
AnnaBridge	171:3a7713b1edbc	1263	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
AnnaBridge	171:3a7713b1edbc	1264	#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
AnnaBridge	171:3a7713b1edbc	1265	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
AnnaBridge	171:3a7713b1edbc	1266	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
AnnaBridge	171:3a7713b1edbc	1267	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
AnnaBridge	171:3a7713b1edbc	1268	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
AnnaBridge	171:3a7713b1edbc	1269	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
AnnaBridge	171:3a7713b1edbc	1270	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
AnnaBridge	171:3a7713b1edbc	1271	#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
AnnaBridge	171:3a7713b1edbc	1272	#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
AnnaBridge	171:3a7713b1edbc	1273	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
AnnaBridge	171:3a7713b1edbc	1274	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
AnnaBridge	171:3a7713b1edbc	1275	/**
AnnaBridge	171:3a7713b1edbc	1276	* @}
AnnaBridge	171:3a7713b1edbc	1277	*/
AnnaBridge	171:3a7713b1edbc	1278
AnnaBridge	171:3a7713b1edbc	1279	/** @defgroup RCC_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
AnnaBridge	171:3a7713b1edbc	1280	* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	171:3a7713b1edbc	1281	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	171:3a7713b1edbc	1282	* power consumption.
AnnaBridge	171:3a7713b1edbc	1283	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	171:3a7713b1edbc	1284	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	171:3a7713b1edbc	1285	* @{
AnnaBridge	171:3a7713b1edbc	1286	*/
AnnaBridge	171:3a7713b1edbc	1287	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
AnnaBridge	171:3a7713b1edbc	1288	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
AnnaBridge	171:3a7713b1edbc	1289
AnnaBridge	171:3a7713b1edbc	1290	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
AnnaBridge	171:3a7713b1edbc	1291	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
AnnaBridge	171:3a7713b1edbc	1292	/**
AnnaBridge	171:3a7713b1edbc	1293	* @}
AnnaBridge	171:3a7713b1edbc	1294	*/
AnnaBridge	171:3a7713b1edbc	1295
AnnaBridge	171:3a7713b1edbc	1296	/** @defgroup RCC_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
AnnaBridge	171:3a7713b1edbc	1297	* @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	171:3a7713b1edbc	1298	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	171:3a7713b1edbc	1299	* power consumption.
AnnaBridge	171:3a7713b1edbc	1300	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	171:3a7713b1edbc	1301	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	171:3a7713b1edbc	1302	* @{
AnnaBridge	171:3a7713b1edbc	1303	*/
AnnaBridge	171:3a7713b1edbc	1304	#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FSMCLPEN))
AnnaBridge	171:3a7713b1edbc	1305	#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
AnnaBridge	171:3a7713b1edbc	1306	/**
AnnaBridge	171:3a7713b1edbc	1307	* @}
AnnaBridge	171:3a7713b1edbc	1308	*/
AnnaBridge	171:3a7713b1edbc	1309
AnnaBridge	171:3a7713b1edbc	1310	/** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
AnnaBridge	171:3a7713b1edbc	1311	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	171:3a7713b1edbc	1312	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	171:3a7713b1edbc	1313	* power consumption.
AnnaBridge	171:3a7713b1edbc	1314	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	171:3a7713b1edbc	1315	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	171:3a7713b1edbc	1316	* @{
AnnaBridge	171:3a7713b1edbc	1317	*/
AnnaBridge	171:3a7713b1edbc	1318	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
AnnaBridge	171:3a7713b1edbc	1319	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
AnnaBridge	171:3a7713b1edbc	1320	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
AnnaBridge	171:3a7713b1edbc	1321	#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM5LPEN))
AnnaBridge	171:3a7713b1edbc	1322	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
AnnaBridge	171:3a7713b1edbc	1323	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
AnnaBridge	171:3a7713b1edbc	1324	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
AnnaBridge	171:3a7713b1edbc	1325	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
AnnaBridge	171:3a7713b1edbc	1326	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
AnnaBridge	171:3a7713b1edbc	1327	#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_WWDGLPEN))
AnnaBridge	171:3a7713b1edbc	1328	#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI2LPEN))
AnnaBridge	171:3a7713b1edbc	1329	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
AnnaBridge	171:3a7713b1edbc	1330	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART2LPEN))
AnnaBridge	171:3a7713b1edbc	1331	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
AnnaBridge	171:3a7713b1edbc	1332	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
AnnaBridge	171:3a7713b1edbc	1333	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
AnnaBridge	171:3a7713b1edbc	1334	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C1LPEN))
AnnaBridge	171:3a7713b1edbc	1335	#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C2LPEN))
AnnaBridge	171:3a7713b1edbc	1336	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
AnnaBridge	171:3a7713b1edbc	1337	#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_PWRLPEN))
AnnaBridge	171:3a7713b1edbc	1338	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
AnnaBridge	171:3a7713b1edbc	1339	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
AnnaBridge	171:3a7713b1edbc	1340	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
AnnaBridge	171:3a7713b1edbc	1341	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
AnnaBridge	171:3a7713b1edbc	1342	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
AnnaBridge	171:3a7713b1edbc	1343	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
AnnaBridge	171:3a7713b1edbc	1344	#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
AnnaBridge	171:3a7713b1edbc	1345	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
AnnaBridge	171:3a7713b1edbc	1346	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
AnnaBridge	171:3a7713b1edbc	1347	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
AnnaBridge	171:3a7713b1edbc	1348	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
AnnaBridge	171:3a7713b1edbc	1349	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
AnnaBridge	171:3a7713b1edbc	1350	#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
AnnaBridge	171:3a7713b1edbc	1351	#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
AnnaBridge	171:3a7713b1edbc	1352	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
AnnaBridge	171:3a7713b1edbc	1353	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
AnnaBridge	171:3a7713b1edbc	1354	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
AnnaBridge	171:3a7713b1edbc	1355	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
AnnaBridge	171:3a7713b1edbc	1356	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
AnnaBridge	171:3a7713b1edbc	1357	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
AnnaBridge	171:3a7713b1edbc	1358	#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
AnnaBridge	171:3a7713b1edbc	1359	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
AnnaBridge	171:3a7713b1edbc	1360	#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
AnnaBridge	171:3a7713b1edbc	1361	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
AnnaBridge	171:3a7713b1edbc	1362	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
AnnaBridge	171:3a7713b1edbc	1363	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
AnnaBridge	171:3a7713b1edbc	1364	/**
AnnaBridge	171:3a7713b1edbc	1365	* @}
AnnaBridge	171:3a7713b1edbc	1366	*/
AnnaBridge	171:3a7713b1edbc	1367
AnnaBridge	171:3a7713b1edbc	1368	/** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
AnnaBridge	171:3a7713b1edbc	1369	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
AnnaBridge	171:3a7713b1edbc	1370	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
AnnaBridge	171:3a7713b1edbc	1371	* power consumption.
AnnaBridge	171:3a7713b1edbc	1372	* @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
AnnaBridge	171:3a7713b1edbc	1373	* @note By default, all peripheral clocks are enabled during SLEEP mode.
AnnaBridge	171:3a7713b1edbc	1374	* @{
AnnaBridge	171:3a7713b1edbc	1375	*/
AnnaBridge	171:3a7713b1edbc	1376	#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM1LPEN))
AnnaBridge	171:3a7713b1edbc	1377	#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART1LPEN))
AnnaBridge	171:3a7713b1edbc	1378	#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART6LPEN))
AnnaBridge	171:3a7713b1edbc	1379	#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC1LPEN))
AnnaBridge	171:3a7713b1edbc	1380	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
AnnaBridge	171:3a7713b1edbc	1381	#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI1LPEN))
AnnaBridge	171:3a7713b1edbc	1382	#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SYSCFGLPEN))
AnnaBridge	171:3a7713b1edbc	1383	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
AnnaBridge	171:3a7713b1edbc	1384	#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM9LPEN))
AnnaBridge	171:3a7713b1edbc	1385	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
AnnaBridge	171:3a7713b1edbc	1386	#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM11LPEN))
AnnaBridge	171:3a7713b1edbc	1387	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
AnnaBridge	171:3a7713b1edbc	1388	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
AnnaBridge	171:3a7713b1edbc	1389
AnnaBridge	171:3a7713b1edbc	1390	#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
AnnaBridge	171:3a7713b1edbc	1391	#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
AnnaBridge	171:3a7713b1edbc	1392	#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
AnnaBridge	171:3a7713b1edbc	1393	#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
AnnaBridge	171:3a7713b1edbc	1394	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
AnnaBridge	171:3a7713b1edbc	1395	#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
AnnaBridge	171:3a7713b1edbc	1396	#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
AnnaBridge	171:3a7713b1edbc	1397	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
AnnaBridge	171:3a7713b1edbc	1398	#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
AnnaBridge	171:3a7713b1edbc	1399	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
AnnaBridge	171:3a7713b1edbc	1400	#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
AnnaBridge	171:3a7713b1edbc	1401	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
AnnaBridge	171:3a7713b1edbc	1402	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
AnnaBridge	171:3a7713b1edbc	1403	/**
AnnaBridge	171:3a7713b1edbc	1404	* @}
AnnaBridge	171:3a7713b1edbc	1405	*/
AnnaBridge	171:3a7713b1edbc	1406
AnnaBridge	171:3a7713b1edbc	1407	/** @defgroup RCC_HSI_Configuration HSI Configuration
AnnaBridge	171:3a7713b1edbc	1408	* @{
AnnaBridge	171:3a7713b1edbc	1409	*/
AnnaBridge	171:3a7713b1edbc	1410
AnnaBridge	171:3a7713b1edbc	1411	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
AnnaBridge	171:3a7713b1edbc	1412	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge	171:3a7713b1edbc	1413	* It is used (enabled by hardware) as system clock source after startup
AnnaBridge	171:3a7713b1edbc	1414	* from Reset, wake-up from STOP and STANDBY mode, or in case of failure
AnnaBridge	171:3a7713b1edbc	1415	* of the HSE used directly or indirectly as system clock (if the Clock
AnnaBridge	171:3a7713b1edbc	1416	* Security System CSS is enabled).
AnnaBridge	171:3a7713b1edbc	1417	* @note HSI can not be stopped if it is used as system clock source. In this case,
AnnaBridge	171:3a7713b1edbc	1418	* you have to select another source of the system clock then stop the HSI.
AnnaBridge	171:3a7713b1edbc	1419	* @note After enabling the HSI, the application software should wait on HSIRDY
AnnaBridge	171:3a7713b1edbc	1420	* flag to be set indicating that HSI clock is stable and can be used as
AnnaBridge	171:3a7713b1edbc	1421	* system clock source.
AnnaBridge	171:3a7713b1edbc	1422	* This parameter can be: ENABLE or DISABLE.
AnnaBridge	171:3a7713b1edbc	1423	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
AnnaBridge	171:3a7713b1edbc	1424	* clock cycles.
AnnaBridge	171:3a7713b1edbc	1425	*/
AnnaBridge	171:3a7713b1edbc	1426	#define __HAL_RCC_HSI_ENABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = ENABLE)
AnnaBridge	171:3a7713b1edbc	1427	#define __HAL_RCC_HSI_DISABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = DISABLE)
AnnaBridge	171:3a7713b1edbc	1428
AnnaBridge	171:3a7713b1edbc	1429	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
AnnaBridge	171:3a7713b1edbc	1430	* @note The calibration is used to compensate for the variations in voltage
AnnaBridge	171:3a7713b1edbc	1431	* and temperature that influence the frequency of the internal HSI RC.
AnnaBridge	171:3a7713b1edbc	1432	* @param __HSICalibrationValue__: specifies the calibration trimming value.
AnnaBridge	171:3a7713b1edbc	1433	* (default is RCC_HSICALIBRATION_DEFAULT).
AnnaBridge	171:3a7713b1edbc	1434	* This parameter must be a number between 0 and 0x1F.
AnnaBridge	171:3a7713b1edbc	1435	*/
AnnaBridge	171:3a7713b1edbc	1436	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
AnnaBridge	171:3a7713b1edbc	1437	RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
AnnaBridge	171:3a7713b1edbc	1438	/**
AnnaBridge	171:3a7713b1edbc	1439	* @}
AnnaBridge	171:3a7713b1edbc	1440	*/
AnnaBridge	171:3a7713b1edbc	1441
AnnaBridge	171:3a7713b1edbc	1442	/** @defgroup RCC_LSI_Configuration LSI Configuration
AnnaBridge	171:3a7713b1edbc	1443	* @{
AnnaBridge	171:3a7713b1edbc	1444	*/
AnnaBridge	171:3a7713b1edbc	1445
AnnaBridge	171:3a7713b1edbc	1446	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
AnnaBridge	171:3a7713b1edbc	1447	* @note After enabling the LSI, the application software should wait on
AnnaBridge	171:3a7713b1edbc	1448	* LSIRDY flag to be set indicating that LSI clock is stable and can
AnnaBridge	171:3a7713b1edbc	1449	* be used to clock the IWDG and/or the RTC.
AnnaBridge	171:3a7713b1edbc	1450	* @note LSI can not be disabled if the IWDG is running.
AnnaBridge	171:3a7713b1edbc	1451	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
AnnaBridge	171:3a7713b1edbc	1452	* clock cycles.
AnnaBridge	171:3a7713b1edbc	1453	*/
AnnaBridge	171:3a7713b1edbc	1454	#define __HAL_RCC_LSI_ENABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = ENABLE)
AnnaBridge	171:3a7713b1edbc	1455	#define __HAL_RCC_LSI_DISABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = DISABLE)
AnnaBridge	171:3a7713b1edbc	1456	/**
AnnaBridge	171:3a7713b1edbc	1457	* @}
AnnaBridge	171:3a7713b1edbc	1458	*/
AnnaBridge	171:3a7713b1edbc	1459
AnnaBridge	171:3a7713b1edbc	1460	/** @defgroup RCC_HSE_Configuration HSE Configuration
AnnaBridge	171:3a7713b1edbc	1461	* @{
AnnaBridge	171:3a7713b1edbc	1462	*/
AnnaBridge	171:3a7713b1edbc	1463
AnnaBridge	171:3a7713b1edbc	1464	/**
AnnaBridge	171:3a7713b1edbc	1465	* @brief Macro to configure the External High Speed oscillator (HSE).
AnnaBridge	171:3a7713b1edbc	1466	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
AnnaBridge	171:3a7713b1edbc	1467	* User should request a transition to HSE Off first and then HSE On or HSE Bypass.
AnnaBridge	171:3a7713b1edbc	1468	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
AnnaBridge	171:3a7713b1edbc	1469	* software should wait on HSERDY flag to be set indicating that HSE clock
AnnaBridge	171:3a7713b1edbc	1470	* is stable and can be used to clock the PLL and/or system clock.
AnnaBridge	171:3a7713b1edbc	1471	* @note HSE state can not be changed if it is used directly or through the
AnnaBridge	171:3a7713b1edbc	1472	* PLL as system clock. In this case, you have to select another source
AnnaBridge	171:3a7713b1edbc	1473	* of the system clock then change the HSE state (ex. disable it).
AnnaBridge	171:3a7713b1edbc	1474	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge	171:3a7713b1edbc	1475	* @note This function reset the CSSON bit, so if the clock security system(CSS)
AnnaBridge	171:3a7713b1edbc	1476	* was previously enabled you have to enable it again after calling this
AnnaBridge	171:3a7713b1edbc	1477	* function.
AnnaBridge	171:3a7713b1edbc	1478	* @param __STATE__: specifies the new state of the HSE.
AnnaBridge	171:3a7713b1edbc	1479	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1480	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
AnnaBridge	171:3a7713b1edbc	1481	* 6 HSE oscillator clock cycles.
AnnaBridge	171:3a7713b1edbc	1482	* @arg RCC_HSE_ON: turn ON the HSE oscillator.
AnnaBridge	171:3a7713b1edbc	1483	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
AnnaBridge	171:3a7713b1edbc	1484	*/
AnnaBridge	171:3a7713b1edbc	1485	#define __HAL_RCC_HSE_CONFIG(__STATE__) ((__IO uint8_t ) RCC_CR_BYTE2_ADDRESS = (__STATE__))
AnnaBridge	171:3a7713b1edbc	1486	/**
AnnaBridge	171:3a7713b1edbc	1487	* @}
AnnaBridge	171:3a7713b1edbc	1488	*/
AnnaBridge	171:3a7713b1edbc	1489
AnnaBridge	171:3a7713b1edbc	1490	/** @defgroup RCC_LSE_Configuration LSE Configuration
AnnaBridge	171:3a7713b1edbc	1491	* @{
AnnaBridge	171:3a7713b1edbc	1492	*/
AnnaBridge	171:3a7713b1edbc	1493	/**
AnnaBridge	171:3a7713b1edbc	1494	* @brief Macro to configure the External Low Speed oscillator (LSE).
AnnaBridge	171:3a7713b1edbc	1495	* @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
AnnaBridge	171:3a7713b1edbc	1496	* User should request a transition to LSE Off first and then LSE On or LSE Bypass.
AnnaBridge	171:3a7713b1edbc	1497	* @note As the LSE is in the Backup domain and write access is denied to
AnnaBridge	171:3a7713b1edbc	1498	* this domain after reset, you have to enable write access using
AnnaBridge	171:3a7713b1edbc	1499	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
AnnaBridge	171:3a7713b1edbc	1500	* (to be done once after reset).
AnnaBridge	171:3a7713b1edbc	1501	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
AnnaBridge	171:3a7713b1edbc	1502	* software should wait on LSERDY flag to be set indicating that LSE clock
AnnaBridge	171:3a7713b1edbc	1503	* is stable and can be used to clock the RTC.
AnnaBridge	171:3a7713b1edbc	1504	* @param __STATE__: specifies the new state of the LSE.
AnnaBridge	171:3a7713b1edbc	1505	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1506	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
AnnaBridge	171:3a7713b1edbc	1507	* 6 LSE oscillator clock cycles.
AnnaBridge	171:3a7713b1edbc	1508	* @arg RCC_LSE_ON: turn ON the LSE oscillator.
AnnaBridge	171:3a7713b1edbc	1509	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
AnnaBridge	171:3a7713b1edbc	1510	*/
AnnaBridge	171:3a7713b1edbc	1511	#define __HAL_RCC_LSE_CONFIG(__STATE__) ((__IO uint8_t ) RCC_BDCR_BYTE0_ADDRESS = (__STATE__))
AnnaBridge	171:3a7713b1edbc	1512
AnnaBridge	171:3a7713b1edbc	1513	/**
AnnaBridge	171:3a7713b1edbc	1514	* @}
AnnaBridge	171:3a7713b1edbc	1515	*/
AnnaBridge	171:3a7713b1edbc	1516
AnnaBridge	171:3a7713b1edbc	1517	/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
AnnaBridge	171:3a7713b1edbc	1518	* @{
AnnaBridge	171:3a7713b1edbc	1519	*/
AnnaBridge	171:3a7713b1edbc	1520
AnnaBridge	171:3a7713b1edbc	1521	/** @brief Macros to enable or disable the RTC clock.
AnnaBridge	171:3a7713b1edbc	1522	* @note These macros must be used only after the RTC clock source was selected.
AnnaBridge	171:3a7713b1edbc	1523	*/
AnnaBridge	171:3a7713b1edbc	1524	#define __HAL_RCC_RTC_ENABLE() ((__IO uint32_t ) RCC_BDCR_RTCEN_BB = ENABLE)
AnnaBridge	171:3a7713b1edbc	1525	#define __HAL_RCC_RTC_DISABLE() ((__IO uint32_t ) RCC_BDCR_RTCEN_BB = DISABLE)
AnnaBridge	171:3a7713b1edbc	1526
AnnaBridge	171:3a7713b1edbc	1527	/** @brief Macros to configure the RTC clock (RTCCLK).
AnnaBridge	171:3a7713b1edbc	1528	* @note As the RTC clock configuration bits are in the Backup domain and write
AnnaBridge	171:3a7713b1edbc	1529	* access is denied to this domain after reset, you have to enable write
AnnaBridge	171:3a7713b1edbc	1530	* access using the Power Backup Access macro before to configure
AnnaBridge	171:3a7713b1edbc	1531	* the RTC clock source (to be done once after reset).
AnnaBridge	171:3a7713b1edbc	1532	* @note Once the RTC clock is configured it can't be changed unless the
AnnaBridge	171:3a7713b1edbc	1533	* Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
AnnaBridge	171:3a7713b1edbc	1534	* a Power On Reset (POR).
AnnaBridge	171:3a7713b1edbc	1535	* @param __RTCCLKSource__: specifies the RTC clock source.
AnnaBridge	171:3a7713b1edbc	1536	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1537	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
AnnaBridge	171:3a7713b1edbc	1538	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
AnnaBridge	171:3a7713b1edbc	1539	* @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
AnnaBridge	171:3a7713b1edbc	1540	* as RTC clock, where x:[2,31]
AnnaBridge	171:3a7713b1edbc	1541	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
AnnaBridge	171:3a7713b1edbc	1542	* work in STOP and STANDBY modes, and can be used as wake-up source.
AnnaBridge	171:3a7713b1edbc	1543	* However, when the HSE clock is used as RTC clock source, the RTC
AnnaBridge	171:3a7713b1edbc	1544	* cannot be used in STOP and STANDBY modes.
AnnaBridge	171:3a7713b1edbc	1545	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
AnnaBridge	171:3a7713b1edbc	1546	* RTC clock source).
AnnaBridge	171:3a7713b1edbc	1547	*/
AnnaBridge	171:3a7713b1edbc	1548	#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
AnnaBridge	171:3a7713b1edbc	1549	MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
AnnaBridge	171:3a7713b1edbc	1550
AnnaBridge	171:3a7713b1edbc	1551	#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
AnnaBridge	171:3a7713b1edbc	1552	RCC->BDCR \|= ((__RTCCLKSource__) & 0x00000FFFU); \
AnnaBridge	171:3a7713b1edbc	1553	} while (0)
AnnaBridge	171:3a7713b1edbc	1554
AnnaBridge	171:3a7713b1edbc	1555	/** @brief Macros to force or release the Backup domain reset.
AnnaBridge	171:3a7713b1edbc	1556	* @note This function resets the RTC peripheral (including the backup registers)
AnnaBridge	171:3a7713b1edbc	1557	* and the RTC clock source selection in RCC_CSR register.
AnnaBridge	171:3a7713b1edbc	1558	* @note The BKPSRAM is not affected by this reset.
AnnaBridge	171:3a7713b1edbc	1559	*/
AnnaBridge	171:3a7713b1edbc	1560	#define __HAL_RCC_BACKUPRESET_FORCE() ((__IO uint32_t ) RCC_BDCR_BDRST_BB = ENABLE)
AnnaBridge	171:3a7713b1edbc	1561	#define __HAL_RCC_BACKUPRESET_RELEASE() ((__IO uint32_t ) RCC_BDCR_BDRST_BB = DISABLE)
AnnaBridge	171:3a7713b1edbc	1562	/**
AnnaBridge	171:3a7713b1edbc	1563	* @}
AnnaBridge	171:3a7713b1edbc	1564	*/
AnnaBridge	171:3a7713b1edbc	1565
AnnaBridge	171:3a7713b1edbc	1566	/** @defgroup RCC_PLL_Configuration PLL Configuration
AnnaBridge	171:3a7713b1edbc	1567	* @{
AnnaBridge	171:3a7713b1edbc	1568	*/
AnnaBridge	171:3a7713b1edbc	1569
AnnaBridge	171:3a7713b1edbc	1570	/** @brief Macros to enable or disable the main PLL.
AnnaBridge	171:3a7713b1edbc	1571	* @note After enabling the main PLL, the application software should wait on
AnnaBridge	171:3a7713b1edbc	1572	* PLLRDY flag to be set indicating that PLL clock is stable and can
AnnaBridge	171:3a7713b1edbc	1573	* be used as system clock source.
AnnaBridge	171:3a7713b1edbc	1574	* @note The main PLL can not be disabled if it is used as system clock source
AnnaBridge	171:3a7713b1edbc	1575	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
AnnaBridge	171:3a7713b1edbc	1576	*/
AnnaBridge	171:3a7713b1edbc	1577	#define __HAL_RCC_PLL_ENABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = ENABLE)
AnnaBridge	171:3a7713b1edbc	1578	#define __HAL_RCC_PLL_DISABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = DISABLE)
AnnaBridge	171:3a7713b1edbc	1579
AnnaBridge	171:3a7713b1edbc	1580
AnnaBridge	171:3a7713b1edbc	1581	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
AnnaBridge	171:3a7713b1edbc	1582	* @note This function must be used only when the main PLL is disabled.
AnnaBridge	171:3a7713b1edbc	1583	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
AnnaBridge	171:3a7713b1edbc	1584	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1585	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
AnnaBridge	171:3a7713b1edbc	1586	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
AnnaBridge	171:3a7713b1edbc	1587	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
AnnaBridge	171:3a7713b1edbc	1588	* @param __PLLM__: specifies the division factor for PLL VCO input clock
AnnaBridge	171:3a7713b1edbc	1589	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
AnnaBridge	171:3a7713b1edbc	1590	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
AnnaBridge	171:3a7713b1edbc	1591	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
AnnaBridge	171:3a7713b1edbc	1592	* of 2 MHz to limit PLL jitter.
AnnaBridge	171:3a7713b1edbc	1593	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
AnnaBridge	171:3a7713b1edbc	1594	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
AnnaBridge	171:3a7713b1edbc	1595	* @note You have to set the PLLN parameter correctly to ensure that the VCO
AnnaBridge	171:3a7713b1edbc	1596	* output frequency is between 192 and 432 MHz.
AnnaBridge	171:3a7713b1edbc	1597	*
AnnaBridge	171:3a7713b1edbc	1598	* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
AnnaBridge	171:3a7713b1edbc	1599	* This parameter must be a number in the range {2, 4, 6, or 8}.
AnnaBridge	171:3a7713b1edbc	1600	*
AnnaBridge	171:3a7713b1edbc	1601	* @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
AnnaBridge	171:3a7713b1edbc	1602	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
AnnaBridge	171:3a7713b1edbc	1603	* @note If the USB OTG FS is used in your application, you have to set the
AnnaBridge	171:3a7713b1edbc	1604	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
AnnaBridge	171:3a7713b1edbc	1605	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
AnnaBridge	171:3a7713b1edbc	1606	* correctly.
AnnaBridge	171:3a7713b1edbc	1607	*
AnnaBridge	171:3a7713b1edbc	1608	*/
AnnaBridge	171:3a7713b1edbc	1609	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \
AnnaBridge	171:3a7713b1edbc	1610	(RCC->PLLCFGR = (0x20000000U \| (__RCC_PLLSource__) \| (__PLLM__)\| \
AnnaBridge	171:3a7713b1edbc	1611	((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) \| \
AnnaBridge	171:3a7713b1edbc	1612	((((__PLLP__) >> 1U) -1U) << POSITION_VAL(RCC_PLLCFGR_PLLP)) \| \
AnnaBridge	171:3a7713b1edbc	1613	((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
AnnaBridge	171:3a7713b1edbc	1614	/**
AnnaBridge	171:3a7713b1edbc	1615	* @}
AnnaBridge	171:3a7713b1edbc	1616	*/
AnnaBridge	171:3a7713b1edbc	1617
AnnaBridge	171:3a7713b1edbc	1618	/** @brief Macro to configure the PLL clock source.
AnnaBridge	171:3a7713b1edbc	1619	* @note This function must be used only when the main PLL is disabled.
AnnaBridge	171:3a7713b1edbc	1620	* @param __PLLSOURCE__: specifies the PLL entry clock source.
AnnaBridge	171:3a7713b1edbc	1621	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1622	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
AnnaBridge	171:3a7713b1edbc	1623	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
AnnaBridge	171:3a7713b1edbc	1624	*
AnnaBridge	171:3a7713b1edbc	1625	*/
AnnaBridge	171:3a7713b1edbc	1626	#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
AnnaBridge	171:3a7713b1edbc	1627
AnnaBridge	171:3a7713b1edbc	1628	/** @brief Macro to configure the PLL multiplication factor.
AnnaBridge	171:3a7713b1edbc	1629	* @note This function must be used only when the main PLL is disabled.
AnnaBridge	171:3a7713b1edbc	1630	* @param __PLLM__: specifies the division factor for PLL VCO input clock
AnnaBridge	171:3a7713b1edbc	1631	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
AnnaBridge	171:3a7713b1edbc	1632	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
AnnaBridge	171:3a7713b1edbc	1633	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
AnnaBridge	171:3a7713b1edbc	1634	* of 2 MHz to limit PLL jitter.
AnnaBridge	171:3a7713b1edbc	1635	*
AnnaBridge	171:3a7713b1edbc	1636	*/
AnnaBridge	171:3a7713b1edbc	1637	#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
AnnaBridge	171:3a7713b1edbc	1638
AnnaBridge	171:3a7713b1edbc	1639	/** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration
AnnaBridge	171:3a7713b1edbc	1640	* @{
AnnaBridge	171:3a7713b1edbc	1641	*/
AnnaBridge	171:3a7713b1edbc	1642
AnnaBridge	171:3a7713b1edbc	1643	/** @brief Macros to enable or disable the PLLI2S.
AnnaBridge	171:3a7713b1edbc	1644	* @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
AnnaBridge	171:3a7713b1edbc	1645	*/
AnnaBridge	171:3a7713b1edbc	1646	#define __HAL_RCC_PLLI2S_ENABLE() ((__IO uint32_t ) RCC_CR_PLLI2SON_BB = ENABLE)
AnnaBridge	171:3a7713b1edbc	1647	#define __HAL_RCC_PLLI2S_DISABLE() ((__IO uint32_t ) RCC_CR_PLLI2SON_BB = DISABLE)
AnnaBridge	171:3a7713b1edbc	1648
AnnaBridge	171:3a7713b1edbc	1649	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
AnnaBridge	171:3a7713b1edbc	1650	* @note This macro must be used only when the PLLI2S is disabled.
AnnaBridge	171:3a7713b1edbc	1651	* @note PLLI2S clock source is common with the main PLL (configured in
AnnaBridge	171:3a7713b1edbc	1652	* HAL_RCC_ClockConfig() API).
AnnaBridge	171:3a7713b1edbc	1653	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
AnnaBridge	171:3a7713b1edbc	1654	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
AnnaBridge	171:3a7713b1edbc	1655	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
AnnaBridge	171:3a7713b1edbc	1656	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
AnnaBridge	171:3a7713b1edbc	1657	* @param __PLLI2SR__: specifies the division factor for I2S clock
AnnaBridge	171:3a7713b1edbc	1658	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
AnnaBridge	171:3a7713b1edbc	1659	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
AnnaBridge	171:3a7713b1edbc	1660	* on the I2S clock frequency.
AnnaBridge	171:3a7713b1edbc	1661	*/
AnnaBridge	171:3a7713b1edbc	1662	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \| ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))
AnnaBridge	171:3a7713b1edbc	1663
AnnaBridge	171:3a7713b1edbc	1664	/** @brief Macro to configure the I2S clock source (I2SCLK).
AnnaBridge	171:3a7713b1edbc	1665	* @note This function must be called before enabling the I2S APB clock.
AnnaBridge	171:3a7713b1edbc	1666	* @param __SOURCE__: specifies the I2S clock source.
AnnaBridge	171:3a7713b1edbc	1667	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1668	* @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
AnnaBridge	171:3a7713b1edbc	1669	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
AnnaBridge	171:3a7713b1edbc	1670	* used as I2S clock source.
AnnaBridge	171:3a7713b1edbc	1671	*/
AnnaBridge	171:3a7713b1edbc	1672	#define __HAL_RCC_I2S_CONFIG(__SOURCE__) ((__IO uint32_t ) RCC_CFGR_I2SSRC_BB = (__SOURCE__))
AnnaBridge	171:3a7713b1edbc	1673	/**
AnnaBridge	171:3a7713b1edbc	1674	* @}
AnnaBridge	171:3a7713b1edbc	1675	*/
AnnaBridge	171:3a7713b1edbc	1676
AnnaBridge	171:3a7713b1edbc	1677	/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
AnnaBridge	171:3a7713b1edbc	1678	* @{
AnnaBridge	171:3a7713b1edbc	1679	*/
AnnaBridge	171:3a7713b1edbc	1680
AnnaBridge	171:3a7713b1edbc	1681	/** @brief Macro to configure the MCO1 clock.
AnnaBridge	171:3a7713b1edbc	1682	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
AnnaBridge	171:3a7713b1edbc	1683	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1684	* @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
AnnaBridge	171:3a7713b1edbc	1685	* @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
AnnaBridge	171:3a7713b1edbc	1686	* @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
AnnaBridge	171:3a7713b1edbc	1687	* @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
AnnaBridge	171:3a7713b1edbc	1688	* @param __MCODIV__ specifies the MCO clock prescaler.
AnnaBridge	171:3a7713b1edbc	1689	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1690	* @arg RCC_MCODIV_1: no division applied to MCOx clock
AnnaBridge	171:3a7713b1edbc	1691	* @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
AnnaBridge	171:3a7713b1edbc	1692	* @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
AnnaBridge	171:3a7713b1edbc	1693	* @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
AnnaBridge	171:3a7713b1edbc	1694	* @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
AnnaBridge	171:3a7713b1edbc	1695	*/
AnnaBridge	171:3a7713b1edbc	1696	#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
AnnaBridge	171:3a7713b1edbc	1697	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 \| RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) \| (__MCODIV__)))
AnnaBridge	171:3a7713b1edbc	1698
AnnaBridge	171:3a7713b1edbc	1699	/** @brief Macro to configure the MCO2 clock.
AnnaBridge	171:3a7713b1edbc	1700	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
AnnaBridge	171:3a7713b1edbc	1701	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1702	* @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
AnnaBridge	171:3a7713b1edbc	1703	* @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
AnnaBridge	171:3a7713b1edbc	1704	* @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
AnnaBridge	171:3a7713b1edbc	1705	* @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
AnnaBridge	171:3a7713b1edbc	1706	* @param __MCODIV__ specifies the MCO clock prescaler.
AnnaBridge	171:3a7713b1edbc	1707	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1708	* @arg RCC_MCODIV_1: no division applied to MCOx clock
AnnaBridge	171:3a7713b1edbc	1709	* @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
AnnaBridge	171:3a7713b1edbc	1710	* @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
AnnaBridge	171:3a7713b1edbc	1711	* @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
AnnaBridge	171:3a7713b1edbc	1712	* @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
AnnaBridge	171:3a7713b1edbc	1713	*/
AnnaBridge	171:3a7713b1edbc	1714	#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
AnnaBridge	171:3a7713b1edbc	1715	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 \| RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) \| ((__MCODIV__) << 3U)));
AnnaBridge	171:3a7713b1edbc	1716	/**
AnnaBridge	171:3a7713b1edbc	1717	* @}
AnnaBridge	171:3a7713b1edbc	1718	*/
AnnaBridge	171:3a7713b1edbc	1719
AnnaBridge	171:3a7713b1edbc	1720	/** @defgroup RCC_Get_Clock_source Get Clock source
AnnaBridge	171:3a7713b1edbc	1721	* @{
AnnaBridge	171:3a7713b1edbc	1722	*/
AnnaBridge	171:3a7713b1edbc	1723	/**
AnnaBridge	171:3a7713b1edbc	1724	* @brief Macro to configure the system clock source.
AnnaBridge	171:3a7713b1edbc	1725	* @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
AnnaBridge	171:3a7713b1edbc	1726	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1727	* - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
AnnaBridge	171:3a7713b1edbc	1728	* - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
AnnaBridge	171:3a7713b1edbc	1729	* - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
AnnaBridge	171:3a7713b1edbc	1730	*/
AnnaBridge	171:3a7713b1edbc	1731	#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
AnnaBridge	171:3a7713b1edbc	1732
AnnaBridge	171:3a7713b1edbc	1733	/** @brief Macro to get the clock source used as system clock.
AnnaBridge	171:3a7713b1edbc	1734	* @retval The clock source used as system clock. The returned value can be one
AnnaBridge	171:3a7713b1edbc	1735	* of the following:
AnnaBridge	171:3a7713b1edbc	1736	* - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
AnnaBridge	171:3a7713b1edbc	1737	* - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
AnnaBridge	171:3a7713b1edbc	1738	* - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
AnnaBridge	171:3a7713b1edbc	1739	*/
AnnaBridge	171:3a7713b1edbc	1740	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
AnnaBridge	171:3a7713b1edbc	1741
AnnaBridge	171:3a7713b1edbc	1742	/** @brief Macro to get the oscillator used as PLL clock source.
AnnaBridge	171:3a7713b1edbc	1743	* @retval The oscillator used as PLL clock source. The returned value can be one
AnnaBridge	171:3a7713b1edbc	1744	* of the following:
AnnaBridge	171:3a7713b1edbc	1745	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
AnnaBridge	171:3a7713b1edbc	1746	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
AnnaBridge	171:3a7713b1edbc	1747	*/
AnnaBridge	171:3a7713b1edbc	1748	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
AnnaBridge	171:3a7713b1edbc	1749	/**
AnnaBridge	171:3a7713b1edbc	1750	* @}
AnnaBridge	171:3a7713b1edbc	1751	*/
AnnaBridge	171:3a7713b1edbc	1752
AnnaBridge	171:3a7713b1edbc	1753	/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
AnnaBridge	171:3a7713b1edbc	1754	* @brief macros to manage the specified RCC Flags and interrupts.
AnnaBridge	171:3a7713b1edbc	1755	* @{
AnnaBridge	171:3a7713b1edbc	1756	*/
AnnaBridge	171:3a7713b1edbc	1757
AnnaBridge	171:3a7713b1edbc	1758	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
AnnaBridge	171:3a7713b1edbc	1759	* the selected interrupts).
AnnaBridge	171:3a7713b1edbc	1760	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
AnnaBridge	171:3a7713b1edbc	1761	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	1762	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
AnnaBridge	171:3a7713b1edbc	1763	* @arg RCC_IT_LSERDY: LSE ready interrupt.
AnnaBridge	171:3a7713b1edbc	1764	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
AnnaBridge	171:3a7713b1edbc	1765	* @arg RCC_IT_HSERDY: HSE ready interrupt.
AnnaBridge	171:3a7713b1edbc	1766	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
AnnaBridge	171:3a7713b1edbc	1767	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
AnnaBridge	171:3a7713b1edbc	1768	*/
AnnaBridge	171:3a7713b1edbc	1769	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	1770
AnnaBridge	171:3a7713b1edbc	1771	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
AnnaBridge	171:3a7713b1edbc	1772	* the selected interrupts).
AnnaBridge	171:3a7713b1edbc	1773	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
AnnaBridge	171:3a7713b1edbc	1774	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	1775	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
AnnaBridge	171:3a7713b1edbc	1776	* @arg RCC_IT_LSERDY: LSE ready interrupt.
AnnaBridge	171:3a7713b1edbc	1777	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
AnnaBridge	171:3a7713b1edbc	1778	* @arg RCC_IT_HSERDY: HSE ready interrupt.
AnnaBridge	171:3a7713b1edbc	1779	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
AnnaBridge	171:3a7713b1edbc	1780	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
AnnaBridge	171:3a7713b1edbc	1781	*/
AnnaBridge	171:3a7713b1edbc	1782	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
AnnaBridge	171:3a7713b1edbc	1783
AnnaBridge	171:3a7713b1edbc	1784	/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
AnnaBridge	171:3a7713b1edbc	1785	* bits to clear the selected interrupt pending bits.
AnnaBridge	171:3a7713b1edbc	1786	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
AnnaBridge	171:3a7713b1edbc	1787	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	1788	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
AnnaBridge	171:3a7713b1edbc	1789	* @arg RCC_IT_LSERDY: LSE ready interrupt.
AnnaBridge	171:3a7713b1edbc	1790	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
AnnaBridge	171:3a7713b1edbc	1791	* @arg RCC_IT_HSERDY: HSE ready interrupt.
AnnaBridge	171:3a7713b1edbc	1792	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
AnnaBridge	171:3a7713b1edbc	1793	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
AnnaBridge	171:3a7713b1edbc	1794	* @arg RCC_IT_CSS: Clock Security System interrupt
AnnaBridge	171:3a7713b1edbc	1795	*/
AnnaBridge	171:3a7713b1edbc	1796	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	1797
AnnaBridge	171:3a7713b1edbc	1798	/** @brief Check the RCC's interrupt has occurred or not.
AnnaBridge	171:3a7713b1edbc	1799	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
AnnaBridge	171:3a7713b1edbc	1800	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1801	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
AnnaBridge	171:3a7713b1edbc	1802	* @arg RCC_IT_LSERDY: LSE ready interrupt.
AnnaBridge	171:3a7713b1edbc	1803	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
AnnaBridge	171:3a7713b1edbc	1804	* @arg RCC_IT_HSERDY: HSE ready interrupt.
AnnaBridge	171:3a7713b1edbc	1805	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
AnnaBridge	171:3a7713b1edbc	1806	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
AnnaBridge	171:3a7713b1edbc	1807	* @arg RCC_IT_CSS: Clock Security System interrupt
AnnaBridge	171:3a7713b1edbc	1808	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
AnnaBridge	171:3a7713b1edbc	1809	*/
AnnaBridge	171:3a7713b1edbc	1810	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	1811
AnnaBridge	171:3a7713b1edbc	1812	/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
AnnaBridge	171:3a7713b1edbc	1813	* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
AnnaBridge	171:3a7713b1edbc	1814	*/
AnnaBridge	171:3a7713b1edbc	1815	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
AnnaBridge	171:3a7713b1edbc	1816
AnnaBridge	171:3a7713b1edbc	1817	/** @brief Check RCC flag is set or not.
AnnaBridge	171:3a7713b1edbc	1818	* @param __FLAG__: specifies the flag to check.
AnnaBridge	171:3a7713b1edbc	1819	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1820	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
AnnaBridge	171:3a7713b1edbc	1821	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
AnnaBridge	171:3a7713b1edbc	1822	* @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
AnnaBridge	171:3a7713b1edbc	1823	* @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
AnnaBridge	171:3a7713b1edbc	1824	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
AnnaBridge	171:3a7713b1edbc	1825	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
AnnaBridge	171:3a7713b1edbc	1826	* @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
AnnaBridge	171:3a7713b1edbc	1827	* @arg RCC_FLAG_PINRST: Pin reset.
AnnaBridge	171:3a7713b1edbc	1828	* @arg RCC_FLAG_PORRST: POR/PDR reset.
AnnaBridge	171:3a7713b1edbc	1829	* @arg RCC_FLAG_SFTRST: Software reset.
AnnaBridge	171:3a7713b1edbc	1830	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
AnnaBridge	171:3a7713b1edbc	1831	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
AnnaBridge	171:3a7713b1edbc	1832	* @arg RCC_FLAG_LPWRRST: Low Power reset.
AnnaBridge	171:3a7713b1edbc	1833	* @retval The new state of __FLAG__ (TRUE or FALSE).
AnnaBridge	171:3a7713b1edbc	1834	*/
AnnaBridge	171:3a7713b1edbc	1835	#define RCC_FLAG_MASK ((uint8_t)0x1FU)
AnnaBridge	171:3a7713b1edbc	1836	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
AnnaBridge	171:3a7713b1edbc	1837
AnnaBridge	171:3a7713b1edbc	1838	#define RCC_GET_PLL_OSCSOURCE() ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> POSITION_VAL(RCC_PLLCFGR_PLLSRC))
AnnaBridge	171:3a7713b1edbc	1839	/**
AnnaBridge	171:3a7713b1edbc	1840	* @}
AnnaBridge	171:3a7713b1edbc	1841	*/
AnnaBridge	171:3a7713b1edbc	1842
AnnaBridge	171:3a7713b1edbc	1843	/**
AnnaBridge	171:3a7713b1edbc	1844	* @}
AnnaBridge	171:3a7713b1edbc	1845	*/
AnnaBridge	171:3a7713b1edbc	1846
AnnaBridge	171:3a7713b1edbc	1847	/* Include RCC HAL Extended module */
AnnaBridge	171:3a7713b1edbc	1848	#include "stm32f2xx_hal_rcc_ex.h"
AnnaBridge	171:3a7713b1edbc	1849	/* Exported functions --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	1850	/** @addtogroup RCC_Exported_Functions
AnnaBridge	171:3a7713b1edbc	1851	* @{
AnnaBridge	171:3a7713b1edbc	1852	*/
AnnaBridge	171:3a7713b1edbc	1853
AnnaBridge	171:3a7713b1edbc	1854	/** @addtogroup RCC_Exported_Functions_Group1
AnnaBridge	171:3a7713b1edbc	1855	* @{
AnnaBridge	171:3a7713b1edbc	1856	*/
AnnaBridge	171:3a7713b1edbc	1857	/* Initialization and de-initialization functions ******************************/
AnnaBridge	171:3a7713b1edbc	1858	void HAL_RCC_DeInit(void);
AnnaBridge	171:3a7713b1edbc	1859	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
AnnaBridge	171:3a7713b1edbc	1860	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
AnnaBridge	171:3a7713b1edbc	1861	/**
AnnaBridge	171:3a7713b1edbc	1862	* @}
AnnaBridge	171:3a7713b1edbc	1863	*/
AnnaBridge	171:3a7713b1edbc	1864
AnnaBridge	171:3a7713b1edbc	1865	/** @addtogroup RCC_Exported_Functions_Group2
AnnaBridge	171:3a7713b1edbc	1866	* @{
AnnaBridge	171:3a7713b1edbc	1867	*/
AnnaBridge	171:3a7713b1edbc	1868	/* Peripheral Control functions ************************************************/
AnnaBridge	171:3a7713b1edbc	1869	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
AnnaBridge	171:3a7713b1edbc	1870	void HAL_RCC_EnableCSS(void);
AnnaBridge	171:3a7713b1edbc	1871	void HAL_RCC_DisableCSS(void);
AnnaBridge	171:3a7713b1edbc	1872	uint32_t HAL_RCC_GetSysClockFreq(void);
AnnaBridge	171:3a7713b1edbc	1873	uint32_t HAL_RCC_GetHCLKFreq(void);
AnnaBridge	171:3a7713b1edbc	1874	uint32_t HAL_RCC_GetPCLK1Freq(void);
AnnaBridge	171:3a7713b1edbc	1875	uint32_t HAL_RCC_GetPCLK2Freq(void);
AnnaBridge	171:3a7713b1edbc	1876	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
AnnaBridge	171:3a7713b1edbc	1877	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
AnnaBridge	171:3a7713b1edbc	1878
AnnaBridge	171:3a7713b1edbc	1879	/* CSS NMI IRQ handler */
AnnaBridge	171:3a7713b1edbc	1880	void HAL_RCC_NMI_IRQHandler(void);
AnnaBridge	171:3a7713b1edbc	1881
AnnaBridge	171:3a7713b1edbc	1882	/* User Callbacks in non blocking mode (IT mode) */
AnnaBridge	171:3a7713b1edbc	1883	void HAL_RCC_CSSCallback(void);
AnnaBridge	171:3a7713b1edbc	1884
AnnaBridge	171:3a7713b1edbc	1885	/**
AnnaBridge	171:3a7713b1edbc	1886	* @}
AnnaBridge	171:3a7713b1edbc	1887	*/
AnnaBridge	171:3a7713b1edbc	1888
AnnaBridge	171:3a7713b1edbc	1889	/**
AnnaBridge	171:3a7713b1edbc	1890	* @}
AnnaBridge	171:3a7713b1edbc	1891	*/
AnnaBridge	171:3a7713b1edbc	1892
AnnaBridge	171:3a7713b1edbc	1893	/* Private types -------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	1894	/* Private variables ---------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	1895	/* Private constants ---------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	1896	/** @defgroup RCC_Private_Constants RCC Private Constants
AnnaBridge	171:3a7713b1edbc	1897	* @{
AnnaBridge	171:3a7713b1edbc	1898	*/
AnnaBridge	171:3a7713b1edbc	1899
AnnaBridge	171:3a7713b1edbc	1900	/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
AnnaBridge	171:3a7713b1edbc	1901	* @brief RCC registers bit address in the alias region
AnnaBridge	171:3a7713b1edbc	1902	* @{
AnnaBridge	171:3a7713b1edbc	1903	*/
AnnaBridge	171:3a7713b1edbc	1904	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
AnnaBridge	171:3a7713b1edbc	1905	/* --- CR Register ---*/
AnnaBridge	171:3a7713b1edbc	1906	/* Alias word address of HSION bit */
AnnaBridge	171:3a7713b1edbc	1907	#define RCC_CR_OFFSET (RCC_OFFSET + 0x00U)
AnnaBridge	171:3a7713b1edbc	1908	#define RCC_HSION_BIT_NUMBER 0x00U
AnnaBridge	171:3a7713b1edbc	1909	#define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U))
AnnaBridge	171:3a7713b1edbc	1910	/* Alias word address of CSSON bit */
AnnaBridge	171:3a7713b1edbc	1911	#define RCC_CSSON_BIT_NUMBER 0x13U
AnnaBridge	171:3a7713b1edbc	1912	#define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))
AnnaBridge	171:3a7713b1edbc	1913	/* Alias word address of PLLON bit */
AnnaBridge	171:3a7713b1edbc	1914	#define RCC_PLLON_BIT_NUMBER 0x18U
AnnaBridge	171:3a7713b1edbc	1915	#define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))
AnnaBridge	171:3a7713b1edbc	1916	/* Alias word address of PLLI2SON bit */
AnnaBridge	171:3a7713b1edbc	1917	#define RCC_PLLI2SON_BIT_NUMBER 0x1AU
AnnaBridge	171:3a7713b1edbc	1918	#define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLI2SON_BIT_NUMBER * 4U))
AnnaBridge	171:3a7713b1edbc	1919
AnnaBridge	171:3a7713b1edbc	1920	/* --- CFGR Register ---*/
AnnaBridge	171:3a7713b1edbc	1921	/* Alias word address of I2SSRC bit */
AnnaBridge	171:3a7713b1edbc	1922	#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08U)
AnnaBridge	171:3a7713b1edbc	1923	#define RCC_I2SSRC_BIT_NUMBER 0x17U
AnnaBridge	171:3a7713b1edbc	1924	#define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_I2SSRC_BIT_NUMBER * 4U))
AnnaBridge	171:3a7713b1edbc	1925
AnnaBridge	171:3a7713b1edbc	1926	/* --- BDCR Register ---*/
AnnaBridge	171:3a7713b1edbc	1927	/* Alias word address of RTCEN bit */
AnnaBridge	171:3a7713b1edbc	1928	#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U)
AnnaBridge	171:3a7713b1edbc	1929	#define RCC_RTCEN_BIT_NUMBER 0x0FU
AnnaBridge	171:3a7713b1edbc	1930	#define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))
AnnaBridge	171:3a7713b1edbc	1931	/* Alias word address of BDRST bit */
AnnaBridge	171:3a7713b1edbc	1932	#define RCC_BDRST_BIT_NUMBER 0x10U
AnnaBridge	171:3a7713b1edbc	1933	#define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))
AnnaBridge	171:3a7713b1edbc	1934
AnnaBridge	171:3a7713b1edbc	1935	/* --- CSR Register ---*/
AnnaBridge	171:3a7713b1edbc	1936	/* Alias word address of LSION bit */
AnnaBridge	171:3a7713b1edbc	1937	#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U)
AnnaBridge	171:3a7713b1edbc	1938	#define RCC_LSION_BIT_NUMBER 0x00U
AnnaBridge	171:3a7713b1edbc	1939	#define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))
AnnaBridge	171:3a7713b1edbc	1940
AnnaBridge	171:3a7713b1edbc	1941	/* CR register byte 3 (Bits[23:16]) base address */
AnnaBridge	171:3a7713b1edbc	1942	#define RCC_CR_BYTE2_ADDRESS 0x40023802U
AnnaBridge	171:3a7713b1edbc	1943
AnnaBridge	171:3a7713b1edbc	1944	/* CIR register byte 2 (Bits[15:8]) base address */
AnnaBridge	171:3a7713b1edbc	1945	#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))
AnnaBridge	171:3a7713b1edbc	1946
AnnaBridge	171:3a7713b1edbc	1947	/* CIR register byte 3 (Bits[23:16]) base address */
AnnaBridge	171:3a7713b1edbc	1948	#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))
AnnaBridge	171:3a7713b1edbc	1949
AnnaBridge	171:3a7713b1edbc	1950	/* BDCR register base address */
AnnaBridge	171:3a7713b1edbc	1951	#define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
AnnaBridge	171:3a7713b1edbc	1952
AnnaBridge	171:3a7713b1edbc	1953	#define RCC_DBP_TIMEOUT_VALUE 2U
AnnaBridge	171:3a7713b1edbc	1954	#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
AnnaBridge	171:3a7713b1edbc	1955
AnnaBridge	171:3a7713b1edbc	1956	#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
AnnaBridge	171:3a7713b1edbc	1957	#define HSI_TIMEOUT_VALUE 2U /* 2 ms */
AnnaBridge	171:3a7713b1edbc	1958	#define LSI_TIMEOUT_VALUE 2U /* 2 ms */
AnnaBridge	171:3a7713b1edbc	1959
AnnaBridge	171:3a7713b1edbc	1960	#define PLLI2S_TIMEOUT_VALUE 2U /* Timeout value fixed to 100 ms */
AnnaBridge	171:3a7713b1edbc	1961	/**
AnnaBridge	171:3a7713b1edbc	1962	* @}
AnnaBridge	171:3a7713b1edbc	1963	*/
AnnaBridge	171:3a7713b1edbc	1964
AnnaBridge	171:3a7713b1edbc	1965	/**
AnnaBridge	171:3a7713b1edbc	1966	* @}
AnnaBridge	171:3a7713b1edbc	1967	*/
AnnaBridge	171:3a7713b1edbc	1968
AnnaBridge	171:3a7713b1edbc	1969	/* Private macros ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	1970	/** @defgroup RCC_Private_Macros RCC Private Macros
AnnaBridge	171:3a7713b1edbc	1971	* @{
AnnaBridge	171:3a7713b1edbc	1972	*/
AnnaBridge	171:3a7713b1edbc	1973
AnnaBridge	171:3a7713b1edbc	1974	/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
AnnaBridge	171:3a7713b1edbc	1975	* @{
AnnaBridge	171:3a7713b1edbc	1976	*/
AnnaBridge	171:3a7713b1edbc	1977	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U)
AnnaBridge	171:3a7713b1edbc	1978
AnnaBridge	171:3a7713b1edbc	1979	#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) \|\| ((HSE) == RCC_HSE_ON) \|\| \
AnnaBridge	171:3a7713b1edbc	1980	((HSE) == RCC_HSE_BYPASS))
AnnaBridge	171:3a7713b1edbc	1981
AnnaBridge	171:3a7713b1edbc	1982	#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) \|\| ((LSE) == RCC_LSE_ON) \|\| \
AnnaBridge	171:3a7713b1edbc	1983	((LSE) == RCC_LSE_BYPASS))
AnnaBridge	171:3a7713b1edbc	1984
AnnaBridge	171:3a7713b1edbc	1985	#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) \|\| ((HSI) == RCC_HSI_ON))
AnnaBridge	171:3a7713b1edbc	1986
AnnaBridge	171:3a7713b1edbc	1987	#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) \|\| ((LSI) == RCC_LSI_ON))
AnnaBridge	171:3a7713b1edbc	1988
AnnaBridge	171:3a7713b1edbc	1989	#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) \|\|((PLL) == RCC_PLL_OFF) \|\| ((PLL) == RCC_PLL_ON))
AnnaBridge	171:3a7713b1edbc	1990
AnnaBridge	171:3a7713b1edbc	1991	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
AnnaBridge	171:3a7713b1edbc	1992	((SOURCE) == RCC_PLLSOURCE_HSE))
AnnaBridge	171:3a7713b1edbc	1993
AnnaBridge	171:3a7713b1edbc	1994	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
AnnaBridge	171:3a7713b1edbc	1995	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
AnnaBridge	171:3a7713b1edbc	1996	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
AnnaBridge	171:3a7713b1edbc	1997
AnnaBridge	171:3a7713b1edbc	1998	#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) \|\| \
AnnaBridge	171:3a7713b1edbc	1999	((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) \|\| \
AnnaBridge	171:3a7713b1edbc	2000	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) \|\| \
AnnaBridge	171:3a7713b1edbc	2001	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) \|\| \
AnnaBridge	171:3a7713b1edbc	2002	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) \|\| \
AnnaBridge	171:3a7713b1edbc	2003	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) \|\| \
AnnaBridge	171:3a7713b1edbc	2004	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) \|\| \
AnnaBridge	171:3a7713b1edbc	2005	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) \|\| \
AnnaBridge	171:3a7713b1edbc	2006	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) \|\| \
AnnaBridge	171:3a7713b1edbc	2007	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) \|\| \
AnnaBridge	171:3a7713b1edbc	2008	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) \|\| \
AnnaBridge	171:3a7713b1edbc	2009	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) \|\| \
AnnaBridge	171:3a7713b1edbc	2010	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) \|\| \
AnnaBridge	171:3a7713b1edbc	2011	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) \|\| \
AnnaBridge	171:3a7713b1edbc	2012	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) \|\| \
AnnaBridge	171:3a7713b1edbc	2013	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) \|\| \
AnnaBridge	171:3a7713b1edbc	2014	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) \|\| \
AnnaBridge	171:3a7713b1edbc	2015	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) \|\| \
AnnaBridge	171:3a7713b1edbc	2016	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) \|\| \
AnnaBridge	171:3a7713b1edbc	2017	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) \|\| \
AnnaBridge	171:3a7713b1edbc	2018	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) \|\| \
AnnaBridge	171:3a7713b1edbc	2019	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) \|\| \
AnnaBridge	171:3a7713b1edbc	2020	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) \|\| \
AnnaBridge	171:3a7713b1edbc	2021	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) \|\| \
AnnaBridge	171:3a7713b1edbc	2022	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) \|\| \
AnnaBridge	171:3a7713b1edbc	2023	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) \|\| \
AnnaBridge	171:3a7713b1edbc	2024	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) \|\| \
AnnaBridge	171:3a7713b1edbc	2025	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) \|\| \
AnnaBridge	171:3a7713b1edbc	2026	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) \|\| \
AnnaBridge	171:3a7713b1edbc	2027	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) \|\| \
AnnaBridge	171:3a7713b1edbc	2028	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) \|\| \
AnnaBridge	171:3a7713b1edbc	2029	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31))
AnnaBridge	171:3a7713b1edbc	2030
AnnaBridge	171:3a7713b1edbc	2031	#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U)
AnnaBridge	171:3a7713b1edbc	2032
AnnaBridge	171:3a7713b1edbc	2033	#define IS_RCC_PLLN_VALUE(VALUE) ((192U <= (VALUE)) && ((VALUE) <= 432U))
AnnaBridge	171:3a7713b1edbc	2034
AnnaBridge	171:3a7713b1edbc	2035	#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) \|\| ((VALUE) == 4U) \|\| ((VALUE) == 6U) \|\| ((VALUE) == 8U))
AnnaBridge	171:3a7713b1edbc	2036
AnnaBridge	171:3a7713b1edbc	2037	#define IS_RCC_PLLQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
AnnaBridge	171:3a7713b1edbc	2038
AnnaBridge	171:3a7713b1edbc	2039	#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) \|\| ((HCLK) == RCC_SYSCLK_DIV2) \|\| \
AnnaBridge	171:3a7713b1edbc	2040	((HCLK) == RCC_SYSCLK_DIV4) \|\| ((HCLK) == RCC_SYSCLK_DIV8) \|\| \
AnnaBridge	171:3a7713b1edbc	2041	((HCLK) == RCC_SYSCLK_DIV16) \|\| ((HCLK) == RCC_SYSCLK_DIV64) \|\| \
AnnaBridge	171:3a7713b1edbc	2042	((HCLK) == RCC_SYSCLK_DIV128) \|\| ((HCLK) == RCC_SYSCLK_DIV256) \|\| \
AnnaBridge	171:3a7713b1edbc	2043	((HCLK) == RCC_SYSCLK_DIV512))
AnnaBridge	171:3a7713b1edbc	2044
AnnaBridge	171:3a7713b1edbc	2045	#define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U))
AnnaBridge	171:3a7713b1edbc	2046
AnnaBridge	171:3a7713b1edbc	2047	#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) \|\| ((PCLK) == RCC_HCLK_DIV2) \|\| \
AnnaBridge	171:3a7713b1edbc	2048	((PCLK) == RCC_HCLK_DIV4) \|\| ((PCLK) == RCC_HCLK_DIV8) \|\| \
AnnaBridge	171:3a7713b1edbc	2049	((PCLK) == RCC_HCLK_DIV16))
AnnaBridge	171:3a7713b1edbc	2050
AnnaBridge	171:3a7713b1edbc	2051	#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) \|\| ((MCOx) == RCC_MCO2))
AnnaBridge	171:3a7713b1edbc	2052
AnnaBridge	171:3a7713b1edbc	2053	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) \|\| ((SOURCE) == RCC_MCO1SOURCE_LSE) \|\| \
AnnaBridge	171:3a7713b1edbc	2054	((SOURCE) == RCC_MCO1SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
AnnaBridge	171:3a7713b1edbc	2055
AnnaBridge	171:3a7713b1edbc	2056	#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)\|\| \
AnnaBridge	171:3a7713b1edbc	2057	((SOURCE) == RCC_MCO2SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
AnnaBridge	171:3a7713b1edbc	2058
AnnaBridge	171:3a7713b1edbc	2059	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) \|\| ((DIV) == RCC_MCODIV_2) \|\| \
AnnaBridge	171:3a7713b1edbc	2060	((DIV) == RCC_MCODIV_3) \|\| ((DIV) == RCC_MCODIV_4) \|\| \
AnnaBridge	171:3a7713b1edbc	2061	((DIV) == RCC_MCODIV_5))
AnnaBridge	171:3a7713b1edbc	2062	#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)
AnnaBridge	171:3a7713b1edbc	2063
AnnaBridge	171:3a7713b1edbc	2064	/**
AnnaBridge	171:3a7713b1edbc	2065	* @}
AnnaBridge	171:3a7713b1edbc	2066	*/
AnnaBridge	171:3a7713b1edbc	2067
AnnaBridge	171:3a7713b1edbc	2068	/**
AnnaBridge	171:3a7713b1edbc	2069	* @}
AnnaBridge	171:3a7713b1edbc	2070	*/
AnnaBridge	171:3a7713b1edbc	2071
AnnaBridge	171:3a7713b1edbc	2072	/**
AnnaBridge	171:3a7713b1edbc	2073	* @}
AnnaBridge	171:3a7713b1edbc	2074	*/
AnnaBridge	171:3a7713b1edbc	2075
AnnaBridge	171:3a7713b1edbc	2076	/**
AnnaBridge	171:3a7713b1edbc	2077	* @}
AnnaBridge	171:3a7713b1edbc	2078	*/
AnnaBridge	171:3a7713b1edbc	2079
AnnaBridge	171:3a7713b1edbc	2080	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	2081	}
AnnaBridge	171:3a7713b1edbc	2082	#endif
AnnaBridge	171:3a7713b1edbc	2083
AnnaBridge	171:3a7713b1edbc	2084	#endif /* __STM32F2xx_HAL_RCC_H */
AnnaBridge	171:3a7713b1edbc	2085
AnnaBridge	171:3a7713b1edbc	2086	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/