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TARGET_NUCLEO_F207ZG/TOOLCHAIN_GCC_ARM/stm32f2xx_hal_nand.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file stm32f2xx_hal_nand.h
AnnaBridge 171:3a7713b1edbc 4 * @author MCD Application Team
AnnaBridge 171:3a7713b1edbc 5 * @version V1.2.1
AnnaBridge 171:3a7713b1edbc 6 * @date 14-April-2017
AnnaBridge 171:3a7713b1edbc 7 * @brief Header file of NAND HAL module.
AnnaBridge 171:3a7713b1edbc 8 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 9 * @attention
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 171:3a7713b1edbc 12 *
AnnaBridge 171:3a7713b1edbc 13 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 14 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 18 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 19 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 171:3a7713b1edbc 21 * may be used to endorse or promote products derived from this software
AnnaBridge 171:3a7713b1edbc 22 * without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 23 *
AnnaBridge 171:3a7713b1edbc 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 171:3a7713b1edbc 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 171:3a7713b1edbc 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 171:3a7713b1edbc 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 171:3a7713b1edbc 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 171:3a7713b1edbc 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 171:3a7713b1edbc 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 171:3a7713b1edbc 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 34 *
AnnaBridge 171:3a7713b1edbc 35 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 36 */
AnnaBridge 171:3a7713b1edbc 37
AnnaBridge 171:3a7713b1edbc 38 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 171:3a7713b1edbc 39 #ifndef __STM32F2xx_HAL_NAND_H
AnnaBridge 171:3a7713b1edbc 40 #define __STM32F2xx_HAL_NAND_H
AnnaBridge 171:3a7713b1edbc 41
AnnaBridge 171:3a7713b1edbc 42 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 43 extern "C" {
AnnaBridge 171:3a7713b1edbc 44 #endif
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46 /* Includes ------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 47 #include "stm32f2xx_ll_fsmc.h"
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49
AnnaBridge 171:3a7713b1edbc 50 /** @addtogroup STM32F2xx_HAL_Driver
AnnaBridge 171:3a7713b1edbc 51 * @{
AnnaBridge 171:3a7713b1edbc 52 */
AnnaBridge 171:3a7713b1edbc 53
AnnaBridge 171:3a7713b1edbc 54 /** @addtogroup NAND
AnnaBridge 171:3a7713b1edbc 55 * @{
AnnaBridge 171:3a7713b1edbc 56 */
AnnaBridge 171:3a7713b1edbc 57
AnnaBridge 171:3a7713b1edbc 58 /* Exported typedef ----------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 59 /* Exported types ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 60 /** @defgroup NAND_Exported_Types NAND Exported Types
AnnaBridge 171:3a7713b1edbc 61 * @{
AnnaBridge 171:3a7713b1edbc 62 */
AnnaBridge 171:3a7713b1edbc 63
AnnaBridge 171:3a7713b1edbc 64 /**
AnnaBridge 171:3a7713b1edbc 65 * @brief HAL NAND State structures definition
AnnaBridge 171:3a7713b1edbc 66 */
AnnaBridge 171:3a7713b1edbc 67 typedef enum
AnnaBridge 171:3a7713b1edbc 68 {
AnnaBridge 171:3a7713b1edbc 69 HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */
AnnaBridge 171:3a7713b1edbc 70 HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */
AnnaBridge 171:3a7713b1edbc 71 HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */
AnnaBridge 171:3a7713b1edbc 72 HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */
AnnaBridge 171:3a7713b1edbc 73 }HAL_NAND_StateTypeDef;
AnnaBridge 171:3a7713b1edbc 74
AnnaBridge 171:3a7713b1edbc 75 /**
AnnaBridge 171:3a7713b1edbc 76 * @brief NAND Memory electronic signature Structure definition
AnnaBridge 171:3a7713b1edbc 77 */
AnnaBridge 171:3a7713b1edbc 78 typedef struct
AnnaBridge 171:3a7713b1edbc 79 {
AnnaBridge 171:3a7713b1edbc 80 /*<! NAND memory electronic signature maker and device IDs */
AnnaBridge 171:3a7713b1edbc 81
AnnaBridge 171:3a7713b1edbc 82 uint8_t Maker_Id;
AnnaBridge 171:3a7713b1edbc 83
AnnaBridge 171:3a7713b1edbc 84 uint8_t Device_Id;
AnnaBridge 171:3a7713b1edbc 85
AnnaBridge 171:3a7713b1edbc 86 uint8_t Third_Id;
AnnaBridge 171:3a7713b1edbc 87
AnnaBridge 171:3a7713b1edbc 88 uint8_t Fourth_Id;
AnnaBridge 171:3a7713b1edbc 89 }NAND_IDTypeDef;
AnnaBridge 171:3a7713b1edbc 90
AnnaBridge 171:3a7713b1edbc 91 /**
AnnaBridge 171:3a7713b1edbc 92 * @brief NAND Memory address Structure definition
AnnaBridge 171:3a7713b1edbc 93 */
AnnaBridge 171:3a7713b1edbc 94 typedef struct
AnnaBridge 171:3a7713b1edbc 95 {
AnnaBridge 171:3a7713b1edbc 96 uint16_t Page; /*!< NAND memory Page address */
AnnaBridge 171:3a7713b1edbc 97
AnnaBridge 171:3a7713b1edbc 98 uint16_t Plane; /*!< NAND memory Plane address */
AnnaBridge 171:3a7713b1edbc 99
AnnaBridge 171:3a7713b1edbc 100 uint16_t Block; /*!< NAND memory Block address */
AnnaBridge 171:3a7713b1edbc 101
AnnaBridge 171:3a7713b1edbc 102 }NAND_AddressTypeDef;
AnnaBridge 171:3a7713b1edbc 103
AnnaBridge 171:3a7713b1edbc 104 /**
AnnaBridge 171:3a7713b1edbc 105 * @brief NAND Memory info Structure definition
AnnaBridge 171:3a7713b1edbc 106 */
AnnaBridge 171:3a7713b1edbc 107 typedef struct
AnnaBridge 171:3a7713b1edbc 108 {
AnnaBridge 171:3a7713b1edbc 109 uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes
AnnaBridge 171:3a7713b1edbc 110 for 8 bits adressing or words for 16 bits addressing */
AnnaBridge 171:3a7713b1edbc 111
AnnaBridge 171:3a7713b1edbc 112 uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes
AnnaBridge 171:3a7713b1edbc 113 for 8 bits adressing or words for 16 bits addressing */
AnnaBridge 171:3a7713b1edbc 114
AnnaBridge 171:3a7713b1edbc 115 uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */
AnnaBridge 171:3a7713b1edbc 116
AnnaBridge 171:3a7713b1edbc 117 uint32_t BlockNbr; /*!< NAND memory number of total blocks */
AnnaBridge 171:3a7713b1edbc 118
AnnaBridge 171:3a7713b1edbc 119 uint32_t PlaneNbr; /*!< NAND memory number of planes */
AnnaBridge 171:3a7713b1edbc 120
AnnaBridge 171:3a7713b1edbc 121 uint32_t PlaneSize; /*!< NAND memory zone size measured in number of blocks */
AnnaBridge 171:3a7713b1edbc 122
AnnaBridge 171:3a7713b1edbc 123 FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This
AnnaBridge 171:3a7713b1edbc 124 parameter is mandatory for some NAND parts after the read
AnnaBridge 171:3a7713b1edbc 125 command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
AnnaBridge 171:3a7713b1edbc 126 Example: Toshiba THTH58BYG3S0HBAI6.
AnnaBridge 171:3a7713b1edbc 127 This parameter could be ENABLE or DISABLE
AnnaBridge 171:3a7713b1edbc 128 Please check the Read Mode sequnece in the NAND device datasheet */
AnnaBridge 171:3a7713b1edbc 129 }NAND_DeviceConfigTypeDef;
AnnaBridge 171:3a7713b1edbc 130
AnnaBridge 171:3a7713b1edbc 131 /**
AnnaBridge 171:3a7713b1edbc 132 * @brief NAND handle Structure definition
AnnaBridge 171:3a7713b1edbc 133 */
AnnaBridge 171:3a7713b1edbc 134 typedef struct
AnnaBridge 171:3a7713b1edbc 135 {
AnnaBridge 171:3a7713b1edbc 136 FSMC_NAND_TypeDef *Instance; /*!< Register base address */
AnnaBridge 171:3a7713b1edbc 137
AnnaBridge 171:3a7713b1edbc 138 FSMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
AnnaBridge 171:3a7713b1edbc 139
AnnaBridge 171:3a7713b1edbc 140 HAL_LockTypeDef Lock; /*!< NAND locking object */
AnnaBridge 171:3a7713b1edbc 141
AnnaBridge 171:3a7713b1edbc 142 __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
AnnaBridge 171:3a7713b1edbc 143
AnnaBridge 171:3a7713b1edbc 144 NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */
AnnaBridge 171:3a7713b1edbc 145
AnnaBridge 171:3a7713b1edbc 146 }NAND_HandleTypeDef;
AnnaBridge 171:3a7713b1edbc 147 /**
AnnaBridge 171:3a7713b1edbc 148 * @}
AnnaBridge 171:3a7713b1edbc 149 */
AnnaBridge 171:3a7713b1edbc 150
AnnaBridge 171:3a7713b1edbc 151 /* Exported constants --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 152 /* Exported macros ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 153 /** @defgroup NAND_Exported_Macros NAND Exported Macros
AnnaBridge 171:3a7713b1edbc 154 * @{
AnnaBridge 171:3a7713b1edbc 155 */
AnnaBridge 171:3a7713b1edbc 156
AnnaBridge 171:3a7713b1edbc 157 /** @brief Reset NAND handle state
AnnaBridge 171:3a7713b1edbc 158 * @param __HANDLE__: specifies the NAND handle.
AnnaBridge 171:3a7713b1edbc 159 * @retval None
AnnaBridge 171:3a7713b1edbc 160 */
AnnaBridge 171:3a7713b1edbc 161 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
AnnaBridge 171:3a7713b1edbc 162
AnnaBridge 171:3a7713b1edbc 163 /**
AnnaBridge 171:3a7713b1edbc 164 * @}
AnnaBridge 171:3a7713b1edbc 165 */
AnnaBridge 171:3a7713b1edbc 166
AnnaBridge 171:3a7713b1edbc 167 /* Exported functions --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 168 /** @addtogroup NAND_Exported_Functions NAND Exported Functions
AnnaBridge 171:3a7713b1edbc 169 * @{
AnnaBridge 171:3a7713b1edbc 170 */
AnnaBridge 171:3a7713b1edbc 171
AnnaBridge 171:3a7713b1edbc 172 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
AnnaBridge 171:3a7713b1edbc 173 * @{
AnnaBridge 171:3a7713b1edbc 174 */
AnnaBridge 171:3a7713b1edbc 175
AnnaBridge 171:3a7713b1edbc 176 /* Initialization/de-initialization functions ********************************/
AnnaBridge 171:3a7713b1edbc 177 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
AnnaBridge 171:3a7713b1edbc 178 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
AnnaBridge 171:3a7713b1edbc 179 HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
AnnaBridge 171:3a7713b1edbc 180 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
AnnaBridge 171:3a7713b1edbc 181 void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
AnnaBridge 171:3a7713b1edbc 182 void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
AnnaBridge 171:3a7713b1edbc 183 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
AnnaBridge 171:3a7713b1edbc 184 void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
AnnaBridge 171:3a7713b1edbc 185
AnnaBridge 171:3a7713b1edbc 186 /**
AnnaBridge 171:3a7713b1edbc 187 * @}
AnnaBridge 171:3a7713b1edbc 188 */
AnnaBridge 171:3a7713b1edbc 189
AnnaBridge 171:3a7713b1edbc 190 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
AnnaBridge 171:3a7713b1edbc 191 * @{
AnnaBridge 171:3a7713b1edbc 192 */
AnnaBridge 171:3a7713b1edbc 193
AnnaBridge 171:3a7713b1edbc 194 /* IO operation functions ****************************************************/
AnnaBridge 171:3a7713b1edbc 195 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
AnnaBridge 171:3a7713b1edbc 196
AnnaBridge 171:3a7713b1edbc 197 HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
AnnaBridge 171:3a7713b1edbc 198 HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
AnnaBridge 171:3a7713b1edbc 199 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
AnnaBridge 171:3a7713b1edbc 200 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
AnnaBridge 171:3a7713b1edbc 201
AnnaBridge 171:3a7713b1edbc 202 HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
AnnaBridge 171:3a7713b1edbc 203 HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
AnnaBridge 171:3a7713b1edbc 204 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
AnnaBridge 171:3a7713b1edbc 205 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
AnnaBridge 171:3a7713b1edbc 206
AnnaBridge 171:3a7713b1edbc 207 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
AnnaBridge 171:3a7713b1edbc 208
AnnaBridge 171:3a7713b1edbc 209 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
AnnaBridge 171:3a7713b1edbc 210 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
AnnaBridge 171:3a7713b1edbc 211
AnnaBridge 171:3a7713b1edbc 212 /**
AnnaBridge 171:3a7713b1edbc 213 * @}
AnnaBridge 171:3a7713b1edbc 214 */
AnnaBridge 171:3a7713b1edbc 215
AnnaBridge 171:3a7713b1edbc 216 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
AnnaBridge 171:3a7713b1edbc 217 * @{
AnnaBridge 171:3a7713b1edbc 218 */
AnnaBridge 171:3a7713b1edbc 219
AnnaBridge 171:3a7713b1edbc 220 /* NAND Control functions ****************************************************/
AnnaBridge 171:3a7713b1edbc 221 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
AnnaBridge 171:3a7713b1edbc 222 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
AnnaBridge 171:3a7713b1edbc 223 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
AnnaBridge 171:3a7713b1edbc 224
AnnaBridge 171:3a7713b1edbc 225 /**
AnnaBridge 171:3a7713b1edbc 226 * @}
AnnaBridge 171:3a7713b1edbc 227 */
AnnaBridge 171:3a7713b1edbc 228
AnnaBridge 171:3a7713b1edbc 229 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
AnnaBridge 171:3a7713b1edbc 230 * @{
AnnaBridge 171:3a7713b1edbc 231 */
AnnaBridge 171:3a7713b1edbc 232 /* NAND State functions *******************************************************/
AnnaBridge 171:3a7713b1edbc 233 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
AnnaBridge 171:3a7713b1edbc 234 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
AnnaBridge 171:3a7713b1edbc 235 /**
AnnaBridge 171:3a7713b1edbc 236 * @}
AnnaBridge 171:3a7713b1edbc 237 */
AnnaBridge 171:3a7713b1edbc 238
AnnaBridge 171:3a7713b1edbc 239 /**
AnnaBridge 171:3a7713b1edbc 240 * @}
AnnaBridge 171:3a7713b1edbc 241 */
AnnaBridge 171:3a7713b1edbc 242
AnnaBridge 171:3a7713b1edbc 243 /* Private types -------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 244 /* Private variables ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 245 /* Private constants ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 246 /** @defgroup NAND_Private_Constants NAND Private Constants
AnnaBridge 171:3a7713b1edbc 247 * @{
AnnaBridge 171:3a7713b1edbc 248 */
AnnaBridge 171:3a7713b1edbc 249 #define NAND_DEVICE1 0x70000000U
AnnaBridge 171:3a7713b1edbc 250 #define NAND_DEVICE2 0x80000000U
AnnaBridge 171:3a7713b1edbc 251 #define NAND_WRITE_TIMEOUT 0x01000000U
AnnaBridge 171:3a7713b1edbc 252
AnnaBridge 171:3a7713b1edbc 253 #define CMD_AREA ((uint32_t)(1U<<16U)) /* A16 = CLE high */
AnnaBridge 171:3a7713b1edbc 254 #define ADDR_AREA ((uint32_t)(1U<<17U)) /* A17 = ALE high */
AnnaBridge 171:3a7713b1edbc 255
AnnaBridge 171:3a7713b1edbc 256 #define NAND_CMD_AREA_A ((uint8_t)0x00)
AnnaBridge 171:3a7713b1edbc 257 #define NAND_CMD_AREA_B ((uint8_t)0x01)
AnnaBridge 171:3a7713b1edbc 258 #define NAND_CMD_AREA_C ((uint8_t)0x50)
AnnaBridge 171:3a7713b1edbc 259 #define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
AnnaBridge 171:3a7713b1edbc 260
AnnaBridge 171:3a7713b1edbc 261 #define NAND_CMD_WRITE0 ((uint8_t)0x80)
AnnaBridge 171:3a7713b1edbc 262 #define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
AnnaBridge 171:3a7713b1edbc 263 #define NAND_CMD_ERASE0 ((uint8_t)0x60)
AnnaBridge 171:3a7713b1edbc 264 #define NAND_CMD_ERASE1 ((uint8_t)0xD0)
AnnaBridge 171:3a7713b1edbc 265 #define NAND_CMD_READID ((uint8_t)0x90)
AnnaBridge 171:3a7713b1edbc 266 #define NAND_CMD_STATUS ((uint8_t)0x70)
AnnaBridge 171:3a7713b1edbc 267 #define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
AnnaBridge 171:3a7713b1edbc 268 #define NAND_CMD_RESET ((uint8_t)0xFF)
AnnaBridge 171:3a7713b1edbc 269
AnnaBridge 171:3a7713b1edbc 270 /* NAND memory status */
AnnaBridge 171:3a7713b1edbc 271 #define NAND_VALID_ADDRESS 0x00000100U
AnnaBridge 171:3a7713b1edbc 272 #define NAND_INVALID_ADDRESS 0x00000200U
AnnaBridge 171:3a7713b1edbc 273 #define NAND_TIMEOUT_ERROR 0x00000400U
AnnaBridge 171:3a7713b1edbc 274 #define NAND_BUSY 0x00000000U
AnnaBridge 171:3a7713b1edbc 275 #define NAND_ERROR 0x00000001U
AnnaBridge 171:3a7713b1edbc 276 #define NAND_READY 0x00000040U
AnnaBridge 171:3a7713b1edbc 277 /**
AnnaBridge 171:3a7713b1edbc 278 * @}
AnnaBridge 171:3a7713b1edbc 279 */
AnnaBridge 171:3a7713b1edbc 280
AnnaBridge 171:3a7713b1edbc 281 /* Private macros ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 282 /** @defgroup NAND_Private_Macros NAND Private Macros
AnnaBridge 171:3a7713b1edbc 283 * @{
AnnaBridge 171:3a7713b1edbc 284 */
AnnaBridge 171:3a7713b1edbc 285
AnnaBridge 171:3a7713b1edbc 286 /**
AnnaBridge 171:3a7713b1edbc 287 * @brief NAND memory address computation.
AnnaBridge 171:3a7713b1edbc 288 * @param __ADDRESS__: NAND memory address.
AnnaBridge 171:3a7713b1edbc 289 * @param __HANDLE__ : NAND handle.
AnnaBridge 171:3a7713b1edbc 290 * @retval NAND Raw address value
AnnaBridge 171:3a7713b1edbc 291 */
AnnaBridge 171:3a7713b1edbc 292 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
AnnaBridge 171:3a7713b1edbc 293 (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
AnnaBridge 171:3a7713b1edbc 294
AnnaBridge 171:3a7713b1edbc 295 /**
AnnaBridge 171:3a7713b1edbc 296 * @brief NAND memory Column address computation.
AnnaBridge 171:3a7713b1edbc 297 * @param __HANDLE__: NAND handle.
AnnaBridge 171:3a7713b1edbc 298 * @retval NAND Raw address value
AnnaBridge 171:3a7713b1edbc 299 */
AnnaBridge 171:3a7713b1edbc 300 #define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
AnnaBridge 171:3a7713b1edbc 301
AnnaBridge 171:3a7713b1edbc 302 /**
AnnaBridge 171:3a7713b1edbc 303 * @brief NAND memory address cycling.
AnnaBridge 171:3a7713b1edbc 304 * @param __ADDRESS__: NAND memory address.
AnnaBridge 171:3a7713b1edbc 305 * @retval NAND address cycling value.
AnnaBridge 171:3a7713b1edbc 306 */
AnnaBridge 171:3a7713b1edbc 307 #define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
AnnaBridge 171:3a7713b1edbc 308 #define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8U) /* 2nd addressing cycle */
AnnaBridge 171:3a7713b1edbc 309 #define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16U) /* 3rd addressing cycle */
AnnaBridge 171:3a7713b1edbc 310 #define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24U) /* 4th addressing cycle */
AnnaBridge 171:3a7713b1edbc 311 /**
AnnaBridge 171:3a7713b1edbc 312 * @brief NAND memory Columns cycling.
AnnaBridge 171:3a7713b1edbc 313 * @param __ADDRESS__: NAND memory address.
AnnaBridge 171:3a7713b1edbc 314 * @retval NAND Column address cycling value.
AnnaBridge 171:3a7713b1edbc 315 */
AnnaBridge 171:3a7713b1edbc 316 #define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */
AnnaBridge 171:3a7713b1edbc 317 #define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */
AnnaBridge 171:3a7713b1edbc 318
AnnaBridge 171:3a7713b1edbc 319
AnnaBridge 171:3a7713b1edbc 320 /**
AnnaBridge 171:3a7713b1edbc 321 * @}
AnnaBridge 171:3a7713b1edbc 322 */
AnnaBridge 171:3a7713b1edbc 323 /**
AnnaBridge 171:3a7713b1edbc 324 * @}
AnnaBridge 171:3a7713b1edbc 325 */
AnnaBridge 171:3a7713b1edbc 326
AnnaBridge 171:3a7713b1edbc 327 /**
AnnaBridge 171:3a7713b1edbc 328 * @}
AnnaBridge 171:3a7713b1edbc 329 */
AnnaBridge 171:3a7713b1edbc 330
AnnaBridge 171:3a7713b1edbc 331 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 332 }
AnnaBridge 171:3a7713b1edbc 333 #endif
AnnaBridge 171:3a7713b1edbc 334
AnnaBridge 171:3a7713b1edbc 335 #endif /* __STM32F2xx_HAL_NAND_H */
AnnaBridge 171:3a7713b1edbc 336
AnnaBridge 171:3a7713b1edbc 337 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/