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TARGET_NUCLEO_F207ZG/TOOLCHAIN_ARM_MICRO/stm32f2xx_ll_dma.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	145:64910690c574	1	/**
AnnaBridge	145:64910690c574	2	******************************************************************************
AnnaBridge	145:64910690c574	3	* @file stm32f2xx_ll_dma.h
AnnaBridge	145:64910690c574	4	* @author MCD Application Team
AnnaBridge	145:64910690c574	5	* @version V1.2.1
AnnaBridge	145:64910690c574	6	* @date 14-April-2017
AnnaBridge	145:64910690c574	7	* @brief Header file of DMA LL module.
AnnaBridge	145:64910690c574	8	******************************************************************************
AnnaBridge	145:64910690c574	9	* @attention
AnnaBridge	145:64910690c574	10	*
AnnaBridge	145:64910690c574	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	145:64910690c574	12	*
AnnaBridge	145:64910690c574	13	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	145:64910690c574	14	* are permitted provided that the following conditions are met:
AnnaBridge	145:64910690c574	15	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	145:64910690c574	16	* this list of conditions and the following disclaimer.
AnnaBridge	145:64910690c574	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	145:64910690c574	18	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	145:64910690c574	19	* and/or other materials provided with the distribution.
AnnaBridge	145:64910690c574	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	145:64910690c574	21	* may be used to endorse or promote products derived from this software
AnnaBridge	145:64910690c574	22	* without specific prior written permission.
AnnaBridge	145:64910690c574	23	*
AnnaBridge	145:64910690c574	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	145:64910690c574	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	145:64910690c574	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	145:64910690c574	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	145:64910690c574	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	145:64910690c574	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	145:64910690c574	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	145:64910690c574	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	145:64910690c574	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	145:64910690c574	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	145:64910690c574	34	*
AnnaBridge	145:64910690c574	35	******************************************************************************
AnnaBridge	145:64910690c574	36	*/
AnnaBridge	145:64910690c574	37
AnnaBridge	145:64910690c574	38	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	145:64910690c574	39	#ifndef __STM32F2xx_LL_DMA_H
AnnaBridge	145:64910690c574	40	#define __STM32F2xx_LL_DMA_H
AnnaBridge	145:64910690c574	41
AnnaBridge	145:64910690c574	42	#ifdef __cplusplus
AnnaBridge	145:64910690c574	43	extern "C" {
AnnaBridge	145:64910690c574	44	#endif
AnnaBridge	145:64910690c574	45
AnnaBridge	145:64910690c574	46	/* Includes ------------------------------------------------------------------*/
AnnaBridge	145:64910690c574	47	#include "stm32f2xx.h"
AnnaBridge	145:64910690c574	48
AnnaBridge	145:64910690c574	49	/** @addtogroup STM32F2xx_LL_Driver
AnnaBridge	145:64910690c574	50	* @{
AnnaBridge	145:64910690c574	51	*/
AnnaBridge	145:64910690c574	52
AnnaBridge	145:64910690c574	53	#if defined (DMA1) \|\| defined (DMA2)
AnnaBridge	145:64910690c574	54
AnnaBridge	145:64910690c574	55	/** @defgroup DMA_LL DMA
AnnaBridge	145:64910690c574	56	* @{
AnnaBridge	145:64910690c574	57	*/
AnnaBridge	145:64910690c574	58
AnnaBridge	145:64910690c574	59	/* Private types -------------------------------------------------------------*/
AnnaBridge	145:64910690c574	60	/* Private variables ---------------------------------------------------------*/
AnnaBridge	145:64910690c574	61	/** @defgroup DMA_LL_Private_Variables DMA Private Variables
AnnaBridge	145:64910690c574	62	* @{
AnnaBridge	145:64910690c574	63	*/
AnnaBridge	145:64910690c574	64	/* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */
AnnaBridge	145:64910690c574	65	static const uint8_t STREAM_OFFSET_TAB[] =
AnnaBridge	145:64910690c574	66	{
AnnaBridge	145:64910690c574	67	(uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
AnnaBridge	145:64910690c574	68	(uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),
AnnaBridge	145:64910690c574	69	(uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),
AnnaBridge	145:64910690c574	70	(uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),
AnnaBridge	145:64910690c574	71	(uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),
AnnaBridge	145:64910690c574	72	(uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),
AnnaBridge	145:64910690c574	73	(uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),
AnnaBridge	145:64910690c574	74	(uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
AnnaBridge	145:64910690c574	75	};
AnnaBridge	145:64910690c574	76
AnnaBridge	145:64910690c574	77	/**
AnnaBridge	145:64910690c574	78	* @}
AnnaBridge	145:64910690c574	79	*/
AnnaBridge	145:64910690c574	80
AnnaBridge	145:64910690c574	81	/* Private constants ---------------------------------------------------------*/
AnnaBridge	145:64910690c574	82	/** @defgroup DMA_LL_Private_Constants DMA Private Constants
AnnaBridge	145:64910690c574	83	* @{
AnnaBridge	145:64910690c574	84	*/
AnnaBridge	145:64910690c574	85	/**
AnnaBridge	145:64910690c574	86	* @}
AnnaBridge	145:64910690c574	87	*/
AnnaBridge	145:64910690c574	88
AnnaBridge	145:64910690c574	89
AnnaBridge	145:64910690c574	90	/* Private macros ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	91	/* Exported types ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	92	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	145:64910690c574	93	/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
AnnaBridge	145:64910690c574	94	* @{
AnnaBridge	145:64910690c574	95	*/
AnnaBridge	145:64910690c574	96	typedef struct
AnnaBridge	145:64910690c574	97	{
AnnaBridge	145:64910690c574	98	uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
AnnaBridge	145:64910690c574	99	or as Source base address in case of memory to memory transfer direction.
AnnaBridge	145:64910690c574	100
AnnaBridge	145:64910690c574	101	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
AnnaBridge	145:64910690c574	102
AnnaBridge	145:64910690c574	103	uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
AnnaBridge	145:64910690c574	104	or as Destination base address in case of memory to memory transfer direction.
AnnaBridge	145:64910690c574	105
AnnaBridge	145:64910690c574	106	This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
AnnaBridge	145:64910690c574	107
AnnaBridge	145:64910690c574	108	uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
AnnaBridge	145:64910690c574	109	from memory to memory or from peripheral to memory.
AnnaBridge	145:64910690c574	110	This parameter can be a value of @ref DMA_LL_EC_DIRECTION
AnnaBridge	145:64910690c574	111
AnnaBridge	145:64910690c574	112	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
AnnaBridge	145:64910690c574	113
AnnaBridge	145:64910690c574	114	uint32_t Mode; /*!< Specifies the normal or circular operation mode.
AnnaBridge	145:64910690c574	115	This parameter can be a value of @ref DMA_LL_EC_MODE
AnnaBridge	145:64910690c574	116	@note The circular buffer mode cannot be used if the memory to memory
AnnaBridge	145:64910690c574	117	data transfer direction is configured on the selected Stream
AnnaBridge	145:64910690c574	118
AnnaBridge	145:64910690c574	119	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
AnnaBridge	145:64910690c574	120
AnnaBridge	145:64910690c574	121	uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
AnnaBridge	145:64910690c574	122	is incremented or not.
AnnaBridge	145:64910690c574	123	This parameter can be a value of @ref DMA_LL_EC_PERIPH
AnnaBridge	145:64910690c574	124
AnnaBridge	145:64910690c574	125	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
AnnaBridge	145:64910690c574	126
AnnaBridge	145:64910690c574	127	uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
AnnaBridge	145:64910690c574	128	is incremented or not.
AnnaBridge	145:64910690c574	129	This parameter can be a value of @ref DMA_LL_EC_MEMORY
AnnaBridge	145:64910690c574	130
AnnaBridge	145:64910690c574	131	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
AnnaBridge	145:64910690c574	132
AnnaBridge	145:64910690c574	133	uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
AnnaBridge	145:64910690c574	134	in case of memory to memory transfer direction.
AnnaBridge	145:64910690c574	135	This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
AnnaBridge	145:64910690c574	136
AnnaBridge	145:64910690c574	137	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
AnnaBridge	145:64910690c574	138
AnnaBridge	145:64910690c574	139	uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
AnnaBridge	145:64910690c574	140	in case of memory to memory transfer direction.
AnnaBridge	145:64910690c574	141	This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
AnnaBridge	145:64910690c574	142
AnnaBridge	145:64910690c574	143	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
AnnaBridge	145:64910690c574	144
AnnaBridge	145:64910690c574	145	uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
AnnaBridge	145:64910690c574	146	The data unit is equal to the source buffer configuration set in PeripheralSize
AnnaBridge	145:64910690c574	147	or MemorySize parameters depending in the transfer direction.
AnnaBridge	145:64910690c574	148	This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
AnnaBridge	145:64910690c574	149
AnnaBridge	145:64910690c574	150	This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
AnnaBridge	145:64910690c574	151
AnnaBridge	145:64910690c574	152	uint32_t Channel; /*!< Specifies the peripheral channel.
AnnaBridge	145:64910690c574	153	This parameter can be a value of @ref DMA_LL_EC_CHANNEL
AnnaBridge	145:64910690c574	154
AnnaBridge	145:64910690c574	155	This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelSelection(). */
AnnaBridge	145:64910690c574	156
AnnaBridge	145:64910690c574	157	uint32_t Priority; /*!< Specifies the channel priority level.
AnnaBridge	145:64910690c574	158	This parameter can be a value of @ref DMA_LL_EC_PRIORITY
AnnaBridge	145:64910690c574	159
AnnaBridge	145:64910690c574	160	This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
AnnaBridge	145:64910690c574	161
AnnaBridge	145:64910690c574	162	uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
AnnaBridge	145:64910690c574	163	This parameter can be a value of @ref DMA_LL_FIFOMODE
AnnaBridge	145:64910690c574	164	@note The Direct mode (FIFO mode disabled) cannot be used if the
AnnaBridge	145:64910690c574	165	memory-to-memory data transfer is configured on the selected stream
AnnaBridge	145:64910690c574	166
AnnaBridge	145:64910690c574	167	This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
AnnaBridge	145:64910690c574	168
AnnaBridge	145:64910690c574	169	uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
AnnaBridge	145:64910690c574	170	This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
AnnaBridge	145:64910690c574	171
AnnaBridge	145:64910690c574	172	This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
AnnaBridge	145:64910690c574	173
AnnaBridge	145:64910690c574	174	uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
AnnaBridge	145:64910690c574	175	It specifies the amount of data to be transferred in a single non interruptible
AnnaBridge	145:64910690c574	176	transaction.
AnnaBridge	145:64910690c574	177	This parameter can be a value of @ref DMA_LL_EC_MBURST
AnnaBridge	145:64910690c574	178	@note The burst mode is possible only if the address Increment mode is enabled.
AnnaBridge	145:64910690c574	179
AnnaBridge	145:64910690c574	180	This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
AnnaBridge	145:64910690c574	181
AnnaBridge	145:64910690c574	182	uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
AnnaBridge	145:64910690c574	183	It specifies the amount of data to be transferred in a single non interruptible
AnnaBridge	145:64910690c574	184	transaction.
AnnaBridge	145:64910690c574	185	This parameter can be a value of @ref DMA_LL_EC_PBURST
AnnaBridge	145:64910690c574	186	@note The burst mode is possible only if the address Increment mode is enabled.
AnnaBridge	145:64910690c574	187
AnnaBridge	145:64910690c574	188	This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
AnnaBridge	145:64910690c574	189
AnnaBridge	145:64910690c574	190	} LL_DMA_InitTypeDef;
AnnaBridge	145:64910690c574	191	/**
AnnaBridge	145:64910690c574	192	* @}
AnnaBridge	145:64910690c574	193	*/
AnnaBridge	145:64910690c574	194	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	145:64910690c574	195	/* Exported constants --------------------------------------------------------*/
AnnaBridge	145:64910690c574	196	/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
AnnaBridge	145:64910690c574	197	* @{
AnnaBridge	145:64910690c574	198	*/
AnnaBridge	145:64910690c574	199
AnnaBridge	145:64910690c574	200	/** @defgroup DMA_LL_EC_STREAM STREAM
AnnaBridge	145:64910690c574	201	* @{
AnnaBridge	145:64910690c574	202	*/
AnnaBridge	145:64910690c574	203	#define LL_DMA_STREAM_0 0x00000000U
AnnaBridge	145:64910690c574	204	#define LL_DMA_STREAM_1 0x00000001U
AnnaBridge	145:64910690c574	205	#define LL_DMA_STREAM_2 0x00000002U
AnnaBridge	145:64910690c574	206	#define LL_DMA_STREAM_3 0x00000003U
AnnaBridge	145:64910690c574	207	#define LL_DMA_STREAM_4 0x00000004U
AnnaBridge	145:64910690c574	208	#define LL_DMA_STREAM_5 0x00000005U
AnnaBridge	145:64910690c574	209	#define LL_DMA_STREAM_6 0x00000006U
AnnaBridge	145:64910690c574	210	#define LL_DMA_STREAM_7 0x00000007U
AnnaBridge	145:64910690c574	211	#define LL_DMA_STREAM_ALL 0xFFFF0000U
AnnaBridge	145:64910690c574	212	/**
AnnaBridge	145:64910690c574	213	* @}
AnnaBridge	145:64910690c574	214	*/
AnnaBridge	145:64910690c574	215
AnnaBridge	145:64910690c574	216	/** @defgroup DMA_LL_EC_DIRECTION DIRECTION
AnnaBridge	145:64910690c574	217	* @{
AnnaBridge	145:64910690c574	218	*/
AnnaBridge	145:64910690c574	219	#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /!< Peripheral to memory direction /
AnnaBridge	145:64910690c574	220	#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /!< Memory to peripheral direction /
AnnaBridge	145:64910690c574	221	#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /!< Memory to memory direction /
AnnaBridge	145:64910690c574	222	/**
AnnaBridge	145:64910690c574	223	* @}
AnnaBridge	145:64910690c574	224	*/
AnnaBridge	145:64910690c574	225
AnnaBridge	145:64910690c574	226	/** @defgroup DMA_LL_EC_MODE MODE
AnnaBridge	145:64910690c574	227	* @{
AnnaBridge	145:64910690c574	228	*/
AnnaBridge	145:64910690c574	229	#define LL_DMA_MODE_NORMAL 0x00000000U /!< Normal Mode /
AnnaBridge	145:64910690c574	230	#define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /!< Circular Mode /
AnnaBridge	145:64910690c574	231	#define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /!< Peripheral flow control mode /
AnnaBridge	145:64910690c574	232	/**
AnnaBridge	145:64910690c574	233	* @}
AnnaBridge	145:64910690c574	234	*/
AnnaBridge	145:64910690c574	235
AnnaBridge	145:64910690c574	236	/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE
AnnaBridge	145:64910690c574	237	* @{
AnnaBridge	145:64910690c574	238	*/
AnnaBridge	145:64910690c574	239	#define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /!< Disable double buffering mode /
AnnaBridge	145:64910690c574	240	#define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /!< Enable double buffering mode /
AnnaBridge	145:64910690c574	241	/**
AnnaBridge	145:64910690c574	242	* @}
AnnaBridge	145:64910690c574	243	*/
AnnaBridge	145:64910690c574	244
AnnaBridge	145:64910690c574	245	/** @defgroup DMA_LL_EC_PERIPH PERIPH
AnnaBridge	145:64910690c574	246	* @{
AnnaBridge	145:64910690c574	247	*/
AnnaBridge	145:64910690c574	248	#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /!< Peripheral increment mode Disable /
AnnaBridge	145:64910690c574	249	#define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /!< Peripheral increment mode Enable /
AnnaBridge	145:64910690c574	250	/**
AnnaBridge	145:64910690c574	251	* @}
AnnaBridge	145:64910690c574	252	*/
AnnaBridge	145:64910690c574	253
AnnaBridge	145:64910690c574	254	/** @defgroup DMA_LL_EC_MEMORY MEMORY
AnnaBridge	145:64910690c574	255	* @{
AnnaBridge	145:64910690c574	256	*/
AnnaBridge	145:64910690c574	257	#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /!< Memory increment mode Disable /
AnnaBridge	145:64910690c574	258	#define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /!< Memory increment mode Enable /
AnnaBridge	145:64910690c574	259	/**
AnnaBridge	145:64910690c574	260	* @}
AnnaBridge	145:64910690c574	261	*/
AnnaBridge	145:64910690c574	262
AnnaBridge	145:64910690c574	263	/** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN
AnnaBridge	145:64910690c574	264	* @{
AnnaBridge	145:64910690c574	265	*/
AnnaBridge	145:64910690c574	266	#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /!< Peripheral data alignment : Byte /
AnnaBridge	145:64910690c574	267	#define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /!< Peripheral data alignment : HalfWord /
AnnaBridge	145:64910690c574	268	#define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /!< Peripheral data alignment : Word /
AnnaBridge	145:64910690c574	269	/**
AnnaBridge	145:64910690c574	270	* @}
AnnaBridge	145:64910690c574	271	*/
AnnaBridge	145:64910690c574	272
AnnaBridge	145:64910690c574	273	/** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN
AnnaBridge	145:64910690c574	274	* @{
AnnaBridge	145:64910690c574	275	*/
AnnaBridge	145:64910690c574	276	#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /!< Memory data alignment : Byte /
AnnaBridge	145:64910690c574	277	#define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /!< Memory data alignment : HalfWord /
AnnaBridge	145:64910690c574	278	#define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /!< Memory data alignment : Word /
AnnaBridge	145:64910690c574	279	/**
AnnaBridge	145:64910690c574	280	* @}
AnnaBridge	145:64910690c574	281	*/
AnnaBridge	145:64910690c574	282
AnnaBridge	145:64910690c574	283	/** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE
AnnaBridge	145:64910690c574	284	* @{
AnnaBridge	145:64910690c574	285	*/
AnnaBridge	145:64910690c574	286	#define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /!< Peripheral increment offset size is linked to the PSIZE /
AnnaBridge	145:64910690c574	287	#define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /!< Peripheral increment offset size is fixed to 4 (32-bit alignment) /
AnnaBridge	145:64910690c574	288	/**
AnnaBridge	145:64910690c574	289	* @}
AnnaBridge	145:64910690c574	290	*/
AnnaBridge	145:64910690c574	291
AnnaBridge	145:64910690c574	292	/** @defgroup DMA_LL_EC_PRIORITY PRIORITY
AnnaBridge	145:64910690c574	293	* @{
AnnaBridge	145:64910690c574	294	*/
AnnaBridge	145:64910690c574	295	#define LL_DMA_PRIORITY_LOW 0x00000000U /!< Priority level : Low /
AnnaBridge	145:64910690c574	296	#define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /!< Priority level : Medium /
AnnaBridge	145:64910690c574	297	#define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /!< Priority level : High /
AnnaBridge	145:64910690c574	298	#define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /!< Priority level : Very_High /
AnnaBridge	145:64910690c574	299	/**
AnnaBridge	145:64910690c574	300	* @}
AnnaBridge	145:64910690c574	301	*/
AnnaBridge	145:64910690c574	302
AnnaBridge	145:64910690c574	303	/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
AnnaBridge	145:64910690c574	304	* @{
AnnaBridge	145:64910690c574	305	*/
AnnaBridge	145:64910690c574	306	#define LL_DMA_CHANNEL_0 0x00000000U /* Select Channel0 of DMA Instance */
AnnaBridge	145:64910690c574	307	#define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 /* Select Channel1 of DMA Instance */
AnnaBridge	145:64910690c574	308	#define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 /* Select Channel2 of DMA Instance */
AnnaBridge	145:64910690c574	309	#define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 \| DMA_SxCR_CHSEL_1) /* Select Channel3 of DMA Instance */
AnnaBridge	145:64910690c574	310	#define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 /* Select Channel4 of DMA Instance */
AnnaBridge	145:64910690c574	311	#define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 \| DMA_SxCR_CHSEL_0) /* Select Channel5 of DMA Instance */
AnnaBridge	145:64910690c574	312	#define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 \| DMA_SxCR_CHSEL_1) /* Select Channel6 of DMA Instance */
AnnaBridge	145:64910690c574	313	#define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 \| DMA_SxCR_CHSEL_1 \| DMA_SxCR_CHSEL_0) /* Select Channel7 of DMA Instance */
AnnaBridge	145:64910690c574	314	/**
AnnaBridge	145:64910690c574	315	* @}
AnnaBridge	145:64910690c574	316	*/
AnnaBridge	145:64910690c574	317
AnnaBridge	145:64910690c574	318	/** @defgroup DMA_LL_EC_MBURST MBURST
AnnaBridge	145:64910690c574	319	* @{
AnnaBridge	145:64910690c574	320	*/
AnnaBridge	145:64910690c574	321	#define LL_DMA_MBURST_SINGLE 0x00000000U /!< Memory burst single transfer configuration /
AnnaBridge	145:64910690c574	322	#define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /!< Memory burst of 4 beats transfer configuration /
AnnaBridge	145:64910690c574	323	#define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /!< Memory burst of 8 beats transfer configuration /
AnnaBridge	145:64910690c574	324	#define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 \| DMA_SxCR_MBURST_1) /!< Memory burst of 16 beats transfer configuration /
AnnaBridge	145:64910690c574	325	/**
AnnaBridge	145:64910690c574	326	* @}
AnnaBridge	145:64910690c574	327	*/
AnnaBridge	145:64910690c574	328
AnnaBridge	145:64910690c574	329	/** @defgroup DMA_LL_EC_PBURST PBURST
AnnaBridge	145:64910690c574	330	* @{
AnnaBridge	145:64910690c574	331	*/
AnnaBridge	145:64910690c574	332	#define LL_DMA_PBURST_SINGLE 0x00000000U /!< Peripheral burst single transfer configuration /
AnnaBridge	145:64910690c574	333	#define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /!< Peripheral burst of 4 beats transfer configuration /
AnnaBridge	145:64910690c574	334	#define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /!< Peripheral burst of 8 beats transfer configuration /
AnnaBridge	145:64910690c574	335	#define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 \| DMA_SxCR_PBURST_1) /!< Peripheral burst of 16 beats transfer configuration /
AnnaBridge	145:64910690c574	336	/**
AnnaBridge	145:64910690c574	337	* @}
AnnaBridge	145:64910690c574	338	*/
AnnaBridge	145:64910690c574	339
AnnaBridge	145:64910690c574	340	/** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE
AnnaBridge	145:64910690c574	341	* @{
AnnaBridge	145:64910690c574	342	*/
AnnaBridge	145:64910690c574	343	#define LL_DMA_FIFOMODE_DISABLE 0x00000000U /!< FIFO mode disable (direct mode is enabled) /
AnnaBridge	145:64910690c574	344	#define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /!< FIFO mode enable /
AnnaBridge	145:64910690c574	345	/**
AnnaBridge	145:64910690c574	346	* @}
AnnaBridge	145:64910690c574	347	*/
AnnaBridge	145:64910690c574	348
AnnaBridge	145:64910690c574	349	/** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0
AnnaBridge	145:64910690c574	350	* @{
AnnaBridge	145:64910690c574	351	*/
AnnaBridge	145:64910690c574	352	#define LL_DMA_FIFOSTATUS_0_25 0x00000000U /!< 0 < fifo_level < 1/4 /
AnnaBridge	145:64910690c574	353	#define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /!< 1/4 < fifo_level < 1/2 /
AnnaBridge	145:64910690c574	354	#define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /!< 1/2 < fifo_level < 3/4 /
AnnaBridge	145:64910690c574	355	#define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 \| DMA_SxFCR_FS_0) /!< 3/4 < fifo_level < full /
AnnaBridge	145:64910690c574	356	#define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /!< FIFO is empty /
AnnaBridge	145:64910690c574	357	#define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 \| DMA_SxFCR_FS_0) /!< FIFO is full /
AnnaBridge	145:64910690c574	358	/**
AnnaBridge	145:64910690c574	359	* @}
AnnaBridge	145:64910690c574	360	*/
AnnaBridge	145:64910690c574	361
AnnaBridge	145:64910690c574	362	/** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD
AnnaBridge	145:64910690c574	363	* @{
AnnaBridge	145:64910690c574	364	*/
AnnaBridge	145:64910690c574	365	#define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /!< FIFO threshold 1 quart full configuration /
AnnaBridge	145:64910690c574	366	#define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /!< FIFO threshold half full configuration /
AnnaBridge	145:64910690c574	367	#define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /!< FIFO threshold 3 quarts full configuration /
AnnaBridge	145:64910690c574	368	#define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /!< FIFO threshold full configuration /
AnnaBridge	145:64910690c574	369	/**
AnnaBridge	145:64910690c574	370	* @}
AnnaBridge	145:64910690c574	371	*/
AnnaBridge	145:64910690c574	372
AnnaBridge	145:64910690c574	373	/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
AnnaBridge	145:64910690c574	374	* @{
AnnaBridge	145:64910690c574	375	*/
AnnaBridge	145:64910690c574	376	#define LL_DMA_CURRENTTARGETMEM0 0x00000000U /!< Set CurrentTarget Memory to Memory 0 /
AnnaBridge	145:64910690c574	377	#define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /!< Set CurrentTarget Memory to Memory 1 /
AnnaBridge	145:64910690c574	378	/**
AnnaBridge	145:64910690c574	379	* @}
AnnaBridge	145:64910690c574	380	*/
AnnaBridge	145:64910690c574	381
AnnaBridge	145:64910690c574	382	/**
AnnaBridge	145:64910690c574	383	* @}
AnnaBridge	145:64910690c574	384	*/
AnnaBridge	145:64910690c574	385
AnnaBridge	145:64910690c574	386	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	387	/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
AnnaBridge	145:64910690c574	388	* @{
AnnaBridge	145:64910690c574	389	*/
AnnaBridge	145:64910690c574	390
AnnaBridge	145:64910690c574	391	/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
AnnaBridge	145:64910690c574	392	* @{
AnnaBridge	145:64910690c574	393	*/
AnnaBridge	145:64910690c574	394	/**
AnnaBridge	145:64910690c574	395	* @brief Write a value in DMA register
AnnaBridge	145:64910690c574	396	* @param __INSTANCE__ DMA Instance
AnnaBridge	145:64910690c574	397	* @param __REG__ Register to be written
AnnaBridge	145:64910690c574	398	* @param __VALUE__ Value to be written in the register
AnnaBridge	145:64910690c574	399	* @retval None
AnnaBridge	145:64910690c574	400	*/
AnnaBridge	145:64910690c574	401	#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	145:64910690c574	402
AnnaBridge	145:64910690c574	403	/**
AnnaBridge	145:64910690c574	404	* @brief Read a value in DMA register
AnnaBridge	145:64910690c574	405	* @param __INSTANCE__ DMA Instance
AnnaBridge	145:64910690c574	406	* @param __REG__ Register to be read
AnnaBridge	145:64910690c574	407	* @retval Register value
AnnaBridge	145:64910690c574	408	*/
AnnaBridge	145:64910690c574	409	#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	145:64910690c574	410	/**
AnnaBridge	145:64910690c574	411	* @}
AnnaBridge	145:64910690c574	412	*/
AnnaBridge	145:64910690c574	413
AnnaBridge	145:64910690c574	414	/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy
AnnaBridge	145:64910690c574	415	* @{
AnnaBridge	145:64910690c574	416	*/
AnnaBridge	145:64910690c574	417	/**
AnnaBridge	145:64910690c574	418	* @brief Convert DMAx_Streamy into DMAx
AnnaBridge	145:64910690c574	419	* @param __STREAM_INSTANCE__ DMAx_Streamy
AnnaBridge	145:64910690c574	420	* @retval DMAx
AnnaBridge	145:64910690c574	421	*/
AnnaBridge	145:64910690c574	422	#define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \
AnnaBridge	145:64910690c574	423	(((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1)
AnnaBridge	145:64910690c574	424
AnnaBridge	145:64910690c574	425	/**
AnnaBridge	145:64910690c574	426	* @brief Convert DMAx_Streamy into LL_DMA_STREAM_y
AnnaBridge	145:64910690c574	427	* @param __STREAM_INSTANCE__ DMAx_Streamy
AnnaBridge	145:64910690c574	428	* @retval LL_DMA_CHANNEL_y
AnnaBridge	145:64910690c574	429	*/
AnnaBridge	145:64910690c574	430	#define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \
AnnaBridge	145:64910690c574	431	(((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \
AnnaBridge	145:64910690c574	432	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \
AnnaBridge	145:64910690c574	433	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \
AnnaBridge	145:64910690c574	434	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \
AnnaBridge	145:64910690c574	435	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \
AnnaBridge	145:64910690c574	436	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \
AnnaBridge	145:64910690c574	437	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \
AnnaBridge	145:64910690c574	438	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \
AnnaBridge	145:64910690c574	439	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \
AnnaBridge	145:64910690c574	440	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \
AnnaBridge	145:64910690c574	441	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
AnnaBridge	145:64910690c574	442	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \
AnnaBridge	145:64910690c574	443	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \
AnnaBridge	145:64910690c574	444	((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \
AnnaBridge	145:64910690c574	445	LL_DMA_STREAM_7)
AnnaBridge	145:64910690c574	446
AnnaBridge	145:64910690c574	447	/**
AnnaBridge	145:64910690c574	448	* @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy
AnnaBridge	145:64910690c574	449	* @param __DMA_INSTANCE__ DMAx
AnnaBridge	145:64910690c574	450	* @param __STREAM__ LL_DMA_STREAM_y
AnnaBridge	145:64910690c574	451	* @retval DMAx_Streamy
AnnaBridge	145:64910690c574	452	*/
AnnaBridge	145:64910690c574	453	#define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \
AnnaBridge	145:64910690c574	454	((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \
AnnaBridge	145:64910690c574	455	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \
AnnaBridge	145:64910690c574	456	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \
AnnaBridge	145:64910690c574	457	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \
AnnaBridge	145:64910690c574	458	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \
AnnaBridge	145:64910690c574	459	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \
AnnaBridge	145:64910690c574	460	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \
AnnaBridge	145:64910690c574	461	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \
AnnaBridge	145:64910690c574	462	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \
AnnaBridge	145:64910690c574	463	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \
AnnaBridge	145:64910690c574	464	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
AnnaBridge	145:64910690c574	465	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \
AnnaBridge	145:64910690c574	466	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \
AnnaBridge	145:64910690c574	467	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \
AnnaBridge	145:64910690c574	468	(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \
AnnaBridge	145:64910690c574	469	DMA2_Stream7)
AnnaBridge	145:64910690c574	470
AnnaBridge	145:64910690c574	471	/**
AnnaBridge	145:64910690c574	472	* @}
AnnaBridge	145:64910690c574	473	*/
AnnaBridge	145:64910690c574	474
AnnaBridge	145:64910690c574	475	/**
AnnaBridge	145:64910690c574	476	* @}
AnnaBridge	145:64910690c574	477	*/
AnnaBridge	145:64910690c574	478
AnnaBridge	145:64910690c574	479
AnnaBridge	145:64910690c574	480	/* Exported functions --------------------------------------------------------*/
AnnaBridge	145:64910690c574	481	/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
AnnaBridge	145:64910690c574	482	* @{
AnnaBridge	145:64910690c574	483	*/
AnnaBridge	145:64910690c574	484
AnnaBridge	145:64910690c574	485	/** @defgroup DMA_LL_EF_Configuration Configuration
AnnaBridge	145:64910690c574	486	* @{
AnnaBridge	145:64910690c574	487	*/
AnnaBridge	145:64910690c574	488	/**
AnnaBridge	145:64910690c574	489	* @brief Enable DMA stream.
AnnaBridge	145:64910690c574	490	* @rmtoll CR EN LL_DMA_EnableStream
AnnaBridge	145:64910690c574	491	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	492	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	493	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	494	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	495	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	496	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	497	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	498	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	499	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	500	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	501	* @retval None
AnnaBridge	145:64910690c574	502	*/
AnnaBridge	145:64910690c574	503	__STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	504	{
AnnaBridge	145:64910690c574	505	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
AnnaBridge	145:64910690c574	506	}
AnnaBridge	145:64910690c574	507
AnnaBridge	145:64910690c574	508	/**
AnnaBridge	145:64910690c574	509	* @brief Disable DMA stream.
AnnaBridge	145:64910690c574	510	* @rmtoll CR EN LL_DMA_DisableStream
AnnaBridge	145:64910690c574	511	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	512	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	513	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	514	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	515	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	516	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	517	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	518	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	519	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	520	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	521	* @retval None
AnnaBridge	145:64910690c574	522	*/
AnnaBridge	145:64910690c574	523	__STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	524	{
AnnaBridge	145:64910690c574	525	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
AnnaBridge	145:64910690c574	526	}
AnnaBridge	145:64910690c574	527
AnnaBridge	145:64910690c574	528	/**
AnnaBridge	145:64910690c574	529	* @brief Check if DMA stream is enabled or disabled.
AnnaBridge	145:64910690c574	530	* @rmtoll CR EN LL_DMA_IsEnabledStream
AnnaBridge	145:64910690c574	531	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	532	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	533	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	534	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	535	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	536	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	537	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	538	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	539	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	540	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	541	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	542	*/
AnnaBridge	145:64910690c574	543	__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	544	{
AnnaBridge	145:64910690c574	545	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN));
AnnaBridge	145:64910690c574	546	}
AnnaBridge	145:64910690c574	547
AnnaBridge	145:64910690c574	548	/**
AnnaBridge	145:64910690c574	549	* @brief Configure all parameters linked to DMA transfer.
AnnaBridge	145:64910690c574	550	* @rmtoll CR DIR LL_DMA_ConfigTransfer\n
AnnaBridge	145:64910690c574	551	* CR CIRC LL_DMA_ConfigTransfer\n
AnnaBridge	145:64910690c574	552	* CR PINC LL_DMA_ConfigTransfer\n
AnnaBridge	145:64910690c574	553	* CR MINC LL_DMA_ConfigTransfer\n
AnnaBridge	145:64910690c574	554	* CR PSIZE LL_DMA_ConfigTransfer\n
AnnaBridge	145:64910690c574	555	* CR MSIZE LL_DMA_ConfigTransfer\n
AnnaBridge	145:64910690c574	556	* CR PL LL_DMA_ConfigTransfer\n
AnnaBridge	145:64910690c574	557	* CR PFCTRL LL_DMA_ConfigTransfer
AnnaBridge	145:64910690c574	558	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	559	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	560	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	561	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	562	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	563	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	564	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	565	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	566	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	567	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	568	* @param Configuration This parameter must be a combination of all the following values:
AnnaBridge	145:64910690c574	569	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	145:64910690c574	570	* @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL
AnnaBridge	145:64910690c574	571	* @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge	145:64910690c574	572	* @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge	145:64910690c574	573	* @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge	145:64910690c574	574	* @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge	145:64910690c574	575	* @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge	145:64910690c574	576	*@retval None
AnnaBridge	145:64910690c574	577	*/
AnnaBridge	145:64910690c574	578	__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
AnnaBridge	145:64910690c574	579	{
AnnaBridge	145:64910690c574	580	MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR,
AnnaBridge	145:64910690c574	581	DMA_SxCR_DIR \| DMA_SxCR_CIRC \| DMA_SxCR_PINC \| DMA_SxCR_MINC \| DMA_SxCR_PSIZE \| DMA_SxCR_MSIZE \| DMA_SxCR_PL \| DMA_SxCR_PFCTRL,
AnnaBridge	145:64910690c574	582	Configuration);
AnnaBridge	145:64910690c574	583	}
AnnaBridge	145:64910690c574	584
AnnaBridge	145:64910690c574	585	/**
AnnaBridge	145:64910690c574	586	* @brief Set Data transfer direction (read from peripheral or from memory).
AnnaBridge	145:64910690c574	587	* @rmtoll CR DIR LL_DMA_SetDataTransferDirection
AnnaBridge	145:64910690c574	588	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	589	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	590	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	591	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	592	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	593	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	594	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	595	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	596	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	597	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	598	* @param Direction This parameter can be one of the following values:
AnnaBridge	145:64910690c574	599	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge	145:64910690c574	600	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge	145:64910690c574	601	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	145:64910690c574	602	* @retval None
AnnaBridge	145:64910690c574	603	*/
AnnaBridge	145:64910690c574	604	__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction)
AnnaBridge	145:64910690c574	605	{
AnnaBridge	145:64910690c574	606	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR, Direction);
AnnaBridge	145:64910690c574	607	}
AnnaBridge	145:64910690c574	608
AnnaBridge	145:64910690c574	609	/**
AnnaBridge	145:64910690c574	610	* @brief Get Data transfer direction (read from peripheral or from memory).
AnnaBridge	145:64910690c574	611	* @rmtoll CR DIR LL_DMA_GetDataTransferDirection
AnnaBridge	145:64910690c574	612	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	613	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	614	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	615	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	616	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	617	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	618	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	619	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	620	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	621	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	622	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	623	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge	145:64910690c574	624	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge	145:64910690c574	625	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	145:64910690c574	626	*/
AnnaBridge	145:64910690c574	627	__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	628	{
AnnaBridge	145:64910690c574	629	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR));
AnnaBridge	145:64910690c574	630	}
AnnaBridge	145:64910690c574	631
AnnaBridge	145:64910690c574	632	/**
AnnaBridge	145:64910690c574	633	* @brief Set DMA mode normal, circular or peripheral flow control.
AnnaBridge	145:64910690c574	634	* @rmtoll CR CIRC LL_DMA_SetMode\n
AnnaBridge	145:64910690c574	635	* CR PFCTRL LL_DMA_SetMode
AnnaBridge	145:64910690c574	636	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	637	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	638	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	639	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	640	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	641	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	642	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	643	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	644	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	645	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	646	* @param Mode This parameter can be one of the following values:
AnnaBridge	145:64910690c574	647	* @arg @ref LL_DMA_MODE_NORMAL
AnnaBridge	145:64910690c574	648	* @arg @ref LL_DMA_MODE_CIRCULAR
AnnaBridge	145:64910690c574	649	* @arg @ref LL_DMA_MODE_PFCTRL
AnnaBridge	145:64910690c574	650	* @retval None
AnnaBridge	145:64910690c574	651	*/
AnnaBridge	145:64910690c574	652	__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
AnnaBridge	145:64910690c574	653	{
AnnaBridge	145:64910690c574	654	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC \| DMA_SxCR_PFCTRL, Mode);
AnnaBridge	145:64910690c574	655	}
AnnaBridge	145:64910690c574	656
AnnaBridge	145:64910690c574	657	/**
AnnaBridge	145:64910690c574	658	* @brief Get DMA mode normal, circular or peripheral flow control.
AnnaBridge	145:64910690c574	659	* @rmtoll CR CIRC LL_DMA_GetMode\n
AnnaBridge	145:64910690c574	660	* CR PFCTRL LL_DMA_GetMode
AnnaBridge	145:64910690c574	661	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	662	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	663	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	664	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	665	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	666	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	667	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	668	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	669	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	670	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	671	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	672	* @arg @ref LL_DMA_MODE_NORMAL
AnnaBridge	145:64910690c574	673	* @arg @ref LL_DMA_MODE_CIRCULAR
AnnaBridge	145:64910690c574	674	* @arg @ref LL_DMA_MODE_PFCTRL
AnnaBridge	145:64910690c574	675	*/
AnnaBridge	145:64910690c574	676	__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	677	{
AnnaBridge	145:64910690c574	678	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC \| DMA_SxCR_PFCTRL));
AnnaBridge	145:64910690c574	679	}
AnnaBridge	145:64910690c574	680
AnnaBridge	145:64910690c574	681	/**
AnnaBridge	145:64910690c574	682	* @brief Set Peripheral increment mode.
AnnaBridge	145:64910690c574	683	* @rmtoll CR PINC LL_DMA_SetPeriphIncMode
AnnaBridge	145:64910690c574	684	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	685	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	686	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	687	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	688	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	689	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	690	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	691	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	692	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	693	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	694	* @param IncrementMode This parameter can be one of the following values:
AnnaBridge	145:64910690c574	695	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge	145:64910690c574	696	* @arg @ref LL_DMA_PERIPH_INCREMENT
AnnaBridge	145:64910690c574	697	* @retval None
AnnaBridge	145:64910690c574	698	*/
AnnaBridge	145:64910690c574	699	__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
AnnaBridge	145:64910690c574	700	{
AnnaBridge	145:64910690c574	701	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC, IncrementMode);
AnnaBridge	145:64910690c574	702	}
AnnaBridge	145:64910690c574	703
AnnaBridge	145:64910690c574	704	/**
AnnaBridge	145:64910690c574	705	* @brief Get Peripheral increment mode.
AnnaBridge	145:64910690c574	706	* @rmtoll CR PINC LL_DMA_GetPeriphIncMode
AnnaBridge	145:64910690c574	707	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	708	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	709	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	710	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	711	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	712	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	713	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	714	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	715	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	716	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	717	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	718	* @arg @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge	145:64910690c574	719	* @arg @ref LL_DMA_PERIPH_INCREMENT
AnnaBridge	145:64910690c574	720	*/
AnnaBridge	145:64910690c574	721	__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	722	{
AnnaBridge	145:64910690c574	723	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC));
AnnaBridge	145:64910690c574	724	}
AnnaBridge	145:64910690c574	725
AnnaBridge	145:64910690c574	726	/**
AnnaBridge	145:64910690c574	727	* @brief Set Memory increment mode.
AnnaBridge	145:64910690c574	728	* @rmtoll CR MINC LL_DMA_SetMemoryIncMode
AnnaBridge	145:64910690c574	729	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	730	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	731	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	732	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	733	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	734	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	735	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	736	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	737	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	738	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	739	* @param IncrementMode This parameter can be one of the following values:
AnnaBridge	145:64910690c574	740	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge	145:64910690c574	741	* @arg @ref LL_DMA_MEMORY_INCREMENT
AnnaBridge	145:64910690c574	742	* @retval None
AnnaBridge	145:64910690c574	743	*/
AnnaBridge	145:64910690c574	744	__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
AnnaBridge	145:64910690c574	745	{
AnnaBridge	145:64910690c574	746	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC, IncrementMode);
AnnaBridge	145:64910690c574	747	}
AnnaBridge	145:64910690c574	748
AnnaBridge	145:64910690c574	749	/**
AnnaBridge	145:64910690c574	750	* @brief Get Memory increment mode.
AnnaBridge	145:64910690c574	751	* @rmtoll CR MINC LL_DMA_GetMemoryIncMode
AnnaBridge	145:64910690c574	752	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	753	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	754	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	755	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	756	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	757	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	758	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	759	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	760	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	761	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	762	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	763	* @arg @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge	145:64910690c574	764	* @arg @ref LL_DMA_MEMORY_INCREMENT
AnnaBridge	145:64910690c574	765	*/
AnnaBridge	145:64910690c574	766	__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	767	{
AnnaBridge	145:64910690c574	768	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC));
AnnaBridge	145:64910690c574	769	}
AnnaBridge	145:64910690c574	770
AnnaBridge	145:64910690c574	771	/**
AnnaBridge	145:64910690c574	772	* @brief Set Peripheral size.
AnnaBridge	145:64910690c574	773	* @rmtoll CR PSIZE LL_DMA_SetPeriphSize
AnnaBridge	145:64910690c574	774	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	775	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	776	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	777	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	778	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	779	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	780	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	781	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	782	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	783	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	784	* @param Size This parameter can be one of the following values:
AnnaBridge	145:64910690c574	785	* @arg @ref LL_DMA_PDATAALIGN_BYTE
AnnaBridge	145:64910690c574	786	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
AnnaBridge	145:64910690c574	787	* @arg @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge	145:64910690c574	788	* @retval None
AnnaBridge	145:64910690c574	789	*/
AnnaBridge	145:64910690c574	790	__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
AnnaBridge	145:64910690c574	791	{
AnnaBridge	145:64910690c574	792	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE, Size);
AnnaBridge	145:64910690c574	793	}
AnnaBridge	145:64910690c574	794
AnnaBridge	145:64910690c574	795	/**
AnnaBridge	145:64910690c574	796	* @brief Get Peripheral size.
AnnaBridge	145:64910690c574	797	* @rmtoll CR PSIZE LL_DMA_GetPeriphSize
AnnaBridge	145:64910690c574	798	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	799	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	800	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	801	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	802	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	803	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	804	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	805	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	806	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	807	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	808	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	809	* @arg @ref LL_DMA_PDATAALIGN_BYTE
AnnaBridge	145:64910690c574	810	* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
AnnaBridge	145:64910690c574	811	* @arg @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge	145:64910690c574	812	*/
AnnaBridge	145:64910690c574	813	__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	814	{
AnnaBridge	145:64910690c574	815	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE));
AnnaBridge	145:64910690c574	816	}
AnnaBridge	145:64910690c574	817
AnnaBridge	145:64910690c574	818	/**
AnnaBridge	145:64910690c574	819	* @brief Set Memory size.
AnnaBridge	145:64910690c574	820	* @rmtoll CR MSIZE LL_DMA_SetMemorySize
AnnaBridge	145:64910690c574	821	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	822	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	823	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	824	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	825	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	826	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	827	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	828	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	829	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	830	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	831	* @param Size This parameter can be one of the following values:
AnnaBridge	145:64910690c574	832	* @arg @ref LL_DMA_MDATAALIGN_BYTE
AnnaBridge	145:64910690c574	833	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
AnnaBridge	145:64910690c574	834	* @arg @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge	145:64910690c574	835	* @retval None
AnnaBridge	145:64910690c574	836	*/
AnnaBridge	145:64910690c574	837	__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
AnnaBridge	145:64910690c574	838	{
AnnaBridge	145:64910690c574	839	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE, Size);
AnnaBridge	145:64910690c574	840	}
AnnaBridge	145:64910690c574	841
AnnaBridge	145:64910690c574	842	/**
AnnaBridge	145:64910690c574	843	* @brief Get Memory size.
AnnaBridge	145:64910690c574	844	* @rmtoll CR MSIZE LL_DMA_GetMemorySize
AnnaBridge	145:64910690c574	845	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	846	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	847	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	848	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	849	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	850	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	851	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	852	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	853	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	854	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	855	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	856	* @arg @ref LL_DMA_MDATAALIGN_BYTE
AnnaBridge	145:64910690c574	857	* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
AnnaBridge	145:64910690c574	858	* @arg @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge	145:64910690c574	859	*/
AnnaBridge	145:64910690c574	860	__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	861	{
AnnaBridge	145:64910690c574	862	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE));
AnnaBridge	145:64910690c574	863	}
AnnaBridge	145:64910690c574	864
AnnaBridge	145:64910690c574	865	/**
AnnaBridge	145:64910690c574	866	* @brief Set Peripheral increment offset size.
AnnaBridge	145:64910690c574	867	* @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize
AnnaBridge	145:64910690c574	868	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	869	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	870	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	871	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	872	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	873	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	874	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	875	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	876	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	877	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	878	* @param OffsetSize This parameter can be one of the following values:
AnnaBridge	145:64910690c574	879	* @arg @ref LL_DMA_OFFSETSIZE_PSIZE
AnnaBridge	145:64910690c574	880	* @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
AnnaBridge	145:64910690c574	881	* @retval None
AnnaBridge	145:64910690c574	882	*/
AnnaBridge	145:64910690c574	883	__STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)
AnnaBridge	145:64910690c574	884	{
AnnaBridge	145:64910690c574	885	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS, OffsetSize);
AnnaBridge	145:64910690c574	886	}
AnnaBridge	145:64910690c574	887
AnnaBridge	145:64910690c574	888	/**
AnnaBridge	145:64910690c574	889	* @brief Get Peripheral increment offset size.
AnnaBridge	145:64910690c574	890	* @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize
AnnaBridge	145:64910690c574	891	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	892	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	893	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	894	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	895	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	896	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	897	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	898	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	899	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	900	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	901	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	902	* @arg @ref LL_DMA_OFFSETSIZE_PSIZE
AnnaBridge	145:64910690c574	903	* @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
AnnaBridge	145:64910690c574	904	*/
AnnaBridge	145:64910690c574	905	__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	906	{
AnnaBridge	145:64910690c574	907	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS));
AnnaBridge	145:64910690c574	908	}
AnnaBridge	145:64910690c574	909
AnnaBridge	145:64910690c574	910	/**
AnnaBridge	145:64910690c574	911	* @brief Set Stream priority level.
AnnaBridge	145:64910690c574	912	* @rmtoll CR PL LL_DMA_SetStreamPriorityLevel
AnnaBridge	145:64910690c574	913	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	914	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	915	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	916	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	917	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	918	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	919	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	920	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	921	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	922	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	923	* @param Priority This parameter can be one of the following values:
AnnaBridge	145:64910690c574	924	* @arg @ref LL_DMA_PRIORITY_LOW
AnnaBridge	145:64910690c574	925	* @arg @ref LL_DMA_PRIORITY_MEDIUM
AnnaBridge	145:64910690c574	926	* @arg @ref LL_DMA_PRIORITY_HIGH
AnnaBridge	145:64910690c574	927	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge	145:64910690c574	928	* @retval None
AnnaBridge	145:64910690c574	929	*/
AnnaBridge	145:64910690c574	930	__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority)
AnnaBridge	145:64910690c574	931	{
AnnaBridge	145:64910690c574	932	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL, Priority);
AnnaBridge	145:64910690c574	933	}
AnnaBridge	145:64910690c574	934
AnnaBridge	145:64910690c574	935	/**
AnnaBridge	145:64910690c574	936	* @brief Get Stream priority level.
AnnaBridge	145:64910690c574	937	* @rmtoll CR PL LL_DMA_GetStreamPriorityLevel
AnnaBridge	145:64910690c574	938	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	939	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	940	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	941	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	942	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	943	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	944	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	945	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	946	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	947	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	948	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	949	* @arg @ref LL_DMA_PRIORITY_LOW
AnnaBridge	145:64910690c574	950	* @arg @ref LL_DMA_PRIORITY_MEDIUM
AnnaBridge	145:64910690c574	951	* @arg @ref LL_DMA_PRIORITY_HIGH
AnnaBridge	145:64910690c574	952	* @arg @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge	145:64910690c574	953	*/
AnnaBridge	145:64910690c574	954	__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	955	{
AnnaBridge	145:64910690c574	956	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL));
AnnaBridge	145:64910690c574	957	}
AnnaBridge	145:64910690c574	958
AnnaBridge	145:64910690c574	959	/**
AnnaBridge	145:64910690c574	960	* @brief Set Number of data to transfer.
AnnaBridge	145:64910690c574	961	* @rmtoll NDTR NDT LL_DMA_SetDataLength
AnnaBridge	145:64910690c574	962	* @note This action has no effect if
AnnaBridge	145:64910690c574	963	* stream is enabled.
AnnaBridge	145:64910690c574	964	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	965	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	966	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	967	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	968	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	969	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	970	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	971	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	972	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	973	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	974	* @param NbData Between 0 to 0xFFFFFFFF
AnnaBridge	145:64910690c574	975	* @retval None
AnnaBridge	145:64910690c574	976	*/
AnnaBridge	145:64910690c574	977	__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData)
AnnaBridge	145:64910690c574	978	{
AnnaBridge	145:64910690c574	979	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT, NbData);
AnnaBridge	145:64910690c574	980	}
AnnaBridge	145:64910690c574	981
AnnaBridge	145:64910690c574	982	/**
AnnaBridge	145:64910690c574	983	* @brief Get Number of data to transfer.
AnnaBridge	145:64910690c574	984	* @rmtoll NDTR NDT LL_DMA_GetDataLength
AnnaBridge	145:64910690c574	985	* @note Once the stream is enabled, the return value indicate the
AnnaBridge	145:64910690c574	986	* remaining bytes to be transmitted.
AnnaBridge	145:64910690c574	987	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	988	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	989	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	990	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	991	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	992	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	993	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	994	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	995	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	996	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	997	* @retval Between 0 to 0xFFFFFFFF
AnnaBridge	145:64910690c574	998	*/
AnnaBridge	145:64910690c574	999	__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	1000	{
AnnaBridge	145:64910690c574	1001	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT));
AnnaBridge	145:64910690c574	1002	}
AnnaBridge	145:64910690c574	1003
AnnaBridge	145:64910690c574	1004	/**
AnnaBridge	145:64910690c574	1005	* @brief Select Channel number associated to the Stream.
AnnaBridge	145:64910690c574	1006	* @rmtoll CR CHSEL LL_DMA_SetChannelSelection
AnnaBridge	145:64910690c574	1007	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1008	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1009	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	1010	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	1011	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	1012	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	1013	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	1014	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	1015	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	1016	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	1017	* @param Channel This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1018	* @arg @ref LL_DMA_CHANNEL_0
AnnaBridge	145:64910690c574	1019	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	1020	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	1021	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	1022	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	1023	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	1024	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	1025	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	1026	* @retval None
AnnaBridge	145:64910690c574	1027	*/
AnnaBridge	145:64910690c574	1028	__STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channel)
AnnaBridge	145:64910690c574	1029	{
AnnaBridge	145:64910690c574	1030	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL, Channel);
AnnaBridge	145:64910690c574	1031	}
AnnaBridge	145:64910690c574	1032
AnnaBridge	145:64910690c574	1033	/**
AnnaBridge	145:64910690c574	1034	* @brief Get the Channel number associated to the Stream.
AnnaBridge	145:64910690c574	1035	* @rmtoll CR CHSEL LL_DMA_GetChannelSelection
AnnaBridge	145:64910690c574	1036	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1037	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1038	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	1039	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	1040	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	1041	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	1042	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	1043	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	1044	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	1045	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	1046	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1047	* @arg @ref LL_DMA_CHANNEL_0
AnnaBridge	145:64910690c574	1048	* @arg @ref LL_DMA_CHANNEL_1
AnnaBridge	145:64910690c574	1049	* @arg @ref LL_DMA_CHANNEL_2
AnnaBridge	145:64910690c574	1050	* @arg @ref LL_DMA_CHANNEL_3
AnnaBridge	145:64910690c574	1051	* @arg @ref LL_DMA_CHANNEL_4
AnnaBridge	145:64910690c574	1052	* @arg @ref LL_DMA_CHANNEL_5
AnnaBridge	145:64910690c574	1053	* @arg @ref LL_DMA_CHANNEL_6
AnnaBridge	145:64910690c574	1054	* @arg @ref LL_DMA_CHANNEL_7
AnnaBridge	145:64910690c574	1055	*/
AnnaBridge	145:64910690c574	1056	__STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	1057	{
AnnaBridge	145:64910690c574	1058	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL));
AnnaBridge	145:64910690c574	1059	}
AnnaBridge	145:64910690c574	1060
AnnaBridge	145:64910690c574	1061	/**
AnnaBridge	145:64910690c574	1062	* @brief Set Memory burst transfer configuration.
AnnaBridge	145:64910690c574	1063	* @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer
AnnaBridge	145:64910690c574	1064	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1065	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1066	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	1067	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	1068	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	1069	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	1070	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	1071	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	1072	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	1073	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	1074	* @param Mburst This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1075	* @arg @ref LL_DMA_MBURST_SINGLE
AnnaBridge	145:64910690c574	1076	* @arg @ref LL_DMA_MBURST_INC4
AnnaBridge	145:64910690c574	1077	* @arg @ref LL_DMA_MBURST_INC8
AnnaBridge	145:64910690c574	1078	* @arg @ref LL_DMA_MBURST_INC16
AnnaBridge	145:64910690c574	1079	* @retval None
AnnaBridge	145:64910690c574	1080	*/
AnnaBridge	145:64910690c574	1081	__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
AnnaBridge	145:64910690c574	1082	{
AnnaBridge	145:64910690c574	1083	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST, Mburst);
AnnaBridge	145:64910690c574	1084	}
AnnaBridge	145:64910690c574	1085
AnnaBridge	145:64910690c574	1086	/**
AnnaBridge	145:64910690c574	1087	* @brief Get Memory burst transfer configuration.
AnnaBridge	145:64910690c574	1088	* @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer
AnnaBridge	145:64910690c574	1089	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1090	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1091	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	1092	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	1093	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	1094	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	1095	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	1096	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	1097	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	1098	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	1099	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1100	* @arg @ref LL_DMA_MBURST_SINGLE
AnnaBridge	145:64910690c574	1101	* @arg @ref LL_DMA_MBURST_INC4
AnnaBridge	145:64910690c574	1102	* @arg @ref LL_DMA_MBURST_INC8
AnnaBridge	145:64910690c574	1103	* @arg @ref LL_DMA_MBURST_INC16
AnnaBridge	145:64910690c574	1104	*/
AnnaBridge	145:64910690c574	1105	__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	1106	{
AnnaBridge	145:64910690c574	1107	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST));
AnnaBridge	145:64910690c574	1108	}
AnnaBridge	145:64910690c574	1109
AnnaBridge	145:64910690c574	1110	/**
AnnaBridge	145:64910690c574	1111	* @brief Set Peripheral burst transfer configuration.
AnnaBridge	145:64910690c574	1112	* @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer
AnnaBridge	145:64910690c574	1113	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1114	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1115	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	1116	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	1117	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	1118	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	1119	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	1120	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	1121	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	1122	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	1123	* @param Pburst This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1124	* @arg @ref LL_DMA_PBURST_SINGLE
AnnaBridge	145:64910690c574	1125	* @arg @ref LL_DMA_PBURST_INC4
AnnaBridge	145:64910690c574	1126	* @arg @ref LL_DMA_PBURST_INC8
AnnaBridge	145:64910690c574	1127	* @arg @ref LL_DMA_PBURST_INC16
AnnaBridge	145:64910690c574	1128	* @retval None
AnnaBridge	145:64910690c574	1129	*/
AnnaBridge	145:64910690c574	1130	__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
AnnaBridge	145:64910690c574	1131	{
AnnaBridge	145:64910690c574	1132	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST, Pburst);
AnnaBridge	145:64910690c574	1133	}
AnnaBridge	145:64910690c574	1134
AnnaBridge	145:64910690c574	1135	/**
AnnaBridge	145:64910690c574	1136	* @brief Get Peripheral burst transfer configuration.
AnnaBridge	145:64910690c574	1137	* @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer
AnnaBridge	145:64910690c574	1138	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1139	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1140	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	1141	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	1142	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	1143	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	1144	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	1145	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	1146	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	1147	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	1148	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1149	* @arg @ref LL_DMA_PBURST_SINGLE
AnnaBridge	145:64910690c574	1150	* @arg @ref LL_DMA_PBURST_INC4
AnnaBridge	145:64910690c574	1151	* @arg @ref LL_DMA_PBURST_INC8
AnnaBridge	145:64910690c574	1152	* @arg @ref LL_DMA_PBURST_INC16
AnnaBridge	145:64910690c574	1153	*/
AnnaBridge	145:64910690c574	1154	__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	1155	{
AnnaBridge	145:64910690c574	1156	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST));
AnnaBridge	145:64910690c574	1157	}
AnnaBridge	145:64910690c574	1158
AnnaBridge	145:64910690c574	1159	/**
AnnaBridge	145:64910690c574	1160	* @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
AnnaBridge	145:64910690c574	1161	* @rmtoll CR CT LL_DMA_SetCurrentTargetMem
AnnaBridge	145:64910690c574	1162	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1163	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1164	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	1165	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	1166	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	1167	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	1168	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	1169	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	1170	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	1171	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	1172	* @param CurrentMemory This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1173	* @arg @ref LL_DMA_CURRENTTARGETMEM0
AnnaBridge	145:64910690c574	1174	* @arg @ref LL_DMA_CURRENTTARGETMEM1
AnnaBridge	145:64910690c574	1175	* @retval None
AnnaBridge	145:64910690c574	1176	*/
AnnaBridge	145:64910690c574	1177	__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)
AnnaBridge	145:64910690c574	1178	{
AnnaBridge	145:64910690c574	1179	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT, CurrentMemory);
AnnaBridge	145:64910690c574	1180	}
AnnaBridge	145:64910690c574	1181
AnnaBridge	145:64910690c574	1182	/**
AnnaBridge	145:64910690c574	1183	* @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
AnnaBridge	145:64910690c574	1184	* @rmtoll CR CT LL_DMA_GetCurrentTargetMem
AnnaBridge	145:64910690c574	1185	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1186	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1187	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	1188	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	1189	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	1190	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	1191	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	1192	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	1193	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	1194	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	1195	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1196	* @arg @ref LL_DMA_CURRENTTARGETMEM0
AnnaBridge	145:64910690c574	1197	* @arg @ref LL_DMA_CURRENTTARGETMEM1
AnnaBridge	145:64910690c574	1198	*/
AnnaBridge	145:64910690c574	1199	__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	1200	{
AnnaBridge	145:64910690c574	1201	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT));
AnnaBridge	145:64910690c574	1202	}
AnnaBridge	145:64910690c574	1203
AnnaBridge	145:64910690c574	1204	/**
AnnaBridge	145:64910690c574	1205	* @brief Enable the double buffer mode.
AnnaBridge	145:64910690c574	1206	* @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode
AnnaBridge	145:64910690c574	1207	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1208	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1209	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	1210	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	1211	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	1212	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	1213	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	1214	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	1215	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	1216	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	1217	* @retval None
AnnaBridge	145:64910690c574	1218	*/
AnnaBridge	145:64910690c574	1219	__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	1220	{
AnnaBridge	145:64910690c574	1221	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
AnnaBridge	145:64910690c574	1222	}
AnnaBridge	145:64910690c574	1223
AnnaBridge	145:64910690c574	1224	/**
AnnaBridge	145:64910690c574	1225	* @brief Disable the double buffer mode.
AnnaBridge	145:64910690c574	1226	* @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode
AnnaBridge	145:64910690c574	1227	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1228	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1229	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	1230	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	1231	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	1232	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	1233	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	1234	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	1235	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	1236	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	1237	* @retval None
AnnaBridge	145:64910690c574	1238	*/
AnnaBridge	145:64910690c574	1239	__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	1240	{
AnnaBridge	145:64910690c574	1241	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
AnnaBridge	145:64910690c574	1242	}
AnnaBridge	145:64910690c574	1243
AnnaBridge	145:64910690c574	1244	/**
AnnaBridge	145:64910690c574	1245	* @brief Get FIFO status.
AnnaBridge	145:64910690c574	1246	* @rmtoll FCR FS LL_DMA_GetFIFOStatus
AnnaBridge	145:64910690c574	1247	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1248	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1249	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	1250	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	1251	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	1252	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	1253	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	1254	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	1255	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	1256	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	1257	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1258	* @arg @ref LL_DMA_FIFOSTATUS_0_25
AnnaBridge	145:64910690c574	1259	* @arg @ref LL_DMA_FIFOSTATUS_25_50
AnnaBridge	145:64910690c574	1260	* @arg @ref LL_DMA_FIFOSTATUS_50_75
AnnaBridge	145:64910690c574	1261	* @arg @ref LL_DMA_FIFOSTATUS_75_100
AnnaBridge	145:64910690c574	1262	* @arg @ref LL_DMA_FIFOSTATUS_EMPTY
AnnaBridge	145:64910690c574	1263	* @arg @ref LL_DMA_FIFOSTATUS_FULL
AnnaBridge	145:64910690c574	1264	*/
AnnaBridge	145:64910690c574	1265	__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	1266	{
AnnaBridge	145:64910690c574	1267	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FS));
AnnaBridge	145:64910690c574	1268	}
AnnaBridge	145:64910690c574	1269
AnnaBridge	145:64910690c574	1270	/**
AnnaBridge	145:64910690c574	1271	* @brief Disable Fifo mode.
AnnaBridge	145:64910690c574	1272	* @rmtoll FCR DMDIS LL_DMA_DisableFifoMode
AnnaBridge	145:64910690c574	1273	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1274	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1275	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	1276	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	1277	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	1278	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	1279	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	1280	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	1281	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	1282	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	1283	* @retval None
AnnaBridge	145:64910690c574	1284	*/
AnnaBridge	145:64910690c574	1285	__STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	1286	{
AnnaBridge	145:64910690c574	1287	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
AnnaBridge	145:64910690c574	1288	}
AnnaBridge	145:64910690c574	1289
AnnaBridge	145:64910690c574	1290	/**
AnnaBridge	145:64910690c574	1291	* @brief Enable Fifo mode.
AnnaBridge	145:64910690c574	1292	* @rmtoll FCR DMDIS LL_DMA_EnableFifoMode
AnnaBridge	145:64910690c574	1293	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1294	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1295	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	1296	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	1297	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	1298	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	1299	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	1300	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	1301	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	1302	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	1303	* @retval None
AnnaBridge	145:64910690c574	1304	*/
AnnaBridge	145:64910690c574	1305	__STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	1306	{
AnnaBridge	145:64910690c574	1307	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
AnnaBridge	145:64910690c574	1308	}
AnnaBridge	145:64910690c574	1309
AnnaBridge	145:64910690c574	1310	/**
AnnaBridge	145:64910690c574	1311	* @brief Select FIFO threshold.
AnnaBridge	145:64910690c574	1312	* @rmtoll FCR FTH LL_DMA_SetFIFOThreshold
AnnaBridge	145:64910690c574	1313	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1314	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1315	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	1316	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	1317	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	1318	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	1319	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	1320	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	1321	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	1322	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	1323	* @param Threshold This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1324	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
AnnaBridge	145:64910690c574	1325	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
AnnaBridge	145:64910690c574	1326	* @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
AnnaBridge	145:64910690c574	1327	* @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
AnnaBridge	145:64910690c574	1328	* @retval None
AnnaBridge	145:64910690c574	1329	*/
AnnaBridge	145:64910690c574	1330	__STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)
AnnaBridge	145:64910690c574	1331	{
AnnaBridge	145:64910690c574	1332	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH, Threshold);
AnnaBridge	145:64910690c574	1333	}
AnnaBridge	145:64910690c574	1334
AnnaBridge	145:64910690c574	1335	/**
AnnaBridge	145:64910690c574	1336	* @brief Get FIFO threshold.
AnnaBridge	145:64910690c574	1337	* @rmtoll FCR FTH LL_DMA_GetFIFOThreshold
AnnaBridge	145:64910690c574	1338	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1339	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1340	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	1341	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	1342	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	1343	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	1344	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	1345	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	1346	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	1347	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	1348	* @retval Returned value can be one of the following values:
AnnaBridge	145:64910690c574	1349	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
AnnaBridge	145:64910690c574	1350	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
AnnaBridge	145:64910690c574	1351	* @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
AnnaBridge	145:64910690c574	1352	* @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
AnnaBridge	145:64910690c574	1353	*/
AnnaBridge	145:64910690c574	1354	__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	1355	{
AnnaBridge	145:64910690c574	1356	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH));
AnnaBridge	145:64910690c574	1357	}
AnnaBridge	145:64910690c574	1358
AnnaBridge	145:64910690c574	1359	/**
AnnaBridge	145:64910690c574	1360	* @brief Configure the FIFO .
AnnaBridge	145:64910690c574	1361	* @rmtoll FCR FTH LL_DMA_ConfigFifo\n
AnnaBridge	145:64910690c574	1362	* FCR DMDIS LL_DMA_ConfigFifo
AnnaBridge	145:64910690c574	1363	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1364	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1365	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	1366	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	1367	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	1368	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	1369	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	1370	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	1371	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	1372	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	1373	* @param FifoMode This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1374	* @arg @ref LL_DMA_FIFOMODE_ENABLE
AnnaBridge	145:64910690c574	1375	* @arg @ref LL_DMA_FIFOMODE_DISABLE
AnnaBridge	145:64910690c574	1376	* @param FifoThreshold This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1377	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
AnnaBridge	145:64910690c574	1378	* @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
AnnaBridge	145:64910690c574	1379	* @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
AnnaBridge	145:64910690c574	1380	* @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
AnnaBridge	145:64910690c574	1381	* @retval None
AnnaBridge	145:64910690c574	1382	*/
AnnaBridge	145:64910690c574	1383	__STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)
AnnaBridge	145:64910690c574	1384	{
AnnaBridge	145:64910690c574	1385	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH\|DMA_SxFCR_DMDIS, FifoMode\|FifoThreshold);
AnnaBridge	145:64910690c574	1386	}
AnnaBridge	145:64910690c574	1387
AnnaBridge	145:64910690c574	1388	/**
AnnaBridge	145:64910690c574	1389	* @brief Configure the Source and Destination addresses.
AnnaBridge	145:64910690c574	1390	* @note This API must not be called when the DMA stream is enabled.
AnnaBridge	145:64910690c574	1391	* @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n
AnnaBridge	145:64910690c574	1392	* PAR PA LL_DMA_ConfigAddresses
AnnaBridge	145:64910690c574	1393	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1394	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1395	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	1396	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	1397	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	1398	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	1399	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	1400	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	1401	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	1402	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	1403	* @param SrcAddress Between 0 to 0xFFFFFFFF
AnnaBridge	145:64910690c574	1404	* @param DstAddress Between 0 to 0xFFFFFFFF
AnnaBridge	145:64910690c574	1405	* @param Direction This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1406	* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge	145:64910690c574	1407	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge	145:64910690c574	1408	* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge	145:64910690c574	1409	* @retval None
AnnaBridge	145:64910690c574	1410	*/
AnnaBridge	145:64910690c574	1411	__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
AnnaBridge	145:64910690c574	1412	{
AnnaBridge	145:64910690c574	1413	/* Direction Memory to Periph */
AnnaBridge	145:64910690c574	1414	if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
AnnaBridge	145:64910690c574	1415	{
AnnaBridge	145:64910690c574	1416	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, SrcAddress);
AnnaBridge	145:64910690c574	1417	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, DstAddress);
AnnaBridge	145:64910690c574	1418	}
AnnaBridge	145:64910690c574	1419	/* Direction Periph to Memory and Memory to Memory */
AnnaBridge	145:64910690c574	1420	else
AnnaBridge	145:64910690c574	1421	{
AnnaBridge	145:64910690c574	1422	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, SrcAddress);
AnnaBridge	145:64910690c574	1423	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, DstAddress);
AnnaBridge	145:64910690c574	1424	}
AnnaBridge	145:64910690c574	1425	}
AnnaBridge	145:64910690c574	1426
AnnaBridge	145:64910690c574	1427	/**
AnnaBridge	145:64910690c574	1428	* @brief Set the Memory address.
AnnaBridge	145:64910690c574	1429	* @rmtoll M0AR M0A LL_DMA_SetMemoryAddress
AnnaBridge	145:64910690c574	1430	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	145:64910690c574	1431	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	145:64910690c574	1432	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1433	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1434	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	1435	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	1436	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	1437	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	1438	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	1439	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	1440	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	1441	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	1442	* @param MemoryAddress Between 0 to 0xFFFFFFFF
AnnaBridge	145:64910690c574	1443	* @retval None
AnnaBridge	145:64910690c574	1444	*/
AnnaBridge	145:64910690c574	1445	__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
AnnaBridge	145:64910690c574	1446	{
AnnaBridge	145:64910690c574	1447	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
AnnaBridge	145:64910690c574	1448	}
AnnaBridge	145:64910690c574	1449
AnnaBridge	145:64910690c574	1450	/**
AnnaBridge	145:64910690c574	1451	* @brief Set the Peripheral address.
AnnaBridge	145:64910690c574	1452	* @rmtoll PAR PA LL_DMA_SetPeriphAddress
AnnaBridge	145:64910690c574	1453	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	145:64910690c574	1454	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	145:64910690c574	1455	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1456	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1457	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	1458	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	1459	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	1460	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	1461	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	1462	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	1463	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	1464	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	1465	* @param PeriphAddress Between 0 to 0xFFFFFFFF
AnnaBridge	145:64910690c574	1466	* @retval None
AnnaBridge	145:64910690c574	1467	*/
AnnaBridge	145:64910690c574	1468	__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAddress)
AnnaBridge	145:64910690c574	1469	{
AnnaBridge	145:64910690c574	1470	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, PeriphAddress);
AnnaBridge	145:64910690c574	1471	}
AnnaBridge	145:64910690c574	1472
AnnaBridge	145:64910690c574	1473	/**
AnnaBridge	145:64910690c574	1474	* @brief Get the Memory address.
AnnaBridge	145:64910690c574	1475	* @rmtoll M0AR M0A LL_DMA_GetMemoryAddress
AnnaBridge	145:64910690c574	1476	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	145:64910690c574	1477	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1478	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1479	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	1480	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	1481	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	1482	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	1483	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	1484	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	1485	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	1486	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	1487	* @retval Between 0 to 0xFFFFFFFF
AnnaBridge	145:64910690c574	1488	*/
AnnaBridge	145:64910690c574	1489	__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	1490	{
AnnaBridge	145:64910690c574	1491	return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
AnnaBridge	145:64910690c574	1492	}
AnnaBridge	145:64910690c574	1493
AnnaBridge	145:64910690c574	1494	/**
AnnaBridge	145:64910690c574	1495	* @brief Get the Peripheral address.
AnnaBridge	145:64910690c574	1496	* @rmtoll PAR PA LL_DMA_GetPeriphAddress
AnnaBridge	145:64910690c574	1497	* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge	145:64910690c574	1498	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1499	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1500	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	1501	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	1502	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	1503	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	1504	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	1505	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	1506	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	1507	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	1508	* @retval Between 0 to 0xFFFFFFFF
AnnaBridge	145:64910690c574	1509	*/
AnnaBridge	145:64910690c574	1510	__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	1511	{
AnnaBridge	145:64910690c574	1512	return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
AnnaBridge	145:64910690c574	1513	}
AnnaBridge	145:64910690c574	1514
AnnaBridge	145:64910690c574	1515	/**
AnnaBridge	145:64910690c574	1516	* @brief Set the Memory to Memory Source address.
AnnaBridge	145:64910690c574	1517	* @rmtoll PAR PA LL_DMA_SetM2MSrcAddress
AnnaBridge	145:64910690c574	1518	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	145:64910690c574	1519	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	145:64910690c574	1520	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1521	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1522	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	1523	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	1524	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	1525	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	1526	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	1527	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	1528	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	1529	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	1530	* @param MemoryAddress Between 0 to 0xFFFFFFFF
AnnaBridge	145:64910690c574	1531	* @retval None
AnnaBridge	145:64910690c574	1532	*/
AnnaBridge	145:64910690c574	1533	__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
AnnaBridge	145:64910690c574	1534	{
AnnaBridge	145:64910690c574	1535	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, MemoryAddress);
AnnaBridge	145:64910690c574	1536	}
AnnaBridge	145:64910690c574	1537
AnnaBridge	145:64910690c574	1538	/**
AnnaBridge	145:64910690c574	1539	* @brief Set the Memory to Memory Destination address.
AnnaBridge	145:64910690c574	1540	* @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress
AnnaBridge	145:64910690c574	1541	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	145:64910690c574	1542	* @note This API must not be called when the DMA channel is enabled.
AnnaBridge	145:64910690c574	1543	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1544	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1545	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	1546	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	1547	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	1548	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	1549	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	1550	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	1551	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	1552	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	1553	* @param MemoryAddress Between 0 to 0xFFFFFFFF
AnnaBridge	145:64910690c574	1554	* @retval None
AnnaBridge	145:64910690c574	1555	*/
AnnaBridge	145:64910690c574	1556	__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
AnnaBridge	145:64910690c574	1557	{
AnnaBridge	145:64910690c574	1558	WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
AnnaBridge	145:64910690c574	1559	}
AnnaBridge	145:64910690c574	1560
AnnaBridge	145:64910690c574	1561	/**
AnnaBridge	145:64910690c574	1562	* @brief Get the Memory to Memory Source address.
AnnaBridge	145:64910690c574	1563	* @rmtoll PAR PA LL_DMA_GetM2MSrcAddress
AnnaBridge	145:64910690c574	1564	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	145:64910690c574	1565	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1566	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1567	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	1568	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	1569	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	1570	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	1571	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	1572	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	1573	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	1574	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	1575	* @retval Between 0 to 0xFFFFFFFF
AnnaBridge	145:64910690c574	1576	*/
AnnaBridge	145:64910690c574	1577	__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	1578	{
AnnaBridge	145:64910690c574	1579	return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
AnnaBridge	145:64910690c574	1580	}
AnnaBridge	145:64910690c574	1581
AnnaBridge	145:64910690c574	1582	/**
AnnaBridge	145:64910690c574	1583	* @brief Get the Memory to Memory Destination address.
AnnaBridge	145:64910690c574	1584	* @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress
AnnaBridge	145:64910690c574	1585	* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge	145:64910690c574	1586	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1587	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1588	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	1589	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	1590	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	1591	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	1592	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	1593	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	1594	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	1595	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	1596	* @retval Between 0 to 0xFFFFFFFF
AnnaBridge	145:64910690c574	1597	*/
AnnaBridge	145:64910690c574	1598	__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	1599	{
AnnaBridge	145:64910690c574	1600	return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
AnnaBridge	145:64910690c574	1601	}
AnnaBridge	145:64910690c574	1602
AnnaBridge	145:64910690c574	1603	/**
AnnaBridge	145:64910690c574	1604	* @brief Set Memory 1 address (used in case of Double buffer mode).
AnnaBridge	145:64910690c574	1605	* @rmtoll M1AR M1A LL_DMA_SetMemory1Address
AnnaBridge	145:64910690c574	1606	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1607	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1608	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	1609	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	1610	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	1611	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	1612	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	1613	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	1614	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	1615	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	1616	* @param Address Between 0 to 0xFFFFFFFF
AnnaBridge	145:64910690c574	1617	* @retval None
AnnaBridge	145:64910690c574	1618	*/
AnnaBridge	145:64910690c574	1619	__STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
AnnaBridge	145:64910690c574	1620	{
AnnaBridge	145:64910690c574	1621	MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, DMA_SxM1AR_M1A, Address);
AnnaBridge	145:64910690c574	1622	}
AnnaBridge	145:64910690c574	1623
AnnaBridge	145:64910690c574	1624	/**
AnnaBridge	145:64910690c574	1625	* @brief Get Memory 1 address (used in case of Double buffer mode).
AnnaBridge	145:64910690c574	1626	* @rmtoll M1AR M1A LL_DMA_GetMemory1Address
AnnaBridge	145:64910690c574	1627	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1628	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	1629	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	1630	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	1631	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	1632	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	1633	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	1634	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	1635	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	1636	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	1637	* @retval Between 0 to 0xFFFFFFFF
AnnaBridge	145:64910690c574	1638	*/
AnnaBridge	145:64910690c574	1639	__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	1640	{
AnnaBridge	145:64910690c574	1641	return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR);
AnnaBridge	145:64910690c574	1642	}
AnnaBridge	145:64910690c574	1643
AnnaBridge	145:64910690c574	1644	/**
AnnaBridge	145:64910690c574	1645	* @}
AnnaBridge	145:64910690c574	1646	*/
AnnaBridge	145:64910690c574	1647
AnnaBridge	145:64910690c574	1648	/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
AnnaBridge	145:64910690c574	1649	* @{
AnnaBridge	145:64910690c574	1650	*/
AnnaBridge	145:64910690c574	1651
AnnaBridge	145:64910690c574	1652	/**
AnnaBridge	145:64910690c574	1653	* @brief Get Stream 0 half transfer flag.
AnnaBridge	145:64910690c574	1654	* @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0
AnnaBridge	145:64910690c574	1655	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1656	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1657	*/
AnnaBridge	145:64910690c574	1658	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1659	{
AnnaBridge	145:64910690c574	1660	return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0));
AnnaBridge	145:64910690c574	1661	}
AnnaBridge	145:64910690c574	1662
AnnaBridge	145:64910690c574	1663	/**
AnnaBridge	145:64910690c574	1664	* @brief Get Stream 1 half transfer flag.
AnnaBridge	145:64910690c574	1665	* @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1
AnnaBridge	145:64910690c574	1666	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1667	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1668	*/
AnnaBridge	145:64910690c574	1669	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1670	{
AnnaBridge	145:64910690c574	1671	return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1));
AnnaBridge	145:64910690c574	1672	}
AnnaBridge	145:64910690c574	1673
AnnaBridge	145:64910690c574	1674	/**
AnnaBridge	145:64910690c574	1675	* @brief Get Stream 2 half transfer flag.
AnnaBridge	145:64910690c574	1676	* @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2
AnnaBridge	145:64910690c574	1677	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1678	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1679	*/
AnnaBridge	145:64910690c574	1680	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1681	{
AnnaBridge	145:64910690c574	1682	return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2));
AnnaBridge	145:64910690c574	1683	}
AnnaBridge	145:64910690c574	1684
AnnaBridge	145:64910690c574	1685	/**
AnnaBridge	145:64910690c574	1686	* @brief Get Stream 3 half transfer flag.
AnnaBridge	145:64910690c574	1687	* @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3
AnnaBridge	145:64910690c574	1688	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1689	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1690	*/
AnnaBridge	145:64910690c574	1691	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1692	{
AnnaBridge	145:64910690c574	1693	return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3));
AnnaBridge	145:64910690c574	1694	}
AnnaBridge	145:64910690c574	1695
AnnaBridge	145:64910690c574	1696	/**
AnnaBridge	145:64910690c574	1697	* @brief Get Stream 4 half transfer flag.
AnnaBridge	145:64910690c574	1698	* @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4
AnnaBridge	145:64910690c574	1699	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1700	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1701	*/
AnnaBridge	145:64910690c574	1702	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1703	{
AnnaBridge	145:64910690c574	1704	return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4));
AnnaBridge	145:64910690c574	1705	}
AnnaBridge	145:64910690c574	1706
AnnaBridge	145:64910690c574	1707	/**
AnnaBridge	145:64910690c574	1708	* @brief Get Stream 5 half transfer flag.
AnnaBridge	145:64910690c574	1709	* @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5
AnnaBridge	145:64910690c574	1710	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1711	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1712	*/
AnnaBridge	145:64910690c574	1713	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1714	{
AnnaBridge	145:64910690c574	1715	return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5));
AnnaBridge	145:64910690c574	1716	}
AnnaBridge	145:64910690c574	1717
AnnaBridge	145:64910690c574	1718	/**
AnnaBridge	145:64910690c574	1719	* @brief Get Stream 6 half transfer flag.
AnnaBridge	145:64910690c574	1720	* @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6
AnnaBridge	145:64910690c574	1721	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1722	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1723	*/
AnnaBridge	145:64910690c574	1724	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1725	{
AnnaBridge	145:64910690c574	1726	return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6));
AnnaBridge	145:64910690c574	1727	}
AnnaBridge	145:64910690c574	1728
AnnaBridge	145:64910690c574	1729	/**
AnnaBridge	145:64910690c574	1730	* @brief Get Stream 7 half transfer flag.
AnnaBridge	145:64910690c574	1731	* @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7
AnnaBridge	145:64910690c574	1732	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1733	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1734	*/
AnnaBridge	145:64910690c574	1735	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1736	{
AnnaBridge	145:64910690c574	1737	return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7));
AnnaBridge	145:64910690c574	1738	}
AnnaBridge	145:64910690c574	1739
AnnaBridge	145:64910690c574	1740	/**
AnnaBridge	145:64910690c574	1741	* @brief Get Stream 0 transfer complete flag.
AnnaBridge	145:64910690c574	1742	* @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0
AnnaBridge	145:64910690c574	1743	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1744	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1745	*/
AnnaBridge	145:64910690c574	1746	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1747	{
AnnaBridge	145:64910690c574	1748	return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0));
AnnaBridge	145:64910690c574	1749	}
AnnaBridge	145:64910690c574	1750
AnnaBridge	145:64910690c574	1751	/**
AnnaBridge	145:64910690c574	1752	* @brief Get Stream 1 transfer complete flag.
AnnaBridge	145:64910690c574	1753	* @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1
AnnaBridge	145:64910690c574	1754	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1755	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1756	*/
AnnaBridge	145:64910690c574	1757	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1758	{
AnnaBridge	145:64910690c574	1759	return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1));
AnnaBridge	145:64910690c574	1760	}
AnnaBridge	145:64910690c574	1761
AnnaBridge	145:64910690c574	1762	/**
AnnaBridge	145:64910690c574	1763	* @brief Get Stream 2 transfer complete flag.
AnnaBridge	145:64910690c574	1764	* @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2
AnnaBridge	145:64910690c574	1765	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1766	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1767	*/
AnnaBridge	145:64910690c574	1768	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1769	{
AnnaBridge	145:64910690c574	1770	return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2));
AnnaBridge	145:64910690c574	1771	}
AnnaBridge	145:64910690c574	1772
AnnaBridge	145:64910690c574	1773	/**
AnnaBridge	145:64910690c574	1774	* @brief Get Stream 3 transfer complete flag.
AnnaBridge	145:64910690c574	1775	* @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3
AnnaBridge	145:64910690c574	1776	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1777	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1778	*/
AnnaBridge	145:64910690c574	1779	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1780	{
AnnaBridge	145:64910690c574	1781	return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3));
AnnaBridge	145:64910690c574	1782	}
AnnaBridge	145:64910690c574	1783
AnnaBridge	145:64910690c574	1784	/**
AnnaBridge	145:64910690c574	1785	* @brief Get Stream 4 transfer complete flag.
AnnaBridge	145:64910690c574	1786	* @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4
AnnaBridge	145:64910690c574	1787	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1788	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1789	*/
AnnaBridge	145:64910690c574	1790	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1791	{
AnnaBridge	145:64910690c574	1792	return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4));
AnnaBridge	145:64910690c574	1793	}
AnnaBridge	145:64910690c574	1794
AnnaBridge	145:64910690c574	1795	/**
AnnaBridge	145:64910690c574	1796	* @brief Get Stream 5 transfer complete flag.
AnnaBridge	145:64910690c574	1797	* @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5
AnnaBridge	145:64910690c574	1798	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1799	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1800	*/
AnnaBridge	145:64910690c574	1801	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1802	{
AnnaBridge	145:64910690c574	1803	return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5));
AnnaBridge	145:64910690c574	1804	}
AnnaBridge	145:64910690c574	1805
AnnaBridge	145:64910690c574	1806	/**
AnnaBridge	145:64910690c574	1807	* @brief Get Stream 6 transfer complete flag.
AnnaBridge	145:64910690c574	1808	* @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6
AnnaBridge	145:64910690c574	1809	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1810	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1811	*/
AnnaBridge	145:64910690c574	1812	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1813	{
AnnaBridge	145:64910690c574	1814	return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6));
AnnaBridge	145:64910690c574	1815	}
AnnaBridge	145:64910690c574	1816
AnnaBridge	145:64910690c574	1817	/**
AnnaBridge	145:64910690c574	1818	* @brief Get Stream 7 transfer complete flag.
AnnaBridge	145:64910690c574	1819	* @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7
AnnaBridge	145:64910690c574	1820	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1821	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1822	*/
AnnaBridge	145:64910690c574	1823	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1824	{
AnnaBridge	145:64910690c574	1825	return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7));
AnnaBridge	145:64910690c574	1826	}
AnnaBridge	145:64910690c574	1827
AnnaBridge	145:64910690c574	1828	/**
AnnaBridge	145:64910690c574	1829	* @brief Get Stream 0 transfer error flag.
AnnaBridge	145:64910690c574	1830	* @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0
AnnaBridge	145:64910690c574	1831	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1832	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1833	*/
AnnaBridge	145:64910690c574	1834	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1835	{
AnnaBridge	145:64910690c574	1836	return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0));
AnnaBridge	145:64910690c574	1837	}
AnnaBridge	145:64910690c574	1838
AnnaBridge	145:64910690c574	1839	/**
AnnaBridge	145:64910690c574	1840	* @brief Get Stream 1 transfer error flag.
AnnaBridge	145:64910690c574	1841	* @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1
AnnaBridge	145:64910690c574	1842	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1843	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1844	*/
AnnaBridge	145:64910690c574	1845	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1846	{
AnnaBridge	145:64910690c574	1847	return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1));
AnnaBridge	145:64910690c574	1848	}
AnnaBridge	145:64910690c574	1849
AnnaBridge	145:64910690c574	1850	/**
AnnaBridge	145:64910690c574	1851	* @brief Get Stream 2 transfer error flag.
AnnaBridge	145:64910690c574	1852	* @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2
AnnaBridge	145:64910690c574	1853	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1854	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1855	*/
AnnaBridge	145:64910690c574	1856	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1857	{
AnnaBridge	145:64910690c574	1858	return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2));
AnnaBridge	145:64910690c574	1859	}
AnnaBridge	145:64910690c574	1860
AnnaBridge	145:64910690c574	1861	/**
AnnaBridge	145:64910690c574	1862	* @brief Get Stream 3 transfer error flag.
AnnaBridge	145:64910690c574	1863	* @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3
AnnaBridge	145:64910690c574	1864	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1865	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1866	*/
AnnaBridge	145:64910690c574	1867	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1868	{
AnnaBridge	145:64910690c574	1869	return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3));
AnnaBridge	145:64910690c574	1870	}
AnnaBridge	145:64910690c574	1871
AnnaBridge	145:64910690c574	1872	/**
AnnaBridge	145:64910690c574	1873	* @brief Get Stream 4 transfer error flag.
AnnaBridge	145:64910690c574	1874	* @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4
AnnaBridge	145:64910690c574	1875	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1876	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1877	*/
AnnaBridge	145:64910690c574	1878	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1879	{
AnnaBridge	145:64910690c574	1880	return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4));
AnnaBridge	145:64910690c574	1881	}
AnnaBridge	145:64910690c574	1882
AnnaBridge	145:64910690c574	1883	/**
AnnaBridge	145:64910690c574	1884	* @brief Get Stream 5 transfer error flag.
AnnaBridge	145:64910690c574	1885	* @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5
AnnaBridge	145:64910690c574	1886	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1887	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1888	*/
AnnaBridge	145:64910690c574	1889	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1890	{
AnnaBridge	145:64910690c574	1891	return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5));
AnnaBridge	145:64910690c574	1892	}
AnnaBridge	145:64910690c574	1893
AnnaBridge	145:64910690c574	1894	/**
AnnaBridge	145:64910690c574	1895	* @brief Get Stream 6 transfer error flag.
AnnaBridge	145:64910690c574	1896	* @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6
AnnaBridge	145:64910690c574	1897	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1898	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1899	*/
AnnaBridge	145:64910690c574	1900	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1901	{
AnnaBridge	145:64910690c574	1902	return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6));
AnnaBridge	145:64910690c574	1903	}
AnnaBridge	145:64910690c574	1904
AnnaBridge	145:64910690c574	1905	/**
AnnaBridge	145:64910690c574	1906	* @brief Get Stream 7 transfer error flag.
AnnaBridge	145:64910690c574	1907	* @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7
AnnaBridge	145:64910690c574	1908	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1909	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1910	*/
AnnaBridge	145:64910690c574	1911	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1912	{
AnnaBridge	145:64910690c574	1913	return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7));
AnnaBridge	145:64910690c574	1914	}
AnnaBridge	145:64910690c574	1915
AnnaBridge	145:64910690c574	1916	/**
AnnaBridge	145:64910690c574	1917	* @brief Get Stream 0 direct mode error flag.
AnnaBridge	145:64910690c574	1918	* @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0
AnnaBridge	145:64910690c574	1919	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1920	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1921	*/
AnnaBridge	145:64910690c574	1922	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1923	{
AnnaBridge	145:64910690c574	1924	return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0));
AnnaBridge	145:64910690c574	1925	}
AnnaBridge	145:64910690c574	1926
AnnaBridge	145:64910690c574	1927	/**
AnnaBridge	145:64910690c574	1928	* @brief Get Stream 1 direct mode error flag.
AnnaBridge	145:64910690c574	1929	* @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1
AnnaBridge	145:64910690c574	1930	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1931	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1932	*/
AnnaBridge	145:64910690c574	1933	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1934	{
AnnaBridge	145:64910690c574	1935	return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1));
AnnaBridge	145:64910690c574	1936	}
AnnaBridge	145:64910690c574	1937
AnnaBridge	145:64910690c574	1938	/**
AnnaBridge	145:64910690c574	1939	* @brief Get Stream 2 direct mode error flag.
AnnaBridge	145:64910690c574	1940	* @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2
AnnaBridge	145:64910690c574	1941	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1942	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1943	*/
AnnaBridge	145:64910690c574	1944	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1945	{
AnnaBridge	145:64910690c574	1946	return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2));
AnnaBridge	145:64910690c574	1947	}
AnnaBridge	145:64910690c574	1948
AnnaBridge	145:64910690c574	1949	/**
AnnaBridge	145:64910690c574	1950	* @brief Get Stream 3 direct mode error flag.
AnnaBridge	145:64910690c574	1951	* @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3
AnnaBridge	145:64910690c574	1952	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1953	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1954	*/
AnnaBridge	145:64910690c574	1955	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1956	{
AnnaBridge	145:64910690c574	1957	return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3));
AnnaBridge	145:64910690c574	1958	}
AnnaBridge	145:64910690c574	1959
AnnaBridge	145:64910690c574	1960	/**
AnnaBridge	145:64910690c574	1961	* @brief Get Stream 4 direct mode error flag.
AnnaBridge	145:64910690c574	1962	* @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4
AnnaBridge	145:64910690c574	1963	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1964	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1965	*/
AnnaBridge	145:64910690c574	1966	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1967	{
AnnaBridge	145:64910690c574	1968	return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4));
AnnaBridge	145:64910690c574	1969	}
AnnaBridge	145:64910690c574	1970
AnnaBridge	145:64910690c574	1971	/**
AnnaBridge	145:64910690c574	1972	* @brief Get Stream 5 direct mode error flag.
AnnaBridge	145:64910690c574	1973	* @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5
AnnaBridge	145:64910690c574	1974	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1975	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1976	*/
AnnaBridge	145:64910690c574	1977	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1978	{
AnnaBridge	145:64910690c574	1979	return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5));
AnnaBridge	145:64910690c574	1980	}
AnnaBridge	145:64910690c574	1981
AnnaBridge	145:64910690c574	1982	/**
AnnaBridge	145:64910690c574	1983	* @brief Get Stream 6 direct mode error flag.
AnnaBridge	145:64910690c574	1984	* @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6
AnnaBridge	145:64910690c574	1985	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1986	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1987	*/
AnnaBridge	145:64910690c574	1988	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	1989	{
AnnaBridge	145:64910690c574	1990	return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6));
AnnaBridge	145:64910690c574	1991	}
AnnaBridge	145:64910690c574	1992
AnnaBridge	145:64910690c574	1993	/**
AnnaBridge	145:64910690c574	1994	* @brief Get Stream 7 direct mode error flag.
AnnaBridge	145:64910690c574	1995	* @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7
AnnaBridge	145:64910690c574	1996	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	1997	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	1998	*/
AnnaBridge	145:64910690c574	1999	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2000	{
AnnaBridge	145:64910690c574	2001	return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7));
AnnaBridge	145:64910690c574	2002	}
AnnaBridge	145:64910690c574	2003
AnnaBridge	145:64910690c574	2004	/**
AnnaBridge	145:64910690c574	2005	* @brief Get Stream 0 FIFO error flag.
AnnaBridge	145:64910690c574	2006	* @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0
AnnaBridge	145:64910690c574	2007	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2008	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2009	*/
AnnaBridge	145:64910690c574	2010	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2011	{
AnnaBridge	145:64910690c574	2012	return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0));
AnnaBridge	145:64910690c574	2013	}
AnnaBridge	145:64910690c574	2014
AnnaBridge	145:64910690c574	2015	/**
AnnaBridge	145:64910690c574	2016	* @brief Get Stream 1 FIFO error flag.
AnnaBridge	145:64910690c574	2017	* @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1
AnnaBridge	145:64910690c574	2018	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2019	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2020	*/
AnnaBridge	145:64910690c574	2021	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2022	{
AnnaBridge	145:64910690c574	2023	return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1));
AnnaBridge	145:64910690c574	2024	}
AnnaBridge	145:64910690c574	2025
AnnaBridge	145:64910690c574	2026	/**
AnnaBridge	145:64910690c574	2027	* @brief Get Stream 2 FIFO error flag.
AnnaBridge	145:64910690c574	2028	* @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2
AnnaBridge	145:64910690c574	2029	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2030	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2031	*/
AnnaBridge	145:64910690c574	2032	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2033	{
AnnaBridge	145:64910690c574	2034	return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2));
AnnaBridge	145:64910690c574	2035	}
AnnaBridge	145:64910690c574	2036
AnnaBridge	145:64910690c574	2037	/**
AnnaBridge	145:64910690c574	2038	* @brief Get Stream 3 FIFO error flag.
AnnaBridge	145:64910690c574	2039	* @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3
AnnaBridge	145:64910690c574	2040	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2041	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2042	*/
AnnaBridge	145:64910690c574	2043	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2044	{
AnnaBridge	145:64910690c574	2045	return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3));
AnnaBridge	145:64910690c574	2046	}
AnnaBridge	145:64910690c574	2047
AnnaBridge	145:64910690c574	2048	/**
AnnaBridge	145:64910690c574	2049	* @brief Get Stream 4 FIFO error flag.
AnnaBridge	145:64910690c574	2050	* @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4
AnnaBridge	145:64910690c574	2051	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2052	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2053	*/
AnnaBridge	145:64910690c574	2054	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2055	{
AnnaBridge	145:64910690c574	2056	return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4));
AnnaBridge	145:64910690c574	2057	}
AnnaBridge	145:64910690c574	2058
AnnaBridge	145:64910690c574	2059	/**
AnnaBridge	145:64910690c574	2060	* @brief Get Stream 5 FIFO error flag.
AnnaBridge	145:64910690c574	2061	* @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5
AnnaBridge	145:64910690c574	2062	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2063	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2064	*/
AnnaBridge	145:64910690c574	2065	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2066	{
AnnaBridge	145:64910690c574	2067	return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5));
AnnaBridge	145:64910690c574	2068	}
AnnaBridge	145:64910690c574	2069
AnnaBridge	145:64910690c574	2070	/**
AnnaBridge	145:64910690c574	2071	* @brief Get Stream 6 FIFO error flag.
AnnaBridge	145:64910690c574	2072	* @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6
AnnaBridge	145:64910690c574	2073	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2074	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2075	*/
AnnaBridge	145:64910690c574	2076	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2077	{
AnnaBridge	145:64910690c574	2078	return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6));
AnnaBridge	145:64910690c574	2079	}
AnnaBridge	145:64910690c574	2080
AnnaBridge	145:64910690c574	2081	/**
AnnaBridge	145:64910690c574	2082	* @brief Get Stream 7 FIFO error flag.
AnnaBridge	145:64910690c574	2083	* @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7
AnnaBridge	145:64910690c574	2084	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2085	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2086	*/
AnnaBridge	145:64910690c574	2087	__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2088	{
AnnaBridge	145:64910690c574	2089	return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7));
AnnaBridge	145:64910690c574	2090	}
AnnaBridge	145:64910690c574	2091
AnnaBridge	145:64910690c574	2092	/**
AnnaBridge	145:64910690c574	2093	* @brief Clear Stream 0 half transfer flag.
AnnaBridge	145:64910690c574	2094	* @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0
AnnaBridge	145:64910690c574	2095	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2096	* @retval None
AnnaBridge	145:64910690c574	2097	*/
AnnaBridge	145:64910690c574	2098	__STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2099	{
AnnaBridge	145:64910690c574	2100	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF0);
AnnaBridge	145:64910690c574	2101	}
AnnaBridge	145:64910690c574	2102
AnnaBridge	145:64910690c574	2103	/**
AnnaBridge	145:64910690c574	2104	* @brief Clear Stream 1 half transfer flag.
AnnaBridge	145:64910690c574	2105	* @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1
AnnaBridge	145:64910690c574	2106	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2107	* @retval None
AnnaBridge	145:64910690c574	2108	*/
AnnaBridge	145:64910690c574	2109	__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2110	{
AnnaBridge	145:64910690c574	2111	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF1);
AnnaBridge	145:64910690c574	2112	}
AnnaBridge	145:64910690c574	2113
AnnaBridge	145:64910690c574	2114	/**
AnnaBridge	145:64910690c574	2115	* @brief Clear Stream 2 half transfer flag.
AnnaBridge	145:64910690c574	2116	* @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2
AnnaBridge	145:64910690c574	2117	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2118	* @retval None
AnnaBridge	145:64910690c574	2119	*/
AnnaBridge	145:64910690c574	2120	__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2121	{
AnnaBridge	145:64910690c574	2122	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF2);
AnnaBridge	145:64910690c574	2123	}
AnnaBridge	145:64910690c574	2124
AnnaBridge	145:64910690c574	2125	/**
AnnaBridge	145:64910690c574	2126	* @brief Clear Stream 3 half transfer flag.
AnnaBridge	145:64910690c574	2127	* @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3
AnnaBridge	145:64910690c574	2128	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2129	* @retval None
AnnaBridge	145:64910690c574	2130	*/
AnnaBridge	145:64910690c574	2131	__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2132	{
AnnaBridge	145:64910690c574	2133	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF3);
AnnaBridge	145:64910690c574	2134	}
AnnaBridge	145:64910690c574	2135
AnnaBridge	145:64910690c574	2136	/**
AnnaBridge	145:64910690c574	2137	* @brief Clear Stream 4 half transfer flag.
AnnaBridge	145:64910690c574	2138	* @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4
AnnaBridge	145:64910690c574	2139	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2140	* @retval None
AnnaBridge	145:64910690c574	2141	*/
AnnaBridge	145:64910690c574	2142	__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2143	{
AnnaBridge	145:64910690c574	2144	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF4);
AnnaBridge	145:64910690c574	2145	}
AnnaBridge	145:64910690c574	2146
AnnaBridge	145:64910690c574	2147	/**
AnnaBridge	145:64910690c574	2148	* @brief Clear Stream 5 half transfer flag.
AnnaBridge	145:64910690c574	2149	* @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5
AnnaBridge	145:64910690c574	2150	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2151	* @retval None
AnnaBridge	145:64910690c574	2152	*/
AnnaBridge	145:64910690c574	2153	__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2154	{
AnnaBridge	145:64910690c574	2155	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF5);
AnnaBridge	145:64910690c574	2156	}
AnnaBridge	145:64910690c574	2157
AnnaBridge	145:64910690c574	2158	/**
AnnaBridge	145:64910690c574	2159	* @brief Clear Stream 6 half transfer flag.
AnnaBridge	145:64910690c574	2160	* @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6
AnnaBridge	145:64910690c574	2161	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2162	* @retval None
AnnaBridge	145:64910690c574	2163	*/
AnnaBridge	145:64910690c574	2164	__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2165	{
AnnaBridge	145:64910690c574	2166	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF6);
AnnaBridge	145:64910690c574	2167	}
AnnaBridge	145:64910690c574	2168
AnnaBridge	145:64910690c574	2169	/**
AnnaBridge	145:64910690c574	2170	* @brief Clear Stream 7 half transfer flag.
AnnaBridge	145:64910690c574	2171	* @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7
AnnaBridge	145:64910690c574	2172	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2173	* @retval None
AnnaBridge	145:64910690c574	2174	*/
AnnaBridge	145:64910690c574	2175	__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2176	{
AnnaBridge	145:64910690c574	2177	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF7);
AnnaBridge	145:64910690c574	2178	}
AnnaBridge	145:64910690c574	2179
AnnaBridge	145:64910690c574	2180	/**
AnnaBridge	145:64910690c574	2181	* @brief Clear Stream 0 transfer complete flag.
AnnaBridge	145:64910690c574	2182	* @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0
AnnaBridge	145:64910690c574	2183	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2184	* @retval None
AnnaBridge	145:64910690c574	2185	*/
AnnaBridge	145:64910690c574	2186	__STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2187	{
AnnaBridge	145:64910690c574	2188	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF0);
AnnaBridge	145:64910690c574	2189	}
AnnaBridge	145:64910690c574	2190
AnnaBridge	145:64910690c574	2191	/**
AnnaBridge	145:64910690c574	2192	* @brief Clear Stream 1 transfer complete flag.
AnnaBridge	145:64910690c574	2193	* @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1
AnnaBridge	145:64910690c574	2194	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2195	* @retval None
AnnaBridge	145:64910690c574	2196	*/
AnnaBridge	145:64910690c574	2197	__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2198	{
AnnaBridge	145:64910690c574	2199	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF1);
AnnaBridge	145:64910690c574	2200	}
AnnaBridge	145:64910690c574	2201
AnnaBridge	145:64910690c574	2202	/**
AnnaBridge	145:64910690c574	2203	* @brief Clear Stream 2 transfer complete flag.
AnnaBridge	145:64910690c574	2204	* @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2
AnnaBridge	145:64910690c574	2205	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2206	* @retval None
AnnaBridge	145:64910690c574	2207	*/
AnnaBridge	145:64910690c574	2208	__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2209	{
AnnaBridge	145:64910690c574	2210	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF2);
AnnaBridge	145:64910690c574	2211	}
AnnaBridge	145:64910690c574	2212
AnnaBridge	145:64910690c574	2213	/**
AnnaBridge	145:64910690c574	2214	* @brief Clear Stream 3 transfer complete flag.
AnnaBridge	145:64910690c574	2215	* @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3
AnnaBridge	145:64910690c574	2216	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2217	* @retval None
AnnaBridge	145:64910690c574	2218	*/
AnnaBridge	145:64910690c574	2219	__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2220	{
AnnaBridge	145:64910690c574	2221	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF3);
AnnaBridge	145:64910690c574	2222	}
AnnaBridge	145:64910690c574	2223
AnnaBridge	145:64910690c574	2224	/**
AnnaBridge	145:64910690c574	2225	* @brief Clear Stream 4 transfer complete flag.
AnnaBridge	145:64910690c574	2226	* @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4
AnnaBridge	145:64910690c574	2227	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2228	* @retval None
AnnaBridge	145:64910690c574	2229	*/
AnnaBridge	145:64910690c574	2230	__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2231	{
AnnaBridge	145:64910690c574	2232	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF4);
AnnaBridge	145:64910690c574	2233	}
AnnaBridge	145:64910690c574	2234
AnnaBridge	145:64910690c574	2235	/**
AnnaBridge	145:64910690c574	2236	* @brief Clear Stream 5 transfer complete flag.
AnnaBridge	145:64910690c574	2237	* @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5
AnnaBridge	145:64910690c574	2238	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2239	* @retval None
AnnaBridge	145:64910690c574	2240	*/
AnnaBridge	145:64910690c574	2241	__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2242	{
AnnaBridge	145:64910690c574	2243	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF5);
AnnaBridge	145:64910690c574	2244	}
AnnaBridge	145:64910690c574	2245
AnnaBridge	145:64910690c574	2246	/**
AnnaBridge	145:64910690c574	2247	* @brief Clear Stream 6 transfer complete flag.
AnnaBridge	145:64910690c574	2248	* @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6
AnnaBridge	145:64910690c574	2249	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2250	* @retval None
AnnaBridge	145:64910690c574	2251	*/
AnnaBridge	145:64910690c574	2252	__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2253	{
AnnaBridge	145:64910690c574	2254	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF6);
AnnaBridge	145:64910690c574	2255	}
AnnaBridge	145:64910690c574	2256
AnnaBridge	145:64910690c574	2257	/**
AnnaBridge	145:64910690c574	2258	* @brief Clear Stream 7 transfer complete flag.
AnnaBridge	145:64910690c574	2259	* @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7
AnnaBridge	145:64910690c574	2260	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2261	* @retval None
AnnaBridge	145:64910690c574	2262	*/
AnnaBridge	145:64910690c574	2263	__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2264	{
AnnaBridge	145:64910690c574	2265	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF7);
AnnaBridge	145:64910690c574	2266	}
AnnaBridge	145:64910690c574	2267
AnnaBridge	145:64910690c574	2268	/**
AnnaBridge	145:64910690c574	2269	* @brief Clear Stream 0 transfer error flag.
AnnaBridge	145:64910690c574	2270	* @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0
AnnaBridge	145:64910690c574	2271	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2272	* @retval None
AnnaBridge	145:64910690c574	2273	*/
AnnaBridge	145:64910690c574	2274	__STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2275	{
AnnaBridge	145:64910690c574	2276	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF0);
AnnaBridge	145:64910690c574	2277	}
AnnaBridge	145:64910690c574	2278
AnnaBridge	145:64910690c574	2279	/**
AnnaBridge	145:64910690c574	2280	* @brief Clear Stream 1 transfer error flag.
AnnaBridge	145:64910690c574	2281	* @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1
AnnaBridge	145:64910690c574	2282	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2283	* @retval None
AnnaBridge	145:64910690c574	2284	*/
AnnaBridge	145:64910690c574	2285	__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2286	{
AnnaBridge	145:64910690c574	2287	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF1);
AnnaBridge	145:64910690c574	2288	}
AnnaBridge	145:64910690c574	2289
AnnaBridge	145:64910690c574	2290	/**
AnnaBridge	145:64910690c574	2291	* @brief Clear Stream 2 transfer error flag.
AnnaBridge	145:64910690c574	2292	* @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2
AnnaBridge	145:64910690c574	2293	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2294	* @retval None
AnnaBridge	145:64910690c574	2295	*/
AnnaBridge	145:64910690c574	2296	__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2297	{
AnnaBridge	145:64910690c574	2298	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF2);
AnnaBridge	145:64910690c574	2299	}
AnnaBridge	145:64910690c574	2300
AnnaBridge	145:64910690c574	2301	/**
AnnaBridge	145:64910690c574	2302	* @brief Clear Stream 3 transfer error flag.
AnnaBridge	145:64910690c574	2303	* @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3
AnnaBridge	145:64910690c574	2304	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2305	* @retval None
AnnaBridge	145:64910690c574	2306	*/
AnnaBridge	145:64910690c574	2307	__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2308	{
AnnaBridge	145:64910690c574	2309	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF3);
AnnaBridge	145:64910690c574	2310	}
AnnaBridge	145:64910690c574	2311
AnnaBridge	145:64910690c574	2312	/**
AnnaBridge	145:64910690c574	2313	* @brief Clear Stream 4 transfer error flag.
AnnaBridge	145:64910690c574	2314	* @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4
AnnaBridge	145:64910690c574	2315	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2316	* @retval None
AnnaBridge	145:64910690c574	2317	*/
AnnaBridge	145:64910690c574	2318	__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2319	{
AnnaBridge	145:64910690c574	2320	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF4);
AnnaBridge	145:64910690c574	2321	}
AnnaBridge	145:64910690c574	2322
AnnaBridge	145:64910690c574	2323	/**
AnnaBridge	145:64910690c574	2324	* @brief Clear Stream 5 transfer error flag.
AnnaBridge	145:64910690c574	2325	* @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5
AnnaBridge	145:64910690c574	2326	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2327	* @retval None
AnnaBridge	145:64910690c574	2328	*/
AnnaBridge	145:64910690c574	2329	__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2330	{
AnnaBridge	145:64910690c574	2331	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF5);
AnnaBridge	145:64910690c574	2332	}
AnnaBridge	145:64910690c574	2333
AnnaBridge	145:64910690c574	2334	/**
AnnaBridge	145:64910690c574	2335	* @brief Clear Stream 6 transfer error flag.
AnnaBridge	145:64910690c574	2336	* @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6
AnnaBridge	145:64910690c574	2337	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2338	* @retval None
AnnaBridge	145:64910690c574	2339	*/
AnnaBridge	145:64910690c574	2340	__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2341	{
AnnaBridge	145:64910690c574	2342	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF6);
AnnaBridge	145:64910690c574	2343	}
AnnaBridge	145:64910690c574	2344
AnnaBridge	145:64910690c574	2345	/**
AnnaBridge	145:64910690c574	2346	* @brief Clear Stream 7 transfer error flag.
AnnaBridge	145:64910690c574	2347	* @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7
AnnaBridge	145:64910690c574	2348	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2349	* @retval None
AnnaBridge	145:64910690c574	2350	*/
AnnaBridge	145:64910690c574	2351	__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2352	{
AnnaBridge	145:64910690c574	2353	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF7);
AnnaBridge	145:64910690c574	2354	}
AnnaBridge	145:64910690c574	2355
AnnaBridge	145:64910690c574	2356	/**
AnnaBridge	145:64910690c574	2357	* @brief Clear Stream 0 direct mode error flag.
AnnaBridge	145:64910690c574	2358	* @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0
AnnaBridge	145:64910690c574	2359	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2360	* @retval None
AnnaBridge	145:64910690c574	2361	*/
AnnaBridge	145:64910690c574	2362	__STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2363	{
AnnaBridge	145:64910690c574	2364	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF0);
AnnaBridge	145:64910690c574	2365	}
AnnaBridge	145:64910690c574	2366
AnnaBridge	145:64910690c574	2367	/**
AnnaBridge	145:64910690c574	2368	* @brief Clear Stream 1 direct mode error flag.
AnnaBridge	145:64910690c574	2369	* @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1
AnnaBridge	145:64910690c574	2370	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2371	* @retval None
AnnaBridge	145:64910690c574	2372	*/
AnnaBridge	145:64910690c574	2373	__STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2374	{
AnnaBridge	145:64910690c574	2375	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF1);
AnnaBridge	145:64910690c574	2376	}
AnnaBridge	145:64910690c574	2377
AnnaBridge	145:64910690c574	2378	/**
AnnaBridge	145:64910690c574	2379	* @brief Clear Stream 2 direct mode error flag.
AnnaBridge	145:64910690c574	2380	* @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2
AnnaBridge	145:64910690c574	2381	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2382	* @retval None
AnnaBridge	145:64910690c574	2383	*/
AnnaBridge	145:64910690c574	2384	__STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2385	{
AnnaBridge	145:64910690c574	2386	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF2);
AnnaBridge	145:64910690c574	2387	}
AnnaBridge	145:64910690c574	2388
AnnaBridge	145:64910690c574	2389	/**
AnnaBridge	145:64910690c574	2390	* @brief Clear Stream 3 direct mode error flag.
AnnaBridge	145:64910690c574	2391	* @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3
AnnaBridge	145:64910690c574	2392	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2393	* @retval None
AnnaBridge	145:64910690c574	2394	*/
AnnaBridge	145:64910690c574	2395	__STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2396	{
AnnaBridge	145:64910690c574	2397	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF3);
AnnaBridge	145:64910690c574	2398	}
AnnaBridge	145:64910690c574	2399
AnnaBridge	145:64910690c574	2400	/**
AnnaBridge	145:64910690c574	2401	* @brief Clear Stream 4 direct mode error flag.
AnnaBridge	145:64910690c574	2402	* @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4
AnnaBridge	145:64910690c574	2403	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2404	* @retval None
AnnaBridge	145:64910690c574	2405	*/
AnnaBridge	145:64910690c574	2406	__STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2407	{
AnnaBridge	145:64910690c574	2408	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF4);
AnnaBridge	145:64910690c574	2409	}
AnnaBridge	145:64910690c574	2410
AnnaBridge	145:64910690c574	2411	/**
AnnaBridge	145:64910690c574	2412	* @brief Clear Stream 5 direct mode error flag.
AnnaBridge	145:64910690c574	2413	* @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5
AnnaBridge	145:64910690c574	2414	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2415	* @retval None
AnnaBridge	145:64910690c574	2416	*/
AnnaBridge	145:64910690c574	2417	__STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2418	{
AnnaBridge	145:64910690c574	2419	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF5);
AnnaBridge	145:64910690c574	2420	}
AnnaBridge	145:64910690c574	2421
AnnaBridge	145:64910690c574	2422	/**
AnnaBridge	145:64910690c574	2423	* @brief Clear Stream 6 direct mode error flag.
AnnaBridge	145:64910690c574	2424	* @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6
AnnaBridge	145:64910690c574	2425	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2426	* @retval None
AnnaBridge	145:64910690c574	2427	*/
AnnaBridge	145:64910690c574	2428	__STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2429	{
AnnaBridge	145:64910690c574	2430	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF6);
AnnaBridge	145:64910690c574	2431	}
AnnaBridge	145:64910690c574	2432
AnnaBridge	145:64910690c574	2433	/**
AnnaBridge	145:64910690c574	2434	* @brief Clear Stream 7 direct mode error flag.
AnnaBridge	145:64910690c574	2435	* @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7
AnnaBridge	145:64910690c574	2436	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2437	* @retval None
AnnaBridge	145:64910690c574	2438	*/
AnnaBridge	145:64910690c574	2439	__STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2440	{
AnnaBridge	145:64910690c574	2441	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF7);
AnnaBridge	145:64910690c574	2442	}
AnnaBridge	145:64910690c574	2443
AnnaBridge	145:64910690c574	2444	/**
AnnaBridge	145:64910690c574	2445	* @brief Clear Stream 0 FIFO error flag.
AnnaBridge	145:64910690c574	2446	* @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0
AnnaBridge	145:64910690c574	2447	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2448	* @retval None
AnnaBridge	145:64910690c574	2449	*/
AnnaBridge	145:64910690c574	2450	__STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2451	{
AnnaBridge	145:64910690c574	2452	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF0);
AnnaBridge	145:64910690c574	2453	}
AnnaBridge	145:64910690c574	2454
AnnaBridge	145:64910690c574	2455	/**
AnnaBridge	145:64910690c574	2456	* @brief Clear Stream 1 FIFO error flag.
AnnaBridge	145:64910690c574	2457	* @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1
AnnaBridge	145:64910690c574	2458	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2459	* @retval None
AnnaBridge	145:64910690c574	2460	*/
AnnaBridge	145:64910690c574	2461	__STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2462	{
AnnaBridge	145:64910690c574	2463	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF1);
AnnaBridge	145:64910690c574	2464	}
AnnaBridge	145:64910690c574	2465
AnnaBridge	145:64910690c574	2466	/**
AnnaBridge	145:64910690c574	2467	* @brief Clear Stream 2 FIFO error flag.
AnnaBridge	145:64910690c574	2468	* @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2
AnnaBridge	145:64910690c574	2469	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2470	* @retval None
AnnaBridge	145:64910690c574	2471	*/
AnnaBridge	145:64910690c574	2472	__STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2473	{
AnnaBridge	145:64910690c574	2474	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF2);
AnnaBridge	145:64910690c574	2475	}
AnnaBridge	145:64910690c574	2476
AnnaBridge	145:64910690c574	2477	/**
AnnaBridge	145:64910690c574	2478	* @brief Clear Stream 3 FIFO error flag.
AnnaBridge	145:64910690c574	2479	* @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3
AnnaBridge	145:64910690c574	2480	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2481	* @retval None
AnnaBridge	145:64910690c574	2482	*/
AnnaBridge	145:64910690c574	2483	__STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2484	{
AnnaBridge	145:64910690c574	2485	SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF3);
AnnaBridge	145:64910690c574	2486	}
AnnaBridge	145:64910690c574	2487
AnnaBridge	145:64910690c574	2488	/**
AnnaBridge	145:64910690c574	2489	* @brief Clear Stream 4 FIFO error flag.
AnnaBridge	145:64910690c574	2490	* @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4
AnnaBridge	145:64910690c574	2491	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2492	* @retval None
AnnaBridge	145:64910690c574	2493	*/
AnnaBridge	145:64910690c574	2494	__STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2495	{
AnnaBridge	145:64910690c574	2496	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF4);
AnnaBridge	145:64910690c574	2497	}
AnnaBridge	145:64910690c574	2498
AnnaBridge	145:64910690c574	2499	/**
AnnaBridge	145:64910690c574	2500	* @brief Clear Stream 5 FIFO error flag.
AnnaBridge	145:64910690c574	2501	* @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5
AnnaBridge	145:64910690c574	2502	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2503	* @retval None
AnnaBridge	145:64910690c574	2504	*/
AnnaBridge	145:64910690c574	2505	__STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2506	{
AnnaBridge	145:64910690c574	2507	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF5);
AnnaBridge	145:64910690c574	2508	}
AnnaBridge	145:64910690c574	2509
AnnaBridge	145:64910690c574	2510	/**
AnnaBridge	145:64910690c574	2511	* @brief Clear Stream 6 FIFO error flag.
AnnaBridge	145:64910690c574	2512	* @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6
AnnaBridge	145:64910690c574	2513	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2514	* @retval None
AnnaBridge	145:64910690c574	2515	*/
AnnaBridge	145:64910690c574	2516	__STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2517	{
AnnaBridge	145:64910690c574	2518	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF6);
AnnaBridge	145:64910690c574	2519	}
AnnaBridge	145:64910690c574	2520
AnnaBridge	145:64910690c574	2521	/**
AnnaBridge	145:64910690c574	2522	* @brief Clear Stream 7 FIFO error flag.
AnnaBridge	145:64910690c574	2523	* @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7
AnnaBridge	145:64910690c574	2524	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2525	* @retval None
AnnaBridge	145:64910690c574	2526	*/
AnnaBridge	145:64910690c574	2527	__STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx)
AnnaBridge	145:64910690c574	2528	{
AnnaBridge	145:64910690c574	2529	SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF7);
AnnaBridge	145:64910690c574	2530	}
AnnaBridge	145:64910690c574	2531
AnnaBridge	145:64910690c574	2532	/**
AnnaBridge	145:64910690c574	2533	* @}
AnnaBridge	145:64910690c574	2534	*/
AnnaBridge	145:64910690c574	2535
AnnaBridge	145:64910690c574	2536	/** @defgroup DMA_LL_EF_IT_Management IT_Management
AnnaBridge	145:64910690c574	2537	* @{
AnnaBridge	145:64910690c574	2538	*/
AnnaBridge	145:64910690c574	2539
AnnaBridge	145:64910690c574	2540	/**
AnnaBridge	145:64910690c574	2541	* @brief Enable Half transfer interrupt.
AnnaBridge	145:64910690c574	2542	* @rmtoll CR HTIE LL_DMA_EnableIT_HT
AnnaBridge	145:64910690c574	2543	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2544	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2545	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	2546	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	2547	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	2548	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	2549	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	2550	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	2551	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	2552	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	2553	* @retval None
AnnaBridge	145:64910690c574	2554	*/
AnnaBridge	145:64910690c574	2555	__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	2556	{
AnnaBridge	145:64910690c574	2557	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
AnnaBridge	145:64910690c574	2558	}
AnnaBridge	145:64910690c574	2559
AnnaBridge	145:64910690c574	2560	/**
AnnaBridge	145:64910690c574	2561	* @brief Enable Transfer error interrupt.
AnnaBridge	145:64910690c574	2562	* @rmtoll CR TEIE LL_DMA_EnableIT_TE
AnnaBridge	145:64910690c574	2563	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2564	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2565	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	2566	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	2567	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	2568	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	2569	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	2570	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	2571	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	2572	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	2573	* @retval None
AnnaBridge	145:64910690c574	2574	*/
AnnaBridge	145:64910690c574	2575	__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	2576	{
AnnaBridge	145:64910690c574	2577	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
AnnaBridge	145:64910690c574	2578	}
AnnaBridge	145:64910690c574	2579
AnnaBridge	145:64910690c574	2580	/**
AnnaBridge	145:64910690c574	2581	* @brief Enable Transfer complete interrupt.
AnnaBridge	145:64910690c574	2582	* @rmtoll CR TCIE LL_DMA_EnableIT_TC
AnnaBridge	145:64910690c574	2583	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2584	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2585	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	2586	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	2587	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	2588	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	2589	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	2590	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	2591	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	2592	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	2593	* @retval None
AnnaBridge	145:64910690c574	2594	*/
AnnaBridge	145:64910690c574	2595	__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	2596	{
AnnaBridge	145:64910690c574	2597	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
AnnaBridge	145:64910690c574	2598	}
AnnaBridge	145:64910690c574	2599
AnnaBridge	145:64910690c574	2600	/**
AnnaBridge	145:64910690c574	2601	* @brief Enable Direct mode error interrupt.
AnnaBridge	145:64910690c574	2602	* @rmtoll CR DMEIE LL_DMA_EnableIT_DME
AnnaBridge	145:64910690c574	2603	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2604	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2605	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	2606	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	2607	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	2608	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	2609	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	2610	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	2611	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	2612	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	2613	* @retval None
AnnaBridge	145:64910690c574	2614	*/
AnnaBridge	145:64910690c574	2615	__STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	2616	{
AnnaBridge	145:64910690c574	2617	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
AnnaBridge	145:64910690c574	2618	}
AnnaBridge	145:64910690c574	2619
AnnaBridge	145:64910690c574	2620	/**
AnnaBridge	145:64910690c574	2621	* @brief Enable FIFO error interrupt.
AnnaBridge	145:64910690c574	2622	* @rmtoll FCR FEIE LL_DMA_EnableIT_FE
AnnaBridge	145:64910690c574	2623	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2624	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2625	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	2626	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	2627	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	2628	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	2629	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	2630	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	2631	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	2632	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	2633	* @retval None
AnnaBridge	145:64910690c574	2634	*/
AnnaBridge	145:64910690c574	2635	__STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	2636	{
AnnaBridge	145:64910690c574	2637	SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
AnnaBridge	145:64910690c574	2638	}
AnnaBridge	145:64910690c574	2639
AnnaBridge	145:64910690c574	2640	/**
AnnaBridge	145:64910690c574	2641	* @brief Disable Half transfer interrupt.
AnnaBridge	145:64910690c574	2642	* @rmtoll CR HTIE LL_DMA_DisableIT_HT
AnnaBridge	145:64910690c574	2643	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2644	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2645	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	2646	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	2647	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	2648	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	2649	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	2650	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	2651	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	2652	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	2653	* @retval None
AnnaBridge	145:64910690c574	2654	*/
AnnaBridge	145:64910690c574	2655	__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	2656	{
AnnaBridge	145:64910690c574	2657	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
AnnaBridge	145:64910690c574	2658	}
AnnaBridge	145:64910690c574	2659
AnnaBridge	145:64910690c574	2660	/**
AnnaBridge	145:64910690c574	2661	* @brief Disable Transfer error interrupt.
AnnaBridge	145:64910690c574	2662	* @rmtoll CR TEIE LL_DMA_DisableIT_TE
AnnaBridge	145:64910690c574	2663	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2664	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2665	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	2666	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	2667	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	2668	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	2669	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	2670	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	2671	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	2672	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	2673	* @retval None
AnnaBridge	145:64910690c574	2674	*/
AnnaBridge	145:64910690c574	2675	__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	2676	{
AnnaBridge	145:64910690c574	2677	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
AnnaBridge	145:64910690c574	2678	}
AnnaBridge	145:64910690c574	2679
AnnaBridge	145:64910690c574	2680	/**
AnnaBridge	145:64910690c574	2681	* @brief Disable Transfer complete interrupt.
AnnaBridge	145:64910690c574	2682	* @rmtoll CR TCIE LL_DMA_DisableIT_TC
AnnaBridge	145:64910690c574	2683	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2684	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2685	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	2686	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	2687	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	2688	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	2689	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	2690	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	2691	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	2692	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	2693	* @retval None
AnnaBridge	145:64910690c574	2694	*/
AnnaBridge	145:64910690c574	2695	__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	2696	{
AnnaBridge	145:64910690c574	2697	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
AnnaBridge	145:64910690c574	2698	}
AnnaBridge	145:64910690c574	2699
AnnaBridge	145:64910690c574	2700	/**
AnnaBridge	145:64910690c574	2701	* @brief Disable Direct mode error interrupt.
AnnaBridge	145:64910690c574	2702	* @rmtoll CR DMEIE LL_DMA_DisableIT_DME
AnnaBridge	145:64910690c574	2703	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2704	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2705	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	2706	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	2707	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	2708	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	2709	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	2710	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	2711	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	2712	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	2713	* @retval None
AnnaBridge	145:64910690c574	2714	*/
AnnaBridge	145:64910690c574	2715	__STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	2716	{
AnnaBridge	145:64910690c574	2717	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
AnnaBridge	145:64910690c574	2718	}
AnnaBridge	145:64910690c574	2719
AnnaBridge	145:64910690c574	2720	/**
AnnaBridge	145:64910690c574	2721	* @brief Disable FIFO error interrupt.
AnnaBridge	145:64910690c574	2722	* @rmtoll FCR FEIE LL_DMA_DisableIT_FE
AnnaBridge	145:64910690c574	2723	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2724	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2725	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	2726	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	2727	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	2728	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	2729	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	2730	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	2731	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	2732	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	2733	* @retval None
AnnaBridge	145:64910690c574	2734	*/
AnnaBridge	145:64910690c574	2735	__STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	2736	{
AnnaBridge	145:64910690c574	2737	CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
AnnaBridge	145:64910690c574	2738	}
AnnaBridge	145:64910690c574	2739
AnnaBridge	145:64910690c574	2740	/**
AnnaBridge	145:64910690c574	2741	* @brief Check if Half transfer interrup is enabled.
AnnaBridge	145:64910690c574	2742	* @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT
AnnaBridge	145:64910690c574	2743	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2744	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2745	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	2746	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	2747	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	2748	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	2749	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	2750	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	2751	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	2752	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	2753	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2754	*/
AnnaBridge	145:64910690c574	2755	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	2756	{
AnnaBridge	145:64910690c574	2757	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE);
AnnaBridge	145:64910690c574	2758	}
AnnaBridge	145:64910690c574	2759
AnnaBridge	145:64910690c574	2760	/**
AnnaBridge	145:64910690c574	2761	* @brief Check if Transfer error nterrup is enabled.
AnnaBridge	145:64910690c574	2762	* @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE
AnnaBridge	145:64910690c574	2763	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2764	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2765	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	2766	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	2767	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	2768	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	2769	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	2770	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	2771	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	2772	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	2773	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2774	*/
AnnaBridge	145:64910690c574	2775	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	2776	{
AnnaBridge	145:64910690c574	2777	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE);
AnnaBridge	145:64910690c574	2778	}
AnnaBridge	145:64910690c574	2779
AnnaBridge	145:64910690c574	2780	/**
AnnaBridge	145:64910690c574	2781	* @brief Check if Transfer complete interrup is enabled.
AnnaBridge	145:64910690c574	2782	* @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC
AnnaBridge	145:64910690c574	2783	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2784	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2785	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	2786	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	2787	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	2788	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	2789	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	2790	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	2791	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	2792	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	2793	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2794	*/
AnnaBridge	145:64910690c574	2795	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	2796	{
AnnaBridge	145:64910690c574	2797	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE);
AnnaBridge	145:64910690c574	2798	}
AnnaBridge	145:64910690c574	2799
AnnaBridge	145:64910690c574	2800	/**
AnnaBridge	145:64910690c574	2801	* @brief Check if Direct mode error interrupt is enabled.
AnnaBridge	145:64910690c574	2802	* @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME
AnnaBridge	145:64910690c574	2803	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2804	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2805	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	2806	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	2807	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	2808	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	2809	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	2810	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	2811	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	2812	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	2813	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2814	*/
AnnaBridge	145:64910690c574	2815	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	2816	{
AnnaBridge	145:64910690c574	2817	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE);
AnnaBridge	145:64910690c574	2818	}
AnnaBridge	145:64910690c574	2819
AnnaBridge	145:64910690c574	2820	/**
AnnaBridge	145:64910690c574	2821	* @brief Check if FIFO error interrup is enabled.
AnnaBridge	145:64910690c574	2822	* @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE
AnnaBridge	145:64910690c574	2823	* @param DMAx DMAx Instance
AnnaBridge	145:64910690c574	2824	* @param Stream This parameter can be one of the following values:
AnnaBridge	145:64910690c574	2825	* @arg @ref LL_DMA_STREAM_0
AnnaBridge	145:64910690c574	2826	* @arg @ref LL_DMA_STREAM_1
AnnaBridge	145:64910690c574	2827	* @arg @ref LL_DMA_STREAM_2
AnnaBridge	145:64910690c574	2828	* @arg @ref LL_DMA_STREAM_3
AnnaBridge	145:64910690c574	2829	* @arg @ref LL_DMA_STREAM_4
AnnaBridge	145:64910690c574	2830	* @arg @ref LL_DMA_STREAM_5
AnnaBridge	145:64910690c574	2831	* @arg @ref LL_DMA_STREAM_6
AnnaBridge	145:64910690c574	2832	* @arg @ref LL_DMA_STREAM_7
AnnaBridge	145:64910690c574	2833	* @retval State of bit (1 or 0).
AnnaBridge	145:64910690c574	2834	*/
AnnaBridge	145:64910690c574	2835	__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
AnnaBridge	145:64910690c574	2836	{
AnnaBridge	145:64910690c574	2837	return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE);
AnnaBridge	145:64910690c574	2838	}
AnnaBridge	145:64910690c574	2839
AnnaBridge	145:64910690c574	2840	/**
AnnaBridge	145:64910690c574	2841	* @}
AnnaBridge	145:64910690c574	2842	*/
AnnaBridge	145:64910690c574	2843
AnnaBridge	145:64910690c574	2844	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	145:64910690c574	2845	/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	145:64910690c574	2846	* @{
AnnaBridge	145:64910690c574	2847	*/
AnnaBridge	145:64910690c574	2848
AnnaBridge	145:64910690c574	2849	uint32_t LL_DMA_Init(DMA_TypeDef DMAx, uint32_t Stream, LL_DMA_InitTypeDef DMA_InitStruct);
AnnaBridge	145:64910690c574	2850	uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream);
AnnaBridge	145:64910690c574	2851	void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
AnnaBridge	145:64910690c574	2852
AnnaBridge	145:64910690c574	2853	/**
AnnaBridge	145:64910690c574	2854	* @}
AnnaBridge	145:64910690c574	2855	*/
AnnaBridge	145:64910690c574	2856	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	145:64910690c574	2857
AnnaBridge	145:64910690c574	2858	/**
AnnaBridge	145:64910690c574	2859	* @}
AnnaBridge	145:64910690c574	2860	*/
AnnaBridge	145:64910690c574	2861
AnnaBridge	145:64910690c574	2862	/**
AnnaBridge	145:64910690c574	2863	* @}
AnnaBridge	145:64910690c574	2864	*/
AnnaBridge	145:64910690c574	2865
AnnaBridge	145:64910690c574	2866	#endif /* DMA1 \|\| DMA2 */
AnnaBridge	145:64910690c574	2867
AnnaBridge	145:64910690c574	2868	/**
AnnaBridge	145:64910690c574	2869	* @}
AnnaBridge	145:64910690c574	2870	*/
AnnaBridge	145:64910690c574	2871
AnnaBridge	145:64910690c574	2872	#ifdef __cplusplus
AnnaBridge	145:64910690c574	2873	}
AnnaBridge	145:64910690c574	2874	#endif
AnnaBridge	145:64910690c574	2875
AnnaBridge	145:64910690c574	2876	#endif /* __STM32F2xx_LL_DMA_H */
AnnaBridge	145:64910690c574	2877
AnnaBridge	145:64910690c574	2878	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/