mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F207ZG/TOOLCHAIN_ARM_MICRO/stm32f2xx_hal_adc.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file stm32f2xx_hal_adc.h
AnnaBridge 171:3a7713b1edbc 4 * @author MCD Application Team
AnnaBridge 171:3a7713b1edbc 5 * @version V1.2.1
AnnaBridge 171:3a7713b1edbc 6 * @date 14-April-2017
AnnaBridge 171:3a7713b1edbc 7 * @brief Header file of ADC HAL extension module.
AnnaBridge 171:3a7713b1edbc 8 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 9 * @attention
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 171:3a7713b1edbc 12 *
AnnaBridge 171:3a7713b1edbc 13 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 14 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 18 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 19 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 171:3a7713b1edbc 21 * may be used to endorse or promote products derived from this software
AnnaBridge 171:3a7713b1edbc 22 * without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 23 *
AnnaBridge 171:3a7713b1edbc 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 171:3a7713b1edbc 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 171:3a7713b1edbc 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 171:3a7713b1edbc 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 171:3a7713b1edbc 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 171:3a7713b1edbc 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 171:3a7713b1edbc 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 171:3a7713b1edbc 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 34 *
AnnaBridge 171:3a7713b1edbc 35 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 36 */
AnnaBridge 171:3a7713b1edbc 37
AnnaBridge 171:3a7713b1edbc 38 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 171:3a7713b1edbc 39 #ifndef __STM32F2xx_ADC_H
AnnaBridge 171:3a7713b1edbc 40 #define __STM32F2xx_ADC_H
AnnaBridge 171:3a7713b1edbc 41
AnnaBridge 171:3a7713b1edbc 42 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 43 extern "C" {
AnnaBridge 171:3a7713b1edbc 44 #endif
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46 /* Includes ------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 47 #include "stm32f2xx_hal_def.h"
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 /** @addtogroup STM32F2xx_HAL_Driver
AnnaBridge 171:3a7713b1edbc 50 * @{
AnnaBridge 171:3a7713b1edbc 51 */
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 /** @addtogroup ADC
AnnaBridge 171:3a7713b1edbc 54 * @{
AnnaBridge 171:3a7713b1edbc 55 */
AnnaBridge 171:3a7713b1edbc 56
AnnaBridge 171:3a7713b1edbc 57 /* Exported types ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 58 /** @defgroup ADC_Exported_Types ADC Exported Types
AnnaBridge 171:3a7713b1edbc 59 * @{
AnnaBridge 171:3a7713b1edbc 60 */
AnnaBridge 171:3a7713b1edbc 61
AnnaBridge 171:3a7713b1edbc 62 /**
AnnaBridge 171:3a7713b1edbc 63 * @brief Structure definition of ADC and regular group initialization
AnnaBridge 171:3a7713b1edbc 64 * @note Parameters of this structure are shared within 2 scopes:
AnnaBridge 171:3a7713b1edbc 65 * - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.
AnnaBridge 171:3a7713b1edbc 66 * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
AnnaBridge 171:3a7713b1edbc 67 * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
AnnaBridge 171:3a7713b1edbc 68 * ADC state can be either:
AnnaBridge 171:3a7713b1edbc 69 * - For all parameters: ADC disabled
AnnaBridge 171:3a7713b1edbc 70 * - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.
AnnaBridge 171:3a7713b1edbc 71 * - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.
AnnaBridge 171:3a7713b1edbc 72 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
AnnaBridge 171:3a7713b1edbc 73 * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
AnnaBridge 171:3a7713b1edbc 74 */
AnnaBridge 171:3a7713b1edbc 75 typedef struct
AnnaBridge 171:3a7713b1edbc 76 {
AnnaBridge 171:3a7713b1edbc 77 uint32_t ClockPrescaler; /*!< Select ADC clock prescaler. The clock is common for
AnnaBridge 171:3a7713b1edbc 78 all the ADCs.
AnnaBridge 171:3a7713b1edbc 79 This parameter can be a value of @ref ADC_ClockPrescaler */
AnnaBridge 171:3a7713b1edbc 80 uint32_t Resolution; /*!< Configures the ADC resolution.
AnnaBridge 171:3a7713b1edbc 81 This parameter can be a value of @ref ADC_Resolution */
AnnaBridge 171:3a7713b1edbc 82 uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
AnnaBridge 171:3a7713b1edbc 83 or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
AnnaBridge 171:3a7713b1edbc 84 This parameter can be a value of @ref ADC_Data_align */
AnnaBridge 171:3a7713b1edbc 85 uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
AnnaBridge 171:3a7713b1edbc 86 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
AnnaBridge 171:3a7713b1edbc 87 If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
AnnaBridge 171:3a7713b1edbc 88 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
AnnaBridge 171:3a7713b1edbc 89 If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
AnnaBridge 171:3a7713b1edbc 90 Scan direction is upward: from rank1 to rank 'n'.
AnnaBridge 171:3a7713b1edbc 91 This parameter can be set to ENABLE or DISABLE */
AnnaBridge 171:3a7713b1edbc 92 uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
AnnaBridge 171:3a7713b1edbc 93 This parameter can be a value of @ref ADC_EOCSelection.
AnnaBridge 171:3a7713b1edbc 94 Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
AnnaBridge 171:3a7713b1edbc 95 Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
AnnaBridge 171:3a7713b1edbc 96 or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
AnnaBridge 171:3a7713b1edbc 97 Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).
AnnaBridge 171:3a7713b1edbc 98 If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */
AnnaBridge 171:3a7713b1edbc 99 uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
AnnaBridge 171:3a7713b1edbc 100 after the selected trigger occurred (software start or external trigger).
AnnaBridge 171:3a7713b1edbc 101 This parameter can be set to ENABLE or DISABLE. */
AnnaBridge 171:3a7713b1edbc 102 uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
AnnaBridge 171:3a7713b1edbc 103 To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
AnnaBridge 171:3a7713b1edbc 104 This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
AnnaBridge 171:3a7713b1edbc 105 uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
AnnaBridge 171:3a7713b1edbc 106 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
AnnaBridge 171:3a7713b1edbc 107 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
AnnaBridge 171:3a7713b1edbc 108 This parameter can be set to ENABLE or DISABLE. */
AnnaBridge 171:3a7713b1edbc 109 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
AnnaBridge 171:3a7713b1edbc 110 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
AnnaBridge 171:3a7713b1edbc 111 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
AnnaBridge 171:3a7713b1edbc 112 uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
AnnaBridge 171:3a7713b1edbc 113 If set to ADC_SOFTWARE_START, external triggers are disabled.
AnnaBridge 171:3a7713b1edbc 114 If set to external trigger source, triggering is on event rising edge by default.
AnnaBridge 171:3a7713b1edbc 115 This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
AnnaBridge 171:3a7713b1edbc 116 uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
AnnaBridge 171:3a7713b1edbc 117 If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
AnnaBridge 171:3a7713b1edbc 118 This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
AnnaBridge 171:3a7713b1edbc 119 uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
AnnaBridge 171:3a7713b1edbc 120 or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
AnnaBridge 171:3a7713b1edbc 121 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
AnnaBridge 171:3a7713b1edbc 122 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
AnnaBridge 171:3a7713b1edbc 123 This parameter can be set to ENABLE or DISABLE. */
AnnaBridge 171:3a7713b1edbc 124 }ADC_InitTypeDef;
AnnaBridge 171:3a7713b1edbc 125
AnnaBridge 171:3a7713b1edbc 126
AnnaBridge 171:3a7713b1edbc 127
AnnaBridge 171:3a7713b1edbc 128 /**
AnnaBridge 171:3a7713b1edbc 129 * @brief Structure definition of ADC channel for regular group
AnnaBridge 171:3a7713b1edbc 130 * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
AnnaBridge 171:3a7713b1edbc 131 * ADC can be either disabled or enabled without conversion on going on regular group.
AnnaBridge 171:3a7713b1edbc 132 */
AnnaBridge 171:3a7713b1edbc 133 typedef struct
AnnaBridge 171:3a7713b1edbc 134 {
AnnaBridge 171:3a7713b1edbc 135 uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
AnnaBridge 171:3a7713b1edbc 136 This parameter can be a value of @ref ADC_channels */
AnnaBridge 171:3a7713b1edbc 137 uint32_t Rank; /*!< Specifies the rank in the regular group sequencer.
AnnaBridge 171:3a7713b1edbc 138 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
AnnaBridge 171:3a7713b1edbc 139 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
AnnaBridge 171:3a7713b1edbc 140 Unit: ADC clock cycles
AnnaBridge 171:3a7713b1edbc 141 Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
AnnaBridge 171:3a7713b1edbc 142 This parameter can be a value of @ref ADC_sampling_times
AnnaBridge 171:3a7713b1edbc 143 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
AnnaBridge 171:3a7713b1edbc 144 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
AnnaBridge 171:3a7713b1edbc 145 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
AnnaBridge 171:3a7713b1edbc 146 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
AnnaBridge 171:3a7713b1edbc 147 Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
AnnaBridge 171:3a7713b1edbc 148 uint32_t Offset; /*!< Reserved for future use, can be set to 0 */
AnnaBridge 171:3a7713b1edbc 149 }ADC_ChannelConfTypeDef;
AnnaBridge 171:3a7713b1edbc 150
AnnaBridge 171:3a7713b1edbc 151 /**
AnnaBridge 171:3a7713b1edbc 152 * @brief ADC Configuration multi-mode structure definition
AnnaBridge 171:3a7713b1edbc 153 */
AnnaBridge 171:3a7713b1edbc 154 typedef struct
AnnaBridge 171:3a7713b1edbc 155 {
AnnaBridge 171:3a7713b1edbc 156 uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode.
AnnaBridge 171:3a7713b1edbc 157 This parameter can be a value of @ref ADC_analog_watchdog_selection */
AnnaBridge 171:3a7713b1edbc 158 uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
AnnaBridge 171:3a7713b1edbc 159 This parameter must be a 12-bit value. */
AnnaBridge 171:3a7713b1edbc 160 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
AnnaBridge 171:3a7713b1edbc 161 This parameter must be a 12-bit value. */
AnnaBridge 171:3a7713b1edbc 162 uint32_t Channel; /*!< Configures ADC channel for the analog watchdog.
AnnaBridge 171:3a7713b1edbc 163 This parameter has an effect only if watchdog mode is configured on single channel
AnnaBridge 171:3a7713b1edbc 164 This parameter can be a value of @ref ADC_channels */
AnnaBridge 171:3a7713b1edbc 165 uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured
AnnaBridge 171:3a7713b1edbc 166 is interrupt mode or in polling mode.
AnnaBridge 171:3a7713b1edbc 167 This parameter can be set to ENABLE or DISABLE */
AnnaBridge 171:3a7713b1edbc 168 uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
AnnaBridge 171:3a7713b1edbc 169 }ADC_AnalogWDGConfTypeDef;
AnnaBridge 171:3a7713b1edbc 170
AnnaBridge 171:3a7713b1edbc 171 /**
AnnaBridge 171:3a7713b1edbc 172 * @brief HAL ADC state machine: ADC states definition (bitfields)
AnnaBridge 171:3a7713b1edbc 173 */
AnnaBridge 171:3a7713b1edbc 174 /* States of ADC global scope */
AnnaBridge 171:3a7713b1edbc 175 #define HAL_ADC_STATE_RESET 0x00000000U /*!< ADC not yet initialized or disabled */
AnnaBridge 171:3a7713b1edbc 176 #define HAL_ADC_STATE_READY 0x00000001U /*!< ADC peripheral ready for use */
AnnaBridge 171:3a7713b1edbc 177 #define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U /*!< ADC is busy to internal process (initialization, calibration) */
AnnaBridge 171:3a7713b1edbc 178 #define HAL_ADC_STATE_TIMEOUT 0x00000004U /*!< TimeOut occurrence */
AnnaBridge 171:3a7713b1edbc 179
AnnaBridge 171:3a7713b1edbc 180 /* States of ADC errors */
AnnaBridge 171:3a7713b1edbc 181 #define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U /*!< Internal error occurrence */
AnnaBridge 171:3a7713b1edbc 182 #define HAL_ADC_STATE_ERROR_CONFIG 0x00000020U /*!< Configuration error occurrence */
AnnaBridge 171:3a7713b1edbc 183 #define HAL_ADC_STATE_ERROR_DMA 0x00000040U /*!< DMA error occurrence */
AnnaBridge 171:3a7713b1edbc 184
AnnaBridge 171:3a7713b1edbc 185 /* States of ADC group regular */
AnnaBridge 171:3a7713b1edbc 186 #define HAL_ADC_STATE_REG_BUSY 0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
AnnaBridge 171:3a7713b1edbc 187 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
AnnaBridge 171:3a7713b1edbc 188 #define HAL_ADC_STATE_REG_EOC 0x00000200U /*!< Conversion data available on group regular */
AnnaBridge 171:3a7713b1edbc 189 #define HAL_ADC_STATE_REG_OVR 0x00000400U /*!< Overrun occurrence */
AnnaBridge 171:3a7713b1edbc 190
AnnaBridge 171:3a7713b1edbc 191 /* States of ADC group injected */
AnnaBridge 171:3a7713b1edbc 192 #define HAL_ADC_STATE_INJ_BUSY 0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
AnnaBridge 171:3a7713b1edbc 193 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
AnnaBridge 171:3a7713b1edbc 194 #define HAL_ADC_STATE_INJ_EOC 0x00002000U /*!< Conversion data available on group injected */
AnnaBridge 171:3a7713b1edbc 195
AnnaBridge 171:3a7713b1edbc 196 /* States of ADC analog watchdogs */
AnnaBridge 171:3a7713b1edbc 197 #define HAL_ADC_STATE_AWD1 0x00010000U /*!< Out-of-window occurrence of analog watchdog 1 */
AnnaBridge 171:3a7713b1edbc 198
AnnaBridge 171:3a7713b1edbc 199 /**
AnnaBridge 171:3a7713b1edbc 200 * @brief ADC handle Structure definition
AnnaBridge 171:3a7713b1edbc 201 */
AnnaBridge 171:3a7713b1edbc 202 typedef struct
AnnaBridge 171:3a7713b1edbc 203 {
AnnaBridge 171:3a7713b1edbc 204 ADC_TypeDef *Instance; /*!< Register base address */
AnnaBridge 171:3a7713b1edbc 205
AnnaBridge 171:3a7713b1edbc 206 ADC_InitTypeDef Init; /*!< ADC required parameters */
AnnaBridge 171:3a7713b1edbc 207
AnnaBridge 171:3a7713b1edbc 208 __IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */
AnnaBridge 171:3a7713b1edbc 209
AnnaBridge 171:3a7713b1edbc 210 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
AnnaBridge 171:3a7713b1edbc 211
AnnaBridge 171:3a7713b1edbc 212 HAL_LockTypeDef Lock; /*!< ADC locking object */
AnnaBridge 171:3a7713b1edbc 213
AnnaBridge 171:3a7713b1edbc 214 __IO uint32_t State; /*!< ADC communication state */
AnnaBridge 171:3a7713b1edbc 215
AnnaBridge 171:3a7713b1edbc 216 __IO uint32_t ErrorCode; /*!< ADC Error code */
AnnaBridge 171:3a7713b1edbc 217 }ADC_HandleTypeDef;
AnnaBridge 171:3a7713b1edbc 218 /**
AnnaBridge 171:3a7713b1edbc 219 * @}
AnnaBridge 171:3a7713b1edbc 220 */
AnnaBridge 171:3a7713b1edbc 221
AnnaBridge 171:3a7713b1edbc 222 /* Exported constants --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 223 /** @defgroup ADC_Exported_Constants ADC Exported Constants
AnnaBridge 171:3a7713b1edbc 224 * @{
AnnaBridge 171:3a7713b1edbc 225 */
AnnaBridge 171:3a7713b1edbc 226
AnnaBridge 171:3a7713b1edbc 227 /** @defgroup ADC_Error_Code ADC Error Code
AnnaBridge 171:3a7713b1edbc 228 * @{
AnnaBridge 171:3a7713b1edbc 229 */
AnnaBridge 171:3a7713b1edbc 230 #define HAL_ADC_ERROR_NONE 0x00U /*!< No error */
AnnaBridge 171:3a7713b1edbc 231 #define HAL_ADC_ERROR_INTERNAL 0x01U /*!< ADC IP internal error: if problem of clocking,
AnnaBridge 171:3a7713b1edbc 232 enable/disable, erroneous state */
AnnaBridge 171:3a7713b1edbc 233 #define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error */
AnnaBridge 171:3a7713b1edbc 234 #define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error */
AnnaBridge 171:3a7713b1edbc 235 /**
AnnaBridge 171:3a7713b1edbc 236 * @}
AnnaBridge 171:3a7713b1edbc 237 */
AnnaBridge 171:3a7713b1edbc 238
AnnaBridge 171:3a7713b1edbc 239
AnnaBridge 171:3a7713b1edbc 240 /** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
AnnaBridge 171:3a7713b1edbc 241 * @{
AnnaBridge 171:3a7713b1edbc 242 */
AnnaBridge 171:3a7713b1edbc 243 #define ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000U
AnnaBridge 171:3a7713b1edbc 244 #define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)
AnnaBridge 171:3a7713b1edbc 245 #define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)
AnnaBridge 171:3a7713b1edbc 246 #define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)
AnnaBridge 171:3a7713b1edbc 247 /**
AnnaBridge 171:3a7713b1edbc 248 * @}
AnnaBridge 171:3a7713b1edbc 249 */
AnnaBridge 171:3a7713b1edbc 250
AnnaBridge 171:3a7713b1edbc 251 /** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases
AnnaBridge 171:3a7713b1edbc 252 * @{
AnnaBridge 171:3a7713b1edbc 253 */
AnnaBridge 171:3a7713b1edbc 254 #define ADC_TWOSAMPLINGDELAY_5CYCLES 0x00000000U
AnnaBridge 171:3a7713b1edbc 255 #define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)
AnnaBridge 171:3a7713b1edbc 256 #define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)
AnnaBridge 171:3a7713b1edbc 257 #define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
AnnaBridge 171:3a7713b1edbc 258 #define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2)
AnnaBridge 171:3a7713b1edbc 259 #define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
AnnaBridge 171:3a7713b1edbc 260 #define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
AnnaBridge 171:3a7713b1edbc 261 #define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
AnnaBridge 171:3a7713b1edbc 262 #define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3)
AnnaBridge 171:3a7713b1edbc 263 #define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
AnnaBridge 171:3a7713b1edbc 264 #define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
AnnaBridge 171:3a7713b1edbc 265 #define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
AnnaBridge 171:3a7713b1edbc 266 #define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
AnnaBridge 171:3a7713b1edbc 267 #define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
AnnaBridge 171:3a7713b1edbc 268 #define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
AnnaBridge 171:3a7713b1edbc 269 #define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)
AnnaBridge 171:3a7713b1edbc 270 /**
AnnaBridge 171:3a7713b1edbc 271 * @}
AnnaBridge 171:3a7713b1edbc 272 */
AnnaBridge 171:3a7713b1edbc 273
AnnaBridge 171:3a7713b1edbc 274 /** @defgroup ADC_Resolution ADC Resolution
AnnaBridge 171:3a7713b1edbc 275 * @{
AnnaBridge 171:3a7713b1edbc 276 */
AnnaBridge 171:3a7713b1edbc 277 #define ADC_RESOLUTION_12B 0x00000000U
AnnaBridge 171:3a7713b1edbc 278 #define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0)
AnnaBridge 171:3a7713b1edbc 279 #define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1)
AnnaBridge 171:3a7713b1edbc 280 #define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES)
AnnaBridge 171:3a7713b1edbc 281 /**
AnnaBridge 171:3a7713b1edbc 282 * @}
AnnaBridge 171:3a7713b1edbc 283 */
AnnaBridge 171:3a7713b1edbc 284
AnnaBridge 171:3a7713b1edbc 285 /** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular
AnnaBridge 171:3a7713b1edbc 286 * @{
AnnaBridge 171:3a7713b1edbc 287 */
AnnaBridge 171:3a7713b1edbc 288 #define ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U
AnnaBridge 171:3a7713b1edbc 289 #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
AnnaBridge 171:3a7713b1edbc 290 #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
AnnaBridge 171:3a7713b1edbc 291 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
AnnaBridge 171:3a7713b1edbc 292 /**
AnnaBridge 171:3a7713b1edbc 293 * @}
AnnaBridge 171:3a7713b1edbc 294 */
AnnaBridge 171:3a7713b1edbc 295
AnnaBridge 171:3a7713b1edbc 296 /** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular
AnnaBridge 171:3a7713b1edbc 297 * @{
AnnaBridge 171:3a7713b1edbc 298 */
AnnaBridge 171:3a7713b1edbc 299 /* Note: Parameter ADC_SOFTWARE_START is a software parameter used for */
AnnaBridge 171:3a7713b1edbc 300 /* compatibility with other STM32 devices. */
AnnaBridge 171:3a7713b1edbc 301 #define ADC_EXTERNALTRIGCONV_T1_CC1 0x00000000U
AnnaBridge 171:3a7713b1edbc 302 #define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)
AnnaBridge 171:3a7713b1edbc 303 #define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)
AnnaBridge 171:3a7713b1edbc 304 #define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
AnnaBridge 171:3a7713b1edbc 305 #define ADC_EXTERNALTRIGCONV_T2_CC3 ((uint32_t)ADC_CR2_EXTSEL_2)
AnnaBridge 171:3a7713b1edbc 306 #define ADC_EXTERNALTRIGCONV_T2_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
AnnaBridge 171:3a7713b1edbc 307 #define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
AnnaBridge 171:3a7713b1edbc 308 #define ADC_EXTERNALTRIGCONV_T3_CC1 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
AnnaBridge 171:3a7713b1edbc 309 #define ADC_EXTERNALTRIGCONV_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_3)
AnnaBridge 171:3a7713b1edbc 310 #define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))
AnnaBridge 171:3a7713b1edbc 311 #define ADC_EXTERNALTRIGCONV_T5_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))
AnnaBridge 171:3a7713b1edbc 312 #define ADC_EXTERNALTRIGCONV_T5_CC2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
AnnaBridge 171:3a7713b1edbc 313 #define ADC_EXTERNALTRIGCONV_T5_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))
AnnaBridge 171:3a7713b1edbc 314 #define ADC_EXTERNALTRIGCONV_T8_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
AnnaBridge 171:3a7713b1edbc 315 #define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
AnnaBridge 171:3a7713b1edbc 316 #define ADC_EXTERNALTRIGCONV_Ext_IT11 ((uint32_t)ADC_CR2_EXTSEL)
AnnaBridge 171:3a7713b1edbc 317 #define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1U)
AnnaBridge 171:3a7713b1edbc 318 /**
AnnaBridge 171:3a7713b1edbc 319 * @}
AnnaBridge 171:3a7713b1edbc 320 */
AnnaBridge 171:3a7713b1edbc 321
AnnaBridge 171:3a7713b1edbc 322 /** @defgroup ADC_Data_align ADC Data Align
AnnaBridge 171:3a7713b1edbc 323 * @{
AnnaBridge 171:3a7713b1edbc 324 */
AnnaBridge 171:3a7713b1edbc 325 #define ADC_DATAALIGN_RIGHT 0x00000000U
AnnaBridge 171:3a7713b1edbc 326 #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
AnnaBridge 171:3a7713b1edbc 327 /**
AnnaBridge 171:3a7713b1edbc 328 * @}
AnnaBridge 171:3a7713b1edbc 329 */
AnnaBridge 171:3a7713b1edbc 330
AnnaBridge 171:3a7713b1edbc 331 /** @defgroup ADC_channels ADC Common Channels
AnnaBridge 171:3a7713b1edbc 332 * @{
AnnaBridge 171:3a7713b1edbc 333 */
AnnaBridge 171:3a7713b1edbc 334 #define ADC_CHANNEL_0 0x00000000U
AnnaBridge 171:3a7713b1edbc 335 #define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0)
AnnaBridge 171:3a7713b1edbc 336 #define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1)
AnnaBridge 171:3a7713b1edbc 337 #define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
AnnaBridge 171:3a7713b1edbc 338 #define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2)
AnnaBridge 171:3a7713b1edbc 339 #define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
AnnaBridge 171:3a7713b1edbc 340 #define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
AnnaBridge 171:3a7713b1edbc 341 #define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
AnnaBridge 171:3a7713b1edbc 342 #define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3)
AnnaBridge 171:3a7713b1edbc 343 #define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))
AnnaBridge 171:3a7713b1edbc 344 #define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))
AnnaBridge 171:3a7713b1edbc 345 #define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
AnnaBridge 171:3a7713b1edbc 346 #define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))
AnnaBridge 171:3a7713b1edbc 347 #define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
AnnaBridge 171:3a7713b1edbc 348 #define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
AnnaBridge 171:3a7713b1edbc 349 #define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
AnnaBridge 171:3a7713b1edbc 350 #define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4)
AnnaBridge 171:3a7713b1edbc 351 #define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
AnnaBridge 171:3a7713b1edbc 352 #define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
AnnaBridge 171:3a7713b1edbc 353
AnnaBridge 171:3a7713b1edbc 354 #define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17)
AnnaBridge 171:3a7713b1edbc 355 #define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)
AnnaBridge 171:3a7713b1edbc 356 /**
AnnaBridge 171:3a7713b1edbc 357 * @}
AnnaBridge 171:3a7713b1edbc 358 */
AnnaBridge 171:3a7713b1edbc 359
AnnaBridge 171:3a7713b1edbc 360 /** @defgroup ADC_sampling_times ADC Sampling Times
AnnaBridge 171:3a7713b1edbc 361 * @{
AnnaBridge 171:3a7713b1edbc 362 */
AnnaBridge 171:3a7713b1edbc 363 #define ADC_SAMPLETIME_3CYCLES 0x00000000U
AnnaBridge 171:3a7713b1edbc 364 #define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0)
AnnaBridge 171:3a7713b1edbc 365 #define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1)
AnnaBridge 171:3a7713b1edbc 366 #define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
AnnaBridge 171:3a7713b1edbc 367 #define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2)
AnnaBridge 171:3a7713b1edbc 368 #define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))
AnnaBridge 171:3a7713b1edbc 369 #define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))
AnnaBridge 171:3a7713b1edbc 370 #define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10)
AnnaBridge 171:3a7713b1edbc 371 /**
AnnaBridge 171:3a7713b1edbc 372 * @}
AnnaBridge 171:3a7713b1edbc 373 */
AnnaBridge 171:3a7713b1edbc 374
AnnaBridge 171:3a7713b1edbc 375 /** @defgroup ADC_EOCSelection ADC EOC Selection
AnnaBridge 171:3a7713b1edbc 376 * @{
AnnaBridge 171:3a7713b1edbc 377 */
AnnaBridge 171:3a7713b1edbc 378 #define ADC_EOC_SEQ_CONV 0x00000000U
AnnaBridge 171:3a7713b1edbc 379 #define ADC_EOC_SINGLE_CONV 0x00000001U
AnnaBridge 171:3a7713b1edbc 380 #define ADC_EOC_SINGLE_SEQ_CONV 0x00000002U /*!< reserved for future use */
AnnaBridge 171:3a7713b1edbc 381 /**
AnnaBridge 171:3a7713b1edbc 382 * @}
AnnaBridge 171:3a7713b1edbc 383 */
AnnaBridge 171:3a7713b1edbc 384
AnnaBridge 171:3a7713b1edbc 385 /** @defgroup ADC_Event_type ADC Event Type
AnnaBridge 171:3a7713b1edbc 386 * @{
AnnaBridge 171:3a7713b1edbc 387 */
AnnaBridge 171:3a7713b1edbc 388 #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
AnnaBridge 171:3a7713b1edbc 389 #define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
AnnaBridge 171:3a7713b1edbc 390 /**
AnnaBridge 171:3a7713b1edbc 391 * @}
AnnaBridge 171:3a7713b1edbc 392 */
AnnaBridge 171:3a7713b1edbc 393
AnnaBridge 171:3a7713b1edbc 394 /** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection
AnnaBridge 171:3a7713b1edbc 395 * @{
AnnaBridge 171:3a7713b1edbc 396 */
AnnaBridge 171:3a7713b1edbc 397 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
AnnaBridge 171:3a7713b1edbc 398 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
AnnaBridge 171:3a7713b1edbc 399 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
AnnaBridge 171:3a7713b1edbc 400 #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
AnnaBridge 171:3a7713b1edbc 401 #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
AnnaBridge 171:3a7713b1edbc 402 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
AnnaBridge 171:3a7713b1edbc 403 #define ADC_ANALOGWATCHDOG_NONE 0x00000000U
AnnaBridge 171:3a7713b1edbc 404 /**
AnnaBridge 171:3a7713b1edbc 405 * @}
AnnaBridge 171:3a7713b1edbc 406 */
AnnaBridge 171:3a7713b1edbc 407
AnnaBridge 171:3a7713b1edbc 408 /** @defgroup ADC_interrupts_definition ADC Interrupts Definition
AnnaBridge 171:3a7713b1edbc 409 * @{
AnnaBridge 171:3a7713b1edbc 410 */
AnnaBridge 171:3a7713b1edbc 411 #define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE)
AnnaBridge 171:3a7713b1edbc 412 #define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE)
AnnaBridge 171:3a7713b1edbc 413 #define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE)
AnnaBridge 171:3a7713b1edbc 414 #define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE)
AnnaBridge 171:3a7713b1edbc 415 /**
AnnaBridge 171:3a7713b1edbc 416 * @}
AnnaBridge 171:3a7713b1edbc 417 */
AnnaBridge 171:3a7713b1edbc 418
AnnaBridge 171:3a7713b1edbc 419 /** @defgroup ADC_flags_definition ADC Flags Definition
AnnaBridge 171:3a7713b1edbc 420 * @{
AnnaBridge 171:3a7713b1edbc 421 */
AnnaBridge 171:3a7713b1edbc 422 #define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD)
AnnaBridge 171:3a7713b1edbc 423 #define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC)
AnnaBridge 171:3a7713b1edbc 424 #define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC)
AnnaBridge 171:3a7713b1edbc 425 #define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT)
AnnaBridge 171:3a7713b1edbc 426 #define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT)
AnnaBridge 171:3a7713b1edbc 427 #define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR)
AnnaBridge 171:3a7713b1edbc 428 /**
AnnaBridge 171:3a7713b1edbc 429 * @}
AnnaBridge 171:3a7713b1edbc 430 */
AnnaBridge 171:3a7713b1edbc 431
AnnaBridge 171:3a7713b1edbc 432 /** @defgroup ADC_channels_type ADC Channels Type
AnnaBridge 171:3a7713b1edbc 433 * @{
AnnaBridge 171:3a7713b1edbc 434 */
AnnaBridge 171:3a7713b1edbc 435 #define ADC_ALL_CHANNELS 0x00000001U
AnnaBridge 171:3a7713b1edbc 436 #define ADC_REGULAR_CHANNELS 0x00000002U /*!< reserved for future use */
AnnaBridge 171:3a7713b1edbc 437 #define ADC_INJECTED_CHANNELS 0x00000003U /*!< reserved for future use */
AnnaBridge 171:3a7713b1edbc 438 /**
AnnaBridge 171:3a7713b1edbc 439 * @}
AnnaBridge 171:3a7713b1edbc 440 */
AnnaBridge 171:3a7713b1edbc 441
AnnaBridge 171:3a7713b1edbc 442 /**
AnnaBridge 171:3a7713b1edbc 443 * @}
AnnaBridge 171:3a7713b1edbc 444 */
AnnaBridge 171:3a7713b1edbc 445
AnnaBridge 171:3a7713b1edbc 446 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 447 /** @defgroup ADC_Exported_Macros ADC Exported Macros
AnnaBridge 171:3a7713b1edbc 448 * @{
AnnaBridge 171:3a7713b1edbc 449 */
AnnaBridge 171:3a7713b1edbc 450
AnnaBridge 171:3a7713b1edbc 451 /** @brief Reset ADC handle state
AnnaBridge 171:3a7713b1edbc 452 * @param __HANDLE__: ADC handle
AnnaBridge 171:3a7713b1edbc 453 * @retval None
AnnaBridge 171:3a7713b1edbc 454 */
AnnaBridge 171:3a7713b1edbc 455 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
AnnaBridge 171:3a7713b1edbc 456
AnnaBridge 171:3a7713b1edbc 457 /**
AnnaBridge 171:3a7713b1edbc 458 * @brief Enable the ADC peripheral.
AnnaBridge 171:3a7713b1edbc 459 * @param __HANDLE__: ADC handle
AnnaBridge 171:3a7713b1edbc 460 * @retval None
AnnaBridge 171:3a7713b1edbc 461 */
AnnaBridge 171:3a7713b1edbc 462 #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON)
AnnaBridge 171:3a7713b1edbc 463
AnnaBridge 171:3a7713b1edbc 464 /**
AnnaBridge 171:3a7713b1edbc 465 * @brief Disable the ADC peripheral.
AnnaBridge 171:3a7713b1edbc 466 * @param __HANDLE__: ADC handle
AnnaBridge 171:3a7713b1edbc 467 * @retval None
AnnaBridge 171:3a7713b1edbc 468 */
AnnaBridge 171:3a7713b1edbc 469 #define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON)
AnnaBridge 171:3a7713b1edbc 470
AnnaBridge 171:3a7713b1edbc 471 /**
AnnaBridge 171:3a7713b1edbc 472 * @brief Enable the ADC end of conversion interrupt.
AnnaBridge 171:3a7713b1edbc 473 * @param __HANDLE__: specifies the ADC Handle.
AnnaBridge 171:3a7713b1edbc 474 * @param __INTERRUPT__: ADC Interrupt.
AnnaBridge 171:3a7713b1edbc 475 * @retval None
AnnaBridge 171:3a7713b1edbc 476 */
AnnaBridge 171:3a7713b1edbc 477 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))
AnnaBridge 171:3a7713b1edbc 478
AnnaBridge 171:3a7713b1edbc 479 /**
AnnaBridge 171:3a7713b1edbc 480 * @brief Disable the ADC end of conversion interrupt.
AnnaBridge 171:3a7713b1edbc 481 * @param __HANDLE__: specifies the ADC Handle.
AnnaBridge 171:3a7713b1edbc 482 * @param __INTERRUPT__: ADC interrupt.
AnnaBridge 171:3a7713b1edbc 483 * @retval None
AnnaBridge 171:3a7713b1edbc 484 */
AnnaBridge 171:3a7713b1edbc 485 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
AnnaBridge 171:3a7713b1edbc 486
AnnaBridge 171:3a7713b1edbc 487 /** @brief Check if the specified ADC interrupt source is enabled or disabled.
AnnaBridge 171:3a7713b1edbc 488 * @param __HANDLE__: specifies the ADC Handle.
AnnaBridge 171:3a7713b1edbc 489 * @param __INTERRUPT__: specifies the ADC interrupt source to check.
AnnaBridge 171:3a7713b1edbc 490 * @retval The new state of __IT__ (TRUE or FALSE).
AnnaBridge 171:3a7713b1edbc 491 */
AnnaBridge 171:3a7713b1edbc 492 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
AnnaBridge 171:3a7713b1edbc 493
AnnaBridge 171:3a7713b1edbc 494 /**
AnnaBridge 171:3a7713b1edbc 495 * @brief Clear the ADC's pending flags.
AnnaBridge 171:3a7713b1edbc 496 * @param __HANDLE__: specifies the ADC Handle.
AnnaBridge 171:3a7713b1edbc 497 * @param __FLAG__: ADC flag.
AnnaBridge 171:3a7713b1edbc 498 * @retval None
AnnaBridge 171:3a7713b1edbc 499 */
AnnaBridge 171:3a7713b1edbc 500 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
AnnaBridge 171:3a7713b1edbc 501
AnnaBridge 171:3a7713b1edbc 502 /**
AnnaBridge 171:3a7713b1edbc 503 * @brief Get the selected ADC's flag status.
AnnaBridge 171:3a7713b1edbc 504 * @param __HANDLE__: specifies the ADC Handle.
AnnaBridge 171:3a7713b1edbc 505 * @param __FLAG__: ADC flag.
AnnaBridge 171:3a7713b1edbc 506 * @retval None
AnnaBridge 171:3a7713b1edbc 507 */
AnnaBridge 171:3a7713b1edbc 508 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
AnnaBridge 171:3a7713b1edbc 509
AnnaBridge 171:3a7713b1edbc 510 /**
AnnaBridge 171:3a7713b1edbc 511 * @}
AnnaBridge 171:3a7713b1edbc 512 */
AnnaBridge 171:3a7713b1edbc 513
AnnaBridge 171:3a7713b1edbc 514 /* Include ADC HAL Extension module */
AnnaBridge 171:3a7713b1edbc 515 #include "stm32f2xx_hal_adc_ex.h"
AnnaBridge 171:3a7713b1edbc 516
AnnaBridge 171:3a7713b1edbc 517 /* Exported functions --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 518 /** @addtogroup ADC_Exported_Functions
AnnaBridge 171:3a7713b1edbc 519 * @{
AnnaBridge 171:3a7713b1edbc 520 */
AnnaBridge 171:3a7713b1edbc 521
AnnaBridge 171:3a7713b1edbc 522 /** @addtogroup ADC_Exported_Functions_Group1
AnnaBridge 171:3a7713b1edbc 523 * @{
AnnaBridge 171:3a7713b1edbc 524 */
AnnaBridge 171:3a7713b1edbc 525 /* Initialization/de-initialization functions ***********************************/
AnnaBridge 171:3a7713b1edbc 526 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 527 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
AnnaBridge 171:3a7713b1edbc 528 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 529 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 530 /**
AnnaBridge 171:3a7713b1edbc 531 * @}
AnnaBridge 171:3a7713b1edbc 532 */
AnnaBridge 171:3a7713b1edbc 533
AnnaBridge 171:3a7713b1edbc 534 /** @addtogroup ADC_Exported_Functions_Group2
AnnaBridge 171:3a7713b1edbc 535 * @{
AnnaBridge 171:3a7713b1edbc 536 */
AnnaBridge 171:3a7713b1edbc 537 /* I/O operation functions ******************************************************/
AnnaBridge 171:3a7713b1edbc 538 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 539 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 540 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
AnnaBridge 171:3a7713b1edbc 541
AnnaBridge 171:3a7713b1edbc 542 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
AnnaBridge 171:3a7713b1edbc 543
AnnaBridge 171:3a7713b1edbc 544 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 545 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 546
AnnaBridge 171:3a7713b1edbc 547 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 548
AnnaBridge 171:3a7713b1edbc 549 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
AnnaBridge 171:3a7713b1edbc 550 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 551
AnnaBridge 171:3a7713b1edbc 552 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 553
AnnaBridge 171:3a7713b1edbc 554 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 555 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 556 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 557 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
AnnaBridge 171:3a7713b1edbc 558 /**
AnnaBridge 171:3a7713b1edbc 559 * @}
AnnaBridge 171:3a7713b1edbc 560 */
AnnaBridge 171:3a7713b1edbc 561
AnnaBridge 171:3a7713b1edbc 562 /** @addtogroup ADC_Exported_Functions_Group3
AnnaBridge 171:3a7713b1edbc 563 * @{
AnnaBridge 171:3a7713b1edbc 564 */
AnnaBridge 171:3a7713b1edbc 565 /* Peripheral Control functions *************************************************/
AnnaBridge 171:3a7713b1edbc 566 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
AnnaBridge 171:3a7713b1edbc 567 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
AnnaBridge 171:3a7713b1edbc 568 /**
AnnaBridge 171:3a7713b1edbc 569 * @}
AnnaBridge 171:3a7713b1edbc 570 */
AnnaBridge 171:3a7713b1edbc 571
AnnaBridge 171:3a7713b1edbc 572 /** @addtogroup ADC_Exported_Functions_Group4
AnnaBridge 171:3a7713b1edbc 573 * @{
AnnaBridge 171:3a7713b1edbc 574 */
AnnaBridge 171:3a7713b1edbc 575 /* Peripheral State functions ***************************************************/
AnnaBridge 171:3a7713b1edbc 576 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 577 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
AnnaBridge 171:3a7713b1edbc 578 /**
AnnaBridge 171:3a7713b1edbc 579 * @}
AnnaBridge 171:3a7713b1edbc 580 */
AnnaBridge 171:3a7713b1edbc 581
AnnaBridge 171:3a7713b1edbc 582 /**
AnnaBridge 171:3a7713b1edbc 583 * @}
AnnaBridge 171:3a7713b1edbc 584 */
AnnaBridge 171:3a7713b1edbc 585 /* Private types -------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 586 /* Private variables ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 587 /* Private constants ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 588 /** @defgroup ADC_Private_Constants ADC Private Constants
AnnaBridge 171:3a7713b1edbc 589 * @{
AnnaBridge 171:3a7713b1edbc 590 */
AnnaBridge 171:3a7713b1edbc 591 /* Delay for ADC stabilization time. */
AnnaBridge 171:3a7713b1edbc 592 /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
AnnaBridge 171:3a7713b1edbc 593 /* Unit: us */
AnnaBridge 171:3a7713b1edbc 594 #define ADC_STAB_DELAY_US 3U
AnnaBridge 171:3a7713b1edbc 595 /* Delay for temperature sensor stabilization time. */
AnnaBridge 171:3a7713b1edbc 596 /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
AnnaBridge 171:3a7713b1edbc 597 /* Unit: us */
AnnaBridge 171:3a7713b1edbc 598 #define ADC_TEMPSENSOR_DELAY_US 10U
AnnaBridge 171:3a7713b1edbc 599 /**
AnnaBridge 171:3a7713b1edbc 600 * @}
AnnaBridge 171:3a7713b1edbc 601 */
AnnaBridge 171:3a7713b1edbc 602
AnnaBridge 171:3a7713b1edbc 603 /* Private macro ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 604
AnnaBridge 171:3a7713b1edbc 605 /** @defgroup ADC_Private_Macros ADC Private Macros
AnnaBridge 171:3a7713b1edbc 606 * @{
AnnaBridge 171:3a7713b1edbc 607 */
AnnaBridge 171:3a7713b1edbc 608 /* Macro reserved for internal HAL driver usage, not intended to be used in
AnnaBridge 171:3a7713b1edbc 609 code of final user */
AnnaBridge 171:3a7713b1edbc 610
AnnaBridge 171:3a7713b1edbc 611 /**
AnnaBridge 171:3a7713b1edbc 612 * @brief Verification of ADC state: enabled or disabled
AnnaBridge 171:3a7713b1edbc 613 * @param __HANDLE__: ADC handle
AnnaBridge 171:3a7713b1edbc 614 * @retval SET (ADC enabled) or RESET (ADC disabled)
AnnaBridge 171:3a7713b1edbc 615 */
AnnaBridge 171:3a7713b1edbc 616 #define ADC_IS_ENABLE(__HANDLE__) \
AnnaBridge 171:3a7713b1edbc 617 ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \
AnnaBridge 171:3a7713b1edbc 618 ) ? SET : RESET)
AnnaBridge 171:3a7713b1edbc 619
AnnaBridge 171:3a7713b1edbc 620 /**
AnnaBridge 171:3a7713b1edbc 621 * @brief Test if conversion trigger of regular group is software start
AnnaBridge 171:3a7713b1edbc 622 * or external trigger.
AnnaBridge 171:3a7713b1edbc 623 * @param __HANDLE__: ADC handle
AnnaBridge 171:3a7713b1edbc 624 * @retval SET (software start) or RESET (external trigger)
AnnaBridge 171:3a7713b1edbc 625 */
AnnaBridge 171:3a7713b1edbc 626 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
AnnaBridge 171:3a7713b1edbc 627 (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
AnnaBridge 171:3a7713b1edbc 628
AnnaBridge 171:3a7713b1edbc 629 /**
AnnaBridge 171:3a7713b1edbc 630 * @brief Test if conversion trigger of injected group is software start
AnnaBridge 171:3a7713b1edbc 631 * or external trigger.
AnnaBridge 171:3a7713b1edbc 632 * @param __HANDLE__: ADC handle
AnnaBridge 171:3a7713b1edbc 633 * @retval SET (software start) or RESET (external trigger)
AnnaBridge 171:3a7713b1edbc 634 */
AnnaBridge 171:3a7713b1edbc 635 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
AnnaBridge 171:3a7713b1edbc 636 (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
AnnaBridge 171:3a7713b1edbc 637
AnnaBridge 171:3a7713b1edbc 638 /**
AnnaBridge 171:3a7713b1edbc 639 * @brief Simultaneously clears and sets specific bits of the handle State
AnnaBridge 171:3a7713b1edbc 640 * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
AnnaBridge 171:3a7713b1edbc 641 * the first parameter is the ADC handle State, the second parameter is the
AnnaBridge 171:3a7713b1edbc 642 * bit field to clear, the third and last parameter is the bit field to set.
AnnaBridge 171:3a7713b1edbc 643 * @retval None
AnnaBridge 171:3a7713b1edbc 644 */
AnnaBridge 171:3a7713b1edbc 645 #define ADC_STATE_CLR_SET MODIFY_REG
AnnaBridge 171:3a7713b1edbc 646
AnnaBridge 171:3a7713b1edbc 647 /**
AnnaBridge 171:3a7713b1edbc 648 * @brief Clear ADC error code (set it to error code: "no error")
AnnaBridge 171:3a7713b1edbc 649 * @param __HANDLE__: ADC handle
AnnaBridge 171:3a7713b1edbc 650 * @retval None
AnnaBridge 171:3a7713b1edbc 651 */
AnnaBridge 171:3a7713b1edbc 652 #define ADC_CLEAR_ERRORCODE(__HANDLE__) \
AnnaBridge 171:3a7713b1edbc 653 ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
AnnaBridge 171:3a7713b1edbc 654
AnnaBridge 171:3a7713b1edbc 655
AnnaBridge 171:3a7713b1edbc 656 #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
AnnaBridge 171:3a7713b1edbc 657 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
AnnaBridge 171:3a7713b1edbc 658 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV6) || \
AnnaBridge 171:3a7713b1edbc 659 ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV8))
AnnaBridge 171:3a7713b1edbc 660 #define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
AnnaBridge 171:3a7713b1edbc 661 ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
AnnaBridge 171:3a7713b1edbc 662 ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
AnnaBridge 171:3a7713b1edbc 663 ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
AnnaBridge 171:3a7713b1edbc 664 ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
AnnaBridge 171:3a7713b1edbc 665 ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
AnnaBridge 171:3a7713b1edbc 666 ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
AnnaBridge 171:3a7713b1edbc 667 ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
AnnaBridge 171:3a7713b1edbc 668 ((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
AnnaBridge 171:3a7713b1edbc 669 ((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
AnnaBridge 171:3a7713b1edbc 670 ((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
AnnaBridge 171:3a7713b1edbc 671 ((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
AnnaBridge 171:3a7713b1edbc 672 ((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
AnnaBridge 171:3a7713b1edbc 673 ((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
AnnaBridge 171:3a7713b1edbc 674 ((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
AnnaBridge 171:3a7713b1edbc 675 ((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES))
AnnaBridge 171:3a7713b1edbc 676 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
AnnaBridge 171:3a7713b1edbc 677 ((RESOLUTION) == ADC_RESOLUTION_10B) || \
AnnaBridge 171:3a7713b1edbc 678 ((RESOLUTION) == ADC_RESOLUTION_8B) || \
AnnaBridge 171:3a7713b1edbc 679 ((RESOLUTION) == ADC_RESOLUTION_6B))
AnnaBridge 171:3a7713b1edbc 680 #define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
AnnaBridge 171:3a7713b1edbc 681 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
AnnaBridge 171:3a7713b1edbc 682 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
AnnaBridge 171:3a7713b1edbc 683 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
AnnaBridge 171:3a7713b1edbc 684 #define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
AnnaBridge 171:3a7713b1edbc 685 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
AnnaBridge 171:3a7713b1edbc 686 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
AnnaBridge 171:3a7713b1edbc 687 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
AnnaBridge 171:3a7713b1edbc 688 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
AnnaBridge 171:3a7713b1edbc 689 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC4) || \
AnnaBridge 171:3a7713b1edbc 690 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
AnnaBridge 171:3a7713b1edbc 691 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
AnnaBridge 171:3a7713b1edbc 692 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
AnnaBridge 171:3a7713b1edbc 693 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
AnnaBridge 171:3a7713b1edbc 694 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \
AnnaBridge 171:3a7713b1edbc 695 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC2) || \
AnnaBridge 171:3a7713b1edbc 696 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \
AnnaBridge 171:3a7713b1edbc 697 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \
AnnaBridge 171:3a7713b1edbc 698 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
AnnaBridge 171:3a7713b1edbc 699 ((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11)|| \
AnnaBridge 171:3a7713b1edbc 700 ((REGTRIG) == ADC_SOFTWARE_START))
AnnaBridge 171:3a7713b1edbc 701 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
AnnaBridge 171:3a7713b1edbc 702 ((ALIGN) == ADC_DATAALIGN_LEFT))
AnnaBridge 171:3a7713b1edbc 703 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_3CYCLES) || \
AnnaBridge 171:3a7713b1edbc 704 ((TIME) == ADC_SAMPLETIME_15CYCLES) || \
AnnaBridge 171:3a7713b1edbc 705 ((TIME) == ADC_SAMPLETIME_28CYCLES) || \
AnnaBridge 171:3a7713b1edbc 706 ((TIME) == ADC_SAMPLETIME_56CYCLES) || \
AnnaBridge 171:3a7713b1edbc 707 ((TIME) == ADC_SAMPLETIME_84CYCLES) || \
AnnaBridge 171:3a7713b1edbc 708 ((TIME) == ADC_SAMPLETIME_112CYCLES) || \
AnnaBridge 171:3a7713b1edbc 709 ((TIME) == ADC_SAMPLETIME_144CYCLES) || \
AnnaBridge 171:3a7713b1edbc 710 ((TIME) == ADC_SAMPLETIME_480CYCLES))
AnnaBridge 171:3a7713b1edbc 711 #define IS_ADC_EOCSelection(EOCSelection) (((EOCSelection) == ADC_EOC_SINGLE_CONV) || \
AnnaBridge 171:3a7713b1edbc 712 ((EOCSelection) == ADC_EOC_SEQ_CONV) || \
AnnaBridge 171:3a7713b1edbc 713 ((EOCSelection) == ADC_EOC_SINGLE_SEQ_CONV))
AnnaBridge 171:3a7713b1edbc 714 #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \
AnnaBridge 171:3a7713b1edbc 715 ((EVENT) == ADC_OVR_EVENT))
AnnaBridge 171:3a7713b1edbc 716 #define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
AnnaBridge 171:3a7713b1edbc 717 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
AnnaBridge 171:3a7713b1edbc 718 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
AnnaBridge 171:3a7713b1edbc 719 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
AnnaBridge 171:3a7713b1edbc 720 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
AnnaBridge 171:3a7713b1edbc 721 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \
AnnaBridge 171:3a7713b1edbc 722 ((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE))
AnnaBridge 171:3a7713b1edbc 723 #define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \
AnnaBridge 171:3a7713b1edbc 724 ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \
AnnaBridge 171:3a7713b1edbc 725 ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))
AnnaBridge 171:3a7713b1edbc 726 #define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFFU)
AnnaBridge 171:3a7713b1edbc 727
AnnaBridge 171:3a7713b1edbc 728 #define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= ((uint32_t)16)))
AnnaBridge 171:3a7713b1edbc 729 #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 1U) && ((RANK) <= ((uint32_t)16)))
AnnaBridge 171:3a7713b1edbc 730 #define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))
AnnaBridge 171:3a7713b1edbc 731 #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
AnnaBridge 171:3a7713b1edbc 732 ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= 0x0FFFU)) || \
AnnaBridge 171:3a7713b1edbc 733 (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= 0x03FFU)) || \
AnnaBridge 171:3a7713b1edbc 734 (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= 0x00FFU)) || \
AnnaBridge 171:3a7713b1edbc 735 (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= 0x003FU)))
AnnaBridge 171:3a7713b1edbc 736
AnnaBridge 171:3a7713b1edbc 737 /**
AnnaBridge 171:3a7713b1edbc 738 * @brief Set ADC Regular channel sequence length.
AnnaBridge 171:3a7713b1edbc 739 * @param _NbrOfConversion_: Regular channel sequence length.
AnnaBridge 171:3a7713b1edbc 740 * @retval None
AnnaBridge 171:3a7713b1edbc 741 */
AnnaBridge 171:3a7713b1edbc 742 #define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20U)
AnnaBridge 171:3a7713b1edbc 743
AnnaBridge 171:3a7713b1edbc 744 /**
AnnaBridge 171:3a7713b1edbc 745 * @brief Set the ADC's sample time for channel numbers between 10 and 18.
AnnaBridge 171:3a7713b1edbc 746 * @param _SAMPLETIME_: Sample time parameter.
AnnaBridge 171:3a7713b1edbc 747 * @param _CHANNELNB_: Channel number.
AnnaBridge 171:3a7713b1edbc 748 * @retval None
AnnaBridge 171:3a7713b1edbc 749 */
AnnaBridge 171:3a7713b1edbc 750 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10U)))
AnnaBridge 171:3a7713b1edbc 751
AnnaBridge 171:3a7713b1edbc 752 /**
AnnaBridge 171:3a7713b1edbc 753 * @brief Set the ADC's sample time for channel numbers between 0 and 9.
AnnaBridge 171:3a7713b1edbc 754 * @param _SAMPLETIME_: Sample time parameter.
AnnaBridge 171:3a7713b1edbc 755 * @param _CHANNELNB_: Channel number.
AnnaBridge 171:3a7713b1edbc 756 * @retval None
AnnaBridge 171:3a7713b1edbc 757 */
AnnaBridge 171:3a7713b1edbc 758 #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
AnnaBridge 171:3a7713b1edbc 759
AnnaBridge 171:3a7713b1edbc 760 /**
AnnaBridge 171:3a7713b1edbc 761 * @brief Set the selected regular channel rank for rank between 1 and 6.
AnnaBridge 171:3a7713b1edbc 762 * @param _CHANNELNB_: Channel number.
AnnaBridge 171:3a7713b1edbc 763 * @param _RANKNB_: Rank number.
AnnaBridge 171:3a7713b1edbc 764 * @retval None
AnnaBridge 171:3a7713b1edbc 765 */
AnnaBridge 171:3a7713b1edbc 766 #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 1U)))
AnnaBridge 171:3a7713b1edbc 767
AnnaBridge 171:3a7713b1edbc 768 /**
AnnaBridge 171:3a7713b1edbc 769 * @brief Set the selected regular channel rank for rank between 7 and 12.
AnnaBridge 171:3a7713b1edbc 770 * @param _CHANNELNB_: Channel number.
AnnaBridge 171:3a7713b1edbc 771 * @param _RANKNB_: Rank number.
AnnaBridge 171:3a7713b1edbc 772 * @retval None
AnnaBridge 171:3a7713b1edbc 773 */
AnnaBridge 171:3a7713b1edbc 774 #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 7U)))
AnnaBridge 171:3a7713b1edbc 775
AnnaBridge 171:3a7713b1edbc 776 /**
AnnaBridge 171:3a7713b1edbc 777 * @brief Set the selected regular channel rank for rank between 13 and 16.
AnnaBridge 171:3a7713b1edbc 778 * @param _CHANNELNB_: Channel number.
AnnaBridge 171:3a7713b1edbc 779 * @param _RANKNB_: Rank number.
AnnaBridge 171:3a7713b1edbc 780 * @retval None
AnnaBridge 171:3a7713b1edbc 781 */
AnnaBridge 171:3a7713b1edbc 782 #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 13U)))
AnnaBridge 171:3a7713b1edbc 783
AnnaBridge 171:3a7713b1edbc 784 /**
AnnaBridge 171:3a7713b1edbc 785 * @brief Enable ADC continuous conversion mode.
AnnaBridge 171:3a7713b1edbc 786 * @param _CONTINUOUS_MODE_: Continuous mode.
AnnaBridge 171:3a7713b1edbc 787 * @retval None
AnnaBridge 171:3a7713b1edbc 788 */
AnnaBridge 171:3a7713b1edbc 789 #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1U)
AnnaBridge 171:3a7713b1edbc 790
AnnaBridge 171:3a7713b1edbc 791 /**
AnnaBridge 171:3a7713b1edbc 792 * @brief Configures the number of discontinuous conversions for the regular group channels.
AnnaBridge 171:3a7713b1edbc 793 * @param _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions.
AnnaBridge 171:3a7713b1edbc 794 * @retval None
AnnaBridge 171:3a7713b1edbc 795 */
AnnaBridge 171:3a7713b1edbc 796 #define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1U) << POSITION_VAL(ADC_CR1_DISCNUM))
AnnaBridge 171:3a7713b1edbc 797
AnnaBridge 171:3a7713b1edbc 798 /**
AnnaBridge 171:3a7713b1edbc 799 * @brief Enable ADC scan mode.
AnnaBridge 171:3a7713b1edbc 800 * @param _SCANCONV_MODE_: Scan conversion mode.
AnnaBridge 171:3a7713b1edbc 801 * @retval None
AnnaBridge 171:3a7713b1edbc 802 */
AnnaBridge 171:3a7713b1edbc 803 #define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8U)
AnnaBridge 171:3a7713b1edbc 804
AnnaBridge 171:3a7713b1edbc 805 /**
AnnaBridge 171:3a7713b1edbc 806 * @brief Enable the ADC end of conversion selection.
AnnaBridge 171:3a7713b1edbc 807 * @param _EOCSelection_MODE_: End of conversion selection mode.
AnnaBridge 171:3a7713b1edbc 808 * @retval None
AnnaBridge 171:3a7713b1edbc 809 */
AnnaBridge 171:3a7713b1edbc 810 #define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10U)
AnnaBridge 171:3a7713b1edbc 811
AnnaBridge 171:3a7713b1edbc 812 /**
AnnaBridge 171:3a7713b1edbc 813 * @brief Enable the ADC DMA continuous request.
AnnaBridge 171:3a7713b1edbc 814 * @param _DMAContReq_MODE_: DMA continuous request mode.
AnnaBridge 171:3a7713b1edbc 815 * @retval None
AnnaBridge 171:3a7713b1edbc 816 */
AnnaBridge 171:3a7713b1edbc 817 #define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9U)
AnnaBridge 171:3a7713b1edbc 818
AnnaBridge 171:3a7713b1edbc 819 /**
AnnaBridge 171:3a7713b1edbc 820 * @brief Return resolution bits in CR1 register.
AnnaBridge 171:3a7713b1edbc 821 * @param __HANDLE__: ADC handle
AnnaBridge 171:3a7713b1edbc 822 * @retval None
AnnaBridge 171:3a7713b1edbc 823 */
AnnaBridge 171:3a7713b1edbc 824 #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
AnnaBridge 171:3a7713b1edbc 825
AnnaBridge 171:3a7713b1edbc 826 /**
AnnaBridge 171:3a7713b1edbc 827 * @}
AnnaBridge 171:3a7713b1edbc 828 */
AnnaBridge 171:3a7713b1edbc 829
AnnaBridge 171:3a7713b1edbc 830 /* Private functions ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 831 /** @defgroup ADC_Private_Functions ADC Private Functions
AnnaBridge 171:3a7713b1edbc 832 * @{
AnnaBridge 171:3a7713b1edbc 833 */
AnnaBridge 171:3a7713b1edbc 834
AnnaBridge 171:3a7713b1edbc 835 /**
AnnaBridge 171:3a7713b1edbc 836 * @}
AnnaBridge 171:3a7713b1edbc 837 */
AnnaBridge 171:3a7713b1edbc 838
AnnaBridge 171:3a7713b1edbc 839 /**
AnnaBridge 171:3a7713b1edbc 840 * @}
AnnaBridge 171:3a7713b1edbc 841 */
AnnaBridge 171:3a7713b1edbc 842
AnnaBridge 171:3a7713b1edbc 843 /**
AnnaBridge 171:3a7713b1edbc 844 * @}
AnnaBridge 171:3a7713b1edbc 845 */
AnnaBridge 171:3a7713b1edbc 846
AnnaBridge 171:3a7713b1edbc 847 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 848 }
AnnaBridge 171:3a7713b1edbc 849 #endif
AnnaBridge 171:3a7713b1edbc 850
AnnaBridge 171:3a7713b1edbc 851 #endif /*__STM32F2xx_ADC_H */
AnnaBridge 171:3a7713b1edbc 852
AnnaBridge 171:3a7713b1edbc 853
AnnaBridge 171:3a7713b1edbc 854 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/