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TARGET_NUCLEO_F103RB/TOOLCHAIN_IAR/stm32f1xx_ll_rcc.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	171:3a7713b1edbc	1	/**
AnnaBridge	171:3a7713b1edbc	2	******************************************************************************
AnnaBridge	171:3a7713b1edbc	3	* @file stm32f1xx_ll_rcc.h
AnnaBridge	171:3a7713b1edbc	4	* @author MCD Application Team
AnnaBridge	171:3a7713b1edbc	5	* @brief Header file of RCC LL module.
AnnaBridge	171:3a7713b1edbc	6	******************************************************************************
AnnaBridge	171:3a7713b1edbc	7	* @attention
AnnaBridge	171:3a7713b1edbc	8	*
AnnaBridge	171:3a7713b1edbc	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	171:3a7713b1edbc	10	*
AnnaBridge	171:3a7713b1edbc	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	171:3a7713b1edbc	12	* are permitted provided that the following conditions are met:
AnnaBridge	171:3a7713b1edbc	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	171:3a7713b1edbc	14	* this list of conditions and the following disclaimer.
AnnaBridge	171:3a7713b1edbc	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	171:3a7713b1edbc	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	171:3a7713b1edbc	17	* and/or other materials provided with the distribution.
AnnaBridge	171:3a7713b1edbc	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	171:3a7713b1edbc	19	* may be used to endorse or promote products derived from this software
AnnaBridge	171:3a7713b1edbc	20	* without specific prior written permission.
AnnaBridge	171:3a7713b1edbc	21	*
AnnaBridge	171:3a7713b1edbc	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	171:3a7713b1edbc	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	171:3a7713b1edbc	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	171:3a7713b1edbc	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	171:3a7713b1edbc	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	171:3a7713b1edbc	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	171:3a7713b1edbc	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	171:3a7713b1edbc	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	171:3a7713b1edbc	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	171:3a7713b1edbc	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	171:3a7713b1edbc	32	*
AnnaBridge	171:3a7713b1edbc	33	******************************************************************************
AnnaBridge	171:3a7713b1edbc	34	*/
AnnaBridge	171:3a7713b1edbc	35
AnnaBridge	171:3a7713b1edbc	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	171:3a7713b1edbc	37	#ifndef __STM32F1xx_LL_RCC_H
AnnaBridge	171:3a7713b1edbc	38	#define __STM32F1xx_LL_RCC_H
AnnaBridge	171:3a7713b1edbc	39
AnnaBridge	171:3a7713b1edbc	40	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	41	extern "C" {
AnnaBridge	171:3a7713b1edbc	42	#endif
AnnaBridge	171:3a7713b1edbc	43
AnnaBridge	171:3a7713b1edbc	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	45	#include "stm32f1xx.h"
AnnaBridge	171:3a7713b1edbc	46
AnnaBridge	171:3a7713b1edbc	47	/** @addtogroup STM32F1xx_LL_Driver
AnnaBridge	171:3a7713b1edbc	48	* @{
AnnaBridge	171:3a7713b1edbc	49	*/
AnnaBridge	171:3a7713b1edbc	50
AnnaBridge	171:3a7713b1edbc	51	#if defined(RCC)
AnnaBridge	171:3a7713b1edbc	52
AnnaBridge	171:3a7713b1edbc	53	/** @defgroup RCC_LL RCC
AnnaBridge	171:3a7713b1edbc	54	* @{
AnnaBridge	171:3a7713b1edbc	55	*/
AnnaBridge	171:3a7713b1edbc	56
AnnaBridge	171:3a7713b1edbc	57	/* Private types -------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	58	/* Private variables ---------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	59	/* Private constants ---------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	60	/* Private macros ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	61	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	171:3a7713b1edbc	62	/** @defgroup RCC_LL_Private_Macros RCC Private Macros
AnnaBridge	171:3a7713b1edbc	63	* @{
AnnaBridge	171:3a7713b1edbc	64	*/
AnnaBridge	171:3a7713b1edbc	65	/**
AnnaBridge	171:3a7713b1edbc	66	* @}
AnnaBridge	171:3a7713b1edbc	67	*/
AnnaBridge	171:3a7713b1edbc	68	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	171:3a7713b1edbc	69	/* Exported types ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	70	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	171:3a7713b1edbc	71	/** @defgroup RCC_LL_Exported_Types RCC Exported Types
AnnaBridge	171:3a7713b1edbc	72	* @{
AnnaBridge	171:3a7713b1edbc	73	*/
AnnaBridge	171:3a7713b1edbc	74
AnnaBridge	171:3a7713b1edbc	75	/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
AnnaBridge	171:3a7713b1edbc	76	* @{
AnnaBridge	171:3a7713b1edbc	77	*/
AnnaBridge	171:3a7713b1edbc	78
AnnaBridge	171:3a7713b1edbc	79	/**
AnnaBridge	171:3a7713b1edbc	80	* @brief RCC Clocks Frequency Structure
AnnaBridge	171:3a7713b1edbc	81	*/
AnnaBridge	171:3a7713b1edbc	82	typedef struct
AnnaBridge	171:3a7713b1edbc	83	{
AnnaBridge	171:3a7713b1edbc	84	uint32_t SYSCLK_Frequency; /!< SYSCLK clock frequency /
AnnaBridge	171:3a7713b1edbc	85	uint32_t HCLK_Frequency; /!< HCLK clock frequency /
AnnaBridge	171:3a7713b1edbc	86	uint32_t PCLK1_Frequency; /!< PCLK1 clock frequency /
AnnaBridge	171:3a7713b1edbc	87	uint32_t PCLK2_Frequency; /!< PCLK2 clock frequency /
AnnaBridge	171:3a7713b1edbc	88	} LL_RCC_ClocksTypeDef;
AnnaBridge	171:3a7713b1edbc	89
AnnaBridge	171:3a7713b1edbc	90	/**
AnnaBridge	171:3a7713b1edbc	91	* @}
AnnaBridge	171:3a7713b1edbc	92	*/
AnnaBridge	171:3a7713b1edbc	93
AnnaBridge	171:3a7713b1edbc	94	/**
AnnaBridge	171:3a7713b1edbc	95	* @}
AnnaBridge	171:3a7713b1edbc	96	*/
AnnaBridge	171:3a7713b1edbc	97	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	171:3a7713b1edbc	98
AnnaBridge	171:3a7713b1edbc	99	/* Exported constants --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	100	/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
AnnaBridge	171:3a7713b1edbc	101	* @{
AnnaBridge	171:3a7713b1edbc	102	*/
AnnaBridge	171:3a7713b1edbc	103
AnnaBridge	171:3a7713b1edbc	104	/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
AnnaBridge	171:3a7713b1edbc	105	* @brief Defines used to adapt values of different oscillators
AnnaBridge	171:3a7713b1edbc	106	* @note These values could be modified in the user environment according to
AnnaBridge	171:3a7713b1edbc	107	* HW set-up.
AnnaBridge	171:3a7713b1edbc	108	* @{
AnnaBridge	171:3a7713b1edbc	109	*/
AnnaBridge	171:3a7713b1edbc	110	#if !defined (HSE_VALUE)
AnnaBridge	171:3a7713b1edbc	111	#define HSE_VALUE 8000000U /!< Value of the HSE oscillator in Hz /
AnnaBridge	171:3a7713b1edbc	112	#endif /* HSE_VALUE */
AnnaBridge	171:3a7713b1edbc	113
AnnaBridge	171:3a7713b1edbc	114	#if !defined (HSI_VALUE)
AnnaBridge	171:3a7713b1edbc	115	#define HSI_VALUE 8000000U /!< Value of the HSI oscillator in Hz /
AnnaBridge	171:3a7713b1edbc	116	#endif /* HSI_VALUE */
AnnaBridge	171:3a7713b1edbc	117
AnnaBridge	171:3a7713b1edbc	118	#if !defined (LSE_VALUE)
AnnaBridge	171:3a7713b1edbc	119	#define LSE_VALUE 32768U /!< Value of the LSE oscillator in Hz /
AnnaBridge	171:3a7713b1edbc	120	#endif /* LSE_VALUE */
AnnaBridge	171:3a7713b1edbc	121
AnnaBridge	171:3a7713b1edbc	122	#if !defined (LSI_VALUE)
AnnaBridge	171:3a7713b1edbc	123	#define LSI_VALUE 32000U /!< Value of the LSI oscillator in Hz /
AnnaBridge	171:3a7713b1edbc	124	#endif /* LSI_VALUE */
AnnaBridge	171:3a7713b1edbc	125	/**
AnnaBridge	171:3a7713b1edbc	126	* @}
AnnaBridge	171:3a7713b1edbc	127	*/
AnnaBridge	171:3a7713b1edbc	128
AnnaBridge	171:3a7713b1edbc	129	/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
AnnaBridge	171:3a7713b1edbc	130	* @brief Flags defines which can be used with LL_RCC_WriteReg function
AnnaBridge	171:3a7713b1edbc	131	* @{
AnnaBridge	171:3a7713b1edbc	132	*/
AnnaBridge	171:3a7713b1edbc	133	#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /!< LSI Ready Interrupt Clear /
AnnaBridge	171:3a7713b1edbc	134	#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /!< LSE Ready Interrupt Clear /
AnnaBridge	171:3a7713b1edbc	135	#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /!< HSI Ready Interrupt Clear /
AnnaBridge	171:3a7713b1edbc	136	#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /!< HSE Ready Interrupt Clear /
AnnaBridge	171:3a7713b1edbc	137	#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /!< PLL Ready Interrupt Clear /
AnnaBridge	171:3a7713b1edbc	138	#define LL_RCC_CIR_PLL3RDYC RCC_CIR_PLL3RDYC /!< PLL3(PLLI2S) Ready Interrupt Clear /
AnnaBridge	171:3a7713b1edbc	139	#define LL_RCC_CIR_PLL2RDYC RCC_CIR_PLL2RDYC /!< PLL2 Ready Interrupt Clear /
AnnaBridge	171:3a7713b1edbc	140	#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /!< Clock Security System Interrupt Clear /
AnnaBridge	171:3a7713b1edbc	141	/**
AnnaBridge	171:3a7713b1edbc	142	* @}
AnnaBridge	171:3a7713b1edbc	143	*/
AnnaBridge	171:3a7713b1edbc	144
AnnaBridge	171:3a7713b1edbc	145	/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	171:3a7713b1edbc	146	* @brief Flags defines which can be used with LL_RCC_ReadReg function
AnnaBridge	171:3a7713b1edbc	147	* @{
AnnaBridge	171:3a7713b1edbc	148	*/
AnnaBridge	171:3a7713b1edbc	149	#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /!< LSI Ready Interrupt flag /
AnnaBridge	171:3a7713b1edbc	150	#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /!< LSE Ready Interrupt flag /
AnnaBridge	171:3a7713b1edbc	151	#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /!< HSI Ready Interrupt flag /
AnnaBridge	171:3a7713b1edbc	152	#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /!< HSE Ready Interrupt flag /
AnnaBridge	171:3a7713b1edbc	153	#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /!< PLL Ready Interrupt flag /
AnnaBridge	171:3a7713b1edbc	154	#define LL_RCC_CIR_PLL3RDYF RCC_CIR_PLL3RDYF /!< PLL3(PLLI2S) Ready Interrupt flag /
AnnaBridge	171:3a7713b1edbc	155	#define LL_RCC_CIR_PLL2RDYF RCC_CIR_PLL2RDYF /!< PLL2 Ready Interrupt flag /
AnnaBridge	171:3a7713b1edbc	156	#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /!< Clock Security System Interrupt flag /
AnnaBridge	171:3a7713b1edbc	157	#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /!< PIN reset flag /
AnnaBridge	171:3a7713b1edbc	158	#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /!< POR/PDR reset flag /
AnnaBridge	171:3a7713b1edbc	159	#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /!< Software Reset flag /
AnnaBridge	171:3a7713b1edbc	160	#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /!< Independent Watchdog reset flag /
AnnaBridge	171:3a7713b1edbc	161	#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /!< Window watchdog reset flag /
AnnaBridge	171:3a7713b1edbc	162	#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /!< Low-Power reset flag /
AnnaBridge	171:3a7713b1edbc	163	/**
AnnaBridge	171:3a7713b1edbc	164	* @}
AnnaBridge	171:3a7713b1edbc	165	*/
AnnaBridge	171:3a7713b1edbc	166
AnnaBridge	171:3a7713b1edbc	167	/** @defgroup RCC_LL_EC_IT IT Defines
AnnaBridge	171:3a7713b1edbc	168	* @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
AnnaBridge	171:3a7713b1edbc	169	* @{
AnnaBridge	171:3a7713b1edbc	170	*/
AnnaBridge	171:3a7713b1edbc	171	#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /!< LSI Ready Interrupt Enable /
AnnaBridge	171:3a7713b1edbc	172	#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /!< LSE Ready Interrupt Enable /
AnnaBridge	171:3a7713b1edbc	173	#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /!< HSI Ready Interrupt Enable /
AnnaBridge	171:3a7713b1edbc	174	#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /!< HSE Ready Interrupt Enable /
AnnaBridge	171:3a7713b1edbc	175	#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /!< PLL Ready Interrupt Enable /
AnnaBridge	171:3a7713b1edbc	176	#define LL_RCC_CIR_PLL3RDYIE RCC_CIR_PLL3RDYIE /!< PLL3(PLLI2S) Ready Interrupt Enable /
AnnaBridge	171:3a7713b1edbc	177	#define LL_RCC_CIR_PLL2RDYIE RCC_CIR_PLL2RDYIE /!< PLL2 Ready Interrupt Enable /
AnnaBridge	171:3a7713b1edbc	178	/**
AnnaBridge	171:3a7713b1edbc	179	* @}
AnnaBridge	171:3a7713b1edbc	180	*/
AnnaBridge	171:3a7713b1edbc	181
AnnaBridge	171:3a7713b1edbc	182	#if defined(RCC_CFGR2_PREDIV2)
AnnaBridge	171:3a7713b1edbc	183	/** @defgroup RCC_LL_EC_HSE_PREDIV2_DIV HSE PREDIV2 Division factor
AnnaBridge	171:3a7713b1edbc	184	* @{
AnnaBridge	171:3a7713b1edbc	185	*/
AnnaBridge	171:3a7713b1edbc	186	#define LL_RCC_HSE_PREDIV2_DIV_1 RCC_CFGR2_PREDIV2_DIV1 /!< PREDIV2 input clock not divided /
AnnaBridge	171:3a7713b1edbc	187	#define LL_RCC_HSE_PREDIV2_DIV_2 RCC_CFGR2_PREDIV2_DIV2 /!< PREDIV2 input clock divided by 2 /
AnnaBridge	171:3a7713b1edbc	188	#define LL_RCC_HSE_PREDIV2_DIV_3 RCC_CFGR2_PREDIV2_DIV3 /!< PREDIV2 input clock divided by 3 /
AnnaBridge	171:3a7713b1edbc	189	#define LL_RCC_HSE_PREDIV2_DIV_4 RCC_CFGR2_PREDIV2_DIV4 /!< PREDIV2 input clock divided by 4 /
AnnaBridge	171:3a7713b1edbc	190	#define LL_RCC_HSE_PREDIV2_DIV_5 RCC_CFGR2_PREDIV2_DIV5 /!< PREDIV2 input clock divided by 5 /
AnnaBridge	171:3a7713b1edbc	191	#define LL_RCC_HSE_PREDIV2_DIV_6 RCC_CFGR2_PREDIV2_DIV6 /!< PREDIV2 input clock divided by 6 /
AnnaBridge	171:3a7713b1edbc	192	#define LL_RCC_HSE_PREDIV2_DIV_7 RCC_CFGR2_PREDIV2_DIV7 /!< PREDIV2 input clock divided by 7 /
AnnaBridge	171:3a7713b1edbc	193	#define LL_RCC_HSE_PREDIV2_DIV_8 RCC_CFGR2_PREDIV2_DIV8 /!< PREDIV2 input clock divided by 8 /
AnnaBridge	171:3a7713b1edbc	194	#define LL_RCC_HSE_PREDIV2_DIV_9 RCC_CFGR2_PREDIV2_DIV9 /!< PREDIV2 input clock divided by 9 /
AnnaBridge	171:3a7713b1edbc	195	#define LL_RCC_HSE_PREDIV2_DIV_10 RCC_CFGR2_PREDIV2_DIV10 /!< PREDIV2 input clock divided by 10 /
AnnaBridge	171:3a7713b1edbc	196	#define LL_RCC_HSE_PREDIV2_DIV_11 RCC_CFGR2_PREDIV2_DIV11 /!< PREDIV2 input clock divided by 11 /
AnnaBridge	171:3a7713b1edbc	197	#define LL_RCC_HSE_PREDIV2_DIV_12 RCC_CFGR2_PREDIV2_DIV12 /!< PREDIV2 input clock divided by 12 /
AnnaBridge	171:3a7713b1edbc	198	#define LL_RCC_HSE_PREDIV2_DIV_13 RCC_CFGR2_PREDIV2_DIV13 /!< PREDIV2 input clock divided by 13 /
AnnaBridge	171:3a7713b1edbc	199	#define LL_RCC_HSE_PREDIV2_DIV_14 RCC_CFGR2_PREDIV2_DIV14 /!< PREDIV2 input clock divided by 14 /
AnnaBridge	171:3a7713b1edbc	200	#define LL_RCC_HSE_PREDIV2_DIV_15 RCC_CFGR2_PREDIV2_DIV15 /!< PREDIV2 input clock divided by 15 /
AnnaBridge	171:3a7713b1edbc	201	#define LL_RCC_HSE_PREDIV2_DIV_16 RCC_CFGR2_PREDIV2_DIV16 /!< PREDIV2 input clock divided by 16 /
AnnaBridge	171:3a7713b1edbc	202	/**
AnnaBridge	171:3a7713b1edbc	203	* @}
AnnaBridge	171:3a7713b1edbc	204	*/
AnnaBridge	171:3a7713b1edbc	205
AnnaBridge	171:3a7713b1edbc	206	#endif /* RCC_CFGR2_PREDIV2 */
AnnaBridge	171:3a7713b1edbc	207
AnnaBridge	171:3a7713b1edbc	208	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
AnnaBridge	171:3a7713b1edbc	209	* @{
AnnaBridge	171:3a7713b1edbc	210	*/
AnnaBridge	171:3a7713b1edbc	211	#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selection as system clock /
AnnaBridge	171:3a7713b1edbc	212	#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selection as system clock /
AnnaBridge	171:3a7713b1edbc	213	#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /!< PLL selection as system clock /
AnnaBridge	171:3a7713b1edbc	214	/**
AnnaBridge	171:3a7713b1edbc	215	* @}
AnnaBridge	171:3a7713b1edbc	216	*/
AnnaBridge	171:3a7713b1edbc	217
AnnaBridge	171:3a7713b1edbc	218	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
AnnaBridge	171:3a7713b1edbc	219	* @{
AnnaBridge	171:3a7713b1edbc	220	*/
AnnaBridge	171:3a7713b1edbc	221	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
AnnaBridge	171:3a7713b1edbc	222	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
AnnaBridge	171:3a7713b1edbc	223	#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /!< PLL used as system clock /
AnnaBridge	171:3a7713b1edbc	224	/**
AnnaBridge	171:3a7713b1edbc	225	* @}
AnnaBridge	171:3a7713b1edbc	226	*/
AnnaBridge	171:3a7713b1edbc	227
AnnaBridge	171:3a7713b1edbc	228	/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
AnnaBridge	171:3a7713b1edbc	229	* @{
AnnaBridge	171:3a7713b1edbc	230	*/
AnnaBridge	171:3a7713b1edbc	231	#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
AnnaBridge	171:3a7713b1edbc	232	#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
AnnaBridge	171:3a7713b1edbc	233	#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
AnnaBridge	171:3a7713b1edbc	234	#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
AnnaBridge	171:3a7713b1edbc	235	#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
AnnaBridge	171:3a7713b1edbc	236	#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
AnnaBridge	171:3a7713b1edbc	237	#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
AnnaBridge	171:3a7713b1edbc	238	#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
AnnaBridge	171:3a7713b1edbc	239	#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
AnnaBridge	171:3a7713b1edbc	240	/**
AnnaBridge	171:3a7713b1edbc	241	* @}
AnnaBridge	171:3a7713b1edbc	242	*/
AnnaBridge	171:3a7713b1edbc	243
AnnaBridge	171:3a7713b1edbc	244	/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
AnnaBridge	171:3a7713b1edbc	245	* @{
AnnaBridge	171:3a7713b1edbc	246	*/
AnnaBridge	171:3a7713b1edbc	247	#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
AnnaBridge	171:3a7713b1edbc	248	#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
AnnaBridge	171:3a7713b1edbc	249	#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
AnnaBridge	171:3a7713b1edbc	250	#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
AnnaBridge	171:3a7713b1edbc	251	#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
AnnaBridge	171:3a7713b1edbc	252	/**
AnnaBridge	171:3a7713b1edbc	253	* @}
AnnaBridge	171:3a7713b1edbc	254	*/
AnnaBridge	171:3a7713b1edbc	255
AnnaBridge	171:3a7713b1edbc	256	/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
AnnaBridge	171:3a7713b1edbc	257	* @{
AnnaBridge	171:3a7713b1edbc	258	*/
AnnaBridge	171:3a7713b1edbc	259	#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /!< HCLK not divided /
AnnaBridge	171:3a7713b1edbc	260	#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /!< HCLK divided by 2 /
AnnaBridge	171:3a7713b1edbc	261	#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /!< HCLK divided by 4 /
AnnaBridge	171:3a7713b1edbc	262	#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /!< HCLK divided by 8 /
AnnaBridge	171:3a7713b1edbc	263	#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /!< HCLK divided by 16 /
AnnaBridge	171:3a7713b1edbc	264	/**
AnnaBridge	171:3a7713b1edbc	265	* @}
AnnaBridge	171:3a7713b1edbc	266	*/
AnnaBridge	171:3a7713b1edbc	267
AnnaBridge	171:3a7713b1edbc	268	/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
AnnaBridge	171:3a7713b1edbc	269	* @{
AnnaBridge	171:3a7713b1edbc	270	*/
AnnaBridge	171:3a7713b1edbc	271	#define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /!< MCO output disabled, no clock on MCO /
AnnaBridge	171:3a7713b1edbc	272	#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /!< SYSCLK selection as MCO source /
AnnaBridge	171:3a7713b1edbc	273	#define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /!< HSI selection as MCO source /
AnnaBridge	171:3a7713b1edbc	274	#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /!< HSE selection as MCO source /
AnnaBridge	171:3a7713b1edbc	275	#define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2 /!< PLL clock divided by 2/
AnnaBridge	171:3a7713b1edbc	276	#if defined(RCC_CFGR_MCOSEL_PLL2CLK)
AnnaBridge	171:3a7713b1edbc	277	#define LL_RCC_MCO1SOURCE_PLL2CLK RCC_CFGR_MCOSEL_PLL2 /!< PLL2 clock selected as MCO source/
AnnaBridge	171:3a7713b1edbc	278	#endif /* RCC_CFGR_MCOSEL_PLL2CLK */
AnnaBridge	171:3a7713b1edbc	279	#if defined(RCC_CFGR_MCOSEL_PLL3CLK_DIV2)
AnnaBridge	171:3a7713b1edbc	280	#define LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 RCC_CFGR_MCOSEL_PLL3_DIV2 /!< PLLI2S clock divided by 2 selected as MCO source/
AnnaBridge	171:3a7713b1edbc	281	#endif /* RCC_CFGR_MCOSEL_PLL3CLK_DIV2 */
AnnaBridge	171:3a7713b1edbc	282	#if defined(RCC_CFGR_MCOSEL_EXT_HSE)
AnnaBridge	171:3a7713b1edbc	283	#define LL_RCC_MCO1SOURCE_EXT_HSE RCC_CFGR_MCOSEL_EXT_HSE /!< XT1 external 3-25 MHz oscillator clock selected as MCO source /
AnnaBridge	171:3a7713b1edbc	284	#endif /* RCC_CFGR_MCOSEL_EXT_HSE */
AnnaBridge	171:3a7713b1edbc	285	#if defined(RCC_CFGR_MCOSEL_PLL3CLK)
AnnaBridge	171:3a7713b1edbc	286	#define LL_RCC_MCO1SOURCE_PLLI2SCLK RCC_CFGR_MCOSEL_PLL3CLK /!< PLLI2S clock selected as MCO source /
AnnaBridge	171:3a7713b1edbc	287	#endif /* RCC_CFGR_MCOSEL_PLL3CLK */
AnnaBridge	171:3a7713b1edbc	288	/**
AnnaBridge	171:3a7713b1edbc	289	* @}
AnnaBridge	171:3a7713b1edbc	290	*/
AnnaBridge	171:3a7713b1edbc	291
AnnaBridge	171:3a7713b1edbc	292	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	171:3a7713b1edbc	293	/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
AnnaBridge	171:3a7713b1edbc	294	* @{
AnnaBridge	171:3a7713b1edbc	295	*/
AnnaBridge	171:3a7713b1edbc	296	#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /!< No clock enabled for the peripheral /
AnnaBridge	171:3a7713b1edbc	297	#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /!< Frequency cannot be provided as external clock /
AnnaBridge	171:3a7713b1edbc	298	/**
AnnaBridge	171:3a7713b1edbc	299	* @}
AnnaBridge	171:3a7713b1edbc	300	*/
AnnaBridge	171:3a7713b1edbc	301	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	171:3a7713b1edbc	302
AnnaBridge	171:3a7713b1edbc	303	#if defined(RCC_CFGR2_I2S2SRC)
AnnaBridge	171:3a7713b1edbc	304	/** @defgroup RCC_LL_EC_I2S2CLKSOURCE Peripheral I2S clock source selection
AnnaBridge	171:3a7713b1edbc	305	* @{
AnnaBridge	171:3a7713b1edbc	306	*/
AnnaBridge	171:3a7713b1edbc	307	#define LL_RCC_I2S2_CLKSOURCE_SYSCLK RCC_CFGR2_I2S2SRC /!< System clock (SYSCLK) selected as I2S2 clock entry /
AnnaBridge	171:3a7713b1edbc	308	#define LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO (uint32_t)(RCC_CFGR2_I2S2SRC \| (RCC_CFGR2_I2S2SRC >> 16U)) /!< PLLI2S VCO clock selected as I2S2 clock entry /
AnnaBridge	171:3a7713b1edbc	309	#define LL_RCC_I2S3_CLKSOURCE_SYSCLK RCC_CFGR2_I2S3SRC /!< System clock (SYSCLK) selected as I2S3 clock entry /
AnnaBridge	171:3a7713b1edbc	310	#define LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO (uint32_t)(RCC_CFGR2_I2S3SRC \| (RCC_CFGR2_I2S3SRC >> 16U)) /!< PLLI2S VCO clock selected as I2S3 clock entry /
AnnaBridge	171:3a7713b1edbc	311	/**
AnnaBridge	171:3a7713b1edbc	312	* @}
AnnaBridge	171:3a7713b1edbc	313	*/
AnnaBridge	171:3a7713b1edbc	314	#endif /* RCC_CFGR2_I2S2SRC */
AnnaBridge	171:3a7713b1edbc	315
AnnaBridge	171:3a7713b1edbc	316	#if defined(USB_OTG_FS) \|\| defined(USB)
AnnaBridge	171:3a7713b1edbc	317	/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
AnnaBridge	171:3a7713b1edbc	318	* @{
AnnaBridge	171:3a7713b1edbc	319	*/
AnnaBridge	171:3a7713b1edbc	320	#if defined(RCC_CFGR_USBPRE)
AnnaBridge	171:3a7713b1edbc	321	#define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE /!< PLL clock is not divided /
AnnaBridge	171:3a7713b1edbc	322	#define LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 0x00000000U /!< PLL clock is divided by 1.5 /
AnnaBridge	171:3a7713b1edbc	323	#endif /RCC_CFGR_USBPRE/
AnnaBridge	171:3a7713b1edbc	324	#if defined(RCC_CFGR_OTGFSPRE)
AnnaBridge	171:3a7713b1edbc	325	#define LL_RCC_USB_CLKSOURCE_PLL_DIV_2 RCC_CFGR_OTGFSPRE /!< PLL clock is divided by 2 /
AnnaBridge	171:3a7713b1edbc	326	#define LL_RCC_USB_CLKSOURCE_PLL_DIV_3 0x00000000U /!< PLL clock is divided by 3 /
AnnaBridge	171:3a7713b1edbc	327	#endif /RCC_CFGR_OTGFSPRE/
AnnaBridge	171:3a7713b1edbc	328	/**
AnnaBridge	171:3a7713b1edbc	329	* @}
AnnaBridge	171:3a7713b1edbc	330	*/
AnnaBridge	171:3a7713b1edbc	331	#endif /* USB_OTG_FS \|\| USB */
AnnaBridge	171:3a7713b1edbc	332
AnnaBridge	171:3a7713b1edbc	333	/** @defgroup RCC_LL_EC_ADC_CLKSOURCE_PCLK2 Peripheral ADC clock source selection
AnnaBridge	171:3a7713b1edbc	334	* @{
AnnaBridge	171:3a7713b1edbc	335	*/
AnnaBridge	171:3a7713b1edbc	336	#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 RCC_CFGR_ADCPRE_DIV2 /ADC prescaler PCLK2 divided by 2/
AnnaBridge	171:3a7713b1edbc	337	#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 RCC_CFGR_ADCPRE_DIV4 /ADC prescaler PCLK2 divided by 4/
AnnaBridge	171:3a7713b1edbc	338	#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 RCC_CFGR_ADCPRE_DIV6 /ADC prescaler PCLK2 divided by 6/
AnnaBridge	171:3a7713b1edbc	339	#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 RCC_CFGR_ADCPRE_DIV8 /ADC prescaler PCLK2 divided by 8/
AnnaBridge	171:3a7713b1edbc	340	/**
AnnaBridge	171:3a7713b1edbc	341	* @}
AnnaBridge	171:3a7713b1edbc	342	*/
AnnaBridge	171:3a7713b1edbc	343
AnnaBridge	171:3a7713b1edbc	344	#if defined(RCC_CFGR2_I2S2SRC)
AnnaBridge	171:3a7713b1edbc	345	/** @defgroup RCC_LL_EC_I2S2 Peripheral I2S get clock source
AnnaBridge	171:3a7713b1edbc	346	* @{
AnnaBridge	171:3a7713b1edbc	347	*/
AnnaBridge	171:3a7713b1edbc	348	#define LL_RCC_I2S2_CLKSOURCE RCC_CFGR2_I2S2SRC /!< I2S2 Clock source selection /
AnnaBridge	171:3a7713b1edbc	349	#define LL_RCC_I2S3_CLKSOURCE RCC_CFGR2_I2S3SRC /!< I2S3 Clock source selection /
AnnaBridge	171:3a7713b1edbc	350	/**
AnnaBridge	171:3a7713b1edbc	351	* @}
AnnaBridge	171:3a7713b1edbc	352	*/
AnnaBridge	171:3a7713b1edbc	353
AnnaBridge	171:3a7713b1edbc	354	#endif /* RCC_CFGR2_I2S2SRC */
AnnaBridge	171:3a7713b1edbc	355
AnnaBridge	171:3a7713b1edbc	356	#if defined(USB_OTG_FS) \|\| defined(USB)
AnnaBridge	171:3a7713b1edbc	357	/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
AnnaBridge	171:3a7713b1edbc	358	* @{
AnnaBridge	171:3a7713b1edbc	359	*/
AnnaBridge	171:3a7713b1edbc	360	#define LL_RCC_USB_CLKSOURCE 0x00400000U /!< USB Clock source selection /
AnnaBridge	171:3a7713b1edbc	361	/**
AnnaBridge	171:3a7713b1edbc	362	* @}
AnnaBridge	171:3a7713b1edbc	363	*/
AnnaBridge	171:3a7713b1edbc	364
AnnaBridge	171:3a7713b1edbc	365	#endif /* USB_OTG_FS \|\| USB */
AnnaBridge	171:3a7713b1edbc	366
AnnaBridge	171:3a7713b1edbc	367	/** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
AnnaBridge	171:3a7713b1edbc	368	* @{
AnnaBridge	171:3a7713b1edbc	369	*/
AnnaBridge	171:3a7713b1edbc	370	#define LL_RCC_ADC_CLKSOURCE RCC_CFGR_ADCPRE /!< ADC Clock source selection /
AnnaBridge	171:3a7713b1edbc	371	/**
AnnaBridge	171:3a7713b1edbc	372	* @}
AnnaBridge	171:3a7713b1edbc	373	*/
AnnaBridge	171:3a7713b1edbc	374
AnnaBridge	171:3a7713b1edbc	375	/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
AnnaBridge	171:3a7713b1edbc	376	* @{
AnnaBridge	171:3a7713b1edbc	377	*/
AnnaBridge	171:3a7713b1edbc	378	#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /!< No clock used as RTC clock /
AnnaBridge	171:3a7713b1edbc	379	#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /!< LSE oscillator clock used as RTC clock /
AnnaBridge	171:3a7713b1edbc	380	#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /!< LSI oscillator clock used as RTC clock /
AnnaBridge	171:3a7713b1edbc	381	#define LL_RCC_RTC_CLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL /!< HSE oscillator clock divided by 128 used as RTC clock /
AnnaBridge	171:3a7713b1edbc	382	/**
AnnaBridge	171:3a7713b1edbc	383	* @}
AnnaBridge	171:3a7713b1edbc	384	*/
AnnaBridge	171:3a7713b1edbc	385
AnnaBridge	171:3a7713b1edbc	386	/** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor
AnnaBridge	171:3a7713b1edbc	387	* @{
AnnaBridge	171:3a7713b1edbc	388	*/
AnnaBridge	171:3a7713b1edbc	389	#if defined(RCC_CFGR_PLLMULL2)
AnnaBridge	171:3a7713b1edbc	390	#define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMULL2 /!< PLL input clock2 */
AnnaBridge	171:3a7713b1edbc	391	#endif /RCC_CFGR_PLLMULL2/
AnnaBridge	171:3a7713b1edbc	392	#if defined(RCC_CFGR_PLLMULL3)
AnnaBridge	171:3a7713b1edbc	393	#define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMULL3 /!< PLL input clock3 */
AnnaBridge	171:3a7713b1edbc	394	#endif /RCC_CFGR_PLLMULL3/
AnnaBridge	171:3a7713b1edbc	395	#define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMULL4 /!< PLL input clock4 */
AnnaBridge	171:3a7713b1edbc	396	#define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMULL5 /!< PLL input clock5 */
AnnaBridge	171:3a7713b1edbc	397	#define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMULL6 /!< PLL input clock6 */
AnnaBridge	171:3a7713b1edbc	398	#define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMULL7 /!< PLL input clock7 */
AnnaBridge	171:3a7713b1edbc	399	#define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMULL8 /!< PLL input clock8 */
AnnaBridge	171:3a7713b1edbc	400	#define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMULL9 /!< PLL input clock9 */
AnnaBridge	171:3a7713b1edbc	401	#if defined(RCC_CFGR_PLLMULL6_5)
AnnaBridge	171:3a7713b1edbc	402	#define LL_RCC_PLL_MUL_6_5 RCC_CFGR_PLLMULL6_5 /!< PLL input clock6 */
AnnaBridge	171:3a7713b1edbc	403	#else
AnnaBridge	171:3a7713b1edbc	404	#define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMULL10 /!< PLL input clock10 */
AnnaBridge	171:3a7713b1edbc	405	#define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMULL11 /!< PLL input clock11 */
AnnaBridge	171:3a7713b1edbc	406	#define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMULL12 /!< PLL input clock12 */
AnnaBridge	171:3a7713b1edbc	407	#define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMULL13 /!< PLL input clock13 */
AnnaBridge	171:3a7713b1edbc	408	#define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMULL14 /!< PLL input clock14 */
AnnaBridge	171:3a7713b1edbc	409	#define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMULL15 /!< PLL input clock15 */
AnnaBridge	171:3a7713b1edbc	410	#define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMULL16 /!< PLL input clock16 */
AnnaBridge	171:3a7713b1edbc	411	#endif /RCC_CFGR_PLLMULL6_5/
AnnaBridge	171:3a7713b1edbc	412	/**
AnnaBridge	171:3a7713b1edbc	413	* @}
AnnaBridge	171:3a7713b1edbc	414	*/
AnnaBridge	171:3a7713b1edbc	415
AnnaBridge	171:3a7713b1edbc	416	/** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE
AnnaBridge	171:3a7713b1edbc	417	* @{
AnnaBridge	171:3a7713b1edbc	418	*/
AnnaBridge	171:3a7713b1edbc	419	#define LL_RCC_PLLSOURCE_HSI_DIV_2 0x00000000U /!< HSI clock divided by 2 selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	420	#define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /!< HSE/PREDIV1 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	421	#if defined(RCC_CFGR2_PREDIV1SRC)
AnnaBridge	171:3a7713b1edbc	422	#define LL_RCC_PLLSOURCE_PLL2 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1SRC << 4U) /!< PLL2/PREDIV1 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	423	#endif /RCC_CFGR2_PREDIV1SRC/
AnnaBridge	171:3a7713b1edbc	424
AnnaBridge	171:3a7713b1edbc	425	#if defined(RCC_CFGR2_PREDIV1)
AnnaBridge	171:3a7713b1edbc	426	#define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV1) /!< HSE/1 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	427	#define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV2) /!< HSE/2 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	428	#define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV3) /!< HSE/3 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	429	#define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV4) /!< HSE/4 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	430	#define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV5) /!< HSE/5 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	431	#define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV6) /!< HSE/6 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	432	#define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV7) /!< HSE/7 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	433	#define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV8) /!< HSE/8 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	434	#define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV9) /!< HSE/9 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	435	#define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV10) /!< HSE/10 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	436	#define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV11) /!< HSE/11 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	437	#define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV12) /!< HSE/12 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	438	#define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV13) /!< HSE/13 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	439	#define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV14) /!< HSE/14 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	440	#define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV15) /!< HSE/15 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	441	#define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV16) /!< HSE/16 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	442	#if defined(RCC_CFGR2_PREDIV1SRC)
AnnaBridge	171:3a7713b1edbc	443	#define LL_RCC_PLLSOURCE_PLL2_DIV_1 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV1 \| RCC_CFGR2_PREDIV1SRC << 4U) /!< PLL2/1 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	444	#define LL_RCC_PLLSOURCE_PLL2_DIV_2 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV2 \| RCC_CFGR2_PREDIV1SRC << 4U) /!< PLL2/2 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	445	#define LL_RCC_PLLSOURCE_PLL2_DIV_3 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV3 \| RCC_CFGR2_PREDIV1SRC << 4U) /!< PLL2/3 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	446	#define LL_RCC_PLLSOURCE_PLL2_DIV_4 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV4 \| RCC_CFGR2_PREDIV1SRC << 4U) /!< PLL2/4 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	447	#define LL_RCC_PLLSOURCE_PLL2_DIV_5 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV5 \| RCC_CFGR2_PREDIV1SRC << 4U) /!< PLL2/5 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	448	#define LL_RCC_PLLSOURCE_PLL2_DIV_6 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV6 \| RCC_CFGR2_PREDIV1SRC << 4U) /!< PLL2/6 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	449	#define LL_RCC_PLLSOURCE_PLL2_DIV_7 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV7 \| RCC_CFGR2_PREDIV1SRC << 4U) /!< PLL2/7 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	450	#define LL_RCC_PLLSOURCE_PLL2_DIV_8 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV8 \| RCC_CFGR2_PREDIV1SRC << 4U) /!< PLL2/8 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	451	#define LL_RCC_PLLSOURCE_PLL2_DIV_9 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV9 \| RCC_CFGR2_PREDIV1SRC << 4U) /!< PLL2/9 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	452	#define LL_RCC_PLLSOURCE_PLL2_DIV_10 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV10 \| RCC_CFGR2_PREDIV1SRC << 4U) /!< PLL2/10 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	453	#define LL_RCC_PLLSOURCE_PLL2_DIV_11 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV11 \| RCC_CFGR2_PREDIV1SRC << 4U) /!< PLL2/11 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	454	#define LL_RCC_PLLSOURCE_PLL2_DIV_12 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV12 \| RCC_CFGR2_PREDIV1SRC << 4U) /!< PLL2/12 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	455	#define LL_RCC_PLLSOURCE_PLL2_DIV_13 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV13 \| RCC_CFGR2_PREDIV1SRC << 4U) /!< PLL2/13 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	456	#define LL_RCC_PLLSOURCE_PLL2_DIV_14 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV14 \| RCC_CFGR2_PREDIV1SRC << 4U) /!< PLL2/14 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	457	#define LL_RCC_PLLSOURCE_PLL2_DIV_15 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV15 \| RCC_CFGR2_PREDIV1SRC << 4U) /!< PLL2/15 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	458	#define LL_RCC_PLLSOURCE_PLL2_DIV_16 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV16 \| RCC_CFGR2_PREDIV1SRC << 4U) /!< PLL2/16 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	459	#endif /RCC_CFGR2_PREDIV1SRC/
AnnaBridge	171:3a7713b1edbc	460	#else
AnnaBridge	171:3a7713b1edbc	461	#define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC \| 0x00000000U) /!< HSE/1 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	462	#define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC \| RCC_CFGR_PLLXTPRE) /!< HSE/2 clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	463	#endif /RCC_CFGR2_PREDIV1/
AnnaBridge	171:3a7713b1edbc	464	/**
AnnaBridge	171:3a7713b1edbc	465	* @}
AnnaBridge	171:3a7713b1edbc	466	*/
AnnaBridge	171:3a7713b1edbc	467
AnnaBridge	171:3a7713b1edbc	468	/** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor
AnnaBridge	171:3a7713b1edbc	469	* @{
AnnaBridge	171:3a7713b1edbc	470	*/
AnnaBridge	171:3a7713b1edbc	471	#if defined(RCC_CFGR2_PREDIV1)
AnnaBridge	171:3a7713b1edbc	472	#define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV1_DIV1 /!< PREDIV1 input clock not divided /
AnnaBridge	171:3a7713b1edbc	473	#define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV1_DIV2 /!< PREDIV1 input clock divided by 2 /
AnnaBridge	171:3a7713b1edbc	474	#define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV1_DIV3 /!< PREDIV1 input clock divided by 3 /
AnnaBridge	171:3a7713b1edbc	475	#define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV1_DIV4 /!< PREDIV1 input clock divided by 4 /
AnnaBridge	171:3a7713b1edbc	476	#define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV1_DIV5 /!< PREDIV1 input clock divided by 5 /
AnnaBridge	171:3a7713b1edbc	477	#define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV1_DIV6 /!< PREDIV1 input clock divided by 6 /
AnnaBridge	171:3a7713b1edbc	478	#define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV1_DIV7 /!< PREDIV1 input clock divided by 7 /
AnnaBridge	171:3a7713b1edbc	479	#define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV1_DIV8 /!< PREDIV1 input clock divided by 8 /
AnnaBridge	171:3a7713b1edbc	480	#define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV1_DIV9 /!< PREDIV1 input clock divided by 9 /
AnnaBridge	171:3a7713b1edbc	481	#define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV1_DIV10 /!< PREDIV1 input clock divided by 10 /
AnnaBridge	171:3a7713b1edbc	482	#define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV1_DIV11 /!< PREDIV1 input clock divided by 11 /
AnnaBridge	171:3a7713b1edbc	483	#define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV1_DIV12 /!< PREDIV1 input clock divided by 12 /
AnnaBridge	171:3a7713b1edbc	484	#define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV1_DIV13 /!< PREDIV1 input clock divided by 13 /
AnnaBridge	171:3a7713b1edbc	485	#define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV1_DIV14 /!< PREDIV1 input clock divided by 14 /
AnnaBridge	171:3a7713b1edbc	486	#define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV1_DIV15 /!< PREDIV1 input clock divided by 15 /
AnnaBridge	171:3a7713b1edbc	487	#define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV1_DIV16 /!< PREDIV1 input clock divided by 16 /
AnnaBridge	171:3a7713b1edbc	488	#else
AnnaBridge	171:3a7713b1edbc	489	#define LL_RCC_PREDIV_DIV_1 0x00000000U /!< HSE divider clock clock not divided /
AnnaBridge	171:3a7713b1edbc	490	#define LL_RCC_PREDIV_DIV_2 RCC_CFGR_PLLXTPRE /!< HSE divider clock divided by 2 for PLL entry /
AnnaBridge	171:3a7713b1edbc	491	#endif /RCC_CFGR2_PREDIV1/
AnnaBridge	171:3a7713b1edbc	492	/**
AnnaBridge	171:3a7713b1edbc	493	* @}
AnnaBridge	171:3a7713b1edbc	494	*/
AnnaBridge	171:3a7713b1edbc	495
AnnaBridge	171:3a7713b1edbc	496	#if defined(RCC_PLLI2S_SUPPORT)
AnnaBridge	171:3a7713b1edbc	497	/** @defgroup RCC_LL_EC_PLLI2S_MUL PLLI2S MUL
AnnaBridge	171:3a7713b1edbc	498	* @{
AnnaBridge	171:3a7713b1edbc	499	*/
AnnaBridge	171:3a7713b1edbc	500	#define LL_RCC_PLLI2S_MUL_8 RCC_CFGR2_PLL3MUL8 /!< PLLI2S input clock 8 */
AnnaBridge	171:3a7713b1edbc	501	#define LL_RCC_PLLI2S_MUL_9 RCC_CFGR2_PLL3MUL9 /!< PLLI2S input clock 9 */
AnnaBridge	171:3a7713b1edbc	502	#define LL_RCC_PLLI2S_MUL_10 RCC_CFGR2_PLL3MUL10 /!< PLLI2S input clock 10 */
AnnaBridge	171:3a7713b1edbc	503	#define LL_RCC_PLLI2S_MUL_11 RCC_CFGR2_PLL3MUL11 /!< PLLI2S input clock 11 */
AnnaBridge	171:3a7713b1edbc	504	#define LL_RCC_PLLI2S_MUL_12 RCC_CFGR2_PLL3MUL12 /!< PLLI2S input clock 12 */
AnnaBridge	171:3a7713b1edbc	505	#define LL_RCC_PLLI2S_MUL_13 RCC_CFGR2_PLL3MUL13 /!< PLLI2S input clock 13 */
AnnaBridge	171:3a7713b1edbc	506	#define LL_RCC_PLLI2S_MUL_14 RCC_CFGR2_PLL3MUL14 /!< PLLI2S input clock 14 */
AnnaBridge	171:3a7713b1edbc	507	#define LL_RCC_PLLI2S_MUL_16 RCC_CFGR2_PLL3MUL16 /!< PLLI2S input clock 16 */
AnnaBridge	171:3a7713b1edbc	508	#define LL_RCC_PLLI2S_MUL_20 RCC_CFGR2_PLL3MUL20 /!< PLLI2S input clock 20 */
AnnaBridge	171:3a7713b1edbc	509	/**
AnnaBridge	171:3a7713b1edbc	510	* @}
AnnaBridge	171:3a7713b1edbc	511	*/
AnnaBridge	171:3a7713b1edbc	512
AnnaBridge	171:3a7713b1edbc	513	#endif /* RCC_PLLI2S_SUPPORT */
AnnaBridge	171:3a7713b1edbc	514
AnnaBridge	171:3a7713b1edbc	515	#if defined(RCC_PLL2_SUPPORT)
AnnaBridge	171:3a7713b1edbc	516	/** @defgroup RCC_LL_EC_PLL2_MUL PLL2 MUL
AnnaBridge	171:3a7713b1edbc	517	* @{
AnnaBridge	171:3a7713b1edbc	518	*/
AnnaBridge	171:3a7713b1edbc	519	#define LL_RCC_PLL2_MUL_8 RCC_CFGR2_PLL2MUL8 /!< PLL2 input clock 8 */
AnnaBridge	171:3a7713b1edbc	520	#define LL_RCC_PLL2_MUL_9 RCC_CFGR2_PLL2MUL9 /!< PLL2 input clock 9 */
AnnaBridge	171:3a7713b1edbc	521	#define LL_RCC_PLL2_MUL_10 RCC_CFGR2_PLL2MUL10 /!< PLL2 input clock 10 */
AnnaBridge	171:3a7713b1edbc	522	#define LL_RCC_PLL2_MUL_11 RCC_CFGR2_PLL2MUL11 /!< PLL2 input clock 11 */
AnnaBridge	171:3a7713b1edbc	523	#define LL_RCC_PLL2_MUL_12 RCC_CFGR2_PLL2MUL12 /!< PLL2 input clock 12 */
AnnaBridge	171:3a7713b1edbc	524	#define LL_RCC_PLL2_MUL_13 RCC_CFGR2_PLL2MUL13 /!< PLL2 input clock 13 */
AnnaBridge	171:3a7713b1edbc	525	#define LL_RCC_PLL2_MUL_14 RCC_CFGR2_PLL2MUL14 /!< PLL2 input clock 14 */
AnnaBridge	171:3a7713b1edbc	526	#define LL_RCC_PLL2_MUL_16 RCC_CFGR2_PLL2MUL16 /!< PLL2 input clock 16 */
AnnaBridge	171:3a7713b1edbc	527	#define LL_RCC_PLL2_MUL_20 RCC_CFGR2_PLL2MUL20 /!< PLL2 input clock 20 */
AnnaBridge	171:3a7713b1edbc	528	/**
AnnaBridge	171:3a7713b1edbc	529	* @}
AnnaBridge	171:3a7713b1edbc	530	*/
AnnaBridge	171:3a7713b1edbc	531
AnnaBridge	171:3a7713b1edbc	532	#endif /* RCC_PLL2_SUPPORT */
AnnaBridge	171:3a7713b1edbc	533
AnnaBridge	171:3a7713b1edbc	534	/**
AnnaBridge	171:3a7713b1edbc	535	* @}
AnnaBridge	171:3a7713b1edbc	536	*/
AnnaBridge	171:3a7713b1edbc	537
AnnaBridge	171:3a7713b1edbc	538	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	539	/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
AnnaBridge	171:3a7713b1edbc	540	* @{
AnnaBridge	171:3a7713b1edbc	541	*/
AnnaBridge	171:3a7713b1edbc	542
AnnaBridge	171:3a7713b1edbc	543	/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	171:3a7713b1edbc	544	* @{
AnnaBridge	171:3a7713b1edbc	545	*/
AnnaBridge	171:3a7713b1edbc	546
AnnaBridge	171:3a7713b1edbc	547	/**
AnnaBridge	171:3a7713b1edbc	548	* @brief Write a value in RCC register
AnnaBridge	171:3a7713b1edbc	549	* @param __REG__ Register to be written
AnnaBridge	171:3a7713b1edbc	550	* @param __VALUE__ Value to be written in the register
AnnaBridge	171:3a7713b1edbc	551	* @retval None
AnnaBridge	171:3a7713b1edbc	552	*/
AnnaBridge	171:3a7713b1edbc	553	#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
AnnaBridge	171:3a7713b1edbc	554
AnnaBridge	171:3a7713b1edbc	555	/**
AnnaBridge	171:3a7713b1edbc	556	* @brief Read a value in RCC register
AnnaBridge	171:3a7713b1edbc	557	* @param __REG__ Register to be read
AnnaBridge	171:3a7713b1edbc	558	* @retval Register value
AnnaBridge	171:3a7713b1edbc	559	*/
AnnaBridge	171:3a7713b1edbc	560	#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
AnnaBridge	171:3a7713b1edbc	561	/**
AnnaBridge	171:3a7713b1edbc	562	* @}
AnnaBridge	171:3a7713b1edbc	563	*/
AnnaBridge	171:3a7713b1edbc	564
AnnaBridge	171:3a7713b1edbc	565	/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
AnnaBridge	171:3a7713b1edbc	566	* @{
AnnaBridge	171:3a7713b1edbc	567	*/
AnnaBridge	171:3a7713b1edbc	568
AnnaBridge	171:3a7713b1edbc	569	#if defined(RCC_CFGR_PLLMULL6_5)
AnnaBridge	171:3a7713b1edbc	570	/**
AnnaBridge	171:3a7713b1edbc	571	* @brief Helper macro to calculate the PLLCLK frequency
AnnaBridge	171:3a7713b1edbc	572	* @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator());
AnnaBridge	171:3a7713b1edbc	573	* @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv1 / HSI div 2 / PLL2 div Prediv1)
AnnaBridge	171:3a7713b1edbc	574	* @param __PLLMUL__: This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	575	* @arg @ref LL_RCC_PLL_MUL_4
AnnaBridge	171:3a7713b1edbc	576	* @arg @ref LL_RCC_PLL_MUL_5
AnnaBridge	171:3a7713b1edbc	577	* @arg @ref LL_RCC_PLL_MUL_6
AnnaBridge	171:3a7713b1edbc	578	* @arg @ref LL_RCC_PLL_MUL_7
AnnaBridge	171:3a7713b1edbc	579	* @arg @ref LL_RCC_PLL_MUL_8
AnnaBridge	171:3a7713b1edbc	580	* @arg @ref LL_RCC_PLL_MUL_9
AnnaBridge	171:3a7713b1edbc	581	* @arg @ref LL_RCC_PLL_MUL_6_5
AnnaBridge	171:3a7713b1edbc	582	* @retval PLL clock frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	583	*/
AnnaBridge	171:3a7713b1edbc	584	#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \
AnnaBridge	171:3a7713b1edbc	585	(((__PLLMUL__) != RCC_CFGR_PLLMULL6_5) ? \
AnnaBridge	171:3a7713b1edbc	586	((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos) + 2U)) :\
AnnaBridge	171:3a7713b1edbc	587	(((__INPUTFREQ__) * 13U) / 2U))
AnnaBridge	171:3a7713b1edbc	588
AnnaBridge	171:3a7713b1edbc	589	#else
AnnaBridge	171:3a7713b1edbc	590	/**
AnnaBridge	171:3a7713b1edbc	591	* @brief Helper macro to calculate the PLLCLK frequency
AnnaBridge	171:3a7713b1edbc	592	* @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator ());
AnnaBridge	171:3a7713b1edbc	593	* @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv1 or div 2 / HSI div 2)
AnnaBridge	171:3a7713b1edbc	594	* @param __PLLMUL__: This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	595	* @arg @ref LL_RCC_PLL_MUL_2
AnnaBridge	171:3a7713b1edbc	596	* @arg @ref LL_RCC_PLL_MUL_3
AnnaBridge	171:3a7713b1edbc	597	* @arg @ref LL_RCC_PLL_MUL_4
AnnaBridge	171:3a7713b1edbc	598	* @arg @ref LL_RCC_PLL_MUL_5
AnnaBridge	171:3a7713b1edbc	599	* @arg @ref LL_RCC_PLL_MUL_6
AnnaBridge	171:3a7713b1edbc	600	* @arg @ref LL_RCC_PLL_MUL_7
AnnaBridge	171:3a7713b1edbc	601	* @arg @ref LL_RCC_PLL_MUL_8
AnnaBridge	171:3a7713b1edbc	602	* @arg @ref LL_RCC_PLL_MUL_9
AnnaBridge	171:3a7713b1edbc	603	* @arg @ref LL_RCC_PLL_MUL_10
AnnaBridge	171:3a7713b1edbc	604	* @arg @ref LL_RCC_PLL_MUL_11
AnnaBridge	171:3a7713b1edbc	605	* @arg @ref LL_RCC_PLL_MUL_12
AnnaBridge	171:3a7713b1edbc	606	* @arg @ref LL_RCC_PLL_MUL_13
AnnaBridge	171:3a7713b1edbc	607	* @arg @ref LL_RCC_PLL_MUL_14
AnnaBridge	171:3a7713b1edbc	608	* @arg @ref LL_RCC_PLL_MUL_15
AnnaBridge	171:3a7713b1edbc	609	* @arg @ref LL_RCC_PLL_MUL_16
AnnaBridge	171:3a7713b1edbc	610	* @retval PLL clock frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	611	*/
AnnaBridge	171:3a7713b1edbc	612	#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) ((__INPUTFREQ__) * (((__PLLMUL__) >> RCC_CFGR_PLLMULL_Pos) + 2U))
AnnaBridge	171:3a7713b1edbc	613	#endif /* RCC_CFGR_PLLMULL6_5 */
AnnaBridge	171:3a7713b1edbc	614
AnnaBridge	171:3a7713b1edbc	615	#if defined(RCC_PLLI2S_SUPPORT)
AnnaBridge	171:3a7713b1edbc	616	/**
AnnaBridge	171:3a7713b1edbc	617	* @brief Helper macro to calculate the PLLI2S frequency
AnnaBridge	171:3a7713b1edbc	618	* @note ex: @ref __LL_RCC_CALC_PLLI2SCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLLI2S_GetMultiplicator (), @ref LL_RCC_HSE_GetPrediv2 ());
AnnaBridge	171:3a7713b1edbc	619	* @param __INPUTFREQ__ PLLI2S Input frequency (based on HSE value)
AnnaBridge	171:3a7713b1edbc	620	* @param __PLLI2SMUL__: This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	621	* @arg @ref LL_RCC_PLLI2S_MUL_8
AnnaBridge	171:3a7713b1edbc	622	* @arg @ref LL_RCC_PLLI2S_MUL_9
AnnaBridge	171:3a7713b1edbc	623	* @arg @ref LL_RCC_PLLI2S_MUL_10
AnnaBridge	171:3a7713b1edbc	624	* @arg @ref LL_RCC_PLLI2S_MUL_11
AnnaBridge	171:3a7713b1edbc	625	* @arg @ref LL_RCC_PLLI2S_MUL_12
AnnaBridge	171:3a7713b1edbc	626	* @arg @ref LL_RCC_PLLI2S_MUL_13
AnnaBridge	171:3a7713b1edbc	627	* @arg @ref LL_RCC_PLLI2S_MUL_14
AnnaBridge	171:3a7713b1edbc	628	* @arg @ref LL_RCC_PLLI2S_MUL_16
AnnaBridge	171:3a7713b1edbc	629	* @arg @ref LL_RCC_PLLI2S_MUL_20
AnnaBridge	171:3a7713b1edbc	630	* @param __PLLI2SDIV__: This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	631	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
AnnaBridge	171:3a7713b1edbc	632	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
AnnaBridge	171:3a7713b1edbc	633	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
AnnaBridge	171:3a7713b1edbc	634	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
AnnaBridge	171:3a7713b1edbc	635	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
AnnaBridge	171:3a7713b1edbc	636	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
AnnaBridge	171:3a7713b1edbc	637	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
AnnaBridge	171:3a7713b1edbc	638	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
AnnaBridge	171:3a7713b1edbc	639	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
AnnaBridge	171:3a7713b1edbc	640	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
AnnaBridge	171:3a7713b1edbc	641	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
AnnaBridge	171:3a7713b1edbc	642	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
AnnaBridge	171:3a7713b1edbc	643	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
AnnaBridge	171:3a7713b1edbc	644	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
AnnaBridge	171:3a7713b1edbc	645	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
AnnaBridge	171:3a7713b1edbc	646	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
AnnaBridge	171:3a7713b1edbc	647	* @retval PLLI2S clock frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	648	*/
AnnaBridge	171:3a7713b1edbc	649	#define __LL_RCC_CALC_PLLI2SCLK_FREQ(__INPUTFREQ__, __PLLI2SMUL__, __PLLI2SDIV__) (((__INPUTFREQ__) * (((__PLLI2SMUL__) >> RCC_CFGR2_PLL3MUL_Pos) + 2U)) / (((__PLLI2SDIV__) >> RCC_CFGR2_PREDIV2_Pos) + 1U))
AnnaBridge	171:3a7713b1edbc	650	#endif /* RCC_PLLI2S_SUPPORT */
AnnaBridge	171:3a7713b1edbc	651
AnnaBridge	171:3a7713b1edbc	652	#if defined(RCC_PLL2_SUPPORT)
AnnaBridge	171:3a7713b1edbc	653	/**
AnnaBridge	171:3a7713b1edbc	654	* @brief Helper macro to calculate the PLL2 frequency
AnnaBridge	171:3a7713b1edbc	655	* @note ex: @ref __LL_RCC_CALC_PLL2CLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL2_GetMultiplicator (), @ref LL_RCC_HSE_GetPrediv2 ());
AnnaBridge	171:3a7713b1edbc	656	* @param __INPUTFREQ__ PLL2 Input frequency (based on HSE value)
AnnaBridge	171:3a7713b1edbc	657	* @param __PLL2MUL__: This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	658	* @arg @ref LL_RCC_PLL2_MUL_8
AnnaBridge	171:3a7713b1edbc	659	* @arg @ref LL_RCC_PLL2_MUL_9
AnnaBridge	171:3a7713b1edbc	660	* @arg @ref LL_RCC_PLL2_MUL_10
AnnaBridge	171:3a7713b1edbc	661	* @arg @ref LL_RCC_PLL2_MUL_11
AnnaBridge	171:3a7713b1edbc	662	* @arg @ref LL_RCC_PLL2_MUL_12
AnnaBridge	171:3a7713b1edbc	663	* @arg @ref LL_RCC_PLL2_MUL_13
AnnaBridge	171:3a7713b1edbc	664	* @arg @ref LL_RCC_PLL2_MUL_14
AnnaBridge	171:3a7713b1edbc	665	* @arg @ref LL_RCC_PLL2_MUL_16
AnnaBridge	171:3a7713b1edbc	666	* @arg @ref LL_RCC_PLL2_MUL_20
AnnaBridge	171:3a7713b1edbc	667	* @param __PLL2DIV__: This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	668	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
AnnaBridge	171:3a7713b1edbc	669	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
AnnaBridge	171:3a7713b1edbc	670	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
AnnaBridge	171:3a7713b1edbc	671	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
AnnaBridge	171:3a7713b1edbc	672	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
AnnaBridge	171:3a7713b1edbc	673	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
AnnaBridge	171:3a7713b1edbc	674	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
AnnaBridge	171:3a7713b1edbc	675	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
AnnaBridge	171:3a7713b1edbc	676	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
AnnaBridge	171:3a7713b1edbc	677	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
AnnaBridge	171:3a7713b1edbc	678	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
AnnaBridge	171:3a7713b1edbc	679	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
AnnaBridge	171:3a7713b1edbc	680	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
AnnaBridge	171:3a7713b1edbc	681	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
AnnaBridge	171:3a7713b1edbc	682	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
AnnaBridge	171:3a7713b1edbc	683	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
AnnaBridge	171:3a7713b1edbc	684	* @retval PLL2 clock frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	685	*/
AnnaBridge	171:3a7713b1edbc	686	#define __LL_RCC_CALC_PLL2CLK_FREQ(__INPUTFREQ__, __PLL2MUL__, __PLL2DIV__) (((__INPUTFREQ__) * (((__PLL2MUL__) >> RCC_CFGR2_PLL2MUL_Pos) + 2U)) / (((__PLL2DIV__) >> RCC_CFGR2_PREDIV2_Pos) + 1U))
AnnaBridge	171:3a7713b1edbc	687	#endif /* RCC_PLL2_SUPPORT */
AnnaBridge	171:3a7713b1edbc	688
AnnaBridge	171:3a7713b1edbc	689	/**
AnnaBridge	171:3a7713b1edbc	690	* @brief Helper macro to calculate the HCLK frequency
AnnaBridge	171:3a7713b1edbc	691	* @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler
AnnaBridge	171:3a7713b1edbc	692	* ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler())
AnnaBridge	171:3a7713b1edbc	693	* @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
AnnaBridge	171:3a7713b1edbc	694	* @param __AHBPRESCALER__: This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	695	* @arg @ref LL_RCC_SYSCLK_DIV_1
AnnaBridge	171:3a7713b1edbc	696	* @arg @ref LL_RCC_SYSCLK_DIV_2
AnnaBridge	171:3a7713b1edbc	697	* @arg @ref LL_RCC_SYSCLK_DIV_4
AnnaBridge	171:3a7713b1edbc	698	* @arg @ref LL_RCC_SYSCLK_DIV_8
AnnaBridge	171:3a7713b1edbc	699	* @arg @ref LL_RCC_SYSCLK_DIV_16
AnnaBridge	171:3a7713b1edbc	700	* @arg @ref LL_RCC_SYSCLK_DIV_64
AnnaBridge	171:3a7713b1edbc	701	* @arg @ref LL_RCC_SYSCLK_DIV_128
AnnaBridge	171:3a7713b1edbc	702	* @arg @ref LL_RCC_SYSCLK_DIV_256
AnnaBridge	171:3a7713b1edbc	703	* @arg @ref LL_RCC_SYSCLK_DIV_512
AnnaBridge	171:3a7713b1edbc	704	* @retval HCLK clock frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	705	*/
AnnaBridge	171:3a7713b1edbc	706	#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
AnnaBridge	171:3a7713b1edbc	707
AnnaBridge	171:3a7713b1edbc	708	/**
AnnaBridge	171:3a7713b1edbc	709	* @brief Helper macro to calculate the PCLK1 frequency (ABP1)
AnnaBridge	171:3a7713b1edbc	710	* @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler
AnnaBridge	171:3a7713b1edbc	711	* ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler())
AnnaBridge	171:3a7713b1edbc	712	* @param __HCLKFREQ__ HCLK frequency
AnnaBridge	171:3a7713b1edbc	713	* @param __APB1PRESCALER__: This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	714	* @arg @ref LL_RCC_APB1_DIV_1
AnnaBridge	171:3a7713b1edbc	715	* @arg @ref LL_RCC_APB1_DIV_2
AnnaBridge	171:3a7713b1edbc	716	* @arg @ref LL_RCC_APB1_DIV_4
AnnaBridge	171:3a7713b1edbc	717	* @arg @ref LL_RCC_APB1_DIV_8
AnnaBridge	171:3a7713b1edbc	718	* @arg @ref LL_RCC_APB1_DIV_16
AnnaBridge	171:3a7713b1edbc	719	* @retval PCLK1 clock frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	720	*/
AnnaBridge	171:3a7713b1edbc	721	#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
AnnaBridge	171:3a7713b1edbc	722
AnnaBridge	171:3a7713b1edbc	723	/**
AnnaBridge	171:3a7713b1edbc	724	* @brief Helper macro to calculate the PCLK2 frequency (ABP2)
AnnaBridge	171:3a7713b1edbc	725	* @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler
AnnaBridge	171:3a7713b1edbc	726	* ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler())
AnnaBridge	171:3a7713b1edbc	727	* @param __HCLKFREQ__ HCLK frequency
AnnaBridge	171:3a7713b1edbc	728	* @param __APB2PRESCALER__: This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	729	* @arg @ref LL_RCC_APB2_DIV_1
AnnaBridge	171:3a7713b1edbc	730	* @arg @ref LL_RCC_APB2_DIV_2
AnnaBridge	171:3a7713b1edbc	731	* @arg @ref LL_RCC_APB2_DIV_4
AnnaBridge	171:3a7713b1edbc	732	* @arg @ref LL_RCC_APB2_DIV_8
AnnaBridge	171:3a7713b1edbc	733	* @arg @ref LL_RCC_APB2_DIV_16
AnnaBridge	171:3a7713b1edbc	734	* @retval PCLK2 clock frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	735	*/
AnnaBridge	171:3a7713b1edbc	736	#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
AnnaBridge	171:3a7713b1edbc	737
AnnaBridge	171:3a7713b1edbc	738	/**
AnnaBridge	171:3a7713b1edbc	739	* @}
AnnaBridge	171:3a7713b1edbc	740	*/
AnnaBridge	171:3a7713b1edbc	741
AnnaBridge	171:3a7713b1edbc	742	/**
AnnaBridge	171:3a7713b1edbc	743	* @}
AnnaBridge	171:3a7713b1edbc	744	*/
AnnaBridge	171:3a7713b1edbc	745
AnnaBridge	171:3a7713b1edbc	746	/* Exported functions --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	747	/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
AnnaBridge	171:3a7713b1edbc	748	* @{
AnnaBridge	171:3a7713b1edbc	749	*/
AnnaBridge	171:3a7713b1edbc	750
AnnaBridge	171:3a7713b1edbc	751	/** @defgroup RCC_LL_EF_HSE HSE
AnnaBridge	171:3a7713b1edbc	752	* @{
AnnaBridge	171:3a7713b1edbc	753	*/
AnnaBridge	171:3a7713b1edbc	754
AnnaBridge	171:3a7713b1edbc	755	/**
AnnaBridge	171:3a7713b1edbc	756	* @brief Enable the Clock Security System.
AnnaBridge	171:3a7713b1edbc	757	* @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
AnnaBridge	171:3a7713b1edbc	758	* @retval None
AnnaBridge	171:3a7713b1edbc	759	*/
AnnaBridge	171:3a7713b1edbc	760	__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
AnnaBridge	171:3a7713b1edbc	761	{
AnnaBridge	171:3a7713b1edbc	762	SET_BIT(RCC->CR, RCC_CR_CSSON);
AnnaBridge	171:3a7713b1edbc	763	}
AnnaBridge	171:3a7713b1edbc	764
AnnaBridge	171:3a7713b1edbc	765	/**
AnnaBridge	171:3a7713b1edbc	766	* @brief Enable HSE external oscillator (HSE Bypass)
AnnaBridge	171:3a7713b1edbc	767	* @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
AnnaBridge	171:3a7713b1edbc	768	* @retval None
AnnaBridge	171:3a7713b1edbc	769	*/
AnnaBridge	171:3a7713b1edbc	770	__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
AnnaBridge	171:3a7713b1edbc	771	{
AnnaBridge	171:3a7713b1edbc	772	SET_BIT(RCC->CR, RCC_CR_HSEBYP);
AnnaBridge	171:3a7713b1edbc	773	}
AnnaBridge	171:3a7713b1edbc	774
AnnaBridge	171:3a7713b1edbc	775	/**
AnnaBridge	171:3a7713b1edbc	776	* @brief Disable HSE external oscillator (HSE Bypass)
AnnaBridge	171:3a7713b1edbc	777	* @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
AnnaBridge	171:3a7713b1edbc	778	* @retval None
AnnaBridge	171:3a7713b1edbc	779	*/
AnnaBridge	171:3a7713b1edbc	780	__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
AnnaBridge	171:3a7713b1edbc	781	{
AnnaBridge	171:3a7713b1edbc	782	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
AnnaBridge	171:3a7713b1edbc	783	}
AnnaBridge	171:3a7713b1edbc	784
AnnaBridge	171:3a7713b1edbc	785	/**
AnnaBridge	171:3a7713b1edbc	786	* @brief Enable HSE crystal oscillator (HSE ON)
AnnaBridge	171:3a7713b1edbc	787	* @rmtoll CR HSEON LL_RCC_HSE_Enable
AnnaBridge	171:3a7713b1edbc	788	* @retval None
AnnaBridge	171:3a7713b1edbc	789	*/
AnnaBridge	171:3a7713b1edbc	790	__STATIC_INLINE void LL_RCC_HSE_Enable(void)
AnnaBridge	171:3a7713b1edbc	791	{
AnnaBridge	171:3a7713b1edbc	792	SET_BIT(RCC->CR, RCC_CR_HSEON);
AnnaBridge	171:3a7713b1edbc	793	}
AnnaBridge	171:3a7713b1edbc	794
AnnaBridge	171:3a7713b1edbc	795	/**
AnnaBridge	171:3a7713b1edbc	796	* @brief Disable HSE crystal oscillator (HSE ON)
AnnaBridge	171:3a7713b1edbc	797	* @rmtoll CR HSEON LL_RCC_HSE_Disable
AnnaBridge	171:3a7713b1edbc	798	* @retval None
AnnaBridge	171:3a7713b1edbc	799	*/
AnnaBridge	171:3a7713b1edbc	800	__STATIC_INLINE void LL_RCC_HSE_Disable(void)
AnnaBridge	171:3a7713b1edbc	801	{
AnnaBridge	171:3a7713b1edbc	802	CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
AnnaBridge	171:3a7713b1edbc	803	}
AnnaBridge	171:3a7713b1edbc	804
AnnaBridge	171:3a7713b1edbc	805	/**
AnnaBridge	171:3a7713b1edbc	806	* @brief Check if HSE oscillator Ready
AnnaBridge	171:3a7713b1edbc	807	* @rmtoll CR HSERDY LL_RCC_HSE_IsReady
AnnaBridge	171:3a7713b1edbc	808	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	809	*/
AnnaBridge	171:3a7713b1edbc	810	__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
AnnaBridge	171:3a7713b1edbc	811	{
AnnaBridge	171:3a7713b1edbc	812	return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
AnnaBridge	171:3a7713b1edbc	813	}
AnnaBridge	171:3a7713b1edbc	814
AnnaBridge	171:3a7713b1edbc	815	#if defined(RCC_CFGR2_PREDIV2)
AnnaBridge	171:3a7713b1edbc	816	/**
AnnaBridge	171:3a7713b1edbc	817	* @brief Get PREDIV2 division factor
AnnaBridge	171:3a7713b1edbc	818	* @rmtoll CFGR2 PREDIV2 LL_RCC_HSE_GetPrediv2
AnnaBridge	171:3a7713b1edbc	819	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	820	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
AnnaBridge	171:3a7713b1edbc	821	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
AnnaBridge	171:3a7713b1edbc	822	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
AnnaBridge	171:3a7713b1edbc	823	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
AnnaBridge	171:3a7713b1edbc	824	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
AnnaBridge	171:3a7713b1edbc	825	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
AnnaBridge	171:3a7713b1edbc	826	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
AnnaBridge	171:3a7713b1edbc	827	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
AnnaBridge	171:3a7713b1edbc	828	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
AnnaBridge	171:3a7713b1edbc	829	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
AnnaBridge	171:3a7713b1edbc	830	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
AnnaBridge	171:3a7713b1edbc	831	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
AnnaBridge	171:3a7713b1edbc	832	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
AnnaBridge	171:3a7713b1edbc	833	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
AnnaBridge	171:3a7713b1edbc	834	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
AnnaBridge	171:3a7713b1edbc	835	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
AnnaBridge	171:3a7713b1edbc	836	*/
AnnaBridge	171:3a7713b1edbc	837	__STATIC_INLINE uint32_t LL_RCC_HSE_GetPrediv2(void)
AnnaBridge	171:3a7713b1edbc	838	{
AnnaBridge	171:3a7713b1edbc	839	return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2));
AnnaBridge	171:3a7713b1edbc	840	}
AnnaBridge	171:3a7713b1edbc	841	#endif /* RCC_CFGR2_PREDIV2 */
AnnaBridge	171:3a7713b1edbc	842
AnnaBridge	171:3a7713b1edbc	843	/**
AnnaBridge	171:3a7713b1edbc	844	* @}
AnnaBridge	171:3a7713b1edbc	845	*/
AnnaBridge	171:3a7713b1edbc	846
AnnaBridge	171:3a7713b1edbc	847	/** @defgroup RCC_LL_EF_HSI HSI
AnnaBridge	171:3a7713b1edbc	848	* @{
AnnaBridge	171:3a7713b1edbc	849	*/
AnnaBridge	171:3a7713b1edbc	850
AnnaBridge	171:3a7713b1edbc	851	/**
AnnaBridge	171:3a7713b1edbc	852	* @brief Enable HSI oscillator
AnnaBridge	171:3a7713b1edbc	853	* @rmtoll CR HSION LL_RCC_HSI_Enable
AnnaBridge	171:3a7713b1edbc	854	* @retval None
AnnaBridge	171:3a7713b1edbc	855	*/
AnnaBridge	171:3a7713b1edbc	856	__STATIC_INLINE void LL_RCC_HSI_Enable(void)
AnnaBridge	171:3a7713b1edbc	857	{
AnnaBridge	171:3a7713b1edbc	858	SET_BIT(RCC->CR, RCC_CR_HSION);
AnnaBridge	171:3a7713b1edbc	859	}
AnnaBridge	171:3a7713b1edbc	860
AnnaBridge	171:3a7713b1edbc	861	/**
AnnaBridge	171:3a7713b1edbc	862	* @brief Disable HSI oscillator
AnnaBridge	171:3a7713b1edbc	863	* @rmtoll CR HSION LL_RCC_HSI_Disable
AnnaBridge	171:3a7713b1edbc	864	* @retval None
AnnaBridge	171:3a7713b1edbc	865	*/
AnnaBridge	171:3a7713b1edbc	866	__STATIC_INLINE void LL_RCC_HSI_Disable(void)
AnnaBridge	171:3a7713b1edbc	867	{
AnnaBridge	171:3a7713b1edbc	868	CLEAR_BIT(RCC->CR, RCC_CR_HSION);
AnnaBridge	171:3a7713b1edbc	869	}
AnnaBridge	171:3a7713b1edbc	870
AnnaBridge	171:3a7713b1edbc	871	/**
AnnaBridge	171:3a7713b1edbc	872	* @brief Check if HSI clock is ready
AnnaBridge	171:3a7713b1edbc	873	* @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
AnnaBridge	171:3a7713b1edbc	874	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	875	*/
AnnaBridge	171:3a7713b1edbc	876	__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
AnnaBridge	171:3a7713b1edbc	877	{
AnnaBridge	171:3a7713b1edbc	878	return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
AnnaBridge	171:3a7713b1edbc	879	}
AnnaBridge	171:3a7713b1edbc	880
AnnaBridge	171:3a7713b1edbc	881	/**
AnnaBridge	171:3a7713b1edbc	882	* @brief Get HSI Calibration value
AnnaBridge	171:3a7713b1edbc	883	* @note When HSITRIM is written, HSICAL is updated with the sum of
AnnaBridge	171:3a7713b1edbc	884	* HSITRIM and the factory trim value
AnnaBridge	171:3a7713b1edbc	885	* @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
AnnaBridge	171:3a7713b1edbc	886	* @retval Between Min_Data = 0x00 and Max_Data = 0xFF
AnnaBridge	171:3a7713b1edbc	887	*/
AnnaBridge	171:3a7713b1edbc	888	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
AnnaBridge	171:3a7713b1edbc	889	{
AnnaBridge	171:3a7713b1edbc	890	return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
AnnaBridge	171:3a7713b1edbc	891	}
AnnaBridge	171:3a7713b1edbc	892
AnnaBridge	171:3a7713b1edbc	893	/**
AnnaBridge	171:3a7713b1edbc	894	* @brief Set HSI Calibration trimming
AnnaBridge	171:3a7713b1edbc	895	* @note user-programmable trimming value that is added to the HSICAL
AnnaBridge	171:3a7713b1edbc	896	* @note Default value is 16, which, when added to the HSICAL value,
AnnaBridge	171:3a7713b1edbc	897	* should trim the HSI to 16 MHz +/- 1 %
AnnaBridge	171:3a7713b1edbc	898	* @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
AnnaBridge	171:3a7713b1edbc	899	* @param Value between Min_Data = 0x00 and Max_Data = 0x1F
AnnaBridge	171:3a7713b1edbc	900	* @retval None
AnnaBridge	171:3a7713b1edbc	901	*/
AnnaBridge	171:3a7713b1edbc	902	__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
AnnaBridge	171:3a7713b1edbc	903	{
AnnaBridge	171:3a7713b1edbc	904	MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
AnnaBridge	171:3a7713b1edbc	905	}
AnnaBridge	171:3a7713b1edbc	906
AnnaBridge	171:3a7713b1edbc	907	/**
AnnaBridge	171:3a7713b1edbc	908	* @brief Get HSI Calibration trimming
AnnaBridge	171:3a7713b1edbc	909	* @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
AnnaBridge	171:3a7713b1edbc	910	* @retval Between Min_Data = 0x00 and Max_Data = 0x1F
AnnaBridge	171:3a7713b1edbc	911	*/
AnnaBridge	171:3a7713b1edbc	912	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
AnnaBridge	171:3a7713b1edbc	913	{
AnnaBridge	171:3a7713b1edbc	914	return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
AnnaBridge	171:3a7713b1edbc	915	}
AnnaBridge	171:3a7713b1edbc	916
AnnaBridge	171:3a7713b1edbc	917	/**
AnnaBridge	171:3a7713b1edbc	918	* @}
AnnaBridge	171:3a7713b1edbc	919	*/
AnnaBridge	171:3a7713b1edbc	920
AnnaBridge	171:3a7713b1edbc	921	/** @defgroup RCC_LL_EF_LSE LSE
AnnaBridge	171:3a7713b1edbc	922	* @{
AnnaBridge	171:3a7713b1edbc	923	*/
AnnaBridge	171:3a7713b1edbc	924
AnnaBridge	171:3a7713b1edbc	925	/**
AnnaBridge	171:3a7713b1edbc	926	* @brief Enable Low Speed External (LSE) crystal.
AnnaBridge	171:3a7713b1edbc	927	* @rmtoll BDCR LSEON LL_RCC_LSE_Enable
AnnaBridge	171:3a7713b1edbc	928	* @retval None
AnnaBridge	171:3a7713b1edbc	929	*/
AnnaBridge	171:3a7713b1edbc	930	__STATIC_INLINE void LL_RCC_LSE_Enable(void)
AnnaBridge	171:3a7713b1edbc	931	{
AnnaBridge	171:3a7713b1edbc	932	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
AnnaBridge	171:3a7713b1edbc	933	}
AnnaBridge	171:3a7713b1edbc	934
AnnaBridge	171:3a7713b1edbc	935	/**
AnnaBridge	171:3a7713b1edbc	936	* @brief Disable Low Speed External (LSE) crystal.
AnnaBridge	171:3a7713b1edbc	937	* @rmtoll BDCR LSEON LL_RCC_LSE_Disable
AnnaBridge	171:3a7713b1edbc	938	* @retval None
AnnaBridge	171:3a7713b1edbc	939	*/
AnnaBridge	171:3a7713b1edbc	940	__STATIC_INLINE void LL_RCC_LSE_Disable(void)
AnnaBridge	171:3a7713b1edbc	941	{
AnnaBridge	171:3a7713b1edbc	942	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
AnnaBridge	171:3a7713b1edbc	943	}
AnnaBridge	171:3a7713b1edbc	944
AnnaBridge	171:3a7713b1edbc	945	/**
AnnaBridge	171:3a7713b1edbc	946	* @brief Enable external clock source (LSE bypass).
AnnaBridge	171:3a7713b1edbc	947	* @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
AnnaBridge	171:3a7713b1edbc	948	* @retval None
AnnaBridge	171:3a7713b1edbc	949	*/
AnnaBridge	171:3a7713b1edbc	950	__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
AnnaBridge	171:3a7713b1edbc	951	{
AnnaBridge	171:3a7713b1edbc	952	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
AnnaBridge	171:3a7713b1edbc	953	}
AnnaBridge	171:3a7713b1edbc	954
AnnaBridge	171:3a7713b1edbc	955	/**
AnnaBridge	171:3a7713b1edbc	956	* @brief Disable external clock source (LSE bypass).
AnnaBridge	171:3a7713b1edbc	957	* @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
AnnaBridge	171:3a7713b1edbc	958	* @retval None
AnnaBridge	171:3a7713b1edbc	959	*/
AnnaBridge	171:3a7713b1edbc	960	__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
AnnaBridge	171:3a7713b1edbc	961	{
AnnaBridge	171:3a7713b1edbc	962	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
AnnaBridge	171:3a7713b1edbc	963	}
AnnaBridge	171:3a7713b1edbc	964
AnnaBridge	171:3a7713b1edbc	965	/**
AnnaBridge	171:3a7713b1edbc	966	* @brief Check if LSE oscillator Ready
AnnaBridge	171:3a7713b1edbc	967	* @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
AnnaBridge	171:3a7713b1edbc	968	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	969	*/
AnnaBridge	171:3a7713b1edbc	970	__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
AnnaBridge	171:3a7713b1edbc	971	{
AnnaBridge	171:3a7713b1edbc	972	return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
AnnaBridge	171:3a7713b1edbc	973	}
AnnaBridge	171:3a7713b1edbc	974
AnnaBridge	171:3a7713b1edbc	975	/**
AnnaBridge	171:3a7713b1edbc	976	* @}
AnnaBridge	171:3a7713b1edbc	977	*/
AnnaBridge	171:3a7713b1edbc	978
AnnaBridge	171:3a7713b1edbc	979	/** @defgroup RCC_LL_EF_LSI LSI
AnnaBridge	171:3a7713b1edbc	980	* @{
AnnaBridge	171:3a7713b1edbc	981	*/
AnnaBridge	171:3a7713b1edbc	982
AnnaBridge	171:3a7713b1edbc	983	/**
AnnaBridge	171:3a7713b1edbc	984	* @brief Enable LSI Oscillator
AnnaBridge	171:3a7713b1edbc	985	* @rmtoll CSR LSION LL_RCC_LSI_Enable
AnnaBridge	171:3a7713b1edbc	986	* @retval None
AnnaBridge	171:3a7713b1edbc	987	*/
AnnaBridge	171:3a7713b1edbc	988	__STATIC_INLINE void LL_RCC_LSI_Enable(void)
AnnaBridge	171:3a7713b1edbc	989	{
AnnaBridge	171:3a7713b1edbc	990	SET_BIT(RCC->CSR, RCC_CSR_LSION);
AnnaBridge	171:3a7713b1edbc	991	}
AnnaBridge	171:3a7713b1edbc	992
AnnaBridge	171:3a7713b1edbc	993	/**
AnnaBridge	171:3a7713b1edbc	994	* @brief Disable LSI Oscillator
AnnaBridge	171:3a7713b1edbc	995	* @rmtoll CSR LSION LL_RCC_LSI_Disable
AnnaBridge	171:3a7713b1edbc	996	* @retval None
AnnaBridge	171:3a7713b1edbc	997	*/
AnnaBridge	171:3a7713b1edbc	998	__STATIC_INLINE void LL_RCC_LSI_Disable(void)
AnnaBridge	171:3a7713b1edbc	999	{
AnnaBridge	171:3a7713b1edbc	1000	CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
AnnaBridge	171:3a7713b1edbc	1001	}
AnnaBridge	171:3a7713b1edbc	1002
AnnaBridge	171:3a7713b1edbc	1003	/**
AnnaBridge	171:3a7713b1edbc	1004	* @brief Check if LSI is Ready
AnnaBridge	171:3a7713b1edbc	1005	* @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
AnnaBridge	171:3a7713b1edbc	1006	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1007	*/
AnnaBridge	171:3a7713b1edbc	1008	__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
AnnaBridge	171:3a7713b1edbc	1009	{
AnnaBridge	171:3a7713b1edbc	1010	return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
AnnaBridge	171:3a7713b1edbc	1011	}
AnnaBridge	171:3a7713b1edbc	1012
AnnaBridge	171:3a7713b1edbc	1013	/**
AnnaBridge	171:3a7713b1edbc	1014	* @}
AnnaBridge	171:3a7713b1edbc	1015	*/
AnnaBridge	171:3a7713b1edbc	1016
AnnaBridge	171:3a7713b1edbc	1017	/** @defgroup RCC_LL_EF_System System
AnnaBridge	171:3a7713b1edbc	1018	* @{
AnnaBridge	171:3a7713b1edbc	1019	*/
AnnaBridge	171:3a7713b1edbc	1020
AnnaBridge	171:3a7713b1edbc	1021	/**
AnnaBridge	171:3a7713b1edbc	1022	* @brief Configure the system clock source
AnnaBridge	171:3a7713b1edbc	1023	* @rmtoll CFGR SW LL_RCC_SetSysClkSource
AnnaBridge	171:3a7713b1edbc	1024	* @param Source This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1025	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
AnnaBridge	171:3a7713b1edbc	1026	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
AnnaBridge	171:3a7713b1edbc	1027	* @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
AnnaBridge	171:3a7713b1edbc	1028	* @retval None
AnnaBridge	171:3a7713b1edbc	1029	*/
AnnaBridge	171:3a7713b1edbc	1030	__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
AnnaBridge	171:3a7713b1edbc	1031	{
AnnaBridge	171:3a7713b1edbc	1032	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
AnnaBridge	171:3a7713b1edbc	1033	}
AnnaBridge	171:3a7713b1edbc	1034
AnnaBridge	171:3a7713b1edbc	1035	/**
AnnaBridge	171:3a7713b1edbc	1036	* @brief Get the system clock source
AnnaBridge	171:3a7713b1edbc	1037	* @rmtoll CFGR SWS LL_RCC_GetSysClkSource
AnnaBridge	171:3a7713b1edbc	1038	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1039	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
AnnaBridge	171:3a7713b1edbc	1040	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
AnnaBridge	171:3a7713b1edbc	1041	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
AnnaBridge	171:3a7713b1edbc	1042	*/
AnnaBridge	171:3a7713b1edbc	1043	__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
AnnaBridge	171:3a7713b1edbc	1044	{
AnnaBridge	171:3a7713b1edbc	1045	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
AnnaBridge	171:3a7713b1edbc	1046	}
AnnaBridge	171:3a7713b1edbc	1047
AnnaBridge	171:3a7713b1edbc	1048	/**
AnnaBridge	171:3a7713b1edbc	1049	* @brief Set AHB prescaler
AnnaBridge	171:3a7713b1edbc	1050	* @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
AnnaBridge	171:3a7713b1edbc	1051	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1052	* @arg @ref LL_RCC_SYSCLK_DIV_1
AnnaBridge	171:3a7713b1edbc	1053	* @arg @ref LL_RCC_SYSCLK_DIV_2
AnnaBridge	171:3a7713b1edbc	1054	* @arg @ref LL_RCC_SYSCLK_DIV_4
AnnaBridge	171:3a7713b1edbc	1055	* @arg @ref LL_RCC_SYSCLK_DIV_8
AnnaBridge	171:3a7713b1edbc	1056	* @arg @ref LL_RCC_SYSCLK_DIV_16
AnnaBridge	171:3a7713b1edbc	1057	* @arg @ref LL_RCC_SYSCLK_DIV_64
AnnaBridge	171:3a7713b1edbc	1058	* @arg @ref LL_RCC_SYSCLK_DIV_128
AnnaBridge	171:3a7713b1edbc	1059	* @arg @ref LL_RCC_SYSCLK_DIV_256
AnnaBridge	171:3a7713b1edbc	1060	* @arg @ref LL_RCC_SYSCLK_DIV_512
AnnaBridge	171:3a7713b1edbc	1061	* @retval None
AnnaBridge	171:3a7713b1edbc	1062	*/
AnnaBridge	171:3a7713b1edbc	1063	__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
AnnaBridge	171:3a7713b1edbc	1064	{
AnnaBridge	171:3a7713b1edbc	1065	MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
AnnaBridge	171:3a7713b1edbc	1066	}
AnnaBridge	171:3a7713b1edbc	1067
AnnaBridge	171:3a7713b1edbc	1068	/**
AnnaBridge	171:3a7713b1edbc	1069	* @brief Set APB1 prescaler
AnnaBridge	171:3a7713b1edbc	1070	* @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
AnnaBridge	171:3a7713b1edbc	1071	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1072	* @arg @ref LL_RCC_APB1_DIV_1
AnnaBridge	171:3a7713b1edbc	1073	* @arg @ref LL_RCC_APB1_DIV_2
AnnaBridge	171:3a7713b1edbc	1074	* @arg @ref LL_RCC_APB1_DIV_4
AnnaBridge	171:3a7713b1edbc	1075	* @arg @ref LL_RCC_APB1_DIV_8
AnnaBridge	171:3a7713b1edbc	1076	* @arg @ref LL_RCC_APB1_DIV_16
AnnaBridge	171:3a7713b1edbc	1077	* @retval None
AnnaBridge	171:3a7713b1edbc	1078	*/
AnnaBridge	171:3a7713b1edbc	1079	__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
AnnaBridge	171:3a7713b1edbc	1080	{
AnnaBridge	171:3a7713b1edbc	1081	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
AnnaBridge	171:3a7713b1edbc	1082	}
AnnaBridge	171:3a7713b1edbc	1083
AnnaBridge	171:3a7713b1edbc	1084	/**
AnnaBridge	171:3a7713b1edbc	1085	* @brief Set APB2 prescaler
AnnaBridge	171:3a7713b1edbc	1086	* @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
AnnaBridge	171:3a7713b1edbc	1087	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1088	* @arg @ref LL_RCC_APB2_DIV_1
AnnaBridge	171:3a7713b1edbc	1089	* @arg @ref LL_RCC_APB2_DIV_2
AnnaBridge	171:3a7713b1edbc	1090	* @arg @ref LL_RCC_APB2_DIV_4
AnnaBridge	171:3a7713b1edbc	1091	* @arg @ref LL_RCC_APB2_DIV_8
AnnaBridge	171:3a7713b1edbc	1092	* @arg @ref LL_RCC_APB2_DIV_16
AnnaBridge	171:3a7713b1edbc	1093	* @retval None
AnnaBridge	171:3a7713b1edbc	1094	*/
AnnaBridge	171:3a7713b1edbc	1095	__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
AnnaBridge	171:3a7713b1edbc	1096	{
AnnaBridge	171:3a7713b1edbc	1097	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
AnnaBridge	171:3a7713b1edbc	1098	}
AnnaBridge	171:3a7713b1edbc	1099
AnnaBridge	171:3a7713b1edbc	1100	/**
AnnaBridge	171:3a7713b1edbc	1101	* @brief Get AHB prescaler
AnnaBridge	171:3a7713b1edbc	1102	* @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
AnnaBridge	171:3a7713b1edbc	1103	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1104	* @arg @ref LL_RCC_SYSCLK_DIV_1
AnnaBridge	171:3a7713b1edbc	1105	* @arg @ref LL_RCC_SYSCLK_DIV_2
AnnaBridge	171:3a7713b1edbc	1106	* @arg @ref LL_RCC_SYSCLK_DIV_4
AnnaBridge	171:3a7713b1edbc	1107	* @arg @ref LL_RCC_SYSCLK_DIV_8
AnnaBridge	171:3a7713b1edbc	1108	* @arg @ref LL_RCC_SYSCLK_DIV_16
AnnaBridge	171:3a7713b1edbc	1109	* @arg @ref LL_RCC_SYSCLK_DIV_64
AnnaBridge	171:3a7713b1edbc	1110	* @arg @ref LL_RCC_SYSCLK_DIV_128
AnnaBridge	171:3a7713b1edbc	1111	* @arg @ref LL_RCC_SYSCLK_DIV_256
AnnaBridge	171:3a7713b1edbc	1112	* @arg @ref LL_RCC_SYSCLK_DIV_512
AnnaBridge	171:3a7713b1edbc	1113	*/
AnnaBridge	171:3a7713b1edbc	1114	__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
AnnaBridge	171:3a7713b1edbc	1115	{
AnnaBridge	171:3a7713b1edbc	1116	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
AnnaBridge	171:3a7713b1edbc	1117	}
AnnaBridge	171:3a7713b1edbc	1118
AnnaBridge	171:3a7713b1edbc	1119	/**
AnnaBridge	171:3a7713b1edbc	1120	* @brief Get APB1 prescaler
AnnaBridge	171:3a7713b1edbc	1121	* @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
AnnaBridge	171:3a7713b1edbc	1122	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1123	* @arg @ref LL_RCC_APB1_DIV_1
AnnaBridge	171:3a7713b1edbc	1124	* @arg @ref LL_RCC_APB1_DIV_2
AnnaBridge	171:3a7713b1edbc	1125	* @arg @ref LL_RCC_APB1_DIV_4
AnnaBridge	171:3a7713b1edbc	1126	* @arg @ref LL_RCC_APB1_DIV_8
AnnaBridge	171:3a7713b1edbc	1127	* @arg @ref LL_RCC_APB1_DIV_16
AnnaBridge	171:3a7713b1edbc	1128	*/
AnnaBridge	171:3a7713b1edbc	1129	__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
AnnaBridge	171:3a7713b1edbc	1130	{
AnnaBridge	171:3a7713b1edbc	1131	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
AnnaBridge	171:3a7713b1edbc	1132	}
AnnaBridge	171:3a7713b1edbc	1133
AnnaBridge	171:3a7713b1edbc	1134	/**
AnnaBridge	171:3a7713b1edbc	1135	* @brief Get APB2 prescaler
AnnaBridge	171:3a7713b1edbc	1136	* @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
AnnaBridge	171:3a7713b1edbc	1137	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1138	* @arg @ref LL_RCC_APB2_DIV_1
AnnaBridge	171:3a7713b1edbc	1139	* @arg @ref LL_RCC_APB2_DIV_2
AnnaBridge	171:3a7713b1edbc	1140	* @arg @ref LL_RCC_APB2_DIV_4
AnnaBridge	171:3a7713b1edbc	1141	* @arg @ref LL_RCC_APB2_DIV_8
AnnaBridge	171:3a7713b1edbc	1142	* @arg @ref LL_RCC_APB2_DIV_16
AnnaBridge	171:3a7713b1edbc	1143	*/
AnnaBridge	171:3a7713b1edbc	1144	__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
AnnaBridge	171:3a7713b1edbc	1145	{
AnnaBridge	171:3a7713b1edbc	1146	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
AnnaBridge	171:3a7713b1edbc	1147	}
AnnaBridge	171:3a7713b1edbc	1148
AnnaBridge	171:3a7713b1edbc	1149	/**
AnnaBridge	171:3a7713b1edbc	1150	* @}
AnnaBridge	171:3a7713b1edbc	1151	*/
AnnaBridge	171:3a7713b1edbc	1152
AnnaBridge	171:3a7713b1edbc	1153	/** @defgroup RCC_LL_EF_MCO MCO
AnnaBridge	171:3a7713b1edbc	1154	* @{
AnnaBridge	171:3a7713b1edbc	1155	*/
AnnaBridge	171:3a7713b1edbc	1156
AnnaBridge	171:3a7713b1edbc	1157	/**
AnnaBridge	171:3a7713b1edbc	1158	* @brief Configure MCOx
AnnaBridge	171:3a7713b1edbc	1159	* @rmtoll CFGR MCO LL_RCC_ConfigMCO
AnnaBridge	171:3a7713b1edbc	1160	* @param MCOxSource This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1161	* @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
AnnaBridge	171:3a7713b1edbc	1162	* @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
AnnaBridge	171:3a7713b1edbc	1163	* @arg @ref LL_RCC_MCO1SOURCE_HSI
AnnaBridge	171:3a7713b1edbc	1164	* @arg @ref LL_RCC_MCO1SOURCE_HSE
AnnaBridge	171:3a7713b1edbc	1165	* @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2
AnnaBridge	171:3a7713b1edbc	1166	* @arg @ref LL_RCC_MCO1SOURCE_PLL2CLK (*)
AnnaBridge	171:3a7713b1edbc	1167	* @arg @ref LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 (*)
AnnaBridge	171:3a7713b1edbc	1168	* @arg @ref LL_RCC_MCO1SOURCE_EXT_HSE (*)
AnnaBridge	171:3a7713b1edbc	1169	* @arg @ref LL_RCC_MCO1SOURCE_PLLI2SCLK (*)
AnnaBridge	171:3a7713b1edbc	1170	*
AnnaBridge	171:3a7713b1edbc	1171	* (*) value not defined in all devices
AnnaBridge	171:3a7713b1edbc	1172	* @retval None
AnnaBridge	171:3a7713b1edbc	1173	*/
AnnaBridge	171:3a7713b1edbc	1174	__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource)
AnnaBridge	171:3a7713b1edbc	1175	{
AnnaBridge	171:3a7713b1edbc	1176	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource);
AnnaBridge	171:3a7713b1edbc	1177	}
AnnaBridge	171:3a7713b1edbc	1178
AnnaBridge	171:3a7713b1edbc	1179	/**
AnnaBridge	171:3a7713b1edbc	1180	* @}
AnnaBridge	171:3a7713b1edbc	1181	*/
AnnaBridge	171:3a7713b1edbc	1182
AnnaBridge	171:3a7713b1edbc	1183	/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
AnnaBridge	171:3a7713b1edbc	1184	* @{
AnnaBridge	171:3a7713b1edbc	1185	*/
AnnaBridge	171:3a7713b1edbc	1186
AnnaBridge	171:3a7713b1edbc	1187	#if defined(RCC_CFGR2_I2S2SRC)
AnnaBridge	171:3a7713b1edbc	1188	/**
AnnaBridge	171:3a7713b1edbc	1189	* @brief Configure I2Sx clock source
AnnaBridge	171:3a7713b1edbc	1190	* @rmtoll CFGR2 I2S2SRC LL_RCC_SetI2SClockSource\n
AnnaBridge	171:3a7713b1edbc	1191	* CFGR2 I2S3SRC LL_RCC_SetI2SClockSource
AnnaBridge	171:3a7713b1edbc	1192	* @param I2SxSource This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1193	* @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK
AnnaBridge	171:3a7713b1edbc	1194	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO
AnnaBridge	171:3a7713b1edbc	1195	* @arg @ref LL_RCC_I2S3_CLKSOURCE_SYSCLK
AnnaBridge	171:3a7713b1edbc	1196	* @arg @ref LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO
AnnaBridge	171:3a7713b1edbc	1197	* @retval None
AnnaBridge	171:3a7713b1edbc	1198	*/
AnnaBridge	171:3a7713b1edbc	1199	__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
AnnaBridge	171:3a7713b1edbc	1200	{
AnnaBridge	171:3a7713b1edbc	1201	MODIFY_REG(RCC->CFGR2, (I2SxSource & 0xFFFF0000U), (I2SxSource << 16U));
AnnaBridge	171:3a7713b1edbc	1202	}
AnnaBridge	171:3a7713b1edbc	1203	#endif /* RCC_CFGR2_I2S2SRC */
AnnaBridge	171:3a7713b1edbc	1204
AnnaBridge	171:3a7713b1edbc	1205	#if defined(USB_OTG_FS) \|\| defined(USB)
AnnaBridge	171:3a7713b1edbc	1206	/**
AnnaBridge	171:3a7713b1edbc	1207	* @brief Configure USB clock source
AnnaBridge	171:3a7713b1edbc	1208	* @rmtoll CFGR OTGFSPRE LL_RCC_SetUSBClockSource\n
AnnaBridge	171:3a7713b1edbc	1209	* CFGR USBPRE LL_RCC_SetUSBClockSource
AnnaBridge	171:3a7713b1edbc	1210	* @param USBxSource This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1211	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL (*)
AnnaBridge	171:3a7713b1edbc	1212	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 (*)
AnnaBridge	171:3a7713b1edbc	1213	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_2 (*)
AnnaBridge	171:3a7713b1edbc	1214	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_3 (*)
AnnaBridge	171:3a7713b1edbc	1215	*
AnnaBridge	171:3a7713b1edbc	1216	* (*) value not defined in all devices
AnnaBridge	171:3a7713b1edbc	1217	* @retval None
AnnaBridge	171:3a7713b1edbc	1218	*/
AnnaBridge	171:3a7713b1edbc	1219	__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
AnnaBridge	171:3a7713b1edbc	1220	{
AnnaBridge	171:3a7713b1edbc	1221	#if defined(RCC_CFGR_USBPRE)
AnnaBridge	171:3a7713b1edbc	1222	MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, USBxSource);
AnnaBridge	171:3a7713b1edbc	1223	#else /RCC_CFGR_OTGFSPRE/
AnnaBridge	171:3a7713b1edbc	1224	MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, USBxSource);
AnnaBridge	171:3a7713b1edbc	1225	#endif /RCC_CFGR_USBPRE/
AnnaBridge	171:3a7713b1edbc	1226	}
AnnaBridge	171:3a7713b1edbc	1227	#endif /* USB_OTG_FS \|\| USB */
AnnaBridge	171:3a7713b1edbc	1228
AnnaBridge	171:3a7713b1edbc	1229	/**
AnnaBridge	171:3a7713b1edbc	1230	* @brief Configure ADC clock source
AnnaBridge	171:3a7713b1edbc	1231	* @rmtoll CFGR ADCPRE LL_RCC_SetADCClockSource
AnnaBridge	171:3a7713b1edbc	1232	* @param ADCxSource This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1233	* @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
AnnaBridge	171:3a7713b1edbc	1234	* @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
AnnaBridge	171:3a7713b1edbc	1235	* @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
AnnaBridge	171:3a7713b1edbc	1236	* @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
AnnaBridge	171:3a7713b1edbc	1237	* @retval None
AnnaBridge	171:3a7713b1edbc	1238	*/
AnnaBridge	171:3a7713b1edbc	1239	__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
AnnaBridge	171:3a7713b1edbc	1240	{
AnnaBridge	171:3a7713b1edbc	1241	MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, ADCxSource);
AnnaBridge	171:3a7713b1edbc	1242	}
AnnaBridge	171:3a7713b1edbc	1243
AnnaBridge	171:3a7713b1edbc	1244	#if defined(RCC_CFGR2_I2S2SRC)
AnnaBridge	171:3a7713b1edbc	1245	/**
AnnaBridge	171:3a7713b1edbc	1246	* @brief Get I2Sx clock source
AnnaBridge	171:3a7713b1edbc	1247	* @rmtoll CFGR2 I2S2SRC LL_RCC_GetI2SClockSource\n
AnnaBridge	171:3a7713b1edbc	1248	* CFGR2 I2S3SRC LL_RCC_GetI2SClockSource
AnnaBridge	171:3a7713b1edbc	1249	* @param I2Sx This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1250	* @arg @ref LL_RCC_I2S2_CLKSOURCE
AnnaBridge	171:3a7713b1edbc	1251	* @arg @ref LL_RCC_I2S3_CLKSOURCE
AnnaBridge	171:3a7713b1edbc	1252	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1253	* @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK
AnnaBridge	171:3a7713b1edbc	1254	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO
AnnaBridge	171:3a7713b1edbc	1255	* @arg @ref LL_RCC_I2S3_CLKSOURCE_SYSCLK
AnnaBridge	171:3a7713b1edbc	1256	* @arg @ref LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO
AnnaBridge	171:3a7713b1edbc	1257	*/
AnnaBridge	171:3a7713b1edbc	1258	__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
AnnaBridge	171:3a7713b1edbc	1259	{
AnnaBridge	171:3a7713b1edbc	1260	return (uint32_t)(READ_BIT(RCC->CFGR2, I2Sx) >> 16U \| I2Sx);
AnnaBridge	171:3a7713b1edbc	1261	}
AnnaBridge	171:3a7713b1edbc	1262	#endif /* RCC_CFGR2_I2S2SRC */
AnnaBridge	171:3a7713b1edbc	1263
AnnaBridge	171:3a7713b1edbc	1264	#if defined(USB_OTG_FS) \|\| defined(USB)
AnnaBridge	171:3a7713b1edbc	1265	/**
AnnaBridge	171:3a7713b1edbc	1266	* @brief Get USBx clock source
AnnaBridge	171:3a7713b1edbc	1267	* @rmtoll CFGR OTGFSPRE LL_RCC_GetUSBClockSource\n
AnnaBridge	171:3a7713b1edbc	1268	* CFGR USBPRE LL_RCC_GetUSBClockSource
AnnaBridge	171:3a7713b1edbc	1269	* @param USBx This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1270	* @arg @ref LL_RCC_USB_CLKSOURCE
AnnaBridge	171:3a7713b1edbc	1271	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1272	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL (*)
AnnaBridge	171:3a7713b1edbc	1273	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 (*)
AnnaBridge	171:3a7713b1edbc	1274	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_2 (*)
AnnaBridge	171:3a7713b1edbc	1275	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_3 (*)
AnnaBridge	171:3a7713b1edbc	1276	*
AnnaBridge	171:3a7713b1edbc	1277	* (*) value not defined in all devices
AnnaBridge	171:3a7713b1edbc	1278	*/
AnnaBridge	171:3a7713b1edbc	1279	__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
AnnaBridge	171:3a7713b1edbc	1280	{
AnnaBridge	171:3a7713b1edbc	1281	return (uint32_t)(READ_BIT(RCC->CFGR, USBx));
AnnaBridge	171:3a7713b1edbc	1282	}
AnnaBridge	171:3a7713b1edbc	1283	#endif /* USB_OTG_FS \|\| USB */
AnnaBridge	171:3a7713b1edbc	1284
AnnaBridge	171:3a7713b1edbc	1285	/**
AnnaBridge	171:3a7713b1edbc	1286	* @brief Get ADCx clock source
AnnaBridge	171:3a7713b1edbc	1287	* @rmtoll CFGR ADCPRE LL_RCC_GetADCClockSource
AnnaBridge	171:3a7713b1edbc	1288	* @param ADCx This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1289	* @arg @ref LL_RCC_ADC_CLKSOURCE
AnnaBridge	171:3a7713b1edbc	1290	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1291	* @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
AnnaBridge	171:3a7713b1edbc	1292	* @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
AnnaBridge	171:3a7713b1edbc	1293	* @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
AnnaBridge	171:3a7713b1edbc	1294	* @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
AnnaBridge	171:3a7713b1edbc	1295	*/
AnnaBridge	171:3a7713b1edbc	1296	__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
AnnaBridge	171:3a7713b1edbc	1297	{
AnnaBridge	171:3a7713b1edbc	1298	return (uint32_t)(READ_BIT(RCC->CFGR, ADCx));
AnnaBridge	171:3a7713b1edbc	1299	}
AnnaBridge	171:3a7713b1edbc	1300
AnnaBridge	171:3a7713b1edbc	1301	/**
AnnaBridge	171:3a7713b1edbc	1302	* @}
AnnaBridge	171:3a7713b1edbc	1303	*/
AnnaBridge	171:3a7713b1edbc	1304
AnnaBridge	171:3a7713b1edbc	1305	/** @defgroup RCC_LL_EF_RTC RTC
AnnaBridge	171:3a7713b1edbc	1306	* @{
AnnaBridge	171:3a7713b1edbc	1307	*/
AnnaBridge	171:3a7713b1edbc	1308
AnnaBridge	171:3a7713b1edbc	1309	/**
AnnaBridge	171:3a7713b1edbc	1310	* @brief Set RTC Clock Source
AnnaBridge	171:3a7713b1edbc	1311	* @note Once the RTC clock source has been selected, it cannot be changed any more unless
AnnaBridge	171:3a7713b1edbc	1312	* the Backup domain is reset. The BDRST bit can be used to reset them.
AnnaBridge	171:3a7713b1edbc	1313	* @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
AnnaBridge	171:3a7713b1edbc	1314	* @param Source This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1315	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
AnnaBridge	171:3a7713b1edbc	1316	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
AnnaBridge	171:3a7713b1edbc	1317	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
AnnaBridge	171:3a7713b1edbc	1318	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128
AnnaBridge	171:3a7713b1edbc	1319	* @retval None
AnnaBridge	171:3a7713b1edbc	1320	*/
AnnaBridge	171:3a7713b1edbc	1321	__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
AnnaBridge	171:3a7713b1edbc	1322	{
AnnaBridge	171:3a7713b1edbc	1323	MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
AnnaBridge	171:3a7713b1edbc	1324	}
AnnaBridge	171:3a7713b1edbc	1325
AnnaBridge	171:3a7713b1edbc	1326	/**
AnnaBridge	171:3a7713b1edbc	1327	* @brief Get RTC Clock Source
AnnaBridge	171:3a7713b1edbc	1328	* @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
AnnaBridge	171:3a7713b1edbc	1329	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1330	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
AnnaBridge	171:3a7713b1edbc	1331	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
AnnaBridge	171:3a7713b1edbc	1332	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
AnnaBridge	171:3a7713b1edbc	1333	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128
AnnaBridge	171:3a7713b1edbc	1334	*/
AnnaBridge	171:3a7713b1edbc	1335	__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
AnnaBridge	171:3a7713b1edbc	1336	{
AnnaBridge	171:3a7713b1edbc	1337	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
AnnaBridge	171:3a7713b1edbc	1338	}
AnnaBridge	171:3a7713b1edbc	1339
AnnaBridge	171:3a7713b1edbc	1340	/**
AnnaBridge	171:3a7713b1edbc	1341	* @brief Enable RTC
AnnaBridge	171:3a7713b1edbc	1342	* @rmtoll BDCR RTCEN LL_RCC_EnableRTC
AnnaBridge	171:3a7713b1edbc	1343	* @retval None
AnnaBridge	171:3a7713b1edbc	1344	*/
AnnaBridge	171:3a7713b1edbc	1345	__STATIC_INLINE void LL_RCC_EnableRTC(void)
AnnaBridge	171:3a7713b1edbc	1346	{
AnnaBridge	171:3a7713b1edbc	1347	SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
AnnaBridge	171:3a7713b1edbc	1348	}
AnnaBridge	171:3a7713b1edbc	1349
AnnaBridge	171:3a7713b1edbc	1350	/**
AnnaBridge	171:3a7713b1edbc	1351	* @brief Disable RTC
AnnaBridge	171:3a7713b1edbc	1352	* @rmtoll BDCR RTCEN LL_RCC_DisableRTC
AnnaBridge	171:3a7713b1edbc	1353	* @retval None
AnnaBridge	171:3a7713b1edbc	1354	*/
AnnaBridge	171:3a7713b1edbc	1355	__STATIC_INLINE void LL_RCC_DisableRTC(void)
AnnaBridge	171:3a7713b1edbc	1356	{
AnnaBridge	171:3a7713b1edbc	1357	CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
AnnaBridge	171:3a7713b1edbc	1358	}
AnnaBridge	171:3a7713b1edbc	1359
AnnaBridge	171:3a7713b1edbc	1360	/**
AnnaBridge	171:3a7713b1edbc	1361	* @brief Check if RTC has been enabled or not
AnnaBridge	171:3a7713b1edbc	1362	* @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
AnnaBridge	171:3a7713b1edbc	1363	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1364	*/
AnnaBridge	171:3a7713b1edbc	1365	__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
AnnaBridge	171:3a7713b1edbc	1366	{
AnnaBridge	171:3a7713b1edbc	1367	return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
AnnaBridge	171:3a7713b1edbc	1368	}
AnnaBridge	171:3a7713b1edbc	1369
AnnaBridge	171:3a7713b1edbc	1370	/**
AnnaBridge	171:3a7713b1edbc	1371	* @brief Force the Backup domain reset
AnnaBridge	171:3a7713b1edbc	1372	* @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
AnnaBridge	171:3a7713b1edbc	1373	* @retval None
AnnaBridge	171:3a7713b1edbc	1374	*/
AnnaBridge	171:3a7713b1edbc	1375	__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
AnnaBridge	171:3a7713b1edbc	1376	{
AnnaBridge	171:3a7713b1edbc	1377	SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
AnnaBridge	171:3a7713b1edbc	1378	}
AnnaBridge	171:3a7713b1edbc	1379
AnnaBridge	171:3a7713b1edbc	1380	/**
AnnaBridge	171:3a7713b1edbc	1381	* @brief Release the Backup domain reset
AnnaBridge	171:3a7713b1edbc	1382	* @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
AnnaBridge	171:3a7713b1edbc	1383	* @retval None
AnnaBridge	171:3a7713b1edbc	1384	*/
AnnaBridge	171:3a7713b1edbc	1385	__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
AnnaBridge	171:3a7713b1edbc	1386	{
AnnaBridge	171:3a7713b1edbc	1387	CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
AnnaBridge	171:3a7713b1edbc	1388	}
AnnaBridge	171:3a7713b1edbc	1389
AnnaBridge	171:3a7713b1edbc	1390	/**
AnnaBridge	171:3a7713b1edbc	1391	* @}
AnnaBridge	171:3a7713b1edbc	1392	*/
AnnaBridge	171:3a7713b1edbc	1393
AnnaBridge	171:3a7713b1edbc	1394	/** @defgroup RCC_LL_EF_PLL PLL
AnnaBridge	171:3a7713b1edbc	1395	* @{
AnnaBridge	171:3a7713b1edbc	1396	*/
AnnaBridge	171:3a7713b1edbc	1397
AnnaBridge	171:3a7713b1edbc	1398	/**
AnnaBridge	171:3a7713b1edbc	1399	* @brief Enable PLL
AnnaBridge	171:3a7713b1edbc	1400	* @rmtoll CR PLLON LL_RCC_PLL_Enable
AnnaBridge	171:3a7713b1edbc	1401	* @retval None
AnnaBridge	171:3a7713b1edbc	1402	*/
AnnaBridge	171:3a7713b1edbc	1403	__STATIC_INLINE void LL_RCC_PLL_Enable(void)
AnnaBridge	171:3a7713b1edbc	1404	{
AnnaBridge	171:3a7713b1edbc	1405	SET_BIT(RCC->CR, RCC_CR_PLLON);
AnnaBridge	171:3a7713b1edbc	1406	}
AnnaBridge	171:3a7713b1edbc	1407
AnnaBridge	171:3a7713b1edbc	1408	/**
AnnaBridge	171:3a7713b1edbc	1409	* @brief Disable PLL
AnnaBridge	171:3a7713b1edbc	1410	* @note Cannot be disabled if the PLL clock is used as the system clock
AnnaBridge	171:3a7713b1edbc	1411	* @rmtoll CR PLLON LL_RCC_PLL_Disable
AnnaBridge	171:3a7713b1edbc	1412	* @retval None
AnnaBridge	171:3a7713b1edbc	1413	*/
AnnaBridge	171:3a7713b1edbc	1414	__STATIC_INLINE void LL_RCC_PLL_Disable(void)
AnnaBridge	171:3a7713b1edbc	1415	{
AnnaBridge	171:3a7713b1edbc	1416	CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
AnnaBridge	171:3a7713b1edbc	1417	}
AnnaBridge	171:3a7713b1edbc	1418
AnnaBridge	171:3a7713b1edbc	1419	/**
AnnaBridge	171:3a7713b1edbc	1420	* @brief Check if PLL Ready
AnnaBridge	171:3a7713b1edbc	1421	* @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
AnnaBridge	171:3a7713b1edbc	1422	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1423	*/
AnnaBridge	171:3a7713b1edbc	1424	__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
AnnaBridge	171:3a7713b1edbc	1425	{
AnnaBridge	171:3a7713b1edbc	1426	return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
AnnaBridge	171:3a7713b1edbc	1427	}
AnnaBridge	171:3a7713b1edbc	1428
AnnaBridge	171:3a7713b1edbc	1429	/**
AnnaBridge	171:3a7713b1edbc	1430	* @brief Configure PLL used for SYSCLK Domain
AnnaBridge	171:3a7713b1edbc	1431	* @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
AnnaBridge	171:3a7713b1edbc	1432	* CFGR PLLXTPRE LL_RCC_PLL_ConfigDomain_SYS\n
AnnaBridge	171:3a7713b1edbc	1433	* CFGR PLLMULL LL_RCC_PLL_ConfigDomain_SYS\n
AnnaBridge	171:3a7713b1edbc	1434	* CFGR2 PREDIV1 LL_RCC_PLL_ConfigDomain_SYS\n
AnnaBridge	171:3a7713b1edbc	1435	* CFGR2 PREDIV1SRC LL_RCC_PLL_ConfigDomain_SYS
AnnaBridge	171:3a7713b1edbc	1436	* @param Source This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1437	* @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2
AnnaBridge	171:3a7713b1edbc	1438	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1
AnnaBridge	171:3a7713b1edbc	1439	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2 (*)
AnnaBridge	171:3a7713b1edbc	1440	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3 (*)
AnnaBridge	171:3a7713b1edbc	1441	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4 (*)
AnnaBridge	171:3a7713b1edbc	1442	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5 (*)
AnnaBridge	171:3a7713b1edbc	1443	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6 (*)
AnnaBridge	171:3a7713b1edbc	1444	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7 (*)
AnnaBridge	171:3a7713b1edbc	1445	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8 (*)
AnnaBridge	171:3a7713b1edbc	1446	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9 (*)
AnnaBridge	171:3a7713b1edbc	1447	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10 (*)
AnnaBridge	171:3a7713b1edbc	1448	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11 (*)
AnnaBridge	171:3a7713b1edbc	1449	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12 (*)
AnnaBridge	171:3a7713b1edbc	1450	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13 (*)
AnnaBridge	171:3a7713b1edbc	1451	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14 (*)
AnnaBridge	171:3a7713b1edbc	1452	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15 (*)
AnnaBridge	171:3a7713b1edbc	1453	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16 (*)
AnnaBridge	171:3a7713b1edbc	1454	* @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_1 (*)
AnnaBridge	171:3a7713b1edbc	1455	* @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_2 (*)
AnnaBridge	171:3a7713b1edbc	1456	* @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_3 (*)
AnnaBridge	171:3a7713b1edbc	1457	* @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_4 (*)
AnnaBridge	171:3a7713b1edbc	1458	* @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_5 (*)
AnnaBridge	171:3a7713b1edbc	1459	* @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_6 (*)
AnnaBridge	171:3a7713b1edbc	1460	* @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_7 (*)
AnnaBridge	171:3a7713b1edbc	1461	* @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_8 (*)
AnnaBridge	171:3a7713b1edbc	1462	* @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_9 (*)
AnnaBridge	171:3a7713b1edbc	1463	* @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_10 (*)
AnnaBridge	171:3a7713b1edbc	1464	* @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_11 (*)
AnnaBridge	171:3a7713b1edbc	1465	* @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_12 (*)
AnnaBridge	171:3a7713b1edbc	1466	* @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_13 (*)
AnnaBridge	171:3a7713b1edbc	1467	* @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_14 (*)
AnnaBridge	171:3a7713b1edbc	1468	* @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_15 (*)
AnnaBridge	171:3a7713b1edbc	1469	* @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_16 (*)
AnnaBridge	171:3a7713b1edbc	1470	*
AnnaBridge	171:3a7713b1edbc	1471	* (*) value not defined in all devices
AnnaBridge	171:3a7713b1edbc	1472	* @param PLLMul This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1473	* @arg @ref LL_RCC_PLL_MUL_2 (*)
AnnaBridge	171:3a7713b1edbc	1474	* @arg @ref LL_RCC_PLL_MUL_3 (*)
AnnaBridge	171:3a7713b1edbc	1475	* @arg @ref LL_RCC_PLL_MUL_4
AnnaBridge	171:3a7713b1edbc	1476	* @arg @ref LL_RCC_PLL_MUL_5
AnnaBridge	171:3a7713b1edbc	1477	* @arg @ref LL_RCC_PLL_MUL_6
AnnaBridge	171:3a7713b1edbc	1478	* @arg @ref LL_RCC_PLL_MUL_7
AnnaBridge	171:3a7713b1edbc	1479	* @arg @ref LL_RCC_PLL_MUL_8
AnnaBridge	171:3a7713b1edbc	1480	* @arg @ref LL_RCC_PLL_MUL_9
AnnaBridge	171:3a7713b1edbc	1481	* @arg @ref LL_RCC_PLL_MUL_6_5 (*)
AnnaBridge	171:3a7713b1edbc	1482	* @arg @ref LL_RCC_PLL_MUL_10 (*)
AnnaBridge	171:3a7713b1edbc	1483	* @arg @ref LL_RCC_PLL_MUL_11 (*)
AnnaBridge	171:3a7713b1edbc	1484	* @arg @ref LL_RCC_PLL_MUL_12 (*)
AnnaBridge	171:3a7713b1edbc	1485	* @arg @ref LL_RCC_PLL_MUL_13 (*)
AnnaBridge	171:3a7713b1edbc	1486	* @arg @ref LL_RCC_PLL_MUL_14 (*)
AnnaBridge	171:3a7713b1edbc	1487	* @arg @ref LL_RCC_PLL_MUL_15 (*)
AnnaBridge	171:3a7713b1edbc	1488	* @arg @ref LL_RCC_PLL_MUL_16 (*)
AnnaBridge	171:3a7713b1edbc	1489	*
AnnaBridge	171:3a7713b1edbc	1490	* (*) value not defined in all devices
AnnaBridge	171:3a7713b1edbc	1491	* @retval None
AnnaBridge	171:3a7713b1edbc	1492	*/
AnnaBridge	171:3a7713b1edbc	1493	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul)
AnnaBridge	171:3a7713b1edbc	1494	{
AnnaBridge	171:3a7713b1edbc	1495	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC \| RCC_CFGR_PLLXTPRE \| RCC_CFGR_PLLMULL,
AnnaBridge	171:3a7713b1edbc	1496	(Source & (RCC_CFGR_PLLSRC \| RCC_CFGR_PLLXTPRE)) \| PLLMul);
AnnaBridge	171:3a7713b1edbc	1497	#if defined(RCC_CFGR2_PREDIV1)
AnnaBridge	171:3a7713b1edbc	1498	#if defined(RCC_CFGR2_PREDIV1SRC)
AnnaBridge	171:3a7713b1edbc	1499	MODIFY_REG(RCC->CFGR2, (RCC_CFGR2_PREDIV1 \| RCC_CFGR2_PREDIV1SRC),
AnnaBridge	171:3a7713b1edbc	1500	(Source & RCC_CFGR2_PREDIV1) \| ((Source & (RCC_CFGR2_PREDIV1SRC << 4U)) >> 4U));
AnnaBridge	171:3a7713b1edbc	1501	#else
AnnaBridge	171:3a7713b1edbc	1502	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (Source & RCC_CFGR2_PREDIV1));
AnnaBridge	171:3a7713b1edbc	1503	#endif /RCC_CFGR2_PREDIV1SRC/
AnnaBridge	171:3a7713b1edbc	1504	#endif /RCC_CFGR2_PREDIV1/
AnnaBridge	171:3a7713b1edbc	1505	}
AnnaBridge	171:3a7713b1edbc	1506
AnnaBridge	171:3a7713b1edbc	1507	/**
AnnaBridge	171:3a7713b1edbc	1508	* @brief Configure PLL clock source
AnnaBridge	171:3a7713b1edbc	1509	* @rmtoll CFGR PLLSRC LL_RCC_PLL_SetMainSource\n
AnnaBridge	171:3a7713b1edbc	1510	* CFGR2 PREDIV1SRC LL_RCC_PLL_SetMainSource
AnnaBridge	171:3a7713b1edbc	1511	* @param PLLSource This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1512	* @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2
AnnaBridge	171:3a7713b1edbc	1513	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	171:3a7713b1edbc	1514	* @arg @ref LL_RCC_PLLSOURCE_PLL2 (*)
AnnaBridge	171:3a7713b1edbc	1515	* @retval None
AnnaBridge	171:3a7713b1edbc	1516	*/
AnnaBridge	171:3a7713b1edbc	1517	__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
AnnaBridge	171:3a7713b1edbc	1518	{
AnnaBridge	171:3a7713b1edbc	1519	#if defined(RCC_CFGR2_PREDIV1SRC)
AnnaBridge	171:3a7713b1edbc	1520	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC, ((PLLSource & (RCC_CFGR2_PREDIV1SRC << 4U)) >> 4U));
AnnaBridge	171:3a7713b1edbc	1521	#endif /* RCC_CFGR2_PREDIV1SRC */
AnnaBridge	171:3a7713b1edbc	1522	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC, PLLSource);
AnnaBridge	171:3a7713b1edbc	1523	}
AnnaBridge	171:3a7713b1edbc	1524
AnnaBridge	171:3a7713b1edbc	1525	/**
AnnaBridge	171:3a7713b1edbc	1526	* @brief Get the oscillator used as PLL clock source.
AnnaBridge	171:3a7713b1edbc	1527	* @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource\n
AnnaBridge	171:3a7713b1edbc	1528	* CFGR2 PREDIV1SRC LL_RCC_PLL_GetMainSource
AnnaBridge	171:3a7713b1edbc	1529	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1530	* @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2
AnnaBridge	171:3a7713b1edbc	1531	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	171:3a7713b1edbc	1532	* @arg @ref LL_RCC_PLLSOURCE_PLL2 (*)
AnnaBridge	171:3a7713b1edbc	1533	*
AnnaBridge	171:3a7713b1edbc	1534	* (*) value not defined in all devices
AnnaBridge	171:3a7713b1edbc	1535	*/
AnnaBridge	171:3a7713b1edbc	1536	__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
AnnaBridge	171:3a7713b1edbc	1537	{
AnnaBridge	171:3a7713b1edbc	1538	#if defined(RCC_CFGR2_PREDIV1SRC)
AnnaBridge	171:3a7713b1edbc	1539	register uint32_t pllsrc = READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC);
AnnaBridge	171:3a7713b1edbc	1540	register uint32_t predivsrc = (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC) << 4U);
AnnaBridge	171:3a7713b1edbc	1541	return (uint32_t)(pllsrc \| predivsrc);
AnnaBridge	171:3a7713b1edbc	1542	#else
AnnaBridge	171:3a7713b1edbc	1543	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC));
AnnaBridge	171:3a7713b1edbc	1544	#endif /RCC_CFGR2_PREDIV1SRC/
AnnaBridge	171:3a7713b1edbc	1545	}
AnnaBridge	171:3a7713b1edbc	1546
AnnaBridge	171:3a7713b1edbc	1547	/**
AnnaBridge	171:3a7713b1edbc	1548	* @brief Get PLL multiplication Factor
AnnaBridge	171:3a7713b1edbc	1549	* @rmtoll CFGR PLLMULL LL_RCC_PLL_GetMultiplicator
AnnaBridge	171:3a7713b1edbc	1550	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1551	* @arg @ref LL_RCC_PLL_MUL_2 (*)
AnnaBridge	171:3a7713b1edbc	1552	* @arg @ref LL_RCC_PLL_MUL_3 (*)
AnnaBridge	171:3a7713b1edbc	1553	* @arg @ref LL_RCC_PLL_MUL_4
AnnaBridge	171:3a7713b1edbc	1554	* @arg @ref LL_RCC_PLL_MUL_5
AnnaBridge	171:3a7713b1edbc	1555	* @arg @ref LL_RCC_PLL_MUL_6
AnnaBridge	171:3a7713b1edbc	1556	* @arg @ref LL_RCC_PLL_MUL_7
AnnaBridge	171:3a7713b1edbc	1557	* @arg @ref LL_RCC_PLL_MUL_8
AnnaBridge	171:3a7713b1edbc	1558	* @arg @ref LL_RCC_PLL_MUL_9
AnnaBridge	171:3a7713b1edbc	1559	* @arg @ref LL_RCC_PLL_MUL_6_5 (*)
AnnaBridge	171:3a7713b1edbc	1560	* @arg @ref LL_RCC_PLL_MUL_10 (*)
AnnaBridge	171:3a7713b1edbc	1561	* @arg @ref LL_RCC_PLL_MUL_11 (*)
AnnaBridge	171:3a7713b1edbc	1562	* @arg @ref LL_RCC_PLL_MUL_12 (*)
AnnaBridge	171:3a7713b1edbc	1563	* @arg @ref LL_RCC_PLL_MUL_13 (*)
AnnaBridge	171:3a7713b1edbc	1564	* @arg @ref LL_RCC_PLL_MUL_14 (*)
AnnaBridge	171:3a7713b1edbc	1565	* @arg @ref LL_RCC_PLL_MUL_15 (*)
AnnaBridge	171:3a7713b1edbc	1566	* @arg @ref LL_RCC_PLL_MUL_16 (*)
AnnaBridge	171:3a7713b1edbc	1567	*
AnnaBridge	171:3a7713b1edbc	1568	* (*) value not defined in all devices
AnnaBridge	171:3a7713b1edbc	1569	*/
AnnaBridge	171:3a7713b1edbc	1570	__STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void)
AnnaBridge	171:3a7713b1edbc	1571	{
AnnaBridge	171:3a7713b1edbc	1572	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMULL));
AnnaBridge	171:3a7713b1edbc	1573	}
AnnaBridge	171:3a7713b1edbc	1574
AnnaBridge	171:3a7713b1edbc	1575	/**
AnnaBridge	171:3a7713b1edbc	1576	* @brief Get PREDIV1 division factor for the main PLL
AnnaBridge	171:3a7713b1edbc	1577	* @note They can be written only when the PLL is disabled
AnnaBridge	171:3a7713b1edbc	1578	* @rmtoll CFGR2 PREDIV1 LL_RCC_PLL_GetPrediv\n
AnnaBridge	171:3a7713b1edbc	1579	* CFGR2 PLLXTPRE LL_RCC_PLL_GetPrediv
AnnaBridge	171:3a7713b1edbc	1580	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1581	* @arg @ref LL_RCC_PREDIV_DIV_1
AnnaBridge	171:3a7713b1edbc	1582	* @arg @ref LL_RCC_PREDIV_DIV_2
AnnaBridge	171:3a7713b1edbc	1583	* @arg @ref LL_RCC_PREDIV_DIV_3 (*)
AnnaBridge	171:3a7713b1edbc	1584	* @arg @ref LL_RCC_PREDIV_DIV_4 (*)
AnnaBridge	171:3a7713b1edbc	1585	* @arg @ref LL_RCC_PREDIV_DIV_5 (*)
AnnaBridge	171:3a7713b1edbc	1586	* @arg @ref LL_RCC_PREDIV_DIV_6 (*)
AnnaBridge	171:3a7713b1edbc	1587	* @arg @ref LL_RCC_PREDIV_DIV_7 (*)
AnnaBridge	171:3a7713b1edbc	1588	* @arg @ref LL_RCC_PREDIV_DIV_8 (*)
AnnaBridge	171:3a7713b1edbc	1589	* @arg @ref LL_RCC_PREDIV_DIV_9 (*)
AnnaBridge	171:3a7713b1edbc	1590	* @arg @ref LL_RCC_PREDIV_DIV_10 (*)
AnnaBridge	171:3a7713b1edbc	1591	* @arg @ref LL_RCC_PREDIV_DIV_11 (*)
AnnaBridge	171:3a7713b1edbc	1592	* @arg @ref LL_RCC_PREDIV_DIV_12 (*)
AnnaBridge	171:3a7713b1edbc	1593	* @arg @ref LL_RCC_PREDIV_DIV_13 (*)
AnnaBridge	171:3a7713b1edbc	1594	* @arg @ref LL_RCC_PREDIV_DIV_14 (*)
AnnaBridge	171:3a7713b1edbc	1595	* @arg @ref LL_RCC_PREDIV_DIV_15 (*)
AnnaBridge	171:3a7713b1edbc	1596	* @arg @ref LL_RCC_PREDIV_DIV_16 (*)
AnnaBridge	171:3a7713b1edbc	1597	*
AnnaBridge	171:3a7713b1edbc	1598	* (*) value not defined in all devices
AnnaBridge	171:3a7713b1edbc	1599	*/
AnnaBridge	171:3a7713b1edbc	1600	__STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void)
AnnaBridge	171:3a7713b1edbc	1601	{
AnnaBridge	171:3a7713b1edbc	1602	#if defined(RCC_CFGR2_PREDIV1)
AnnaBridge	171:3a7713b1edbc	1603	return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1));
AnnaBridge	171:3a7713b1edbc	1604	#else
AnnaBridge	171:3a7713b1edbc	1605	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE));
AnnaBridge	171:3a7713b1edbc	1606	#endif /RCC_CFGR2_PREDIV1/
AnnaBridge	171:3a7713b1edbc	1607	}
AnnaBridge	171:3a7713b1edbc	1608
AnnaBridge	171:3a7713b1edbc	1609	/**
AnnaBridge	171:3a7713b1edbc	1610	* @}
AnnaBridge	171:3a7713b1edbc	1611	*/
AnnaBridge	171:3a7713b1edbc	1612
AnnaBridge	171:3a7713b1edbc	1613	#if defined(RCC_PLLI2S_SUPPORT)
AnnaBridge	171:3a7713b1edbc	1614	/** @defgroup RCC_LL_EF_PLLI2S PLLI2S
AnnaBridge	171:3a7713b1edbc	1615	* @{
AnnaBridge	171:3a7713b1edbc	1616	*/
AnnaBridge	171:3a7713b1edbc	1617
AnnaBridge	171:3a7713b1edbc	1618	/**
AnnaBridge	171:3a7713b1edbc	1619	* @brief Enable PLLI2S
AnnaBridge	171:3a7713b1edbc	1620	* @rmtoll CR PLL3ON LL_RCC_PLLI2S_Enable
AnnaBridge	171:3a7713b1edbc	1621	* @retval None
AnnaBridge	171:3a7713b1edbc	1622	*/
AnnaBridge	171:3a7713b1edbc	1623	__STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
AnnaBridge	171:3a7713b1edbc	1624	{
AnnaBridge	171:3a7713b1edbc	1625	SET_BIT(RCC->CR, RCC_CR_PLL3ON);
AnnaBridge	171:3a7713b1edbc	1626	}
AnnaBridge	171:3a7713b1edbc	1627
AnnaBridge	171:3a7713b1edbc	1628	/**
AnnaBridge	171:3a7713b1edbc	1629	* @brief Disable PLLI2S
AnnaBridge	171:3a7713b1edbc	1630	* @rmtoll CR PLL3ON LL_RCC_PLLI2S_Disable
AnnaBridge	171:3a7713b1edbc	1631	* @retval None
AnnaBridge	171:3a7713b1edbc	1632	*/
AnnaBridge	171:3a7713b1edbc	1633	__STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
AnnaBridge	171:3a7713b1edbc	1634	{
AnnaBridge	171:3a7713b1edbc	1635	CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
AnnaBridge	171:3a7713b1edbc	1636	}
AnnaBridge	171:3a7713b1edbc	1637
AnnaBridge	171:3a7713b1edbc	1638	/**
AnnaBridge	171:3a7713b1edbc	1639	* @brief Check if PLLI2S Ready
AnnaBridge	171:3a7713b1edbc	1640	* @rmtoll CR PLL3RDY LL_RCC_PLLI2S_IsReady
AnnaBridge	171:3a7713b1edbc	1641	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1642	*/
AnnaBridge	171:3a7713b1edbc	1643	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
AnnaBridge	171:3a7713b1edbc	1644	{
AnnaBridge	171:3a7713b1edbc	1645	return (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == (RCC_CR_PLL3RDY));
AnnaBridge	171:3a7713b1edbc	1646	}
AnnaBridge	171:3a7713b1edbc	1647
AnnaBridge	171:3a7713b1edbc	1648	/**
AnnaBridge	171:3a7713b1edbc	1649	* @brief Configure PLLI2S used for I2S Domain
AnnaBridge	171:3a7713b1edbc	1650	* @rmtoll CFGR2 PREDIV2 LL_RCC_PLL_ConfigDomain_PLLI2S\n
AnnaBridge	171:3a7713b1edbc	1651	* CFGR2 PLL3MUL LL_RCC_PLL_ConfigDomain_PLLI2S
AnnaBridge	171:3a7713b1edbc	1652	* @param Divider This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1653	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
AnnaBridge	171:3a7713b1edbc	1654	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
AnnaBridge	171:3a7713b1edbc	1655	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
AnnaBridge	171:3a7713b1edbc	1656	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
AnnaBridge	171:3a7713b1edbc	1657	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
AnnaBridge	171:3a7713b1edbc	1658	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
AnnaBridge	171:3a7713b1edbc	1659	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
AnnaBridge	171:3a7713b1edbc	1660	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
AnnaBridge	171:3a7713b1edbc	1661	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
AnnaBridge	171:3a7713b1edbc	1662	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
AnnaBridge	171:3a7713b1edbc	1663	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
AnnaBridge	171:3a7713b1edbc	1664	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
AnnaBridge	171:3a7713b1edbc	1665	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
AnnaBridge	171:3a7713b1edbc	1666	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
AnnaBridge	171:3a7713b1edbc	1667	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
AnnaBridge	171:3a7713b1edbc	1668	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
AnnaBridge	171:3a7713b1edbc	1669	* @param Multiplicator This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1670	* @arg @ref LL_RCC_PLLI2S_MUL_8
AnnaBridge	171:3a7713b1edbc	1671	* @arg @ref LL_RCC_PLLI2S_MUL_9
AnnaBridge	171:3a7713b1edbc	1672	* @arg @ref LL_RCC_PLLI2S_MUL_10
AnnaBridge	171:3a7713b1edbc	1673	* @arg @ref LL_RCC_PLLI2S_MUL_11
AnnaBridge	171:3a7713b1edbc	1674	* @arg @ref LL_RCC_PLLI2S_MUL_12
AnnaBridge	171:3a7713b1edbc	1675	* @arg @ref LL_RCC_PLLI2S_MUL_13
AnnaBridge	171:3a7713b1edbc	1676	* @arg @ref LL_RCC_PLLI2S_MUL_14
AnnaBridge	171:3a7713b1edbc	1677	* @arg @ref LL_RCC_PLLI2S_MUL_16
AnnaBridge	171:3a7713b1edbc	1678	* @arg @ref LL_RCC_PLLI2S_MUL_20
AnnaBridge	171:3a7713b1edbc	1679	* @retval None
AnnaBridge	171:3a7713b1edbc	1680	*/
AnnaBridge	171:3a7713b1edbc	1681	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_PLLI2S(uint32_t Divider, uint32_t Multiplicator)
AnnaBridge	171:3a7713b1edbc	1682	{
AnnaBridge	171:3a7713b1edbc	1683	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2 \| RCC_CFGR2_PLL3MUL, Divider \| Multiplicator);
AnnaBridge	171:3a7713b1edbc	1684	}
AnnaBridge	171:3a7713b1edbc	1685
AnnaBridge	171:3a7713b1edbc	1686	/**
AnnaBridge	171:3a7713b1edbc	1687	* @brief Get PLLI2S Multiplication Factor
AnnaBridge	171:3a7713b1edbc	1688	* @rmtoll CFGR2 PLL3MUL LL_RCC_PLLI2S_GetMultiplicator
AnnaBridge	171:3a7713b1edbc	1689	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1690	* @arg @ref LL_RCC_PLLI2S_MUL_8
AnnaBridge	171:3a7713b1edbc	1691	* @arg @ref LL_RCC_PLLI2S_MUL_9
AnnaBridge	171:3a7713b1edbc	1692	* @arg @ref LL_RCC_PLLI2S_MUL_10
AnnaBridge	171:3a7713b1edbc	1693	* @arg @ref LL_RCC_PLLI2S_MUL_11
AnnaBridge	171:3a7713b1edbc	1694	* @arg @ref LL_RCC_PLLI2S_MUL_12
AnnaBridge	171:3a7713b1edbc	1695	* @arg @ref LL_RCC_PLLI2S_MUL_13
AnnaBridge	171:3a7713b1edbc	1696	* @arg @ref LL_RCC_PLLI2S_MUL_14
AnnaBridge	171:3a7713b1edbc	1697	* @arg @ref LL_RCC_PLLI2S_MUL_16
AnnaBridge	171:3a7713b1edbc	1698	* @arg @ref LL_RCC_PLLI2S_MUL_20
AnnaBridge	171:3a7713b1edbc	1699	*/
AnnaBridge	171:3a7713b1edbc	1700	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMultiplicator(void)
AnnaBridge	171:3a7713b1edbc	1701	{
AnnaBridge	171:3a7713b1edbc	1702	return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL));
AnnaBridge	171:3a7713b1edbc	1703	}
AnnaBridge	171:3a7713b1edbc	1704
AnnaBridge	171:3a7713b1edbc	1705	/**
AnnaBridge	171:3a7713b1edbc	1706	* @}
AnnaBridge	171:3a7713b1edbc	1707	*/
AnnaBridge	171:3a7713b1edbc	1708	#endif /* RCC_PLLI2S_SUPPORT */
AnnaBridge	171:3a7713b1edbc	1709
AnnaBridge	171:3a7713b1edbc	1710	#if defined(RCC_PLL2_SUPPORT)
AnnaBridge	171:3a7713b1edbc	1711	/** @defgroup RCC_LL_EF_PLL2 PLL2
AnnaBridge	171:3a7713b1edbc	1712	* @{
AnnaBridge	171:3a7713b1edbc	1713	*/
AnnaBridge	171:3a7713b1edbc	1714
AnnaBridge	171:3a7713b1edbc	1715	/**
AnnaBridge	171:3a7713b1edbc	1716	* @brief Enable PLL2
AnnaBridge	171:3a7713b1edbc	1717	* @rmtoll CR PLL2ON LL_RCC_PLL2_Enable
AnnaBridge	171:3a7713b1edbc	1718	* @retval None
AnnaBridge	171:3a7713b1edbc	1719	*/
AnnaBridge	171:3a7713b1edbc	1720	__STATIC_INLINE void LL_RCC_PLL2_Enable(void)
AnnaBridge	171:3a7713b1edbc	1721	{
AnnaBridge	171:3a7713b1edbc	1722	SET_BIT(RCC->CR, RCC_CR_PLL2ON);
AnnaBridge	171:3a7713b1edbc	1723	}
AnnaBridge	171:3a7713b1edbc	1724
AnnaBridge	171:3a7713b1edbc	1725	/**
AnnaBridge	171:3a7713b1edbc	1726	* @brief Disable PLL2
AnnaBridge	171:3a7713b1edbc	1727	* @rmtoll CR PLL2ON LL_RCC_PLL2_Disable
AnnaBridge	171:3a7713b1edbc	1728	* @retval None
AnnaBridge	171:3a7713b1edbc	1729	*/
AnnaBridge	171:3a7713b1edbc	1730	__STATIC_INLINE void LL_RCC_PLL2_Disable(void)
AnnaBridge	171:3a7713b1edbc	1731	{
AnnaBridge	171:3a7713b1edbc	1732	CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
AnnaBridge	171:3a7713b1edbc	1733	}
AnnaBridge	171:3a7713b1edbc	1734
AnnaBridge	171:3a7713b1edbc	1735	/**
AnnaBridge	171:3a7713b1edbc	1736	* @brief Check if PLL2 Ready
AnnaBridge	171:3a7713b1edbc	1737	* @rmtoll CR PLL2RDY LL_RCC_PLL2_IsReady
AnnaBridge	171:3a7713b1edbc	1738	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1739	*/
AnnaBridge	171:3a7713b1edbc	1740	__STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void)
AnnaBridge	171:3a7713b1edbc	1741	{
AnnaBridge	171:3a7713b1edbc	1742	return (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == (RCC_CR_PLL2RDY));
AnnaBridge	171:3a7713b1edbc	1743	}
AnnaBridge	171:3a7713b1edbc	1744
AnnaBridge	171:3a7713b1edbc	1745	/**
AnnaBridge	171:3a7713b1edbc	1746	* @brief Configure PLL2 used for PLL2 Domain
AnnaBridge	171:3a7713b1edbc	1747	* @rmtoll CFGR2 PREDIV2 LL_RCC_PLL_ConfigDomain_PLL2\n
AnnaBridge	171:3a7713b1edbc	1748	* CFGR2 PLL2MUL LL_RCC_PLL_ConfigDomain_PLL2
AnnaBridge	171:3a7713b1edbc	1749	* @param Divider This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1750	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
AnnaBridge	171:3a7713b1edbc	1751	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
AnnaBridge	171:3a7713b1edbc	1752	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
AnnaBridge	171:3a7713b1edbc	1753	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
AnnaBridge	171:3a7713b1edbc	1754	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
AnnaBridge	171:3a7713b1edbc	1755	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
AnnaBridge	171:3a7713b1edbc	1756	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
AnnaBridge	171:3a7713b1edbc	1757	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
AnnaBridge	171:3a7713b1edbc	1758	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
AnnaBridge	171:3a7713b1edbc	1759	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
AnnaBridge	171:3a7713b1edbc	1760	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
AnnaBridge	171:3a7713b1edbc	1761	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
AnnaBridge	171:3a7713b1edbc	1762	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
AnnaBridge	171:3a7713b1edbc	1763	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
AnnaBridge	171:3a7713b1edbc	1764	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
AnnaBridge	171:3a7713b1edbc	1765	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
AnnaBridge	171:3a7713b1edbc	1766	* @param Multiplicator This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1767	* @arg @ref LL_RCC_PLL2_MUL_8
AnnaBridge	171:3a7713b1edbc	1768	* @arg @ref LL_RCC_PLL2_MUL_9
AnnaBridge	171:3a7713b1edbc	1769	* @arg @ref LL_RCC_PLL2_MUL_10
AnnaBridge	171:3a7713b1edbc	1770	* @arg @ref LL_RCC_PLL2_MUL_11
AnnaBridge	171:3a7713b1edbc	1771	* @arg @ref LL_RCC_PLL2_MUL_12
AnnaBridge	171:3a7713b1edbc	1772	* @arg @ref LL_RCC_PLL2_MUL_13
AnnaBridge	171:3a7713b1edbc	1773	* @arg @ref LL_RCC_PLL2_MUL_14
AnnaBridge	171:3a7713b1edbc	1774	* @arg @ref LL_RCC_PLL2_MUL_16
AnnaBridge	171:3a7713b1edbc	1775	* @arg @ref LL_RCC_PLL2_MUL_20
AnnaBridge	171:3a7713b1edbc	1776	* @retval None
AnnaBridge	171:3a7713b1edbc	1777	*/
AnnaBridge	171:3a7713b1edbc	1778	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_PLL2(uint32_t Divider, uint32_t Multiplicator)
AnnaBridge	171:3a7713b1edbc	1779	{
AnnaBridge	171:3a7713b1edbc	1780	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2 \| RCC_CFGR2_PLL2MUL, Divider \| Multiplicator);
AnnaBridge	171:3a7713b1edbc	1781	}
AnnaBridge	171:3a7713b1edbc	1782
AnnaBridge	171:3a7713b1edbc	1783	/**
AnnaBridge	171:3a7713b1edbc	1784	* @brief Get PLL2 Multiplication Factor
AnnaBridge	171:3a7713b1edbc	1785	* @rmtoll CFGR2 PLL2MUL LL_RCC_PLL2_GetMultiplicator
AnnaBridge	171:3a7713b1edbc	1786	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1787	* @arg @ref LL_RCC_PLL2_MUL_8
AnnaBridge	171:3a7713b1edbc	1788	* @arg @ref LL_RCC_PLL2_MUL_9
AnnaBridge	171:3a7713b1edbc	1789	* @arg @ref LL_RCC_PLL2_MUL_10
AnnaBridge	171:3a7713b1edbc	1790	* @arg @ref LL_RCC_PLL2_MUL_11
AnnaBridge	171:3a7713b1edbc	1791	* @arg @ref LL_RCC_PLL2_MUL_12
AnnaBridge	171:3a7713b1edbc	1792	* @arg @ref LL_RCC_PLL2_MUL_13
AnnaBridge	171:3a7713b1edbc	1793	* @arg @ref LL_RCC_PLL2_MUL_14
AnnaBridge	171:3a7713b1edbc	1794	* @arg @ref LL_RCC_PLL2_MUL_16
AnnaBridge	171:3a7713b1edbc	1795	* @arg @ref LL_RCC_PLL2_MUL_20
AnnaBridge	171:3a7713b1edbc	1796	*/
AnnaBridge	171:3a7713b1edbc	1797	__STATIC_INLINE uint32_t LL_RCC_PLL2_GetMultiplicator(void)
AnnaBridge	171:3a7713b1edbc	1798	{
AnnaBridge	171:3a7713b1edbc	1799	return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL2MUL));
AnnaBridge	171:3a7713b1edbc	1800	}
AnnaBridge	171:3a7713b1edbc	1801
AnnaBridge	171:3a7713b1edbc	1802	/**
AnnaBridge	171:3a7713b1edbc	1803	* @}
AnnaBridge	171:3a7713b1edbc	1804	*/
AnnaBridge	171:3a7713b1edbc	1805	#endif /* RCC_PLL2_SUPPORT */
AnnaBridge	171:3a7713b1edbc	1806
AnnaBridge	171:3a7713b1edbc	1807	/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
AnnaBridge	171:3a7713b1edbc	1808	* @{
AnnaBridge	171:3a7713b1edbc	1809	*/
AnnaBridge	171:3a7713b1edbc	1810
AnnaBridge	171:3a7713b1edbc	1811	/**
AnnaBridge	171:3a7713b1edbc	1812	* @brief Clear LSI ready interrupt flag
AnnaBridge	171:3a7713b1edbc	1813	* @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
AnnaBridge	171:3a7713b1edbc	1814	* @retval None
AnnaBridge	171:3a7713b1edbc	1815	*/
AnnaBridge	171:3a7713b1edbc	1816	__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
AnnaBridge	171:3a7713b1edbc	1817	{
AnnaBridge	171:3a7713b1edbc	1818	SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
AnnaBridge	171:3a7713b1edbc	1819	}
AnnaBridge	171:3a7713b1edbc	1820
AnnaBridge	171:3a7713b1edbc	1821	/**
AnnaBridge	171:3a7713b1edbc	1822	* @brief Clear LSE ready interrupt flag
AnnaBridge	171:3a7713b1edbc	1823	* @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
AnnaBridge	171:3a7713b1edbc	1824	* @retval None
AnnaBridge	171:3a7713b1edbc	1825	*/
AnnaBridge	171:3a7713b1edbc	1826	__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
AnnaBridge	171:3a7713b1edbc	1827	{
AnnaBridge	171:3a7713b1edbc	1828	SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
AnnaBridge	171:3a7713b1edbc	1829	}
AnnaBridge	171:3a7713b1edbc	1830
AnnaBridge	171:3a7713b1edbc	1831	/**
AnnaBridge	171:3a7713b1edbc	1832	* @brief Clear HSI ready interrupt flag
AnnaBridge	171:3a7713b1edbc	1833	* @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
AnnaBridge	171:3a7713b1edbc	1834	* @retval None
AnnaBridge	171:3a7713b1edbc	1835	*/
AnnaBridge	171:3a7713b1edbc	1836	__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
AnnaBridge	171:3a7713b1edbc	1837	{
AnnaBridge	171:3a7713b1edbc	1838	SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
AnnaBridge	171:3a7713b1edbc	1839	}
AnnaBridge	171:3a7713b1edbc	1840
AnnaBridge	171:3a7713b1edbc	1841	/**
AnnaBridge	171:3a7713b1edbc	1842	* @brief Clear HSE ready interrupt flag
AnnaBridge	171:3a7713b1edbc	1843	* @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
AnnaBridge	171:3a7713b1edbc	1844	* @retval None
AnnaBridge	171:3a7713b1edbc	1845	*/
AnnaBridge	171:3a7713b1edbc	1846	__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
AnnaBridge	171:3a7713b1edbc	1847	{
AnnaBridge	171:3a7713b1edbc	1848	SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
AnnaBridge	171:3a7713b1edbc	1849	}
AnnaBridge	171:3a7713b1edbc	1850
AnnaBridge	171:3a7713b1edbc	1851	/**
AnnaBridge	171:3a7713b1edbc	1852	* @brief Clear PLL ready interrupt flag
AnnaBridge	171:3a7713b1edbc	1853	* @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
AnnaBridge	171:3a7713b1edbc	1854	* @retval None
AnnaBridge	171:3a7713b1edbc	1855	*/
AnnaBridge	171:3a7713b1edbc	1856	__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
AnnaBridge	171:3a7713b1edbc	1857	{
AnnaBridge	171:3a7713b1edbc	1858	SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
AnnaBridge	171:3a7713b1edbc	1859	}
AnnaBridge	171:3a7713b1edbc	1860
AnnaBridge	171:3a7713b1edbc	1861	#if defined(RCC_PLLI2S_SUPPORT)
AnnaBridge	171:3a7713b1edbc	1862	/**
AnnaBridge	171:3a7713b1edbc	1863	* @brief Clear PLLI2S ready interrupt flag
AnnaBridge	171:3a7713b1edbc	1864	* @rmtoll CIR PLL3RDYC LL_RCC_ClearFlag_PLLI2SRDY
AnnaBridge	171:3a7713b1edbc	1865	* @retval None
AnnaBridge	171:3a7713b1edbc	1866	*/
AnnaBridge	171:3a7713b1edbc	1867	__STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)
AnnaBridge	171:3a7713b1edbc	1868	{
AnnaBridge	171:3a7713b1edbc	1869	SET_BIT(RCC->CIR, RCC_CIR_PLL3RDYC);
AnnaBridge	171:3a7713b1edbc	1870	}
AnnaBridge	171:3a7713b1edbc	1871	#endif /* RCC_PLLI2S_SUPPORT */
AnnaBridge	171:3a7713b1edbc	1872
AnnaBridge	171:3a7713b1edbc	1873	#if defined(RCC_PLL2_SUPPORT)
AnnaBridge	171:3a7713b1edbc	1874	/**
AnnaBridge	171:3a7713b1edbc	1875	* @brief Clear PLL2 ready interrupt flag
AnnaBridge	171:3a7713b1edbc	1876	* @rmtoll CIR PLL2RDYC LL_RCC_ClearFlag_PLL2RDY
AnnaBridge	171:3a7713b1edbc	1877	* @retval None
AnnaBridge	171:3a7713b1edbc	1878	*/
AnnaBridge	171:3a7713b1edbc	1879	__STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void)
AnnaBridge	171:3a7713b1edbc	1880	{
AnnaBridge	171:3a7713b1edbc	1881	SET_BIT(RCC->CIR, RCC_CIR_PLL2RDYC);
AnnaBridge	171:3a7713b1edbc	1882	}
AnnaBridge	171:3a7713b1edbc	1883	#endif /* RCC_PLL2_SUPPORT */
AnnaBridge	171:3a7713b1edbc	1884
AnnaBridge	171:3a7713b1edbc	1885	/**
AnnaBridge	171:3a7713b1edbc	1886	* @brief Clear Clock security system interrupt flag
AnnaBridge	171:3a7713b1edbc	1887	* @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
AnnaBridge	171:3a7713b1edbc	1888	* @retval None
AnnaBridge	171:3a7713b1edbc	1889	*/
AnnaBridge	171:3a7713b1edbc	1890	__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
AnnaBridge	171:3a7713b1edbc	1891	{
AnnaBridge	171:3a7713b1edbc	1892	SET_BIT(RCC->CIR, RCC_CIR_CSSC);
AnnaBridge	171:3a7713b1edbc	1893	}
AnnaBridge	171:3a7713b1edbc	1894
AnnaBridge	171:3a7713b1edbc	1895	/**
AnnaBridge	171:3a7713b1edbc	1896	* @brief Check if LSI ready interrupt occurred or not
AnnaBridge	171:3a7713b1edbc	1897	* @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
AnnaBridge	171:3a7713b1edbc	1898	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1899	*/
AnnaBridge	171:3a7713b1edbc	1900	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
AnnaBridge	171:3a7713b1edbc	1901	{
AnnaBridge	171:3a7713b1edbc	1902	return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
AnnaBridge	171:3a7713b1edbc	1903	}
AnnaBridge	171:3a7713b1edbc	1904
AnnaBridge	171:3a7713b1edbc	1905	/**
AnnaBridge	171:3a7713b1edbc	1906	* @brief Check if LSE ready interrupt occurred or not
AnnaBridge	171:3a7713b1edbc	1907	* @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
AnnaBridge	171:3a7713b1edbc	1908	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1909	*/
AnnaBridge	171:3a7713b1edbc	1910	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
AnnaBridge	171:3a7713b1edbc	1911	{
AnnaBridge	171:3a7713b1edbc	1912	return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
AnnaBridge	171:3a7713b1edbc	1913	}
AnnaBridge	171:3a7713b1edbc	1914
AnnaBridge	171:3a7713b1edbc	1915	/**
AnnaBridge	171:3a7713b1edbc	1916	* @brief Check if HSI ready interrupt occurred or not
AnnaBridge	171:3a7713b1edbc	1917	* @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
AnnaBridge	171:3a7713b1edbc	1918	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1919	*/
AnnaBridge	171:3a7713b1edbc	1920	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
AnnaBridge	171:3a7713b1edbc	1921	{
AnnaBridge	171:3a7713b1edbc	1922	return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
AnnaBridge	171:3a7713b1edbc	1923	}
AnnaBridge	171:3a7713b1edbc	1924
AnnaBridge	171:3a7713b1edbc	1925	/**
AnnaBridge	171:3a7713b1edbc	1926	* @brief Check if HSE ready interrupt occurred or not
AnnaBridge	171:3a7713b1edbc	1927	* @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
AnnaBridge	171:3a7713b1edbc	1928	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1929	*/
AnnaBridge	171:3a7713b1edbc	1930	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
AnnaBridge	171:3a7713b1edbc	1931	{
AnnaBridge	171:3a7713b1edbc	1932	return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
AnnaBridge	171:3a7713b1edbc	1933	}
AnnaBridge	171:3a7713b1edbc	1934
AnnaBridge	171:3a7713b1edbc	1935	/**
AnnaBridge	171:3a7713b1edbc	1936	* @brief Check if PLL ready interrupt occurred or not
AnnaBridge	171:3a7713b1edbc	1937	* @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
AnnaBridge	171:3a7713b1edbc	1938	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1939	*/
AnnaBridge	171:3a7713b1edbc	1940	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
AnnaBridge	171:3a7713b1edbc	1941	{
AnnaBridge	171:3a7713b1edbc	1942	return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
AnnaBridge	171:3a7713b1edbc	1943	}
AnnaBridge	171:3a7713b1edbc	1944
AnnaBridge	171:3a7713b1edbc	1945	#if defined(RCC_PLLI2S_SUPPORT)
AnnaBridge	171:3a7713b1edbc	1946	/**
AnnaBridge	171:3a7713b1edbc	1947	* @brief Check if PLLI2S ready interrupt occurred or not
AnnaBridge	171:3a7713b1edbc	1948	* @rmtoll CIR PLL3RDYF LL_RCC_IsActiveFlag_PLLI2SRDY
AnnaBridge	171:3a7713b1edbc	1949	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1950	*/
AnnaBridge	171:3a7713b1edbc	1951	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)
AnnaBridge	171:3a7713b1edbc	1952	{
AnnaBridge	171:3a7713b1edbc	1953	return (READ_BIT(RCC->CIR, RCC_CIR_PLL3RDYF) == (RCC_CIR_PLL3RDYF));
AnnaBridge	171:3a7713b1edbc	1954	}
AnnaBridge	171:3a7713b1edbc	1955	#endif /* RCC_PLLI2S_SUPPORT */
AnnaBridge	171:3a7713b1edbc	1956
AnnaBridge	171:3a7713b1edbc	1957	#if defined(RCC_PLL2_SUPPORT)
AnnaBridge	171:3a7713b1edbc	1958	/**
AnnaBridge	171:3a7713b1edbc	1959	* @brief Check if PLL2 ready interrupt occurred or not
AnnaBridge	171:3a7713b1edbc	1960	* @rmtoll CIR PLL2RDYF LL_RCC_IsActiveFlag_PLL2RDY
AnnaBridge	171:3a7713b1edbc	1961	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1962	*/
AnnaBridge	171:3a7713b1edbc	1963	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void)
AnnaBridge	171:3a7713b1edbc	1964	{
AnnaBridge	171:3a7713b1edbc	1965	return (READ_BIT(RCC->CIR, RCC_CIR_PLL2RDYF) == (RCC_CIR_PLL2RDYF));
AnnaBridge	171:3a7713b1edbc	1966	}
AnnaBridge	171:3a7713b1edbc	1967	#endif /* RCC_PLL2_SUPPORT */
AnnaBridge	171:3a7713b1edbc	1968
AnnaBridge	171:3a7713b1edbc	1969	/**
AnnaBridge	171:3a7713b1edbc	1970	* @brief Check if Clock security system interrupt occurred or not
AnnaBridge	171:3a7713b1edbc	1971	* @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
AnnaBridge	171:3a7713b1edbc	1972	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1973	*/
AnnaBridge	171:3a7713b1edbc	1974	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
AnnaBridge	171:3a7713b1edbc	1975	{
AnnaBridge	171:3a7713b1edbc	1976	return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
AnnaBridge	171:3a7713b1edbc	1977	}
AnnaBridge	171:3a7713b1edbc	1978
AnnaBridge	171:3a7713b1edbc	1979	/**
AnnaBridge	171:3a7713b1edbc	1980	* @brief Check if RCC flag Independent Watchdog reset is set or not.
AnnaBridge	171:3a7713b1edbc	1981	* @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
AnnaBridge	171:3a7713b1edbc	1982	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1983	*/
AnnaBridge	171:3a7713b1edbc	1984	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
AnnaBridge	171:3a7713b1edbc	1985	{
AnnaBridge	171:3a7713b1edbc	1986	return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
AnnaBridge	171:3a7713b1edbc	1987	}
AnnaBridge	171:3a7713b1edbc	1988
AnnaBridge	171:3a7713b1edbc	1989	/**
AnnaBridge	171:3a7713b1edbc	1990	* @brief Check if RCC flag Low Power reset is set or not.
AnnaBridge	171:3a7713b1edbc	1991	* @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
AnnaBridge	171:3a7713b1edbc	1992	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1993	*/
AnnaBridge	171:3a7713b1edbc	1994	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
AnnaBridge	171:3a7713b1edbc	1995	{
AnnaBridge	171:3a7713b1edbc	1996	return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
AnnaBridge	171:3a7713b1edbc	1997	}
AnnaBridge	171:3a7713b1edbc	1998
AnnaBridge	171:3a7713b1edbc	1999	/**
AnnaBridge	171:3a7713b1edbc	2000	* @brief Check if RCC flag Pin reset is set or not.
AnnaBridge	171:3a7713b1edbc	2001	* @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
AnnaBridge	171:3a7713b1edbc	2002	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2003	*/
AnnaBridge	171:3a7713b1edbc	2004	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
AnnaBridge	171:3a7713b1edbc	2005	{
AnnaBridge	171:3a7713b1edbc	2006	return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
AnnaBridge	171:3a7713b1edbc	2007	}
AnnaBridge	171:3a7713b1edbc	2008
AnnaBridge	171:3a7713b1edbc	2009	/**
AnnaBridge	171:3a7713b1edbc	2010	* @brief Check if RCC flag POR/PDR reset is set or not.
AnnaBridge	171:3a7713b1edbc	2011	* @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
AnnaBridge	171:3a7713b1edbc	2012	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2013	*/
AnnaBridge	171:3a7713b1edbc	2014	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
AnnaBridge	171:3a7713b1edbc	2015	{
AnnaBridge	171:3a7713b1edbc	2016	return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
AnnaBridge	171:3a7713b1edbc	2017	}
AnnaBridge	171:3a7713b1edbc	2018
AnnaBridge	171:3a7713b1edbc	2019	/**
AnnaBridge	171:3a7713b1edbc	2020	* @brief Check if RCC flag Software reset is set or not.
AnnaBridge	171:3a7713b1edbc	2021	* @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
AnnaBridge	171:3a7713b1edbc	2022	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2023	*/
AnnaBridge	171:3a7713b1edbc	2024	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
AnnaBridge	171:3a7713b1edbc	2025	{
AnnaBridge	171:3a7713b1edbc	2026	return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
AnnaBridge	171:3a7713b1edbc	2027	}
AnnaBridge	171:3a7713b1edbc	2028
AnnaBridge	171:3a7713b1edbc	2029	/**
AnnaBridge	171:3a7713b1edbc	2030	* @brief Check if RCC flag Window Watchdog reset is set or not.
AnnaBridge	171:3a7713b1edbc	2031	* @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
AnnaBridge	171:3a7713b1edbc	2032	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2033	*/
AnnaBridge	171:3a7713b1edbc	2034	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
AnnaBridge	171:3a7713b1edbc	2035	{
AnnaBridge	171:3a7713b1edbc	2036	return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
AnnaBridge	171:3a7713b1edbc	2037	}
AnnaBridge	171:3a7713b1edbc	2038
AnnaBridge	171:3a7713b1edbc	2039	/**
AnnaBridge	171:3a7713b1edbc	2040	* @brief Set RMVF bit to clear the reset flags.
AnnaBridge	171:3a7713b1edbc	2041	* @rmtoll CSR RMVF LL_RCC_ClearResetFlags
AnnaBridge	171:3a7713b1edbc	2042	* @retval None
AnnaBridge	171:3a7713b1edbc	2043	*/
AnnaBridge	171:3a7713b1edbc	2044	__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
AnnaBridge	171:3a7713b1edbc	2045	{
AnnaBridge	171:3a7713b1edbc	2046	SET_BIT(RCC->CSR, RCC_CSR_RMVF);
AnnaBridge	171:3a7713b1edbc	2047	}
AnnaBridge	171:3a7713b1edbc	2048
AnnaBridge	171:3a7713b1edbc	2049	/**
AnnaBridge	171:3a7713b1edbc	2050	* @}
AnnaBridge	171:3a7713b1edbc	2051	*/
AnnaBridge	171:3a7713b1edbc	2052
AnnaBridge	171:3a7713b1edbc	2053	/** @defgroup RCC_LL_EF_IT_Management IT Management
AnnaBridge	171:3a7713b1edbc	2054	* @{
AnnaBridge	171:3a7713b1edbc	2055	*/
AnnaBridge	171:3a7713b1edbc	2056
AnnaBridge	171:3a7713b1edbc	2057	/**
AnnaBridge	171:3a7713b1edbc	2058	* @brief Enable LSI ready interrupt
AnnaBridge	171:3a7713b1edbc	2059	* @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
AnnaBridge	171:3a7713b1edbc	2060	* @retval None
AnnaBridge	171:3a7713b1edbc	2061	*/
AnnaBridge	171:3a7713b1edbc	2062	__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
AnnaBridge	171:3a7713b1edbc	2063	{
AnnaBridge	171:3a7713b1edbc	2064	SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
AnnaBridge	171:3a7713b1edbc	2065	}
AnnaBridge	171:3a7713b1edbc	2066
AnnaBridge	171:3a7713b1edbc	2067	/**
AnnaBridge	171:3a7713b1edbc	2068	* @brief Enable LSE ready interrupt
AnnaBridge	171:3a7713b1edbc	2069	* @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
AnnaBridge	171:3a7713b1edbc	2070	* @retval None
AnnaBridge	171:3a7713b1edbc	2071	*/
AnnaBridge	171:3a7713b1edbc	2072	__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
AnnaBridge	171:3a7713b1edbc	2073	{
AnnaBridge	171:3a7713b1edbc	2074	SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
AnnaBridge	171:3a7713b1edbc	2075	}
AnnaBridge	171:3a7713b1edbc	2076
AnnaBridge	171:3a7713b1edbc	2077	/**
AnnaBridge	171:3a7713b1edbc	2078	* @brief Enable HSI ready interrupt
AnnaBridge	171:3a7713b1edbc	2079	* @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
AnnaBridge	171:3a7713b1edbc	2080	* @retval None
AnnaBridge	171:3a7713b1edbc	2081	*/
AnnaBridge	171:3a7713b1edbc	2082	__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
AnnaBridge	171:3a7713b1edbc	2083	{
AnnaBridge	171:3a7713b1edbc	2084	SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
AnnaBridge	171:3a7713b1edbc	2085	}
AnnaBridge	171:3a7713b1edbc	2086
AnnaBridge	171:3a7713b1edbc	2087	/**
AnnaBridge	171:3a7713b1edbc	2088	* @brief Enable HSE ready interrupt
AnnaBridge	171:3a7713b1edbc	2089	* @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
AnnaBridge	171:3a7713b1edbc	2090	* @retval None
AnnaBridge	171:3a7713b1edbc	2091	*/
AnnaBridge	171:3a7713b1edbc	2092	__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
AnnaBridge	171:3a7713b1edbc	2093	{
AnnaBridge	171:3a7713b1edbc	2094	SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
AnnaBridge	171:3a7713b1edbc	2095	}
AnnaBridge	171:3a7713b1edbc	2096
AnnaBridge	171:3a7713b1edbc	2097	/**
AnnaBridge	171:3a7713b1edbc	2098	* @brief Enable PLL ready interrupt
AnnaBridge	171:3a7713b1edbc	2099	* @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
AnnaBridge	171:3a7713b1edbc	2100	* @retval None
AnnaBridge	171:3a7713b1edbc	2101	*/
AnnaBridge	171:3a7713b1edbc	2102	__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
AnnaBridge	171:3a7713b1edbc	2103	{
AnnaBridge	171:3a7713b1edbc	2104	SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
AnnaBridge	171:3a7713b1edbc	2105	}
AnnaBridge	171:3a7713b1edbc	2106
AnnaBridge	171:3a7713b1edbc	2107	#if defined(RCC_PLLI2S_SUPPORT)
AnnaBridge	171:3a7713b1edbc	2108	/**
AnnaBridge	171:3a7713b1edbc	2109	* @brief Enable PLLI2S ready interrupt
AnnaBridge	171:3a7713b1edbc	2110	* @rmtoll CIR PLL3RDYIE LL_RCC_EnableIT_PLLI2SRDY
AnnaBridge	171:3a7713b1edbc	2111	* @retval None
AnnaBridge	171:3a7713b1edbc	2112	*/
AnnaBridge	171:3a7713b1edbc	2113	__STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)
AnnaBridge	171:3a7713b1edbc	2114	{
AnnaBridge	171:3a7713b1edbc	2115	SET_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE);
AnnaBridge	171:3a7713b1edbc	2116	}
AnnaBridge	171:3a7713b1edbc	2117	#endif /* RCC_PLLI2S_SUPPORT */
AnnaBridge	171:3a7713b1edbc	2118
AnnaBridge	171:3a7713b1edbc	2119	#if defined(RCC_PLL2_SUPPORT)
AnnaBridge	171:3a7713b1edbc	2120	/**
AnnaBridge	171:3a7713b1edbc	2121	* @brief Enable PLL2 ready interrupt
AnnaBridge	171:3a7713b1edbc	2122	* @rmtoll CIR PLL2RDYIE LL_RCC_EnableIT_PLL2RDY
AnnaBridge	171:3a7713b1edbc	2123	* @retval None
AnnaBridge	171:3a7713b1edbc	2124	*/
AnnaBridge	171:3a7713b1edbc	2125	__STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void)
AnnaBridge	171:3a7713b1edbc	2126	{
AnnaBridge	171:3a7713b1edbc	2127	SET_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE);
AnnaBridge	171:3a7713b1edbc	2128	}
AnnaBridge	171:3a7713b1edbc	2129	#endif /* RCC_PLL2_SUPPORT */
AnnaBridge	171:3a7713b1edbc	2130
AnnaBridge	171:3a7713b1edbc	2131	/**
AnnaBridge	171:3a7713b1edbc	2132	* @brief Disable LSI ready interrupt
AnnaBridge	171:3a7713b1edbc	2133	* @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
AnnaBridge	171:3a7713b1edbc	2134	* @retval None
AnnaBridge	171:3a7713b1edbc	2135	*/
AnnaBridge	171:3a7713b1edbc	2136	__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
AnnaBridge	171:3a7713b1edbc	2137	{
AnnaBridge	171:3a7713b1edbc	2138	CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
AnnaBridge	171:3a7713b1edbc	2139	}
AnnaBridge	171:3a7713b1edbc	2140
AnnaBridge	171:3a7713b1edbc	2141	/**
AnnaBridge	171:3a7713b1edbc	2142	* @brief Disable LSE ready interrupt
AnnaBridge	171:3a7713b1edbc	2143	* @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
AnnaBridge	171:3a7713b1edbc	2144	* @retval None
AnnaBridge	171:3a7713b1edbc	2145	*/
AnnaBridge	171:3a7713b1edbc	2146	__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
AnnaBridge	171:3a7713b1edbc	2147	{
AnnaBridge	171:3a7713b1edbc	2148	CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
AnnaBridge	171:3a7713b1edbc	2149	}
AnnaBridge	171:3a7713b1edbc	2150
AnnaBridge	171:3a7713b1edbc	2151	/**
AnnaBridge	171:3a7713b1edbc	2152	* @brief Disable HSI ready interrupt
AnnaBridge	171:3a7713b1edbc	2153	* @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
AnnaBridge	171:3a7713b1edbc	2154	* @retval None
AnnaBridge	171:3a7713b1edbc	2155	*/
AnnaBridge	171:3a7713b1edbc	2156	__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
AnnaBridge	171:3a7713b1edbc	2157	{
AnnaBridge	171:3a7713b1edbc	2158	CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
AnnaBridge	171:3a7713b1edbc	2159	}
AnnaBridge	171:3a7713b1edbc	2160
AnnaBridge	171:3a7713b1edbc	2161	/**
AnnaBridge	171:3a7713b1edbc	2162	* @brief Disable HSE ready interrupt
AnnaBridge	171:3a7713b1edbc	2163	* @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
AnnaBridge	171:3a7713b1edbc	2164	* @retval None
AnnaBridge	171:3a7713b1edbc	2165	*/
AnnaBridge	171:3a7713b1edbc	2166	__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
AnnaBridge	171:3a7713b1edbc	2167	{
AnnaBridge	171:3a7713b1edbc	2168	CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
AnnaBridge	171:3a7713b1edbc	2169	}
AnnaBridge	171:3a7713b1edbc	2170
AnnaBridge	171:3a7713b1edbc	2171	/**
AnnaBridge	171:3a7713b1edbc	2172	* @brief Disable PLL ready interrupt
AnnaBridge	171:3a7713b1edbc	2173	* @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
AnnaBridge	171:3a7713b1edbc	2174	* @retval None
AnnaBridge	171:3a7713b1edbc	2175	*/
AnnaBridge	171:3a7713b1edbc	2176	__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
AnnaBridge	171:3a7713b1edbc	2177	{
AnnaBridge	171:3a7713b1edbc	2178	CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
AnnaBridge	171:3a7713b1edbc	2179	}
AnnaBridge	171:3a7713b1edbc	2180
AnnaBridge	171:3a7713b1edbc	2181	#if defined(RCC_PLLI2S_SUPPORT)
AnnaBridge	171:3a7713b1edbc	2182	/**
AnnaBridge	171:3a7713b1edbc	2183	* @brief Disable PLLI2S ready interrupt
AnnaBridge	171:3a7713b1edbc	2184	* @rmtoll CIR PLL3RDYIE LL_RCC_DisableIT_PLLI2SRDY
AnnaBridge	171:3a7713b1edbc	2185	* @retval None
AnnaBridge	171:3a7713b1edbc	2186	*/
AnnaBridge	171:3a7713b1edbc	2187	__STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)
AnnaBridge	171:3a7713b1edbc	2188	{
AnnaBridge	171:3a7713b1edbc	2189	CLEAR_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE);
AnnaBridge	171:3a7713b1edbc	2190	}
AnnaBridge	171:3a7713b1edbc	2191	#endif /* RCC_PLLI2S_SUPPORT */
AnnaBridge	171:3a7713b1edbc	2192
AnnaBridge	171:3a7713b1edbc	2193	#if defined(RCC_PLL2_SUPPORT)
AnnaBridge	171:3a7713b1edbc	2194	/**
AnnaBridge	171:3a7713b1edbc	2195	* @brief Disable PLL2 ready interrupt
AnnaBridge	171:3a7713b1edbc	2196	* @rmtoll CIR PLL2RDYIE LL_RCC_DisableIT_PLL2RDY
AnnaBridge	171:3a7713b1edbc	2197	* @retval None
AnnaBridge	171:3a7713b1edbc	2198	*/
AnnaBridge	171:3a7713b1edbc	2199	__STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void)
AnnaBridge	171:3a7713b1edbc	2200	{
AnnaBridge	171:3a7713b1edbc	2201	CLEAR_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE);
AnnaBridge	171:3a7713b1edbc	2202	}
AnnaBridge	171:3a7713b1edbc	2203	#endif /* RCC_PLL2_SUPPORT */
AnnaBridge	171:3a7713b1edbc	2204
AnnaBridge	171:3a7713b1edbc	2205	/**
AnnaBridge	171:3a7713b1edbc	2206	* @brief Checks if LSI ready interrupt source is enabled or disabled.
AnnaBridge	171:3a7713b1edbc	2207	* @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
AnnaBridge	171:3a7713b1edbc	2208	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2209	*/
AnnaBridge	171:3a7713b1edbc	2210	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
AnnaBridge	171:3a7713b1edbc	2211	{
AnnaBridge	171:3a7713b1edbc	2212	return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
AnnaBridge	171:3a7713b1edbc	2213	}
AnnaBridge	171:3a7713b1edbc	2214
AnnaBridge	171:3a7713b1edbc	2215	/**
AnnaBridge	171:3a7713b1edbc	2216	* @brief Checks if LSE ready interrupt source is enabled or disabled.
AnnaBridge	171:3a7713b1edbc	2217	* @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
AnnaBridge	171:3a7713b1edbc	2218	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2219	*/
AnnaBridge	171:3a7713b1edbc	2220	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
AnnaBridge	171:3a7713b1edbc	2221	{
AnnaBridge	171:3a7713b1edbc	2222	return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
AnnaBridge	171:3a7713b1edbc	2223	}
AnnaBridge	171:3a7713b1edbc	2224
AnnaBridge	171:3a7713b1edbc	2225	/**
AnnaBridge	171:3a7713b1edbc	2226	* @brief Checks if HSI ready interrupt source is enabled or disabled.
AnnaBridge	171:3a7713b1edbc	2227	* @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
AnnaBridge	171:3a7713b1edbc	2228	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2229	*/
AnnaBridge	171:3a7713b1edbc	2230	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
AnnaBridge	171:3a7713b1edbc	2231	{
AnnaBridge	171:3a7713b1edbc	2232	return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
AnnaBridge	171:3a7713b1edbc	2233	}
AnnaBridge	171:3a7713b1edbc	2234
AnnaBridge	171:3a7713b1edbc	2235	/**
AnnaBridge	171:3a7713b1edbc	2236	* @brief Checks if HSE ready interrupt source is enabled or disabled.
AnnaBridge	171:3a7713b1edbc	2237	* @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
AnnaBridge	171:3a7713b1edbc	2238	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2239	*/
AnnaBridge	171:3a7713b1edbc	2240	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
AnnaBridge	171:3a7713b1edbc	2241	{
AnnaBridge	171:3a7713b1edbc	2242	return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
AnnaBridge	171:3a7713b1edbc	2243	}
AnnaBridge	171:3a7713b1edbc	2244
AnnaBridge	171:3a7713b1edbc	2245	/**
AnnaBridge	171:3a7713b1edbc	2246	* @brief Checks if PLL ready interrupt source is enabled or disabled.
AnnaBridge	171:3a7713b1edbc	2247	* @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
AnnaBridge	171:3a7713b1edbc	2248	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2249	*/
AnnaBridge	171:3a7713b1edbc	2250	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
AnnaBridge	171:3a7713b1edbc	2251	{
AnnaBridge	171:3a7713b1edbc	2252	return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
AnnaBridge	171:3a7713b1edbc	2253	}
AnnaBridge	171:3a7713b1edbc	2254
AnnaBridge	171:3a7713b1edbc	2255	#if defined(RCC_PLLI2S_SUPPORT)
AnnaBridge	171:3a7713b1edbc	2256	/**
AnnaBridge	171:3a7713b1edbc	2257	* @brief Checks if PLLI2S ready interrupt source is enabled or disabled.
AnnaBridge	171:3a7713b1edbc	2258	* @rmtoll CIR PLL3RDYIE LL_RCC_IsEnabledIT_PLLI2SRDY
AnnaBridge	171:3a7713b1edbc	2259	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2260	*/
AnnaBridge	171:3a7713b1edbc	2261	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)
AnnaBridge	171:3a7713b1edbc	2262	{
AnnaBridge	171:3a7713b1edbc	2263	return (READ_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE) == (RCC_CIR_PLL3RDYIE));
AnnaBridge	171:3a7713b1edbc	2264	}
AnnaBridge	171:3a7713b1edbc	2265	#endif /* RCC_PLLI2S_SUPPORT */
AnnaBridge	171:3a7713b1edbc	2266
AnnaBridge	171:3a7713b1edbc	2267	#if defined(RCC_PLL2_SUPPORT)
AnnaBridge	171:3a7713b1edbc	2268	/**
AnnaBridge	171:3a7713b1edbc	2269	* @brief Checks if PLL2 ready interrupt source is enabled or disabled.
AnnaBridge	171:3a7713b1edbc	2270	* @rmtoll CIR PLL2RDYIE LL_RCC_IsEnabledIT_PLL2RDY
AnnaBridge	171:3a7713b1edbc	2271	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2272	*/
AnnaBridge	171:3a7713b1edbc	2273	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL2RDY(void)
AnnaBridge	171:3a7713b1edbc	2274	{
AnnaBridge	171:3a7713b1edbc	2275	return (READ_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE) == (RCC_CIR_PLL2RDYIE));
AnnaBridge	171:3a7713b1edbc	2276	}
AnnaBridge	171:3a7713b1edbc	2277	#endif /* RCC_PLL2_SUPPORT */
AnnaBridge	171:3a7713b1edbc	2278
AnnaBridge	171:3a7713b1edbc	2279	/**
AnnaBridge	171:3a7713b1edbc	2280	* @}
AnnaBridge	171:3a7713b1edbc	2281	*/
AnnaBridge	171:3a7713b1edbc	2282
AnnaBridge	171:3a7713b1edbc	2283	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	171:3a7713b1edbc	2284	/** @defgroup RCC_LL_EF_Init De-initialization function
AnnaBridge	171:3a7713b1edbc	2285	* @{
AnnaBridge	171:3a7713b1edbc	2286	*/
AnnaBridge	171:3a7713b1edbc	2287	ErrorStatus LL_RCC_DeInit(void);
AnnaBridge	171:3a7713b1edbc	2288	/**
AnnaBridge	171:3a7713b1edbc	2289	* @}
AnnaBridge	171:3a7713b1edbc	2290	*/
AnnaBridge	171:3a7713b1edbc	2291
AnnaBridge	171:3a7713b1edbc	2292	/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
AnnaBridge	171:3a7713b1edbc	2293	* @{
AnnaBridge	171:3a7713b1edbc	2294	*/
AnnaBridge	171:3a7713b1edbc	2295	void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
AnnaBridge	171:3a7713b1edbc	2296	#if defined(RCC_CFGR2_I2S2SRC)
AnnaBridge	171:3a7713b1edbc	2297	uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
AnnaBridge	171:3a7713b1edbc	2298	#endif /* RCC_CFGR2_I2S2SRC */
AnnaBridge	171:3a7713b1edbc	2299	#if defined(USB_OTG_FS) \|\| defined(USB)
AnnaBridge	171:3a7713b1edbc	2300	uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
AnnaBridge	171:3a7713b1edbc	2301	#endif /* USB_OTG_FS \|\| USB */
AnnaBridge	171:3a7713b1edbc	2302	uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
AnnaBridge	171:3a7713b1edbc	2303	/**
AnnaBridge	171:3a7713b1edbc	2304	* @}
AnnaBridge	171:3a7713b1edbc	2305	*/
AnnaBridge	171:3a7713b1edbc	2306	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	171:3a7713b1edbc	2307
AnnaBridge	171:3a7713b1edbc	2308	/**
AnnaBridge	171:3a7713b1edbc	2309	* @}
AnnaBridge	171:3a7713b1edbc	2310	*/
AnnaBridge	171:3a7713b1edbc	2311
AnnaBridge	171:3a7713b1edbc	2312	/**
AnnaBridge	171:3a7713b1edbc	2313	* @}
AnnaBridge	171:3a7713b1edbc	2314	*/
AnnaBridge	171:3a7713b1edbc	2315
AnnaBridge	171:3a7713b1edbc	2316	#endif /* RCC */
AnnaBridge	171:3a7713b1edbc	2317
AnnaBridge	171:3a7713b1edbc	2318	/**
AnnaBridge	171:3a7713b1edbc	2319	* @}
AnnaBridge	171:3a7713b1edbc	2320	*/
AnnaBridge	171:3a7713b1edbc	2321
AnnaBridge	171:3a7713b1edbc	2322	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	2323	}
AnnaBridge	171:3a7713b1edbc	2324	#endif
AnnaBridge	171:3a7713b1edbc	2325
AnnaBridge	171:3a7713b1edbc	2326	#endif /* __STM32F1xx_LL_RCC_H */
AnnaBridge	171:3a7713b1edbc	2327
AnnaBridge	171:3a7713b1edbc	2328	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/