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TARGET_NUCLEO_F103RB/TOOLCHAIN_IAR/stm32f1xx_hal_rcc.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file stm32f1xx_hal_rcc.h
AnnaBridge 171:3a7713b1edbc 4 * @author MCD Application Team
AnnaBridge 171:3a7713b1edbc 5 * @brief Header file of RCC HAL module.
AnnaBridge 171:3a7713b1edbc 6 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 7 * @attention
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 12 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 14 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 17 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 171:3a7713b1edbc 19 * may be used to endorse or promote products derived from this software
AnnaBridge 171:3a7713b1edbc 20 * without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 171:3a7713b1edbc 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 171:3a7713b1edbc 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 171:3a7713b1edbc 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 171:3a7713b1edbc 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 171:3a7713b1edbc 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 171:3a7713b1edbc 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 171:3a7713b1edbc 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 32 *
AnnaBridge 171:3a7713b1edbc 33 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 34 */
AnnaBridge 171:3a7713b1edbc 35
AnnaBridge 171:3a7713b1edbc 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 171:3a7713b1edbc 37 #ifndef __STM32F1xx_HAL_RCC_H
AnnaBridge 171:3a7713b1edbc 38 #define __STM32F1xx_HAL_RCC_H
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 41 extern "C" {
AnnaBridge 171:3a7713b1edbc 42 #endif
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 /* Includes ------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 45 #include "stm32f1xx_hal_def.h"
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /** @addtogroup STM32F1xx_HAL_Driver
AnnaBridge 171:3a7713b1edbc 48 * @{
AnnaBridge 171:3a7713b1edbc 49 */
AnnaBridge 171:3a7713b1edbc 50
AnnaBridge 171:3a7713b1edbc 51 /** @addtogroup RCC
AnnaBridge 171:3a7713b1edbc 52 * @{
AnnaBridge 171:3a7713b1edbc 53 */
AnnaBridge 171:3a7713b1edbc 54
AnnaBridge 171:3a7713b1edbc 55 /* Exported types ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 56
AnnaBridge 171:3a7713b1edbc 57 /** @defgroup RCC_Exported_Types RCC Exported Types
AnnaBridge 171:3a7713b1edbc 58 * @{
AnnaBridge 171:3a7713b1edbc 59 */
AnnaBridge 171:3a7713b1edbc 60
AnnaBridge 171:3a7713b1edbc 61 /**
AnnaBridge 171:3a7713b1edbc 62 * @brief RCC PLL configuration structure definition
AnnaBridge 171:3a7713b1edbc 63 */
AnnaBridge 171:3a7713b1edbc 64 typedef struct
AnnaBridge 171:3a7713b1edbc 65 {
AnnaBridge 171:3a7713b1edbc 66 uint32_t PLLState; /*!< PLLState: The new state of the PLL.
AnnaBridge 171:3a7713b1edbc 67 This parameter can be a value of @ref RCC_PLL_Config */
AnnaBridge 171:3a7713b1edbc 68
AnnaBridge 171:3a7713b1edbc 69 uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
AnnaBridge 171:3a7713b1edbc 70 This parameter must be a value of @ref RCC_PLL_Clock_Source */
AnnaBridge 171:3a7713b1edbc 71
AnnaBridge 171:3a7713b1edbc 72 uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
AnnaBridge 171:3a7713b1edbc 73 This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */
AnnaBridge 171:3a7713b1edbc 74 } RCC_PLLInitTypeDef;
AnnaBridge 171:3a7713b1edbc 75
AnnaBridge 171:3a7713b1edbc 76 /**
AnnaBridge 171:3a7713b1edbc 77 * @brief RCC System, AHB and APB busses clock configuration structure definition
AnnaBridge 171:3a7713b1edbc 78 */
AnnaBridge 171:3a7713b1edbc 79 typedef struct
AnnaBridge 171:3a7713b1edbc 80 {
AnnaBridge 171:3a7713b1edbc 81 uint32_t ClockType; /*!< The clock to be configured.
AnnaBridge 171:3a7713b1edbc 82 This parameter can be a value of @ref RCC_System_Clock_Type */
AnnaBridge 171:3a7713b1edbc 83
AnnaBridge 171:3a7713b1edbc 84 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
AnnaBridge 171:3a7713b1edbc 85 This parameter can be a value of @ref RCC_System_Clock_Source */
AnnaBridge 171:3a7713b1edbc 86
AnnaBridge 171:3a7713b1edbc 87 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
AnnaBridge 171:3a7713b1edbc 88 This parameter can be a value of @ref RCC_AHB_Clock_Source */
AnnaBridge 171:3a7713b1edbc 89
AnnaBridge 171:3a7713b1edbc 90 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
AnnaBridge 171:3a7713b1edbc 91 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
AnnaBridge 171:3a7713b1edbc 92
AnnaBridge 171:3a7713b1edbc 93 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
AnnaBridge 171:3a7713b1edbc 94 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
AnnaBridge 171:3a7713b1edbc 95 } RCC_ClkInitTypeDef;
AnnaBridge 171:3a7713b1edbc 96
AnnaBridge 171:3a7713b1edbc 97 /**
AnnaBridge 171:3a7713b1edbc 98 * @}
AnnaBridge 171:3a7713b1edbc 99 */
AnnaBridge 171:3a7713b1edbc 100
AnnaBridge 171:3a7713b1edbc 101 /* Exported constants --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 102 /** @defgroup RCC_Exported_Constants RCC Exported Constants
AnnaBridge 171:3a7713b1edbc 103 * @{
AnnaBridge 171:3a7713b1edbc 104 */
AnnaBridge 171:3a7713b1edbc 105
AnnaBridge 171:3a7713b1edbc 106 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
AnnaBridge 171:3a7713b1edbc 107 * @{
AnnaBridge 171:3a7713b1edbc 108 */
AnnaBridge 171:3a7713b1edbc 109
AnnaBridge 171:3a7713b1edbc 110 #define RCC_PLLSOURCE_HSI_DIV2 0x00000000U /*!< HSI clock divided by 2 selected as PLL entry clock source */
AnnaBridge 171:3a7713b1edbc 111 #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE clock selected as PLL entry clock source */
AnnaBridge 171:3a7713b1edbc 112
AnnaBridge 171:3a7713b1edbc 113 /**
AnnaBridge 171:3a7713b1edbc 114 * @}
AnnaBridge 171:3a7713b1edbc 115 */
AnnaBridge 171:3a7713b1edbc 116
AnnaBridge 171:3a7713b1edbc 117 /** @defgroup RCC_Oscillator_Type Oscillator Type
AnnaBridge 171:3a7713b1edbc 118 * @{
AnnaBridge 171:3a7713b1edbc 119 */
AnnaBridge 171:3a7713b1edbc 120 #define RCC_OSCILLATORTYPE_NONE 0x00000000U
AnnaBridge 171:3a7713b1edbc 121 #define RCC_OSCILLATORTYPE_HSE 0x00000001U
AnnaBridge 171:3a7713b1edbc 122 #define RCC_OSCILLATORTYPE_HSI 0x00000002U
AnnaBridge 171:3a7713b1edbc 123 #define RCC_OSCILLATORTYPE_LSE 0x00000004U
AnnaBridge 171:3a7713b1edbc 124 #define RCC_OSCILLATORTYPE_LSI 0x00000008U
AnnaBridge 171:3a7713b1edbc 125 /**
AnnaBridge 171:3a7713b1edbc 126 * @}
AnnaBridge 171:3a7713b1edbc 127 */
AnnaBridge 171:3a7713b1edbc 128
AnnaBridge 171:3a7713b1edbc 129 /** @defgroup RCC_HSE_Config HSE Config
AnnaBridge 171:3a7713b1edbc 130 * @{
AnnaBridge 171:3a7713b1edbc 131 */
AnnaBridge 171:3a7713b1edbc 132 #define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */
AnnaBridge 171:3a7713b1edbc 133 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */
AnnaBridge 171:3a7713b1edbc 134 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */
AnnaBridge 171:3a7713b1edbc 135 /**
AnnaBridge 171:3a7713b1edbc 136 * @}
AnnaBridge 171:3a7713b1edbc 137 */
AnnaBridge 171:3a7713b1edbc 138
AnnaBridge 171:3a7713b1edbc 139 /** @defgroup RCC_LSE_Config LSE Config
AnnaBridge 171:3a7713b1edbc 140 * @{
AnnaBridge 171:3a7713b1edbc 141 */
AnnaBridge 171:3a7713b1edbc 142 #define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */
AnnaBridge 171:3a7713b1edbc 143 #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */
AnnaBridge 171:3a7713b1edbc 144 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */
AnnaBridge 171:3a7713b1edbc 145
AnnaBridge 171:3a7713b1edbc 146 /**
AnnaBridge 171:3a7713b1edbc 147 * @}
AnnaBridge 171:3a7713b1edbc 148 */
AnnaBridge 171:3a7713b1edbc 149
AnnaBridge 171:3a7713b1edbc 150 /** @defgroup RCC_HSI_Config HSI Config
AnnaBridge 171:3a7713b1edbc 151 * @{
AnnaBridge 171:3a7713b1edbc 152 */
AnnaBridge 171:3a7713b1edbc 153 #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */
AnnaBridge 171:3a7713b1edbc 154 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
AnnaBridge 171:3a7713b1edbc 155
AnnaBridge 171:3a7713b1edbc 156 #define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */
AnnaBridge 171:3a7713b1edbc 157
AnnaBridge 171:3a7713b1edbc 158 /**
AnnaBridge 171:3a7713b1edbc 159 * @}
AnnaBridge 171:3a7713b1edbc 160 */
AnnaBridge 171:3a7713b1edbc 161
AnnaBridge 171:3a7713b1edbc 162 /** @defgroup RCC_LSI_Config LSI Config
AnnaBridge 171:3a7713b1edbc 163 * @{
AnnaBridge 171:3a7713b1edbc 164 */
AnnaBridge 171:3a7713b1edbc 165 #define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */
AnnaBridge 171:3a7713b1edbc 166 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
AnnaBridge 171:3a7713b1edbc 167
AnnaBridge 171:3a7713b1edbc 168 /**
AnnaBridge 171:3a7713b1edbc 169 * @}
AnnaBridge 171:3a7713b1edbc 170 */
AnnaBridge 171:3a7713b1edbc 171
AnnaBridge 171:3a7713b1edbc 172 /** @defgroup RCC_PLL_Config PLL Config
AnnaBridge 171:3a7713b1edbc 173 * @{
AnnaBridge 171:3a7713b1edbc 174 */
AnnaBridge 171:3a7713b1edbc 175 #define RCC_PLL_NONE 0x00000000U /*!< PLL is not configured */
AnnaBridge 171:3a7713b1edbc 176 #define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */
AnnaBridge 171:3a7713b1edbc 177 #define RCC_PLL_ON 0x00000002U /*!< PLL activation */
AnnaBridge 171:3a7713b1edbc 178
AnnaBridge 171:3a7713b1edbc 179 /**
AnnaBridge 171:3a7713b1edbc 180 * @}
AnnaBridge 171:3a7713b1edbc 181 */
AnnaBridge 171:3a7713b1edbc 182
AnnaBridge 171:3a7713b1edbc 183 /** @defgroup RCC_System_Clock_Type System Clock Type
AnnaBridge 171:3a7713b1edbc 184 * @{
AnnaBridge 171:3a7713b1edbc 185 */
AnnaBridge 171:3a7713b1edbc 186 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */
AnnaBridge 171:3a7713b1edbc 187 #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */
AnnaBridge 171:3a7713b1edbc 188 #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */
AnnaBridge 171:3a7713b1edbc 189 #define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */
AnnaBridge 171:3a7713b1edbc 190
AnnaBridge 171:3a7713b1edbc 191 /**
AnnaBridge 171:3a7713b1edbc 192 * @}
AnnaBridge 171:3a7713b1edbc 193 */
AnnaBridge 171:3a7713b1edbc 194
AnnaBridge 171:3a7713b1edbc 195 /** @defgroup RCC_System_Clock_Source System Clock Source
AnnaBridge 171:3a7713b1edbc 196 * @{
AnnaBridge 171:3a7713b1edbc 197 */
AnnaBridge 171:3a7713b1edbc 198 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */
AnnaBridge 171:3a7713b1edbc 199 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */
AnnaBridge 171:3a7713b1edbc 200 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */
AnnaBridge 171:3a7713b1edbc 201
AnnaBridge 171:3a7713b1edbc 202 /**
AnnaBridge 171:3a7713b1edbc 203 * @}
AnnaBridge 171:3a7713b1edbc 204 */
AnnaBridge 171:3a7713b1edbc 205
AnnaBridge 171:3a7713b1edbc 206 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
AnnaBridge 171:3a7713b1edbc 207 * @{
AnnaBridge 171:3a7713b1edbc 208 */
AnnaBridge 171:3a7713b1edbc 209 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
AnnaBridge 171:3a7713b1edbc 210 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
AnnaBridge 171:3a7713b1edbc 211 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
AnnaBridge 171:3a7713b1edbc 212
AnnaBridge 171:3a7713b1edbc 213 /**
AnnaBridge 171:3a7713b1edbc 214 * @}
AnnaBridge 171:3a7713b1edbc 215 */
AnnaBridge 171:3a7713b1edbc 216
AnnaBridge 171:3a7713b1edbc 217 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
AnnaBridge 171:3a7713b1edbc 218 * @{
AnnaBridge 171:3a7713b1edbc 219 */
AnnaBridge 171:3a7713b1edbc 220 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
AnnaBridge 171:3a7713b1edbc 221 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
AnnaBridge 171:3a7713b1edbc 222 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
AnnaBridge 171:3a7713b1edbc 223 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
AnnaBridge 171:3a7713b1edbc 224 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
AnnaBridge 171:3a7713b1edbc 225 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
AnnaBridge 171:3a7713b1edbc 226 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
AnnaBridge 171:3a7713b1edbc 227 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
AnnaBridge 171:3a7713b1edbc 228 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
AnnaBridge 171:3a7713b1edbc 229
AnnaBridge 171:3a7713b1edbc 230 /**
AnnaBridge 171:3a7713b1edbc 231 * @}
AnnaBridge 171:3a7713b1edbc 232 */
AnnaBridge 171:3a7713b1edbc 233
AnnaBridge 171:3a7713b1edbc 234 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
AnnaBridge 171:3a7713b1edbc 235 * @{
AnnaBridge 171:3a7713b1edbc 236 */
AnnaBridge 171:3a7713b1edbc 237 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
AnnaBridge 171:3a7713b1edbc 238 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
AnnaBridge 171:3a7713b1edbc 239 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
AnnaBridge 171:3a7713b1edbc 240 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
AnnaBridge 171:3a7713b1edbc 241 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
AnnaBridge 171:3a7713b1edbc 242
AnnaBridge 171:3a7713b1edbc 243 /**
AnnaBridge 171:3a7713b1edbc 244 * @}
AnnaBridge 171:3a7713b1edbc 245 */
AnnaBridge 171:3a7713b1edbc 246
AnnaBridge 171:3a7713b1edbc 247 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
AnnaBridge 171:3a7713b1edbc 248 * @{
AnnaBridge 171:3a7713b1edbc 249 */
AnnaBridge 171:3a7713b1edbc 250 #define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U /*!< No clock */
AnnaBridge 171:3a7713b1edbc 251 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */
AnnaBridge 171:3a7713b1edbc 252 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */
AnnaBridge 171:3a7713b1edbc 253 #define RCC_RTCCLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 128 used as RTC clock */
AnnaBridge 171:3a7713b1edbc 254 /**
AnnaBridge 171:3a7713b1edbc 255 * @}
AnnaBridge 171:3a7713b1edbc 256 */
AnnaBridge 171:3a7713b1edbc 257
AnnaBridge 171:3a7713b1edbc 258
AnnaBridge 171:3a7713b1edbc 259 /** @defgroup RCC_MCO_Index MCO Index
AnnaBridge 171:3a7713b1edbc 260 * @{
AnnaBridge 171:3a7713b1edbc 261 */
AnnaBridge 171:3a7713b1edbc 262 #define RCC_MCO1 0x00000000U
AnnaBridge 171:3a7713b1edbc 263 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
AnnaBridge 171:3a7713b1edbc 264
AnnaBridge 171:3a7713b1edbc 265 /**
AnnaBridge 171:3a7713b1edbc 266 * @}
AnnaBridge 171:3a7713b1edbc 267 */
AnnaBridge 171:3a7713b1edbc 268
AnnaBridge 171:3a7713b1edbc 269 /** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler
AnnaBridge 171:3a7713b1edbc 270 * @{
AnnaBridge 171:3a7713b1edbc 271 */
AnnaBridge 171:3a7713b1edbc 272 #define RCC_MCODIV_1 0x00000000U
AnnaBridge 171:3a7713b1edbc 273
AnnaBridge 171:3a7713b1edbc 274 /**
AnnaBridge 171:3a7713b1edbc 275 * @}
AnnaBridge 171:3a7713b1edbc 276 */
AnnaBridge 171:3a7713b1edbc 277
AnnaBridge 171:3a7713b1edbc 278 /** @defgroup RCC_Interrupt Interrupts
AnnaBridge 171:3a7713b1edbc 279 * @{
AnnaBridge 171:3a7713b1edbc 280 */
AnnaBridge 171:3a7713b1edbc 281 #define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */
AnnaBridge 171:3a7713b1edbc 282 #define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */
AnnaBridge 171:3a7713b1edbc 283 #define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */
AnnaBridge 171:3a7713b1edbc 284 #define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */
AnnaBridge 171:3a7713b1edbc 285 #define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */
AnnaBridge 171:3a7713b1edbc 286 #define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */
AnnaBridge 171:3a7713b1edbc 287 /**
AnnaBridge 171:3a7713b1edbc 288 * @}
AnnaBridge 171:3a7713b1edbc 289 */
AnnaBridge 171:3a7713b1edbc 290
AnnaBridge 171:3a7713b1edbc 291 /** @defgroup RCC_Flag Flags
AnnaBridge 171:3a7713b1edbc 292 * Elements values convention: XXXYYYYYb
AnnaBridge 171:3a7713b1edbc 293 * - YYYYY : Flag position in the register
AnnaBridge 171:3a7713b1edbc 294 * - XXX : Register index
AnnaBridge 171:3a7713b1edbc 295 * - 001: CR register
AnnaBridge 171:3a7713b1edbc 296 * - 010: BDCR register
AnnaBridge 171:3a7713b1edbc 297 * - 011: CSR register
AnnaBridge 171:3a7713b1edbc 298 * @{
AnnaBridge 171:3a7713b1edbc 299 */
AnnaBridge 171:3a7713b1edbc 300 /* Flags in the CR register */
AnnaBridge 171:3a7713b1edbc 301 #define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< Internal High Speed clock ready flag */
AnnaBridge 171:3a7713b1edbc 302 #define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< External High Speed clock ready flag */
AnnaBridge 171:3a7713b1edbc 303 #define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL clock ready flag */
AnnaBridge 171:3a7713b1edbc 304
AnnaBridge 171:3a7713b1edbc 305 /* Flags in the CSR register */
AnnaBridge 171:3a7713b1edbc 306 #define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)) /*!< Internal Low Speed oscillator Ready */
AnnaBridge 171:3a7713b1edbc 307 #define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) /*!< PIN reset flag */
AnnaBridge 171:3a7713b1edbc 308 #define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos)) /*!< POR/PDR reset flag */
AnnaBridge 171:3a7713b1edbc 309 #define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) /*!< Software Reset flag */
AnnaBridge 171:3a7713b1edbc 310 #define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */
AnnaBridge 171:3a7713b1edbc 311 #define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */
AnnaBridge 171:3a7713b1edbc 312 #define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */
AnnaBridge 171:3a7713b1edbc 313
AnnaBridge 171:3a7713b1edbc 314 /* Flags in the BDCR register */
AnnaBridge 171:3a7713b1edbc 315 #define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< External Low Speed oscillator Ready */
AnnaBridge 171:3a7713b1edbc 316
AnnaBridge 171:3a7713b1edbc 317 /**
AnnaBridge 171:3a7713b1edbc 318 * @}
AnnaBridge 171:3a7713b1edbc 319 */
AnnaBridge 171:3a7713b1edbc 320
AnnaBridge 171:3a7713b1edbc 321 /**
AnnaBridge 171:3a7713b1edbc 322 * @}
AnnaBridge 171:3a7713b1edbc 323 */
AnnaBridge 171:3a7713b1edbc 324
AnnaBridge 171:3a7713b1edbc 325 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 326
AnnaBridge 171:3a7713b1edbc 327 /** @defgroup RCC_Exported_Macros RCC Exported Macros
AnnaBridge 171:3a7713b1edbc 328 * @{
AnnaBridge 171:3a7713b1edbc 329 */
AnnaBridge 171:3a7713b1edbc 330
AnnaBridge 171:3a7713b1edbc 331 /** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
AnnaBridge 171:3a7713b1edbc 332 * @brief Enable or disable the AHB1 peripheral clock.
AnnaBridge 171:3a7713b1edbc 333 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 171:3a7713b1edbc 334 * is disabled and the application software has to enable this clock before
AnnaBridge 171:3a7713b1edbc 335 * using it.
AnnaBridge 171:3a7713b1edbc 336 * @{
AnnaBridge 171:3a7713b1edbc 337 */
AnnaBridge 171:3a7713b1edbc 338 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
AnnaBridge 171:3a7713b1edbc 339 __IO uint32_t tmpreg; \
AnnaBridge 171:3a7713b1edbc 340 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
AnnaBridge 171:3a7713b1edbc 341 /* Delay after an RCC peripheral clock enabling */\
AnnaBridge 171:3a7713b1edbc 342 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
AnnaBridge 171:3a7713b1edbc 343 UNUSED(tmpreg); \
AnnaBridge 171:3a7713b1edbc 344 } while(0U)
AnnaBridge 171:3a7713b1edbc 345
AnnaBridge 171:3a7713b1edbc 346 #define __HAL_RCC_SRAM_CLK_ENABLE() do { \
AnnaBridge 171:3a7713b1edbc 347 __IO uint32_t tmpreg; \
AnnaBridge 171:3a7713b1edbc 348 SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
AnnaBridge 171:3a7713b1edbc 349 /* Delay after an RCC peripheral clock enabling */\
AnnaBridge 171:3a7713b1edbc 350 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
AnnaBridge 171:3a7713b1edbc 351 UNUSED(tmpreg); \
AnnaBridge 171:3a7713b1edbc 352 } while(0U)
AnnaBridge 171:3a7713b1edbc 353
AnnaBridge 171:3a7713b1edbc 354 #define __HAL_RCC_FLITF_CLK_ENABLE() do { \
AnnaBridge 171:3a7713b1edbc 355 __IO uint32_t tmpreg; \
AnnaBridge 171:3a7713b1edbc 356 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
AnnaBridge 171:3a7713b1edbc 357 /* Delay after an RCC peripheral clock enabling */\
AnnaBridge 171:3a7713b1edbc 358 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
AnnaBridge 171:3a7713b1edbc 359 UNUSED(tmpreg); \
AnnaBridge 171:3a7713b1edbc 360 } while(0U)
AnnaBridge 171:3a7713b1edbc 361
AnnaBridge 171:3a7713b1edbc 362 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
AnnaBridge 171:3a7713b1edbc 363 __IO uint32_t tmpreg; \
AnnaBridge 171:3a7713b1edbc 364 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
AnnaBridge 171:3a7713b1edbc 365 /* Delay after an RCC peripheral clock enabling */\
AnnaBridge 171:3a7713b1edbc 366 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
AnnaBridge 171:3a7713b1edbc 367 UNUSED(tmpreg); \
AnnaBridge 171:3a7713b1edbc 368 } while(0U)
AnnaBridge 171:3a7713b1edbc 369
AnnaBridge 171:3a7713b1edbc 370 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
AnnaBridge 171:3a7713b1edbc 371 #define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
AnnaBridge 171:3a7713b1edbc 372 #define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
AnnaBridge 171:3a7713b1edbc 373 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
AnnaBridge 171:3a7713b1edbc 374
AnnaBridge 171:3a7713b1edbc 375 /**
AnnaBridge 171:3a7713b1edbc 376 * @}
AnnaBridge 171:3a7713b1edbc 377 */
AnnaBridge 171:3a7713b1edbc 378
AnnaBridge 171:3a7713b1edbc 379 /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
AnnaBridge 171:3a7713b1edbc 380 * @brief Get the enable or disable status of the AHB peripheral clock.
AnnaBridge 171:3a7713b1edbc 381 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 171:3a7713b1edbc 382 * is disabled and the application software has to enable this clock before
AnnaBridge 171:3a7713b1edbc 383 * using it.
AnnaBridge 171:3a7713b1edbc 384 * @{
AnnaBridge 171:3a7713b1edbc 385 */
AnnaBridge 171:3a7713b1edbc 386
AnnaBridge 171:3a7713b1edbc 387 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
AnnaBridge 171:3a7713b1edbc 388 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
AnnaBridge 171:3a7713b1edbc 389 #define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
AnnaBridge 171:3a7713b1edbc 390 #define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
AnnaBridge 171:3a7713b1edbc 391 #define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
AnnaBridge 171:3a7713b1edbc 392 #define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
AnnaBridge 171:3a7713b1edbc 393 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
AnnaBridge 171:3a7713b1edbc 394 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
AnnaBridge 171:3a7713b1edbc 395
AnnaBridge 171:3a7713b1edbc 396 /**
AnnaBridge 171:3a7713b1edbc 397 * @}
AnnaBridge 171:3a7713b1edbc 398 */
AnnaBridge 171:3a7713b1edbc 399
AnnaBridge 171:3a7713b1edbc 400 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
AnnaBridge 171:3a7713b1edbc 401 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
AnnaBridge 171:3a7713b1edbc 402 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 171:3a7713b1edbc 403 * is disabled and the application software has to enable this clock before
AnnaBridge 171:3a7713b1edbc 404 * using it.
AnnaBridge 171:3a7713b1edbc 405 * @{
AnnaBridge 171:3a7713b1edbc 406 */
AnnaBridge 171:3a7713b1edbc 407 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
AnnaBridge 171:3a7713b1edbc 408 __IO uint32_t tmpreg; \
AnnaBridge 171:3a7713b1edbc 409 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge 171:3a7713b1edbc 410 /* Delay after an RCC peripheral clock enabling */\
AnnaBridge 171:3a7713b1edbc 411 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
AnnaBridge 171:3a7713b1edbc 412 UNUSED(tmpreg); \
AnnaBridge 171:3a7713b1edbc 413 } while(0U)
AnnaBridge 171:3a7713b1edbc 414
AnnaBridge 171:3a7713b1edbc 415 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
AnnaBridge 171:3a7713b1edbc 416 __IO uint32_t tmpreg; \
AnnaBridge 171:3a7713b1edbc 417 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge 171:3a7713b1edbc 418 /* Delay after an RCC peripheral clock enabling */\
AnnaBridge 171:3a7713b1edbc 419 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge 171:3a7713b1edbc 420 UNUSED(tmpreg); \
AnnaBridge 171:3a7713b1edbc 421 } while(0U)
AnnaBridge 171:3a7713b1edbc 422
AnnaBridge 171:3a7713b1edbc 423 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
AnnaBridge 171:3a7713b1edbc 424 __IO uint32_t tmpreg; \
AnnaBridge 171:3a7713b1edbc 425 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
AnnaBridge 171:3a7713b1edbc 426 /* Delay after an RCC peripheral clock enabling */\
AnnaBridge 171:3a7713b1edbc 427 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
AnnaBridge 171:3a7713b1edbc 428 UNUSED(tmpreg); \
AnnaBridge 171:3a7713b1edbc 429 } while(0U)
AnnaBridge 171:3a7713b1edbc 430
AnnaBridge 171:3a7713b1edbc 431 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
AnnaBridge 171:3a7713b1edbc 432 __IO uint32_t tmpreg; \
AnnaBridge 171:3a7713b1edbc 433 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
AnnaBridge 171:3a7713b1edbc 434 /* Delay after an RCC peripheral clock enabling */\
AnnaBridge 171:3a7713b1edbc 435 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
AnnaBridge 171:3a7713b1edbc 436 UNUSED(tmpreg); \
AnnaBridge 171:3a7713b1edbc 437 } while(0U)
AnnaBridge 171:3a7713b1edbc 438
AnnaBridge 171:3a7713b1edbc 439 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
AnnaBridge 171:3a7713b1edbc 440 __IO uint32_t tmpreg; \
AnnaBridge 171:3a7713b1edbc 441 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
AnnaBridge 171:3a7713b1edbc 442 /* Delay after an RCC peripheral clock enabling */\
AnnaBridge 171:3a7713b1edbc 443 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
AnnaBridge 171:3a7713b1edbc 444 UNUSED(tmpreg); \
AnnaBridge 171:3a7713b1edbc 445 } while(0U)
AnnaBridge 171:3a7713b1edbc 446
AnnaBridge 171:3a7713b1edbc 447 #define __HAL_RCC_BKP_CLK_ENABLE() do { \
AnnaBridge 171:3a7713b1edbc 448 __IO uint32_t tmpreg; \
AnnaBridge 171:3a7713b1edbc 449 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
AnnaBridge 171:3a7713b1edbc 450 /* Delay after an RCC peripheral clock enabling */\
AnnaBridge 171:3a7713b1edbc 451 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
AnnaBridge 171:3a7713b1edbc 452 UNUSED(tmpreg); \
AnnaBridge 171:3a7713b1edbc 453 } while(0U)
AnnaBridge 171:3a7713b1edbc 454
AnnaBridge 171:3a7713b1edbc 455 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
AnnaBridge 171:3a7713b1edbc 456 __IO uint32_t tmpreg; \
AnnaBridge 171:3a7713b1edbc 457 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
AnnaBridge 171:3a7713b1edbc 458 /* Delay after an RCC peripheral clock enabling */\
AnnaBridge 171:3a7713b1edbc 459 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
AnnaBridge 171:3a7713b1edbc 460 UNUSED(tmpreg); \
AnnaBridge 171:3a7713b1edbc 461 } while(0U)
AnnaBridge 171:3a7713b1edbc 462
AnnaBridge 171:3a7713b1edbc 463 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
AnnaBridge 171:3a7713b1edbc 464 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
AnnaBridge 171:3a7713b1edbc 465 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
AnnaBridge 171:3a7713b1edbc 466 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
AnnaBridge 171:3a7713b1edbc 467 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
AnnaBridge 171:3a7713b1edbc 468
AnnaBridge 171:3a7713b1edbc 469 #define __HAL_RCC_BKP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN))
AnnaBridge 171:3a7713b1edbc 470 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
AnnaBridge 171:3a7713b1edbc 471
AnnaBridge 171:3a7713b1edbc 472 /**
AnnaBridge 171:3a7713b1edbc 473 * @}
AnnaBridge 171:3a7713b1edbc 474 */
AnnaBridge 171:3a7713b1edbc 475
AnnaBridge 171:3a7713b1edbc 476 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
AnnaBridge 171:3a7713b1edbc 477 * @brief Get the enable or disable status of the APB1 peripheral clock.
AnnaBridge 171:3a7713b1edbc 478 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 171:3a7713b1edbc 479 * is disabled and the application software has to enable this clock before
AnnaBridge 171:3a7713b1edbc 480 * using it.
AnnaBridge 171:3a7713b1edbc 481 * @{
AnnaBridge 171:3a7713b1edbc 482 */
AnnaBridge 171:3a7713b1edbc 483
AnnaBridge 171:3a7713b1edbc 484 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
AnnaBridge 171:3a7713b1edbc 485 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
AnnaBridge 171:3a7713b1edbc 486 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
AnnaBridge 171:3a7713b1edbc 487 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
AnnaBridge 171:3a7713b1edbc 488 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
AnnaBridge 171:3a7713b1edbc 489 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
AnnaBridge 171:3a7713b1edbc 490 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
AnnaBridge 171:3a7713b1edbc 491 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
AnnaBridge 171:3a7713b1edbc 492 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
AnnaBridge 171:3a7713b1edbc 493 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
AnnaBridge 171:3a7713b1edbc 494 #define __HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET)
AnnaBridge 171:3a7713b1edbc 495 #define __HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET)
AnnaBridge 171:3a7713b1edbc 496 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
AnnaBridge 171:3a7713b1edbc 497 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
AnnaBridge 171:3a7713b1edbc 498
AnnaBridge 171:3a7713b1edbc 499 /**
AnnaBridge 171:3a7713b1edbc 500 * @}
AnnaBridge 171:3a7713b1edbc 501 */
AnnaBridge 171:3a7713b1edbc 502
AnnaBridge 171:3a7713b1edbc 503 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
AnnaBridge 171:3a7713b1edbc 504 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
AnnaBridge 171:3a7713b1edbc 505 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 171:3a7713b1edbc 506 * is disabled and the application software has to enable this clock before
AnnaBridge 171:3a7713b1edbc 507 * using it.
AnnaBridge 171:3a7713b1edbc 508 * @{
AnnaBridge 171:3a7713b1edbc 509 */
AnnaBridge 171:3a7713b1edbc 510 #define __HAL_RCC_AFIO_CLK_ENABLE() do { \
AnnaBridge 171:3a7713b1edbc 511 __IO uint32_t tmpreg; \
AnnaBridge 171:3a7713b1edbc 512 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
AnnaBridge 171:3a7713b1edbc 513 /* Delay after an RCC peripheral clock enabling */\
AnnaBridge 171:3a7713b1edbc 514 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
AnnaBridge 171:3a7713b1edbc 515 UNUSED(tmpreg); \
AnnaBridge 171:3a7713b1edbc 516 } while(0U)
AnnaBridge 171:3a7713b1edbc 517
AnnaBridge 171:3a7713b1edbc 518 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
AnnaBridge 171:3a7713b1edbc 519 __IO uint32_t tmpreg; \
AnnaBridge 171:3a7713b1edbc 520 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
AnnaBridge 171:3a7713b1edbc 521 /* Delay after an RCC peripheral clock enabling */\
AnnaBridge 171:3a7713b1edbc 522 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
AnnaBridge 171:3a7713b1edbc 523 UNUSED(tmpreg); \
AnnaBridge 171:3a7713b1edbc 524 } while(0U)
AnnaBridge 171:3a7713b1edbc 525
AnnaBridge 171:3a7713b1edbc 526 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
AnnaBridge 171:3a7713b1edbc 527 __IO uint32_t tmpreg; \
AnnaBridge 171:3a7713b1edbc 528 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
AnnaBridge 171:3a7713b1edbc 529 /* Delay after an RCC peripheral clock enabling */\
AnnaBridge 171:3a7713b1edbc 530 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
AnnaBridge 171:3a7713b1edbc 531 UNUSED(tmpreg); \
AnnaBridge 171:3a7713b1edbc 532 } while(0U)
AnnaBridge 171:3a7713b1edbc 533
AnnaBridge 171:3a7713b1edbc 534 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
AnnaBridge 171:3a7713b1edbc 535 __IO uint32_t tmpreg; \
AnnaBridge 171:3a7713b1edbc 536 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
AnnaBridge 171:3a7713b1edbc 537 /* Delay after an RCC peripheral clock enabling */\
AnnaBridge 171:3a7713b1edbc 538 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
AnnaBridge 171:3a7713b1edbc 539 UNUSED(tmpreg); \
AnnaBridge 171:3a7713b1edbc 540 } while(0U)
AnnaBridge 171:3a7713b1edbc 541
AnnaBridge 171:3a7713b1edbc 542 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
AnnaBridge 171:3a7713b1edbc 543 __IO uint32_t tmpreg; \
AnnaBridge 171:3a7713b1edbc 544 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
AnnaBridge 171:3a7713b1edbc 545 /* Delay after an RCC peripheral clock enabling */\
AnnaBridge 171:3a7713b1edbc 546 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
AnnaBridge 171:3a7713b1edbc 547 UNUSED(tmpreg); \
AnnaBridge 171:3a7713b1edbc 548 } while(0U)
AnnaBridge 171:3a7713b1edbc 549
AnnaBridge 171:3a7713b1edbc 550 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
AnnaBridge 171:3a7713b1edbc 551 __IO uint32_t tmpreg; \
AnnaBridge 171:3a7713b1edbc 552 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
AnnaBridge 171:3a7713b1edbc 553 /* Delay after an RCC peripheral clock enabling */\
AnnaBridge 171:3a7713b1edbc 554 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
AnnaBridge 171:3a7713b1edbc 555 UNUSED(tmpreg); \
AnnaBridge 171:3a7713b1edbc 556 } while(0U)
AnnaBridge 171:3a7713b1edbc 557
AnnaBridge 171:3a7713b1edbc 558 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
AnnaBridge 171:3a7713b1edbc 559 __IO uint32_t tmpreg; \
AnnaBridge 171:3a7713b1edbc 560 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
AnnaBridge 171:3a7713b1edbc 561 /* Delay after an RCC peripheral clock enabling */\
AnnaBridge 171:3a7713b1edbc 562 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
AnnaBridge 171:3a7713b1edbc 563 UNUSED(tmpreg); \
AnnaBridge 171:3a7713b1edbc 564 } while(0U)
AnnaBridge 171:3a7713b1edbc 565
AnnaBridge 171:3a7713b1edbc 566 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
AnnaBridge 171:3a7713b1edbc 567 __IO uint32_t tmpreg; \
AnnaBridge 171:3a7713b1edbc 568 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
AnnaBridge 171:3a7713b1edbc 569 /* Delay after an RCC peripheral clock enabling */\
AnnaBridge 171:3a7713b1edbc 570 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
AnnaBridge 171:3a7713b1edbc 571 UNUSED(tmpreg); \
AnnaBridge 171:3a7713b1edbc 572 } while(0U)
AnnaBridge 171:3a7713b1edbc 573
AnnaBridge 171:3a7713b1edbc 574 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
AnnaBridge 171:3a7713b1edbc 575 __IO uint32_t tmpreg; \
AnnaBridge 171:3a7713b1edbc 576 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
AnnaBridge 171:3a7713b1edbc 577 /* Delay after an RCC peripheral clock enabling */\
AnnaBridge 171:3a7713b1edbc 578 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
AnnaBridge 171:3a7713b1edbc 579 UNUSED(tmpreg); \
AnnaBridge 171:3a7713b1edbc 580 } while(0U)
AnnaBridge 171:3a7713b1edbc 581
AnnaBridge 171:3a7713b1edbc 582 #define __HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN))
AnnaBridge 171:3a7713b1edbc 583 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN))
AnnaBridge 171:3a7713b1edbc 584 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN))
AnnaBridge 171:3a7713b1edbc 585 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN))
AnnaBridge 171:3a7713b1edbc 586 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN))
AnnaBridge 171:3a7713b1edbc 587 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
AnnaBridge 171:3a7713b1edbc 588
AnnaBridge 171:3a7713b1edbc 589 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
AnnaBridge 171:3a7713b1edbc 590 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
AnnaBridge 171:3a7713b1edbc 591 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
AnnaBridge 171:3a7713b1edbc 592
AnnaBridge 171:3a7713b1edbc 593 /**
AnnaBridge 171:3a7713b1edbc 594 * @}
AnnaBridge 171:3a7713b1edbc 595 */
AnnaBridge 171:3a7713b1edbc 596
AnnaBridge 171:3a7713b1edbc 597 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
AnnaBridge 171:3a7713b1edbc 598 * @brief Get the enable or disable status of the APB2 peripheral clock.
AnnaBridge 171:3a7713b1edbc 599 * @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge 171:3a7713b1edbc 600 * is disabled and the application software has to enable this clock before
AnnaBridge 171:3a7713b1edbc 601 * using it.
AnnaBridge 171:3a7713b1edbc 602 * @{
AnnaBridge 171:3a7713b1edbc 603 */
AnnaBridge 171:3a7713b1edbc 604
AnnaBridge 171:3a7713b1edbc 605 #define __HAL_RCC_AFIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET)
AnnaBridge 171:3a7713b1edbc 606 #define __HAL_RCC_AFIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET)
AnnaBridge 171:3a7713b1edbc 607 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET)
AnnaBridge 171:3a7713b1edbc 608 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET)
AnnaBridge 171:3a7713b1edbc 609 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET)
AnnaBridge 171:3a7713b1edbc 610 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET)
AnnaBridge 171:3a7713b1edbc 611 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET)
AnnaBridge 171:3a7713b1edbc 612 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET)
AnnaBridge 171:3a7713b1edbc 613 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET)
AnnaBridge 171:3a7713b1edbc 614 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET)
AnnaBridge 171:3a7713b1edbc 615 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
AnnaBridge 171:3a7713b1edbc 616 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
AnnaBridge 171:3a7713b1edbc 617 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
AnnaBridge 171:3a7713b1edbc 618 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
AnnaBridge 171:3a7713b1edbc 619 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
AnnaBridge 171:3a7713b1edbc 620 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
AnnaBridge 171:3a7713b1edbc 621 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
AnnaBridge 171:3a7713b1edbc 622 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
AnnaBridge 171:3a7713b1edbc 623
AnnaBridge 171:3a7713b1edbc 624 /**
AnnaBridge 171:3a7713b1edbc 625 * @}
AnnaBridge 171:3a7713b1edbc 626 */
AnnaBridge 171:3a7713b1edbc 627
AnnaBridge 171:3a7713b1edbc 628 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
AnnaBridge 171:3a7713b1edbc 629 * @brief Force or release APB1 peripheral reset.
AnnaBridge 171:3a7713b1edbc 630 * @{
AnnaBridge 171:3a7713b1edbc 631 */
AnnaBridge 171:3a7713b1edbc 632 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 633 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
AnnaBridge 171:3a7713b1edbc 634 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
AnnaBridge 171:3a7713b1edbc 635 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
AnnaBridge 171:3a7713b1edbc 636 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
AnnaBridge 171:3a7713b1edbc 637 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
AnnaBridge 171:3a7713b1edbc 638
AnnaBridge 171:3a7713b1edbc 639 #define __HAL_RCC_BKP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_BKPRST))
AnnaBridge 171:3a7713b1edbc 640 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
AnnaBridge 171:3a7713b1edbc 641
AnnaBridge 171:3a7713b1edbc 642 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
AnnaBridge 171:3a7713b1edbc 643 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
AnnaBridge 171:3a7713b1edbc 644 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
AnnaBridge 171:3a7713b1edbc 645 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
AnnaBridge 171:3a7713b1edbc 646 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
AnnaBridge 171:3a7713b1edbc 647 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
AnnaBridge 171:3a7713b1edbc 648
AnnaBridge 171:3a7713b1edbc 649 #define __HAL_RCC_BKP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST))
AnnaBridge 171:3a7713b1edbc 650 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
AnnaBridge 171:3a7713b1edbc 651
AnnaBridge 171:3a7713b1edbc 652 /**
AnnaBridge 171:3a7713b1edbc 653 * @}
AnnaBridge 171:3a7713b1edbc 654 */
AnnaBridge 171:3a7713b1edbc 655
AnnaBridge 171:3a7713b1edbc 656 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
AnnaBridge 171:3a7713b1edbc 657 * @brief Force or release APB2 peripheral reset.
AnnaBridge 171:3a7713b1edbc 658 * @{
AnnaBridge 171:3a7713b1edbc 659 */
AnnaBridge 171:3a7713b1edbc 660 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 661 #define __HAL_RCC_AFIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST))
AnnaBridge 171:3a7713b1edbc 662 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST))
AnnaBridge 171:3a7713b1edbc 663 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST))
AnnaBridge 171:3a7713b1edbc 664 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPCRST))
AnnaBridge 171:3a7713b1edbc 665 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPDRST))
AnnaBridge 171:3a7713b1edbc 666 #define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
AnnaBridge 171:3a7713b1edbc 667
AnnaBridge 171:3a7713b1edbc 668 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
AnnaBridge 171:3a7713b1edbc 669 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
AnnaBridge 171:3a7713b1edbc 670 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
AnnaBridge 171:3a7713b1edbc 671
AnnaBridge 171:3a7713b1edbc 672 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
AnnaBridge 171:3a7713b1edbc 673 #define __HAL_RCC_AFIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST))
AnnaBridge 171:3a7713b1edbc 674 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST))
AnnaBridge 171:3a7713b1edbc 675 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST))
AnnaBridge 171:3a7713b1edbc 676 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST))
AnnaBridge 171:3a7713b1edbc 677 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST))
AnnaBridge 171:3a7713b1edbc 678 #define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
AnnaBridge 171:3a7713b1edbc 679
AnnaBridge 171:3a7713b1edbc 680 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
AnnaBridge 171:3a7713b1edbc 681 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
AnnaBridge 171:3a7713b1edbc 682 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
AnnaBridge 171:3a7713b1edbc 683
AnnaBridge 171:3a7713b1edbc 684 /**
AnnaBridge 171:3a7713b1edbc 685 * @}
AnnaBridge 171:3a7713b1edbc 686 */
AnnaBridge 171:3a7713b1edbc 687
AnnaBridge 171:3a7713b1edbc 688 /** @defgroup RCC_HSI_Configuration HSI Configuration
AnnaBridge 171:3a7713b1edbc 689 * @{
AnnaBridge 171:3a7713b1edbc 690 */
AnnaBridge 171:3a7713b1edbc 691
AnnaBridge 171:3a7713b1edbc 692 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
AnnaBridge 171:3a7713b1edbc 693 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge 171:3a7713b1edbc 694 * @note HSI can not be stopped if it is used as system clock source. In this case,
AnnaBridge 171:3a7713b1edbc 695 * you have to select another source of the system clock then stop the HSI.
AnnaBridge 171:3a7713b1edbc 696 * @note After enabling the HSI, the application software should wait on HSIRDY
AnnaBridge 171:3a7713b1edbc 697 * flag to be set indicating that HSI clock is stable and can be used as
AnnaBridge 171:3a7713b1edbc 698 * system clock source.
AnnaBridge 171:3a7713b1edbc 699 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
AnnaBridge 171:3a7713b1edbc 700 * clock cycles.
AnnaBridge 171:3a7713b1edbc 701 */
AnnaBridge 171:3a7713b1edbc 702 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
AnnaBridge 171:3a7713b1edbc 703 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
AnnaBridge 171:3a7713b1edbc 704
AnnaBridge 171:3a7713b1edbc 705 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
AnnaBridge 171:3a7713b1edbc 706 * @note The calibration is used to compensate for the variations in voltage
AnnaBridge 171:3a7713b1edbc 707 * and temperature that influence the frequency of the internal HSI RC.
AnnaBridge 171:3a7713b1edbc 708 * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
AnnaBridge 171:3a7713b1edbc 709 * (default is RCC_HSICALIBRATION_DEFAULT).
AnnaBridge 171:3a7713b1edbc 710 * This parameter must be a number between 0 and 0x1F.
AnnaBridge 171:3a7713b1edbc 711 */
AnnaBridge 171:3a7713b1edbc 712 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
AnnaBridge 171:3a7713b1edbc 713 (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_Pos))
AnnaBridge 171:3a7713b1edbc 714
AnnaBridge 171:3a7713b1edbc 715 /**
AnnaBridge 171:3a7713b1edbc 716 * @}
AnnaBridge 171:3a7713b1edbc 717 */
AnnaBridge 171:3a7713b1edbc 718
AnnaBridge 171:3a7713b1edbc 719 /** @defgroup RCC_LSI_Configuration LSI Configuration
AnnaBridge 171:3a7713b1edbc 720 * @{
AnnaBridge 171:3a7713b1edbc 721 */
AnnaBridge 171:3a7713b1edbc 722
AnnaBridge 171:3a7713b1edbc 723 /** @brief Macro to enable the Internal Low Speed oscillator (LSI).
AnnaBridge 171:3a7713b1edbc 724 * @note After enabling the LSI, the application software should wait on
AnnaBridge 171:3a7713b1edbc 725 * LSIRDY flag to be set indicating that LSI clock is stable and can
AnnaBridge 171:3a7713b1edbc 726 * be used to clock the IWDG and/or the RTC.
AnnaBridge 171:3a7713b1edbc 727 */
AnnaBridge 171:3a7713b1edbc 728 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
AnnaBridge 171:3a7713b1edbc 729
AnnaBridge 171:3a7713b1edbc 730 /** @brief Macro to disable the Internal Low Speed oscillator (LSI).
AnnaBridge 171:3a7713b1edbc 731 * @note LSI can not be disabled if the IWDG is running.
AnnaBridge 171:3a7713b1edbc 732 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
AnnaBridge 171:3a7713b1edbc 733 * clock cycles.
AnnaBridge 171:3a7713b1edbc 734 */
AnnaBridge 171:3a7713b1edbc 735 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
AnnaBridge 171:3a7713b1edbc 736
AnnaBridge 171:3a7713b1edbc 737 /**
AnnaBridge 171:3a7713b1edbc 738 * @}
AnnaBridge 171:3a7713b1edbc 739 */
AnnaBridge 171:3a7713b1edbc 740
AnnaBridge 171:3a7713b1edbc 741 /** @defgroup RCC_HSE_Configuration HSE Configuration
AnnaBridge 171:3a7713b1edbc 742 * @{
AnnaBridge 171:3a7713b1edbc 743 */
AnnaBridge 171:3a7713b1edbc 744
AnnaBridge 171:3a7713b1edbc 745 /**
AnnaBridge 171:3a7713b1edbc 746 * @brief Macro to configure the External High Speed oscillator (HSE).
AnnaBridge 171:3a7713b1edbc 747 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
AnnaBridge 171:3a7713b1edbc 748 * supported by this macro. User should request a transition to HSE Off
AnnaBridge 171:3a7713b1edbc 749 * first and then HSE On or HSE Bypass.
AnnaBridge 171:3a7713b1edbc 750 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
AnnaBridge 171:3a7713b1edbc 751 * software should wait on HSERDY flag to be set indicating that HSE clock
AnnaBridge 171:3a7713b1edbc 752 * is stable and can be used to clock the PLL and/or system clock.
AnnaBridge 171:3a7713b1edbc 753 * @note HSE state can not be changed if it is used directly or through the
AnnaBridge 171:3a7713b1edbc 754 * PLL as system clock. In this case, you have to select another source
AnnaBridge 171:3a7713b1edbc 755 * of the system clock then change the HSE state (ex. disable it).
AnnaBridge 171:3a7713b1edbc 756 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge 171:3a7713b1edbc 757 * @note This function reset the CSSON bit, so if the clock security system(CSS)
AnnaBridge 171:3a7713b1edbc 758 * was previously enabled you have to enable it again after calling this
AnnaBridge 171:3a7713b1edbc 759 * function.
AnnaBridge 171:3a7713b1edbc 760 * @param __STATE__ specifies the new state of the HSE.
AnnaBridge 171:3a7713b1edbc 761 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 762 * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
AnnaBridge 171:3a7713b1edbc 763 * 6 HSE oscillator clock cycles.
AnnaBridge 171:3a7713b1edbc 764 * @arg @ref RCC_HSE_ON turn ON the HSE oscillator
AnnaBridge 171:3a7713b1edbc 765 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
AnnaBridge 171:3a7713b1edbc 766 */
AnnaBridge 171:3a7713b1edbc 767 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
AnnaBridge 171:3a7713b1edbc 768 do{ \
AnnaBridge 171:3a7713b1edbc 769 if ((__STATE__) == RCC_HSE_ON) \
AnnaBridge 171:3a7713b1edbc 770 { \
AnnaBridge 171:3a7713b1edbc 771 SET_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge 171:3a7713b1edbc 772 } \
AnnaBridge 171:3a7713b1edbc 773 else if ((__STATE__) == RCC_HSE_OFF) \
AnnaBridge 171:3a7713b1edbc 774 { \
AnnaBridge 171:3a7713b1edbc 775 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge 171:3a7713b1edbc 776 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
AnnaBridge 171:3a7713b1edbc 777 } \
AnnaBridge 171:3a7713b1edbc 778 else if ((__STATE__) == RCC_HSE_BYPASS) \
AnnaBridge 171:3a7713b1edbc 779 { \
AnnaBridge 171:3a7713b1edbc 780 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
AnnaBridge 171:3a7713b1edbc 781 SET_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge 171:3a7713b1edbc 782 } \
AnnaBridge 171:3a7713b1edbc 783 else \
AnnaBridge 171:3a7713b1edbc 784 { \
AnnaBridge 171:3a7713b1edbc 785 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge 171:3a7713b1edbc 786 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
AnnaBridge 171:3a7713b1edbc 787 } \
AnnaBridge 171:3a7713b1edbc 788 }while(0U)
AnnaBridge 171:3a7713b1edbc 789
AnnaBridge 171:3a7713b1edbc 790 /**
AnnaBridge 171:3a7713b1edbc 791 * @}
AnnaBridge 171:3a7713b1edbc 792 */
AnnaBridge 171:3a7713b1edbc 793
AnnaBridge 171:3a7713b1edbc 794 /** @defgroup RCC_LSE_Configuration LSE Configuration
AnnaBridge 171:3a7713b1edbc 795 * @{
AnnaBridge 171:3a7713b1edbc 796 */
AnnaBridge 171:3a7713b1edbc 797
AnnaBridge 171:3a7713b1edbc 798 /**
AnnaBridge 171:3a7713b1edbc 799 * @brief Macro to configure the External Low Speed oscillator (LSE).
AnnaBridge 171:3a7713b1edbc 800 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
AnnaBridge 171:3a7713b1edbc 801 * @note As the LSE is in the Backup domain and write access is denied to
AnnaBridge 171:3a7713b1edbc 802 * this domain after reset, you have to enable write access using
AnnaBridge 171:3a7713b1edbc 803 * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
AnnaBridge 171:3a7713b1edbc 804 * (to be done once after reset).
AnnaBridge 171:3a7713b1edbc 805 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
AnnaBridge 171:3a7713b1edbc 806 * software should wait on LSERDY flag to be set indicating that LSE clock
AnnaBridge 171:3a7713b1edbc 807 * is stable and can be used to clock the RTC.
AnnaBridge 171:3a7713b1edbc 808 * @param __STATE__ specifies the new state of the LSE.
AnnaBridge 171:3a7713b1edbc 809 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 810 * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
AnnaBridge 171:3a7713b1edbc 811 * 6 LSE oscillator clock cycles.
AnnaBridge 171:3a7713b1edbc 812 * @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
AnnaBridge 171:3a7713b1edbc 813 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
AnnaBridge 171:3a7713b1edbc 814 */
AnnaBridge 171:3a7713b1edbc 815 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
AnnaBridge 171:3a7713b1edbc 816 do{ \
AnnaBridge 171:3a7713b1edbc 817 if ((__STATE__) == RCC_LSE_ON) \
AnnaBridge 171:3a7713b1edbc 818 { \
AnnaBridge 171:3a7713b1edbc 819 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
AnnaBridge 171:3a7713b1edbc 820 } \
AnnaBridge 171:3a7713b1edbc 821 else if ((__STATE__) == RCC_LSE_OFF) \
AnnaBridge 171:3a7713b1edbc 822 { \
AnnaBridge 171:3a7713b1edbc 823 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
AnnaBridge 171:3a7713b1edbc 824 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
AnnaBridge 171:3a7713b1edbc 825 } \
AnnaBridge 171:3a7713b1edbc 826 else if ((__STATE__) == RCC_LSE_BYPASS) \
AnnaBridge 171:3a7713b1edbc 827 { \
AnnaBridge 171:3a7713b1edbc 828 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
AnnaBridge 171:3a7713b1edbc 829 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
AnnaBridge 171:3a7713b1edbc 830 } \
AnnaBridge 171:3a7713b1edbc 831 else \
AnnaBridge 171:3a7713b1edbc 832 { \
AnnaBridge 171:3a7713b1edbc 833 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
AnnaBridge 171:3a7713b1edbc 834 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
AnnaBridge 171:3a7713b1edbc 835 } \
AnnaBridge 171:3a7713b1edbc 836 }while(0U)
AnnaBridge 171:3a7713b1edbc 837
AnnaBridge 171:3a7713b1edbc 838 /**
AnnaBridge 171:3a7713b1edbc 839 * @}
AnnaBridge 171:3a7713b1edbc 840 */
AnnaBridge 171:3a7713b1edbc 841
AnnaBridge 171:3a7713b1edbc 842 /** @defgroup RCC_PLL_Configuration PLL Configuration
AnnaBridge 171:3a7713b1edbc 843 * @{
AnnaBridge 171:3a7713b1edbc 844 */
AnnaBridge 171:3a7713b1edbc 845
AnnaBridge 171:3a7713b1edbc 846 /** @brief Macro to enable the main PLL.
AnnaBridge 171:3a7713b1edbc 847 * @note After enabling the main PLL, the application software should wait on
AnnaBridge 171:3a7713b1edbc 848 * PLLRDY flag to be set indicating that PLL clock is stable and can
AnnaBridge 171:3a7713b1edbc 849 * be used as system clock source.
AnnaBridge 171:3a7713b1edbc 850 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
AnnaBridge 171:3a7713b1edbc 851 */
AnnaBridge 171:3a7713b1edbc 852 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
AnnaBridge 171:3a7713b1edbc 853
AnnaBridge 171:3a7713b1edbc 854 /** @brief Macro to disable the main PLL.
AnnaBridge 171:3a7713b1edbc 855 * @note The main PLL can not be disabled if it is used as system clock source
AnnaBridge 171:3a7713b1edbc 856 */
AnnaBridge 171:3a7713b1edbc 857 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
AnnaBridge 171:3a7713b1edbc 858
AnnaBridge 171:3a7713b1edbc 859 /** @brief Macro to configure the main PLL clock source and multiplication factors.
AnnaBridge 171:3a7713b1edbc 860 * @note This function must be used only when the main PLL is disabled.
AnnaBridge 171:3a7713b1edbc 861 *
AnnaBridge 171:3a7713b1edbc 862 * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source.
AnnaBridge 171:3a7713b1edbc 863 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 864 * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL clock entry
AnnaBridge 171:3a7713b1edbc 865 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
AnnaBridge 171:3a7713b1edbc 866 * @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock
AnnaBridge 171:3a7713b1edbc 867 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 868 * @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4
AnnaBridge 171:3a7713b1edbc 869 * @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6
AnnaBridge 171:3a7713b1edbc 870 @if STM32F105xC
AnnaBridge 171:3a7713b1edbc 871 * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5
AnnaBridge 171:3a7713b1edbc 872 @elseif STM32F107xC
AnnaBridge 171:3a7713b1edbc 873 * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5
AnnaBridge 171:3a7713b1edbc 874 @else
AnnaBridge 171:3a7713b1edbc 875 * @arg @ref RCC_PLL_MUL2 PLLVCO = PLL clock entry x 2
AnnaBridge 171:3a7713b1edbc 876 * @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3
AnnaBridge 171:3a7713b1edbc 877 * @arg @ref RCC_PLL_MUL10 PLLVCO = PLL clock entry x 10
AnnaBridge 171:3a7713b1edbc 878 * @arg @ref RCC_PLL_MUL11 PLLVCO = PLL clock entry x 11
AnnaBridge 171:3a7713b1edbc 879 * @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12
AnnaBridge 171:3a7713b1edbc 880 * @arg @ref RCC_PLL_MUL13 PLLVCO = PLL clock entry x 13
AnnaBridge 171:3a7713b1edbc 881 * @arg @ref RCC_PLL_MUL14 PLLVCO = PLL clock entry x 14
AnnaBridge 171:3a7713b1edbc 882 * @arg @ref RCC_PLL_MUL15 PLLVCO = PLL clock entry x 15
AnnaBridge 171:3a7713b1edbc 883 * @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16
AnnaBridge 171:3a7713b1edbc 884 @endif
AnnaBridge 171:3a7713b1edbc 885 * @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8
AnnaBridge 171:3a7713b1edbc 886 * @arg @ref RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9
AnnaBridge 171:3a7713b1edbc 887 *
AnnaBridge 171:3a7713b1edbc 888 */
AnnaBridge 171:3a7713b1edbc 889 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\
AnnaBridge 171:3a7713b1edbc 890 MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) ))
AnnaBridge 171:3a7713b1edbc 891
AnnaBridge 171:3a7713b1edbc 892 /** @brief Get oscillator clock selected as PLL input clock
AnnaBridge 171:3a7713b1edbc 893 * @retval The clock source used for PLL entry. The returned value can be one
AnnaBridge 171:3a7713b1edbc 894 * of the following:
AnnaBridge 171:3a7713b1edbc 895 * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL input clock
AnnaBridge 171:3a7713b1edbc 896 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
AnnaBridge 171:3a7713b1edbc 897 */
AnnaBridge 171:3a7713b1edbc 898 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
AnnaBridge 171:3a7713b1edbc 899
AnnaBridge 171:3a7713b1edbc 900 /**
AnnaBridge 171:3a7713b1edbc 901 * @}
AnnaBridge 171:3a7713b1edbc 902 */
AnnaBridge 171:3a7713b1edbc 903
AnnaBridge 171:3a7713b1edbc 904 /** @defgroup RCC_Get_Clock_source Get Clock source
AnnaBridge 171:3a7713b1edbc 905 * @{
AnnaBridge 171:3a7713b1edbc 906 */
AnnaBridge 171:3a7713b1edbc 907
AnnaBridge 171:3a7713b1edbc 908 /**
AnnaBridge 171:3a7713b1edbc 909 * @brief Macro to configure the system clock source.
AnnaBridge 171:3a7713b1edbc 910 * @param __SYSCLKSOURCE__ specifies the system clock source.
AnnaBridge 171:3a7713b1edbc 911 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 912 * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
AnnaBridge 171:3a7713b1edbc 913 * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
AnnaBridge 171:3a7713b1edbc 914 * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
AnnaBridge 171:3a7713b1edbc 915 */
AnnaBridge 171:3a7713b1edbc 916 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
AnnaBridge 171:3a7713b1edbc 917 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
AnnaBridge 171:3a7713b1edbc 918
AnnaBridge 171:3a7713b1edbc 919 /** @brief Macro to get the clock source used as system clock.
AnnaBridge 171:3a7713b1edbc 920 * @retval The clock source used as system clock. The returned value can be one
AnnaBridge 171:3a7713b1edbc 921 * of the following:
AnnaBridge 171:3a7713b1edbc 922 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
AnnaBridge 171:3a7713b1edbc 923 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
AnnaBridge 171:3a7713b1edbc 924 * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
AnnaBridge 171:3a7713b1edbc 925 */
AnnaBridge 171:3a7713b1edbc 926 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
AnnaBridge 171:3a7713b1edbc 927
AnnaBridge 171:3a7713b1edbc 928 /**
AnnaBridge 171:3a7713b1edbc 929 * @}
AnnaBridge 171:3a7713b1edbc 930 */
AnnaBridge 171:3a7713b1edbc 931
AnnaBridge 171:3a7713b1edbc 932 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
AnnaBridge 171:3a7713b1edbc 933 * @{
AnnaBridge 171:3a7713b1edbc 934 */
AnnaBridge 171:3a7713b1edbc 935
AnnaBridge 171:3a7713b1edbc 936 #if defined(RCC_CFGR_MCO_3)
AnnaBridge 171:3a7713b1edbc 937 /** @brief Macro to configure the MCO clock.
AnnaBridge 171:3a7713b1edbc 938 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
AnnaBridge 171:3a7713b1edbc 939 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 940 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
AnnaBridge 171:3a7713b1edbc 941 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock
AnnaBridge 171:3a7713b1edbc 942 * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
AnnaBridge 171:3a7713b1edbc 943 * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
AnnaBridge 171:3a7713b1edbc 944 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock
AnnaBridge 171:3a7713b1edbc 945 * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected by 2 selected as MCO clock
AnnaBridge 171:3a7713b1edbc 946 * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO clock
AnnaBridge 171:3a7713b1edbc 947 * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected (for Ethernet) as MCO clock
AnnaBridge 171:3a7713b1edbc 948 * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected (for Ethernet) as MCO clock
AnnaBridge 171:3a7713b1edbc 949 * @param __MCODIV__ specifies the MCO clock prescaler.
AnnaBridge 171:3a7713b1edbc 950 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 951 * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
AnnaBridge 171:3a7713b1edbc 952 */
AnnaBridge 171:3a7713b1edbc 953 #else
AnnaBridge 171:3a7713b1edbc 954 /** @brief Macro to configure the MCO clock.
AnnaBridge 171:3a7713b1edbc 955 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
AnnaBridge 171:3a7713b1edbc 956 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 957 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
AnnaBridge 171:3a7713b1edbc 958 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock
AnnaBridge 171:3a7713b1edbc 959 * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
AnnaBridge 171:3a7713b1edbc 960 * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
AnnaBridge 171:3a7713b1edbc 961 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock
AnnaBridge 171:3a7713b1edbc 962 * @param __MCODIV__ specifies the MCO clock prescaler.
AnnaBridge 171:3a7713b1edbc 963 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 964 * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
AnnaBridge 171:3a7713b1edbc 965 */
AnnaBridge 171:3a7713b1edbc 966 #endif
AnnaBridge 171:3a7713b1edbc 967
AnnaBridge 171:3a7713b1edbc 968 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
AnnaBridge 171:3a7713b1edbc 969 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
AnnaBridge 171:3a7713b1edbc 970
AnnaBridge 171:3a7713b1edbc 971
AnnaBridge 171:3a7713b1edbc 972 /**
AnnaBridge 171:3a7713b1edbc 973 * @}
AnnaBridge 171:3a7713b1edbc 974 */
AnnaBridge 171:3a7713b1edbc 975
AnnaBridge 171:3a7713b1edbc 976 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
AnnaBridge 171:3a7713b1edbc 977 * @{
AnnaBridge 171:3a7713b1edbc 978 */
AnnaBridge 171:3a7713b1edbc 979
AnnaBridge 171:3a7713b1edbc 980 /** @brief Macro to configure the RTC clock (RTCCLK).
AnnaBridge 171:3a7713b1edbc 981 * @note As the RTC clock configuration bits are in the Backup domain and write
AnnaBridge 171:3a7713b1edbc 982 * access is denied to this domain after reset, you have to enable write
AnnaBridge 171:3a7713b1edbc 983 * access using the Power Backup Access macro before to configure
AnnaBridge 171:3a7713b1edbc 984 * the RTC clock source (to be done once after reset).
AnnaBridge 171:3a7713b1edbc 985 * @note Once the RTC clock is configured it can't be changed unless the
AnnaBridge 171:3a7713b1edbc 986 * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
AnnaBridge 171:3a7713b1edbc 987 * a Power On Reset (POR).
AnnaBridge 171:3a7713b1edbc 988 *
AnnaBridge 171:3a7713b1edbc 989 * @param __RTC_CLKSOURCE__ specifies the RTC clock source.
AnnaBridge 171:3a7713b1edbc 990 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 991 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
AnnaBridge 171:3a7713b1edbc 992 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
AnnaBridge 171:3a7713b1edbc 993 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
AnnaBridge 171:3a7713b1edbc 994 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
AnnaBridge 171:3a7713b1edbc 995 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
AnnaBridge 171:3a7713b1edbc 996 * work in STOP and STANDBY modes, and can be used as wakeup source.
AnnaBridge 171:3a7713b1edbc 997 * However, when the HSE clock is used as RTC clock source, the RTC
AnnaBridge 171:3a7713b1edbc 998 * cannot be used in STOP and STANDBY modes.
AnnaBridge 171:3a7713b1edbc 999 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
AnnaBridge 171:3a7713b1edbc 1000 * RTC clock source).
AnnaBridge 171:3a7713b1edbc 1001 */
AnnaBridge 171:3a7713b1edbc 1002 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
AnnaBridge 171:3a7713b1edbc 1003
AnnaBridge 171:3a7713b1edbc 1004 /** @brief Macro to get the RTC clock source.
AnnaBridge 171:3a7713b1edbc 1005 * @retval The clock source can be one of the following values:
AnnaBridge 171:3a7713b1edbc 1006 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
AnnaBridge 171:3a7713b1edbc 1007 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
AnnaBridge 171:3a7713b1edbc 1008 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
AnnaBridge 171:3a7713b1edbc 1009 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
AnnaBridge 171:3a7713b1edbc 1010 */
AnnaBridge 171:3a7713b1edbc 1011 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
AnnaBridge 171:3a7713b1edbc 1012
AnnaBridge 171:3a7713b1edbc 1013 /** @brief Macro to enable the the RTC clock.
AnnaBridge 171:3a7713b1edbc 1014 * @note These macros must be used only after the RTC clock source was selected.
AnnaBridge 171:3a7713b1edbc 1015 */
AnnaBridge 171:3a7713b1edbc 1016 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
AnnaBridge 171:3a7713b1edbc 1017
AnnaBridge 171:3a7713b1edbc 1018 /** @brief Macro to disable the the RTC clock.
AnnaBridge 171:3a7713b1edbc 1019 * @note These macros must be used only after the RTC clock source was selected.
AnnaBridge 171:3a7713b1edbc 1020 */
AnnaBridge 171:3a7713b1edbc 1021 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
AnnaBridge 171:3a7713b1edbc 1022
AnnaBridge 171:3a7713b1edbc 1023 /** @brief Macro to force the Backup domain reset.
AnnaBridge 171:3a7713b1edbc 1024 * @note This function resets the RTC peripheral (including the backup registers)
AnnaBridge 171:3a7713b1edbc 1025 * and the RTC clock source selection in RCC_BDCR register.
AnnaBridge 171:3a7713b1edbc 1026 */
AnnaBridge 171:3a7713b1edbc 1027 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
AnnaBridge 171:3a7713b1edbc 1028
AnnaBridge 171:3a7713b1edbc 1029 /** @brief Macros to release the Backup domain reset.
AnnaBridge 171:3a7713b1edbc 1030 */
AnnaBridge 171:3a7713b1edbc 1031 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
AnnaBridge 171:3a7713b1edbc 1032
AnnaBridge 171:3a7713b1edbc 1033 /**
AnnaBridge 171:3a7713b1edbc 1034 * @}
AnnaBridge 171:3a7713b1edbc 1035 */
AnnaBridge 171:3a7713b1edbc 1036
AnnaBridge 171:3a7713b1edbc 1037 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
AnnaBridge 171:3a7713b1edbc 1038 * @brief macros to manage the specified RCC Flags and interrupts.
AnnaBridge 171:3a7713b1edbc 1039 * @{
AnnaBridge 171:3a7713b1edbc 1040 */
AnnaBridge 171:3a7713b1edbc 1041
AnnaBridge 171:3a7713b1edbc 1042 /** @brief Enable RCC interrupt.
AnnaBridge 171:3a7713b1edbc 1043 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
AnnaBridge 171:3a7713b1edbc 1044 * This parameter can be any combination of the following values:
AnnaBridge 171:3a7713b1edbc 1045 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
AnnaBridge 171:3a7713b1edbc 1046 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
AnnaBridge 171:3a7713b1edbc 1047 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
AnnaBridge 171:3a7713b1edbc 1048 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
AnnaBridge 171:3a7713b1edbc 1049 * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
AnnaBridge 171:3a7713b1edbc 1050 @if STM32F105xx
AnnaBridge 171:3a7713b1edbc 1051 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
AnnaBridge 171:3a7713b1edbc 1052 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
AnnaBridge 171:3a7713b1edbc 1053 @elsif STM32F107xx
AnnaBridge 171:3a7713b1edbc 1054 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
AnnaBridge 171:3a7713b1edbc 1055 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
AnnaBridge 171:3a7713b1edbc 1056 @endif
AnnaBridge 171:3a7713b1edbc 1057 */
AnnaBridge 171:3a7713b1edbc 1058 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
AnnaBridge 171:3a7713b1edbc 1059
AnnaBridge 171:3a7713b1edbc 1060 /** @brief Disable RCC interrupt.
AnnaBridge 171:3a7713b1edbc 1061 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
AnnaBridge 171:3a7713b1edbc 1062 * This parameter can be any combination of the following values:
AnnaBridge 171:3a7713b1edbc 1063 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
AnnaBridge 171:3a7713b1edbc 1064 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
AnnaBridge 171:3a7713b1edbc 1065 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
AnnaBridge 171:3a7713b1edbc 1066 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
AnnaBridge 171:3a7713b1edbc 1067 * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
AnnaBridge 171:3a7713b1edbc 1068 @if STM32F105xx
AnnaBridge 171:3a7713b1edbc 1069 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
AnnaBridge 171:3a7713b1edbc 1070 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
AnnaBridge 171:3a7713b1edbc 1071 @elsif STM32F107xx
AnnaBridge 171:3a7713b1edbc 1072 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
AnnaBridge 171:3a7713b1edbc 1073 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
AnnaBridge 171:3a7713b1edbc 1074 @endif
AnnaBridge 171:3a7713b1edbc 1075 */
AnnaBridge 171:3a7713b1edbc 1076 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
AnnaBridge 171:3a7713b1edbc 1077
AnnaBridge 171:3a7713b1edbc 1078 /** @brief Clear the RCC's interrupt pending bits.
AnnaBridge 171:3a7713b1edbc 1079 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
AnnaBridge 171:3a7713b1edbc 1080 * This parameter can be any combination of the following values:
AnnaBridge 171:3a7713b1edbc 1081 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
AnnaBridge 171:3a7713b1edbc 1082 * @arg @ref RCC_IT_LSERDY LSE ready interrupt.
AnnaBridge 171:3a7713b1edbc 1083 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
AnnaBridge 171:3a7713b1edbc 1084 * @arg @ref RCC_IT_HSERDY HSE ready interrupt.
AnnaBridge 171:3a7713b1edbc 1085 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
AnnaBridge 171:3a7713b1edbc 1086 @if STM32F105xx
AnnaBridge 171:3a7713b1edbc 1087 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
AnnaBridge 171:3a7713b1edbc 1088 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
AnnaBridge 171:3a7713b1edbc 1089 @elsif STM32F107xx
AnnaBridge 171:3a7713b1edbc 1090 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
AnnaBridge 171:3a7713b1edbc 1091 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
AnnaBridge 171:3a7713b1edbc 1092 @endif
AnnaBridge 171:3a7713b1edbc 1093 * @arg @ref RCC_IT_CSS Clock Security System interrupt
AnnaBridge 171:3a7713b1edbc 1094 */
AnnaBridge 171:3a7713b1edbc 1095 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
AnnaBridge 171:3a7713b1edbc 1096
AnnaBridge 171:3a7713b1edbc 1097 /** @brief Check the RCC's interrupt has occurred or not.
AnnaBridge 171:3a7713b1edbc 1098 * @param __INTERRUPT__ specifies the RCC interrupt source to check.
AnnaBridge 171:3a7713b1edbc 1099 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 1100 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
AnnaBridge 171:3a7713b1edbc 1101 * @arg @ref RCC_IT_LSERDY LSE ready interrupt.
AnnaBridge 171:3a7713b1edbc 1102 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
AnnaBridge 171:3a7713b1edbc 1103 * @arg @ref RCC_IT_HSERDY HSE ready interrupt.
AnnaBridge 171:3a7713b1edbc 1104 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
AnnaBridge 171:3a7713b1edbc 1105 @if STM32F105xx
AnnaBridge 171:3a7713b1edbc 1106 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
AnnaBridge 171:3a7713b1edbc 1107 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
AnnaBridge 171:3a7713b1edbc 1108 @elsif STM32F107xx
AnnaBridge 171:3a7713b1edbc 1109 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
AnnaBridge 171:3a7713b1edbc 1110 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
AnnaBridge 171:3a7713b1edbc 1111 @endif
AnnaBridge 171:3a7713b1edbc 1112 * @arg @ref RCC_IT_CSS Clock Security System interrupt
AnnaBridge 171:3a7713b1edbc 1113 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
AnnaBridge 171:3a7713b1edbc 1114 */
AnnaBridge 171:3a7713b1edbc 1115 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
AnnaBridge 171:3a7713b1edbc 1116
AnnaBridge 171:3a7713b1edbc 1117 /** @brief Set RMVF bit to clear the reset flags.
AnnaBridge 171:3a7713b1edbc 1118 * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
AnnaBridge 171:3a7713b1edbc 1119 * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
AnnaBridge 171:3a7713b1edbc 1120 */
AnnaBridge 171:3a7713b1edbc 1121 #define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE)
AnnaBridge 171:3a7713b1edbc 1122
AnnaBridge 171:3a7713b1edbc 1123 /** @brief Check RCC flag is set or not.
AnnaBridge 171:3a7713b1edbc 1124 * @param __FLAG__ specifies the flag to check.
AnnaBridge 171:3a7713b1edbc 1125 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 1126 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.
AnnaBridge 171:3a7713b1edbc 1127 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.
AnnaBridge 171:3a7713b1edbc 1128 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.
AnnaBridge 171:3a7713b1edbc 1129 @if STM32F105xx
AnnaBridge 171:3a7713b1edbc 1130 * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready.
AnnaBridge 171:3a7713b1edbc 1131 * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready.
AnnaBridge 171:3a7713b1edbc 1132 @elsif STM32F107xx
AnnaBridge 171:3a7713b1edbc 1133 * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready.
AnnaBridge 171:3a7713b1edbc 1134 * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready.
AnnaBridge 171:3a7713b1edbc 1135 @endif
AnnaBridge 171:3a7713b1edbc 1136 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
AnnaBridge 171:3a7713b1edbc 1137 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
AnnaBridge 171:3a7713b1edbc 1138 * @arg @ref RCC_FLAG_PINRST Pin reset.
AnnaBridge 171:3a7713b1edbc 1139 * @arg @ref RCC_FLAG_PORRST POR/PDR reset.
AnnaBridge 171:3a7713b1edbc 1140 * @arg @ref RCC_FLAG_SFTRST Software reset.
AnnaBridge 171:3a7713b1edbc 1141 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
AnnaBridge 171:3a7713b1edbc 1142 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
AnnaBridge 171:3a7713b1edbc 1143 * @arg @ref RCC_FLAG_LPWRRST Low Power reset.
AnnaBridge 171:3a7713b1edbc 1144 * @retval The new state of __FLAG__ (TRUE or FALSE).
AnnaBridge 171:3a7713b1edbc 1145 */
AnnaBridge 171:3a7713b1edbc 1146 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \
AnnaBridge 171:3a7713b1edbc 1147 ((((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \
AnnaBridge 171:3a7713b1edbc 1148 RCC->CSR)) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
AnnaBridge 171:3a7713b1edbc 1149
AnnaBridge 171:3a7713b1edbc 1150 /**
AnnaBridge 171:3a7713b1edbc 1151 * @}
AnnaBridge 171:3a7713b1edbc 1152 */
AnnaBridge 171:3a7713b1edbc 1153
AnnaBridge 171:3a7713b1edbc 1154 /**
AnnaBridge 171:3a7713b1edbc 1155 * @}
AnnaBridge 171:3a7713b1edbc 1156 */
AnnaBridge 171:3a7713b1edbc 1157
AnnaBridge 171:3a7713b1edbc 1158 /* Include RCC HAL Extension module */
AnnaBridge 171:3a7713b1edbc 1159 #include "stm32f1xx_hal_rcc_ex.h"
AnnaBridge 171:3a7713b1edbc 1160
AnnaBridge 171:3a7713b1edbc 1161 /* Exported functions --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 1162 /** @addtogroup RCC_Exported_Functions
AnnaBridge 171:3a7713b1edbc 1163 * @{
AnnaBridge 171:3a7713b1edbc 1164 */
AnnaBridge 171:3a7713b1edbc 1165
AnnaBridge 171:3a7713b1edbc 1166 /** @addtogroup RCC_Exported_Functions_Group1
AnnaBridge 171:3a7713b1edbc 1167 * @{
AnnaBridge 171:3a7713b1edbc 1168 */
AnnaBridge 171:3a7713b1edbc 1169
AnnaBridge 171:3a7713b1edbc 1170 /* Initialization and de-initialization functions ******************************/
AnnaBridge 171:3a7713b1edbc 1171 HAL_StatusTypeDef HAL_RCC_DeInit(void);
AnnaBridge 171:3a7713b1edbc 1172 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
AnnaBridge 171:3a7713b1edbc 1173 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
AnnaBridge 171:3a7713b1edbc 1174
AnnaBridge 171:3a7713b1edbc 1175 /**
AnnaBridge 171:3a7713b1edbc 1176 * @}
AnnaBridge 171:3a7713b1edbc 1177 */
AnnaBridge 171:3a7713b1edbc 1178
AnnaBridge 171:3a7713b1edbc 1179 /** @addtogroup RCC_Exported_Functions_Group2
AnnaBridge 171:3a7713b1edbc 1180 * @{
AnnaBridge 171:3a7713b1edbc 1181 */
AnnaBridge 171:3a7713b1edbc 1182
AnnaBridge 171:3a7713b1edbc 1183 /* Peripheral Control functions ************************************************/
AnnaBridge 171:3a7713b1edbc 1184 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
AnnaBridge 171:3a7713b1edbc 1185 void HAL_RCC_EnableCSS(void);
AnnaBridge 171:3a7713b1edbc 1186 void HAL_RCC_DisableCSS(void);
AnnaBridge 171:3a7713b1edbc 1187 uint32_t HAL_RCC_GetSysClockFreq(void);
AnnaBridge 171:3a7713b1edbc 1188 uint32_t HAL_RCC_GetHCLKFreq(void);
AnnaBridge 171:3a7713b1edbc 1189 uint32_t HAL_RCC_GetPCLK1Freq(void);
AnnaBridge 171:3a7713b1edbc 1190 uint32_t HAL_RCC_GetPCLK2Freq(void);
AnnaBridge 171:3a7713b1edbc 1191 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
AnnaBridge 171:3a7713b1edbc 1192 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
AnnaBridge 171:3a7713b1edbc 1193
AnnaBridge 171:3a7713b1edbc 1194 /* CSS NMI IRQ handler */
AnnaBridge 171:3a7713b1edbc 1195 void HAL_RCC_NMI_IRQHandler(void);
AnnaBridge 171:3a7713b1edbc 1196
AnnaBridge 171:3a7713b1edbc 1197 /* User Callbacks in non blocking mode (IT mode) */
AnnaBridge 171:3a7713b1edbc 1198 void HAL_RCC_CSSCallback(void);
AnnaBridge 171:3a7713b1edbc 1199
AnnaBridge 171:3a7713b1edbc 1200 /**
AnnaBridge 171:3a7713b1edbc 1201 * @}
AnnaBridge 171:3a7713b1edbc 1202 */
AnnaBridge 171:3a7713b1edbc 1203
AnnaBridge 171:3a7713b1edbc 1204 /**
AnnaBridge 171:3a7713b1edbc 1205 * @}
AnnaBridge 171:3a7713b1edbc 1206 */
AnnaBridge 171:3a7713b1edbc 1207
AnnaBridge 171:3a7713b1edbc 1208 /** @addtogroup RCC_Private_Constants
AnnaBridge 171:3a7713b1edbc 1209 * @{
AnnaBridge 171:3a7713b1edbc 1210 */
AnnaBridge 171:3a7713b1edbc 1211
AnnaBridge 171:3a7713b1edbc 1212 /** @defgroup RCC_Timeout RCC Timeout
AnnaBridge 171:3a7713b1edbc 1213 * @{
AnnaBridge 171:3a7713b1edbc 1214 */
AnnaBridge 171:3a7713b1edbc 1215
AnnaBridge 171:3a7713b1edbc 1216 /* Disable Backup domain write protection state change timeout */
AnnaBridge 171:3a7713b1edbc 1217 #define RCC_DBP_TIMEOUT_VALUE 100U /* 100 ms */
AnnaBridge 171:3a7713b1edbc 1218 /* LSE state change timeout */
AnnaBridge 171:3a7713b1edbc 1219 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
AnnaBridge 171:3a7713b1edbc 1220 #define CLOCKSWITCH_TIMEOUT_VALUE 5000 /* 5 s */
AnnaBridge 171:3a7713b1edbc 1221 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
AnnaBridge 171:3a7713b1edbc 1222 #define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
AnnaBridge 171:3a7713b1edbc 1223 #define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
AnnaBridge 171:3a7713b1edbc 1224 #define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
AnnaBridge 171:3a7713b1edbc 1225
AnnaBridge 171:3a7713b1edbc 1226 /**
AnnaBridge 171:3a7713b1edbc 1227 * @}
AnnaBridge 171:3a7713b1edbc 1228 */
AnnaBridge 171:3a7713b1edbc 1229
AnnaBridge 171:3a7713b1edbc 1230 /** @defgroup RCC_Register_Offset Register offsets
AnnaBridge 171:3a7713b1edbc 1231 * @{
AnnaBridge 171:3a7713b1edbc 1232 */
AnnaBridge 171:3a7713b1edbc 1233 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
AnnaBridge 171:3a7713b1edbc 1234 #define RCC_CR_OFFSET 0x00U
AnnaBridge 171:3a7713b1edbc 1235 #define RCC_CFGR_OFFSET 0x04U
AnnaBridge 171:3a7713b1edbc 1236 #define RCC_CIR_OFFSET 0x08U
AnnaBridge 171:3a7713b1edbc 1237 #define RCC_BDCR_OFFSET 0x20U
AnnaBridge 171:3a7713b1edbc 1238 #define RCC_CSR_OFFSET 0x24U
AnnaBridge 171:3a7713b1edbc 1239
AnnaBridge 171:3a7713b1edbc 1240 /**
AnnaBridge 171:3a7713b1edbc 1241 * @}
AnnaBridge 171:3a7713b1edbc 1242 */
AnnaBridge 171:3a7713b1edbc 1243
AnnaBridge 171:3a7713b1edbc 1244 /** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
AnnaBridge 171:3a7713b1edbc 1245 * @brief RCC registers bit address in the alias region
AnnaBridge 171:3a7713b1edbc 1246 * @{
AnnaBridge 171:3a7713b1edbc 1247 */
AnnaBridge 171:3a7713b1edbc 1248 #define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
AnnaBridge 171:3a7713b1edbc 1249 #define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
AnnaBridge 171:3a7713b1edbc 1250 #define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
AnnaBridge 171:3a7713b1edbc 1251 #define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET)
AnnaBridge 171:3a7713b1edbc 1252 #define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
AnnaBridge 171:3a7713b1edbc 1253
AnnaBridge 171:3a7713b1edbc 1254 /* --- CR Register ---*/
AnnaBridge 171:3a7713b1edbc 1255 /* Alias word address of HSION bit */
AnnaBridge 171:3a7713b1edbc 1256 #define RCC_HSION_BIT_NUMBER RCC_CR_HSION_Pos
AnnaBridge 171:3a7713b1edbc 1257 #define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))
AnnaBridge 171:3a7713b1edbc 1258 /* Alias word address of HSEON bit */
AnnaBridge 171:3a7713b1edbc 1259 #define RCC_HSEON_BIT_NUMBER RCC_CR_HSEON_Pos
AnnaBridge 171:3a7713b1edbc 1260 #define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))
AnnaBridge 171:3a7713b1edbc 1261 /* Alias word address of CSSON bit */
AnnaBridge 171:3a7713b1edbc 1262 #define RCC_CSSON_BIT_NUMBER RCC_CR_CSSON_Pos
AnnaBridge 171:3a7713b1edbc 1263 #define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))
AnnaBridge 171:3a7713b1edbc 1264 /* Alias word address of PLLON bit */
AnnaBridge 171:3a7713b1edbc 1265 #define RCC_PLLON_BIT_NUMBER RCC_CR_PLLON_Pos
AnnaBridge 171:3a7713b1edbc 1266 #define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))
AnnaBridge 171:3a7713b1edbc 1267
AnnaBridge 171:3a7713b1edbc 1268 /* --- CSR Register ---*/
AnnaBridge 171:3a7713b1edbc 1269 /* Alias word address of LSION bit */
AnnaBridge 171:3a7713b1edbc 1270 #define RCC_LSION_BIT_NUMBER RCC_CSR_LSION_Pos
AnnaBridge 171:3a7713b1edbc 1271 #define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))
AnnaBridge 171:3a7713b1edbc 1272
AnnaBridge 171:3a7713b1edbc 1273 /* Alias word address of RMVF bit */
AnnaBridge 171:3a7713b1edbc 1274 #define RCC_RMVF_BIT_NUMBER RCC_CSR_RMVF_Pos
AnnaBridge 171:3a7713b1edbc 1275 #define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))
AnnaBridge 171:3a7713b1edbc 1276
AnnaBridge 171:3a7713b1edbc 1277 /* --- BDCR Registers ---*/
AnnaBridge 171:3a7713b1edbc 1278 /* Alias word address of LSEON bit */
AnnaBridge 171:3a7713b1edbc 1279 #define RCC_LSEON_BIT_NUMBER RCC_BDCR_LSEON_Pos
AnnaBridge 171:3a7713b1edbc 1280 #define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))
AnnaBridge 171:3a7713b1edbc 1281
AnnaBridge 171:3a7713b1edbc 1282 /* Alias word address of LSEON bit */
AnnaBridge 171:3a7713b1edbc 1283 #define RCC_LSEBYP_BIT_NUMBER RCC_BDCR_LSEBYP_Pos
AnnaBridge 171:3a7713b1edbc 1284 #define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))
AnnaBridge 171:3a7713b1edbc 1285
AnnaBridge 171:3a7713b1edbc 1286 /* Alias word address of RTCEN bit */
AnnaBridge 171:3a7713b1edbc 1287 #define RCC_RTCEN_BIT_NUMBER RCC_BDCR_RTCEN_Pos
AnnaBridge 171:3a7713b1edbc 1288 #define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))
AnnaBridge 171:3a7713b1edbc 1289
AnnaBridge 171:3a7713b1edbc 1290 /* Alias word address of BDRST bit */
AnnaBridge 171:3a7713b1edbc 1291 #define RCC_BDRST_BIT_NUMBER RCC_BDCR_BDRST_Pos
AnnaBridge 171:3a7713b1edbc 1292 #define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)))
AnnaBridge 171:3a7713b1edbc 1293
AnnaBridge 171:3a7713b1edbc 1294 /**
AnnaBridge 171:3a7713b1edbc 1295 * @}
AnnaBridge 171:3a7713b1edbc 1296 */
AnnaBridge 171:3a7713b1edbc 1297
AnnaBridge 171:3a7713b1edbc 1298 /* CR register byte 2 (Bits[23:16]) base address */
AnnaBridge 171:3a7713b1edbc 1299 #define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
AnnaBridge 171:3a7713b1edbc 1300
AnnaBridge 171:3a7713b1edbc 1301 /* CIR register byte 1 (Bits[15:8]) base address */
AnnaBridge 171:3a7713b1edbc 1302 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
AnnaBridge 171:3a7713b1edbc 1303
AnnaBridge 171:3a7713b1edbc 1304 /* CIR register byte 2 (Bits[23:16]) base address */
AnnaBridge 171:3a7713b1edbc 1305 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
AnnaBridge 171:3a7713b1edbc 1306
AnnaBridge 171:3a7713b1edbc 1307 /* Defines used for Flags */
AnnaBridge 171:3a7713b1edbc 1308 #define CR_REG_INDEX ((uint8_t)1)
AnnaBridge 171:3a7713b1edbc 1309 #define BDCR_REG_INDEX ((uint8_t)2)
AnnaBridge 171:3a7713b1edbc 1310 #define CSR_REG_INDEX ((uint8_t)3)
AnnaBridge 171:3a7713b1edbc 1311
AnnaBridge 171:3a7713b1edbc 1312 #define RCC_FLAG_MASK ((uint8_t)0x1F)
AnnaBridge 171:3a7713b1edbc 1313
AnnaBridge 171:3a7713b1edbc 1314 /**
AnnaBridge 171:3a7713b1edbc 1315 * @}
AnnaBridge 171:3a7713b1edbc 1316 */
AnnaBridge 171:3a7713b1edbc 1317
AnnaBridge 171:3a7713b1edbc 1318 /** @addtogroup RCC_Private_Macros
AnnaBridge 171:3a7713b1edbc 1319 * @{
AnnaBridge 171:3a7713b1edbc 1320 */
AnnaBridge 171:3a7713b1edbc 1321 /** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy
AnnaBridge 171:3a7713b1edbc 1322 * @{
AnnaBridge 171:3a7713b1edbc 1323 */
AnnaBridge 171:3a7713b1edbc 1324 #define __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
AnnaBridge 171:3a7713b1edbc 1325 #define __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
AnnaBridge 171:3a7713b1edbc 1326 #define __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
AnnaBridge 171:3a7713b1edbc 1327 #define __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
AnnaBridge 171:3a7713b1edbc 1328 /**
AnnaBridge 171:3a7713b1edbc 1329 * @}
AnnaBridge 171:3a7713b1edbc 1330 */
AnnaBridge 171:3a7713b1edbc 1331
AnnaBridge 171:3a7713b1edbc 1332 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || \
AnnaBridge 171:3a7713b1edbc 1333 ((__SOURCE__) == RCC_PLLSOURCE_HSE))
AnnaBridge 171:3a7713b1edbc 1334 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
AnnaBridge 171:3a7713b1edbc 1335 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
AnnaBridge 171:3a7713b1edbc 1336 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
AnnaBridge 171:3a7713b1edbc 1337 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
AnnaBridge 171:3a7713b1edbc 1338 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
AnnaBridge 171:3a7713b1edbc 1339 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
AnnaBridge 171:3a7713b1edbc 1340 ((__HSE__) == RCC_HSE_BYPASS))
AnnaBridge 171:3a7713b1edbc 1341 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
AnnaBridge 171:3a7713b1edbc 1342 ((__LSE__) == RCC_LSE_BYPASS))
AnnaBridge 171:3a7713b1edbc 1343 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
AnnaBridge 171:3a7713b1edbc 1344 #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
AnnaBridge 171:3a7713b1edbc 1345 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
AnnaBridge 171:3a7713b1edbc 1346 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
AnnaBridge 171:3a7713b1edbc 1347 ((__PLL__) == RCC_PLL_ON))
AnnaBridge 171:3a7713b1edbc 1348
AnnaBridge 171:3a7713b1edbc 1349 #define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
AnnaBridge 171:3a7713b1edbc 1350 (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
AnnaBridge 171:3a7713b1edbc 1351 (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \
AnnaBridge 171:3a7713b1edbc 1352 (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
AnnaBridge 171:3a7713b1edbc 1353 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
AnnaBridge 171:3a7713b1edbc 1354 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
AnnaBridge 171:3a7713b1edbc 1355 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
AnnaBridge 171:3a7713b1edbc 1356 #define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
AnnaBridge 171:3a7713b1edbc 1357 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
AnnaBridge 171:3a7713b1edbc 1358 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
AnnaBridge 171:3a7713b1edbc 1359 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
AnnaBridge 171:3a7713b1edbc 1360 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
AnnaBridge 171:3a7713b1edbc 1361 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
AnnaBridge 171:3a7713b1edbc 1362 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
AnnaBridge 171:3a7713b1edbc 1363 ((__HCLK__) == RCC_SYSCLK_DIV512))
AnnaBridge 171:3a7713b1edbc 1364 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
AnnaBridge 171:3a7713b1edbc 1365 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
AnnaBridge 171:3a7713b1edbc 1366 ((__PCLK__) == RCC_HCLK_DIV16))
AnnaBridge 171:3a7713b1edbc 1367 #define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
AnnaBridge 171:3a7713b1edbc 1368 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1))
AnnaBridge 171:3a7713b1edbc 1369 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
AnnaBridge 171:3a7713b1edbc 1370 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
AnnaBridge 171:3a7713b1edbc 1371 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
AnnaBridge 171:3a7713b1edbc 1372 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128))
AnnaBridge 171:3a7713b1edbc 1373
AnnaBridge 171:3a7713b1edbc 1374 /**
AnnaBridge 171:3a7713b1edbc 1375 * @}
AnnaBridge 171:3a7713b1edbc 1376 */
AnnaBridge 171:3a7713b1edbc 1377
AnnaBridge 171:3a7713b1edbc 1378 /**
AnnaBridge 171:3a7713b1edbc 1379 * @}
AnnaBridge 171:3a7713b1edbc 1380 */
AnnaBridge 171:3a7713b1edbc 1381
AnnaBridge 171:3a7713b1edbc 1382 /**
AnnaBridge 171:3a7713b1edbc 1383 * @}
AnnaBridge 171:3a7713b1edbc 1384 */
AnnaBridge 171:3a7713b1edbc 1385
AnnaBridge 171:3a7713b1edbc 1386 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 1387 }
AnnaBridge 171:3a7713b1edbc 1388 #endif
AnnaBridge 171:3a7713b1edbc 1389
AnnaBridge 171:3a7713b1edbc 1390 #endif /* __STM32F1xx_HAL_RCC_H */
AnnaBridge 171:3a7713b1edbc 1391
AnnaBridge 171:3a7713b1edbc 1392 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
AnnaBridge 171:3a7713b1edbc 1393