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TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_dma.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 143:86740a56073b 1 /**
AnnaBridge 143:86740a56073b 2 ******************************************************************************
AnnaBridge 143:86740a56073b 3 * @file stm32f1xx_ll_dma.h
AnnaBridge 143:86740a56073b 4 * @author MCD Application Team
AnnaBridge 143:86740a56073b 5 * @brief Header file of DMA LL module.
AnnaBridge 143:86740a56073b 6 ******************************************************************************
AnnaBridge 143:86740a56073b 7 * @attention
AnnaBridge 143:86740a56073b 8 *
AnnaBridge 143:86740a56073b 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 143:86740a56073b 10 *
AnnaBridge 143:86740a56073b 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 143:86740a56073b 12 * are permitted provided that the following conditions are met:
AnnaBridge 143:86740a56073b 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 143:86740a56073b 14 * this list of conditions and the following disclaimer.
AnnaBridge 143:86740a56073b 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 143:86740a56073b 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 143:86740a56073b 17 * and/or other materials provided with the distribution.
AnnaBridge 143:86740a56073b 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 143:86740a56073b 19 * may be used to endorse or promote products derived from this software
AnnaBridge 143:86740a56073b 20 * without specific prior written permission.
AnnaBridge 143:86740a56073b 21 *
AnnaBridge 143:86740a56073b 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 143:86740a56073b 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 143:86740a56073b 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 143:86740a56073b 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 143:86740a56073b 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 143:86740a56073b 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 143:86740a56073b 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 143:86740a56073b 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 143:86740a56073b 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 143:86740a56073b 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 143:86740a56073b 32 *
AnnaBridge 143:86740a56073b 33 ******************************************************************************
AnnaBridge 143:86740a56073b 34 */
AnnaBridge 143:86740a56073b 35
AnnaBridge 143:86740a56073b 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 143:86740a56073b 37 #ifndef __STM32F1xx_LL_DMA_H
AnnaBridge 143:86740a56073b 38 #define __STM32F1xx_LL_DMA_H
AnnaBridge 143:86740a56073b 39
AnnaBridge 143:86740a56073b 40 #ifdef __cplusplus
AnnaBridge 143:86740a56073b 41 extern "C" {
AnnaBridge 143:86740a56073b 42 #endif
AnnaBridge 143:86740a56073b 43
AnnaBridge 143:86740a56073b 44 /* Includes ------------------------------------------------------------------*/
AnnaBridge 143:86740a56073b 45 #include "stm32f1xx.h"
AnnaBridge 143:86740a56073b 46
AnnaBridge 143:86740a56073b 47 /** @addtogroup STM32F1xx_LL_Driver
AnnaBridge 143:86740a56073b 48 * @{
AnnaBridge 143:86740a56073b 49 */
AnnaBridge 143:86740a56073b 50
AnnaBridge 143:86740a56073b 51 #if defined (DMA1) || defined (DMA2)
AnnaBridge 143:86740a56073b 52
AnnaBridge 143:86740a56073b 53 /** @defgroup DMA_LL DMA
AnnaBridge 143:86740a56073b 54 * @{
AnnaBridge 143:86740a56073b 55 */
AnnaBridge 143:86740a56073b 56
AnnaBridge 143:86740a56073b 57 /* Private types -------------------------------------------------------------*/
AnnaBridge 143:86740a56073b 58 /* Private variables ---------------------------------------------------------*/
AnnaBridge 143:86740a56073b 59 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
AnnaBridge 143:86740a56073b 60 * @{
AnnaBridge 143:86740a56073b 61 */
AnnaBridge 143:86740a56073b 62 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
AnnaBridge 143:86740a56073b 63 static const uint8_t CHANNEL_OFFSET_TAB[] =
AnnaBridge 143:86740a56073b 64 {
AnnaBridge 143:86740a56073b 65 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
AnnaBridge 143:86740a56073b 66 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
AnnaBridge 143:86740a56073b 67 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
AnnaBridge 143:86740a56073b 68 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
AnnaBridge 143:86740a56073b 69 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
AnnaBridge 143:86740a56073b 70 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
AnnaBridge 143:86740a56073b 71 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
AnnaBridge 143:86740a56073b 72 };
AnnaBridge 143:86740a56073b 73 /**
AnnaBridge 143:86740a56073b 74 * @}
AnnaBridge 143:86740a56073b 75 */
AnnaBridge 143:86740a56073b 76 /* Private constants ---------------------------------------------------------*/
AnnaBridge 143:86740a56073b 77 /* Private macros ------------------------------------------------------------*/
AnnaBridge 143:86740a56073b 78 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 143:86740a56073b 79 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
AnnaBridge 143:86740a56073b 80 * @{
AnnaBridge 143:86740a56073b 81 */
AnnaBridge 143:86740a56073b 82 /**
AnnaBridge 143:86740a56073b 83 * @}
AnnaBridge 143:86740a56073b 84 */
AnnaBridge 143:86740a56073b 85 #endif /*USE_FULL_LL_DRIVER*/
AnnaBridge 143:86740a56073b 86
AnnaBridge 143:86740a56073b 87 /* Exported types ------------------------------------------------------------*/
AnnaBridge 143:86740a56073b 88 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 143:86740a56073b 89 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
AnnaBridge 143:86740a56073b 90 * @{
AnnaBridge 143:86740a56073b 91 */
AnnaBridge 143:86740a56073b 92 typedef struct
AnnaBridge 143:86740a56073b 93 {
AnnaBridge 143:86740a56073b 94 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
AnnaBridge 143:86740a56073b 95 or as Source base address in case of memory to memory transfer direction.
AnnaBridge 143:86740a56073b 96
AnnaBridge 143:86740a56073b 97 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
AnnaBridge 143:86740a56073b 98
AnnaBridge 143:86740a56073b 99 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
AnnaBridge 143:86740a56073b 100 or as Destination base address in case of memory to memory transfer direction.
AnnaBridge 143:86740a56073b 101
AnnaBridge 143:86740a56073b 102 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
AnnaBridge 143:86740a56073b 103
AnnaBridge 143:86740a56073b 104 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
AnnaBridge 143:86740a56073b 105 from memory to memory or from peripheral to memory.
AnnaBridge 143:86740a56073b 106 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
AnnaBridge 143:86740a56073b 107
AnnaBridge 143:86740a56073b 108 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
AnnaBridge 143:86740a56073b 109
AnnaBridge 143:86740a56073b 110 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
AnnaBridge 143:86740a56073b 111 This parameter can be a value of @ref DMA_LL_EC_MODE
AnnaBridge 143:86740a56073b 112 @note: The circular buffer mode cannot be used if the memory to memory
AnnaBridge 143:86740a56073b 113 data transfer direction is configured on the selected Channel
AnnaBridge 143:86740a56073b 114
AnnaBridge 143:86740a56073b 115 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
AnnaBridge 143:86740a56073b 116
AnnaBridge 143:86740a56073b 117 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
AnnaBridge 143:86740a56073b 118 is incremented or not.
AnnaBridge 143:86740a56073b 119 This parameter can be a value of @ref DMA_LL_EC_PERIPH
AnnaBridge 143:86740a56073b 120
AnnaBridge 143:86740a56073b 121 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
AnnaBridge 143:86740a56073b 122
AnnaBridge 143:86740a56073b 123 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
AnnaBridge 143:86740a56073b 124 is incremented or not.
AnnaBridge 143:86740a56073b 125 This parameter can be a value of @ref DMA_LL_EC_MEMORY
AnnaBridge 143:86740a56073b 126
AnnaBridge 143:86740a56073b 127 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
AnnaBridge 143:86740a56073b 128
AnnaBridge 143:86740a56073b 129 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
AnnaBridge 143:86740a56073b 130 in case of memory to memory transfer direction.
AnnaBridge 143:86740a56073b 131 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
AnnaBridge 143:86740a56073b 132
AnnaBridge 143:86740a56073b 133 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
AnnaBridge 143:86740a56073b 134
AnnaBridge 143:86740a56073b 135 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
AnnaBridge 143:86740a56073b 136 in case of memory to memory transfer direction.
AnnaBridge 143:86740a56073b 137 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
AnnaBridge 143:86740a56073b 138
AnnaBridge 143:86740a56073b 139 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
AnnaBridge 143:86740a56073b 140
AnnaBridge 143:86740a56073b 141 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
AnnaBridge 143:86740a56073b 142 The data unit is equal to the source buffer configuration set in PeripheralSize
AnnaBridge 143:86740a56073b 143 or MemorySize parameters depending in the transfer direction.
AnnaBridge 143:86740a56073b 144 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
AnnaBridge 143:86740a56073b 145
AnnaBridge 143:86740a56073b 146 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
AnnaBridge 143:86740a56073b 147
AnnaBridge 143:86740a56073b 148 uint32_t Priority; /*!< Specifies the channel priority level.
AnnaBridge 143:86740a56073b 149 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
AnnaBridge 143:86740a56073b 150
AnnaBridge 143:86740a56073b 151 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
AnnaBridge 143:86740a56073b 152
AnnaBridge 143:86740a56073b 153 } LL_DMA_InitTypeDef;
AnnaBridge 143:86740a56073b 154 /**
AnnaBridge 143:86740a56073b 155 * @}
AnnaBridge 143:86740a56073b 156 */
AnnaBridge 143:86740a56073b 157 #endif /*USE_FULL_LL_DRIVER*/
AnnaBridge 143:86740a56073b 158
AnnaBridge 143:86740a56073b 159 /* Exported constants --------------------------------------------------------*/
AnnaBridge 143:86740a56073b 160 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
AnnaBridge 143:86740a56073b 161 * @{
AnnaBridge 143:86740a56073b 162 */
AnnaBridge 143:86740a56073b 163 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
AnnaBridge 143:86740a56073b 164 * @brief Flags defines which can be used with LL_DMA_WriteReg function
AnnaBridge 143:86740a56073b 165 * @{
AnnaBridge 143:86740a56073b 166 */
AnnaBridge 143:86740a56073b 167 #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
AnnaBridge 143:86740a56073b 168 #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
AnnaBridge 143:86740a56073b 169 #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
AnnaBridge 143:86740a56073b 170 #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
AnnaBridge 143:86740a56073b 171 #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
AnnaBridge 143:86740a56073b 172 #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
AnnaBridge 143:86740a56073b 173 #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
AnnaBridge 143:86740a56073b 174 #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
AnnaBridge 143:86740a56073b 175 #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
AnnaBridge 143:86740a56073b 176 #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
AnnaBridge 143:86740a56073b 177 #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
AnnaBridge 143:86740a56073b 178 #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
AnnaBridge 143:86740a56073b 179 #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
AnnaBridge 143:86740a56073b 180 #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
AnnaBridge 143:86740a56073b 181 #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
AnnaBridge 143:86740a56073b 182 #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
AnnaBridge 143:86740a56073b 183 #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
AnnaBridge 143:86740a56073b 184 #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
AnnaBridge 143:86740a56073b 185 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
AnnaBridge 143:86740a56073b 186 #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
AnnaBridge 143:86740a56073b 187 #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
AnnaBridge 143:86740a56073b 188 #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
AnnaBridge 143:86740a56073b 189 #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
AnnaBridge 143:86740a56073b 190 #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
AnnaBridge 143:86740a56073b 191 #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
AnnaBridge 143:86740a56073b 192 #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
AnnaBridge 143:86740a56073b 193 #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
AnnaBridge 143:86740a56073b 194 #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
AnnaBridge 143:86740a56073b 195 /**
AnnaBridge 143:86740a56073b 196 * @}
AnnaBridge 143:86740a56073b 197 */
AnnaBridge 143:86740a56073b 198
AnnaBridge 143:86740a56073b 199 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge 143:86740a56073b 200 * @brief Flags defines which can be used with LL_DMA_ReadReg function
AnnaBridge 143:86740a56073b 201 * @{
AnnaBridge 143:86740a56073b 202 */
AnnaBridge 143:86740a56073b 203 #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
AnnaBridge 143:86740a56073b 204 #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
AnnaBridge 143:86740a56073b 205 #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
AnnaBridge 143:86740a56073b 206 #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
AnnaBridge 143:86740a56073b 207 #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
AnnaBridge 143:86740a56073b 208 #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
AnnaBridge 143:86740a56073b 209 #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
AnnaBridge 143:86740a56073b 210 #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
AnnaBridge 143:86740a56073b 211 #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
AnnaBridge 143:86740a56073b 212 #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
AnnaBridge 143:86740a56073b 213 #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
AnnaBridge 143:86740a56073b 214 #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
AnnaBridge 143:86740a56073b 215 #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
AnnaBridge 143:86740a56073b 216 #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
AnnaBridge 143:86740a56073b 217 #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
AnnaBridge 143:86740a56073b 218 #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
AnnaBridge 143:86740a56073b 219 #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
AnnaBridge 143:86740a56073b 220 #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
AnnaBridge 143:86740a56073b 221 #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
AnnaBridge 143:86740a56073b 222 #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
AnnaBridge 143:86740a56073b 223 #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
AnnaBridge 143:86740a56073b 224 #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
AnnaBridge 143:86740a56073b 225 #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
AnnaBridge 143:86740a56073b 226 #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
AnnaBridge 143:86740a56073b 227 #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
AnnaBridge 143:86740a56073b 228 #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
AnnaBridge 143:86740a56073b 229 #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
AnnaBridge 143:86740a56073b 230 #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
AnnaBridge 143:86740a56073b 231 /**
AnnaBridge 143:86740a56073b 232 * @}
AnnaBridge 143:86740a56073b 233 */
AnnaBridge 143:86740a56073b 234
AnnaBridge 143:86740a56073b 235 /** @defgroup DMA_LL_EC_IT IT Defines
AnnaBridge 143:86740a56073b 236 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
AnnaBridge 143:86740a56073b 237 * @{
AnnaBridge 143:86740a56073b 238 */
AnnaBridge 143:86740a56073b 239 #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
AnnaBridge 143:86740a56073b 240 #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
AnnaBridge 143:86740a56073b 241 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
AnnaBridge 143:86740a56073b 242 /**
AnnaBridge 143:86740a56073b 243 * @}
AnnaBridge 143:86740a56073b 244 */
AnnaBridge 143:86740a56073b 245
AnnaBridge 143:86740a56073b 246 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
AnnaBridge 143:86740a56073b 247 * @{
AnnaBridge 143:86740a56073b 248 */
AnnaBridge 143:86740a56073b 249 #define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */
AnnaBridge 143:86740a56073b 250 #define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */
AnnaBridge 143:86740a56073b 251 #define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */
AnnaBridge 143:86740a56073b 252 #define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */
AnnaBridge 143:86740a56073b 253 #define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */
AnnaBridge 143:86740a56073b 254 #define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */
AnnaBridge 143:86740a56073b 255 #define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */
AnnaBridge 143:86740a56073b 256 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 143:86740a56073b 257 #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
AnnaBridge 143:86740a56073b 258 #endif /*USE_FULL_LL_DRIVER*/
AnnaBridge 143:86740a56073b 259 /**
AnnaBridge 143:86740a56073b 260 * @}
AnnaBridge 143:86740a56073b 261 */
AnnaBridge 143:86740a56073b 262
AnnaBridge 143:86740a56073b 263 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
AnnaBridge 143:86740a56073b 264 * @{
AnnaBridge 143:86740a56073b 265 */
AnnaBridge 143:86740a56073b 266 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
AnnaBridge 143:86740a56073b 267 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
AnnaBridge 143:86740a56073b 268 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
AnnaBridge 143:86740a56073b 269 /**
AnnaBridge 143:86740a56073b 270 * @}
AnnaBridge 143:86740a56073b 271 */
AnnaBridge 143:86740a56073b 272
AnnaBridge 143:86740a56073b 273 /** @defgroup DMA_LL_EC_MODE Transfer mode
AnnaBridge 143:86740a56073b 274 * @{
AnnaBridge 143:86740a56073b 275 */
AnnaBridge 143:86740a56073b 276 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
AnnaBridge 143:86740a56073b 277 #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
AnnaBridge 143:86740a56073b 278 /**
AnnaBridge 143:86740a56073b 279 * @}
AnnaBridge 143:86740a56073b 280 */
AnnaBridge 143:86740a56073b 281
AnnaBridge 143:86740a56073b 282 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
AnnaBridge 143:86740a56073b 283 * @{
AnnaBridge 143:86740a56073b 284 */
AnnaBridge 143:86740a56073b 285 #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
AnnaBridge 143:86740a56073b 286 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
AnnaBridge 143:86740a56073b 287 /**
AnnaBridge 143:86740a56073b 288 * @}
AnnaBridge 143:86740a56073b 289 */
AnnaBridge 143:86740a56073b 290
AnnaBridge 143:86740a56073b 291 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
AnnaBridge 143:86740a56073b 292 * @{
AnnaBridge 143:86740a56073b 293 */
AnnaBridge 143:86740a56073b 294 #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
AnnaBridge 143:86740a56073b 295 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
AnnaBridge 143:86740a56073b 296 /**
AnnaBridge 143:86740a56073b 297 * @}
AnnaBridge 143:86740a56073b 298 */
AnnaBridge 143:86740a56073b 299
AnnaBridge 143:86740a56073b 300 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
AnnaBridge 143:86740a56073b 301 * @{
AnnaBridge 143:86740a56073b 302 */
AnnaBridge 143:86740a56073b 303 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
AnnaBridge 143:86740a56073b 304 #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
AnnaBridge 143:86740a56073b 305 #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
AnnaBridge 143:86740a56073b 306 /**
AnnaBridge 143:86740a56073b 307 * @}
AnnaBridge 143:86740a56073b 308 */
AnnaBridge 143:86740a56073b 309
AnnaBridge 143:86740a56073b 310 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
AnnaBridge 143:86740a56073b 311 * @{
AnnaBridge 143:86740a56073b 312 */
AnnaBridge 143:86740a56073b 313 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
AnnaBridge 143:86740a56073b 314 #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
AnnaBridge 143:86740a56073b 315 #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
AnnaBridge 143:86740a56073b 316 /**
AnnaBridge 143:86740a56073b 317 * @}
AnnaBridge 143:86740a56073b 318 */
AnnaBridge 143:86740a56073b 319
AnnaBridge 143:86740a56073b 320 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
AnnaBridge 143:86740a56073b 321 * @{
AnnaBridge 143:86740a56073b 322 */
AnnaBridge 143:86740a56073b 323 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
AnnaBridge 143:86740a56073b 324 #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
AnnaBridge 143:86740a56073b 325 #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
AnnaBridge 143:86740a56073b 326 #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
AnnaBridge 143:86740a56073b 327 /**
AnnaBridge 143:86740a56073b 328 * @}
AnnaBridge 143:86740a56073b 329 */
AnnaBridge 143:86740a56073b 330
AnnaBridge 143:86740a56073b 331 /**
AnnaBridge 143:86740a56073b 332 * @}
AnnaBridge 143:86740a56073b 333 */
AnnaBridge 143:86740a56073b 334
AnnaBridge 143:86740a56073b 335 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 143:86740a56073b 336 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
AnnaBridge 143:86740a56073b 337 * @{
AnnaBridge 143:86740a56073b 338 */
AnnaBridge 143:86740a56073b 339
AnnaBridge 143:86740a56073b 340 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
AnnaBridge 143:86740a56073b 341 * @{
AnnaBridge 143:86740a56073b 342 */
AnnaBridge 143:86740a56073b 343 /**
AnnaBridge 143:86740a56073b 344 * @brief Write a value in DMA register
AnnaBridge 143:86740a56073b 345 * @param __INSTANCE__ DMA Instance
AnnaBridge 143:86740a56073b 346 * @param __REG__ Register to be written
AnnaBridge 143:86740a56073b 347 * @param __VALUE__ Value to be written in the register
AnnaBridge 143:86740a56073b 348 * @retval None
AnnaBridge 143:86740a56073b 349 */
AnnaBridge 143:86740a56073b 350 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge 143:86740a56073b 351
AnnaBridge 143:86740a56073b 352 /**
AnnaBridge 143:86740a56073b 353 * @brief Read a value in DMA register
AnnaBridge 143:86740a56073b 354 * @param __INSTANCE__ DMA Instance
AnnaBridge 143:86740a56073b 355 * @param __REG__ Register to be read
AnnaBridge 143:86740a56073b 356 * @retval Register value
AnnaBridge 143:86740a56073b 357 */
AnnaBridge 143:86740a56073b 358 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge 143:86740a56073b 359 /**
AnnaBridge 143:86740a56073b 360 * @}
AnnaBridge 143:86740a56073b 361 */
AnnaBridge 143:86740a56073b 362
AnnaBridge 143:86740a56073b 363 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
AnnaBridge 143:86740a56073b 364 * @{
AnnaBridge 143:86740a56073b 365 */
AnnaBridge 143:86740a56073b 366
AnnaBridge 143:86740a56073b 367 /**
AnnaBridge 143:86740a56073b 368 * @brief Convert DMAx_Channely into DMAx
AnnaBridge 143:86740a56073b 369 * @param __CHANNEL_INSTANCE__ DMAx_Channely
AnnaBridge 143:86740a56073b 370 * @retval DMAx
AnnaBridge 143:86740a56073b 371 */
AnnaBridge 143:86740a56073b 372 #if defined(DMA2)
AnnaBridge 143:86740a56073b 373 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
AnnaBridge 143:86740a56073b 374 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
AnnaBridge 143:86740a56073b 375 #else
AnnaBridge 143:86740a56073b 376 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
AnnaBridge 143:86740a56073b 377 #endif
AnnaBridge 143:86740a56073b 378
AnnaBridge 143:86740a56073b 379 /**
AnnaBridge 143:86740a56073b 380 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
AnnaBridge 143:86740a56073b 381 * @param __CHANNEL_INSTANCE__ DMAx_Channely
AnnaBridge 143:86740a56073b 382 * @retval LL_DMA_CHANNEL_y
AnnaBridge 143:86740a56073b 383 */
AnnaBridge 143:86740a56073b 384 #if defined (DMA2)
AnnaBridge 143:86740a56073b 385 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
AnnaBridge 143:86740a56073b 386 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge 143:86740a56073b 387 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge 143:86740a56073b 388 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge 143:86740a56073b 389 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge 143:86740a56073b 390 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge 143:86740a56073b 391 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge 143:86740a56073b 392 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge 143:86740a56073b 393 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge 143:86740a56073b 394 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge 143:86740a56073b 395 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge 143:86740a56073b 396 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge 143:86740a56073b 397 LL_DMA_CHANNEL_7)
AnnaBridge 143:86740a56073b 398 #else
AnnaBridge 143:86740a56073b 399 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
AnnaBridge 143:86740a56073b 400 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
AnnaBridge 143:86740a56073b 401 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
AnnaBridge 143:86740a56073b 402 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
AnnaBridge 143:86740a56073b 403 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
AnnaBridge 143:86740a56073b 404 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
AnnaBridge 143:86740a56073b 405 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
AnnaBridge 143:86740a56073b 406 LL_DMA_CHANNEL_7)
AnnaBridge 143:86740a56073b 407 #endif
AnnaBridge 143:86740a56073b 408
AnnaBridge 143:86740a56073b 409 /**
AnnaBridge 143:86740a56073b 410 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
AnnaBridge 143:86740a56073b 411 * @param __DMA_INSTANCE__ DMAx
AnnaBridge 143:86740a56073b 412 * @param __CHANNEL__ LL_DMA_CHANNEL_y
AnnaBridge 143:86740a56073b 413 * @retval DMAx_Channely
AnnaBridge 143:86740a56073b 414 */
AnnaBridge 143:86740a56073b 415 #if defined (DMA2)
AnnaBridge 143:86740a56073b 416 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
AnnaBridge 143:86740a56073b 417 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
AnnaBridge 143:86740a56073b 418 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
AnnaBridge 143:86740a56073b 419 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
AnnaBridge 143:86740a56073b 420 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
AnnaBridge 143:86740a56073b 421 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
AnnaBridge 143:86740a56073b 422 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
AnnaBridge 143:86740a56073b 423 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
AnnaBridge 143:86740a56073b 424 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
AnnaBridge 143:86740a56073b 425 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
AnnaBridge 143:86740a56073b 426 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
AnnaBridge 143:86740a56073b 427 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
AnnaBridge 143:86740a56073b 428 DMA1_Channel7)
AnnaBridge 143:86740a56073b 429 #else
AnnaBridge 143:86740a56073b 430 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
AnnaBridge 143:86740a56073b 431 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
AnnaBridge 143:86740a56073b 432 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
AnnaBridge 143:86740a56073b 433 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
AnnaBridge 143:86740a56073b 434 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
AnnaBridge 143:86740a56073b 435 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
AnnaBridge 143:86740a56073b 436 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
AnnaBridge 143:86740a56073b 437 DMA1_Channel7)
AnnaBridge 143:86740a56073b 438 #endif
AnnaBridge 143:86740a56073b 439
AnnaBridge 143:86740a56073b 440 /**
AnnaBridge 143:86740a56073b 441 * @}
AnnaBridge 143:86740a56073b 442 */
AnnaBridge 143:86740a56073b 443
AnnaBridge 143:86740a56073b 444 /**
AnnaBridge 143:86740a56073b 445 * @}
AnnaBridge 143:86740a56073b 446 */
AnnaBridge 143:86740a56073b 447
AnnaBridge 143:86740a56073b 448 /* Exported functions --------------------------------------------------------*/
AnnaBridge 143:86740a56073b 449 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
AnnaBridge 143:86740a56073b 450 * @{
AnnaBridge 143:86740a56073b 451 */
AnnaBridge 143:86740a56073b 452
AnnaBridge 143:86740a56073b 453 /** @defgroup DMA_LL_EF_Configuration Configuration
AnnaBridge 143:86740a56073b 454 * @{
AnnaBridge 143:86740a56073b 455 */
AnnaBridge 143:86740a56073b 456 /**
AnnaBridge 143:86740a56073b 457 * @brief Enable DMA channel.
AnnaBridge 143:86740a56073b 458 * @rmtoll CCR EN LL_DMA_EnableChannel
AnnaBridge 143:86740a56073b 459 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 460 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 461 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 462 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 463 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 464 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 465 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 466 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 467 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 468 * @retval None
AnnaBridge 143:86740a56073b 469 */
AnnaBridge 143:86740a56073b 470 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 143:86740a56073b 471 {
AnnaBridge 143:86740a56073b 472 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
AnnaBridge 143:86740a56073b 473 }
AnnaBridge 143:86740a56073b 474
AnnaBridge 143:86740a56073b 475 /**
AnnaBridge 143:86740a56073b 476 * @brief Disable DMA channel.
AnnaBridge 143:86740a56073b 477 * @rmtoll CCR EN LL_DMA_DisableChannel
AnnaBridge 143:86740a56073b 478 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 479 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 480 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 481 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 482 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 483 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 484 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 485 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 486 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 487 * @retval None
AnnaBridge 143:86740a56073b 488 */
AnnaBridge 143:86740a56073b 489 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 143:86740a56073b 490 {
AnnaBridge 143:86740a56073b 491 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
AnnaBridge 143:86740a56073b 492 }
AnnaBridge 143:86740a56073b 493
AnnaBridge 143:86740a56073b 494 /**
AnnaBridge 143:86740a56073b 495 * @brief Check if DMA channel is enabled or disabled.
AnnaBridge 143:86740a56073b 496 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
AnnaBridge 143:86740a56073b 497 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 498 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 499 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 500 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 501 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 502 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 503 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 504 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 505 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 506 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 507 */
AnnaBridge 143:86740a56073b 508 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 143:86740a56073b 509 {
AnnaBridge 143:86740a56073b 510 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 143:86740a56073b 511 DMA_CCR_EN) == (DMA_CCR_EN));
AnnaBridge 143:86740a56073b 512 }
AnnaBridge 143:86740a56073b 513
AnnaBridge 143:86740a56073b 514 /**
AnnaBridge 143:86740a56073b 515 * @brief Configure all parameters link to DMA transfer.
AnnaBridge 143:86740a56073b 516 * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
AnnaBridge 143:86740a56073b 517 * CCR MEM2MEM LL_DMA_ConfigTransfer\n
AnnaBridge 143:86740a56073b 518 * CCR CIRC LL_DMA_ConfigTransfer\n
AnnaBridge 143:86740a56073b 519 * CCR PINC LL_DMA_ConfigTransfer\n
AnnaBridge 143:86740a56073b 520 * CCR MINC LL_DMA_ConfigTransfer\n
AnnaBridge 143:86740a56073b 521 * CCR PSIZE LL_DMA_ConfigTransfer\n
AnnaBridge 143:86740a56073b 522 * CCR MSIZE LL_DMA_ConfigTransfer\n
AnnaBridge 143:86740a56073b 523 * CCR PL LL_DMA_ConfigTransfer
AnnaBridge 143:86740a56073b 524 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 525 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 526 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 527 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 528 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 529 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 530 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 531 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 532 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 533 * @param Configuration This parameter must be a combination of all the following values:
AnnaBridge 143:86740a56073b 534 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge 143:86740a56073b 535 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
AnnaBridge 143:86740a56073b 536 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge 143:86740a56073b 537 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge 143:86740a56073b 538 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge 143:86740a56073b 539 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge 143:86740a56073b 540 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge 143:86740a56073b 541 * @retval None
AnnaBridge 143:86740a56073b 542 */
AnnaBridge 143:86740a56073b 543 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
AnnaBridge 143:86740a56073b 544 {
AnnaBridge 143:86740a56073b 545 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 143:86740a56073b 546 DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
AnnaBridge 143:86740a56073b 547 Configuration);
AnnaBridge 143:86740a56073b 548 }
AnnaBridge 143:86740a56073b 549
AnnaBridge 143:86740a56073b 550 /**
AnnaBridge 143:86740a56073b 551 * @brief Set Data transfer direction (read from peripheral or from memory).
AnnaBridge 143:86740a56073b 552 * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
AnnaBridge 143:86740a56073b 553 * CCR MEM2MEM LL_DMA_SetDataTransferDirection
AnnaBridge 143:86740a56073b 554 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 555 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 556 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 557 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 558 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 559 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 560 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 561 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 562 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 563 * @param Direction This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 564 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge 143:86740a56073b 565 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge 143:86740a56073b 566 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge 143:86740a56073b 567 * @retval None
AnnaBridge 143:86740a56073b 568 */
AnnaBridge 143:86740a56073b 569 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
AnnaBridge 143:86740a56073b 570 {
AnnaBridge 143:86740a56073b 571 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 143:86740a56073b 572 DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
AnnaBridge 143:86740a56073b 573 }
AnnaBridge 143:86740a56073b 574
AnnaBridge 143:86740a56073b 575 /**
AnnaBridge 143:86740a56073b 576 * @brief Get Data transfer direction (read from peripheral or from memory).
AnnaBridge 143:86740a56073b 577 * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
AnnaBridge 143:86740a56073b 578 * CCR MEM2MEM LL_DMA_GetDataTransferDirection
AnnaBridge 143:86740a56073b 579 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 580 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 581 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 582 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 583 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 584 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 585 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 586 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 587 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 588 * @retval Returned value can be one of the following values:
AnnaBridge 143:86740a56073b 589 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge 143:86740a56073b 590 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge 143:86740a56073b 591 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge 143:86740a56073b 592 */
AnnaBridge 143:86740a56073b 593 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 143:86740a56073b 594 {
AnnaBridge 143:86740a56073b 595 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 143:86740a56073b 596 DMA_CCR_DIR | DMA_CCR_MEM2MEM));
AnnaBridge 143:86740a56073b 597 }
AnnaBridge 143:86740a56073b 598
AnnaBridge 143:86740a56073b 599 /**
AnnaBridge 143:86740a56073b 600 * @brief Set DMA mode circular or normal.
AnnaBridge 143:86740a56073b 601 * @note The circular buffer mode cannot be used if the memory-to-memory
AnnaBridge 143:86740a56073b 602 * data transfer is configured on the selected Channel.
AnnaBridge 143:86740a56073b 603 * @rmtoll CCR CIRC LL_DMA_SetMode
AnnaBridge 143:86740a56073b 604 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 605 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 606 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 607 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 608 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 609 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 610 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 611 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 612 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 613 * @param Mode This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 614 * @arg @ref LL_DMA_MODE_NORMAL
AnnaBridge 143:86740a56073b 615 * @arg @ref LL_DMA_MODE_CIRCULAR
AnnaBridge 143:86740a56073b 616 * @retval None
AnnaBridge 143:86740a56073b 617 */
AnnaBridge 143:86740a56073b 618 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
AnnaBridge 143:86740a56073b 619 {
AnnaBridge 143:86740a56073b 620 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
AnnaBridge 143:86740a56073b 621 Mode);
AnnaBridge 143:86740a56073b 622 }
AnnaBridge 143:86740a56073b 623
AnnaBridge 143:86740a56073b 624 /**
AnnaBridge 143:86740a56073b 625 * @brief Get DMA mode circular or normal.
AnnaBridge 143:86740a56073b 626 * @rmtoll CCR CIRC LL_DMA_GetMode
AnnaBridge 143:86740a56073b 627 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 628 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 629 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 630 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 631 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 632 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 633 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 634 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 635 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 636 * @retval Returned value can be one of the following values:
AnnaBridge 143:86740a56073b 637 * @arg @ref LL_DMA_MODE_NORMAL
AnnaBridge 143:86740a56073b 638 * @arg @ref LL_DMA_MODE_CIRCULAR
AnnaBridge 143:86740a56073b 639 */
AnnaBridge 143:86740a56073b 640 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 143:86740a56073b 641 {
AnnaBridge 143:86740a56073b 642 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 143:86740a56073b 643 DMA_CCR_CIRC));
AnnaBridge 143:86740a56073b 644 }
AnnaBridge 143:86740a56073b 645
AnnaBridge 143:86740a56073b 646 /**
AnnaBridge 143:86740a56073b 647 * @brief Set Peripheral increment mode.
AnnaBridge 143:86740a56073b 648 * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
AnnaBridge 143:86740a56073b 649 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 650 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 651 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 652 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 653 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 654 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 655 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 656 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 657 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 658 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 659 * @arg @ref LL_DMA_PERIPH_INCREMENT
AnnaBridge 143:86740a56073b 660 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge 143:86740a56073b 661 * @retval None
AnnaBridge 143:86740a56073b 662 */
AnnaBridge 143:86740a56073b 663 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
AnnaBridge 143:86740a56073b 664 {
AnnaBridge 143:86740a56073b 665 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
AnnaBridge 143:86740a56073b 666 PeriphOrM2MSrcIncMode);
AnnaBridge 143:86740a56073b 667 }
AnnaBridge 143:86740a56073b 668
AnnaBridge 143:86740a56073b 669 /**
AnnaBridge 143:86740a56073b 670 * @brief Get Peripheral increment mode.
AnnaBridge 143:86740a56073b 671 * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
AnnaBridge 143:86740a56073b 672 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 673 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 674 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 675 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 676 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 677 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 678 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 679 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 680 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 681 * @retval Returned value can be one of the following values:
AnnaBridge 143:86740a56073b 682 * @arg @ref LL_DMA_PERIPH_INCREMENT
AnnaBridge 143:86740a56073b 683 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
AnnaBridge 143:86740a56073b 684 */
AnnaBridge 143:86740a56073b 685 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 143:86740a56073b 686 {
AnnaBridge 143:86740a56073b 687 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 143:86740a56073b 688 DMA_CCR_PINC));
AnnaBridge 143:86740a56073b 689 }
AnnaBridge 143:86740a56073b 690
AnnaBridge 143:86740a56073b 691 /**
AnnaBridge 143:86740a56073b 692 * @brief Set Memory increment mode.
AnnaBridge 143:86740a56073b 693 * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
AnnaBridge 143:86740a56073b 694 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 695 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 696 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 697 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 698 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 699 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 700 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 701 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 702 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 703 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 704 * @arg @ref LL_DMA_MEMORY_INCREMENT
AnnaBridge 143:86740a56073b 705 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge 143:86740a56073b 706 * @retval None
AnnaBridge 143:86740a56073b 707 */
AnnaBridge 143:86740a56073b 708 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
AnnaBridge 143:86740a56073b 709 {
AnnaBridge 143:86740a56073b 710 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
AnnaBridge 143:86740a56073b 711 MemoryOrM2MDstIncMode);
AnnaBridge 143:86740a56073b 712 }
AnnaBridge 143:86740a56073b 713
AnnaBridge 143:86740a56073b 714 /**
AnnaBridge 143:86740a56073b 715 * @brief Get Memory increment mode.
AnnaBridge 143:86740a56073b 716 * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
AnnaBridge 143:86740a56073b 717 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 718 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 719 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 720 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 721 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 722 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 723 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 724 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 725 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 726 * @retval Returned value can be one of the following values:
AnnaBridge 143:86740a56073b 727 * @arg @ref LL_DMA_MEMORY_INCREMENT
AnnaBridge 143:86740a56073b 728 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
AnnaBridge 143:86740a56073b 729 */
AnnaBridge 143:86740a56073b 730 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 143:86740a56073b 731 {
AnnaBridge 143:86740a56073b 732 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 143:86740a56073b 733 DMA_CCR_MINC));
AnnaBridge 143:86740a56073b 734 }
AnnaBridge 143:86740a56073b 735
AnnaBridge 143:86740a56073b 736 /**
AnnaBridge 143:86740a56073b 737 * @brief Set Peripheral size.
AnnaBridge 143:86740a56073b 738 * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
AnnaBridge 143:86740a56073b 739 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 740 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 741 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 742 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 743 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 744 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 745 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 746 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 747 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 748 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 749 * @arg @ref LL_DMA_PDATAALIGN_BYTE
AnnaBridge 143:86740a56073b 750 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
AnnaBridge 143:86740a56073b 751 * @arg @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge 143:86740a56073b 752 * @retval None
AnnaBridge 143:86740a56073b 753 */
AnnaBridge 143:86740a56073b 754 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
AnnaBridge 143:86740a56073b 755 {
AnnaBridge 143:86740a56073b 756 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
AnnaBridge 143:86740a56073b 757 PeriphOrM2MSrcDataSize);
AnnaBridge 143:86740a56073b 758 }
AnnaBridge 143:86740a56073b 759
AnnaBridge 143:86740a56073b 760 /**
AnnaBridge 143:86740a56073b 761 * @brief Get Peripheral size.
AnnaBridge 143:86740a56073b 762 * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
AnnaBridge 143:86740a56073b 763 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 764 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 765 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 766 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 767 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 768 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 769 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 770 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 771 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 772 * @retval Returned value can be one of the following values:
AnnaBridge 143:86740a56073b 773 * @arg @ref LL_DMA_PDATAALIGN_BYTE
AnnaBridge 143:86740a56073b 774 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
AnnaBridge 143:86740a56073b 775 * @arg @ref LL_DMA_PDATAALIGN_WORD
AnnaBridge 143:86740a56073b 776 */
AnnaBridge 143:86740a56073b 777 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 143:86740a56073b 778 {
AnnaBridge 143:86740a56073b 779 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 143:86740a56073b 780 DMA_CCR_PSIZE));
AnnaBridge 143:86740a56073b 781 }
AnnaBridge 143:86740a56073b 782
AnnaBridge 143:86740a56073b 783 /**
AnnaBridge 143:86740a56073b 784 * @brief Set Memory size.
AnnaBridge 143:86740a56073b 785 * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
AnnaBridge 143:86740a56073b 786 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 787 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 788 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 789 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 790 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 791 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 792 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 793 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 794 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 795 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 796 * @arg @ref LL_DMA_MDATAALIGN_BYTE
AnnaBridge 143:86740a56073b 797 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
AnnaBridge 143:86740a56073b 798 * @arg @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge 143:86740a56073b 799 * @retval None
AnnaBridge 143:86740a56073b 800 */
AnnaBridge 143:86740a56073b 801 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
AnnaBridge 143:86740a56073b 802 {
AnnaBridge 143:86740a56073b 803 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
AnnaBridge 143:86740a56073b 804 MemoryOrM2MDstDataSize);
AnnaBridge 143:86740a56073b 805 }
AnnaBridge 143:86740a56073b 806
AnnaBridge 143:86740a56073b 807 /**
AnnaBridge 143:86740a56073b 808 * @brief Get Memory size.
AnnaBridge 143:86740a56073b 809 * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
AnnaBridge 143:86740a56073b 810 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 811 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 812 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 813 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 814 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 815 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 816 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 817 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 818 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 819 * @retval Returned value can be one of the following values:
AnnaBridge 143:86740a56073b 820 * @arg @ref LL_DMA_MDATAALIGN_BYTE
AnnaBridge 143:86740a56073b 821 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
AnnaBridge 143:86740a56073b 822 * @arg @ref LL_DMA_MDATAALIGN_WORD
AnnaBridge 143:86740a56073b 823 */
AnnaBridge 143:86740a56073b 824 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 143:86740a56073b 825 {
AnnaBridge 143:86740a56073b 826 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 143:86740a56073b 827 DMA_CCR_MSIZE));
AnnaBridge 143:86740a56073b 828 }
AnnaBridge 143:86740a56073b 829
AnnaBridge 143:86740a56073b 830 /**
AnnaBridge 143:86740a56073b 831 * @brief Set Channel priority level.
AnnaBridge 143:86740a56073b 832 * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
AnnaBridge 143:86740a56073b 833 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 834 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 835 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 836 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 837 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 838 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 839 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 840 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 841 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 842 * @param Priority This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 843 * @arg @ref LL_DMA_PRIORITY_LOW
AnnaBridge 143:86740a56073b 844 * @arg @ref LL_DMA_PRIORITY_MEDIUM
AnnaBridge 143:86740a56073b 845 * @arg @ref LL_DMA_PRIORITY_HIGH
AnnaBridge 143:86740a56073b 846 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge 143:86740a56073b 847 * @retval None
AnnaBridge 143:86740a56073b 848 */
AnnaBridge 143:86740a56073b 849 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
AnnaBridge 143:86740a56073b 850 {
AnnaBridge 143:86740a56073b 851 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
AnnaBridge 143:86740a56073b 852 Priority);
AnnaBridge 143:86740a56073b 853 }
AnnaBridge 143:86740a56073b 854
AnnaBridge 143:86740a56073b 855 /**
AnnaBridge 143:86740a56073b 856 * @brief Get Channel priority level.
AnnaBridge 143:86740a56073b 857 * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
AnnaBridge 143:86740a56073b 858 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 859 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 860 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 861 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 862 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 863 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 864 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 865 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 866 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 867 * @retval Returned value can be one of the following values:
AnnaBridge 143:86740a56073b 868 * @arg @ref LL_DMA_PRIORITY_LOW
AnnaBridge 143:86740a56073b 869 * @arg @ref LL_DMA_PRIORITY_MEDIUM
AnnaBridge 143:86740a56073b 870 * @arg @ref LL_DMA_PRIORITY_HIGH
AnnaBridge 143:86740a56073b 871 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
AnnaBridge 143:86740a56073b 872 */
AnnaBridge 143:86740a56073b 873 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 143:86740a56073b 874 {
AnnaBridge 143:86740a56073b 875 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 143:86740a56073b 876 DMA_CCR_PL));
AnnaBridge 143:86740a56073b 877 }
AnnaBridge 143:86740a56073b 878
AnnaBridge 143:86740a56073b 879 /**
AnnaBridge 143:86740a56073b 880 * @brief Set Number of data to transfer.
AnnaBridge 143:86740a56073b 881 * @note This action has no effect if
AnnaBridge 143:86740a56073b 882 * channel is enabled.
AnnaBridge 143:86740a56073b 883 * @rmtoll CNDTR NDT LL_DMA_SetDataLength
AnnaBridge 143:86740a56073b 884 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 885 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 886 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 887 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 888 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 889 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 890 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 891 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 892 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 893 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
AnnaBridge 143:86740a56073b 894 * @retval None
AnnaBridge 143:86740a56073b 895 */
AnnaBridge 143:86740a56073b 896 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
AnnaBridge 143:86740a56073b 897 {
AnnaBridge 143:86740a56073b 898 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
AnnaBridge 143:86740a56073b 899 DMA_CNDTR_NDT, NbData);
AnnaBridge 143:86740a56073b 900 }
AnnaBridge 143:86740a56073b 901
AnnaBridge 143:86740a56073b 902 /**
AnnaBridge 143:86740a56073b 903 * @brief Get Number of data to transfer.
AnnaBridge 143:86740a56073b 904 * @note Once the channel is enabled, the return value indicate the
AnnaBridge 143:86740a56073b 905 * remaining bytes to be transmitted.
AnnaBridge 143:86740a56073b 906 * @rmtoll CNDTR NDT LL_DMA_GetDataLength
AnnaBridge 143:86740a56073b 907 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 908 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 909 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 910 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 911 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 912 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 913 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 914 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 915 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 916 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 143:86740a56073b 917 */
AnnaBridge 143:86740a56073b 918 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 143:86740a56073b 919 {
AnnaBridge 143:86740a56073b 920 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
AnnaBridge 143:86740a56073b 921 DMA_CNDTR_NDT));
AnnaBridge 143:86740a56073b 922 }
AnnaBridge 143:86740a56073b 923
AnnaBridge 143:86740a56073b 924 /**
AnnaBridge 143:86740a56073b 925 * @brief Configure the Source and Destination addresses.
AnnaBridge 143:86740a56073b 926 * @note This API must not be called when the DMA channel is enabled.
AnnaBridge 143:86740a56073b 927 * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
AnnaBridge 143:86740a56073b 928 * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
AnnaBridge 143:86740a56073b 929 * CMAR MA LL_DMA_ConfigAddresses
AnnaBridge 143:86740a56073b 930 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 931 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 932 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 933 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 934 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 935 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 936 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 937 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 938 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 939 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 143:86740a56073b 940 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 143:86740a56073b 941 * @param Direction This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 942 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
AnnaBridge 143:86740a56073b 943 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
AnnaBridge 143:86740a56073b 944 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
AnnaBridge 143:86740a56073b 945 * @retval None
AnnaBridge 143:86740a56073b 946 */
AnnaBridge 143:86740a56073b 947 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
AnnaBridge 143:86740a56073b 948 uint32_t DstAddress, uint32_t Direction)
AnnaBridge 143:86740a56073b 949 {
AnnaBridge 143:86740a56073b 950 /* Direction Memory to Periph */
AnnaBridge 143:86740a56073b 951 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
AnnaBridge 143:86740a56073b 952 {
AnnaBridge 143:86740a56073b 953 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
AnnaBridge 143:86740a56073b 954 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
AnnaBridge 143:86740a56073b 955 }
AnnaBridge 143:86740a56073b 956 /* Direction Periph to Memory and Memory to Memory */
AnnaBridge 143:86740a56073b 957 else
AnnaBridge 143:86740a56073b 958 {
AnnaBridge 143:86740a56073b 959 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
AnnaBridge 143:86740a56073b 960 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
AnnaBridge 143:86740a56073b 961 }
AnnaBridge 143:86740a56073b 962 }
AnnaBridge 143:86740a56073b 963
AnnaBridge 143:86740a56073b 964 /**
AnnaBridge 143:86740a56073b 965 * @brief Set the Memory address.
AnnaBridge 143:86740a56073b 966 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge 143:86740a56073b 967 * @note This API must not be called when the DMA channel is enabled.
AnnaBridge 143:86740a56073b 968 * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
AnnaBridge 143:86740a56073b 969 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 970 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 971 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 972 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 973 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 974 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 975 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 976 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 977 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 978 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 143:86740a56073b 979 * @retval None
AnnaBridge 143:86740a56073b 980 */
AnnaBridge 143:86740a56073b 981 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
AnnaBridge 143:86740a56073b 982 {
AnnaBridge 143:86740a56073b 983 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
AnnaBridge 143:86740a56073b 984 }
AnnaBridge 143:86740a56073b 985
AnnaBridge 143:86740a56073b 986 /**
AnnaBridge 143:86740a56073b 987 * @brief Set the Peripheral address.
AnnaBridge 143:86740a56073b 988 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge 143:86740a56073b 989 * @note This API must not be called when the DMA channel is enabled.
AnnaBridge 143:86740a56073b 990 * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
AnnaBridge 143:86740a56073b 991 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 992 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 993 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 994 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 995 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 996 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 997 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 998 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 999 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 1000 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 143:86740a56073b 1001 * @retval None
AnnaBridge 143:86740a56073b 1002 */
AnnaBridge 143:86740a56073b 1003 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
AnnaBridge 143:86740a56073b 1004 {
AnnaBridge 143:86740a56073b 1005 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
AnnaBridge 143:86740a56073b 1006 }
AnnaBridge 143:86740a56073b 1007
AnnaBridge 143:86740a56073b 1008 /**
AnnaBridge 143:86740a56073b 1009 * @brief Get Memory address.
AnnaBridge 143:86740a56073b 1010 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge 143:86740a56073b 1011 * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
AnnaBridge 143:86740a56073b 1012 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1013 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 1014 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 1015 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 1016 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 1017 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 1018 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 1019 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 1020 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 1021 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 143:86740a56073b 1022 */
AnnaBridge 143:86740a56073b 1023 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 143:86740a56073b 1024 {
AnnaBridge 143:86740a56073b 1025 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
AnnaBridge 143:86740a56073b 1026 }
AnnaBridge 143:86740a56073b 1027
AnnaBridge 143:86740a56073b 1028 /**
AnnaBridge 143:86740a56073b 1029 * @brief Get Peripheral address.
AnnaBridge 143:86740a56073b 1030 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
AnnaBridge 143:86740a56073b 1031 * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
AnnaBridge 143:86740a56073b 1032 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1033 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 1034 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 1035 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 1036 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 1037 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 1038 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 1039 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 1040 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 1041 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 143:86740a56073b 1042 */
AnnaBridge 143:86740a56073b 1043 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 143:86740a56073b 1044 {
AnnaBridge 143:86740a56073b 1045 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
AnnaBridge 143:86740a56073b 1046 }
AnnaBridge 143:86740a56073b 1047
AnnaBridge 143:86740a56073b 1048 /**
AnnaBridge 143:86740a56073b 1049 * @brief Set the Memory to Memory Source address.
AnnaBridge 143:86740a56073b 1050 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge 143:86740a56073b 1051 * @note This API must not be called when the DMA channel is enabled.
AnnaBridge 143:86740a56073b 1052 * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
AnnaBridge 143:86740a56073b 1053 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1054 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 1055 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 1056 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 1057 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 1058 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 1059 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 1060 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 1061 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 1062 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 143:86740a56073b 1063 * @retval None
AnnaBridge 143:86740a56073b 1064 */
AnnaBridge 143:86740a56073b 1065 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
AnnaBridge 143:86740a56073b 1066 {
AnnaBridge 143:86740a56073b 1067 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
AnnaBridge 143:86740a56073b 1068 }
AnnaBridge 143:86740a56073b 1069
AnnaBridge 143:86740a56073b 1070 /**
AnnaBridge 143:86740a56073b 1071 * @brief Set the Memory to Memory Destination address.
AnnaBridge 143:86740a56073b 1072 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge 143:86740a56073b 1073 * @note This API must not be called when the DMA channel is enabled.
AnnaBridge 143:86740a56073b 1074 * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
AnnaBridge 143:86740a56073b 1075 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1076 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 1077 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 1078 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 1079 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 1080 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 1081 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 1082 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 1083 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 1084 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 143:86740a56073b 1085 * @retval None
AnnaBridge 143:86740a56073b 1086 */
AnnaBridge 143:86740a56073b 1087 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
AnnaBridge 143:86740a56073b 1088 {
AnnaBridge 143:86740a56073b 1089 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
AnnaBridge 143:86740a56073b 1090 }
AnnaBridge 143:86740a56073b 1091
AnnaBridge 143:86740a56073b 1092 /**
AnnaBridge 143:86740a56073b 1093 * @brief Get the Memory to Memory Source address.
AnnaBridge 143:86740a56073b 1094 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge 143:86740a56073b 1095 * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
AnnaBridge 143:86740a56073b 1096 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1097 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 1098 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 1099 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 1100 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 1101 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 1102 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 1103 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 1104 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 1105 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 143:86740a56073b 1106 */
AnnaBridge 143:86740a56073b 1107 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 143:86740a56073b 1108 {
AnnaBridge 143:86740a56073b 1109 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
AnnaBridge 143:86740a56073b 1110 }
AnnaBridge 143:86740a56073b 1111
AnnaBridge 143:86740a56073b 1112 /**
AnnaBridge 143:86740a56073b 1113 * @brief Get the Memory to Memory Destination address.
AnnaBridge 143:86740a56073b 1114 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
AnnaBridge 143:86740a56073b 1115 * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
AnnaBridge 143:86740a56073b 1116 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1117 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 1118 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 1119 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 1120 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 1121 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 1122 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 1123 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 1124 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 1125 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
AnnaBridge 143:86740a56073b 1126 */
AnnaBridge 143:86740a56073b 1127 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 143:86740a56073b 1128 {
AnnaBridge 143:86740a56073b 1129 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
AnnaBridge 143:86740a56073b 1130 }
AnnaBridge 143:86740a56073b 1131
AnnaBridge 143:86740a56073b 1132 /**
AnnaBridge 143:86740a56073b 1133 * @}
AnnaBridge 143:86740a56073b 1134 */
AnnaBridge 143:86740a56073b 1135
AnnaBridge 143:86740a56073b 1136 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
AnnaBridge 143:86740a56073b 1137 * @{
AnnaBridge 143:86740a56073b 1138 */
AnnaBridge 143:86740a56073b 1139
AnnaBridge 143:86740a56073b 1140 /**
AnnaBridge 143:86740a56073b 1141 * @brief Get Channel 1 global interrupt flag.
AnnaBridge 143:86740a56073b 1142 * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
AnnaBridge 143:86740a56073b 1143 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1144 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 1145 */
AnnaBridge 143:86740a56073b 1146 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1147 {
AnnaBridge 143:86740a56073b 1148 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
AnnaBridge 143:86740a56073b 1149 }
AnnaBridge 143:86740a56073b 1150
AnnaBridge 143:86740a56073b 1151 /**
AnnaBridge 143:86740a56073b 1152 * @brief Get Channel 2 global interrupt flag.
AnnaBridge 143:86740a56073b 1153 * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
AnnaBridge 143:86740a56073b 1154 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1155 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 1156 */
AnnaBridge 143:86740a56073b 1157 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1158 {
AnnaBridge 143:86740a56073b 1159 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
AnnaBridge 143:86740a56073b 1160 }
AnnaBridge 143:86740a56073b 1161
AnnaBridge 143:86740a56073b 1162 /**
AnnaBridge 143:86740a56073b 1163 * @brief Get Channel 3 global interrupt flag.
AnnaBridge 143:86740a56073b 1164 * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
AnnaBridge 143:86740a56073b 1165 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1166 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 1167 */
AnnaBridge 143:86740a56073b 1168 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1169 {
AnnaBridge 143:86740a56073b 1170 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
AnnaBridge 143:86740a56073b 1171 }
AnnaBridge 143:86740a56073b 1172
AnnaBridge 143:86740a56073b 1173 /**
AnnaBridge 143:86740a56073b 1174 * @brief Get Channel 4 global interrupt flag.
AnnaBridge 143:86740a56073b 1175 * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
AnnaBridge 143:86740a56073b 1176 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1177 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 1178 */
AnnaBridge 143:86740a56073b 1179 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1180 {
AnnaBridge 143:86740a56073b 1181 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
AnnaBridge 143:86740a56073b 1182 }
AnnaBridge 143:86740a56073b 1183
AnnaBridge 143:86740a56073b 1184 /**
AnnaBridge 143:86740a56073b 1185 * @brief Get Channel 5 global interrupt flag.
AnnaBridge 143:86740a56073b 1186 * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
AnnaBridge 143:86740a56073b 1187 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1188 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 1189 */
AnnaBridge 143:86740a56073b 1190 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1191 {
AnnaBridge 143:86740a56073b 1192 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
AnnaBridge 143:86740a56073b 1193 }
AnnaBridge 143:86740a56073b 1194
AnnaBridge 143:86740a56073b 1195 /**
AnnaBridge 143:86740a56073b 1196 * @brief Get Channel 6 global interrupt flag.
AnnaBridge 143:86740a56073b 1197 * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
AnnaBridge 143:86740a56073b 1198 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1199 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 1200 */
AnnaBridge 143:86740a56073b 1201 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1202 {
AnnaBridge 143:86740a56073b 1203 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
AnnaBridge 143:86740a56073b 1204 }
AnnaBridge 143:86740a56073b 1205
AnnaBridge 143:86740a56073b 1206 /**
AnnaBridge 143:86740a56073b 1207 * @brief Get Channel 7 global interrupt flag.
AnnaBridge 143:86740a56073b 1208 * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
AnnaBridge 143:86740a56073b 1209 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1210 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 1211 */
AnnaBridge 143:86740a56073b 1212 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1213 {
AnnaBridge 143:86740a56073b 1214 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
AnnaBridge 143:86740a56073b 1215 }
AnnaBridge 143:86740a56073b 1216
AnnaBridge 143:86740a56073b 1217 /**
AnnaBridge 143:86740a56073b 1218 * @brief Get Channel 1 transfer complete flag.
AnnaBridge 143:86740a56073b 1219 * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
AnnaBridge 143:86740a56073b 1220 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1221 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 1222 */
AnnaBridge 143:86740a56073b 1223 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1224 {
AnnaBridge 143:86740a56073b 1225 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
AnnaBridge 143:86740a56073b 1226 }
AnnaBridge 143:86740a56073b 1227
AnnaBridge 143:86740a56073b 1228 /**
AnnaBridge 143:86740a56073b 1229 * @brief Get Channel 2 transfer complete flag.
AnnaBridge 143:86740a56073b 1230 * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
AnnaBridge 143:86740a56073b 1231 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1232 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 1233 */
AnnaBridge 143:86740a56073b 1234 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1235 {
AnnaBridge 143:86740a56073b 1236 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
AnnaBridge 143:86740a56073b 1237 }
AnnaBridge 143:86740a56073b 1238
AnnaBridge 143:86740a56073b 1239 /**
AnnaBridge 143:86740a56073b 1240 * @brief Get Channel 3 transfer complete flag.
AnnaBridge 143:86740a56073b 1241 * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
AnnaBridge 143:86740a56073b 1242 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1243 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 1244 */
AnnaBridge 143:86740a56073b 1245 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1246 {
AnnaBridge 143:86740a56073b 1247 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
AnnaBridge 143:86740a56073b 1248 }
AnnaBridge 143:86740a56073b 1249
AnnaBridge 143:86740a56073b 1250 /**
AnnaBridge 143:86740a56073b 1251 * @brief Get Channel 4 transfer complete flag.
AnnaBridge 143:86740a56073b 1252 * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
AnnaBridge 143:86740a56073b 1253 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1254 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 1255 */
AnnaBridge 143:86740a56073b 1256 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1257 {
AnnaBridge 143:86740a56073b 1258 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
AnnaBridge 143:86740a56073b 1259 }
AnnaBridge 143:86740a56073b 1260
AnnaBridge 143:86740a56073b 1261 /**
AnnaBridge 143:86740a56073b 1262 * @brief Get Channel 5 transfer complete flag.
AnnaBridge 143:86740a56073b 1263 * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
AnnaBridge 143:86740a56073b 1264 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1265 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 1266 */
AnnaBridge 143:86740a56073b 1267 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1268 {
AnnaBridge 143:86740a56073b 1269 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
AnnaBridge 143:86740a56073b 1270 }
AnnaBridge 143:86740a56073b 1271
AnnaBridge 143:86740a56073b 1272 /**
AnnaBridge 143:86740a56073b 1273 * @brief Get Channel 6 transfer complete flag.
AnnaBridge 143:86740a56073b 1274 * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
AnnaBridge 143:86740a56073b 1275 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1276 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 1277 */
AnnaBridge 143:86740a56073b 1278 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1279 {
AnnaBridge 143:86740a56073b 1280 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
AnnaBridge 143:86740a56073b 1281 }
AnnaBridge 143:86740a56073b 1282
AnnaBridge 143:86740a56073b 1283 /**
AnnaBridge 143:86740a56073b 1284 * @brief Get Channel 7 transfer complete flag.
AnnaBridge 143:86740a56073b 1285 * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
AnnaBridge 143:86740a56073b 1286 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1287 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 1288 */
AnnaBridge 143:86740a56073b 1289 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1290 {
AnnaBridge 143:86740a56073b 1291 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
AnnaBridge 143:86740a56073b 1292 }
AnnaBridge 143:86740a56073b 1293
AnnaBridge 143:86740a56073b 1294 /**
AnnaBridge 143:86740a56073b 1295 * @brief Get Channel 1 half transfer flag.
AnnaBridge 143:86740a56073b 1296 * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
AnnaBridge 143:86740a56073b 1297 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1298 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 1299 */
AnnaBridge 143:86740a56073b 1300 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1301 {
AnnaBridge 143:86740a56073b 1302 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
AnnaBridge 143:86740a56073b 1303 }
AnnaBridge 143:86740a56073b 1304
AnnaBridge 143:86740a56073b 1305 /**
AnnaBridge 143:86740a56073b 1306 * @brief Get Channel 2 half transfer flag.
AnnaBridge 143:86740a56073b 1307 * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
AnnaBridge 143:86740a56073b 1308 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1309 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 1310 */
AnnaBridge 143:86740a56073b 1311 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1312 {
AnnaBridge 143:86740a56073b 1313 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
AnnaBridge 143:86740a56073b 1314 }
AnnaBridge 143:86740a56073b 1315
AnnaBridge 143:86740a56073b 1316 /**
AnnaBridge 143:86740a56073b 1317 * @brief Get Channel 3 half transfer flag.
AnnaBridge 143:86740a56073b 1318 * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
AnnaBridge 143:86740a56073b 1319 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1320 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 1321 */
AnnaBridge 143:86740a56073b 1322 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1323 {
AnnaBridge 143:86740a56073b 1324 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
AnnaBridge 143:86740a56073b 1325 }
AnnaBridge 143:86740a56073b 1326
AnnaBridge 143:86740a56073b 1327 /**
AnnaBridge 143:86740a56073b 1328 * @brief Get Channel 4 half transfer flag.
AnnaBridge 143:86740a56073b 1329 * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
AnnaBridge 143:86740a56073b 1330 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1331 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 1332 */
AnnaBridge 143:86740a56073b 1333 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1334 {
AnnaBridge 143:86740a56073b 1335 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
AnnaBridge 143:86740a56073b 1336 }
AnnaBridge 143:86740a56073b 1337
AnnaBridge 143:86740a56073b 1338 /**
AnnaBridge 143:86740a56073b 1339 * @brief Get Channel 5 half transfer flag.
AnnaBridge 143:86740a56073b 1340 * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
AnnaBridge 143:86740a56073b 1341 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1342 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 1343 */
AnnaBridge 143:86740a56073b 1344 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1345 {
AnnaBridge 143:86740a56073b 1346 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
AnnaBridge 143:86740a56073b 1347 }
AnnaBridge 143:86740a56073b 1348
AnnaBridge 143:86740a56073b 1349 /**
AnnaBridge 143:86740a56073b 1350 * @brief Get Channel 6 half transfer flag.
AnnaBridge 143:86740a56073b 1351 * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
AnnaBridge 143:86740a56073b 1352 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1353 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 1354 */
AnnaBridge 143:86740a56073b 1355 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1356 {
AnnaBridge 143:86740a56073b 1357 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
AnnaBridge 143:86740a56073b 1358 }
AnnaBridge 143:86740a56073b 1359
AnnaBridge 143:86740a56073b 1360 /**
AnnaBridge 143:86740a56073b 1361 * @brief Get Channel 7 half transfer flag.
AnnaBridge 143:86740a56073b 1362 * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
AnnaBridge 143:86740a56073b 1363 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1364 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 1365 */
AnnaBridge 143:86740a56073b 1366 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1367 {
AnnaBridge 143:86740a56073b 1368 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
AnnaBridge 143:86740a56073b 1369 }
AnnaBridge 143:86740a56073b 1370
AnnaBridge 143:86740a56073b 1371 /**
AnnaBridge 143:86740a56073b 1372 * @brief Get Channel 1 transfer error flag.
AnnaBridge 143:86740a56073b 1373 * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
AnnaBridge 143:86740a56073b 1374 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1375 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 1376 */
AnnaBridge 143:86740a56073b 1377 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1378 {
AnnaBridge 143:86740a56073b 1379 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
AnnaBridge 143:86740a56073b 1380 }
AnnaBridge 143:86740a56073b 1381
AnnaBridge 143:86740a56073b 1382 /**
AnnaBridge 143:86740a56073b 1383 * @brief Get Channel 2 transfer error flag.
AnnaBridge 143:86740a56073b 1384 * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
AnnaBridge 143:86740a56073b 1385 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1386 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 1387 */
AnnaBridge 143:86740a56073b 1388 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1389 {
AnnaBridge 143:86740a56073b 1390 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
AnnaBridge 143:86740a56073b 1391 }
AnnaBridge 143:86740a56073b 1392
AnnaBridge 143:86740a56073b 1393 /**
AnnaBridge 143:86740a56073b 1394 * @brief Get Channel 3 transfer error flag.
AnnaBridge 143:86740a56073b 1395 * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
AnnaBridge 143:86740a56073b 1396 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1397 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 1398 */
AnnaBridge 143:86740a56073b 1399 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1400 {
AnnaBridge 143:86740a56073b 1401 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
AnnaBridge 143:86740a56073b 1402 }
AnnaBridge 143:86740a56073b 1403
AnnaBridge 143:86740a56073b 1404 /**
AnnaBridge 143:86740a56073b 1405 * @brief Get Channel 4 transfer error flag.
AnnaBridge 143:86740a56073b 1406 * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
AnnaBridge 143:86740a56073b 1407 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1408 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 1409 */
AnnaBridge 143:86740a56073b 1410 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1411 {
AnnaBridge 143:86740a56073b 1412 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
AnnaBridge 143:86740a56073b 1413 }
AnnaBridge 143:86740a56073b 1414
AnnaBridge 143:86740a56073b 1415 /**
AnnaBridge 143:86740a56073b 1416 * @brief Get Channel 5 transfer error flag.
AnnaBridge 143:86740a56073b 1417 * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
AnnaBridge 143:86740a56073b 1418 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1419 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 1420 */
AnnaBridge 143:86740a56073b 1421 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1422 {
AnnaBridge 143:86740a56073b 1423 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
AnnaBridge 143:86740a56073b 1424 }
AnnaBridge 143:86740a56073b 1425
AnnaBridge 143:86740a56073b 1426 /**
AnnaBridge 143:86740a56073b 1427 * @brief Get Channel 6 transfer error flag.
AnnaBridge 143:86740a56073b 1428 * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
AnnaBridge 143:86740a56073b 1429 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1430 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 1431 */
AnnaBridge 143:86740a56073b 1432 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1433 {
AnnaBridge 143:86740a56073b 1434 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
AnnaBridge 143:86740a56073b 1435 }
AnnaBridge 143:86740a56073b 1436
AnnaBridge 143:86740a56073b 1437 /**
AnnaBridge 143:86740a56073b 1438 * @brief Get Channel 7 transfer error flag.
AnnaBridge 143:86740a56073b 1439 * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
AnnaBridge 143:86740a56073b 1440 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1441 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 1442 */
AnnaBridge 143:86740a56073b 1443 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1444 {
AnnaBridge 143:86740a56073b 1445 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
AnnaBridge 143:86740a56073b 1446 }
AnnaBridge 143:86740a56073b 1447
AnnaBridge 143:86740a56073b 1448 /**
AnnaBridge 143:86740a56073b 1449 * @brief Clear Channel 1 global interrupt flag.
AnnaBridge 143:86740a56073b 1450 * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
AnnaBridge 143:86740a56073b 1451 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1452 * @retval None
AnnaBridge 143:86740a56073b 1453 */
AnnaBridge 143:86740a56073b 1454 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1455 {
AnnaBridge 143:86740a56073b 1456 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
AnnaBridge 143:86740a56073b 1457 }
AnnaBridge 143:86740a56073b 1458
AnnaBridge 143:86740a56073b 1459 /**
AnnaBridge 143:86740a56073b 1460 * @brief Clear Channel 2 global interrupt flag.
AnnaBridge 143:86740a56073b 1461 * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
AnnaBridge 143:86740a56073b 1462 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1463 * @retval None
AnnaBridge 143:86740a56073b 1464 */
AnnaBridge 143:86740a56073b 1465 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1466 {
AnnaBridge 143:86740a56073b 1467 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
AnnaBridge 143:86740a56073b 1468 }
AnnaBridge 143:86740a56073b 1469
AnnaBridge 143:86740a56073b 1470 /**
AnnaBridge 143:86740a56073b 1471 * @brief Clear Channel 3 global interrupt flag.
AnnaBridge 143:86740a56073b 1472 * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
AnnaBridge 143:86740a56073b 1473 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1474 * @retval None
AnnaBridge 143:86740a56073b 1475 */
AnnaBridge 143:86740a56073b 1476 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1477 {
AnnaBridge 143:86740a56073b 1478 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
AnnaBridge 143:86740a56073b 1479 }
AnnaBridge 143:86740a56073b 1480
AnnaBridge 143:86740a56073b 1481 /**
AnnaBridge 143:86740a56073b 1482 * @brief Clear Channel 4 global interrupt flag.
AnnaBridge 143:86740a56073b 1483 * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
AnnaBridge 143:86740a56073b 1484 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1485 * @retval None
AnnaBridge 143:86740a56073b 1486 */
AnnaBridge 143:86740a56073b 1487 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1488 {
AnnaBridge 143:86740a56073b 1489 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
AnnaBridge 143:86740a56073b 1490 }
AnnaBridge 143:86740a56073b 1491
AnnaBridge 143:86740a56073b 1492 /**
AnnaBridge 143:86740a56073b 1493 * @brief Clear Channel 5 global interrupt flag.
AnnaBridge 143:86740a56073b 1494 * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
AnnaBridge 143:86740a56073b 1495 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1496 * @retval None
AnnaBridge 143:86740a56073b 1497 */
AnnaBridge 143:86740a56073b 1498 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1499 {
AnnaBridge 143:86740a56073b 1500 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
AnnaBridge 143:86740a56073b 1501 }
AnnaBridge 143:86740a56073b 1502
AnnaBridge 143:86740a56073b 1503 /**
AnnaBridge 143:86740a56073b 1504 * @brief Clear Channel 6 global interrupt flag.
AnnaBridge 143:86740a56073b 1505 * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
AnnaBridge 143:86740a56073b 1506 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1507 * @retval None
AnnaBridge 143:86740a56073b 1508 */
AnnaBridge 143:86740a56073b 1509 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1510 {
AnnaBridge 143:86740a56073b 1511 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
AnnaBridge 143:86740a56073b 1512 }
AnnaBridge 143:86740a56073b 1513
AnnaBridge 143:86740a56073b 1514 /**
AnnaBridge 143:86740a56073b 1515 * @brief Clear Channel 7 global interrupt flag.
AnnaBridge 143:86740a56073b 1516 * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
AnnaBridge 143:86740a56073b 1517 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1518 * @retval None
AnnaBridge 143:86740a56073b 1519 */
AnnaBridge 143:86740a56073b 1520 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1521 {
AnnaBridge 143:86740a56073b 1522 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
AnnaBridge 143:86740a56073b 1523 }
AnnaBridge 143:86740a56073b 1524
AnnaBridge 143:86740a56073b 1525 /**
AnnaBridge 143:86740a56073b 1526 * @brief Clear Channel 1 transfer complete flag.
AnnaBridge 143:86740a56073b 1527 * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
AnnaBridge 143:86740a56073b 1528 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1529 * @retval None
AnnaBridge 143:86740a56073b 1530 */
AnnaBridge 143:86740a56073b 1531 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1532 {
AnnaBridge 143:86740a56073b 1533 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
AnnaBridge 143:86740a56073b 1534 }
AnnaBridge 143:86740a56073b 1535
AnnaBridge 143:86740a56073b 1536 /**
AnnaBridge 143:86740a56073b 1537 * @brief Clear Channel 2 transfer complete flag.
AnnaBridge 143:86740a56073b 1538 * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
AnnaBridge 143:86740a56073b 1539 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1540 * @retval None
AnnaBridge 143:86740a56073b 1541 */
AnnaBridge 143:86740a56073b 1542 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1543 {
AnnaBridge 143:86740a56073b 1544 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
AnnaBridge 143:86740a56073b 1545 }
AnnaBridge 143:86740a56073b 1546
AnnaBridge 143:86740a56073b 1547 /**
AnnaBridge 143:86740a56073b 1548 * @brief Clear Channel 3 transfer complete flag.
AnnaBridge 143:86740a56073b 1549 * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
AnnaBridge 143:86740a56073b 1550 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1551 * @retval None
AnnaBridge 143:86740a56073b 1552 */
AnnaBridge 143:86740a56073b 1553 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1554 {
AnnaBridge 143:86740a56073b 1555 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
AnnaBridge 143:86740a56073b 1556 }
AnnaBridge 143:86740a56073b 1557
AnnaBridge 143:86740a56073b 1558 /**
AnnaBridge 143:86740a56073b 1559 * @brief Clear Channel 4 transfer complete flag.
AnnaBridge 143:86740a56073b 1560 * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
AnnaBridge 143:86740a56073b 1561 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1562 * @retval None
AnnaBridge 143:86740a56073b 1563 */
AnnaBridge 143:86740a56073b 1564 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1565 {
AnnaBridge 143:86740a56073b 1566 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
AnnaBridge 143:86740a56073b 1567 }
AnnaBridge 143:86740a56073b 1568
AnnaBridge 143:86740a56073b 1569 /**
AnnaBridge 143:86740a56073b 1570 * @brief Clear Channel 5 transfer complete flag.
AnnaBridge 143:86740a56073b 1571 * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
AnnaBridge 143:86740a56073b 1572 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1573 * @retval None
AnnaBridge 143:86740a56073b 1574 */
AnnaBridge 143:86740a56073b 1575 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1576 {
AnnaBridge 143:86740a56073b 1577 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
AnnaBridge 143:86740a56073b 1578 }
AnnaBridge 143:86740a56073b 1579
AnnaBridge 143:86740a56073b 1580 /**
AnnaBridge 143:86740a56073b 1581 * @brief Clear Channel 6 transfer complete flag.
AnnaBridge 143:86740a56073b 1582 * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
AnnaBridge 143:86740a56073b 1583 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1584 * @retval None
AnnaBridge 143:86740a56073b 1585 */
AnnaBridge 143:86740a56073b 1586 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1587 {
AnnaBridge 143:86740a56073b 1588 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
AnnaBridge 143:86740a56073b 1589 }
AnnaBridge 143:86740a56073b 1590
AnnaBridge 143:86740a56073b 1591 /**
AnnaBridge 143:86740a56073b 1592 * @brief Clear Channel 7 transfer complete flag.
AnnaBridge 143:86740a56073b 1593 * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
AnnaBridge 143:86740a56073b 1594 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1595 * @retval None
AnnaBridge 143:86740a56073b 1596 */
AnnaBridge 143:86740a56073b 1597 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1598 {
AnnaBridge 143:86740a56073b 1599 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
AnnaBridge 143:86740a56073b 1600 }
AnnaBridge 143:86740a56073b 1601
AnnaBridge 143:86740a56073b 1602 /**
AnnaBridge 143:86740a56073b 1603 * @brief Clear Channel 1 half transfer flag.
AnnaBridge 143:86740a56073b 1604 * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
AnnaBridge 143:86740a56073b 1605 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1606 * @retval None
AnnaBridge 143:86740a56073b 1607 */
AnnaBridge 143:86740a56073b 1608 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1609 {
AnnaBridge 143:86740a56073b 1610 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
AnnaBridge 143:86740a56073b 1611 }
AnnaBridge 143:86740a56073b 1612
AnnaBridge 143:86740a56073b 1613 /**
AnnaBridge 143:86740a56073b 1614 * @brief Clear Channel 2 half transfer flag.
AnnaBridge 143:86740a56073b 1615 * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
AnnaBridge 143:86740a56073b 1616 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1617 * @retval None
AnnaBridge 143:86740a56073b 1618 */
AnnaBridge 143:86740a56073b 1619 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1620 {
AnnaBridge 143:86740a56073b 1621 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
AnnaBridge 143:86740a56073b 1622 }
AnnaBridge 143:86740a56073b 1623
AnnaBridge 143:86740a56073b 1624 /**
AnnaBridge 143:86740a56073b 1625 * @brief Clear Channel 3 half transfer flag.
AnnaBridge 143:86740a56073b 1626 * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
AnnaBridge 143:86740a56073b 1627 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1628 * @retval None
AnnaBridge 143:86740a56073b 1629 */
AnnaBridge 143:86740a56073b 1630 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1631 {
AnnaBridge 143:86740a56073b 1632 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
AnnaBridge 143:86740a56073b 1633 }
AnnaBridge 143:86740a56073b 1634
AnnaBridge 143:86740a56073b 1635 /**
AnnaBridge 143:86740a56073b 1636 * @brief Clear Channel 4 half transfer flag.
AnnaBridge 143:86740a56073b 1637 * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
AnnaBridge 143:86740a56073b 1638 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1639 * @retval None
AnnaBridge 143:86740a56073b 1640 */
AnnaBridge 143:86740a56073b 1641 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1642 {
AnnaBridge 143:86740a56073b 1643 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
AnnaBridge 143:86740a56073b 1644 }
AnnaBridge 143:86740a56073b 1645
AnnaBridge 143:86740a56073b 1646 /**
AnnaBridge 143:86740a56073b 1647 * @brief Clear Channel 5 half transfer flag.
AnnaBridge 143:86740a56073b 1648 * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
AnnaBridge 143:86740a56073b 1649 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1650 * @retval None
AnnaBridge 143:86740a56073b 1651 */
AnnaBridge 143:86740a56073b 1652 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1653 {
AnnaBridge 143:86740a56073b 1654 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
AnnaBridge 143:86740a56073b 1655 }
AnnaBridge 143:86740a56073b 1656
AnnaBridge 143:86740a56073b 1657 /**
AnnaBridge 143:86740a56073b 1658 * @brief Clear Channel 6 half transfer flag.
AnnaBridge 143:86740a56073b 1659 * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
AnnaBridge 143:86740a56073b 1660 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1661 * @retval None
AnnaBridge 143:86740a56073b 1662 */
AnnaBridge 143:86740a56073b 1663 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1664 {
AnnaBridge 143:86740a56073b 1665 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
AnnaBridge 143:86740a56073b 1666 }
AnnaBridge 143:86740a56073b 1667
AnnaBridge 143:86740a56073b 1668 /**
AnnaBridge 143:86740a56073b 1669 * @brief Clear Channel 7 half transfer flag.
AnnaBridge 143:86740a56073b 1670 * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
AnnaBridge 143:86740a56073b 1671 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1672 * @retval None
AnnaBridge 143:86740a56073b 1673 */
AnnaBridge 143:86740a56073b 1674 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1675 {
AnnaBridge 143:86740a56073b 1676 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
AnnaBridge 143:86740a56073b 1677 }
AnnaBridge 143:86740a56073b 1678
AnnaBridge 143:86740a56073b 1679 /**
AnnaBridge 143:86740a56073b 1680 * @brief Clear Channel 1 transfer error flag.
AnnaBridge 143:86740a56073b 1681 * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
AnnaBridge 143:86740a56073b 1682 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1683 * @retval None
AnnaBridge 143:86740a56073b 1684 */
AnnaBridge 143:86740a56073b 1685 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1686 {
AnnaBridge 143:86740a56073b 1687 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
AnnaBridge 143:86740a56073b 1688 }
AnnaBridge 143:86740a56073b 1689
AnnaBridge 143:86740a56073b 1690 /**
AnnaBridge 143:86740a56073b 1691 * @brief Clear Channel 2 transfer error flag.
AnnaBridge 143:86740a56073b 1692 * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
AnnaBridge 143:86740a56073b 1693 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1694 * @retval None
AnnaBridge 143:86740a56073b 1695 */
AnnaBridge 143:86740a56073b 1696 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1697 {
AnnaBridge 143:86740a56073b 1698 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
AnnaBridge 143:86740a56073b 1699 }
AnnaBridge 143:86740a56073b 1700
AnnaBridge 143:86740a56073b 1701 /**
AnnaBridge 143:86740a56073b 1702 * @brief Clear Channel 3 transfer error flag.
AnnaBridge 143:86740a56073b 1703 * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
AnnaBridge 143:86740a56073b 1704 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1705 * @retval None
AnnaBridge 143:86740a56073b 1706 */
AnnaBridge 143:86740a56073b 1707 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1708 {
AnnaBridge 143:86740a56073b 1709 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
AnnaBridge 143:86740a56073b 1710 }
AnnaBridge 143:86740a56073b 1711
AnnaBridge 143:86740a56073b 1712 /**
AnnaBridge 143:86740a56073b 1713 * @brief Clear Channel 4 transfer error flag.
AnnaBridge 143:86740a56073b 1714 * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
AnnaBridge 143:86740a56073b 1715 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1716 * @retval None
AnnaBridge 143:86740a56073b 1717 */
AnnaBridge 143:86740a56073b 1718 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1719 {
AnnaBridge 143:86740a56073b 1720 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
AnnaBridge 143:86740a56073b 1721 }
AnnaBridge 143:86740a56073b 1722
AnnaBridge 143:86740a56073b 1723 /**
AnnaBridge 143:86740a56073b 1724 * @brief Clear Channel 5 transfer error flag.
AnnaBridge 143:86740a56073b 1725 * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
AnnaBridge 143:86740a56073b 1726 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1727 * @retval None
AnnaBridge 143:86740a56073b 1728 */
AnnaBridge 143:86740a56073b 1729 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1730 {
AnnaBridge 143:86740a56073b 1731 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
AnnaBridge 143:86740a56073b 1732 }
AnnaBridge 143:86740a56073b 1733
AnnaBridge 143:86740a56073b 1734 /**
AnnaBridge 143:86740a56073b 1735 * @brief Clear Channel 6 transfer error flag.
AnnaBridge 143:86740a56073b 1736 * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
AnnaBridge 143:86740a56073b 1737 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1738 * @retval None
AnnaBridge 143:86740a56073b 1739 */
AnnaBridge 143:86740a56073b 1740 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1741 {
AnnaBridge 143:86740a56073b 1742 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
AnnaBridge 143:86740a56073b 1743 }
AnnaBridge 143:86740a56073b 1744
AnnaBridge 143:86740a56073b 1745 /**
AnnaBridge 143:86740a56073b 1746 * @brief Clear Channel 7 transfer error flag.
AnnaBridge 143:86740a56073b 1747 * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
AnnaBridge 143:86740a56073b 1748 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1749 * @retval None
AnnaBridge 143:86740a56073b 1750 */
AnnaBridge 143:86740a56073b 1751 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
AnnaBridge 143:86740a56073b 1752 {
AnnaBridge 143:86740a56073b 1753 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
AnnaBridge 143:86740a56073b 1754 }
AnnaBridge 143:86740a56073b 1755
AnnaBridge 143:86740a56073b 1756 /**
AnnaBridge 143:86740a56073b 1757 * @}
AnnaBridge 143:86740a56073b 1758 */
AnnaBridge 143:86740a56073b 1759
AnnaBridge 143:86740a56073b 1760 /** @defgroup DMA_LL_EF_IT_Management IT_Management
AnnaBridge 143:86740a56073b 1761 * @{
AnnaBridge 143:86740a56073b 1762 */
AnnaBridge 143:86740a56073b 1763
AnnaBridge 143:86740a56073b 1764 /**
AnnaBridge 143:86740a56073b 1765 * @brief Enable Transfer complete interrupt.
AnnaBridge 143:86740a56073b 1766 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
AnnaBridge 143:86740a56073b 1767 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1768 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 1769 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 1770 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 1771 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 1772 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 1773 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 1774 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 1775 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 1776 * @retval None
AnnaBridge 143:86740a56073b 1777 */
AnnaBridge 143:86740a56073b 1778 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 143:86740a56073b 1779 {
AnnaBridge 143:86740a56073b 1780 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
AnnaBridge 143:86740a56073b 1781 }
AnnaBridge 143:86740a56073b 1782
AnnaBridge 143:86740a56073b 1783 /**
AnnaBridge 143:86740a56073b 1784 * @brief Enable Half transfer interrupt.
AnnaBridge 143:86740a56073b 1785 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
AnnaBridge 143:86740a56073b 1786 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1787 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 1788 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 1789 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 1790 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 1791 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 1792 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 1793 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 1794 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 1795 * @retval None
AnnaBridge 143:86740a56073b 1796 */
AnnaBridge 143:86740a56073b 1797 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 143:86740a56073b 1798 {
AnnaBridge 143:86740a56073b 1799 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
AnnaBridge 143:86740a56073b 1800 }
AnnaBridge 143:86740a56073b 1801
AnnaBridge 143:86740a56073b 1802 /**
AnnaBridge 143:86740a56073b 1803 * @brief Enable Transfer error interrupt.
AnnaBridge 143:86740a56073b 1804 * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
AnnaBridge 143:86740a56073b 1805 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1806 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 1807 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 1808 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 1809 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 1810 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 1811 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 1812 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 1813 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 1814 * @retval None
AnnaBridge 143:86740a56073b 1815 */
AnnaBridge 143:86740a56073b 1816 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 143:86740a56073b 1817 {
AnnaBridge 143:86740a56073b 1818 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
AnnaBridge 143:86740a56073b 1819 }
AnnaBridge 143:86740a56073b 1820
AnnaBridge 143:86740a56073b 1821 /**
AnnaBridge 143:86740a56073b 1822 * @brief Disable Transfer complete interrupt.
AnnaBridge 143:86740a56073b 1823 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
AnnaBridge 143:86740a56073b 1824 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1825 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 1826 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 1827 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 1828 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 1829 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 1830 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 1831 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 1832 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 1833 * @retval None
AnnaBridge 143:86740a56073b 1834 */
AnnaBridge 143:86740a56073b 1835 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 143:86740a56073b 1836 {
AnnaBridge 143:86740a56073b 1837 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
AnnaBridge 143:86740a56073b 1838 }
AnnaBridge 143:86740a56073b 1839
AnnaBridge 143:86740a56073b 1840 /**
AnnaBridge 143:86740a56073b 1841 * @brief Disable Half transfer interrupt.
AnnaBridge 143:86740a56073b 1842 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
AnnaBridge 143:86740a56073b 1843 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1844 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 1845 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 1846 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 1847 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 1848 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 1849 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 1850 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 1851 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 1852 * @retval None
AnnaBridge 143:86740a56073b 1853 */
AnnaBridge 143:86740a56073b 1854 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 143:86740a56073b 1855 {
AnnaBridge 143:86740a56073b 1856 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
AnnaBridge 143:86740a56073b 1857 }
AnnaBridge 143:86740a56073b 1858
AnnaBridge 143:86740a56073b 1859 /**
AnnaBridge 143:86740a56073b 1860 * @brief Disable Transfer error interrupt.
AnnaBridge 143:86740a56073b 1861 * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
AnnaBridge 143:86740a56073b 1862 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1863 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 1864 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 1865 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 1866 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 1867 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 1868 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 1869 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 1870 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 1871 * @retval None
AnnaBridge 143:86740a56073b 1872 */
AnnaBridge 143:86740a56073b 1873 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 143:86740a56073b 1874 {
AnnaBridge 143:86740a56073b 1875 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
AnnaBridge 143:86740a56073b 1876 }
AnnaBridge 143:86740a56073b 1877
AnnaBridge 143:86740a56073b 1878 /**
AnnaBridge 143:86740a56073b 1879 * @brief Check if Transfer complete Interrupt is enabled.
AnnaBridge 143:86740a56073b 1880 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
AnnaBridge 143:86740a56073b 1881 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1882 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 1883 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 1884 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 1885 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 1886 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 1887 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 1888 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 1889 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 1890 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 1891 */
AnnaBridge 143:86740a56073b 1892 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 143:86740a56073b 1893 {
AnnaBridge 143:86740a56073b 1894 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 143:86740a56073b 1895 DMA_CCR_TCIE) == (DMA_CCR_TCIE));
AnnaBridge 143:86740a56073b 1896 }
AnnaBridge 143:86740a56073b 1897
AnnaBridge 143:86740a56073b 1898 /**
AnnaBridge 143:86740a56073b 1899 * @brief Check if Half transfer Interrupt is enabled.
AnnaBridge 143:86740a56073b 1900 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
AnnaBridge 143:86740a56073b 1901 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1902 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 1903 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 1904 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 1905 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 1906 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 1907 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 1908 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 1909 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 1910 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 1911 */
AnnaBridge 143:86740a56073b 1912 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 143:86740a56073b 1913 {
AnnaBridge 143:86740a56073b 1914 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 143:86740a56073b 1915 DMA_CCR_HTIE) == (DMA_CCR_HTIE));
AnnaBridge 143:86740a56073b 1916 }
AnnaBridge 143:86740a56073b 1917
AnnaBridge 143:86740a56073b 1918 /**
AnnaBridge 143:86740a56073b 1919 * @brief Check if Transfer error Interrupt is enabled.
AnnaBridge 143:86740a56073b 1920 * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
AnnaBridge 143:86740a56073b 1921 * @param DMAx DMAx Instance
AnnaBridge 143:86740a56073b 1922 * @param Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 1923 * @arg @ref LL_DMA_CHANNEL_1
AnnaBridge 143:86740a56073b 1924 * @arg @ref LL_DMA_CHANNEL_2
AnnaBridge 143:86740a56073b 1925 * @arg @ref LL_DMA_CHANNEL_3
AnnaBridge 143:86740a56073b 1926 * @arg @ref LL_DMA_CHANNEL_4
AnnaBridge 143:86740a56073b 1927 * @arg @ref LL_DMA_CHANNEL_5
AnnaBridge 143:86740a56073b 1928 * @arg @ref LL_DMA_CHANNEL_6
AnnaBridge 143:86740a56073b 1929 * @arg @ref LL_DMA_CHANNEL_7
AnnaBridge 143:86740a56073b 1930 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 1931 */
AnnaBridge 143:86740a56073b 1932 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
AnnaBridge 143:86740a56073b 1933 {
AnnaBridge 143:86740a56073b 1934 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
AnnaBridge 143:86740a56073b 1935 DMA_CCR_TEIE) == (DMA_CCR_TEIE));
AnnaBridge 143:86740a56073b 1936 }
AnnaBridge 143:86740a56073b 1937
AnnaBridge 143:86740a56073b 1938 /**
AnnaBridge 143:86740a56073b 1939 * @}
AnnaBridge 143:86740a56073b 1940 */
AnnaBridge 143:86740a56073b 1941
AnnaBridge 143:86740a56073b 1942 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 143:86740a56073b 1943 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
AnnaBridge 143:86740a56073b 1944 * @{
AnnaBridge 143:86740a56073b 1945 */
AnnaBridge 143:86740a56073b 1946
AnnaBridge 143:86740a56073b 1947 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
AnnaBridge 143:86740a56073b 1948 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
AnnaBridge 143:86740a56073b 1949 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
AnnaBridge 143:86740a56073b 1950
AnnaBridge 143:86740a56073b 1951 /**
AnnaBridge 143:86740a56073b 1952 * @}
AnnaBridge 143:86740a56073b 1953 */
AnnaBridge 143:86740a56073b 1954 #endif /* USE_FULL_LL_DRIVER */
AnnaBridge 143:86740a56073b 1955
AnnaBridge 143:86740a56073b 1956 /**
AnnaBridge 143:86740a56073b 1957 * @}
AnnaBridge 143:86740a56073b 1958 */
AnnaBridge 143:86740a56073b 1959
AnnaBridge 143:86740a56073b 1960 /**
AnnaBridge 143:86740a56073b 1961 * @}
AnnaBridge 143:86740a56073b 1962 */
AnnaBridge 143:86740a56073b 1963
AnnaBridge 143:86740a56073b 1964 #endif /* DMA1 || DMA2 */
AnnaBridge 143:86740a56073b 1965
AnnaBridge 143:86740a56073b 1966 /**
AnnaBridge 143:86740a56073b 1967 * @}
AnnaBridge 143:86740a56073b 1968 */
AnnaBridge 143:86740a56073b 1969
AnnaBridge 143:86740a56073b 1970 #ifdef __cplusplus
AnnaBridge 143:86740a56073b 1971 }
AnnaBridge 143:86740a56073b 1972 #endif
AnnaBridge 143:86740a56073b 1973
AnnaBridge 143:86740a56073b 1974 #endif /* __STM32F1xx_LL_DMA_H */
AnnaBridge 143:86740a56073b 1975
AnnaBridge 143:86740a56073b 1976 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/