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TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_ll_dac.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 143:86740a56073b 1 /**
AnnaBridge 143:86740a56073b 2 ******************************************************************************
AnnaBridge 143:86740a56073b 3 * @file stm32f1xx_ll_dac.h
AnnaBridge 143:86740a56073b 4 * @author MCD Application Team
AnnaBridge 143:86740a56073b 5 * @brief Header file of DAC LL module.
AnnaBridge 143:86740a56073b 6 ******************************************************************************
AnnaBridge 143:86740a56073b 7 * @attention
AnnaBridge 143:86740a56073b 8 *
AnnaBridge 143:86740a56073b 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 143:86740a56073b 10 *
AnnaBridge 143:86740a56073b 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 143:86740a56073b 12 * are permitted provided that the following conditions are met:
AnnaBridge 143:86740a56073b 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 143:86740a56073b 14 * this list of conditions and the following disclaimer.
AnnaBridge 143:86740a56073b 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 143:86740a56073b 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 143:86740a56073b 17 * and/or other materials provided with the distribution.
AnnaBridge 143:86740a56073b 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 143:86740a56073b 19 * may be used to endorse or promote products derived from this software
AnnaBridge 143:86740a56073b 20 * without specific prior written permission.
AnnaBridge 143:86740a56073b 21 *
AnnaBridge 143:86740a56073b 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 143:86740a56073b 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 143:86740a56073b 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 143:86740a56073b 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 143:86740a56073b 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 143:86740a56073b 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 143:86740a56073b 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 143:86740a56073b 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 143:86740a56073b 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 143:86740a56073b 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 143:86740a56073b 32 *
AnnaBridge 143:86740a56073b 33 ******************************************************************************
AnnaBridge 143:86740a56073b 34 */
AnnaBridge 143:86740a56073b 35
AnnaBridge 143:86740a56073b 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 143:86740a56073b 37 #ifndef __STM32F1xx_LL_DAC_H
AnnaBridge 143:86740a56073b 38 #define __STM32F1xx_LL_DAC_H
AnnaBridge 143:86740a56073b 39
AnnaBridge 143:86740a56073b 40 #ifdef __cplusplus
AnnaBridge 143:86740a56073b 41 extern "C" {
AnnaBridge 143:86740a56073b 42 #endif
AnnaBridge 143:86740a56073b 43
AnnaBridge 143:86740a56073b 44 /* Includes ------------------------------------------------------------------*/
AnnaBridge 143:86740a56073b 45 #include "stm32f1xx.h"
AnnaBridge 143:86740a56073b 46
AnnaBridge 143:86740a56073b 47 /** @addtogroup STM32F1xx_LL_Driver
AnnaBridge 143:86740a56073b 48 * @{
AnnaBridge 143:86740a56073b 49 */
AnnaBridge 143:86740a56073b 50
AnnaBridge 143:86740a56073b 51 #if defined (DAC)
AnnaBridge 143:86740a56073b 52
AnnaBridge 143:86740a56073b 53 /** @defgroup DAC_LL DAC
AnnaBridge 143:86740a56073b 54 * @{
AnnaBridge 143:86740a56073b 55 */
AnnaBridge 143:86740a56073b 56
AnnaBridge 143:86740a56073b 57 /* Private types -------------------------------------------------------------*/
AnnaBridge 143:86740a56073b 58 /* Private variables ---------------------------------------------------------*/
AnnaBridge 143:86740a56073b 59
AnnaBridge 143:86740a56073b 60 /* Private constants ---------------------------------------------------------*/
AnnaBridge 143:86740a56073b 61 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
AnnaBridge 143:86740a56073b 62 * @{
AnnaBridge 143:86740a56073b 63 */
AnnaBridge 143:86740a56073b 64
AnnaBridge 143:86740a56073b 65 /* Internal masks for DAC channels definition */
AnnaBridge 143:86740a56073b 66 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
AnnaBridge 143:86740a56073b 67 /* - channel bits position into register CR */
AnnaBridge 143:86740a56073b 68 /* - channel bits position into register SWTRIG */
AnnaBridge 143:86740a56073b 69 /* - channel register offset of data holding register DHRx */
AnnaBridge 143:86740a56073b 70 /* - channel register offset of data output register DORx */
AnnaBridge 143:86740a56073b 71 #define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
AnnaBridge 143:86740a56073b 72 #define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
AnnaBridge 143:86740a56073b 73 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
AnnaBridge 143:86740a56073b 74
AnnaBridge 143:86740a56073b 75 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
AnnaBridge 143:86740a56073b 76 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
AnnaBridge 143:86740a56073b 77 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
AnnaBridge 143:86740a56073b 78
AnnaBridge 143:86740a56073b 79 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
AnnaBridge 143:86740a56073b 80 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
AnnaBridge 143:86740a56073b 81 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
AnnaBridge 143:86740a56073b 82 #define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
AnnaBridge 143:86740a56073b 83 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
AnnaBridge 143:86740a56073b 84 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
AnnaBridge 143:86740a56073b 85 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
AnnaBridge 143:86740a56073b 86 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
AnnaBridge 143:86740a56073b 87 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
AnnaBridge 143:86740a56073b 88 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
AnnaBridge 143:86740a56073b 89
AnnaBridge 143:86740a56073b 90 #define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */
AnnaBridge 143:86740a56073b 91 #define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
AnnaBridge 143:86740a56073b 92 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
AnnaBridge 143:86740a56073b 93
AnnaBridge 143:86740a56073b 94 /* DAC registers bits positions */
AnnaBridge 143:86740a56073b 95 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
AnnaBridge 143:86740a56073b 96 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
AnnaBridge 143:86740a56073b 97 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
AnnaBridge 143:86740a56073b 98
AnnaBridge 143:86740a56073b 99 /* Miscellaneous data */
AnnaBridge 143:86740a56073b 100 #define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
AnnaBridge 143:86740a56073b 101
AnnaBridge 143:86740a56073b 102 /**
AnnaBridge 143:86740a56073b 103 * @}
AnnaBridge 143:86740a56073b 104 */
AnnaBridge 143:86740a56073b 105
AnnaBridge 143:86740a56073b 106
AnnaBridge 143:86740a56073b 107 /* Private macros ------------------------------------------------------------*/
AnnaBridge 143:86740a56073b 108 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
AnnaBridge 143:86740a56073b 109 * @{
AnnaBridge 143:86740a56073b 110 */
AnnaBridge 143:86740a56073b 111
AnnaBridge 143:86740a56073b 112 /**
AnnaBridge 143:86740a56073b 113 * @brief Driver macro reserved for internal use: isolate bits with the
AnnaBridge 143:86740a56073b 114 * selected mask and shift them to the register LSB
AnnaBridge 143:86740a56073b 115 * (shift mask on register position bit 0).
AnnaBridge 143:86740a56073b 116 * @param __BITS__ Bits in register 32 bits
AnnaBridge 143:86740a56073b 117 * @param __MASK__ Mask in register 32 bits
AnnaBridge 143:86740a56073b 118 * @retval Bits in register 32 bits
AnnaBridge 143:86740a56073b 119 */
AnnaBridge 143:86740a56073b 120 #define __DAC_MASK_SHIFT(__BITS__, __MASK__) \
AnnaBridge 143:86740a56073b 121 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
AnnaBridge 143:86740a56073b 122
AnnaBridge 143:86740a56073b 123 /**
AnnaBridge 143:86740a56073b 124 * @brief Driver macro reserved for internal use: set a pointer to
AnnaBridge 143:86740a56073b 125 * a register from a register basis from which an offset
AnnaBridge 143:86740a56073b 126 * is applied.
AnnaBridge 143:86740a56073b 127 * @param __REG__ Register basis from which the offset is applied.
AnnaBridge 143:86740a56073b 128 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
AnnaBridge 143:86740a56073b 129 * @retval Pointer to register address
AnnaBridge 143:86740a56073b 130 */
AnnaBridge 143:86740a56073b 131 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
AnnaBridge 143:86740a56073b 132 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
AnnaBridge 143:86740a56073b 133
AnnaBridge 143:86740a56073b 134 /**
AnnaBridge 143:86740a56073b 135 * @}
AnnaBridge 143:86740a56073b 136 */
AnnaBridge 143:86740a56073b 137
AnnaBridge 143:86740a56073b 138
AnnaBridge 143:86740a56073b 139 /* Exported types ------------------------------------------------------------*/
AnnaBridge 143:86740a56073b 140 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 143:86740a56073b 141 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
AnnaBridge 143:86740a56073b 142 * @{
AnnaBridge 143:86740a56073b 143 */
AnnaBridge 143:86740a56073b 144
AnnaBridge 143:86740a56073b 145 /**
AnnaBridge 143:86740a56073b 146 * @brief Structure definition of some features of DAC instance.
AnnaBridge 143:86740a56073b 147 */
AnnaBridge 143:86740a56073b 148 typedef struct
AnnaBridge 143:86740a56073b 149 {
AnnaBridge 143:86740a56073b 150 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
AnnaBridge 143:86740a56073b 151 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
AnnaBridge 143:86740a56073b 152
AnnaBridge 143:86740a56073b 153 This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */
AnnaBridge 143:86740a56073b 154
AnnaBridge 143:86740a56073b 155 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
AnnaBridge 143:86740a56073b 156 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
AnnaBridge 143:86740a56073b 157
AnnaBridge 143:86740a56073b 158 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
AnnaBridge 143:86740a56073b 159
AnnaBridge 143:86740a56073b 160 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
AnnaBridge 143:86740a56073b 161 If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
AnnaBridge 143:86740a56073b 162 If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
AnnaBridge 143:86740a56073b 163 @note If waveform automatic generation mode is disabled, this parameter is discarded.
AnnaBridge 143:86740a56073b 164
AnnaBridge 143:86740a56073b 165 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */
AnnaBridge 143:86740a56073b 166
AnnaBridge 143:86740a56073b 167 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
AnnaBridge 143:86740a56073b 168 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
AnnaBridge 143:86740a56073b 169
AnnaBridge 143:86740a56073b 170 This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
AnnaBridge 143:86740a56073b 171
AnnaBridge 143:86740a56073b 172 } LL_DAC_InitTypeDef;
AnnaBridge 143:86740a56073b 173
AnnaBridge 143:86740a56073b 174 /**
AnnaBridge 143:86740a56073b 175 * @}
AnnaBridge 143:86740a56073b 176 */
AnnaBridge 143:86740a56073b 177 #endif /* USE_FULL_LL_DRIVER */
AnnaBridge 143:86740a56073b 178
AnnaBridge 143:86740a56073b 179 /* Exported constants --------------------------------------------------------*/
AnnaBridge 143:86740a56073b 180 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
AnnaBridge 143:86740a56073b 181 * @{
AnnaBridge 143:86740a56073b 182 */
AnnaBridge 143:86740a56073b 183
AnnaBridge 143:86740a56073b 184 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
AnnaBridge 143:86740a56073b 185 * @brief Flags defines which can be used with LL_DAC_ReadReg function
AnnaBridge 143:86740a56073b 186 * @{
AnnaBridge 143:86740a56073b 187 */
AnnaBridge 143:86740a56073b 188 /* DAC channel 1 flags */
AnnaBridge 143:86740a56073b 189 #if defined(DAC_SR_DMAUDR1)
AnnaBridge 143:86740a56073b 190 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
AnnaBridge 143:86740a56073b 191 #endif /* DAC_SR_DMAUDR1 */
AnnaBridge 143:86740a56073b 192
AnnaBridge 143:86740a56073b 193 /* DAC channel 2 flags */
AnnaBridge 143:86740a56073b 194 #if defined(DAC_SR_DMAUDR2)
AnnaBridge 143:86740a56073b 195 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
AnnaBridge 143:86740a56073b 196 #endif /* DAC_SR_DMAUDR2 */
AnnaBridge 143:86740a56073b 197 /**
AnnaBridge 143:86740a56073b 198 * @}
AnnaBridge 143:86740a56073b 199 */
AnnaBridge 143:86740a56073b 200
AnnaBridge 143:86740a56073b 201 /** @defgroup DAC_LL_EC_IT DAC interruptions
AnnaBridge 143:86740a56073b 202 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
AnnaBridge 143:86740a56073b 203 * @{
AnnaBridge 143:86740a56073b 204 */
AnnaBridge 143:86740a56073b 205 #if defined(DAC_CR_DMAUDRIE1)
AnnaBridge 143:86740a56073b 206 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
AnnaBridge 143:86740a56073b 207 #endif /* DAC_CR_DMAUDRIE1 */
AnnaBridge 143:86740a56073b 208 #if defined(DAC_CR_DMAUDRIE2)
AnnaBridge 143:86740a56073b 209 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
AnnaBridge 143:86740a56073b 210 #endif /* DAC_CR_DMAUDRIE2 */
AnnaBridge 143:86740a56073b 211 /**
AnnaBridge 143:86740a56073b 212 * @}
AnnaBridge 143:86740a56073b 213 */
AnnaBridge 143:86740a56073b 214
AnnaBridge 143:86740a56073b 215 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
AnnaBridge 143:86740a56073b 216 * @{
AnnaBridge 143:86740a56073b 217 */
AnnaBridge 143:86740a56073b 218 #define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */
AnnaBridge 143:86740a56073b 219 #define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */
AnnaBridge 143:86740a56073b 220 /**
AnnaBridge 143:86740a56073b 221 * @}
AnnaBridge 143:86740a56073b 222 */
AnnaBridge 143:86740a56073b 223
AnnaBridge 143:86740a56073b 224 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
AnnaBridge 143:86740a56073b 225 * @{
AnnaBridge 143:86740a56073b 226 */
AnnaBridge 143:86740a56073b 227 #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
AnnaBridge 143:86740a56073b 228 #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM3 TRGO. */
AnnaBridge 143:86740a56073b 229 #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. */
AnnaBridge 143:86740a56073b 230 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
AnnaBridge 143:86740a56073b 231 #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */
AnnaBridge 143:86740a56073b 232 #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
AnnaBridge 143:86740a56073b 233 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
AnnaBridge 143:86740a56073b 234 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
AnnaBridge 143:86740a56073b 235 #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */
AnnaBridge 143:86740a56073b 236 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
AnnaBridge 143:86740a56073b 237 /**
AnnaBridge 143:86740a56073b 238 * @}
AnnaBridge 143:86740a56073b 239 */
AnnaBridge 143:86740a56073b 240
AnnaBridge 143:86740a56073b 241 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
AnnaBridge 143:86740a56073b 242 * @{
AnnaBridge 143:86740a56073b 243 */
AnnaBridge 143:86740a56073b 244 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */
AnnaBridge 143:86740a56073b 245 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
AnnaBridge 143:86740a56073b 246 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
AnnaBridge 143:86740a56073b 247 /**
AnnaBridge 143:86740a56073b 248 * @}
AnnaBridge 143:86740a56073b 249 */
AnnaBridge 143:86740a56073b 250
AnnaBridge 143:86740a56073b 251 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
AnnaBridge 143:86740a56073b 252 * @{
AnnaBridge 143:86740a56073b 253 */
AnnaBridge 143:86740a56073b 254 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
AnnaBridge 143:86740a56073b 255 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
AnnaBridge 143:86740a56073b 256 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
AnnaBridge 143:86740a56073b 257 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
AnnaBridge 143:86740a56073b 258 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
AnnaBridge 143:86740a56073b 259 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
AnnaBridge 143:86740a56073b 260 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
AnnaBridge 143:86740a56073b 261 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
AnnaBridge 143:86740a56073b 262 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
AnnaBridge 143:86740a56073b 263 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
AnnaBridge 143:86740a56073b 264 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
AnnaBridge 143:86740a56073b 265 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
AnnaBridge 143:86740a56073b 266 /**
AnnaBridge 143:86740a56073b 267 * @}
AnnaBridge 143:86740a56073b 268 */
AnnaBridge 143:86740a56073b 269
AnnaBridge 143:86740a56073b 270 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
AnnaBridge 143:86740a56073b 271 * @{
AnnaBridge 143:86740a56073b 272 */
AnnaBridge 143:86740a56073b 273 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
AnnaBridge 143:86740a56073b 274 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
AnnaBridge 143:86740a56073b 275 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
AnnaBridge 143:86740a56073b 276 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
AnnaBridge 143:86740a56073b 277 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
AnnaBridge 143:86740a56073b 278 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
AnnaBridge 143:86740a56073b 279 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
AnnaBridge 143:86740a56073b 280 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
AnnaBridge 143:86740a56073b 281 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
AnnaBridge 143:86740a56073b 282 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
AnnaBridge 143:86740a56073b 283 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
AnnaBridge 143:86740a56073b 284 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
AnnaBridge 143:86740a56073b 285 /**
AnnaBridge 143:86740a56073b 286 * @}
AnnaBridge 143:86740a56073b 287 */
AnnaBridge 143:86740a56073b 288
AnnaBridge 143:86740a56073b 289 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
AnnaBridge 143:86740a56073b 290 * @{
AnnaBridge 143:86740a56073b 291 */
AnnaBridge 143:86740a56073b 292 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
AnnaBridge 143:86740a56073b 293 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
AnnaBridge 143:86740a56073b 294 /**
AnnaBridge 143:86740a56073b 295 * @}
AnnaBridge 143:86740a56073b 296 */
AnnaBridge 143:86740a56073b 297
AnnaBridge 143:86740a56073b 298
AnnaBridge 143:86740a56073b 299 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
AnnaBridge 143:86740a56073b 300 * @{
AnnaBridge 143:86740a56073b 301 */
AnnaBridge 143:86740a56073b 302 #define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */
AnnaBridge 143:86740a56073b 303 #define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */
AnnaBridge 143:86740a56073b 304 /**
AnnaBridge 143:86740a56073b 305 * @}
AnnaBridge 143:86740a56073b 306 */
AnnaBridge 143:86740a56073b 307
AnnaBridge 143:86740a56073b 308 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
AnnaBridge 143:86740a56073b 309 * @{
AnnaBridge 143:86740a56073b 310 */
AnnaBridge 143:86740a56073b 311 /* List of DAC registers intended to be used (most commonly) with */
AnnaBridge 143:86740a56073b 312 /* DMA transfer. */
AnnaBridge 143:86740a56073b 313 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
AnnaBridge 143:86740a56073b 314 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */
AnnaBridge 143:86740a56073b 315 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */
AnnaBridge 143:86740a56073b 316 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK /*!< DAC channel data holding register 8 bits right aligned */
AnnaBridge 143:86740a56073b 317 /**
AnnaBridge 143:86740a56073b 318 * @}
AnnaBridge 143:86740a56073b 319 */
AnnaBridge 143:86740a56073b 320
AnnaBridge 143:86740a56073b 321 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
AnnaBridge 143:86740a56073b 322 * @note Only DAC IP HW delays are defined in DAC LL driver driver,
AnnaBridge 143:86740a56073b 323 * not timeout values.
AnnaBridge 143:86740a56073b 324 * For details on delays values, refer to descriptions in source code
AnnaBridge 143:86740a56073b 325 * above each literal definition.
AnnaBridge 143:86740a56073b 326 * @{
AnnaBridge 143:86740a56073b 327 */
AnnaBridge 143:86740a56073b 328
AnnaBridge 143:86740a56073b 329 /* Delay for DAC channel voltage settling time from DAC channel startup */
AnnaBridge 143:86740a56073b 330 /* (transition from disable to enable). */
AnnaBridge 143:86740a56073b 331 /* Note: DAC channel startup time depends on board application environment: */
AnnaBridge 143:86740a56073b 332 /* impedance connected to DAC channel output. */
AnnaBridge 143:86740a56073b 333 /* The delay below is specified under conditions: */
AnnaBridge 143:86740a56073b 334 /* - voltage maximum transition (lowest to highest value) */
AnnaBridge 143:86740a56073b 335 /* - until voltage reaches final value +-1LSB */
AnnaBridge 143:86740a56073b 336 /* - DAC channel output buffer enabled */
AnnaBridge 143:86740a56073b 337 /* - load impedance of 5kOhm (min), 50pF (max) */
AnnaBridge 143:86740a56073b 338 /* Literal set to maximum value (refer to device datasheet, */
AnnaBridge 143:86740a56073b 339 /* parameter "tWAKEUP"). */
AnnaBridge 143:86740a56073b 340 /* Unit: us */
AnnaBridge 143:86740a56073b 341 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
AnnaBridge 143:86740a56073b 342
AnnaBridge 143:86740a56073b 343 /* Delay for DAC channel voltage settling time. */
AnnaBridge 143:86740a56073b 344 /* Note: DAC channel startup time depends on board application environment: */
AnnaBridge 143:86740a56073b 345 /* impedance connected to DAC channel output. */
AnnaBridge 143:86740a56073b 346 /* The delay below is specified under conditions: */
AnnaBridge 143:86740a56073b 347 /* - voltage maximum transition (lowest to highest value) */
AnnaBridge 143:86740a56073b 348 /* - until voltage reaches final value +-1LSB */
AnnaBridge 143:86740a56073b 349 /* - DAC channel output buffer enabled */
AnnaBridge 143:86740a56073b 350 /* - load impedance of 5kOhm min, 50pF max */
AnnaBridge 143:86740a56073b 351 /* Literal set to maximum value (refer to device datasheet, */
AnnaBridge 143:86740a56073b 352 /* parameter "tSETTLING"). */
AnnaBridge 143:86740a56073b 353 /* Unit: us */
AnnaBridge 143:86740a56073b 354 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */
AnnaBridge 143:86740a56073b 355 /**
AnnaBridge 143:86740a56073b 356 * @}
AnnaBridge 143:86740a56073b 357 */
AnnaBridge 143:86740a56073b 358
AnnaBridge 143:86740a56073b 359 /**
AnnaBridge 143:86740a56073b 360 * @}
AnnaBridge 143:86740a56073b 361 */
AnnaBridge 143:86740a56073b 362
AnnaBridge 143:86740a56073b 363 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 143:86740a56073b 364 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
AnnaBridge 143:86740a56073b 365 * @{
AnnaBridge 143:86740a56073b 366 */
AnnaBridge 143:86740a56073b 367
AnnaBridge 143:86740a56073b 368 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
AnnaBridge 143:86740a56073b 369 * @{
AnnaBridge 143:86740a56073b 370 */
AnnaBridge 143:86740a56073b 371
AnnaBridge 143:86740a56073b 372 /**
AnnaBridge 143:86740a56073b 373 * @brief Write a value in DAC register
AnnaBridge 143:86740a56073b 374 * @param __INSTANCE__ DAC Instance
AnnaBridge 143:86740a56073b 375 * @param __REG__ Register to be written
AnnaBridge 143:86740a56073b 376 * @param __VALUE__ Value to be written in the register
AnnaBridge 143:86740a56073b 377 * @retval None
AnnaBridge 143:86740a56073b 378 */
AnnaBridge 143:86740a56073b 379 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge 143:86740a56073b 380
AnnaBridge 143:86740a56073b 381 /**
AnnaBridge 143:86740a56073b 382 * @brief Read a value in DAC register
AnnaBridge 143:86740a56073b 383 * @param __INSTANCE__ DAC Instance
AnnaBridge 143:86740a56073b 384 * @param __REG__ Register to be read
AnnaBridge 143:86740a56073b 385 * @retval Register value
AnnaBridge 143:86740a56073b 386 */
AnnaBridge 143:86740a56073b 387 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge 143:86740a56073b 388
AnnaBridge 143:86740a56073b 389 /**
AnnaBridge 143:86740a56073b 390 * @}
AnnaBridge 143:86740a56073b 391 */
AnnaBridge 143:86740a56073b 392
AnnaBridge 143:86740a56073b 393 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
AnnaBridge 143:86740a56073b 394 * @{
AnnaBridge 143:86740a56073b 395 */
AnnaBridge 143:86740a56073b 396
AnnaBridge 143:86740a56073b 397 /**
AnnaBridge 143:86740a56073b 398 * @brief Helper macro to get DAC channel number in decimal format
AnnaBridge 143:86740a56073b 399 * from literals LL_DAC_CHANNEL_x.
AnnaBridge 143:86740a56073b 400 * Example:
AnnaBridge 143:86740a56073b 401 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
AnnaBridge 143:86740a56073b 402 * will return decimal number "1".
AnnaBridge 143:86740a56073b 403 * @note The input can be a value from functions where a channel
AnnaBridge 143:86740a56073b 404 * number is returned.
AnnaBridge 143:86740a56073b 405 * @param __CHANNEL__ This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 406 * @arg @ref LL_DAC_CHANNEL_1
AnnaBridge 143:86740a56073b 407 * @arg @ref LL_DAC_CHANNEL_2
AnnaBridge 143:86740a56073b 408 * @retval 1...2
AnnaBridge 143:86740a56073b 409 */
AnnaBridge 143:86740a56073b 410 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
AnnaBridge 143:86740a56073b 411 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
AnnaBridge 143:86740a56073b 412
AnnaBridge 143:86740a56073b 413 /**
AnnaBridge 143:86740a56073b 414 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
AnnaBridge 143:86740a56073b 415 * from number in decimal format.
AnnaBridge 143:86740a56073b 416 * Example:
AnnaBridge 143:86740a56073b 417 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
AnnaBridge 143:86740a56073b 418 * will return a data equivalent to "LL_DAC_CHANNEL_1".
AnnaBridge 143:86740a56073b 419 * @note If the input parameter does not correspond to a DAC channel,
AnnaBridge 143:86740a56073b 420 * this macro returns value '0'.
AnnaBridge 143:86740a56073b 421 * @param __DECIMAL_NB__ 1...2
AnnaBridge 143:86740a56073b 422 * @retval Returned value can be one of the following values:
AnnaBridge 143:86740a56073b 423 * @arg @ref LL_DAC_CHANNEL_1
AnnaBridge 143:86740a56073b 424 * @arg @ref LL_DAC_CHANNEL_2
AnnaBridge 143:86740a56073b 425 */
AnnaBridge 143:86740a56073b 426 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
AnnaBridge 143:86740a56073b 427 (((__DECIMAL_NB__) == 1U) \
AnnaBridge 143:86740a56073b 428 ? ( \
AnnaBridge 143:86740a56073b 429 LL_DAC_CHANNEL_1 \
AnnaBridge 143:86740a56073b 430 ) \
AnnaBridge 143:86740a56073b 431 : \
AnnaBridge 143:86740a56073b 432 (((__DECIMAL_NB__) == 2U) \
AnnaBridge 143:86740a56073b 433 ? ( \
AnnaBridge 143:86740a56073b 434 LL_DAC_CHANNEL_2 \
AnnaBridge 143:86740a56073b 435 ) \
AnnaBridge 143:86740a56073b 436 : \
AnnaBridge 143:86740a56073b 437 ( \
AnnaBridge 143:86740a56073b 438 0 \
AnnaBridge 143:86740a56073b 439 ) \
AnnaBridge 143:86740a56073b 440 ) \
AnnaBridge 143:86740a56073b 441 )
AnnaBridge 143:86740a56073b 442
AnnaBridge 143:86740a56073b 443 /**
AnnaBridge 143:86740a56073b 444 * @brief Helper macro to define the DAC conversion data full-scale digital
AnnaBridge 143:86740a56073b 445 * value corresponding to the selected DAC resolution.
AnnaBridge 143:86740a56073b 446 * @note DAC conversion data full-scale corresponds to voltage range
AnnaBridge 143:86740a56073b 447 * determined by analog voltage references Vref+ and Vref-
AnnaBridge 143:86740a56073b 448 * (refer to reference manual).
AnnaBridge 143:86740a56073b 449 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 450 * @arg @ref LL_DAC_RESOLUTION_12B
AnnaBridge 143:86740a56073b 451 * @arg @ref LL_DAC_RESOLUTION_8B
AnnaBridge 143:86740a56073b 452 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
AnnaBridge 143:86740a56073b 453 */
AnnaBridge 143:86740a56073b 454 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
AnnaBridge 143:86740a56073b 455 ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
AnnaBridge 143:86740a56073b 456
AnnaBridge 143:86740a56073b 457 /**
AnnaBridge 143:86740a56073b 458 * @brief Helper macro to calculate the DAC conversion data (unit: digital
AnnaBridge 143:86740a56073b 459 * value) corresponding to a voltage (unit: mVolt).
AnnaBridge 143:86740a56073b 460 * @note This helper macro is intended to provide input data in voltage
AnnaBridge 143:86740a56073b 461 * rather than digital value,
AnnaBridge 143:86740a56073b 462 * to be used with LL DAC functions such as
AnnaBridge 143:86740a56073b 463 * @ref LL_DAC_ConvertData12RightAligned().
AnnaBridge 143:86740a56073b 464 * @note Analog reference voltage (Vref+) must be either known from
AnnaBridge 143:86740a56073b 465 * user board environment or can be calculated using ADC measurement
AnnaBridge 143:86740a56073b 466 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
AnnaBridge 143:86740a56073b 467 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
AnnaBridge 143:86740a56073b 468 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
AnnaBridge 143:86740a56073b 469 * (unit: mVolt).
AnnaBridge 143:86740a56073b 470 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 471 * @arg @ref LL_DAC_RESOLUTION_12B
AnnaBridge 143:86740a56073b 472 * @arg @ref LL_DAC_RESOLUTION_8B
AnnaBridge 143:86740a56073b 473 * @retval DAC conversion data (unit: digital value)
AnnaBridge 143:86740a56073b 474 */
AnnaBridge 143:86740a56073b 475 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
AnnaBridge 143:86740a56073b 476 __DAC_VOLTAGE__,\
AnnaBridge 143:86740a56073b 477 __DAC_RESOLUTION__) \
AnnaBridge 143:86740a56073b 478 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
AnnaBridge 143:86740a56073b 479 / (__VREFANALOG_VOLTAGE__) \
AnnaBridge 143:86740a56073b 480 )
AnnaBridge 143:86740a56073b 481
AnnaBridge 143:86740a56073b 482 /**
AnnaBridge 143:86740a56073b 483 * @}
AnnaBridge 143:86740a56073b 484 */
AnnaBridge 143:86740a56073b 485
AnnaBridge 143:86740a56073b 486 /**
AnnaBridge 143:86740a56073b 487 * @}
AnnaBridge 143:86740a56073b 488 */
AnnaBridge 143:86740a56073b 489
AnnaBridge 143:86740a56073b 490
AnnaBridge 143:86740a56073b 491 /* Exported functions --------------------------------------------------------*/
AnnaBridge 143:86740a56073b 492 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
AnnaBridge 143:86740a56073b 493 * @{
AnnaBridge 143:86740a56073b 494 */
AnnaBridge 143:86740a56073b 495 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
AnnaBridge 143:86740a56073b 496 * @{
AnnaBridge 143:86740a56073b 497 */
AnnaBridge 143:86740a56073b 498
AnnaBridge 143:86740a56073b 499 /**
AnnaBridge 143:86740a56073b 500 * @brief Set the conversion trigger source for the selected DAC channel.
AnnaBridge 143:86740a56073b 501 * @note For conversion trigger source to be effective, DAC trigger
AnnaBridge 143:86740a56073b 502 * must be enabled using function @ref LL_DAC_EnableTrigger().
AnnaBridge 143:86740a56073b 503 * @note To set conversion trigger source, DAC channel must be disabled.
AnnaBridge 143:86740a56073b 504 * Otherwise, the setting is discarded.
AnnaBridge 143:86740a56073b 505 * @note Availability of parameters of trigger sources from timer
AnnaBridge 143:86740a56073b 506 * depends on timers availability on the selected device.
AnnaBridge 143:86740a56073b 507 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
AnnaBridge 143:86740a56073b 508 * CR TSEL2 LL_DAC_SetTriggerSource
AnnaBridge 143:86740a56073b 509 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 510 * @param DAC_Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 511 * @arg @ref LL_DAC_CHANNEL_1
AnnaBridge 143:86740a56073b 512 * @arg @ref LL_DAC_CHANNEL_2
AnnaBridge 143:86740a56073b 513 * @param TriggerSource This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 514 * @arg @ref LL_DAC_TRIG_SOFTWARE
AnnaBridge 143:86740a56073b 515 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
AnnaBridge 143:86740a56073b 516 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
AnnaBridge 143:86740a56073b 517 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
AnnaBridge 143:86740a56073b 518 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
AnnaBridge 143:86740a56073b 519 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
AnnaBridge 143:86740a56073b 520 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
AnnaBridge 143:86740a56073b 521 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
AnnaBridge 143:86740a56073b 522 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
AnnaBridge 143:86740a56073b 523 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
AnnaBridge 143:86740a56073b 524 * @retval None
AnnaBridge 143:86740a56073b 525 */
AnnaBridge 143:86740a56073b 526 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
AnnaBridge 143:86740a56073b 527 {
AnnaBridge 143:86740a56073b 528 MODIFY_REG(DACx->CR,
AnnaBridge 143:86740a56073b 529 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge 143:86740a56073b 530 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge 143:86740a56073b 531 }
AnnaBridge 143:86740a56073b 532
AnnaBridge 143:86740a56073b 533 /**
AnnaBridge 143:86740a56073b 534 * @brief Get the conversion trigger source for the selected DAC channel.
AnnaBridge 143:86740a56073b 535 * @note For conversion trigger source to be effective, DAC trigger
AnnaBridge 143:86740a56073b 536 * must be enabled using function @ref LL_DAC_EnableTrigger().
AnnaBridge 143:86740a56073b 537 * @note Availability of parameters of trigger sources from timer
AnnaBridge 143:86740a56073b 538 * depends on timers availability on the selected device.
AnnaBridge 143:86740a56073b 539 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
AnnaBridge 143:86740a56073b 540 * CR TSEL2 LL_DAC_GetTriggerSource
AnnaBridge 143:86740a56073b 541 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 542 * @param DAC_Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 543 * @arg @ref LL_DAC_CHANNEL_1
AnnaBridge 143:86740a56073b 544 * @arg @ref LL_DAC_CHANNEL_2
AnnaBridge 143:86740a56073b 545 * @retval Returned value can be one of the following values:
AnnaBridge 143:86740a56073b 546 * @arg @ref LL_DAC_TRIG_SOFTWARE
AnnaBridge 143:86740a56073b 547 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
AnnaBridge 143:86740a56073b 548 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
AnnaBridge 143:86740a56073b 549 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO
AnnaBridge 143:86740a56073b 550 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
AnnaBridge 143:86740a56073b 551 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
AnnaBridge 143:86740a56073b 552 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO
AnnaBridge 143:86740a56073b 553 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
AnnaBridge 143:86740a56073b 554 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
AnnaBridge 143:86740a56073b 555 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
AnnaBridge 143:86740a56073b 556 */
AnnaBridge 143:86740a56073b 557 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge 143:86740a56073b 558 {
AnnaBridge 143:86740a56073b 559 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge 143:86740a56073b 560 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge 143:86740a56073b 561 );
AnnaBridge 143:86740a56073b 562 }
AnnaBridge 143:86740a56073b 563
AnnaBridge 143:86740a56073b 564 /**
AnnaBridge 143:86740a56073b 565 * @brief Set the waveform automatic generation mode
AnnaBridge 143:86740a56073b 566 * for the selected DAC channel.
AnnaBridge 143:86740a56073b 567 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
AnnaBridge 143:86740a56073b 568 * CR WAVE2 LL_DAC_SetWaveAutoGeneration
AnnaBridge 143:86740a56073b 569 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 570 * @param DAC_Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 571 * @arg @ref LL_DAC_CHANNEL_1
AnnaBridge 143:86740a56073b 572 * @arg @ref LL_DAC_CHANNEL_2
AnnaBridge 143:86740a56073b 573 * @param WaveAutoGeneration This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 574 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
AnnaBridge 143:86740a56073b 575 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
AnnaBridge 143:86740a56073b 576 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
AnnaBridge 143:86740a56073b 577 * @retval None
AnnaBridge 143:86740a56073b 578 */
AnnaBridge 143:86740a56073b 579 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
AnnaBridge 143:86740a56073b 580 {
AnnaBridge 143:86740a56073b 581 MODIFY_REG(DACx->CR,
AnnaBridge 143:86740a56073b 582 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge 143:86740a56073b 583 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge 143:86740a56073b 584 }
AnnaBridge 143:86740a56073b 585
AnnaBridge 143:86740a56073b 586 /**
AnnaBridge 143:86740a56073b 587 * @brief Get the waveform automatic generation mode
AnnaBridge 143:86740a56073b 588 * for the selected DAC channel.
AnnaBridge 143:86740a56073b 589 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
AnnaBridge 143:86740a56073b 590 * CR WAVE2 LL_DAC_GetWaveAutoGeneration
AnnaBridge 143:86740a56073b 591 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 592 * @param DAC_Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 593 * @arg @ref LL_DAC_CHANNEL_1
AnnaBridge 143:86740a56073b 594 * @arg @ref LL_DAC_CHANNEL_2
AnnaBridge 143:86740a56073b 595 * @retval Returned value can be one of the following values:
AnnaBridge 143:86740a56073b 596 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
AnnaBridge 143:86740a56073b 597 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
AnnaBridge 143:86740a56073b 598 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
AnnaBridge 143:86740a56073b 599 */
AnnaBridge 143:86740a56073b 600 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge 143:86740a56073b 601 {
AnnaBridge 143:86740a56073b 602 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge 143:86740a56073b 603 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge 143:86740a56073b 604 );
AnnaBridge 143:86740a56073b 605 }
AnnaBridge 143:86740a56073b 606
AnnaBridge 143:86740a56073b 607 /**
AnnaBridge 143:86740a56073b 608 * @brief Set the noise waveform generation for the selected DAC channel:
AnnaBridge 143:86740a56073b 609 * Noise mode and parameters LFSR (linear feedback shift register).
AnnaBridge 143:86740a56073b 610 * @note For wave generation to be effective, DAC channel
AnnaBridge 143:86740a56073b 611 * wave generation mode must be enabled using
AnnaBridge 143:86740a56073b 612 * function @ref LL_DAC_SetWaveAutoGeneration().
AnnaBridge 143:86740a56073b 613 * @note This setting can be set when the selected DAC channel is disabled
AnnaBridge 143:86740a56073b 614 * (otherwise, the setting operation is ignored).
AnnaBridge 143:86740a56073b 615 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
AnnaBridge 143:86740a56073b 616 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
AnnaBridge 143:86740a56073b 617 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 618 * @param DAC_Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 619 * @arg @ref LL_DAC_CHANNEL_1
AnnaBridge 143:86740a56073b 620 * @arg @ref LL_DAC_CHANNEL_2
AnnaBridge 143:86740a56073b 621 * @param NoiseLFSRMask This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 622 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
AnnaBridge 143:86740a56073b 623 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
AnnaBridge 143:86740a56073b 624 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
AnnaBridge 143:86740a56073b 625 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
AnnaBridge 143:86740a56073b 626 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
AnnaBridge 143:86740a56073b 627 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
AnnaBridge 143:86740a56073b 628 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
AnnaBridge 143:86740a56073b 629 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
AnnaBridge 143:86740a56073b 630 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
AnnaBridge 143:86740a56073b 631 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
AnnaBridge 143:86740a56073b 632 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
AnnaBridge 143:86740a56073b 633 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
AnnaBridge 143:86740a56073b 634 * @retval None
AnnaBridge 143:86740a56073b 635 */
AnnaBridge 143:86740a56073b 636 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
AnnaBridge 143:86740a56073b 637 {
AnnaBridge 143:86740a56073b 638 MODIFY_REG(DACx->CR,
AnnaBridge 143:86740a56073b 639 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge 143:86740a56073b 640 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge 143:86740a56073b 641 }
AnnaBridge 143:86740a56073b 642
AnnaBridge 143:86740a56073b 643 /**
AnnaBridge 143:86740a56073b 644 * @brief Set the noise waveform generation for the selected DAC channel:
AnnaBridge 143:86740a56073b 645 * Noise mode and parameters LFSR (linear feedback shift register).
AnnaBridge 143:86740a56073b 646 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
AnnaBridge 143:86740a56073b 647 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
AnnaBridge 143:86740a56073b 648 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 649 * @param DAC_Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 650 * @arg @ref LL_DAC_CHANNEL_1
AnnaBridge 143:86740a56073b 651 * @arg @ref LL_DAC_CHANNEL_2
AnnaBridge 143:86740a56073b 652 * @retval Returned value can be one of the following values:
AnnaBridge 143:86740a56073b 653 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
AnnaBridge 143:86740a56073b 654 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
AnnaBridge 143:86740a56073b 655 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
AnnaBridge 143:86740a56073b 656 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
AnnaBridge 143:86740a56073b 657 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
AnnaBridge 143:86740a56073b 658 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
AnnaBridge 143:86740a56073b 659 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
AnnaBridge 143:86740a56073b 660 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
AnnaBridge 143:86740a56073b 661 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
AnnaBridge 143:86740a56073b 662 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
AnnaBridge 143:86740a56073b 663 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
AnnaBridge 143:86740a56073b 664 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
AnnaBridge 143:86740a56073b 665 */
AnnaBridge 143:86740a56073b 666 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge 143:86740a56073b 667 {
AnnaBridge 143:86740a56073b 668 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge 143:86740a56073b 669 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge 143:86740a56073b 670 );
AnnaBridge 143:86740a56073b 671 }
AnnaBridge 143:86740a56073b 672
AnnaBridge 143:86740a56073b 673 /**
AnnaBridge 143:86740a56073b 674 * @brief Set the triangle waveform generation for the selected DAC channel:
AnnaBridge 143:86740a56073b 675 * triangle mode and amplitude.
AnnaBridge 143:86740a56073b 676 * @note For wave generation to be effective, DAC channel
AnnaBridge 143:86740a56073b 677 * wave generation mode must be enabled using
AnnaBridge 143:86740a56073b 678 * function @ref LL_DAC_SetWaveAutoGeneration().
AnnaBridge 143:86740a56073b 679 * @note This setting can be set when the selected DAC channel is disabled
AnnaBridge 143:86740a56073b 680 * (otherwise, the setting operation is ignored).
AnnaBridge 143:86740a56073b 681 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
AnnaBridge 143:86740a56073b 682 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
AnnaBridge 143:86740a56073b 683 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 684 * @param DAC_Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 685 * @arg @ref LL_DAC_CHANNEL_1
AnnaBridge 143:86740a56073b 686 * @arg @ref LL_DAC_CHANNEL_2
AnnaBridge 143:86740a56073b 687 * @param TriangleAmplitude This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 688 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
AnnaBridge 143:86740a56073b 689 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
AnnaBridge 143:86740a56073b 690 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
AnnaBridge 143:86740a56073b 691 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
AnnaBridge 143:86740a56073b 692 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
AnnaBridge 143:86740a56073b 693 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
AnnaBridge 143:86740a56073b 694 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
AnnaBridge 143:86740a56073b 695 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
AnnaBridge 143:86740a56073b 696 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
AnnaBridge 143:86740a56073b 697 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
AnnaBridge 143:86740a56073b 698 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
AnnaBridge 143:86740a56073b 699 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
AnnaBridge 143:86740a56073b 700 * @retval None
AnnaBridge 143:86740a56073b 701 */
AnnaBridge 143:86740a56073b 702 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude)
AnnaBridge 143:86740a56073b 703 {
AnnaBridge 143:86740a56073b 704 MODIFY_REG(DACx->CR,
AnnaBridge 143:86740a56073b 705 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge 143:86740a56073b 706 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge 143:86740a56073b 707 }
AnnaBridge 143:86740a56073b 708
AnnaBridge 143:86740a56073b 709 /**
AnnaBridge 143:86740a56073b 710 * @brief Set the triangle waveform generation for the selected DAC channel:
AnnaBridge 143:86740a56073b 711 * triangle mode and amplitude.
AnnaBridge 143:86740a56073b 712 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
AnnaBridge 143:86740a56073b 713 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
AnnaBridge 143:86740a56073b 714 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 715 * @param DAC_Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 716 * @arg @ref LL_DAC_CHANNEL_1
AnnaBridge 143:86740a56073b 717 * @arg @ref LL_DAC_CHANNEL_2
AnnaBridge 143:86740a56073b 718 * @retval Returned value can be one of the following values:
AnnaBridge 143:86740a56073b 719 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
AnnaBridge 143:86740a56073b 720 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
AnnaBridge 143:86740a56073b 721 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
AnnaBridge 143:86740a56073b 722 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
AnnaBridge 143:86740a56073b 723 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
AnnaBridge 143:86740a56073b 724 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
AnnaBridge 143:86740a56073b 725 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
AnnaBridge 143:86740a56073b 726 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
AnnaBridge 143:86740a56073b 727 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
AnnaBridge 143:86740a56073b 728 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
AnnaBridge 143:86740a56073b 729 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
AnnaBridge 143:86740a56073b 730 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
AnnaBridge 143:86740a56073b 731 */
AnnaBridge 143:86740a56073b 732 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge 143:86740a56073b 733 {
AnnaBridge 143:86740a56073b 734 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge 143:86740a56073b 735 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge 143:86740a56073b 736 );
AnnaBridge 143:86740a56073b 737 }
AnnaBridge 143:86740a56073b 738
AnnaBridge 143:86740a56073b 739 /**
AnnaBridge 143:86740a56073b 740 * @brief Set the output buffer for the selected DAC channel.
AnnaBridge 143:86740a56073b 741 * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n
AnnaBridge 143:86740a56073b 742 * CR BOFF2 LL_DAC_SetOutputBuffer
AnnaBridge 143:86740a56073b 743 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 744 * @param DAC_Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 745 * @arg @ref LL_DAC_CHANNEL_1
AnnaBridge 143:86740a56073b 746 * @arg @ref LL_DAC_CHANNEL_2
AnnaBridge 143:86740a56073b 747 * @param OutputBuffer This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 748 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
AnnaBridge 143:86740a56073b 749 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
AnnaBridge 143:86740a56073b 750 * @retval None
AnnaBridge 143:86740a56073b 751 */
AnnaBridge 143:86740a56073b 752 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
AnnaBridge 143:86740a56073b 753 {
AnnaBridge 143:86740a56073b 754 MODIFY_REG(DACx->CR,
AnnaBridge 143:86740a56073b 755 DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
AnnaBridge 143:86740a56073b 756 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge 143:86740a56073b 757 }
AnnaBridge 143:86740a56073b 758
AnnaBridge 143:86740a56073b 759 /**
AnnaBridge 143:86740a56073b 760 * @brief Get the output buffer state for the selected DAC channel.
AnnaBridge 143:86740a56073b 761 * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n
AnnaBridge 143:86740a56073b 762 * CR BOFF2 LL_DAC_GetOutputBuffer
AnnaBridge 143:86740a56073b 763 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 764 * @param DAC_Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 765 * @arg @ref LL_DAC_CHANNEL_1
AnnaBridge 143:86740a56073b 766 * @arg @ref LL_DAC_CHANNEL_2
AnnaBridge 143:86740a56073b 767 * @retval Returned value can be one of the following values:
AnnaBridge 143:86740a56073b 768 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
AnnaBridge 143:86740a56073b 769 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
AnnaBridge 143:86740a56073b 770 */
AnnaBridge 143:86740a56073b 771 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge 143:86740a56073b 772 {
AnnaBridge 143:86740a56073b 773 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge 143:86740a56073b 774 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
AnnaBridge 143:86740a56073b 775 );
AnnaBridge 143:86740a56073b 776 }
AnnaBridge 143:86740a56073b 777
AnnaBridge 143:86740a56073b 778 /**
AnnaBridge 143:86740a56073b 779 * @}
AnnaBridge 143:86740a56073b 780 */
AnnaBridge 143:86740a56073b 781
AnnaBridge 143:86740a56073b 782 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
AnnaBridge 143:86740a56073b 783 * @{
AnnaBridge 143:86740a56073b 784 */
AnnaBridge 143:86740a56073b 785
AnnaBridge 143:86740a56073b 786 /**
AnnaBridge 143:86740a56073b 787 * @brief Enable DAC DMA transfer request of the selected channel.
AnnaBridge 143:86740a56073b 788 * @note To configure DMA source address (peripheral address),
AnnaBridge 143:86740a56073b 789 * use function @ref LL_DAC_DMA_GetRegAddr().
AnnaBridge 143:86740a56073b 790 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
AnnaBridge 143:86740a56073b 791 * CR DMAEN2 LL_DAC_EnableDMAReq
AnnaBridge 143:86740a56073b 792 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 793 * @param DAC_Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 794 * @arg @ref LL_DAC_CHANNEL_1
AnnaBridge 143:86740a56073b 795 * @arg @ref LL_DAC_CHANNEL_2
AnnaBridge 143:86740a56073b 796 * @retval None
AnnaBridge 143:86740a56073b 797 */
AnnaBridge 143:86740a56073b 798 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge 143:86740a56073b 799 {
AnnaBridge 143:86740a56073b 800 SET_BIT(DACx->CR,
AnnaBridge 143:86740a56073b 801 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge 143:86740a56073b 802 }
AnnaBridge 143:86740a56073b 803
AnnaBridge 143:86740a56073b 804 /**
AnnaBridge 143:86740a56073b 805 * @brief Disable DAC DMA transfer request of the selected channel.
AnnaBridge 143:86740a56073b 806 * @note To configure DMA source address (peripheral address),
AnnaBridge 143:86740a56073b 807 * use function @ref LL_DAC_DMA_GetRegAddr().
AnnaBridge 143:86740a56073b 808 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
AnnaBridge 143:86740a56073b 809 * CR DMAEN2 LL_DAC_DisableDMAReq
AnnaBridge 143:86740a56073b 810 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 811 * @param DAC_Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 812 * @arg @ref LL_DAC_CHANNEL_1
AnnaBridge 143:86740a56073b 813 * @arg @ref LL_DAC_CHANNEL_2
AnnaBridge 143:86740a56073b 814 * @retval None
AnnaBridge 143:86740a56073b 815 */
AnnaBridge 143:86740a56073b 816 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge 143:86740a56073b 817 {
AnnaBridge 143:86740a56073b 818 CLEAR_BIT(DACx->CR,
AnnaBridge 143:86740a56073b 819 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge 143:86740a56073b 820 }
AnnaBridge 143:86740a56073b 821
AnnaBridge 143:86740a56073b 822 /**
AnnaBridge 143:86740a56073b 823 * @brief Get DAC DMA transfer request state of the selected channel.
AnnaBridge 143:86740a56073b 824 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
AnnaBridge 143:86740a56073b 825 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
AnnaBridge 143:86740a56073b 826 * CR DMAEN2 LL_DAC_IsDMAReqEnabled
AnnaBridge 143:86740a56073b 827 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 828 * @param DAC_Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 829 * @arg @ref LL_DAC_CHANNEL_1
AnnaBridge 143:86740a56073b 830 * @arg @ref LL_DAC_CHANNEL_2
AnnaBridge 143:86740a56073b 831 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 832 */
AnnaBridge 143:86740a56073b 833 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge 143:86740a56073b 834 {
AnnaBridge 143:86740a56073b 835 return (READ_BIT(DACx->CR,
AnnaBridge 143:86740a56073b 836 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge 143:86740a56073b 837 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
AnnaBridge 143:86740a56073b 838 }
AnnaBridge 143:86740a56073b 839
AnnaBridge 143:86740a56073b 840 /**
AnnaBridge 143:86740a56073b 841 * @brief Function to help to configure DMA transfer to DAC: retrieve the
AnnaBridge 143:86740a56073b 842 * DAC register address from DAC instance and a list of DAC registers
AnnaBridge 143:86740a56073b 843 * intended to be used (most commonly) with DMA transfer.
AnnaBridge 143:86740a56073b 844 * @note These DAC registers are data holding registers:
AnnaBridge 143:86740a56073b 845 * when DAC conversion is requested, DAC generates a DMA transfer
AnnaBridge 143:86740a56073b 846 * request to have data available in DAC data holding registers.
AnnaBridge 143:86740a56073b 847 * @note This macro is intended to be used with LL DMA driver, refer to
AnnaBridge 143:86740a56073b 848 * function "LL_DMA_ConfigAddresses()".
AnnaBridge 143:86740a56073b 849 * Example:
AnnaBridge 143:86740a56073b 850 * LL_DMA_ConfigAddresses(DMA1,
AnnaBridge 143:86740a56073b 851 * LL_DMA_CHANNEL_1,
AnnaBridge 143:86740a56073b 852 * (uint32_t)&< array or variable >,
AnnaBridge 143:86740a56073b 853 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
AnnaBridge 143:86740a56073b 854 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
AnnaBridge 143:86740a56073b 855 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
AnnaBridge 143:86740a56073b 856 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
AnnaBridge 143:86740a56073b 857 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
AnnaBridge 143:86740a56073b 858 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
AnnaBridge 143:86740a56073b 859 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
AnnaBridge 143:86740a56073b 860 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
AnnaBridge 143:86740a56073b 861 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 862 * @param DAC_Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 863 * @arg @ref LL_DAC_CHANNEL_1
AnnaBridge 143:86740a56073b 864 * @arg @ref LL_DAC_CHANNEL_2
AnnaBridge 143:86740a56073b 865 * @param Register This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 866 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
AnnaBridge 143:86740a56073b 867 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
AnnaBridge 143:86740a56073b 868 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
AnnaBridge 143:86740a56073b 869 * @retval DAC register address
AnnaBridge 143:86740a56073b 870 */
AnnaBridge 143:86740a56073b 871 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
AnnaBridge 143:86740a56073b 872 {
AnnaBridge 143:86740a56073b 873 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
AnnaBridge 143:86740a56073b 874 /* DAC channel selected. */
AnnaBridge 143:86740a56073b 875 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register))));
AnnaBridge 143:86740a56073b 876 }
AnnaBridge 143:86740a56073b 877 /**
AnnaBridge 143:86740a56073b 878 * @}
AnnaBridge 143:86740a56073b 879 */
AnnaBridge 143:86740a56073b 880
AnnaBridge 143:86740a56073b 881 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
AnnaBridge 143:86740a56073b 882 * @{
AnnaBridge 143:86740a56073b 883 */
AnnaBridge 143:86740a56073b 884
AnnaBridge 143:86740a56073b 885 /**
AnnaBridge 143:86740a56073b 886 * @brief Enable DAC selected channel.
AnnaBridge 143:86740a56073b 887 * @rmtoll CR EN1 LL_DAC_Enable\n
AnnaBridge 143:86740a56073b 888 * CR EN2 LL_DAC_Enable
AnnaBridge 143:86740a56073b 889 * @note After enable from off state, DAC channel requires a delay
AnnaBridge 143:86740a56073b 890 * for output voltage to reach accuracy +/- 1 LSB.
AnnaBridge 143:86740a56073b 891 * Refer to device datasheet, parameter "tWAKEUP".
AnnaBridge 143:86740a56073b 892 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 893 * @param DAC_Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 894 * @arg @ref LL_DAC_CHANNEL_1
AnnaBridge 143:86740a56073b 895 * @arg @ref LL_DAC_CHANNEL_2
AnnaBridge 143:86740a56073b 896 * @retval None
AnnaBridge 143:86740a56073b 897 */
AnnaBridge 143:86740a56073b 898 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge 143:86740a56073b 899 {
AnnaBridge 143:86740a56073b 900 SET_BIT(DACx->CR,
AnnaBridge 143:86740a56073b 901 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge 143:86740a56073b 902 }
AnnaBridge 143:86740a56073b 903
AnnaBridge 143:86740a56073b 904 /**
AnnaBridge 143:86740a56073b 905 * @brief Disable DAC selected channel.
AnnaBridge 143:86740a56073b 906 * @rmtoll CR EN1 LL_DAC_Disable\n
AnnaBridge 143:86740a56073b 907 * CR EN2 LL_DAC_Disable
AnnaBridge 143:86740a56073b 908 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 909 * @param DAC_Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 910 * @arg @ref LL_DAC_CHANNEL_1
AnnaBridge 143:86740a56073b 911 * @arg @ref LL_DAC_CHANNEL_2
AnnaBridge 143:86740a56073b 912 * @retval None
AnnaBridge 143:86740a56073b 913 */
AnnaBridge 143:86740a56073b 914 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge 143:86740a56073b 915 {
AnnaBridge 143:86740a56073b 916 CLEAR_BIT(DACx->CR,
AnnaBridge 143:86740a56073b 917 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge 143:86740a56073b 918 }
AnnaBridge 143:86740a56073b 919
AnnaBridge 143:86740a56073b 920 /**
AnnaBridge 143:86740a56073b 921 * @brief Get DAC enable state of the selected channel.
AnnaBridge 143:86740a56073b 922 * (0: DAC channel is disabled, 1: DAC channel is enabled)
AnnaBridge 143:86740a56073b 923 * @rmtoll CR EN1 LL_DAC_IsEnabled\n
AnnaBridge 143:86740a56073b 924 * CR EN2 LL_DAC_IsEnabled
AnnaBridge 143:86740a56073b 925 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 926 * @param DAC_Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 927 * @arg @ref LL_DAC_CHANNEL_1
AnnaBridge 143:86740a56073b 928 * @arg @ref LL_DAC_CHANNEL_2
AnnaBridge 143:86740a56073b 929 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 930 */
AnnaBridge 143:86740a56073b 931 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge 143:86740a56073b 932 {
AnnaBridge 143:86740a56073b 933 return (READ_BIT(DACx->CR,
AnnaBridge 143:86740a56073b 934 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge 143:86740a56073b 935 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
AnnaBridge 143:86740a56073b 936 }
AnnaBridge 143:86740a56073b 937
AnnaBridge 143:86740a56073b 938 /**
AnnaBridge 143:86740a56073b 939 * @brief Enable DAC trigger of the selected channel.
AnnaBridge 143:86740a56073b 940 * @note - If DAC trigger is disabled, DAC conversion is performed
AnnaBridge 143:86740a56073b 941 * automatically once the data holding register is updated,
AnnaBridge 143:86740a56073b 942 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
AnnaBridge 143:86740a56073b 943 * @ref LL_DAC_ConvertData12RightAligned(), ...
AnnaBridge 143:86740a56073b 944 * - If DAC trigger is enabled, DAC conversion is performed
AnnaBridge 143:86740a56073b 945 * only when a hardware of software trigger event is occurring.
AnnaBridge 143:86740a56073b 946 * Select trigger source using
AnnaBridge 143:86740a56073b 947 * function @ref LL_DAC_SetTriggerSource().
AnnaBridge 143:86740a56073b 948 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
AnnaBridge 143:86740a56073b 949 * CR TEN2 LL_DAC_EnableTrigger
AnnaBridge 143:86740a56073b 950 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 951 * @param DAC_Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 952 * @arg @ref LL_DAC_CHANNEL_1
AnnaBridge 143:86740a56073b 953 * @arg @ref LL_DAC_CHANNEL_2
AnnaBridge 143:86740a56073b 954 * @retval None
AnnaBridge 143:86740a56073b 955 */
AnnaBridge 143:86740a56073b 956 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge 143:86740a56073b 957 {
AnnaBridge 143:86740a56073b 958 SET_BIT(DACx->CR,
AnnaBridge 143:86740a56073b 959 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge 143:86740a56073b 960 }
AnnaBridge 143:86740a56073b 961
AnnaBridge 143:86740a56073b 962 /**
AnnaBridge 143:86740a56073b 963 * @brief Disable DAC trigger of the selected channel.
AnnaBridge 143:86740a56073b 964 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
AnnaBridge 143:86740a56073b 965 * CR TEN2 LL_DAC_DisableTrigger
AnnaBridge 143:86740a56073b 966 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 967 * @param DAC_Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 968 * @arg @ref LL_DAC_CHANNEL_1
AnnaBridge 143:86740a56073b 969 * @arg @ref LL_DAC_CHANNEL_2
AnnaBridge 143:86740a56073b 970 * @retval None
AnnaBridge 143:86740a56073b 971 */
AnnaBridge 143:86740a56073b 972 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge 143:86740a56073b 973 {
AnnaBridge 143:86740a56073b 974 CLEAR_BIT(DACx->CR,
AnnaBridge 143:86740a56073b 975 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
AnnaBridge 143:86740a56073b 976 }
AnnaBridge 143:86740a56073b 977
AnnaBridge 143:86740a56073b 978 /**
AnnaBridge 143:86740a56073b 979 * @brief Get DAC trigger state of the selected channel.
AnnaBridge 143:86740a56073b 980 * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
AnnaBridge 143:86740a56073b 981 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
AnnaBridge 143:86740a56073b 982 * CR TEN2 LL_DAC_IsTriggerEnabled
AnnaBridge 143:86740a56073b 983 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 984 * @param DAC_Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 985 * @arg @ref LL_DAC_CHANNEL_1
AnnaBridge 143:86740a56073b 986 * @arg @ref LL_DAC_CHANNEL_2
AnnaBridge 143:86740a56073b 987 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 988 */
AnnaBridge 143:86740a56073b 989 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge 143:86740a56073b 990 {
AnnaBridge 143:86740a56073b 991 return (READ_BIT(DACx->CR,
AnnaBridge 143:86740a56073b 992 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
AnnaBridge 143:86740a56073b 993 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)));
AnnaBridge 143:86740a56073b 994 }
AnnaBridge 143:86740a56073b 995
AnnaBridge 143:86740a56073b 996 /**
AnnaBridge 143:86740a56073b 997 * @brief Trig DAC conversion by software for the selected DAC channel.
AnnaBridge 143:86740a56073b 998 * @note Preliminarily, DAC trigger must be set to software trigger
AnnaBridge 143:86740a56073b 999 * using function @ref LL_DAC_SetTriggerSource()
AnnaBridge 143:86740a56073b 1000 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
AnnaBridge 143:86740a56073b 1001 * and DAC trigger must be enabled using
AnnaBridge 143:86740a56073b 1002 * function @ref LL_DAC_EnableTrigger().
AnnaBridge 143:86740a56073b 1003 * @note For devices featuring DAC with 2 channels: this function
AnnaBridge 143:86740a56073b 1004 * can perform a SW start of both DAC channels simultaneously.
AnnaBridge 143:86740a56073b 1005 * Two channels can be selected as parameter.
AnnaBridge 143:86740a56073b 1006 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
AnnaBridge 143:86740a56073b 1007 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
AnnaBridge 143:86740a56073b 1008 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
AnnaBridge 143:86740a56073b 1009 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 1010 * @param DAC_Channel This parameter can a combination of the following values:
AnnaBridge 143:86740a56073b 1011 * @arg @ref LL_DAC_CHANNEL_1
AnnaBridge 143:86740a56073b 1012 * @arg @ref LL_DAC_CHANNEL_2
AnnaBridge 143:86740a56073b 1013 * @retval None
AnnaBridge 143:86740a56073b 1014 */
AnnaBridge 143:86740a56073b 1015 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge 143:86740a56073b 1016 {
AnnaBridge 143:86740a56073b 1017 SET_BIT(DACx->SWTRIGR,
AnnaBridge 143:86740a56073b 1018 (DAC_Channel & DAC_SWTR_CHX_MASK));
AnnaBridge 143:86740a56073b 1019 }
AnnaBridge 143:86740a56073b 1020
AnnaBridge 143:86740a56073b 1021 /**
AnnaBridge 143:86740a56073b 1022 * @brief Set the data to be loaded in the data holding register
AnnaBridge 143:86740a56073b 1023 * in format 12 bits left alignment (LSB aligned on bit 0),
AnnaBridge 143:86740a56073b 1024 * for the selected DAC channel.
AnnaBridge 143:86740a56073b 1025 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
AnnaBridge 143:86740a56073b 1026 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
AnnaBridge 143:86740a56073b 1027 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 1028 * @param DAC_Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 1029 * @arg @ref LL_DAC_CHANNEL_1
AnnaBridge 143:86740a56073b 1030 * @arg @ref LL_DAC_CHANNEL_2
AnnaBridge 143:86740a56073b 1031 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
AnnaBridge 143:86740a56073b 1032 * @retval None
AnnaBridge 143:86740a56073b 1033 */
AnnaBridge 143:86740a56073b 1034 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
AnnaBridge 143:86740a56073b 1035 {
AnnaBridge 143:86740a56073b 1036 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK));
AnnaBridge 143:86740a56073b 1037
AnnaBridge 143:86740a56073b 1038 MODIFY_REG(*preg,
AnnaBridge 143:86740a56073b 1039 DAC_DHR12R1_DACC1DHR,
AnnaBridge 143:86740a56073b 1040 Data);
AnnaBridge 143:86740a56073b 1041 }
AnnaBridge 143:86740a56073b 1042
AnnaBridge 143:86740a56073b 1043 /**
AnnaBridge 143:86740a56073b 1044 * @brief Set the data to be loaded in the data holding register
AnnaBridge 143:86740a56073b 1045 * in format 12 bits left alignment (MSB aligned on bit 15),
AnnaBridge 143:86740a56073b 1046 * for the selected DAC channel.
AnnaBridge 143:86740a56073b 1047 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
AnnaBridge 143:86740a56073b 1048 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
AnnaBridge 143:86740a56073b 1049 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 1050 * @param DAC_Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 1051 * @arg @ref LL_DAC_CHANNEL_1
AnnaBridge 143:86740a56073b 1052 * @arg @ref LL_DAC_CHANNEL_2
AnnaBridge 143:86740a56073b 1053 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
AnnaBridge 143:86740a56073b 1054 * @retval None
AnnaBridge 143:86740a56073b 1055 */
AnnaBridge 143:86740a56073b 1056 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
AnnaBridge 143:86740a56073b 1057 {
AnnaBridge 143:86740a56073b 1058 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK));
AnnaBridge 143:86740a56073b 1059
AnnaBridge 143:86740a56073b 1060 MODIFY_REG(*preg,
AnnaBridge 143:86740a56073b 1061 DAC_DHR12L1_DACC1DHR,
AnnaBridge 143:86740a56073b 1062 Data);
AnnaBridge 143:86740a56073b 1063 }
AnnaBridge 143:86740a56073b 1064
AnnaBridge 143:86740a56073b 1065 /**
AnnaBridge 143:86740a56073b 1066 * @brief Set the data to be loaded in the data holding register
AnnaBridge 143:86740a56073b 1067 * in format 8 bits left alignment (LSB aligned on bit 0),
AnnaBridge 143:86740a56073b 1068 * for the selected DAC channel.
AnnaBridge 143:86740a56073b 1069 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
AnnaBridge 143:86740a56073b 1070 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
AnnaBridge 143:86740a56073b 1071 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 1072 * @param DAC_Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 1073 * @arg @ref LL_DAC_CHANNEL_1
AnnaBridge 143:86740a56073b 1074 * @arg @ref LL_DAC_CHANNEL_2
AnnaBridge 143:86740a56073b 1075 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge 143:86740a56073b 1076 * @retval None
AnnaBridge 143:86740a56073b 1077 */
AnnaBridge 143:86740a56073b 1078 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
AnnaBridge 143:86740a56073b 1079 {
AnnaBridge 143:86740a56073b 1080 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK));
AnnaBridge 143:86740a56073b 1081
AnnaBridge 143:86740a56073b 1082 MODIFY_REG(*preg,
AnnaBridge 143:86740a56073b 1083 DAC_DHR8R1_DACC1DHR,
AnnaBridge 143:86740a56073b 1084 Data);
AnnaBridge 143:86740a56073b 1085 }
AnnaBridge 143:86740a56073b 1086
AnnaBridge 143:86740a56073b 1087 /**
AnnaBridge 143:86740a56073b 1088 * @brief Set the data to be loaded in the data holding register
AnnaBridge 143:86740a56073b 1089 * in format 12 bits left alignment (LSB aligned on bit 0),
AnnaBridge 143:86740a56073b 1090 * for both DAC channels.
AnnaBridge 143:86740a56073b 1091 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
AnnaBridge 143:86740a56073b 1092 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
AnnaBridge 143:86740a56073b 1093 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 1094 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
AnnaBridge 143:86740a56073b 1095 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
AnnaBridge 143:86740a56073b 1096 * @retval None
AnnaBridge 143:86740a56073b 1097 */
AnnaBridge 143:86740a56073b 1098 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
AnnaBridge 143:86740a56073b 1099 {
AnnaBridge 143:86740a56073b 1100 MODIFY_REG(DACx->DHR12RD,
AnnaBridge 143:86740a56073b 1101 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
AnnaBridge 143:86740a56073b 1102 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
AnnaBridge 143:86740a56073b 1103 }
AnnaBridge 143:86740a56073b 1104
AnnaBridge 143:86740a56073b 1105 /**
AnnaBridge 143:86740a56073b 1106 * @brief Set the data to be loaded in the data holding register
AnnaBridge 143:86740a56073b 1107 * in format 12 bits left alignment (MSB aligned on bit 15),
AnnaBridge 143:86740a56073b 1108 * for both DAC channels.
AnnaBridge 143:86740a56073b 1109 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
AnnaBridge 143:86740a56073b 1110 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
AnnaBridge 143:86740a56073b 1111 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 1112 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
AnnaBridge 143:86740a56073b 1113 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
AnnaBridge 143:86740a56073b 1114 * @retval None
AnnaBridge 143:86740a56073b 1115 */
AnnaBridge 143:86740a56073b 1116 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
AnnaBridge 143:86740a56073b 1117 {
AnnaBridge 143:86740a56073b 1118 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
AnnaBridge 143:86740a56073b 1119 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
AnnaBridge 143:86740a56073b 1120 /* the 4 LSB must be taken into account for the shift value. */
AnnaBridge 143:86740a56073b 1121 MODIFY_REG(DACx->DHR12LD,
AnnaBridge 143:86740a56073b 1122 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
AnnaBridge 143:86740a56073b 1123 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
AnnaBridge 143:86740a56073b 1124 }
AnnaBridge 143:86740a56073b 1125
AnnaBridge 143:86740a56073b 1126 /**
AnnaBridge 143:86740a56073b 1127 * @brief Set the data to be loaded in the data holding register
AnnaBridge 143:86740a56073b 1128 * in format 8 bits left alignment (LSB aligned on bit 0),
AnnaBridge 143:86740a56073b 1129 * for both DAC channels.
AnnaBridge 143:86740a56073b 1130 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
AnnaBridge 143:86740a56073b 1131 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
AnnaBridge 143:86740a56073b 1132 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 1133 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge 143:86740a56073b 1134 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge 143:86740a56073b 1135 * @retval None
AnnaBridge 143:86740a56073b 1136 */
AnnaBridge 143:86740a56073b 1137 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2)
AnnaBridge 143:86740a56073b 1138 {
AnnaBridge 143:86740a56073b 1139 MODIFY_REG(DACx->DHR8RD,
AnnaBridge 143:86740a56073b 1140 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
AnnaBridge 143:86740a56073b 1141 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
AnnaBridge 143:86740a56073b 1142 }
AnnaBridge 143:86740a56073b 1143
AnnaBridge 143:86740a56073b 1144 /**
AnnaBridge 143:86740a56073b 1145 * @brief Retrieve output data currently generated for the selected DAC channel.
AnnaBridge 143:86740a56073b 1146 * @note Whatever alignment and resolution settings
AnnaBridge 143:86740a56073b 1147 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
AnnaBridge 143:86740a56073b 1148 * @ref LL_DAC_ConvertData12RightAligned(), ...),
AnnaBridge 143:86740a56073b 1149 * output data format is 12 bits right aligned (LSB aligned on bit 0).
AnnaBridge 143:86740a56073b 1150 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
AnnaBridge 143:86740a56073b 1151 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
AnnaBridge 143:86740a56073b 1152 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 1153 * @param DAC_Channel This parameter can be one of the following values:
AnnaBridge 143:86740a56073b 1154 * @arg @ref LL_DAC_CHANNEL_1
AnnaBridge 143:86740a56073b 1155 * @arg @ref LL_DAC_CHANNEL_2
AnnaBridge 143:86740a56073b 1156 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
AnnaBridge 143:86740a56073b 1157 */
AnnaBridge 143:86740a56073b 1158 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
AnnaBridge 143:86740a56073b 1159 {
AnnaBridge 143:86740a56073b 1160 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK));
AnnaBridge 143:86740a56073b 1161
AnnaBridge 143:86740a56073b 1162 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
AnnaBridge 143:86740a56073b 1163 }
AnnaBridge 143:86740a56073b 1164
AnnaBridge 143:86740a56073b 1165 /**
AnnaBridge 143:86740a56073b 1166 * @}
AnnaBridge 143:86740a56073b 1167 */
AnnaBridge 143:86740a56073b 1168
AnnaBridge 143:86740a56073b 1169 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
AnnaBridge 143:86740a56073b 1170 * @{
AnnaBridge 143:86740a56073b 1171 */
AnnaBridge 143:86740a56073b 1172 #if defined(DAC_SR_DMAUDR1)
AnnaBridge 143:86740a56073b 1173 /**
AnnaBridge 143:86740a56073b 1174 * @brief Get DAC underrun flag for DAC channel 1
AnnaBridge 143:86740a56073b 1175 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
AnnaBridge 143:86740a56073b 1176 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 1177 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 1178 */
AnnaBridge 143:86740a56073b 1179 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
AnnaBridge 143:86740a56073b 1180 {
AnnaBridge 143:86740a56073b 1181 return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1));
AnnaBridge 143:86740a56073b 1182 }
AnnaBridge 143:86740a56073b 1183 #endif /* DAC_SR_DMAUDR1 */
AnnaBridge 143:86740a56073b 1184
AnnaBridge 143:86740a56073b 1185 #if defined(DAC_SR_DMAUDR2)
AnnaBridge 143:86740a56073b 1186 /**
AnnaBridge 143:86740a56073b 1187 * @brief Get DAC underrun flag for DAC channel 2
AnnaBridge 143:86740a56073b 1188 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
AnnaBridge 143:86740a56073b 1189 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 1190 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 1191 */
AnnaBridge 143:86740a56073b 1192 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
AnnaBridge 143:86740a56073b 1193 {
AnnaBridge 143:86740a56073b 1194 return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2));
AnnaBridge 143:86740a56073b 1195 }
AnnaBridge 143:86740a56073b 1196 #endif /* DAC_SR_DMAUDR2 */
AnnaBridge 143:86740a56073b 1197
AnnaBridge 143:86740a56073b 1198 #if defined(DAC_SR_DMAUDR1)
AnnaBridge 143:86740a56073b 1199 /**
AnnaBridge 143:86740a56073b 1200 * @brief Clear DAC underrun flag for DAC channel 1
AnnaBridge 143:86740a56073b 1201 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
AnnaBridge 143:86740a56073b 1202 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 1203 * @retval None
AnnaBridge 143:86740a56073b 1204 */
AnnaBridge 143:86740a56073b 1205 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
AnnaBridge 143:86740a56073b 1206 {
AnnaBridge 143:86740a56073b 1207 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
AnnaBridge 143:86740a56073b 1208 }
AnnaBridge 143:86740a56073b 1209 #endif /* DAC_SR_DMAUDR1 */
AnnaBridge 143:86740a56073b 1210
AnnaBridge 143:86740a56073b 1211 #if defined(DAC_SR_DMAUDR2)
AnnaBridge 143:86740a56073b 1212 /**
AnnaBridge 143:86740a56073b 1213 * @brief Clear DAC underrun flag for DAC channel 2
AnnaBridge 143:86740a56073b 1214 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
AnnaBridge 143:86740a56073b 1215 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 1216 * @retval None
AnnaBridge 143:86740a56073b 1217 */
AnnaBridge 143:86740a56073b 1218 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
AnnaBridge 143:86740a56073b 1219 {
AnnaBridge 143:86740a56073b 1220 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
AnnaBridge 143:86740a56073b 1221 }
AnnaBridge 143:86740a56073b 1222 #endif /* DAC_SR_DMAUDR2 */
AnnaBridge 143:86740a56073b 1223
AnnaBridge 143:86740a56073b 1224 /**
AnnaBridge 143:86740a56073b 1225 * @}
AnnaBridge 143:86740a56073b 1226 */
AnnaBridge 143:86740a56073b 1227 /** @defgroup DAC_LL_EF_IT_Management IT management
AnnaBridge 143:86740a56073b 1228 * @{
AnnaBridge 143:86740a56073b 1229 */
AnnaBridge 143:86740a56073b 1230
AnnaBridge 143:86740a56073b 1231 #if defined(DAC_CR_DMAUDRIE1)
AnnaBridge 143:86740a56073b 1232 /**
AnnaBridge 143:86740a56073b 1233 * @brief Enable DMA underrun interrupt for DAC channel 1
AnnaBridge 143:86740a56073b 1234 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
AnnaBridge 143:86740a56073b 1235 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 1236 * @retval None
AnnaBridge 143:86740a56073b 1237 */
AnnaBridge 143:86740a56073b 1238 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
AnnaBridge 143:86740a56073b 1239 {
AnnaBridge 143:86740a56073b 1240 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
AnnaBridge 143:86740a56073b 1241 }
AnnaBridge 143:86740a56073b 1242 #endif /* DAC_CR_DMAUDRIE1 */
AnnaBridge 143:86740a56073b 1243
AnnaBridge 143:86740a56073b 1244 #if defined(DAC_CR_DMAUDRIE2)
AnnaBridge 143:86740a56073b 1245 /**
AnnaBridge 143:86740a56073b 1246 * @brief Enable DMA underrun interrupt for DAC channel 2
AnnaBridge 143:86740a56073b 1247 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
AnnaBridge 143:86740a56073b 1248 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 1249 * @retval None
AnnaBridge 143:86740a56073b 1250 */
AnnaBridge 143:86740a56073b 1251 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
AnnaBridge 143:86740a56073b 1252 {
AnnaBridge 143:86740a56073b 1253 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
AnnaBridge 143:86740a56073b 1254 }
AnnaBridge 143:86740a56073b 1255 #endif /* DAC_CR_DMAUDRIE2 */
AnnaBridge 143:86740a56073b 1256
AnnaBridge 143:86740a56073b 1257 #if defined(DAC_CR_DMAUDRIE1)
AnnaBridge 143:86740a56073b 1258 /**
AnnaBridge 143:86740a56073b 1259 * @brief Disable DMA underrun interrupt for DAC channel 1
AnnaBridge 143:86740a56073b 1260 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
AnnaBridge 143:86740a56073b 1261 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 1262 * @retval None
AnnaBridge 143:86740a56073b 1263 */
AnnaBridge 143:86740a56073b 1264 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
AnnaBridge 143:86740a56073b 1265 {
AnnaBridge 143:86740a56073b 1266 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
AnnaBridge 143:86740a56073b 1267 }
AnnaBridge 143:86740a56073b 1268 #endif /* DAC_CR_DMAUDRIE1 */
AnnaBridge 143:86740a56073b 1269
AnnaBridge 143:86740a56073b 1270 #if defined(DAC_CR_DMAUDRIE2)
AnnaBridge 143:86740a56073b 1271 /**
AnnaBridge 143:86740a56073b 1272 * @brief Disable DMA underrun interrupt for DAC channel 2
AnnaBridge 143:86740a56073b 1273 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
AnnaBridge 143:86740a56073b 1274 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 1275 * @retval None
AnnaBridge 143:86740a56073b 1276 */
AnnaBridge 143:86740a56073b 1277 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
AnnaBridge 143:86740a56073b 1278 {
AnnaBridge 143:86740a56073b 1279 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
AnnaBridge 143:86740a56073b 1280 }
AnnaBridge 143:86740a56073b 1281 #endif /* DAC_CR_DMAUDRIE2 */
AnnaBridge 143:86740a56073b 1282
AnnaBridge 143:86740a56073b 1283 #if defined(DAC_CR_DMAUDRIE1)
AnnaBridge 143:86740a56073b 1284 /**
AnnaBridge 143:86740a56073b 1285 * @brief Get DMA underrun interrupt for DAC channel 1
AnnaBridge 143:86740a56073b 1286 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
AnnaBridge 143:86740a56073b 1287 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 1288 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 1289 */
AnnaBridge 143:86740a56073b 1290 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
AnnaBridge 143:86740a56073b 1291 {
AnnaBridge 143:86740a56073b 1292 return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1));
AnnaBridge 143:86740a56073b 1293 }
AnnaBridge 143:86740a56073b 1294 #endif /* DAC_CR_DMAUDRIE1 */
AnnaBridge 143:86740a56073b 1295
AnnaBridge 143:86740a56073b 1296 #if defined(DAC_CR_DMAUDRIE2)
AnnaBridge 143:86740a56073b 1297 /**
AnnaBridge 143:86740a56073b 1298 * @brief Get DMA underrun interrupt for DAC channel 2
AnnaBridge 143:86740a56073b 1299 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
AnnaBridge 143:86740a56073b 1300 * @param DACx DAC instance
AnnaBridge 143:86740a56073b 1301 * @retval State of bit (1 or 0).
AnnaBridge 143:86740a56073b 1302 */
AnnaBridge 143:86740a56073b 1303 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
AnnaBridge 143:86740a56073b 1304 {
AnnaBridge 143:86740a56073b 1305 return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2));
AnnaBridge 143:86740a56073b 1306 }
AnnaBridge 143:86740a56073b 1307 #endif /* DAC_CR_DMAUDRIE2 */
AnnaBridge 143:86740a56073b 1308
AnnaBridge 143:86740a56073b 1309 /**
AnnaBridge 143:86740a56073b 1310 * @}
AnnaBridge 143:86740a56073b 1311 */
AnnaBridge 143:86740a56073b 1312
AnnaBridge 143:86740a56073b 1313 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 143:86740a56073b 1314 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
AnnaBridge 143:86740a56073b 1315 * @{
AnnaBridge 143:86740a56073b 1316 */
AnnaBridge 143:86740a56073b 1317
AnnaBridge 143:86740a56073b 1318 ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx);
AnnaBridge 143:86740a56073b 1319 ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct);
AnnaBridge 143:86740a56073b 1320 void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct);
AnnaBridge 143:86740a56073b 1321
AnnaBridge 143:86740a56073b 1322 /**
AnnaBridge 143:86740a56073b 1323 * @}
AnnaBridge 143:86740a56073b 1324 */
AnnaBridge 143:86740a56073b 1325 #endif /* USE_FULL_LL_DRIVER */
AnnaBridge 143:86740a56073b 1326
AnnaBridge 143:86740a56073b 1327 /**
AnnaBridge 143:86740a56073b 1328 * @}
AnnaBridge 143:86740a56073b 1329 */
AnnaBridge 143:86740a56073b 1330
AnnaBridge 143:86740a56073b 1331 /**
AnnaBridge 143:86740a56073b 1332 * @}
AnnaBridge 143:86740a56073b 1333 */
AnnaBridge 143:86740a56073b 1334
AnnaBridge 143:86740a56073b 1335 #endif /* DAC */
AnnaBridge 143:86740a56073b 1336
AnnaBridge 143:86740a56073b 1337 /**
AnnaBridge 143:86740a56073b 1338 * @}
AnnaBridge 143:86740a56073b 1339 */
AnnaBridge 143:86740a56073b 1340
AnnaBridge 143:86740a56073b 1341 #ifdef __cplusplus
AnnaBridge 143:86740a56073b 1342 }
AnnaBridge 143:86740a56073b 1343 #endif
AnnaBridge 143:86740a56073b 1344
AnnaBridge 143:86740a56073b 1345 #endif /* __STM32F1xx_LL_DAC_H */
AnnaBridge 143:86740a56073b 1346
AnnaBridge 143:86740a56073b 1347 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/