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TARGET_NUCLEO_F103RB/TOOLCHAIN_GCC_ARM/stm32f1xx_hal_dma_ex.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
AnnaBridge | 171:3a7713b1edbc | 1 | /** |
AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32f1xx_hal_dma_ex.h |
AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of DMA HAL extension module. |
AnnaBridge | 171:3a7713b1edbc | 6 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 7 | * @attention |
AnnaBridge | 171:3a7713b1edbc | 8 | * |
AnnaBridge | 171:3a7713b1edbc | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
AnnaBridge | 171:3a7713b1edbc | 10 | * |
AnnaBridge | 171:3a7713b1edbc | 11 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 171:3a7713b1edbc | 12 | * are permitted provided that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 14 | * this list of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 171:3a7713b1edbc | 17 | * and/or other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 171:3a7713b1edbc | 19 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 171:3a7713b1edbc | 20 | * without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 21 | * |
AnnaBridge | 171:3a7713b1edbc | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 171:3a7713b1edbc | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 171:3a7713b1edbc | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 171:3a7713b1edbc | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 171:3a7713b1edbc | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 171:3a7713b1edbc | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 171:3a7713b1edbc | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 171:3a7713b1edbc | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 171:3a7713b1edbc | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 171:3a7713b1edbc | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 32 | * |
AnnaBridge | 171:3a7713b1edbc | 33 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 34 | */ |
AnnaBridge | 171:3a7713b1edbc | 35 | |
AnnaBridge | 171:3a7713b1edbc | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 37 | #ifndef __STM32F1xx_HAL_DMA_EX_H |
AnnaBridge | 171:3a7713b1edbc | 38 | #define __STM32F1xx_HAL_DMA_EX_H |
AnnaBridge | 171:3a7713b1edbc | 39 | |
AnnaBridge | 171:3a7713b1edbc | 40 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 41 | extern "C" { |
AnnaBridge | 171:3a7713b1edbc | 42 | #endif |
AnnaBridge | 171:3a7713b1edbc | 43 | |
AnnaBridge | 171:3a7713b1edbc | 44 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 45 | #include "stm32f1xx_hal_def.h" |
AnnaBridge | 171:3a7713b1edbc | 46 | |
AnnaBridge | 171:3a7713b1edbc | 47 | /** @addtogroup STM32F1xx_HAL_Driver |
AnnaBridge | 171:3a7713b1edbc | 48 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 49 | */ |
AnnaBridge | 171:3a7713b1edbc | 50 | |
AnnaBridge | 171:3a7713b1edbc | 51 | /** @defgroup DMAEx DMAEx |
AnnaBridge | 171:3a7713b1edbc | 52 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 53 | */ |
AnnaBridge | 171:3a7713b1edbc | 54 | |
AnnaBridge | 171:3a7713b1edbc | 55 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 56 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 57 | /* Exported macro ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 58 | /** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros |
AnnaBridge | 171:3a7713b1edbc | 59 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 60 | */ |
AnnaBridge | 171:3a7713b1edbc | 61 | /* Interrupt & Flag management */ |
AnnaBridge | 171:3a7713b1edbc | 62 | #if defined (STM32F100xE) || defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || \ |
AnnaBridge | 171:3a7713b1edbc | 63 | defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC) |
AnnaBridge | 171:3a7713b1edbc | 64 | /** @defgroup DMAEx_High_density_XL_density_Product_devices DMAEx High density and XL density product devices |
AnnaBridge | 171:3a7713b1edbc | 65 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 66 | */ |
AnnaBridge | 171:3a7713b1edbc | 67 | |
AnnaBridge | 171:3a7713b1edbc | 68 | /** |
AnnaBridge | 171:3a7713b1edbc | 69 | * @brief Returns the current DMA Channel transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 70 | * @param __HANDLE__: DMA handle |
AnnaBridge | 171:3a7713b1edbc | 71 | * @retval The specified transfer complete flag index. |
AnnaBridge | 171:3a7713b1edbc | 72 | */ |
AnnaBridge | 171:3a7713b1edbc | 73 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
AnnaBridge | 171:3a7713b1edbc | 74 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ |
AnnaBridge | 171:3a7713b1edbc | 75 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ |
AnnaBridge | 171:3a7713b1edbc | 76 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ |
AnnaBridge | 171:3a7713b1edbc | 77 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ |
AnnaBridge | 171:3a7713b1edbc | 78 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ |
AnnaBridge | 171:3a7713b1edbc | 79 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ |
AnnaBridge | 171:3a7713b1edbc | 80 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\ |
AnnaBridge | 171:3a7713b1edbc | 81 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ |
AnnaBridge | 171:3a7713b1edbc | 82 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ |
AnnaBridge | 171:3a7713b1edbc | 83 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ |
AnnaBridge | 171:3a7713b1edbc | 84 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ |
AnnaBridge | 171:3a7713b1edbc | 85 | DMA_FLAG_TC5) |
AnnaBridge | 171:3a7713b1edbc | 86 | |
AnnaBridge | 171:3a7713b1edbc | 87 | /** |
AnnaBridge | 171:3a7713b1edbc | 88 | * @brief Returns the current DMA Channel half transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 89 | * @param __HANDLE__: DMA handle |
AnnaBridge | 171:3a7713b1edbc | 90 | * @retval The specified half transfer complete flag index. |
AnnaBridge | 171:3a7713b1edbc | 91 | */ |
AnnaBridge | 171:3a7713b1edbc | 92 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
AnnaBridge | 171:3a7713b1edbc | 93 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ |
AnnaBridge | 171:3a7713b1edbc | 94 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ |
AnnaBridge | 171:3a7713b1edbc | 95 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ |
AnnaBridge | 171:3a7713b1edbc | 96 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ |
AnnaBridge | 171:3a7713b1edbc | 97 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ |
AnnaBridge | 171:3a7713b1edbc | 98 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ |
AnnaBridge | 171:3a7713b1edbc | 99 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\ |
AnnaBridge | 171:3a7713b1edbc | 100 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ |
AnnaBridge | 171:3a7713b1edbc | 101 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ |
AnnaBridge | 171:3a7713b1edbc | 102 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ |
AnnaBridge | 171:3a7713b1edbc | 103 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ |
AnnaBridge | 171:3a7713b1edbc | 104 | DMA_FLAG_HT5) |
AnnaBridge | 171:3a7713b1edbc | 105 | |
AnnaBridge | 171:3a7713b1edbc | 106 | /** |
AnnaBridge | 171:3a7713b1edbc | 107 | * @brief Returns the current DMA Channel transfer error flag. |
AnnaBridge | 171:3a7713b1edbc | 108 | * @param __HANDLE__: DMA handle |
AnnaBridge | 171:3a7713b1edbc | 109 | * @retval The specified transfer error flag index. |
AnnaBridge | 171:3a7713b1edbc | 110 | */ |
AnnaBridge | 171:3a7713b1edbc | 111 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
AnnaBridge | 171:3a7713b1edbc | 112 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ |
AnnaBridge | 171:3a7713b1edbc | 113 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ |
AnnaBridge | 171:3a7713b1edbc | 114 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ |
AnnaBridge | 171:3a7713b1edbc | 115 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ |
AnnaBridge | 171:3a7713b1edbc | 116 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ |
AnnaBridge | 171:3a7713b1edbc | 117 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ |
AnnaBridge | 171:3a7713b1edbc | 118 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\ |
AnnaBridge | 171:3a7713b1edbc | 119 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ |
AnnaBridge | 171:3a7713b1edbc | 120 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ |
AnnaBridge | 171:3a7713b1edbc | 121 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ |
AnnaBridge | 171:3a7713b1edbc | 122 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ |
AnnaBridge | 171:3a7713b1edbc | 123 | DMA_FLAG_TE5) |
AnnaBridge | 171:3a7713b1edbc | 124 | |
AnnaBridge | 171:3a7713b1edbc | 125 | /** |
AnnaBridge | 171:3a7713b1edbc | 126 | * @brief Return the current DMA Channel Global interrupt flag. |
AnnaBridge | 171:3a7713b1edbc | 127 | * @param __HANDLE__: DMA handle |
AnnaBridge | 171:3a7713b1edbc | 128 | * @retval The specified transfer error flag index. |
AnnaBridge | 171:3a7713b1edbc | 129 | */ |
AnnaBridge | 171:3a7713b1edbc | 130 | #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ |
AnnaBridge | 171:3a7713b1edbc | 131 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ |
AnnaBridge | 171:3a7713b1edbc | 132 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ |
AnnaBridge | 171:3a7713b1edbc | 133 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ |
AnnaBridge | 171:3a7713b1edbc | 134 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ |
AnnaBridge | 171:3a7713b1edbc | 135 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ |
AnnaBridge | 171:3a7713b1edbc | 136 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ |
AnnaBridge | 171:3a7713b1edbc | 137 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\ |
AnnaBridge | 171:3a7713b1edbc | 138 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\ |
AnnaBridge | 171:3a7713b1edbc | 139 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\ |
AnnaBridge | 171:3a7713b1edbc | 140 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\ |
AnnaBridge | 171:3a7713b1edbc | 141 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\ |
AnnaBridge | 171:3a7713b1edbc | 142 | DMA_FLAG_GL5) |
AnnaBridge | 171:3a7713b1edbc | 143 | |
AnnaBridge | 171:3a7713b1edbc | 144 | /** |
AnnaBridge | 171:3a7713b1edbc | 145 | * @brief Get the DMA Channel pending flags. |
AnnaBridge | 171:3a7713b1edbc | 146 | * @param __HANDLE__: DMA handle |
AnnaBridge | 171:3a7713b1edbc | 147 | * @param __FLAG__: Get the specified flag. |
AnnaBridge | 171:3a7713b1edbc | 148 | * This parameter can be any combination of the following values: |
AnnaBridge | 171:3a7713b1edbc | 149 | * @arg DMA_FLAG_TCx: Transfer complete flag |
AnnaBridge | 171:3a7713b1edbc | 150 | * @arg DMA_FLAG_HTx: Half transfer complete flag |
AnnaBridge | 171:3a7713b1edbc | 151 | * @arg DMA_FLAG_TEx: Transfer error flag |
AnnaBridge | 171:3a7713b1edbc | 152 | * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag. |
AnnaBridge | 171:3a7713b1edbc | 153 | * @retval The state of FLAG (SET or RESET). |
AnnaBridge | 171:3a7713b1edbc | 154 | */ |
AnnaBridge | 171:3a7713b1edbc | 155 | #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ |
AnnaBridge | 171:3a7713b1edbc | 156 | (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\ |
AnnaBridge | 171:3a7713b1edbc | 157 | (DMA1->ISR & (__FLAG__))) |
AnnaBridge | 171:3a7713b1edbc | 158 | |
AnnaBridge | 171:3a7713b1edbc | 159 | /** |
AnnaBridge | 171:3a7713b1edbc | 160 | * @brief Clears the DMA Channel pending flags. |
AnnaBridge | 171:3a7713b1edbc | 161 | * @param __HANDLE__: DMA handle |
AnnaBridge | 171:3a7713b1edbc | 162 | * @param __FLAG__: specifies the flag to clear. |
AnnaBridge | 171:3a7713b1edbc | 163 | * This parameter can be any combination of the following values: |
AnnaBridge | 171:3a7713b1edbc | 164 | * @arg DMA_FLAG_TCx: Transfer complete flag |
AnnaBridge | 171:3a7713b1edbc | 165 | * @arg DMA_FLAG_HTx: Half transfer complete flag |
AnnaBridge | 171:3a7713b1edbc | 166 | * @arg DMA_FLAG_TEx: Transfer error flag |
AnnaBridge | 171:3a7713b1edbc | 167 | * Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag. |
AnnaBridge | 171:3a7713b1edbc | 168 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 169 | */ |
AnnaBridge | 171:3a7713b1edbc | 170 | #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ |
AnnaBridge | 171:3a7713b1edbc | 171 | (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\ |
AnnaBridge | 171:3a7713b1edbc | 172 | (DMA1->IFCR = (__FLAG__))) |
AnnaBridge | 171:3a7713b1edbc | 173 | |
AnnaBridge | 171:3a7713b1edbc | 174 | /** |
AnnaBridge | 171:3a7713b1edbc | 175 | * @} |
AnnaBridge | 171:3a7713b1edbc | 176 | */ |
AnnaBridge | 171:3a7713b1edbc | 177 | |
AnnaBridge | 171:3a7713b1edbc | 178 | #else |
AnnaBridge | 171:3a7713b1edbc | 179 | /** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices |
AnnaBridge | 171:3a7713b1edbc | 180 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 181 | */ |
AnnaBridge | 171:3a7713b1edbc | 182 | |
AnnaBridge | 171:3a7713b1edbc | 183 | /** |
AnnaBridge | 171:3a7713b1edbc | 184 | * @brief Returns the current DMA Channel transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 185 | * @param __HANDLE__: DMA handle |
AnnaBridge | 171:3a7713b1edbc | 186 | * @retval The specified transfer complete flag index. |
AnnaBridge | 171:3a7713b1edbc | 187 | */ |
AnnaBridge | 171:3a7713b1edbc | 188 | #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ |
AnnaBridge | 171:3a7713b1edbc | 189 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ |
AnnaBridge | 171:3a7713b1edbc | 190 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ |
AnnaBridge | 171:3a7713b1edbc | 191 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ |
AnnaBridge | 171:3a7713b1edbc | 192 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ |
AnnaBridge | 171:3a7713b1edbc | 193 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ |
AnnaBridge | 171:3a7713b1edbc | 194 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ |
AnnaBridge | 171:3a7713b1edbc | 195 | DMA_FLAG_TC7) |
AnnaBridge | 171:3a7713b1edbc | 196 | |
AnnaBridge | 171:3a7713b1edbc | 197 | /** |
AnnaBridge | 171:3a7713b1edbc | 198 | * @brief Return the current DMA Channel half transfer complete flag. |
AnnaBridge | 171:3a7713b1edbc | 199 | * @param __HANDLE__: DMA handle |
AnnaBridge | 171:3a7713b1edbc | 200 | * @retval The specified half transfer complete flag index. |
AnnaBridge | 171:3a7713b1edbc | 201 | */ |
AnnaBridge | 171:3a7713b1edbc | 202 | #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ |
AnnaBridge | 171:3a7713b1edbc | 203 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ |
AnnaBridge | 171:3a7713b1edbc | 204 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ |
AnnaBridge | 171:3a7713b1edbc | 205 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ |
AnnaBridge | 171:3a7713b1edbc | 206 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ |
AnnaBridge | 171:3a7713b1edbc | 207 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ |
AnnaBridge | 171:3a7713b1edbc | 208 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ |
AnnaBridge | 171:3a7713b1edbc | 209 | DMA_FLAG_HT7) |
AnnaBridge | 171:3a7713b1edbc | 210 | |
AnnaBridge | 171:3a7713b1edbc | 211 | /** |
AnnaBridge | 171:3a7713b1edbc | 212 | * @brief Return the current DMA Channel transfer error flag. |
AnnaBridge | 171:3a7713b1edbc | 213 | * @param __HANDLE__: DMA handle |
AnnaBridge | 171:3a7713b1edbc | 214 | * @retval The specified transfer error flag index. |
AnnaBridge | 171:3a7713b1edbc | 215 | */ |
AnnaBridge | 171:3a7713b1edbc | 216 | #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ |
AnnaBridge | 171:3a7713b1edbc | 217 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ |
AnnaBridge | 171:3a7713b1edbc | 218 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ |
AnnaBridge | 171:3a7713b1edbc | 219 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ |
AnnaBridge | 171:3a7713b1edbc | 220 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ |
AnnaBridge | 171:3a7713b1edbc | 221 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ |
AnnaBridge | 171:3a7713b1edbc | 222 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ |
AnnaBridge | 171:3a7713b1edbc | 223 | DMA_FLAG_TE7) |
AnnaBridge | 171:3a7713b1edbc | 224 | |
AnnaBridge | 171:3a7713b1edbc | 225 | /** |
AnnaBridge | 171:3a7713b1edbc | 226 | * @brief Return the current DMA Channel Global interrupt flag. |
AnnaBridge | 171:3a7713b1edbc | 227 | * @param __HANDLE__: DMA handle |
AnnaBridge | 171:3a7713b1edbc | 228 | * @retval The specified transfer error flag index. |
AnnaBridge | 171:3a7713b1edbc | 229 | */ |
AnnaBridge | 171:3a7713b1edbc | 230 | #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ |
AnnaBridge | 171:3a7713b1edbc | 231 | (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\ |
AnnaBridge | 171:3a7713b1edbc | 232 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\ |
AnnaBridge | 171:3a7713b1edbc | 233 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\ |
AnnaBridge | 171:3a7713b1edbc | 234 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\ |
AnnaBridge | 171:3a7713b1edbc | 235 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\ |
AnnaBridge | 171:3a7713b1edbc | 236 | ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\ |
AnnaBridge | 171:3a7713b1edbc | 237 | DMA_FLAG_GL7) |
AnnaBridge | 171:3a7713b1edbc | 238 | |
AnnaBridge | 171:3a7713b1edbc | 239 | /** |
AnnaBridge | 171:3a7713b1edbc | 240 | * @brief Get the DMA Channel pending flags. |
AnnaBridge | 171:3a7713b1edbc | 241 | * @param __HANDLE__: DMA handle |
AnnaBridge | 171:3a7713b1edbc | 242 | * @param __FLAG__: Get the specified flag. |
AnnaBridge | 171:3a7713b1edbc | 243 | * This parameter can be any combination of the following values: |
AnnaBridge | 171:3a7713b1edbc | 244 | * @arg DMA_FLAG_TCx: Transfer complete flag |
AnnaBridge | 171:3a7713b1edbc | 245 | * @arg DMA_FLAG_HTx: Half transfer complete flag |
AnnaBridge | 171:3a7713b1edbc | 246 | * @arg DMA_FLAG_TEx: Transfer error flag |
AnnaBridge | 171:3a7713b1edbc | 247 | * @arg DMA_FLAG_GLx: Global interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 248 | * Where x can be 1_7 to select the DMA Channel flag. |
AnnaBridge | 171:3a7713b1edbc | 249 | * @retval The state of FLAG (SET or RESET). |
AnnaBridge | 171:3a7713b1edbc | 250 | */ |
AnnaBridge | 171:3a7713b1edbc | 251 | |
AnnaBridge | 171:3a7713b1edbc | 252 | #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) |
AnnaBridge | 171:3a7713b1edbc | 253 | |
AnnaBridge | 171:3a7713b1edbc | 254 | /** |
AnnaBridge | 171:3a7713b1edbc | 255 | * @brief Clear the DMA Channel pending flags. |
AnnaBridge | 171:3a7713b1edbc | 256 | * @param __HANDLE__: DMA handle |
AnnaBridge | 171:3a7713b1edbc | 257 | * @param __FLAG__: specifies the flag to clear. |
AnnaBridge | 171:3a7713b1edbc | 258 | * This parameter can be any combination of the following values: |
AnnaBridge | 171:3a7713b1edbc | 259 | * @arg DMA_FLAG_TCx: Transfer complete flag |
AnnaBridge | 171:3a7713b1edbc | 260 | * @arg DMA_FLAG_HTx: Half transfer complete flag |
AnnaBridge | 171:3a7713b1edbc | 261 | * @arg DMA_FLAG_TEx: Transfer error flag |
AnnaBridge | 171:3a7713b1edbc | 262 | * @arg DMA_FLAG_GLx: Global interrupt flag |
AnnaBridge | 171:3a7713b1edbc | 263 | * Where x can be 1_7 to select the DMA Channel flag. |
AnnaBridge | 171:3a7713b1edbc | 264 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 265 | */ |
AnnaBridge | 171:3a7713b1edbc | 266 | #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) |
AnnaBridge | 171:3a7713b1edbc | 267 | |
AnnaBridge | 171:3a7713b1edbc | 268 | /** |
AnnaBridge | 171:3a7713b1edbc | 269 | * @} |
AnnaBridge | 171:3a7713b1edbc | 270 | */ |
AnnaBridge | 171:3a7713b1edbc | 271 | |
AnnaBridge | 171:3a7713b1edbc | 272 | #endif |
AnnaBridge | 171:3a7713b1edbc | 273 | |
AnnaBridge | 171:3a7713b1edbc | 274 | /** |
AnnaBridge | 171:3a7713b1edbc | 275 | * @} |
AnnaBridge | 171:3a7713b1edbc | 276 | */ |
AnnaBridge | 171:3a7713b1edbc | 277 | |
AnnaBridge | 171:3a7713b1edbc | 278 | /** |
AnnaBridge | 171:3a7713b1edbc | 279 | * @} |
AnnaBridge | 171:3a7713b1edbc | 280 | */ |
AnnaBridge | 171:3a7713b1edbc | 281 | |
AnnaBridge | 171:3a7713b1edbc | 282 | /** |
AnnaBridge | 171:3a7713b1edbc | 283 | * @} |
AnnaBridge | 171:3a7713b1edbc | 284 | */ |
AnnaBridge | 171:3a7713b1edbc | 285 | |
AnnaBridge | 171:3a7713b1edbc | 286 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 287 | } |
AnnaBridge | 171:3a7713b1edbc | 288 | #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || */ |
AnnaBridge | 171:3a7713b1edbc | 289 | /* STM32F103xG || STM32F105xC || STM32F107xC */ |
AnnaBridge | 171:3a7713b1edbc | 290 | |
AnnaBridge | 171:3a7713b1edbc | 291 | #endif /* __STM32F1xx_HAL_DMA_H */ |
AnnaBridge | 171:3a7713b1edbc | 292 | |
AnnaBridge | 171:3a7713b1edbc | 293 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |