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TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f1xx_hal_rcc_ex.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	171:3a7713b1edbc	1	/**
AnnaBridge	171:3a7713b1edbc	2	******************************************************************************
AnnaBridge	171:3a7713b1edbc	3	* @file stm32f1xx_hal_rcc_ex.h
AnnaBridge	171:3a7713b1edbc	4	* @author MCD Application Team
AnnaBridge	171:3a7713b1edbc	5	* @brief Header file of RCC HAL Extension module.
AnnaBridge	171:3a7713b1edbc	6	******************************************************************************
AnnaBridge	171:3a7713b1edbc	7	* @attention
AnnaBridge	171:3a7713b1edbc	8	*
AnnaBridge	171:3a7713b1edbc	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	171:3a7713b1edbc	10	*
AnnaBridge	171:3a7713b1edbc	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	171:3a7713b1edbc	12	* are permitted provided that the following conditions are met:
AnnaBridge	171:3a7713b1edbc	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	171:3a7713b1edbc	14	* this list of conditions and the following disclaimer.
AnnaBridge	171:3a7713b1edbc	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	171:3a7713b1edbc	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	171:3a7713b1edbc	17	* and/or other materials provided with the distribution.
AnnaBridge	171:3a7713b1edbc	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	171:3a7713b1edbc	19	* may be used to endorse or promote products derived from this software
AnnaBridge	171:3a7713b1edbc	20	* without specific prior written permission.
AnnaBridge	171:3a7713b1edbc	21	*
AnnaBridge	171:3a7713b1edbc	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	171:3a7713b1edbc	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	171:3a7713b1edbc	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	171:3a7713b1edbc	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	171:3a7713b1edbc	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	171:3a7713b1edbc	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	171:3a7713b1edbc	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	171:3a7713b1edbc	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	171:3a7713b1edbc	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	171:3a7713b1edbc	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	171:3a7713b1edbc	32	*
AnnaBridge	171:3a7713b1edbc	33	******************************************************************************
AnnaBridge	171:3a7713b1edbc	34	*/
AnnaBridge	171:3a7713b1edbc	35
AnnaBridge	171:3a7713b1edbc	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	171:3a7713b1edbc	37	#ifndef __STM32F1xx_HAL_RCC_EX_H
AnnaBridge	171:3a7713b1edbc	38	#define __STM32F1xx_HAL_RCC_EX_H
AnnaBridge	171:3a7713b1edbc	39
AnnaBridge	171:3a7713b1edbc	40	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	41	extern "C" {
AnnaBridge	171:3a7713b1edbc	42	#endif
AnnaBridge	171:3a7713b1edbc	43
AnnaBridge	171:3a7713b1edbc	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	45	#include "stm32f1xx_hal_def.h"
AnnaBridge	171:3a7713b1edbc	46
AnnaBridge	171:3a7713b1edbc	47	/** @addtogroup STM32F1xx_HAL_Driver
AnnaBridge	171:3a7713b1edbc	48	* @{
AnnaBridge	171:3a7713b1edbc	49	*/
AnnaBridge	171:3a7713b1edbc	50
AnnaBridge	171:3a7713b1edbc	51	/** @addtogroup RCCEx
AnnaBridge	171:3a7713b1edbc	52	* @{
AnnaBridge	171:3a7713b1edbc	53	*/
AnnaBridge	171:3a7713b1edbc	54
AnnaBridge	171:3a7713b1edbc	55	/** @addtogroup RCCEx_Private_Constants
AnnaBridge	171:3a7713b1edbc	56	* @{
AnnaBridge	171:3a7713b1edbc	57	*/
AnnaBridge	171:3a7713b1edbc	58
AnnaBridge	171:3a7713b1edbc	59	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	60
AnnaBridge	171:3a7713b1edbc	61	/* Alias word address of PLLI2SON bit */
AnnaBridge	171:3a7713b1edbc	62	#define PLLI2SON_BITNUMBER RCC_CR_PLL3ON_Pos
AnnaBridge	171:3a7713b1edbc	63	#define RCC_CR_PLLI2SON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLLI2SON_BITNUMBER * 4U)))
AnnaBridge	171:3a7713b1edbc	64	/* Alias word address of PLL2ON bit */
AnnaBridge	171:3a7713b1edbc	65	#define PLL2ON_BITNUMBER RCC_CR_PLL2ON_Pos
AnnaBridge	171:3a7713b1edbc	66	#define RCC_CR_PLL2ON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (PLL2ON_BITNUMBER * 4U)))
AnnaBridge	171:3a7713b1edbc	67
AnnaBridge	171:3a7713b1edbc	68	#define PLLI2S_TIMEOUT_VALUE 100U /* 100 ms */
AnnaBridge	171:3a7713b1edbc	69	#define PLL2_TIMEOUT_VALUE 100U /* 100 ms */
AnnaBridge	171:3a7713b1edbc	70
AnnaBridge	171:3a7713b1edbc	71	#endif /* STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	72
AnnaBridge	171:3a7713b1edbc	73
AnnaBridge	171:3a7713b1edbc	74	#define CR_REG_INDEX ((uint8_t)1)
AnnaBridge	171:3a7713b1edbc	75
AnnaBridge	171:3a7713b1edbc	76	/**
AnnaBridge	171:3a7713b1edbc	77	* @}
AnnaBridge	171:3a7713b1edbc	78	*/
AnnaBridge	171:3a7713b1edbc	79
AnnaBridge	171:3a7713b1edbc	80	/** @addtogroup RCCEx_Private_Macros
AnnaBridge	171:3a7713b1edbc	81	* @{
AnnaBridge	171:3a7713b1edbc	82	*/
AnnaBridge	171:3a7713b1edbc	83
AnnaBridge	171:3a7713b1edbc	84	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	85	#define IS_RCC_PREDIV1_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_PREDIV1_SOURCE_HSE) \|\| \
AnnaBridge	171:3a7713b1edbc	86	((__SOURCE__) == RCC_PREDIV1_SOURCE_PLL2))
AnnaBridge	171:3a7713b1edbc	87	#endif /* STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	88
AnnaBridge	171:3a7713b1edbc	89	#if defined(STM32F105xC) \|\| defined(STM32F107xC) \|\| defined(STM32F100xB)\
AnnaBridge	171:3a7713b1edbc	90	\|\| defined(STM32F100xE)
AnnaBridge	171:3a7713b1edbc	91	#define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) \|\| ((__DIV__) == RCC_HSE_PREDIV_DIV2) \|\| \
AnnaBridge	171:3a7713b1edbc	92	((__DIV__) == RCC_HSE_PREDIV_DIV3) \|\| ((__DIV__) == RCC_HSE_PREDIV_DIV4) \|\| \
AnnaBridge	171:3a7713b1edbc	93	((__DIV__) == RCC_HSE_PREDIV_DIV5) \|\| ((__DIV__) == RCC_HSE_PREDIV_DIV6) \|\| \
AnnaBridge	171:3a7713b1edbc	94	((__DIV__) == RCC_HSE_PREDIV_DIV7) \|\| ((__DIV__) == RCC_HSE_PREDIV_DIV8) \|\| \
AnnaBridge	171:3a7713b1edbc	95	((__DIV__) == RCC_HSE_PREDIV_DIV9) \|\| ((__DIV__) == RCC_HSE_PREDIV_DIV10) \|\| \
AnnaBridge	171:3a7713b1edbc	96	((__DIV__) == RCC_HSE_PREDIV_DIV11) \|\| ((__DIV__) == RCC_HSE_PREDIV_DIV12) \|\| \
AnnaBridge	171:3a7713b1edbc	97	((__DIV__) == RCC_HSE_PREDIV_DIV13) \|\| ((__DIV__) == RCC_HSE_PREDIV_DIV14) \|\| \
AnnaBridge	171:3a7713b1edbc	98	((__DIV__) == RCC_HSE_PREDIV_DIV15) \|\| ((__DIV__) == RCC_HSE_PREDIV_DIV16))
AnnaBridge	171:3a7713b1edbc	99
AnnaBridge	171:3a7713b1edbc	100	#else
AnnaBridge	171:3a7713b1edbc	101	#define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) \|\| ((__DIV__) == RCC_HSE_PREDIV_DIV2))
AnnaBridge	171:3a7713b1edbc	102	#endif /* STM32F105xC \|\| STM32F107xC \|\| STM32F100xB \|\| STM32F100xE */
AnnaBridge	171:3a7713b1edbc	103
AnnaBridge	171:3a7713b1edbc	104	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	105	#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL4) \|\| ((__MUL__) == RCC_PLL_MUL5) \|\| \
AnnaBridge	171:3a7713b1edbc	106	((__MUL__) == RCC_PLL_MUL6) \|\| ((__MUL__) == RCC_PLL_MUL7) \|\| \
AnnaBridge	171:3a7713b1edbc	107	((__MUL__) == RCC_PLL_MUL8) \|\| ((__MUL__) == RCC_PLL_MUL9) \|\| \
AnnaBridge	171:3a7713b1edbc	108	((__MUL__) == RCC_PLL_MUL6_5))
AnnaBridge	171:3a7713b1edbc	109
AnnaBridge	171:3a7713b1edbc	110	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \
AnnaBridge	171:3a7713b1edbc	111	\|\| ((__SOURCE__) == RCC_MCO1SOURCE_HSE) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \
AnnaBridge	171:3a7713b1edbc	112	\|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLL2CLK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK) \
AnnaBridge	171:3a7713b1edbc	113	\|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK_DIV2) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_EXT_HSE) \
AnnaBridge	171:3a7713b1edbc	114	\|\| ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
AnnaBridge	171:3a7713b1edbc	115
AnnaBridge	171:3a7713b1edbc	116	#else
AnnaBridge	171:3a7713b1edbc	117	#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) \|\| ((__MUL__) == RCC_PLL_MUL3) \|\| \
AnnaBridge	171:3a7713b1edbc	118	((__MUL__) == RCC_PLL_MUL4) \|\| ((__MUL__) == RCC_PLL_MUL5) \|\| \
AnnaBridge	171:3a7713b1edbc	119	((__MUL__) == RCC_PLL_MUL6) \|\| ((__MUL__) == RCC_PLL_MUL7) \|\| \
AnnaBridge	171:3a7713b1edbc	120	((__MUL__) == RCC_PLL_MUL8) \|\| ((__MUL__) == RCC_PLL_MUL9) \|\| \
AnnaBridge	171:3a7713b1edbc	121	((__MUL__) == RCC_PLL_MUL10) \|\| ((__MUL__) == RCC_PLL_MUL11) \|\| \
AnnaBridge	171:3a7713b1edbc	122	((__MUL__) == RCC_PLL_MUL12) \|\| ((__MUL__) == RCC_PLL_MUL13) \|\| \
AnnaBridge	171:3a7713b1edbc	123	((__MUL__) == RCC_PLL_MUL14) \|\| ((__MUL__) == RCC_PLL_MUL15) \|\| \
AnnaBridge	171:3a7713b1edbc	124	((__MUL__) == RCC_PLL_MUL16))
AnnaBridge	171:3a7713b1edbc	125
AnnaBridge	171:3a7713b1edbc	126	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \
AnnaBridge	171:3a7713b1edbc	127	\|\| ((__SOURCE__) == RCC_MCO1SOURCE_HSE) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \
AnnaBridge	171:3a7713b1edbc	128	\|\| ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
AnnaBridge	171:3a7713b1edbc	129
AnnaBridge	171:3a7713b1edbc	130	#endif /* STM32F105xC \|\| STM32F107xC*/
AnnaBridge	171:3a7713b1edbc	131
AnnaBridge	171:3a7713b1edbc	132	#define IS_RCC_ADCPLLCLK_DIV(__ADCCLK__) (((__ADCCLK__) == RCC_ADCPCLK2_DIV2) \|\| ((__ADCCLK__) == RCC_ADCPCLK2_DIV4) \|\| \
AnnaBridge	171:3a7713b1edbc	133	((__ADCCLK__) == RCC_ADCPCLK2_DIV6) \|\| ((__ADCCLK__) == RCC_ADCPCLK2_DIV8))
AnnaBridge	171:3a7713b1edbc	134
AnnaBridge	171:3a7713b1edbc	135	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	136	#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) \|\| ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLLI2S_VCO))
AnnaBridge	171:3a7713b1edbc	137
AnnaBridge	171:3a7713b1edbc	138	#define IS_RCC_I2S3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) \|\| ((__SOURCE__) == RCC_I2S3CLKSOURCE_PLLI2S_VCO))
AnnaBridge	171:3a7713b1edbc	139
AnnaBridge	171:3a7713b1edbc	140	#define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV2) \|\| ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV3))
AnnaBridge	171:3a7713b1edbc	141
AnnaBridge	171:3a7713b1edbc	142	#define IS_RCC_PLLI2S_MUL(__MUL__) (((__MUL__) == RCC_PLLI2S_MUL8) \|\| ((__MUL__) == RCC_PLLI2S_MUL9) \|\| \
AnnaBridge	171:3a7713b1edbc	143	((__MUL__) == RCC_PLLI2S_MUL10) \|\| ((__MUL__) == RCC_PLLI2S_MUL11) \|\| \
AnnaBridge	171:3a7713b1edbc	144	((__MUL__) == RCC_PLLI2S_MUL12) \|\| ((__MUL__) == RCC_PLLI2S_MUL13) \|\| \
AnnaBridge	171:3a7713b1edbc	145	((__MUL__) == RCC_PLLI2S_MUL14) \|\| ((__MUL__) == RCC_PLLI2S_MUL16) \|\| \
AnnaBridge	171:3a7713b1edbc	146	((__MUL__) == RCC_PLLI2S_MUL20))
AnnaBridge	171:3a7713b1edbc	147
AnnaBridge	171:3a7713b1edbc	148	#define IS_RCC_HSE_PREDIV2(__DIV__) (((__DIV__) == RCC_HSE_PREDIV2_DIV1) \|\| ((__DIV__) == RCC_HSE_PREDIV2_DIV2) \|\| \
AnnaBridge	171:3a7713b1edbc	149	((__DIV__) == RCC_HSE_PREDIV2_DIV3) \|\| ((__DIV__) == RCC_HSE_PREDIV2_DIV4) \|\| \
AnnaBridge	171:3a7713b1edbc	150	((__DIV__) == RCC_HSE_PREDIV2_DIV5) \|\| ((__DIV__) == RCC_HSE_PREDIV2_DIV6) \|\| \
AnnaBridge	171:3a7713b1edbc	151	((__DIV__) == RCC_HSE_PREDIV2_DIV7) \|\| ((__DIV__) == RCC_HSE_PREDIV2_DIV8) \|\| \
AnnaBridge	171:3a7713b1edbc	152	((__DIV__) == RCC_HSE_PREDIV2_DIV9) \|\| ((__DIV__) == RCC_HSE_PREDIV2_DIV10) \|\| \
AnnaBridge	171:3a7713b1edbc	153	((__DIV__) == RCC_HSE_PREDIV2_DIV11) \|\| ((__DIV__) == RCC_HSE_PREDIV2_DIV12) \|\| \
AnnaBridge	171:3a7713b1edbc	154	((__DIV__) == RCC_HSE_PREDIV2_DIV13) \|\| ((__DIV__) == RCC_HSE_PREDIV2_DIV14) \|\| \
AnnaBridge	171:3a7713b1edbc	155	((__DIV__) == RCC_HSE_PREDIV2_DIV15) \|\| ((__DIV__) == RCC_HSE_PREDIV2_DIV16))
AnnaBridge	171:3a7713b1edbc	156
AnnaBridge	171:3a7713b1edbc	157	#define IS_RCC_PLL2(__PLL__) (((__PLL__) == RCC_PLL2_NONE) \|\| ((__PLL__) == RCC_PLL2_OFF) \|\| \
AnnaBridge	171:3a7713b1edbc	158	((__PLL__) == RCC_PLL2_ON))
AnnaBridge	171:3a7713b1edbc	159
AnnaBridge	171:3a7713b1edbc	160	#define IS_RCC_PLL2_MUL(__MUL__) (((__MUL__) == RCC_PLL2_MUL8) \|\| ((__MUL__) == RCC_PLL2_MUL9) \|\| \
AnnaBridge	171:3a7713b1edbc	161	((__MUL__) == RCC_PLL2_MUL10) \|\| ((__MUL__) == RCC_PLL2_MUL11) \|\| \
AnnaBridge	171:3a7713b1edbc	162	((__MUL__) == RCC_PLL2_MUL12) \|\| ((__MUL__) == RCC_PLL2_MUL13) \|\| \
AnnaBridge	171:3a7713b1edbc	163	((__MUL__) == RCC_PLL2_MUL14) \|\| ((__MUL__) == RCC_PLL2_MUL16) \|\| \
AnnaBridge	171:3a7713b1edbc	164	((__MUL__) == RCC_PLL2_MUL20))
AnnaBridge	171:3a7713b1edbc	165
AnnaBridge	171:3a7713b1edbc	166	#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
AnnaBridge	171:3a7713b1edbc	167	((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) \|\| \
AnnaBridge	171:3a7713b1edbc	168	(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) \|\| \
AnnaBridge	171:3a7713b1edbc	169	(((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) \|\| \
AnnaBridge	171:3a7713b1edbc	170	(((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) \|\| \
AnnaBridge	171:3a7713b1edbc	171	(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
AnnaBridge	171:3a7713b1edbc	172
AnnaBridge	171:3a7713b1edbc	173	#elif defined(STM32F103xE) \|\| defined(STM32F103xG)
AnnaBridge	171:3a7713b1edbc	174
AnnaBridge	171:3a7713b1edbc	175	#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK)
AnnaBridge	171:3a7713b1edbc	176
AnnaBridge	171:3a7713b1edbc	177	#define IS_RCC_I2S3CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK)
AnnaBridge	171:3a7713b1edbc	178
AnnaBridge	171:3a7713b1edbc	179	#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
AnnaBridge	171:3a7713b1edbc	180	((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) \|\| \
AnnaBridge	171:3a7713b1edbc	181	(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) \|\| \
AnnaBridge	171:3a7713b1edbc	182	(((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) \|\| \
AnnaBridge	171:3a7713b1edbc	183	(((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) \|\| \
AnnaBridge	171:3a7713b1edbc	184	(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
AnnaBridge	171:3a7713b1edbc	185
AnnaBridge	171:3a7713b1edbc	186
AnnaBridge	171:3a7713b1edbc	187	#elif defined(STM32F102x6) \|\| defined(STM32F102xB) \|\| defined(STM32F103x6)\
AnnaBridge	171:3a7713b1edbc	188	\|\| defined(STM32F103xB)
AnnaBridge	171:3a7713b1edbc	189
AnnaBridge	171:3a7713b1edbc	190	#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
AnnaBridge	171:3a7713b1edbc	191	((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) \|\| \
AnnaBridge	171:3a7713b1edbc	192	(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) \|\| \
AnnaBridge	171:3a7713b1edbc	193	(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
AnnaBridge	171:3a7713b1edbc	194
AnnaBridge	171:3a7713b1edbc	195	#else
AnnaBridge	171:3a7713b1edbc	196
AnnaBridge	171:3a7713b1edbc	197	#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
AnnaBridge	171:3a7713b1edbc	198	((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) \|\| \
AnnaBridge	171:3a7713b1edbc	199	(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC))
AnnaBridge	171:3a7713b1edbc	200
AnnaBridge	171:3a7713b1edbc	201	#endif /* STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	202
AnnaBridge	171:3a7713b1edbc	203	#if defined(STM32F102x6) \|\| defined(STM32F102xB) \|\| defined(STM32F103x6)\
AnnaBridge	171:3a7713b1edbc	204	\|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG)
AnnaBridge	171:3a7713b1edbc	205
AnnaBridge	171:3a7713b1edbc	206	#define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL) \|\| ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV1_5))
AnnaBridge	171:3a7713b1edbc	207
AnnaBridge	171:3a7713b1edbc	208	#endif /* STM32F102x6 \|\| STM32F102xB \|\| STM32F103x6 \|\| STM32F103xB \|\| STM32F103xE \|\| STM32F103xG */
AnnaBridge	171:3a7713b1edbc	209
AnnaBridge	171:3a7713b1edbc	210	/**
AnnaBridge	171:3a7713b1edbc	211	* @}
AnnaBridge	171:3a7713b1edbc	212	*/
AnnaBridge	171:3a7713b1edbc	213
AnnaBridge	171:3a7713b1edbc	214	/* Exported types ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	215
AnnaBridge	171:3a7713b1edbc	216	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
AnnaBridge	171:3a7713b1edbc	217	* @{
AnnaBridge	171:3a7713b1edbc	218	*/
AnnaBridge	171:3a7713b1edbc	219
AnnaBridge	171:3a7713b1edbc	220	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	221	/**
AnnaBridge	171:3a7713b1edbc	222	* @brief RCC PLL2 configuration structure definition
AnnaBridge	171:3a7713b1edbc	223	*/
AnnaBridge	171:3a7713b1edbc	224	typedef struct
AnnaBridge	171:3a7713b1edbc	225	{
AnnaBridge	171:3a7713b1edbc	226	uint32_t PLL2State; /*!< The new state of the PLL2.
AnnaBridge	171:3a7713b1edbc	227	This parameter can be a value of @ref RCCEx_PLL2_Config */
AnnaBridge	171:3a7713b1edbc	228
AnnaBridge	171:3a7713b1edbc	229	uint32_t PLL2MUL; /*!< PLL2MUL: Multiplication factor for PLL2 VCO input clock
AnnaBridge	171:3a7713b1edbc	230	This parameter must be a value of @ref RCCEx_PLL2_Multiplication_Factor*/
AnnaBridge	171:3a7713b1edbc	231
AnnaBridge	171:3a7713b1edbc	232	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	233	uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value.
AnnaBridge	171:3a7713b1edbc	234	This parameter can be a value of @ref RCCEx_Prediv2_Factor */
AnnaBridge	171:3a7713b1edbc	235
AnnaBridge	171:3a7713b1edbc	236	#endif /* STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	237	} RCC_PLL2InitTypeDef;
AnnaBridge	171:3a7713b1edbc	238
AnnaBridge	171:3a7713b1edbc	239	#endif /* STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	240
AnnaBridge	171:3a7713b1edbc	241	/**
AnnaBridge	171:3a7713b1edbc	242	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
AnnaBridge	171:3a7713b1edbc	243	*/
AnnaBridge	171:3a7713b1edbc	244	typedef struct
AnnaBridge	171:3a7713b1edbc	245	{
AnnaBridge	171:3a7713b1edbc	246	uint32_t OscillatorType; /*!< The oscillators to be configured.
AnnaBridge	171:3a7713b1edbc	247	This parameter can be a value of @ref RCC_Oscillator_Type */
AnnaBridge	171:3a7713b1edbc	248
AnnaBridge	171:3a7713b1edbc	249	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	250	uint32_t Prediv1Source; /*!< The Prediv1 source value.
AnnaBridge	171:3a7713b1edbc	251	This parameter can be a value of @ref RCCEx_Prediv1_Source */
AnnaBridge	171:3a7713b1edbc	252	#endif /* STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	253
AnnaBridge	171:3a7713b1edbc	254	uint32_t HSEState; /*!< The new state of the HSE.
AnnaBridge	171:3a7713b1edbc	255	This parameter can be a value of @ref RCC_HSE_Config */
AnnaBridge	171:3a7713b1edbc	256
AnnaBridge	171:3a7713b1edbc	257	uint32_t HSEPredivValue; /*!< The Prediv1 factor value (named PREDIV1 or PLLXTPRE in RM)
AnnaBridge	171:3a7713b1edbc	258	This parameter can be a value of @ref RCCEx_Prediv1_Factor */
AnnaBridge	171:3a7713b1edbc	259
AnnaBridge	171:3a7713b1edbc	260	uint32_t LSEState; /*!< The new state of the LSE.
AnnaBridge	171:3a7713b1edbc	261	This parameter can be a value of @ref RCC_LSE_Config */
AnnaBridge	171:3a7713b1edbc	262
AnnaBridge	171:3a7713b1edbc	263	uint32_t HSIState; /*!< The new state of the HSI.
AnnaBridge	171:3a7713b1edbc	264	This parameter can be a value of @ref RCC_HSI_Config */
AnnaBridge	171:3a7713b1edbc	265
AnnaBridge	171:3a7713b1edbc	266	uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
AnnaBridge	171:3a7713b1edbc	267	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
AnnaBridge	171:3a7713b1edbc	268
AnnaBridge	171:3a7713b1edbc	269	uint32_t LSIState; /*!< The new state of the LSI.
AnnaBridge	171:3a7713b1edbc	270	This parameter can be a value of @ref RCC_LSI_Config */
AnnaBridge	171:3a7713b1edbc	271
AnnaBridge	171:3a7713b1edbc	272	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
AnnaBridge	171:3a7713b1edbc	273
AnnaBridge	171:3a7713b1edbc	274	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	275	RCC_PLL2InitTypeDef PLL2; /!< PLL2 structure parameters /
AnnaBridge	171:3a7713b1edbc	276	#endif /* STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	277	} RCC_OscInitTypeDef;
AnnaBridge	171:3a7713b1edbc	278
AnnaBridge	171:3a7713b1edbc	279	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	280	/**
AnnaBridge	171:3a7713b1edbc	281	* @brief RCC PLLI2S configuration structure definition
AnnaBridge	171:3a7713b1edbc	282	*/
AnnaBridge	171:3a7713b1edbc	283	typedef struct
AnnaBridge	171:3a7713b1edbc	284	{
AnnaBridge	171:3a7713b1edbc	285	uint32_t PLLI2SMUL; /*!< PLLI2SMUL: Multiplication factor for PLLI2S VCO input clock
AnnaBridge	171:3a7713b1edbc	286	This parameter must be a value of @ref RCCEx_PLLI2S_Multiplication_Factor*/
AnnaBridge	171:3a7713b1edbc	287
AnnaBridge	171:3a7713b1edbc	288	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	289	uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value.
AnnaBridge	171:3a7713b1edbc	290	This parameter can be a value of @ref RCCEx_Prediv2_Factor */
AnnaBridge	171:3a7713b1edbc	291
AnnaBridge	171:3a7713b1edbc	292	#endif /* STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	293	} RCC_PLLI2SInitTypeDef;
AnnaBridge	171:3a7713b1edbc	294	#endif /* STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	295
AnnaBridge	171:3a7713b1edbc	296	/**
AnnaBridge	171:3a7713b1edbc	297	* @brief RCC extended clocks structure definition
AnnaBridge	171:3a7713b1edbc	298	*/
AnnaBridge	171:3a7713b1edbc	299	typedef struct
AnnaBridge	171:3a7713b1edbc	300	{
AnnaBridge	171:3a7713b1edbc	301	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
AnnaBridge	171:3a7713b1edbc	302	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
AnnaBridge	171:3a7713b1edbc	303
AnnaBridge	171:3a7713b1edbc	304	uint32_t RTCClockSelection; /*!< specifies the RTC clock source.
AnnaBridge	171:3a7713b1edbc	305	This parameter can be a value of @ref RCC_RTC_Clock_Source */
AnnaBridge	171:3a7713b1edbc	306
AnnaBridge	171:3a7713b1edbc	307	uint32_t AdcClockSelection; /*!< ADC clock source
AnnaBridge	171:3a7713b1edbc	308	This parameter can be a value of @ref RCCEx_ADC_Prescaler */
AnnaBridge	171:3a7713b1edbc	309
AnnaBridge	171:3a7713b1edbc	310	#if defined(STM32F103xE) \|\| defined(STM32F103xG) \|\| defined(STM32F105xC)\
AnnaBridge	171:3a7713b1edbc	311	\|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	312	uint32_t I2s2ClockSelection; /*!< I2S2 clock source
AnnaBridge	171:3a7713b1edbc	313	This parameter can be a value of @ref RCCEx_I2S2_Clock_Source */
AnnaBridge	171:3a7713b1edbc	314
AnnaBridge	171:3a7713b1edbc	315	uint32_t I2s3ClockSelection; /*!< I2S3 clock source
AnnaBridge	171:3a7713b1edbc	316	This parameter can be a value of @ref RCCEx_I2S3_Clock_Source */
AnnaBridge	171:3a7713b1edbc	317
AnnaBridge	171:3a7713b1edbc	318	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	319	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters
AnnaBridge	171:3a7713b1edbc	320	This parameter will be used only when PLLI2S is selected as Clock Source I2S2 or I2S3 */
AnnaBridge	171:3a7713b1edbc	321
AnnaBridge	171:3a7713b1edbc	322	#endif /* STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	323	#endif /* STM32F103xE \|\| STM32F103xG \|\| STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	324
AnnaBridge	171:3a7713b1edbc	325	#if defined(STM32F102x6) \|\| defined(STM32F102xB) \|\| defined(STM32F103x6)\
AnnaBridge	171:3a7713b1edbc	326	\|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG)\
AnnaBridge	171:3a7713b1edbc	327	\|\| defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	328	uint32_t UsbClockSelection; /*!< USB clock source
AnnaBridge	171:3a7713b1edbc	329	This parameter can be a value of @ref RCCEx_USB_Prescaler */
AnnaBridge	171:3a7713b1edbc	330
AnnaBridge	171:3a7713b1edbc	331	#endif /* STM32F102x6 \|\| STM32F102xB \|\| STM32F103x6 \|\| STM32F103xB \|\| STM32F103xE \|\| STM32F103xG \|\| STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	332	} RCC_PeriphCLKInitTypeDef;
AnnaBridge	171:3a7713b1edbc	333
AnnaBridge	171:3a7713b1edbc	334	/**
AnnaBridge	171:3a7713b1edbc	335	* @}
AnnaBridge	171:3a7713b1edbc	336	*/
AnnaBridge	171:3a7713b1edbc	337
AnnaBridge	171:3a7713b1edbc	338	/* Exported constants --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	339
AnnaBridge	171:3a7713b1edbc	340	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
AnnaBridge	171:3a7713b1edbc	341	* @{
AnnaBridge	171:3a7713b1edbc	342	*/
AnnaBridge	171:3a7713b1edbc	343
AnnaBridge	171:3a7713b1edbc	344	/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
AnnaBridge	171:3a7713b1edbc	345	* @{
AnnaBridge	171:3a7713b1edbc	346	*/
AnnaBridge	171:3a7713b1edbc	347	#define RCC_PERIPHCLK_RTC 0x00000001U
AnnaBridge	171:3a7713b1edbc	348	#define RCC_PERIPHCLK_ADC 0x00000002U
AnnaBridge	171:3a7713b1edbc	349	#if defined(STM32F103xE) \|\| defined(STM32F103xG) \|\| defined(STM32F105xC)\
AnnaBridge	171:3a7713b1edbc	350	\|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	351	#define RCC_PERIPHCLK_I2S2 0x00000004U
AnnaBridge	171:3a7713b1edbc	352	#define RCC_PERIPHCLK_I2S3 0x00000008U
AnnaBridge	171:3a7713b1edbc	353	#endif /* STM32F103xE \|\| STM32F103xG \|\| STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	354	#if defined(STM32F102x6) \|\| defined(STM32F102xB) \|\| defined(STM32F103x6)\
AnnaBridge	171:3a7713b1edbc	355	\|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG)\
AnnaBridge	171:3a7713b1edbc	356	\|\| defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	357	#define RCC_PERIPHCLK_USB 0x00000010U
AnnaBridge	171:3a7713b1edbc	358	#endif /* STM32F102x6 \|\| STM32F102xB \|\| STM32F103x6 \|\| STM32F103xB \|\| STM32F103xE \|\| STM32F103xG \|\| STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	359
AnnaBridge	171:3a7713b1edbc	360	/**
AnnaBridge	171:3a7713b1edbc	361	* @}
AnnaBridge	171:3a7713b1edbc	362	*/
AnnaBridge	171:3a7713b1edbc	363
AnnaBridge	171:3a7713b1edbc	364	/** @defgroup RCCEx_ADC_Prescaler ADC Prescaler
AnnaBridge	171:3a7713b1edbc	365	* @{
AnnaBridge	171:3a7713b1edbc	366	*/
AnnaBridge	171:3a7713b1edbc	367	#define RCC_ADCPCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2
AnnaBridge	171:3a7713b1edbc	368	#define RCC_ADCPCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4
AnnaBridge	171:3a7713b1edbc	369	#define RCC_ADCPCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6
AnnaBridge	171:3a7713b1edbc	370	#define RCC_ADCPCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8
AnnaBridge	171:3a7713b1edbc	371
AnnaBridge	171:3a7713b1edbc	372	/**
AnnaBridge	171:3a7713b1edbc	373	* @}
AnnaBridge	171:3a7713b1edbc	374	*/
AnnaBridge	171:3a7713b1edbc	375
AnnaBridge	171:3a7713b1edbc	376	#if defined(STM32F103xE) \|\| defined(STM32F103xG) \|\| defined(STM32F105xC)\
AnnaBridge	171:3a7713b1edbc	377	\|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	378	/** @defgroup RCCEx_I2S2_Clock_Source I2S2 Clock Source
AnnaBridge	171:3a7713b1edbc	379	* @{
AnnaBridge	171:3a7713b1edbc	380	*/
AnnaBridge	171:3a7713b1edbc	381	#define RCC_I2S2CLKSOURCE_SYSCLK 0x00000000U
AnnaBridge	171:3a7713b1edbc	382	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	383	#define RCC_I2S2CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S2SRC
AnnaBridge	171:3a7713b1edbc	384	#endif /* STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	385
AnnaBridge	171:3a7713b1edbc	386	/**
AnnaBridge	171:3a7713b1edbc	387	* @}
AnnaBridge	171:3a7713b1edbc	388	*/
AnnaBridge	171:3a7713b1edbc	389
AnnaBridge	171:3a7713b1edbc	390	/** @defgroup RCCEx_I2S3_Clock_Source I2S3 Clock Source
AnnaBridge	171:3a7713b1edbc	391	* @{
AnnaBridge	171:3a7713b1edbc	392	*/
AnnaBridge	171:3a7713b1edbc	393	#define RCC_I2S3CLKSOURCE_SYSCLK 0x00000000U
AnnaBridge	171:3a7713b1edbc	394	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	395	#define RCC_I2S3CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S3SRC
AnnaBridge	171:3a7713b1edbc	396	#endif /* STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	397
AnnaBridge	171:3a7713b1edbc	398	/**
AnnaBridge	171:3a7713b1edbc	399	* @}
AnnaBridge	171:3a7713b1edbc	400	*/
AnnaBridge	171:3a7713b1edbc	401
AnnaBridge	171:3a7713b1edbc	402	#endif /* STM32F103xE \|\| STM32F103xG \|\| STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	403
AnnaBridge	171:3a7713b1edbc	404	#if defined(STM32F102x6) \|\| defined(STM32F102xB) \|\| defined(STM32F103x6)\
AnnaBridge	171:3a7713b1edbc	405	\|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG)
AnnaBridge	171:3a7713b1edbc	406
AnnaBridge	171:3a7713b1edbc	407	/** @defgroup RCCEx_USB_Prescaler USB Prescaler
AnnaBridge	171:3a7713b1edbc	408	* @{
AnnaBridge	171:3a7713b1edbc	409	*/
AnnaBridge	171:3a7713b1edbc	410	#define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE
AnnaBridge	171:3a7713b1edbc	411	#define RCC_USBCLKSOURCE_PLL_DIV1_5 0x00000000U
AnnaBridge	171:3a7713b1edbc	412
AnnaBridge	171:3a7713b1edbc	413	/**
AnnaBridge	171:3a7713b1edbc	414	* @}
AnnaBridge	171:3a7713b1edbc	415	*/
AnnaBridge	171:3a7713b1edbc	416
AnnaBridge	171:3a7713b1edbc	417	#endif /* STM32F102x6 \|\| STM32F102xB \|\| STM32F103x6 \|\| STM32F103xB \|\| STM32F103xE \|\| STM32F103xG */
AnnaBridge	171:3a7713b1edbc	418
AnnaBridge	171:3a7713b1edbc	419
AnnaBridge	171:3a7713b1edbc	420	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	421	/** @defgroup RCCEx_USB_Prescaler USB Prescaler
AnnaBridge	171:3a7713b1edbc	422	* @{
AnnaBridge	171:3a7713b1edbc	423	*/
AnnaBridge	171:3a7713b1edbc	424	#define RCC_USBCLKSOURCE_PLL_DIV2 RCC_CFGR_OTGFSPRE
AnnaBridge	171:3a7713b1edbc	425	#define RCC_USBCLKSOURCE_PLL_DIV3 0x00000000U
AnnaBridge	171:3a7713b1edbc	426
AnnaBridge	171:3a7713b1edbc	427	/**
AnnaBridge	171:3a7713b1edbc	428	* @}
AnnaBridge	171:3a7713b1edbc	429	*/
AnnaBridge	171:3a7713b1edbc	430
AnnaBridge	171:3a7713b1edbc	431	/** @defgroup RCCEx_PLLI2S_Multiplication_Factor PLLI2S Multiplication Factor
AnnaBridge	171:3a7713b1edbc	432	* @{
AnnaBridge	171:3a7713b1edbc	433	*/
AnnaBridge	171:3a7713b1edbc	434
AnnaBridge	171:3a7713b1edbc	435	#define RCC_PLLI2S_MUL8 RCC_CFGR2_PLL3MUL8 /!< PLLI2S input clock 8 */
AnnaBridge	171:3a7713b1edbc	436	#define RCC_PLLI2S_MUL9 RCC_CFGR2_PLL3MUL9 /!< PLLI2S input clock 9 */
AnnaBridge	171:3a7713b1edbc	437	#define RCC_PLLI2S_MUL10 RCC_CFGR2_PLL3MUL10 /!< PLLI2S input clock 10 */
AnnaBridge	171:3a7713b1edbc	438	#define RCC_PLLI2S_MUL11 RCC_CFGR2_PLL3MUL11 /!< PLLI2S input clock 11 */
AnnaBridge	171:3a7713b1edbc	439	#define RCC_PLLI2S_MUL12 RCC_CFGR2_PLL3MUL12 /!< PLLI2S input clock 12 */
AnnaBridge	171:3a7713b1edbc	440	#define RCC_PLLI2S_MUL13 RCC_CFGR2_PLL3MUL13 /!< PLLI2S input clock 13 */
AnnaBridge	171:3a7713b1edbc	441	#define RCC_PLLI2S_MUL14 RCC_CFGR2_PLL3MUL14 /!< PLLI2S input clock 14 */
AnnaBridge	171:3a7713b1edbc	442	#define RCC_PLLI2S_MUL16 RCC_CFGR2_PLL3MUL16 /!< PLLI2S input clock 16 */
AnnaBridge	171:3a7713b1edbc	443	#define RCC_PLLI2S_MUL20 RCC_CFGR2_PLL3MUL20 /!< PLLI2S input clock 20 */
AnnaBridge	171:3a7713b1edbc	444
AnnaBridge	171:3a7713b1edbc	445	/**
AnnaBridge	171:3a7713b1edbc	446	* @}
AnnaBridge	171:3a7713b1edbc	447	*/
AnnaBridge	171:3a7713b1edbc	448	#endif /* STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	449
AnnaBridge	171:3a7713b1edbc	450	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	451	/** @defgroup RCCEx_Prediv1_Source Prediv1 Source
AnnaBridge	171:3a7713b1edbc	452	* @{
AnnaBridge	171:3a7713b1edbc	453	*/
AnnaBridge	171:3a7713b1edbc	454
AnnaBridge	171:3a7713b1edbc	455	#define RCC_PREDIV1_SOURCE_HSE RCC_CFGR2_PREDIV1SRC_HSE
AnnaBridge	171:3a7713b1edbc	456	#define RCC_PREDIV1_SOURCE_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2
AnnaBridge	171:3a7713b1edbc	457
AnnaBridge	171:3a7713b1edbc	458	/**
AnnaBridge	171:3a7713b1edbc	459	* @}
AnnaBridge	171:3a7713b1edbc	460	*/
AnnaBridge	171:3a7713b1edbc	461	#endif /* STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	462
AnnaBridge	171:3a7713b1edbc	463	/** @defgroup RCCEx_Prediv1_Factor HSE Prediv1 Factor
AnnaBridge	171:3a7713b1edbc	464	* @{
AnnaBridge	171:3a7713b1edbc	465	*/
AnnaBridge	171:3a7713b1edbc	466
AnnaBridge	171:3a7713b1edbc	467	#define RCC_HSE_PREDIV_DIV1 0x00000000U
AnnaBridge	171:3a7713b1edbc	468
AnnaBridge	171:3a7713b1edbc	469	#if defined(STM32F105xC) \|\| defined(STM32F107xC) \|\| defined(STM32F100xB)\
AnnaBridge	171:3a7713b1edbc	470	\|\| defined(STM32F100xE)
AnnaBridge	171:3a7713b1edbc	471	#define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV1_DIV2
AnnaBridge	171:3a7713b1edbc	472	#define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV1_DIV3
AnnaBridge	171:3a7713b1edbc	473	#define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV1_DIV4
AnnaBridge	171:3a7713b1edbc	474	#define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV1_DIV5
AnnaBridge	171:3a7713b1edbc	475	#define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV1_DIV6
AnnaBridge	171:3a7713b1edbc	476	#define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV1_DIV7
AnnaBridge	171:3a7713b1edbc	477	#define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV1_DIV8
AnnaBridge	171:3a7713b1edbc	478	#define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV1_DIV9
AnnaBridge	171:3a7713b1edbc	479	#define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV1_DIV10
AnnaBridge	171:3a7713b1edbc	480	#define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV1_DIV11
AnnaBridge	171:3a7713b1edbc	481	#define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV1_DIV12
AnnaBridge	171:3a7713b1edbc	482	#define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV1_DIV13
AnnaBridge	171:3a7713b1edbc	483	#define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV1_DIV14
AnnaBridge	171:3a7713b1edbc	484	#define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV1_DIV15
AnnaBridge	171:3a7713b1edbc	485	#define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV1_DIV16
AnnaBridge	171:3a7713b1edbc	486	#else
AnnaBridge	171:3a7713b1edbc	487	#define RCC_HSE_PREDIV_DIV2 RCC_CFGR_PLLXTPRE
AnnaBridge	171:3a7713b1edbc	488	#endif /* STM32F105xC \|\| STM32F107xC \|\| STM32F100xB \|\| STM32F100xE */
AnnaBridge	171:3a7713b1edbc	489
AnnaBridge	171:3a7713b1edbc	490	/**
AnnaBridge	171:3a7713b1edbc	491	* @}
AnnaBridge	171:3a7713b1edbc	492	*/
AnnaBridge	171:3a7713b1edbc	493
AnnaBridge	171:3a7713b1edbc	494	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	495	/** @defgroup RCCEx_Prediv2_Factor HSE Prediv2 Factor
AnnaBridge	171:3a7713b1edbc	496	* @{
AnnaBridge	171:3a7713b1edbc	497	*/
AnnaBridge	171:3a7713b1edbc	498
AnnaBridge	171:3a7713b1edbc	499	#define RCC_HSE_PREDIV2_DIV1 RCC_CFGR2_PREDIV2_DIV1 /!< PREDIV2 input clock not divided /
AnnaBridge	171:3a7713b1edbc	500	#define RCC_HSE_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2 /!< PREDIV2 input clock divided by 2 /
AnnaBridge	171:3a7713b1edbc	501	#define RCC_HSE_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3 /!< PREDIV2 input clock divided by 3 /
AnnaBridge	171:3a7713b1edbc	502	#define RCC_HSE_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4 /!< PREDIV2 input clock divided by 4 /
AnnaBridge	171:3a7713b1edbc	503	#define RCC_HSE_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5 /!< PREDIV2 input clock divided by 5 /
AnnaBridge	171:3a7713b1edbc	504	#define RCC_HSE_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6 /!< PREDIV2 input clock divided by 6 /
AnnaBridge	171:3a7713b1edbc	505	#define RCC_HSE_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7 /!< PREDIV2 input clock divided by 7 /
AnnaBridge	171:3a7713b1edbc	506	#define RCC_HSE_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8 /!< PREDIV2 input clock divided by 8 /
AnnaBridge	171:3a7713b1edbc	507	#define RCC_HSE_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9 /!< PREDIV2 input clock divided by 9 /
AnnaBridge	171:3a7713b1edbc	508	#define RCC_HSE_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10 /!< PREDIV2 input clock divided by 10 /
AnnaBridge	171:3a7713b1edbc	509	#define RCC_HSE_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11 /!< PREDIV2 input clock divided by 11 /
AnnaBridge	171:3a7713b1edbc	510	#define RCC_HSE_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12 /!< PREDIV2 input clock divided by 12 /
AnnaBridge	171:3a7713b1edbc	511	#define RCC_HSE_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13 /!< PREDIV2 input clock divided by 13 /
AnnaBridge	171:3a7713b1edbc	512	#define RCC_HSE_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14 /!< PREDIV2 input clock divided by 14 /
AnnaBridge	171:3a7713b1edbc	513	#define RCC_HSE_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15 /!< PREDIV2 input clock divided by 15 /
AnnaBridge	171:3a7713b1edbc	514	#define RCC_HSE_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16 /!< PREDIV2 input clock divided by 16 /
AnnaBridge	171:3a7713b1edbc	515
AnnaBridge	171:3a7713b1edbc	516	/**
AnnaBridge	171:3a7713b1edbc	517	* @}
AnnaBridge	171:3a7713b1edbc	518	*/
AnnaBridge	171:3a7713b1edbc	519
AnnaBridge	171:3a7713b1edbc	520	/** @defgroup RCCEx_PLL2_Config PLL Config
AnnaBridge	171:3a7713b1edbc	521	* @{
AnnaBridge	171:3a7713b1edbc	522	*/
AnnaBridge	171:3a7713b1edbc	523	#define RCC_PLL2_NONE 0x00000000U
AnnaBridge	171:3a7713b1edbc	524	#define RCC_PLL2_OFF 0x00000001U
AnnaBridge	171:3a7713b1edbc	525	#define RCC_PLL2_ON 0x00000002U
AnnaBridge	171:3a7713b1edbc	526
AnnaBridge	171:3a7713b1edbc	527	/**
AnnaBridge	171:3a7713b1edbc	528	* @}
AnnaBridge	171:3a7713b1edbc	529	*/
AnnaBridge	171:3a7713b1edbc	530
AnnaBridge	171:3a7713b1edbc	531	/** @defgroup RCCEx_PLL2_Multiplication_Factor PLL2 Multiplication Factor
AnnaBridge	171:3a7713b1edbc	532	* @{
AnnaBridge	171:3a7713b1edbc	533	*/
AnnaBridge	171:3a7713b1edbc	534
AnnaBridge	171:3a7713b1edbc	535	#define RCC_PLL2_MUL8 RCC_CFGR2_PLL2MUL8 /!< PLL2 input clock 8 */
AnnaBridge	171:3a7713b1edbc	536	#define RCC_PLL2_MUL9 RCC_CFGR2_PLL2MUL9 /!< PLL2 input clock 9 */
AnnaBridge	171:3a7713b1edbc	537	#define RCC_PLL2_MUL10 RCC_CFGR2_PLL2MUL10 /!< PLL2 input clock 10 */
AnnaBridge	171:3a7713b1edbc	538	#define RCC_PLL2_MUL11 RCC_CFGR2_PLL2MUL11 /!< PLL2 input clock 11 */
AnnaBridge	171:3a7713b1edbc	539	#define RCC_PLL2_MUL12 RCC_CFGR2_PLL2MUL12 /!< PLL2 input clock 12 */
AnnaBridge	171:3a7713b1edbc	540	#define RCC_PLL2_MUL13 RCC_CFGR2_PLL2MUL13 /!< PLL2 input clock 13 */
AnnaBridge	171:3a7713b1edbc	541	#define RCC_PLL2_MUL14 RCC_CFGR2_PLL2MUL14 /!< PLL2 input clock 14 */
AnnaBridge	171:3a7713b1edbc	542	#define RCC_PLL2_MUL16 RCC_CFGR2_PLL2MUL16 /!< PLL2 input clock 16 */
AnnaBridge	171:3a7713b1edbc	543	#define RCC_PLL2_MUL20 RCC_CFGR2_PLL2MUL20 /!< PLL2 input clock 20 */
AnnaBridge	171:3a7713b1edbc	544
AnnaBridge	171:3a7713b1edbc	545	/**
AnnaBridge	171:3a7713b1edbc	546	* @}
AnnaBridge	171:3a7713b1edbc	547	*/
AnnaBridge	171:3a7713b1edbc	548
AnnaBridge	171:3a7713b1edbc	549	#endif /* STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	550
AnnaBridge	171:3a7713b1edbc	551	/** @defgroup RCCEx_PLL_Multiplication_Factor PLL Multiplication Factor
AnnaBridge	171:3a7713b1edbc	552	* @{
AnnaBridge	171:3a7713b1edbc	553	*/
AnnaBridge	171:3a7713b1edbc	554
AnnaBridge	171:3a7713b1edbc	555	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	556	#else
AnnaBridge	171:3a7713b1edbc	557	#define RCC_PLL_MUL2 RCC_CFGR_PLLMULL2
AnnaBridge	171:3a7713b1edbc	558	#define RCC_PLL_MUL3 RCC_CFGR_PLLMULL3
AnnaBridge	171:3a7713b1edbc	559	#endif /* STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	560	#define RCC_PLL_MUL4 RCC_CFGR_PLLMULL4
AnnaBridge	171:3a7713b1edbc	561	#define RCC_PLL_MUL5 RCC_CFGR_PLLMULL5
AnnaBridge	171:3a7713b1edbc	562	#define RCC_PLL_MUL6 RCC_CFGR_PLLMULL6
AnnaBridge	171:3a7713b1edbc	563	#define RCC_PLL_MUL7 RCC_CFGR_PLLMULL7
AnnaBridge	171:3a7713b1edbc	564	#define RCC_PLL_MUL8 RCC_CFGR_PLLMULL8
AnnaBridge	171:3a7713b1edbc	565	#define RCC_PLL_MUL9 RCC_CFGR_PLLMULL9
AnnaBridge	171:3a7713b1edbc	566	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	567	#define RCC_PLL_MUL6_5 RCC_CFGR_PLLMULL6_5
AnnaBridge	171:3a7713b1edbc	568	#else
AnnaBridge	171:3a7713b1edbc	569	#define RCC_PLL_MUL10 RCC_CFGR_PLLMULL10
AnnaBridge	171:3a7713b1edbc	570	#define RCC_PLL_MUL11 RCC_CFGR_PLLMULL11
AnnaBridge	171:3a7713b1edbc	571	#define RCC_PLL_MUL12 RCC_CFGR_PLLMULL12
AnnaBridge	171:3a7713b1edbc	572	#define RCC_PLL_MUL13 RCC_CFGR_PLLMULL13
AnnaBridge	171:3a7713b1edbc	573	#define RCC_PLL_MUL14 RCC_CFGR_PLLMULL14
AnnaBridge	171:3a7713b1edbc	574	#define RCC_PLL_MUL15 RCC_CFGR_PLLMULL15
AnnaBridge	171:3a7713b1edbc	575	#define RCC_PLL_MUL16 RCC_CFGR_PLLMULL16
AnnaBridge	171:3a7713b1edbc	576	#endif /* STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	577
AnnaBridge	171:3a7713b1edbc	578	/**
AnnaBridge	171:3a7713b1edbc	579	* @}
AnnaBridge	171:3a7713b1edbc	580	*/
AnnaBridge	171:3a7713b1edbc	581
AnnaBridge	171:3a7713b1edbc	582	/** @defgroup RCCEx_MCO1_Clock_Source MCO1 Clock Source
AnnaBridge	171:3a7713b1edbc	583	* @{
AnnaBridge	171:3a7713b1edbc	584	*/
AnnaBridge	171:3a7713b1edbc	585	#define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK)
AnnaBridge	171:3a7713b1edbc	586	#define RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK)
AnnaBridge	171:3a7713b1edbc	587	#define RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI)
AnnaBridge	171:3a7713b1edbc	588	#define RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE)
AnnaBridge	171:3a7713b1edbc	589	#define RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLLCLK_DIV2)
AnnaBridge	171:3a7713b1edbc	590	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	591	#define RCC_MCO1SOURCE_PLL2CLK ((uint32_t)RCC_CFGR_MCO_PLL2CLK)
AnnaBridge	171:3a7713b1edbc	592	#define RCC_MCO1SOURCE_PLL3CLK_DIV2 ((uint32_t)RCC_CFGR_MCO_PLL3CLK_DIV2)
AnnaBridge	171:3a7713b1edbc	593	#define RCC_MCO1SOURCE_EXT_HSE ((uint32_t)RCC_CFGR_MCO_EXT_HSE)
AnnaBridge	171:3a7713b1edbc	594	#define RCC_MCO1SOURCE_PLL3CLK ((uint32_t)RCC_CFGR_MCO_PLL3CLK)
AnnaBridge	171:3a7713b1edbc	595	#endif /* STM32F105xC \|\| STM32F107xC*/
AnnaBridge	171:3a7713b1edbc	596	/**
AnnaBridge	171:3a7713b1edbc	597	* @}
AnnaBridge	171:3a7713b1edbc	598	*/
AnnaBridge	171:3a7713b1edbc	599
AnnaBridge	171:3a7713b1edbc	600	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	601	/** @defgroup RCCEx_Interrupt RCCEx Interrupt
AnnaBridge	171:3a7713b1edbc	602	* @{
AnnaBridge	171:3a7713b1edbc	603	*/
AnnaBridge	171:3a7713b1edbc	604	#define RCC_IT_PLL2RDY ((uint8_t)RCC_CIR_PLL2RDYF)
AnnaBridge	171:3a7713b1edbc	605	#define RCC_IT_PLLI2SRDY ((uint8_t)RCC_CIR_PLL3RDYF)
AnnaBridge	171:3a7713b1edbc	606	/**
AnnaBridge	171:3a7713b1edbc	607	* @}
AnnaBridge	171:3a7713b1edbc	608	*/
AnnaBridge	171:3a7713b1edbc	609
AnnaBridge	171:3a7713b1edbc	610	/** @defgroup RCCEx_Flag RCCEx Flag
AnnaBridge	171:3a7713b1edbc	611	* Elements values convention: 0XXYYYYYb
AnnaBridge	171:3a7713b1edbc	612	* - YYYYY : Flag position in the register
AnnaBridge	171:3a7713b1edbc	613	* - XX : Register index
AnnaBridge	171:3a7713b1edbc	614	* - 01: CR register
AnnaBridge	171:3a7713b1edbc	615	* @{
AnnaBridge	171:3a7713b1edbc	616	*/
AnnaBridge	171:3a7713b1edbc	617	/* Flags in the CR register */
AnnaBridge	171:3a7713b1edbc	618	#define RCC_FLAG_PLL2RDY ((uint8_t)((CR_REG_INDEX << 5U) \| RCC_CR_PLL2RDY_Pos))
AnnaBridge	171:3a7713b1edbc	619	#define RCC_FLAG_PLLI2SRDY ((uint8_t)((CR_REG_INDEX << 5U) \| RCC_CR_PLL3RDY_Pos))
AnnaBridge	171:3a7713b1edbc	620	/**
AnnaBridge	171:3a7713b1edbc	621	* @}
AnnaBridge	171:3a7713b1edbc	622	*/
AnnaBridge	171:3a7713b1edbc	623	#endif /* STM32F105xC \|\| STM32F107xC*/
AnnaBridge	171:3a7713b1edbc	624
AnnaBridge	171:3a7713b1edbc	625	/**
AnnaBridge	171:3a7713b1edbc	626	* @}
AnnaBridge	171:3a7713b1edbc	627	*/
AnnaBridge	171:3a7713b1edbc	628
AnnaBridge	171:3a7713b1edbc	629	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	630	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
AnnaBridge	171:3a7713b1edbc	631	* @{
AnnaBridge	171:3a7713b1edbc	632	*/
AnnaBridge	171:3a7713b1edbc	633
AnnaBridge	171:3a7713b1edbc	634	/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
AnnaBridge	171:3a7713b1edbc	635	* @brief Enable or disable the AHB1 peripheral clock.
AnnaBridge	171:3a7713b1edbc	636	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	171:3a7713b1edbc	637	* is disabled and the application software has to enable this clock before
AnnaBridge	171:3a7713b1edbc	638	* using it.
AnnaBridge	171:3a7713b1edbc	639	* @{
AnnaBridge	171:3a7713b1edbc	640	*/
AnnaBridge	171:3a7713b1edbc	641
AnnaBridge	171:3a7713b1edbc	642	#if defined(STM32F101xE) \|\| defined(STM32F103xE) \|\| defined(STM32F101xG)\
AnnaBridge	171:3a7713b1edbc	643	\|\| defined(STM32F103xG) \|\| defined(STM32F105xC) \|\| defined (STM32F107xC)\
AnnaBridge	171:3a7713b1edbc	644	\|\| defined (STM32F100xE)
AnnaBridge	171:3a7713b1edbc	645	#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	646	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	647	SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
AnnaBridge	171:3a7713b1edbc	648	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	649	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
AnnaBridge	171:3a7713b1edbc	650	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	651	} while(0U)
AnnaBridge	171:3a7713b1edbc	652
AnnaBridge	171:3a7713b1edbc	653	#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
AnnaBridge	171:3a7713b1edbc	654	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| STM32F103xG \|\| STM32F105xC \|\| STM32F107xC \|\| STM32F100xE */
AnnaBridge	171:3a7713b1edbc	655
AnnaBridge	171:3a7713b1edbc	656	#if defined(STM32F101xE) \|\| defined(STM32F103xE) \|\| defined(STM32F101xG)\
AnnaBridge	171:3a7713b1edbc	657	\|\| defined(STM32F103xG) \|\| defined (STM32F100xE)
AnnaBridge	171:3a7713b1edbc	658	#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	659	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	660	SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
AnnaBridge	171:3a7713b1edbc	661	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	662	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
AnnaBridge	171:3a7713b1edbc	663	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	664	} while(0U)
AnnaBridge	171:3a7713b1edbc	665
AnnaBridge	171:3a7713b1edbc	666	#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN))
AnnaBridge	171:3a7713b1edbc	667	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| STM32F103xG \|\| STM32F100xE */
AnnaBridge	171:3a7713b1edbc	668
AnnaBridge	171:3a7713b1edbc	669	#if defined(STM32F103xE) \|\| defined(STM32F103xG)
AnnaBridge	171:3a7713b1edbc	670	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	671	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	672	SET_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\
AnnaBridge	171:3a7713b1edbc	673	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	674	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\
AnnaBridge	171:3a7713b1edbc	675	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	676	} while(0U)
AnnaBridge	171:3a7713b1edbc	677
AnnaBridge	171:3a7713b1edbc	678
AnnaBridge	171:3a7713b1edbc	679	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SDIOEN))
AnnaBridge	171:3a7713b1edbc	680	#endif /* STM32F103xE \|\| STM32F103xG */
AnnaBridge	171:3a7713b1edbc	681
AnnaBridge	171:3a7713b1edbc	682	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	683	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	684	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	685	SET_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\
AnnaBridge	171:3a7713b1edbc	686	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	687	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\
AnnaBridge	171:3a7713b1edbc	688	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	689	} while(0U)
AnnaBridge	171:3a7713b1edbc	690
AnnaBridge	171:3a7713b1edbc	691
AnnaBridge	171:3a7713b1edbc	692	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_OTGFSEN))
AnnaBridge	171:3a7713b1edbc	693	#endif /* STM32F105xC \|\| STM32F107xC*/
AnnaBridge	171:3a7713b1edbc	694
AnnaBridge	171:3a7713b1edbc	695	#if defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	696	#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	697	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	698	SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\
AnnaBridge	171:3a7713b1edbc	699	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	700	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\
AnnaBridge	171:3a7713b1edbc	701	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	702	} while(0U)
AnnaBridge	171:3a7713b1edbc	703
AnnaBridge	171:3a7713b1edbc	704	#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	705	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	706	SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\
AnnaBridge	171:3a7713b1edbc	707	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	708	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\
AnnaBridge	171:3a7713b1edbc	709	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	710	} while(0U)
AnnaBridge	171:3a7713b1edbc	711
AnnaBridge	171:3a7713b1edbc	712	#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	713	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	714	SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\
AnnaBridge	171:3a7713b1edbc	715	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	716	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\
AnnaBridge	171:3a7713b1edbc	717	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	718	} while(0U)
AnnaBridge	171:3a7713b1edbc	719
AnnaBridge	171:3a7713b1edbc	720	#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN))
AnnaBridge	171:3a7713b1edbc	721	#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACTXEN))
AnnaBridge	171:3a7713b1edbc	722	#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACRXEN))
AnnaBridge	171:3a7713b1edbc	723
AnnaBridge	171:3a7713b1edbc	724	/**
AnnaBridge	171:3a7713b1edbc	725	* @brief Enable ETHERNET clock.
AnnaBridge	171:3a7713b1edbc	726	*/
AnnaBridge	171:3a7713b1edbc	727	#define __HAL_RCC_ETH_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	728	__HAL_RCC_ETHMAC_CLK_ENABLE(); \
AnnaBridge	171:3a7713b1edbc	729	__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
AnnaBridge	171:3a7713b1edbc	730	__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
AnnaBridge	171:3a7713b1edbc	731	} while(0U)
AnnaBridge	171:3a7713b1edbc	732	/**
AnnaBridge	171:3a7713b1edbc	733	* @brief Disable ETHERNET clock.
AnnaBridge	171:3a7713b1edbc	734	*/
AnnaBridge	171:3a7713b1edbc	735	#define __HAL_RCC_ETH_CLK_DISABLE() do { \
AnnaBridge	171:3a7713b1edbc	736	__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
AnnaBridge	171:3a7713b1edbc	737	__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
AnnaBridge	171:3a7713b1edbc	738	__HAL_RCC_ETHMAC_CLK_DISABLE(); \
AnnaBridge	171:3a7713b1edbc	739	} while(0U)
AnnaBridge	171:3a7713b1edbc	740
AnnaBridge	171:3a7713b1edbc	741	#endif /* STM32F107xC*/
AnnaBridge	171:3a7713b1edbc	742
AnnaBridge	171:3a7713b1edbc	743	/**
AnnaBridge	171:3a7713b1edbc	744	* @}
AnnaBridge	171:3a7713b1edbc	745	*/
AnnaBridge	171:3a7713b1edbc	746
AnnaBridge	171:3a7713b1edbc	747	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
AnnaBridge	171:3a7713b1edbc	748	* @brief Get the enable or disable status of the AHB1 peripheral clock.
AnnaBridge	171:3a7713b1edbc	749	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	171:3a7713b1edbc	750	* is disabled and the application software has to enable this clock before
AnnaBridge	171:3a7713b1edbc	751	* using it.
AnnaBridge	171:3a7713b1edbc	752	* @{
AnnaBridge	171:3a7713b1edbc	753	*/
AnnaBridge	171:3a7713b1edbc	754
AnnaBridge	171:3a7713b1edbc	755	#if defined(STM32F101xE) \|\| defined(STM32F103xE) \|\| defined(STM32F101xG)\
AnnaBridge	171:3a7713b1edbc	756	\|\| defined(STM32F103xG) \|\| defined(STM32F105xC) \|\| defined (STM32F107xC)\
AnnaBridge	171:3a7713b1edbc	757	\|\| defined (STM32F100xE)
AnnaBridge	171:3a7713b1edbc	758	#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	759	#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	760	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| STM32F103xG \|\| STM32F105xC \|\| STM32F107xC \|\| STM32F100xE */
AnnaBridge	171:3a7713b1edbc	761	#if defined(STM32F101xE) \|\| defined(STM32F103xE) \|\| defined(STM32F101xG)\
AnnaBridge	171:3a7713b1edbc	762	\|\| defined(STM32F103xG) \|\| defined (STM32F100xE)
AnnaBridge	171:3a7713b1edbc	763	#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	764	#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	765	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| STM32F103xG \|\| STM32F100xE */
AnnaBridge	171:3a7713b1edbc	766	#if defined(STM32F103xE) \|\| defined(STM32F103xG)
AnnaBridge	171:3a7713b1edbc	767	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	768	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	769	#endif /* STM32F103xE \|\| STM32F103xG */
AnnaBridge	171:3a7713b1edbc	770	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	771	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	772	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	773	#endif /* STM32F105xC \|\| STM32F107xC*/
AnnaBridge	171:3a7713b1edbc	774	#if defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	775	#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	776	#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	777	#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	778	#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	779	#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	780	#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	781	#endif /* STM32F107xC*/
AnnaBridge	171:3a7713b1edbc	782
AnnaBridge	171:3a7713b1edbc	783	/**
AnnaBridge	171:3a7713b1edbc	784	* @}
AnnaBridge	171:3a7713b1edbc	785	*/
AnnaBridge	171:3a7713b1edbc	786
AnnaBridge	171:3a7713b1edbc	787	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
AnnaBridge	171:3a7713b1edbc	788	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
AnnaBridge	171:3a7713b1edbc	789	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	171:3a7713b1edbc	790	* is disabled and the application software has to enable this clock before
AnnaBridge	171:3a7713b1edbc	791	* using it.
AnnaBridge	171:3a7713b1edbc	792	* @{
AnnaBridge	171:3a7713b1edbc	793	*/
AnnaBridge	171:3a7713b1edbc	794
AnnaBridge	171:3a7713b1edbc	795	#if defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE)\
AnnaBridge	171:3a7713b1edbc	796	\|\| defined(STM32F103xG) \|\| defined(STM32F105xC) \|\|defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	797	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	798	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	799	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
AnnaBridge	171:3a7713b1edbc	800	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	801	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
AnnaBridge	171:3a7713b1edbc	802	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	803	} while(0U)
AnnaBridge	171:3a7713b1edbc	804
AnnaBridge	171:3a7713b1edbc	805	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
AnnaBridge	171:3a7713b1edbc	806	#endif /* STM32F103x6 \|\| STM32F103xB \|\| STM32F103xE \|\| STM32F103xG \|\| STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	807
AnnaBridge	171:3a7713b1edbc	808	#if defined(STM32F100xB) \|\| defined(STM32F100xE) \|\| defined(STM32F101xB)\
AnnaBridge	171:3a7713b1edbc	809	\|\| defined(STM32F101xE) \|\| defined(STM32F101xG) \|\| defined(STM32F102xB)\
AnnaBridge	171:3a7713b1edbc	810	\|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG)\
AnnaBridge	171:3a7713b1edbc	811	\|\| defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	812	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	813	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	814	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	171:3a7713b1edbc	815	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	816	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
AnnaBridge	171:3a7713b1edbc	817	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	818	} while(0U)
AnnaBridge	171:3a7713b1edbc	819
AnnaBridge	171:3a7713b1edbc	820	#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	821	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	822	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
AnnaBridge	171:3a7713b1edbc	823	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	824	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
AnnaBridge	171:3a7713b1edbc	825	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	826	} while(0U)
AnnaBridge	171:3a7713b1edbc	827
AnnaBridge	171:3a7713b1edbc	828	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	829	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	830	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
AnnaBridge	171:3a7713b1edbc	831	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	832	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
AnnaBridge	171:3a7713b1edbc	833	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	834	} while(0U)
AnnaBridge	171:3a7713b1edbc	835
AnnaBridge	171:3a7713b1edbc	836	#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	837	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	838	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
AnnaBridge	171:3a7713b1edbc	839	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	840	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
AnnaBridge	171:3a7713b1edbc	841	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	842	} while(0U)
AnnaBridge	171:3a7713b1edbc	843
AnnaBridge	171:3a7713b1edbc	844	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
AnnaBridge	171:3a7713b1edbc	845	#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
AnnaBridge	171:3a7713b1edbc	846	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
AnnaBridge	171:3a7713b1edbc	847	#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
AnnaBridge	171:3a7713b1edbc	848	#endif /* STM32F100xB \|\| STM32F101xB \|\| STM32F101xE \|\| (...) \|\| STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	849
AnnaBridge	171:3a7713b1edbc	850	#if defined(STM32F102x6) \|\| defined(STM32F102xB) \|\| defined(STM32F103x6)\
AnnaBridge	171:3a7713b1edbc	851	\|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG)
AnnaBridge	171:3a7713b1edbc	852	#define __HAL_RCC_USB_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	853	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	854	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
AnnaBridge	171:3a7713b1edbc	855	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	856	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
AnnaBridge	171:3a7713b1edbc	857	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	858	} while(0U)
AnnaBridge	171:3a7713b1edbc	859
AnnaBridge	171:3a7713b1edbc	860	#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
AnnaBridge	171:3a7713b1edbc	861	#endif /* STM32F102x6 \|\| STM32F102xB \|\| STM32F103x6 \|\| STM32F103xB \|\| STM32F103xE \|\| STM32F103xG */
AnnaBridge	171:3a7713b1edbc	862
AnnaBridge	171:3a7713b1edbc	863	#if defined(STM32F101xE) \|\| defined(STM32F103xE) \|\| defined(STM32F101xG)\
AnnaBridge	171:3a7713b1edbc	864	\|\| defined(STM32F103xG) \|\| defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	865	#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	866	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	867	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
AnnaBridge	171:3a7713b1edbc	868	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	869	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
AnnaBridge	171:3a7713b1edbc	870	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	871	} while(0U)
AnnaBridge	171:3a7713b1edbc	872
AnnaBridge	171:3a7713b1edbc	873	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	874	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	875	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge	171:3a7713b1edbc	876	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	877	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge	171:3a7713b1edbc	878	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	879	} while(0U)
AnnaBridge	171:3a7713b1edbc	880
AnnaBridge	171:3a7713b1edbc	881	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	882	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	883	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
AnnaBridge	171:3a7713b1edbc	884	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	885	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
AnnaBridge	171:3a7713b1edbc	886	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	887	} while(0U)
AnnaBridge	171:3a7713b1edbc	888
AnnaBridge	171:3a7713b1edbc	889	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	890	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	891	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	171:3a7713b1edbc	892	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	893	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	171:3a7713b1edbc	894	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	895	} while(0U)
AnnaBridge	171:3a7713b1edbc	896
AnnaBridge	171:3a7713b1edbc	897	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	898	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	899	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
AnnaBridge	171:3a7713b1edbc	900	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	901	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
AnnaBridge	171:3a7713b1edbc	902	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	903	} while(0U)
AnnaBridge	171:3a7713b1edbc	904
AnnaBridge	171:3a7713b1edbc	905	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	906	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	907	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
AnnaBridge	171:3a7713b1edbc	908	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	909	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
AnnaBridge	171:3a7713b1edbc	910	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	911	} while(0U)
AnnaBridge	171:3a7713b1edbc	912
AnnaBridge	171:3a7713b1edbc	913	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	914	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	915	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge	171:3a7713b1edbc	916	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	917	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge	171:3a7713b1edbc	918	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	919	} while(0U)
AnnaBridge	171:3a7713b1edbc	920
AnnaBridge	171:3a7713b1edbc	921	#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
AnnaBridge	171:3a7713b1edbc	922	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
AnnaBridge	171:3a7713b1edbc	923	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
AnnaBridge	171:3a7713b1edbc	924	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
AnnaBridge	171:3a7713b1edbc	925	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
AnnaBridge	171:3a7713b1edbc	926	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
AnnaBridge	171:3a7713b1edbc	927	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
AnnaBridge	171:3a7713b1edbc	928	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| (...) \|\| STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	929
AnnaBridge	171:3a7713b1edbc	930	#if defined(STM32F100xB) \|\| defined (STM32F100xE)
AnnaBridge	171:3a7713b1edbc	931	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	932	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	933	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge	171:3a7713b1edbc	934	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	935	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
AnnaBridge	171:3a7713b1edbc	936	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	937	} while(0U)
AnnaBridge	171:3a7713b1edbc	938
AnnaBridge	171:3a7713b1edbc	939	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	940	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	941	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
AnnaBridge	171:3a7713b1edbc	942	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	943	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
AnnaBridge	171:3a7713b1edbc	944	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	945	} while(0U)
AnnaBridge	171:3a7713b1edbc	946
AnnaBridge	171:3a7713b1edbc	947	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	948	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	949	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge	171:3a7713b1edbc	950	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	951	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
AnnaBridge	171:3a7713b1edbc	952	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	953	} while(0U)
AnnaBridge	171:3a7713b1edbc	954
AnnaBridge	171:3a7713b1edbc	955	#define __HAL_RCC_CEC_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	956	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	957	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
AnnaBridge	171:3a7713b1edbc	958	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	959	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
AnnaBridge	171:3a7713b1edbc	960	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	961	} while(0U)
AnnaBridge	171:3a7713b1edbc	962
AnnaBridge	171:3a7713b1edbc	963	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
AnnaBridge	171:3a7713b1edbc	964	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
AnnaBridge	171:3a7713b1edbc	965	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
AnnaBridge	171:3a7713b1edbc	966	#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
AnnaBridge	171:3a7713b1edbc	967	#endif /* STM32F100xB \|\| STM32F100xE */
AnnaBridge	171:3a7713b1edbc	968
AnnaBridge	171:3a7713b1edbc	969	#ifdef STM32F100xE
AnnaBridge	171:3a7713b1edbc	970	#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	971	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	972	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
AnnaBridge	171:3a7713b1edbc	973	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	974	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
AnnaBridge	171:3a7713b1edbc	975	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	976	} while(0U)
AnnaBridge	171:3a7713b1edbc	977
AnnaBridge	171:3a7713b1edbc	978	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	979	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	980	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
AnnaBridge	171:3a7713b1edbc	981	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	982	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
AnnaBridge	171:3a7713b1edbc	983	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	984	} while(0U)
AnnaBridge	171:3a7713b1edbc	985
AnnaBridge	171:3a7713b1edbc	986	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	987	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	988	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
AnnaBridge	171:3a7713b1edbc	989	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	990	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
AnnaBridge	171:3a7713b1edbc	991	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	992	} while(0U)
AnnaBridge	171:3a7713b1edbc	993
AnnaBridge	171:3a7713b1edbc	994	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	995	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	996	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge	171:3a7713b1edbc	997	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	998	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge	171:3a7713b1edbc	999	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	1000	} while(0U)
AnnaBridge	171:3a7713b1edbc	1001
AnnaBridge	171:3a7713b1edbc	1002	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	1003	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	1004	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	171:3a7713b1edbc	1005	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	1006	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
AnnaBridge	171:3a7713b1edbc	1007	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	1008	} while(0U)
AnnaBridge	171:3a7713b1edbc	1009
AnnaBridge	171:3a7713b1edbc	1010	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	1011	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	1012	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
AnnaBridge	171:3a7713b1edbc	1013	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	1014	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
AnnaBridge	171:3a7713b1edbc	1015	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	1016	} while(0U)
AnnaBridge	171:3a7713b1edbc	1017
AnnaBridge	171:3a7713b1edbc	1018	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	1019	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	1020	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
AnnaBridge	171:3a7713b1edbc	1021	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	1022	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
AnnaBridge	171:3a7713b1edbc	1023	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	1024	} while(0U)
AnnaBridge	171:3a7713b1edbc	1025
AnnaBridge	171:3a7713b1edbc	1026	#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
AnnaBridge	171:3a7713b1edbc	1027	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
AnnaBridge	171:3a7713b1edbc	1028	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
AnnaBridge	171:3a7713b1edbc	1029	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
AnnaBridge	171:3a7713b1edbc	1030	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
AnnaBridge	171:3a7713b1edbc	1031	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
AnnaBridge	171:3a7713b1edbc	1032	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
AnnaBridge	171:3a7713b1edbc	1033	#endif /* STM32F100xE */
AnnaBridge	171:3a7713b1edbc	1034
AnnaBridge	171:3a7713b1edbc	1035	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	1036	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	1037	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	1038	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
AnnaBridge	171:3a7713b1edbc	1039	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	1040	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
AnnaBridge	171:3a7713b1edbc	1041	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	1042	} while(0U)
AnnaBridge	171:3a7713b1edbc	1043
AnnaBridge	171:3a7713b1edbc	1044	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
AnnaBridge	171:3a7713b1edbc	1045	#endif /* STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	1046
AnnaBridge	171:3a7713b1edbc	1047	#if defined(STM32F101xG) \|\| defined(STM32F103xG)
AnnaBridge	171:3a7713b1edbc	1048	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	1049	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	1050	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
AnnaBridge	171:3a7713b1edbc	1051	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	1052	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
AnnaBridge	171:3a7713b1edbc	1053	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	1054	} while(0U)
AnnaBridge	171:3a7713b1edbc	1055
AnnaBridge	171:3a7713b1edbc	1056	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	1057	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	1058	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
AnnaBridge	171:3a7713b1edbc	1059	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	1060	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
AnnaBridge	171:3a7713b1edbc	1061	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	1062	} while(0U)
AnnaBridge	171:3a7713b1edbc	1063
AnnaBridge	171:3a7713b1edbc	1064	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	1065	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	1066	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge	171:3a7713b1edbc	1067	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	1068	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge	171:3a7713b1edbc	1069	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	1070	} while(0U)
AnnaBridge	171:3a7713b1edbc	1071
AnnaBridge	171:3a7713b1edbc	1072	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
AnnaBridge	171:3a7713b1edbc	1073	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
AnnaBridge	171:3a7713b1edbc	1074	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
AnnaBridge	171:3a7713b1edbc	1075	#endif /* STM32F101xG \|\| STM32F103xG*/
AnnaBridge	171:3a7713b1edbc	1076
AnnaBridge	171:3a7713b1edbc	1077	/**
AnnaBridge	171:3a7713b1edbc	1078	* @}
AnnaBridge	171:3a7713b1edbc	1079	*/
AnnaBridge	171:3a7713b1edbc	1080
AnnaBridge	171:3a7713b1edbc	1081	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
AnnaBridge	171:3a7713b1edbc	1082	* @brief Get the enable or disable status of the APB1 peripheral clock.
AnnaBridge	171:3a7713b1edbc	1083	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	171:3a7713b1edbc	1084	* is disabled and the application software has to enable this clock before
AnnaBridge	171:3a7713b1edbc	1085	* using it.
AnnaBridge	171:3a7713b1edbc	1086	* @{
AnnaBridge	171:3a7713b1edbc	1087	*/
AnnaBridge	171:3a7713b1edbc	1088
AnnaBridge	171:3a7713b1edbc	1089	#if defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE)\
AnnaBridge	171:3a7713b1edbc	1090	\|\| defined(STM32F103xG) \|\| defined(STM32F105xC) \|\|defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	1091	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1092	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1093	#endif /* STM32F103x6 \|\| STM32F103xB \|\| STM32F103xE \|\| STM32F103xG \|\| STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	1094	#if defined(STM32F100xB) \|\| defined(STM32F100xE) \|\| defined(STM32F101xB)\
AnnaBridge	171:3a7713b1edbc	1095	\|\| defined(STM32F101xE) \|\| defined(STM32F101xG) \|\| defined(STM32F102xB)\
AnnaBridge	171:3a7713b1edbc	1096	\|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG)\
AnnaBridge	171:3a7713b1edbc	1097	\|\| defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	1098	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1099	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1100	#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1101	#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1102	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1103	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1104	#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1105	#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1106	#endif /* STM32F100xB \|\| STM32F101xB \|\| STM32F101xE \|\| (...) \|\| STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	1107	#if defined(STM32F102x6) \|\| defined(STM32F102xB) \|\| defined(STM32F103x6)\
AnnaBridge	171:3a7713b1edbc	1108	\|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG)
AnnaBridge	171:3a7713b1edbc	1109	#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1110	#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1111	#endif /* STM32F102x6 \|\| STM32F102xB \|\| STM32F103x6 \|\| STM32F103xB \|\| STM32F103xE \|\| STM32F103xG */
AnnaBridge	171:3a7713b1edbc	1112	#if defined(STM32F101xE) \|\| defined(STM32F103xE) \|\| defined(STM32F101xG)\
AnnaBridge	171:3a7713b1edbc	1113	\|\| defined(STM32F103xG) \|\| defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	1114	#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1115	#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1116	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1117	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1118	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1119	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1120	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1121	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1122	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1123	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1124	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1125	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1126	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1127	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1128	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| (...) \|\| STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	1129	#if defined(STM32F100xB) \|\| defined (STM32F100xE)
AnnaBridge	171:3a7713b1edbc	1130	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1131	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1132	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1133	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1134	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1135	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1136	#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1137	#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1138	#endif /* STM32F100xB \|\| STM32F100xE */
AnnaBridge	171:3a7713b1edbc	1139	#ifdef STM32F100xE
AnnaBridge	171:3a7713b1edbc	1140	#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1141	#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1142	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1143	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1144	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1145	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1146	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1147	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1148	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1149	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1150	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1151	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1152	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1153	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1154	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1155	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1156	#endif /* STM32F100xE */
AnnaBridge	171:3a7713b1edbc	1157	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	1158	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1159	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1160	#endif /* STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	1161	#if defined(STM32F101xG) \|\| defined(STM32F103xG)
AnnaBridge	171:3a7713b1edbc	1162	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1163	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1164	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1165	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1166	#endif /* STM32F101xG \|\| STM32F103xG*/
AnnaBridge	171:3a7713b1edbc	1167
AnnaBridge	171:3a7713b1edbc	1168	/**
AnnaBridge	171:3a7713b1edbc	1169	* @}
AnnaBridge	171:3a7713b1edbc	1170	*/
AnnaBridge	171:3a7713b1edbc	1171
AnnaBridge	171:3a7713b1edbc	1172	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
AnnaBridge	171:3a7713b1edbc	1173	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
AnnaBridge	171:3a7713b1edbc	1174	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	171:3a7713b1edbc	1175	* is disabled and the application software has to enable this clock before
AnnaBridge	171:3a7713b1edbc	1176	* using it.
AnnaBridge	171:3a7713b1edbc	1177	* @{
AnnaBridge	171:3a7713b1edbc	1178	*/
AnnaBridge	171:3a7713b1edbc	1179
AnnaBridge	171:3a7713b1edbc	1180	#if defined(STM32F101xG) \|\| defined(STM32F103x6) \|\| defined(STM32F103xB)\
AnnaBridge	171:3a7713b1edbc	1181	\|\| defined(STM32F105xC) \|\| defined(STM32F107xC) \|\| defined(STM32F103xE)\
AnnaBridge	171:3a7713b1edbc	1182	\|\| defined(STM32F103xG)
AnnaBridge	171:3a7713b1edbc	1183	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	1184	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	1185	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
AnnaBridge	171:3a7713b1edbc	1186	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	1187	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
AnnaBridge	171:3a7713b1edbc	1188	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	1189	} while(0U)
AnnaBridge	171:3a7713b1edbc	1190
AnnaBridge	171:3a7713b1edbc	1191	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
AnnaBridge	171:3a7713b1edbc	1192	#endif /* STM32F101xG \|\| STM32F103x6 \|\| STM32F103xB \|\| STM32F105xC \|\| STM32F107xC \|\| STM32F103xE \|\| STM32F103xG */
AnnaBridge	171:3a7713b1edbc	1193
AnnaBridge	171:3a7713b1edbc	1194	#if defined(STM32F100xB) \|\| defined(STM32F100xE)
AnnaBridge	171:3a7713b1edbc	1195	#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	1196	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	1197	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
AnnaBridge	171:3a7713b1edbc	1198	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	1199	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
AnnaBridge	171:3a7713b1edbc	1200	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	1201	} while(0U)
AnnaBridge	171:3a7713b1edbc	1202
AnnaBridge	171:3a7713b1edbc	1203	#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	1204	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	1205	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
AnnaBridge	171:3a7713b1edbc	1206	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	1207	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
AnnaBridge	171:3a7713b1edbc	1208	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	1209	} while(0U)
AnnaBridge	171:3a7713b1edbc	1210
AnnaBridge	171:3a7713b1edbc	1211	#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	1212	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	1213	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
AnnaBridge	171:3a7713b1edbc	1214	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	1215	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
AnnaBridge	171:3a7713b1edbc	1216	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	1217	} while(0U)
AnnaBridge	171:3a7713b1edbc	1218
AnnaBridge	171:3a7713b1edbc	1219	#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
AnnaBridge	171:3a7713b1edbc	1220	#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
AnnaBridge	171:3a7713b1edbc	1221	#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
AnnaBridge	171:3a7713b1edbc	1222	#endif /* STM32F100xB \|\| STM32F100xE */
AnnaBridge	171:3a7713b1edbc	1223
AnnaBridge	171:3a7713b1edbc	1224	#if defined(STM32F100xE) \|\| defined(STM32F101xB) \|\| defined(STM32F101xE)\
AnnaBridge	171:3a7713b1edbc	1225	\|\| defined(STM32F101xG) \|\| defined(STM32F100xB) \|\| defined(STM32F103xB)\
AnnaBridge	171:3a7713b1edbc	1226	\|\| defined(STM32F103xE) \|\| defined(STM32F103xG) \|\| defined(STM32F105xC)\
AnnaBridge	171:3a7713b1edbc	1227	\|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	1228	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	1229	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	1230	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\
AnnaBridge	171:3a7713b1edbc	1231	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	1232	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\
AnnaBridge	171:3a7713b1edbc	1233	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	1234	} while(0U)
AnnaBridge	171:3a7713b1edbc	1235
AnnaBridge	171:3a7713b1edbc	1236	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPEEN))
AnnaBridge	171:3a7713b1edbc	1237	#endif /* STM32F101x6 \|\| STM32F101xB \|\| STM32F101xE \|\| (...) \|\| STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	1238
AnnaBridge	171:3a7713b1edbc	1239	#if defined(STM32F101xE) \|\| defined(STM32F103xE) \|\| defined(STM32F101xG)\
AnnaBridge	171:3a7713b1edbc	1240	\|\| defined(STM32F103xG)
AnnaBridge	171:3a7713b1edbc	1241	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	1242	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	1243	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
AnnaBridge	171:3a7713b1edbc	1244	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	1245	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
AnnaBridge	171:3a7713b1edbc	1246	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	1247	} while(0U)
AnnaBridge	171:3a7713b1edbc	1248
AnnaBridge	171:3a7713b1edbc	1249	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	1250	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	1251	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
AnnaBridge	171:3a7713b1edbc	1252	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	1253	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
AnnaBridge	171:3a7713b1edbc	1254	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	1255	} while(0U)
AnnaBridge	171:3a7713b1edbc	1256
AnnaBridge	171:3a7713b1edbc	1257	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))
AnnaBridge	171:3a7713b1edbc	1258	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))
AnnaBridge	171:3a7713b1edbc	1259	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| STM32F103xG*/
AnnaBridge	171:3a7713b1edbc	1260
AnnaBridge	171:3a7713b1edbc	1261	#if defined(STM32F103xE) \|\| defined(STM32F103xG)
AnnaBridge	171:3a7713b1edbc	1262	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	1263	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	1264	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
AnnaBridge	171:3a7713b1edbc	1265	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	1266	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
AnnaBridge	171:3a7713b1edbc	1267	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	1268	} while(0U)
AnnaBridge	171:3a7713b1edbc	1269
AnnaBridge	171:3a7713b1edbc	1270	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	1271	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	1272	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
AnnaBridge	171:3a7713b1edbc	1273	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	1274	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
AnnaBridge	171:3a7713b1edbc	1275	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	1276	} while(0U)
AnnaBridge	171:3a7713b1edbc	1277
AnnaBridge	171:3a7713b1edbc	1278	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
AnnaBridge	171:3a7713b1edbc	1279	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
AnnaBridge	171:3a7713b1edbc	1280	#endif /* STM32F103xE \|\| STM32F103xG */
AnnaBridge	171:3a7713b1edbc	1281
AnnaBridge	171:3a7713b1edbc	1282	#if defined(STM32F100xE)
AnnaBridge	171:3a7713b1edbc	1283	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	1284	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	1285	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
AnnaBridge	171:3a7713b1edbc	1286	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	1287	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
AnnaBridge	171:3a7713b1edbc	1288	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	1289	} while(0U)
AnnaBridge	171:3a7713b1edbc	1290
AnnaBridge	171:3a7713b1edbc	1291	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	1292	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	1293	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
AnnaBridge	171:3a7713b1edbc	1294	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	1295	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
AnnaBridge	171:3a7713b1edbc	1296	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	1297	} while(0U)
AnnaBridge	171:3a7713b1edbc	1298
AnnaBridge	171:3a7713b1edbc	1299	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))
AnnaBridge	171:3a7713b1edbc	1300	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))
AnnaBridge	171:3a7713b1edbc	1301	#endif /* STM32F100xE */
AnnaBridge	171:3a7713b1edbc	1302
AnnaBridge	171:3a7713b1edbc	1303	#if defined(STM32F101xG) \|\| defined(STM32F103xG)
AnnaBridge	171:3a7713b1edbc	1304	#define __HAL_RCC_TIM9_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	1305	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	1306	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
AnnaBridge	171:3a7713b1edbc	1307	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	1308	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
AnnaBridge	171:3a7713b1edbc	1309	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	1310	} while(0U)
AnnaBridge	171:3a7713b1edbc	1311
AnnaBridge	171:3a7713b1edbc	1312	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	1313	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	1314	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge	171:3a7713b1edbc	1315	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	1316	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
AnnaBridge	171:3a7713b1edbc	1317	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	1318	} while(0U)
AnnaBridge	171:3a7713b1edbc	1319
AnnaBridge	171:3a7713b1edbc	1320	#define __HAL_RCC_TIM11_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	1321	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	1322	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
AnnaBridge	171:3a7713b1edbc	1323	/* Delay after an RCC peripheral clock enabling */ \
AnnaBridge	171:3a7713b1edbc	1324	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
AnnaBridge	171:3a7713b1edbc	1325	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	1326	} while(0U)
AnnaBridge	171:3a7713b1edbc	1327
AnnaBridge	171:3a7713b1edbc	1328	#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
AnnaBridge	171:3a7713b1edbc	1329	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
AnnaBridge	171:3a7713b1edbc	1330	#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
AnnaBridge	171:3a7713b1edbc	1331	#endif /* STM32F101xG \|\| STM32F103xG */
AnnaBridge	171:3a7713b1edbc	1332
AnnaBridge	171:3a7713b1edbc	1333	/**
AnnaBridge	171:3a7713b1edbc	1334	* @}
AnnaBridge	171:3a7713b1edbc	1335	*/
AnnaBridge	171:3a7713b1edbc	1336
AnnaBridge	171:3a7713b1edbc	1337	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
AnnaBridge	171:3a7713b1edbc	1338	* @brief Get the enable or disable status of the APB2 peripheral clock.
AnnaBridge	171:3a7713b1edbc	1339	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	171:3a7713b1edbc	1340	* is disabled and the application software has to enable this clock before
AnnaBridge	171:3a7713b1edbc	1341	* using it.
AnnaBridge	171:3a7713b1edbc	1342	* @{
AnnaBridge	171:3a7713b1edbc	1343	*/
AnnaBridge	171:3a7713b1edbc	1344
AnnaBridge	171:3a7713b1edbc	1345	#if defined(STM32F101xG) \|\| defined(STM32F103x6) \|\| defined(STM32F103xB)\
AnnaBridge	171:3a7713b1edbc	1346	\|\| defined(STM32F105xC) \|\| defined(STM32F107xC) \|\| defined(STM32F103xE)\
AnnaBridge	171:3a7713b1edbc	1347	\|\| defined(STM32F103xG)
AnnaBridge	171:3a7713b1edbc	1348	#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1349	#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1350	#endif /* STM32F101xG \|\| STM32F103x6 \|\| STM32F103xB \|\| STM32F105xC \|\| STM32F107xC \|\| STM32F103xE \|\| STM32F103xG */
AnnaBridge	171:3a7713b1edbc	1351	#if defined(STM32F100xB) \|\| defined(STM32F100xE)
AnnaBridge	171:3a7713b1edbc	1352	#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1353	#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1354	#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1355	#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1356	#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1357	#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1358	#endif /* STM32F100xB \|\| STM32F100xE */
AnnaBridge	171:3a7713b1edbc	1359	#if defined(STM32F100xE) \|\| defined(STM32F101xB) \|\| defined(STM32F101xE)\
AnnaBridge	171:3a7713b1edbc	1360	\|\| defined(STM32F101xG) \|\| defined(STM32F100xB) \|\| defined(STM32F103xB)\
AnnaBridge	171:3a7713b1edbc	1361	\|\| defined(STM32F103xE) \|\| defined(STM32F103xG) \|\| defined(STM32F105xC)\
AnnaBridge	171:3a7713b1edbc	1362	\|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	1363	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1364	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1365	#endif /* STM32F101x6 \|\| STM32F101xB \|\| STM32F101xE \|\| (...) \|\| STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	1366	#if defined(STM32F101xE) \|\| defined(STM32F103xE) \|\| defined(STM32F101xG)\
AnnaBridge	171:3a7713b1edbc	1367	\|\| defined(STM32F103xG)
AnnaBridge	171:3a7713b1edbc	1368	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1369	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1370	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1371	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1372	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| STM32F103xG*/
AnnaBridge	171:3a7713b1edbc	1373	#if defined(STM32F103xE) \|\| defined(STM32F103xG)
AnnaBridge	171:3a7713b1edbc	1374	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1375	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1376	#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1377	#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1378	#endif /* STM32F103xE \|\| STM32F103xG */
AnnaBridge	171:3a7713b1edbc	1379	#if defined(STM32F100xE)
AnnaBridge	171:3a7713b1edbc	1380	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1381	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1382	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1383	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1384	#endif /* STM32F100xE */
AnnaBridge	171:3a7713b1edbc	1385	#if defined(STM32F101xG) \|\| defined(STM32F103xG)
AnnaBridge	171:3a7713b1edbc	1386	#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1387	#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1388	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1389	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1390	#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	1391	#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	1392	#endif /* STM32F101xG \|\| STM32F103xG */
AnnaBridge	171:3a7713b1edbc	1393
AnnaBridge	171:3a7713b1edbc	1394	/**
AnnaBridge	171:3a7713b1edbc	1395	* @}
AnnaBridge	171:3a7713b1edbc	1396	*/
AnnaBridge	171:3a7713b1edbc	1397
AnnaBridge	171:3a7713b1edbc	1398	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	1399	/** @defgroup RCCEx_Peripheral_Clock_Force_Release Peripheral Clock Force Release
AnnaBridge	171:3a7713b1edbc	1400	* @brief Force or release AHB peripheral reset.
AnnaBridge	171:3a7713b1edbc	1401	* @{
AnnaBridge	171:3a7713b1edbc	1402	*/
AnnaBridge	171:3a7713b1edbc	1403	#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU)
AnnaBridge	171:3a7713b1edbc	1404	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_OTGFSRST))
AnnaBridge	171:3a7713b1edbc	1405	#if defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	1406	#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_ETHMACRST))
AnnaBridge	171:3a7713b1edbc	1407	#endif /* STM32F107xC */
AnnaBridge	171:3a7713b1edbc	1408
AnnaBridge	171:3a7713b1edbc	1409	#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
AnnaBridge	171:3a7713b1edbc	1410	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_OTGFSRST))
AnnaBridge	171:3a7713b1edbc	1411	#if defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	1412	#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ETHMACRST))
AnnaBridge	171:3a7713b1edbc	1413	#endif /* STM32F107xC */
AnnaBridge	171:3a7713b1edbc	1414
AnnaBridge	171:3a7713b1edbc	1415	/**
AnnaBridge	171:3a7713b1edbc	1416	* @}
AnnaBridge	171:3a7713b1edbc	1417	*/
AnnaBridge	171:3a7713b1edbc	1418	#endif /* STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	1419
AnnaBridge	171:3a7713b1edbc	1420	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
AnnaBridge	171:3a7713b1edbc	1421	* @brief Force or release APB1 peripheral reset.
AnnaBridge	171:3a7713b1edbc	1422	* @{
AnnaBridge	171:3a7713b1edbc	1423	*/
AnnaBridge	171:3a7713b1edbc	1424
AnnaBridge	171:3a7713b1edbc	1425	#if defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE)\
AnnaBridge	171:3a7713b1edbc	1426	\|\| defined(STM32F103xG) \|\| defined(STM32F105xC) \|\|defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	1427	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
AnnaBridge	171:3a7713b1edbc	1428
AnnaBridge	171:3a7713b1edbc	1429	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
AnnaBridge	171:3a7713b1edbc	1430	#endif /* STM32F103x6 \|\| STM32F103xB \|\| STM32F103xE \|\| STM32F103xG \|\| STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	1431
AnnaBridge	171:3a7713b1edbc	1432	#if defined(STM32F100xB) \|\| defined(STM32F100xE) \|\| defined(STM32F101xB)\
AnnaBridge	171:3a7713b1edbc	1433	\|\| defined(STM32F101xE) \|\| defined(STM32F101xG) \|\| defined(STM32F102xB)\
AnnaBridge	171:3a7713b1edbc	1434	\|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG)\
AnnaBridge	171:3a7713b1edbc	1435	\|\| defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	1436	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
AnnaBridge	171:3a7713b1edbc	1437	#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
AnnaBridge	171:3a7713b1edbc	1438	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
AnnaBridge	171:3a7713b1edbc	1439	#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
AnnaBridge	171:3a7713b1edbc	1440
AnnaBridge	171:3a7713b1edbc	1441	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
AnnaBridge	171:3a7713b1edbc	1442	#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
AnnaBridge	171:3a7713b1edbc	1443	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
AnnaBridge	171:3a7713b1edbc	1444	#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
AnnaBridge	171:3a7713b1edbc	1445	#endif /* STM32F100xB \|\| STM32F101xB \|\| STM32F101xE \|\| (...) \|\| STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	1446
AnnaBridge	171:3a7713b1edbc	1447	#if defined(STM32F102x6) \|\| defined(STM32F102xB) \|\| defined(STM32F103x6)\
AnnaBridge	171:3a7713b1edbc	1448	\|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG)
AnnaBridge	171:3a7713b1edbc	1449	#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USBRST))
AnnaBridge	171:3a7713b1edbc	1450	#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
AnnaBridge	171:3a7713b1edbc	1451	#endif /* STM32F102x6 \|\| STM32F102xB \|\| STM32F103x6 \|\| STM32F103xB \|\| STM32F103xE \|\| STM32F103xG */
AnnaBridge	171:3a7713b1edbc	1452
AnnaBridge	171:3a7713b1edbc	1453	#if defined(STM32F101xE) \|\| defined(STM32F103xE) \|\| defined(STM32F101xG)\
AnnaBridge	171:3a7713b1edbc	1454	\|\| defined(STM32F103xG) \|\| defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	1455	#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM5RST))
AnnaBridge	171:3a7713b1edbc	1456	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
AnnaBridge	171:3a7713b1edbc	1457	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
AnnaBridge	171:3a7713b1edbc	1458	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
AnnaBridge	171:3a7713b1edbc	1459	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
AnnaBridge	171:3a7713b1edbc	1460	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
AnnaBridge	171:3a7713b1edbc	1461	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
AnnaBridge	171:3a7713b1edbc	1462
AnnaBridge	171:3a7713b1edbc	1463	#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
AnnaBridge	171:3a7713b1edbc	1464	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
AnnaBridge	171:3a7713b1edbc	1465	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
AnnaBridge	171:3a7713b1edbc	1466	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
AnnaBridge	171:3a7713b1edbc	1467	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
AnnaBridge	171:3a7713b1edbc	1468	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
AnnaBridge	171:3a7713b1edbc	1469	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
AnnaBridge	171:3a7713b1edbc	1470	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| (...) \|\| STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	1471
AnnaBridge	171:3a7713b1edbc	1472	#if defined(STM32F100xB) \|\| defined (STM32F100xE)
AnnaBridge	171:3a7713b1edbc	1473	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
AnnaBridge	171:3a7713b1edbc	1474	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
AnnaBridge	171:3a7713b1edbc	1475	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
AnnaBridge	171:3a7713b1edbc	1476	#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
AnnaBridge	171:3a7713b1edbc	1477
AnnaBridge	171:3a7713b1edbc	1478	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
AnnaBridge	171:3a7713b1edbc	1479	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
AnnaBridge	171:3a7713b1edbc	1480	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
AnnaBridge	171:3a7713b1edbc	1481	#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
AnnaBridge	171:3a7713b1edbc	1482	#endif /* STM32F100xB \|\| STM32F100xE */
AnnaBridge	171:3a7713b1edbc	1483
AnnaBridge	171:3a7713b1edbc	1484	#if defined (STM32F100xE)
AnnaBridge	171:3a7713b1edbc	1485	#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM5RST))
AnnaBridge	171:3a7713b1edbc	1486	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
AnnaBridge	171:3a7713b1edbc	1487	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
AnnaBridge	171:3a7713b1edbc	1488	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
AnnaBridge	171:3a7713b1edbc	1489	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
AnnaBridge	171:3a7713b1edbc	1490	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
AnnaBridge	171:3a7713b1edbc	1491	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
AnnaBridge	171:3a7713b1edbc	1492
AnnaBridge	171:3a7713b1edbc	1493	#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
AnnaBridge	171:3a7713b1edbc	1494	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
AnnaBridge	171:3a7713b1edbc	1495	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
AnnaBridge	171:3a7713b1edbc	1496	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
AnnaBridge	171:3a7713b1edbc	1497	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
AnnaBridge	171:3a7713b1edbc	1498	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
AnnaBridge	171:3a7713b1edbc	1499	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
AnnaBridge	171:3a7713b1edbc	1500	#endif /* STM32F100xE */
AnnaBridge	171:3a7713b1edbc	1501
AnnaBridge	171:3a7713b1edbc	1502	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	1503	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
AnnaBridge	171:3a7713b1edbc	1504
AnnaBridge	171:3a7713b1edbc	1505	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
AnnaBridge	171:3a7713b1edbc	1506	#endif /* STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	1507
AnnaBridge	171:3a7713b1edbc	1508	#if defined(STM32F101xG) \|\| defined(STM32F103xG)
AnnaBridge	171:3a7713b1edbc	1509	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
AnnaBridge	171:3a7713b1edbc	1510	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
AnnaBridge	171:3a7713b1edbc	1511	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
AnnaBridge	171:3a7713b1edbc	1512
AnnaBridge	171:3a7713b1edbc	1513	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
AnnaBridge	171:3a7713b1edbc	1514	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
AnnaBridge	171:3a7713b1edbc	1515	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
AnnaBridge	171:3a7713b1edbc	1516	#endif /* STM32F101xG \|\| STM32F103xG */
AnnaBridge	171:3a7713b1edbc	1517
AnnaBridge	171:3a7713b1edbc	1518	/**
AnnaBridge	171:3a7713b1edbc	1519	* @}
AnnaBridge	171:3a7713b1edbc	1520	*/
AnnaBridge	171:3a7713b1edbc	1521
AnnaBridge	171:3a7713b1edbc	1522	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
AnnaBridge	171:3a7713b1edbc	1523	* @brief Force or release APB2 peripheral reset.
AnnaBridge	171:3a7713b1edbc	1524	* @{
AnnaBridge	171:3a7713b1edbc	1525	*/
AnnaBridge	171:3a7713b1edbc	1526
AnnaBridge	171:3a7713b1edbc	1527	#if defined(STM32F101xG) \|\| defined(STM32F103x6) \|\| defined(STM32F103xB)\
AnnaBridge	171:3a7713b1edbc	1528	\|\| defined(STM32F105xC) \|\| defined(STM32F107xC) \|\| defined(STM32F103xE)\
AnnaBridge	171:3a7713b1edbc	1529	\|\| defined(STM32F103xG)
AnnaBridge	171:3a7713b1edbc	1530	#define __HAL_RCC_ADC2_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADC2RST))
AnnaBridge	171:3a7713b1edbc	1531
AnnaBridge	171:3a7713b1edbc	1532	#define __HAL_RCC_ADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST))
AnnaBridge	171:3a7713b1edbc	1533	#endif /* STM32F101xG \|\| STM32F103x6 \|\| STM32F103xB \|\| STM32F105xC \|\| STM32F107xC \|\| STM32F103xE \|\| STM32F103xG */
AnnaBridge	171:3a7713b1edbc	1534
AnnaBridge	171:3a7713b1edbc	1535	#if defined(STM32F100xB) \|\| defined(STM32F100xE)
AnnaBridge	171:3a7713b1edbc	1536	#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM15RST))
AnnaBridge	171:3a7713b1edbc	1537	#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM16RST))
AnnaBridge	171:3a7713b1edbc	1538	#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM17RST))
AnnaBridge	171:3a7713b1edbc	1539
AnnaBridge	171:3a7713b1edbc	1540	#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
AnnaBridge	171:3a7713b1edbc	1541	#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
AnnaBridge	171:3a7713b1edbc	1542	#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
AnnaBridge	171:3a7713b1edbc	1543	#endif /* STM32F100xB \|\| STM32F100xE */
AnnaBridge	171:3a7713b1edbc	1544
AnnaBridge	171:3a7713b1edbc	1545	#if defined(STM32F100xE) \|\| defined(STM32F101xB) \|\| defined(STM32F101xE)\
AnnaBridge	171:3a7713b1edbc	1546	\|\| defined(STM32F101xG) \|\| defined(STM32F100xB) \|\| defined(STM32F103xB)\
AnnaBridge	171:3a7713b1edbc	1547	\|\| defined(STM32F103xE) \|\| defined(STM32F103xG) \|\| defined(STM32F105xC)\
AnnaBridge	171:3a7713b1edbc	1548	\|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	1549	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPERST))
AnnaBridge	171:3a7713b1edbc	1550
AnnaBridge	171:3a7713b1edbc	1551	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST))
AnnaBridge	171:3a7713b1edbc	1552	#endif /* STM32F101x6 \|\| STM32F101xB \|\| STM32F101xE \|\| (...) \|\| STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	1553
AnnaBridge	171:3a7713b1edbc	1554	#if defined(STM32F101xE) \|\| defined(STM32F103xE) \|\| defined(STM32F101xG)\
AnnaBridge	171:3a7713b1edbc	1555	\|\| defined(STM32F103xG)
AnnaBridge	171:3a7713b1edbc	1556	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPFRST))
AnnaBridge	171:3a7713b1edbc	1557	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPGRST))
AnnaBridge	171:3a7713b1edbc	1558
AnnaBridge	171:3a7713b1edbc	1559	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))
AnnaBridge	171:3a7713b1edbc	1560	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))
AnnaBridge	171:3a7713b1edbc	1561	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| STM32F103xG*/
AnnaBridge	171:3a7713b1edbc	1562
AnnaBridge	171:3a7713b1edbc	1563	#if defined(STM32F103xE) \|\| defined(STM32F103xG)
AnnaBridge	171:3a7713b1edbc	1564	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
AnnaBridge	171:3a7713b1edbc	1565	#define __HAL_RCC_ADC3_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADC3RST))
AnnaBridge	171:3a7713b1edbc	1566
AnnaBridge	171:3a7713b1edbc	1567	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
AnnaBridge	171:3a7713b1edbc	1568	#define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC3RST))
AnnaBridge	171:3a7713b1edbc	1569	#endif /* STM32F103xE \|\| STM32F103xG */
AnnaBridge	171:3a7713b1edbc	1570
AnnaBridge	171:3a7713b1edbc	1571	#if defined(STM32F100xE)
AnnaBridge	171:3a7713b1edbc	1572	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPFRST))
AnnaBridge	171:3a7713b1edbc	1573	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPGRST))
AnnaBridge	171:3a7713b1edbc	1574
AnnaBridge	171:3a7713b1edbc	1575	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))
AnnaBridge	171:3a7713b1edbc	1576	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))
AnnaBridge	171:3a7713b1edbc	1577	#endif /* STM32F100xE */
AnnaBridge	171:3a7713b1edbc	1578
AnnaBridge	171:3a7713b1edbc	1579	#if defined(STM32F101xG) \|\| defined(STM32F103xG)
AnnaBridge	171:3a7713b1edbc	1580	#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM9RST))
AnnaBridge	171:3a7713b1edbc	1581	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
AnnaBridge	171:3a7713b1edbc	1582	#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM11RST))
AnnaBridge	171:3a7713b1edbc	1583
AnnaBridge	171:3a7713b1edbc	1584	#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
AnnaBridge	171:3a7713b1edbc	1585	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
AnnaBridge	171:3a7713b1edbc	1586	#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
AnnaBridge	171:3a7713b1edbc	1587	#endif /* STM32F101xG \|\| STM32F103xG*/
AnnaBridge	171:3a7713b1edbc	1588
AnnaBridge	171:3a7713b1edbc	1589	/**
AnnaBridge	171:3a7713b1edbc	1590	* @}
AnnaBridge	171:3a7713b1edbc	1591	*/
AnnaBridge	171:3a7713b1edbc	1592
AnnaBridge	171:3a7713b1edbc	1593	/** @defgroup RCCEx_HSE_Configuration HSE Configuration
AnnaBridge	171:3a7713b1edbc	1594	* @{
AnnaBridge	171:3a7713b1edbc	1595	*/
AnnaBridge	171:3a7713b1edbc	1596
AnnaBridge	171:3a7713b1edbc	1597	#if defined(STM32F105xC) \|\| defined(STM32F107xC) \|\| defined(STM32F100xB)\
AnnaBridge	171:3a7713b1edbc	1598	\|\| defined(STM32F100xE)
AnnaBridge	171:3a7713b1edbc	1599	/**
AnnaBridge	171:3a7713b1edbc	1600	* @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
AnnaBridge	171:3a7713b1edbc	1601	* @note Predivision factor can not be changed if PLL is used as system clock
AnnaBridge	171:3a7713b1edbc	1602	* In this case, you have to select another source of the system clock, disable the PLL and
AnnaBridge	171:3a7713b1edbc	1603	* then change the HSE predivision factor.
AnnaBridge	171:3a7713b1edbc	1604	* @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.
AnnaBridge	171:3a7713b1edbc	1605	* This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
AnnaBridge	171:3a7713b1edbc	1606	*/
AnnaBridge	171:3a7713b1edbc	1607	#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (uint32_t)(__HSE_PREDIV_VALUE__))
AnnaBridge	171:3a7713b1edbc	1608	#else
AnnaBridge	171:3a7713b1edbc	1609	/**
AnnaBridge	171:3a7713b1edbc	1610	* @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
AnnaBridge	171:3a7713b1edbc	1611	* @note Predivision factor can not be changed if PLL is used as system clock
AnnaBridge	171:3a7713b1edbc	1612	* In this case, you have to select another source of the system clock, disable the PLL and
AnnaBridge	171:3a7713b1edbc	1613	* then change the HSE predivision factor.
AnnaBridge	171:3a7713b1edbc	1614	* @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.
AnnaBridge	171:3a7713b1edbc	1615	* This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV2.
AnnaBridge	171:3a7713b1edbc	1616	*/
AnnaBridge	171:3a7713b1edbc	1617	#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \
AnnaBridge	171:3a7713b1edbc	1618	MODIFY_REG(RCC->CFGR,RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__))
AnnaBridge	171:3a7713b1edbc	1619
AnnaBridge	171:3a7713b1edbc	1620	#endif /* STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	1621
AnnaBridge	171:3a7713b1edbc	1622	#if defined(STM32F105xC) \|\| defined(STM32F107xC) \|\| defined(STM32F100xB)\
AnnaBridge	171:3a7713b1edbc	1623	\|\| defined(STM32F100xE)
AnnaBridge	171:3a7713b1edbc	1624	/**
AnnaBridge	171:3a7713b1edbc	1625	* @brief Macro to get prediv1 factor for PLL.
AnnaBridge	171:3a7713b1edbc	1626	*/
AnnaBridge	171:3a7713b1edbc	1627	#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1)
AnnaBridge	171:3a7713b1edbc	1628
AnnaBridge	171:3a7713b1edbc	1629	#else
AnnaBridge	171:3a7713b1edbc	1630	/**
AnnaBridge	171:3a7713b1edbc	1631	* @brief Macro to get prediv1 factor for PLL.
AnnaBridge	171:3a7713b1edbc	1632	*/
AnnaBridge	171:3a7713b1edbc	1633	#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE)
AnnaBridge	171:3a7713b1edbc	1634
AnnaBridge	171:3a7713b1edbc	1635	#endif /* STM32F105xC \|\| STM32F107xC \|\| STM32F100xB \|\| STM32F100xE */
AnnaBridge	171:3a7713b1edbc	1636
AnnaBridge	171:3a7713b1edbc	1637	/**
AnnaBridge	171:3a7713b1edbc	1638	* @}
AnnaBridge	171:3a7713b1edbc	1639	*/
AnnaBridge	171:3a7713b1edbc	1640
AnnaBridge	171:3a7713b1edbc	1641	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	1642	/** @defgroup RCCEx_PLLI2S_Configuration PLLI2S Configuration
AnnaBridge	171:3a7713b1edbc	1643	* @{
AnnaBridge	171:3a7713b1edbc	1644	*/
AnnaBridge	171:3a7713b1edbc	1645
AnnaBridge	171:3a7713b1edbc	1646	/** @brief Macros to enable the main PLLI2S.
AnnaBridge	171:3a7713b1edbc	1647	* @note After enabling the main PLLI2S, the application software should wait on
AnnaBridge	171:3a7713b1edbc	1648	* PLLI2SRDY flag to be set indicating that PLLI2S clock is stable and can
AnnaBridge	171:3a7713b1edbc	1649	* be used as system clock source.
AnnaBridge	171:3a7713b1edbc	1650	* @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
AnnaBridge	171:3a7713b1edbc	1651	*/
AnnaBridge	171:3a7713b1edbc	1652	#define __HAL_RCC_PLLI2S_ENABLE() ((__IO uint32_t ) RCC_CR_PLLI2SON_BB = ENABLE)
AnnaBridge	171:3a7713b1edbc	1653
AnnaBridge	171:3a7713b1edbc	1654	/** @brief Macros to disable the main PLLI2S.
AnnaBridge	171:3a7713b1edbc	1655	* @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
AnnaBridge	171:3a7713b1edbc	1656	*/
AnnaBridge	171:3a7713b1edbc	1657	#define __HAL_RCC_PLLI2S_DISABLE() ((__IO uint32_t ) RCC_CR_PLLI2SON_BB = DISABLE)
AnnaBridge	171:3a7713b1edbc	1658
AnnaBridge	171:3a7713b1edbc	1659	/** @brief macros to configure the main PLLI2S multiplication factor.
AnnaBridge	171:3a7713b1edbc	1660	* @note This function must be used only when the main PLLI2S is disabled.
AnnaBridge	171:3a7713b1edbc	1661	*
AnnaBridge	171:3a7713b1edbc	1662	* @param __PLLI2SMUL__ specifies the multiplication factor for PLLI2S VCO output clock
AnnaBridge	171:3a7713b1edbc	1663	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1664	* @arg @ref RCC_PLLI2S_MUL8 PLLI2SVCO = PLLI2S clock entry x 8
AnnaBridge	171:3a7713b1edbc	1665	* @arg @ref RCC_PLLI2S_MUL9 PLLI2SVCO = PLLI2S clock entry x 9
AnnaBridge	171:3a7713b1edbc	1666	* @arg @ref RCC_PLLI2S_MUL10 PLLI2SVCO = PLLI2S clock entry x 10
AnnaBridge	171:3a7713b1edbc	1667	* @arg @ref RCC_PLLI2S_MUL11 PLLI2SVCO = PLLI2S clock entry x 11
AnnaBridge	171:3a7713b1edbc	1668	* @arg @ref RCC_PLLI2S_MUL12 PLLI2SVCO = PLLI2S clock entry x 12
AnnaBridge	171:3a7713b1edbc	1669	* @arg @ref RCC_PLLI2S_MUL13 PLLI2SVCO = PLLI2S clock entry x 13
AnnaBridge	171:3a7713b1edbc	1670	* @arg @ref RCC_PLLI2S_MUL14 PLLI2SVCO = PLLI2S clock entry x 14
AnnaBridge	171:3a7713b1edbc	1671	* @arg @ref RCC_PLLI2S_MUL16 PLLI2SVCO = PLLI2S clock entry x 16
AnnaBridge	171:3a7713b1edbc	1672	* @arg @ref RCC_PLLI2S_MUL20 PLLI2SVCO = PLLI2S clock entry x 20
AnnaBridge	171:3a7713b1edbc	1673	*
AnnaBridge	171:3a7713b1edbc	1674	*/
AnnaBridge	171:3a7713b1edbc	1675	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SMUL__)\
AnnaBridge	171:3a7713b1edbc	1676	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL3MUL,(__PLLI2SMUL__))
AnnaBridge	171:3a7713b1edbc	1677
AnnaBridge	171:3a7713b1edbc	1678	/**
AnnaBridge	171:3a7713b1edbc	1679	* @}
AnnaBridge	171:3a7713b1edbc	1680	*/
AnnaBridge	171:3a7713b1edbc	1681
AnnaBridge	171:3a7713b1edbc	1682	#endif /* STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	1683
AnnaBridge	171:3a7713b1edbc	1684	/** @defgroup RCCEx_Peripheral_Configuration Peripheral Configuration
AnnaBridge	171:3a7713b1edbc	1685	* @brief Macros to configure clock source of different peripherals.
AnnaBridge	171:3a7713b1edbc	1686	* @{
AnnaBridge	171:3a7713b1edbc	1687	*/
AnnaBridge	171:3a7713b1edbc	1688
AnnaBridge	171:3a7713b1edbc	1689	#if defined(STM32F102x6) \|\| defined(STM32F102xB) \|\| defined(STM32F103x6)\
AnnaBridge	171:3a7713b1edbc	1690	\|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG)
AnnaBridge	171:3a7713b1edbc	1691	/** @brief Macro to configure the USB clock.
AnnaBridge	171:3a7713b1edbc	1692	* @param __USBCLKSOURCE__ specifies the USB clock source.
AnnaBridge	171:3a7713b1edbc	1693	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1694	* @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock
AnnaBridge	171:3a7713b1edbc	1695	* @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock
AnnaBridge	171:3a7713b1edbc	1696	*/
AnnaBridge	171:3a7713b1edbc	1697	#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
AnnaBridge	171:3a7713b1edbc	1698	MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__))
AnnaBridge	171:3a7713b1edbc	1699
AnnaBridge	171:3a7713b1edbc	1700	/** @brief Macro to get the USB clock (USBCLK).
AnnaBridge	171:3a7713b1edbc	1701	* @retval The clock source can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1702	* @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock
AnnaBridge	171:3a7713b1edbc	1703	* @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock
AnnaBridge	171:3a7713b1edbc	1704	*/
AnnaBridge	171:3a7713b1edbc	1705	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
AnnaBridge	171:3a7713b1edbc	1706
AnnaBridge	171:3a7713b1edbc	1707	#endif /* STM32F102x6 \|\| STM32F102xB \|\| STM32F103x6 \|\| STM32F103xB \|\| STM32F103xE \|\| STM32F103xG */
AnnaBridge	171:3a7713b1edbc	1708
AnnaBridge	171:3a7713b1edbc	1709	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	1710
AnnaBridge	171:3a7713b1edbc	1711	/** @brief Macro to configure the USB OTSclock.
AnnaBridge	171:3a7713b1edbc	1712	* @param __USBCLKSOURCE__ specifies the USB clock source.
AnnaBridge	171:3a7713b1edbc	1713	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1714	* @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock
AnnaBridge	171:3a7713b1edbc	1715	* @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock
AnnaBridge	171:3a7713b1edbc	1716	*/
AnnaBridge	171:3a7713b1edbc	1717	#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
AnnaBridge	171:3a7713b1edbc	1718	MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, (uint32_t)(__USBCLKSOURCE__))
AnnaBridge	171:3a7713b1edbc	1719
AnnaBridge	171:3a7713b1edbc	1720	/** @brief Macro to get the USB clock (USBCLK).
AnnaBridge	171:3a7713b1edbc	1721	* @retval The clock source can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1722	* @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock
AnnaBridge	171:3a7713b1edbc	1723	* @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock
AnnaBridge	171:3a7713b1edbc	1724	*/
AnnaBridge	171:3a7713b1edbc	1725	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_OTGFSPRE)))
AnnaBridge	171:3a7713b1edbc	1726
AnnaBridge	171:3a7713b1edbc	1727	#endif /* STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	1728
AnnaBridge	171:3a7713b1edbc	1729	/** @brief Macro to configure the ADCx clock (x=1 to 3 depending on devices).
AnnaBridge	171:3a7713b1edbc	1730	* @param __ADCCLKSOURCE__ specifies the ADC clock source.
AnnaBridge	171:3a7713b1edbc	1731	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1732	* @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock
AnnaBridge	171:3a7713b1edbc	1733	* @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock
AnnaBridge	171:3a7713b1edbc	1734	* @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock
AnnaBridge	171:3a7713b1edbc	1735	* @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock
AnnaBridge	171:3a7713b1edbc	1736	*/
AnnaBridge	171:3a7713b1edbc	1737	#define __HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) \
AnnaBridge	171:3a7713b1edbc	1738	MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__))
AnnaBridge	171:3a7713b1edbc	1739
AnnaBridge	171:3a7713b1edbc	1740	/** @brief Macro to get the ADC clock (ADCxCLK, x=1 to 3 depending on devices).
AnnaBridge	171:3a7713b1edbc	1741	* @retval The clock source can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1742	* @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock
AnnaBridge	171:3a7713b1edbc	1743	* @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock
AnnaBridge	171:3a7713b1edbc	1744	* @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock
AnnaBridge	171:3a7713b1edbc	1745	* @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock
AnnaBridge	171:3a7713b1edbc	1746	*/
AnnaBridge	171:3a7713b1edbc	1747	#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
AnnaBridge	171:3a7713b1edbc	1748
AnnaBridge	171:3a7713b1edbc	1749	/**
AnnaBridge	171:3a7713b1edbc	1750	* @}
AnnaBridge	171:3a7713b1edbc	1751	*/
AnnaBridge	171:3a7713b1edbc	1752
AnnaBridge	171:3a7713b1edbc	1753	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	1754
AnnaBridge	171:3a7713b1edbc	1755	/** @addtogroup RCCEx_HSE_Configuration
AnnaBridge	171:3a7713b1edbc	1756	* @{
AnnaBridge	171:3a7713b1edbc	1757	*/
AnnaBridge	171:3a7713b1edbc	1758
AnnaBridge	171:3a7713b1edbc	1759	/**
AnnaBridge	171:3a7713b1edbc	1760	* @brief Macro to configure the PLL2 & PLLI2S Predivision factor.
AnnaBridge	171:3a7713b1edbc	1761	* @note Predivision factor can not be changed if PLL2 is used indirectly as system clock
AnnaBridge	171:3a7713b1edbc	1762	* In this case, you have to select another source of the system clock, disable the PLL2 and PLLI2S and
AnnaBridge	171:3a7713b1edbc	1763	* then change the PREDIV2 factor.
AnnaBridge	171:3a7713b1edbc	1764	* @param __HSE_PREDIV2_VALUE__ specifies the PREDIV2 value applied to PLL2 & PLLI2S.
AnnaBridge	171:3a7713b1edbc	1765	* This parameter must be a number between RCC_HSE_PREDIV2_DIV1 and RCC_HSE_PREDIV2_DIV16.
AnnaBridge	171:3a7713b1edbc	1766	*/
AnnaBridge	171:3a7713b1edbc	1767	#define __HAL_RCC_HSE_PREDIV2_CONFIG(__HSE_PREDIV2_VALUE__) \
AnnaBridge	171:3a7713b1edbc	1768	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2, (uint32_t)(__HSE_PREDIV2_VALUE__))
AnnaBridge	171:3a7713b1edbc	1769
AnnaBridge	171:3a7713b1edbc	1770	/**
AnnaBridge	171:3a7713b1edbc	1771	* @brief Macro to get prediv2 factor for PLL2 & PLL3.
AnnaBridge	171:3a7713b1edbc	1772	*/
AnnaBridge	171:3a7713b1edbc	1773	#define __HAL_RCC_HSE_GET_PREDIV2() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2)
AnnaBridge	171:3a7713b1edbc	1774
AnnaBridge	171:3a7713b1edbc	1775	/**
AnnaBridge	171:3a7713b1edbc	1776	* @}
AnnaBridge	171:3a7713b1edbc	1777	*/
AnnaBridge	171:3a7713b1edbc	1778
AnnaBridge	171:3a7713b1edbc	1779	/** @addtogroup RCCEx_PLLI2S_Configuration
AnnaBridge	171:3a7713b1edbc	1780	* @{
AnnaBridge	171:3a7713b1edbc	1781	*/
AnnaBridge	171:3a7713b1edbc	1782
AnnaBridge	171:3a7713b1edbc	1783	/** @brief Macros to enable the main PLL2.
AnnaBridge	171:3a7713b1edbc	1784	* @note After enabling the main PLL2, the application software should wait on
AnnaBridge	171:3a7713b1edbc	1785	* PLL2RDY flag to be set indicating that PLL2 clock is stable and can
AnnaBridge	171:3a7713b1edbc	1786	* be used as system clock source.
AnnaBridge	171:3a7713b1edbc	1787	* @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes.
AnnaBridge	171:3a7713b1edbc	1788	*/
AnnaBridge	171:3a7713b1edbc	1789	#define __HAL_RCC_PLL2_ENABLE() ((__IO uint32_t ) RCC_CR_PLL2ON_BB = ENABLE)
AnnaBridge	171:3a7713b1edbc	1790
AnnaBridge	171:3a7713b1edbc	1791	/** @brief Macros to disable the main PLL2.
AnnaBridge	171:3a7713b1edbc	1792	* @note The main PLL2 can not be disabled if it is used indirectly as system clock source
AnnaBridge	171:3a7713b1edbc	1793	* @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes.
AnnaBridge	171:3a7713b1edbc	1794	*/
AnnaBridge	171:3a7713b1edbc	1795	#define __HAL_RCC_PLL2_DISABLE() ((__IO uint32_t ) RCC_CR_PLL2ON_BB = DISABLE)
AnnaBridge	171:3a7713b1edbc	1796
AnnaBridge	171:3a7713b1edbc	1797	/** @brief macros to configure the main PLL2 multiplication factor.
AnnaBridge	171:3a7713b1edbc	1798	* @note This function must be used only when the main PLL2 is disabled.
AnnaBridge	171:3a7713b1edbc	1799	*
AnnaBridge	171:3a7713b1edbc	1800	* @param __PLL2MUL__ specifies the multiplication factor for PLL2 VCO output clock
AnnaBridge	171:3a7713b1edbc	1801	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1802	* @arg @ref RCC_PLL2_MUL8 PLL2VCO = PLL2 clock entry x 8
AnnaBridge	171:3a7713b1edbc	1803	* @arg @ref RCC_PLL2_MUL9 PLL2VCO = PLL2 clock entry x 9
AnnaBridge	171:3a7713b1edbc	1804	* @arg @ref RCC_PLL2_MUL10 PLL2VCO = PLL2 clock entry x 10
AnnaBridge	171:3a7713b1edbc	1805	* @arg @ref RCC_PLL2_MUL11 PLL2VCO = PLL2 clock entry x 11
AnnaBridge	171:3a7713b1edbc	1806	* @arg @ref RCC_PLL2_MUL12 PLL2VCO = PLL2 clock entry x 12
AnnaBridge	171:3a7713b1edbc	1807	* @arg @ref RCC_PLL2_MUL13 PLL2VCO = PLL2 clock entry x 13
AnnaBridge	171:3a7713b1edbc	1808	* @arg @ref RCC_PLL2_MUL14 PLL2VCO = PLL2 clock entry x 14
AnnaBridge	171:3a7713b1edbc	1809	* @arg @ref RCC_PLL2_MUL16 PLL2VCO = PLL2 clock entry x 16
AnnaBridge	171:3a7713b1edbc	1810	* @arg @ref RCC_PLL2_MUL20 PLL2VCO = PLL2 clock entry x 20
AnnaBridge	171:3a7713b1edbc	1811	*
AnnaBridge	171:3a7713b1edbc	1812	*/
AnnaBridge	171:3a7713b1edbc	1813	#define __HAL_RCC_PLL2_CONFIG(__PLL2MUL__)\
AnnaBridge	171:3a7713b1edbc	1814	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL2MUL,(__PLL2MUL__))
AnnaBridge	171:3a7713b1edbc	1815
AnnaBridge	171:3a7713b1edbc	1816	/**
AnnaBridge	171:3a7713b1edbc	1817	* @}
AnnaBridge	171:3a7713b1edbc	1818	*/
AnnaBridge	171:3a7713b1edbc	1819
AnnaBridge	171:3a7713b1edbc	1820	/** @defgroup RCCEx_I2S_Configuration I2S Configuration
AnnaBridge	171:3a7713b1edbc	1821	* @brief Macros to configure clock source of I2S peripherals.
AnnaBridge	171:3a7713b1edbc	1822	* @{
AnnaBridge	171:3a7713b1edbc	1823	*/
AnnaBridge	171:3a7713b1edbc	1824
AnnaBridge	171:3a7713b1edbc	1825	/** @brief Macro to configure the I2S2 clock.
AnnaBridge	171:3a7713b1edbc	1826	* @param __I2S2CLKSOURCE__ specifies the I2S2 clock source.
AnnaBridge	171:3a7713b1edbc	1827	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1828	* @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
AnnaBridge	171:3a7713b1edbc	1829	* @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
AnnaBridge	171:3a7713b1edbc	1830	*/
AnnaBridge	171:3a7713b1edbc	1831	#define __HAL_RCC_I2S2_CONFIG(__I2S2CLKSOURCE__) \
AnnaBridge	171:3a7713b1edbc	1832	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S2SRC, (uint32_t)(__I2S2CLKSOURCE__))
AnnaBridge	171:3a7713b1edbc	1833
AnnaBridge	171:3a7713b1edbc	1834	/** @brief Macro to get the I2S2 clock (I2S2CLK).
AnnaBridge	171:3a7713b1edbc	1835	* @retval The clock source can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1836	* @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
AnnaBridge	171:3a7713b1edbc	1837	* @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
AnnaBridge	171:3a7713b1edbc	1838	*/
AnnaBridge	171:3a7713b1edbc	1839	#define __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S2SRC)))
AnnaBridge	171:3a7713b1edbc	1840
AnnaBridge	171:3a7713b1edbc	1841	/** @brief Macro to configure the I2S3 clock.
AnnaBridge	171:3a7713b1edbc	1842	* @param __I2S2CLKSOURCE__ specifies the I2S3 clock source.
AnnaBridge	171:3a7713b1edbc	1843	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1844	* @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
AnnaBridge	171:3a7713b1edbc	1845	* @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
AnnaBridge	171:3a7713b1edbc	1846	*/
AnnaBridge	171:3a7713b1edbc	1847	#define __HAL_RCC_I2S3_CONFIG(__I2S2CLKSOURCE__) \
AnnaBridge	171:3a7713b1edbc	1848	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S3SRC, (uint32_t)(__I2S2CLKSOURCE__))
AnnaBridge	171:3a7713b1edbc	1849
AnnaBridge	171:3a7713b1edbc	1850	/** @brief Macro to get the I2S3 clock (I2S3CLK).
AnnaBridge	171:3a7713b1edbc	1851	* @retval The clock source can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1852	* @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
AnnaBridge	171:3a7713b1edbc	1853	* @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
AnnaBridge	171:3a7713b1edbc	1854	*/
AnnaBridge	171:3a7713b1edbc	1855	#define __HAL_RCC_GET_I2S3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S3SRC)))
AnnaBridge	171:3a7713b1edbc	1856
AnnaBridge	171:3a7713b1edbc	1857	/**
AnnaBridge	171:3a7713b1edbc	1858	* @}
AnnaBridge	171:3a7713b1edbc	1859	*/
AnnaBridge	171:3a7713b1edbc	1860
AnnaBridge	171:3a7713b1edbc	1861	#endif /* STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	1862	/**
AnnaBridge	171:3a7713b1edbc	1863	* @}
AnnaBridge	171:3a7713b1edbc	1864	*/
AnnaBridge	171:3a7713b1edbc	1865
AnnaBridge	171:3a7713b1edbc	1866	/* Exported functions --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	1867	/** @addtogroup RCCEx_Exported_Functions
AnnaBridge	171:3a7713b1edbc	1868	* @{
AnnaBridge	171:3a7713b1edbc	1869	*/
AnnaBridge	171:3a7713b1edbc	1870
AnnaBridge	171:3a7713b1edbc	1871	/** @addtogroup RCCEx_Exported_Functions_Group1
AnnaBridge	171:3a7713b1edbc	1872	* @{
AnnaBridge	171:3a7713b1edbc	1873	*/
AnnaBridge	171:3a7713b1edbc	1874
AnnaBridge	171:3a7713b1edbc	1875	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
AnnaBridge	171:3a7713b1edbc	1876	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
AnnaBridge	171:3a7713b1edbc	1877	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
AnnaBridge	171:3a7713b1edbc	1878
AnnaBridge	171:3a7713b1edbc	1879	/**
AnnaBridge	171:3a7713b1edbc	1880	* @}
AnnaBridge	171:3a7713b1edbc	1881	*/
AnnaBridge	171:3a7713b1edbc	1882
AnnaBridge	171:3a7713b1edbc	1883	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
AnnaBridge	171:3a7713b1edbc	1884	/** @addtogroup RCCEx_Exported_Functions_Group2
AnnaBridge	171:3a7713b1edbc	1885	* @{
AnnaBridge	171:3a7713b1edbc	1886	*/
AnnaBridge	171:3a7713b1edbc	1887	HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit);
AnnaBridge	171:3a7713b1edbc	1888	HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void);
AnnaBridge	171:3a7713b1edbc	1889
AnnaBridge	171:3a7713b1edbc	1890	/**
AnnaBridge	171:3a7713b1edbc	1891	* @}
AnnaBridge	171:3a7713b1edbc	1892	*/
AnnaBridge	171:3a7713b1edbc	1893
AnnaBridge	171:3a7713b1edbc	1894	/** @addtogroup RCCEx_Exported_Functions_Group3
AnnaBridge	171:3a7713b1edbc	1895	* @{
AnnaBridge	171:3a7713b1edbc	1896	*/
AnnaBridge	171:3a7713b1edbc	1897	HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init);
AnnaBridge	171:3a7713b1edbc	1898	HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void);
AnnaBridge	171:3a7713b1edbc	1899
AnnaBridge	171:3a7713b1edbc	1900	/**
AnnaBridge	171:3a7713b1edbc	1901	* @}
AnnaBridge	171:3a7713b1edbc	1902	*/
AnnaBridge	171:3a7713b1edbc	1903	#endif /* STM32F105xC \|\| STM32F107xC */
AnnaBridge	171:3a7713b1edbc	1904
AnnaBridge	171:3a7713b1edbc	1905	/**
AnnaBridge	171:3a7713b1edbc	1906	* @}
AnnaBridge	171:3a7713b1edbc	1907	*/
AnnaBridge	171:3a7713b1edbc	1908
AnnaBridge	171:3a7713b1edbc	1909	/**
AnnaBridge	171:3a7713b1edbc	1910	* @}
AnnaBridge	171:3a7713b1edbc	1911	*/
AnnaBridge	171:3a7713b1edbc	1912
AnnaBridge	171:3a7713b1edbc	1913	/**
AnnaBridge	171:3a7713b1edbc	1914	* @}
AnnaBridge	171:3a7713b1edbc	1915	*/
AnnaBridge	171:3a7713b1edbc	1916
AnnaBridge	171:3a7713b1edbc	1917	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	1918	}
AnnaBridge	171:3a7713b1edbc	1919	#endif
AnnaBridge	171:3a7713b1edbc	1920
AnnaBridge	171:3a7713b1edbc	1921	#endif /* __STM32F1xx_HAL_RCC_EX_H */
AnnaBridge	171:3a7713b1edbc	1922
AnnaBridge	171:3a7713b1edbc	1923	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
AnnaBridge	171:3a7713b1edbc	1924