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TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_MICRO/stm32f1xx_hal_pwr.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /** |
| AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32f1xx_hal_pwr.h |
| AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
| AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of PWR HAL module. |
| AnnaBridge | 171:3a7713b1edbc | 6 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 7 | * @attention |
| AnnaBridge | 171:3a7713b1edbc | 8 | * |
| AnnaBridge | 171:3a7713b1edbc | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| AnnaBridge | 171:3a7713b1edbc | 10 | * |
| AnnaBridge | 171:3a7713b1edbc | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 171:3a7713b1edbc | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 171:3a7713b1edbc | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 171:3a7713b1edbc | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 171:3a7713b1edbc | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 171:3a7713b1edbc | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 171:3a7713b1edbc | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 171:3a7713b1edbc | 20 | * without specific prior written permission. |
| AnnaBridge | 171:3a7713b1edbc | 21 | * |
| AnnaBridge | 171:3a7713b1edbc | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 171:3a7713b1edbc | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 171:3a7713b1edbc | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 171:3a7713b1edbc | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 171:3a7713b1edbc | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 171:3a7713b1edbc | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 171:3a7713b1edbc | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 171:3a7713b1edbc | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 171:3a7713b1edbc | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 171:3a7713b1edbc | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 171:3a7713b1edbc | 32 | * |
| AnnaBridge | 171:3a7713b1edbc | 33 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 34 | */ |
| AnnaBridge | 171:3a7713b1edbc | 35 | |
| AnnaBridge | 171:3a7713b1edbc | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 37 | #ifndef __STM32F1xx_HAL_PWR_H |
| AnnaBridge | 171:3a7713b1edbc | 38 | #define __STM32F1xx_HAL_PWR_H |
| AnnaBridge | 171:3a7713b1edbc | 39 | |
| AnnaBridge | 171:3a7713b1edbc | 40 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 41 | extern "C" { |
| AnnaBridge | 171:3a7713b1edbc | 42 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 43 | |
| AnnaBridge | 171:3a7713b1edbc | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 45 | #include "stm32f1xx_hal_def.h" |
| AnnaBridge | 171:3a7713b1edbc | 46 | |
| AnnaBridge | 171:3a7713b1edbc | 47 | /** @addtogroup STM32F1xx_HAL_Driver |
| AnnaBridge | 171:3a7713b1edbc | 48 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 49 | */ |
| AnnaBridge | 171:3a7713b1edbc | 50 | |
| AnnaBridge | 171:3a7713b1edbc | 51 | /** @addtogroup PWR |
| AnnaBridge | 171:3a7713b1edbc | 52 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 53 | */ |
| AnnaBridge | 171:3a7713b1edbc | 54 | |
| AnnaBridge | 171:3a7713b1edbc | 55 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 56 | |
| AnnaBridge | 171:3a7713b1edbc | 57 | /** @defgroup PWR_Exported_Types PWR Exported Types |
| AnnaBridge | 171:3a7713b1edbc | 58 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 59 | */ |
| AnnaBridge | 171:3a7713b1edbc | 60 | |
| AnnaBridge | 171:3a7713b1edbc | 61 | /** |
| AnnaBridge | 171:3a7713b1edbc | 62 | * @brief PWR PVD configuration structure definition |
| AnnaBridge | 171:3a7713b1edbc | 63 | */ |
| AnnaBridge | 171:3a7713b1edbc | 64 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 65 | { |
| AnnaBridge | 171:3a7713b1edbc | 66 | uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. |
| AnnaBridge | 171:3a7713b1edbc | 67 | This parameter can be a value of @ref PWR_PVD_detection_level */ |
| AnnaBridge | 171:3a7713b1edbc | 68 | |
| AnnaBridge | 171:3a7713b1edbc | 69 | uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. |
| AnnaBridge | 171:3a7713b1edbc | 70 | This parameter can be a value of @ref PWR_PVD_Mode */ |
| AnnaBridge | 171:3a7713b1edbc | 71 | }PWR_PVDTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 72 | |
| AnnaBridge | 171:3a7713b1edbc | 73 | |
| AnnaBridge | 171:3a7713b1edbc | 74 | /** |
| AnnaBridge | 171:3a7713b1edbc | 75 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 76 | */ |
| AnnaBridge | 171:3a7713b1edbc | 77 | |
| AnnaBridge | 171:3a7713b1edbc | 78 | |
| AnnaBridge | 171:3a7713b1edbc | 79 | /* Internal constants --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 80 | |
| AnnaBridge | 171:3a7713b1edbc | 81 | /** @addtogroup PWR_Private_Constants |
| AnnaBridge | 171:3a7713b1edbc | 82 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 83 | */ |
| AnnaBridge | 171:3a7713b1edbc | 84 | |
| AnnaBridge | 171:3a7713b1edbc | 85 | #define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ |
| AnnaBridge | 171:3a7713b1edbc | 86 | |
| AnnaBridge | 171:3a7713b1edbc | 87 | /** |
| AnnaBridge | 171:3a7713b1edbc | 88 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 89 | */ |
| AnnaBridge | 171:3a7713b1edbc | 90 | |
| AnnaBridge | 171:3a7713b1edbc | 91 | |
| AnnaBridge | 171:3a7713b1edbc | 92 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 93 | |
| AnnaBridge | 171:3a7713b1edbc | 94 | /** @defgroup PWR_Exported_Constants PWR Exported Constants |
| AnnaBridge | 171:3a7713b1edbc | 95 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 96 | */ |
| AnnaBridge | 171:3a7713b1edbc | 97 | |
| AnnaBridge | 171:3a7713b1edbc | 98 | /** @defgroup PWR_PVD_detection_level PWR PVD detection level |
| AnnaBridge | 171:3a7713b1edbc | 99 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 100 | */ |
| AnnaBridge | 171:3a7713b1edbc | 101 | #define PWR_PVDLEVEL_0 PWR_CR_PLS_2V2 |
| AnnaBridge | 171:3a7713b1edbc | 102 | #define PWR_PVDLEVEL_1 PWR_CR_PLS_2V3 |
| AnnaBridge | 171:3a7713b1edbc | 103 | #define PWR_PVDLEVEL_2 PWR_CR_PLS_2V4 |
| AnnaBridge | 171:3a7713b1edbc | 104 | #define PWR_PVDLEVEL_3 PWR_CR_PLS_2V5 |
| AnnaBridge | 171:3a7713b1edbc | 105 | #define PWR_PVDLEVEL_4 PWR_CR_PLS_2V6 |
| AnnaBridge | 171:3a7713b1edbc | 106 | #define PWR_PVDLEVEL_5 PWR_CR_PLS_2V7 |
| AnnaBridge | 171:3a7713b1edbc | 107 | #define PWR_PVDLEVEL_6 PWR_CR_PLS_2V8 |
| AnnaBridge | 171:3a7713b1edbc | 108 | #define PWR_PVDLEVEL_7 PWR_CR_PLS_2V9 |
| AnnaBridge | 171:3a7713b1edbc | 109 | |
| AnnaBridge | 171:3a7713b1edbc | 110 | /** |
| AnnaBridge | 171:3a7713b1edbc | 111 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 112 | */ |
| AnnaBridge | 171:3a7713b1edbc | 113 | |
| AnnaBridge | 171:3a7713b1edbc | 114 | /** @defgroup PWR_PVD_Mode PWR PVD Mode |
| AnnaBridge | 171:3a7713b1edbc | 115 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 116 | */ |
| AnnaBridge | 171:3a7713b1edbc | 117 | #define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */ |
| AnnaBridge | 171:3a7713b1edbc | 118 | #define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */ |
| AnnaBridge | 171:3a7713b1edbc | 119 | #define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */ |
| AnnaBridge | 171:3a7713b1edbc | 120 | #define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ |
| AnnaBridge | 171:3a7713b1edbc | 121 | #define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */ |
| AnnaBridge | 171:3a7713b1edbc | 122 | #define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */ |
| AnnaBridge | 171:3a7713b1edbc | 123 | #define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */ |
| AnnaBridge | 171:3a7713b1edbc | 124 | |
| AnnaBridge | 171:3a7713b1edbc | 125 | /** |
| AnnaBridge | 171:3a7713b1edbc | 126 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 127 | */ |
| AnnaBridge | 171:3a7713b1edbc | 128 | |
| AnnaBridge | 171:3a7713b1edbc | 129 | |
| AnnaBridge | 171:3a7713b1edbc | 130 | /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins |
| AnnaBridge | 171:3a7713b1edbc | 131 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 132 | */ |
| AnnaBridge | 171:3a7713b1edbc | 133 | |
| AnnaBridge | 171:3a7713b1edbc | 134 | #define PWR_WAKEUP_PIN1 PWR_CSR_EWUP |
| AnnaBridge | 171:3a7713b1edbc | 135 | |
| AnnaBridge | 171:3a7713b1edbc | 136 | /** |
| AnnaBridge | 171:3a7713b1edbc | 137 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 138 | */ |
| AnnaBridge | 171:3a7713b1edbc | 139 | |
| AnnaBridge | 171:3a7713b1edbc | 140 | /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode |
| AnnaBridge | 171:3a7713b1edbc | 141 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 142 | */ |
| AnnaBridge | 171:3a7713b1edbc | 143 | #define PWR_MAINREGULATOR_ON 0x00000000U |
| AnnaBridge | 171:3a7713b1edbc | 144 | #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS |
| AnnaBridge | 171:3a7713b1edbc | 145 | |
| AnnaBridge | 171:3a7713b1edbc | 146 | /** |
| AnnaBridge | 171:3a7713b1edbc | 147 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 148 | */ |
| AnnaBridge | 171:3a7713b1edbc | 149 | |
| AnnaBridge | 171:3a7713b1edbc | 150 | /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry |
| AnnaBridge | 171:3a7713b1edbc | 151 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 152 | */ |
| AnnaBridge | 171:3a7713b1edbc | 153 | #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) |
| AnnaBridge | 171:3a7713b1edbc | 154 | #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) |
| AnnaBridge | 171:3a7713b1edbc | 155 | |
| AnnaBridge | 171:3a7713b1edbc | 156 | /** |
| AnnaBridge | 171:3a7713b1edbc | 157 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 158 | */ |
| AnnaBridge | 171:3a7713b1edbc | 159 | |
| AnnaBridge | 171:3a7713b1edbc | 160 | /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry |
| AnnaBridge | 171:3a7713b1edbc | 161 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 162 | */ |
| AnnaBridge | 171:3a7713b1edbc | 163 | #define PWR_STOPENTRY_WFI ((uint8_t)0x01) |
| AnnaBridge | 171:3a7713b1edbc | 164 | #define PWR_STOPENTRY_WFE ((uint8_t)0x02) |
| AnnaBridge | 171:3a7713b1edbc | 165 | |
| AnnaBridge | 171:3a7713b1edbc | 166 | /** |
| AnnaBridge | 171:3a7713b1edbc | 167 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 168 | */ |
| AnnaBridge | 171:3a7713b1edbc | 169 | |
| AnnaBridge | 171:3a7713b1edbc | 170 | /** @defgroup PWR_Flag PWR Flag |
| AnnaBridge | 171:3a7713b1edbc | 171 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 172 | */ |
| AnnaBridge | 171:3a7713b1edbc | 173 | #define PWR_FLAG_WU PWR_CSR_WUF |
| AnnaBridge | 171:3a7713b1edbc | 174 | #define PWR_FLAG_SB PWR_CSR_SBF |
| AnnaBridge | 171:3a7713b1edbc | 175 | #define PWR_FLAG_PVDO PWR_CSR_PVDO |
| AnnaBridge | 171:3a7713b1edbc | 176 | |
| AnnaBridge | 171:3a7713b1edbc | 177 | |
| AnnaBridge | 171:3a7713b1edbc | 178 | /** |
| AnnaBridge | 171:3a7713b1edbc | 179 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 180 | */ |
| AnnaBridge | 171:3a7713b1edbc | 181 | |
| AnnaBridge | 171:3a7713b1edbc | 182 | /** |
| AnnaBridge | 171:3a7713b1edbc | 183 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 184 | */ |
| AnnaBridge | 171:3a7713b1edbc | 185 | |
| AnnaBridge | 171:3a7713b1edbc | 186 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 187 | /** @defgroup PWR_Exported_Macros PWR Exported Macros |
| AnnaBridge | 171:3a7713b1edbc | 188 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 189 | */ |
| AnnaBridge | 171:3a7713b1edbc | 190 | |
| AnnaBridge | 171:3a7713b1edbc | 191 | /** @brief Check PWR flag is set or not. |
| AnnaBridge | 171:3a7713b1edbc | 192 | * @param __FLAG__: specifies the flag to check. |
| AnnaBridge | 171:3a7713b1edbc | 193 | * This parameter can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 194 | * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event |
| AnnaBridge | 171:3a7713b1edbc | 195 | * was received from the WKUP pin or from the RTC alarm |
| AnnaBridge | 171:3a7713b1edbc | 196 | * An additional wakeup event is detected if the WKUP pin is enabled |
| AnnaBridge | 171:3a7713b1edbc | 197 | * (by setting the EWUP bit) when the WKUP pin level is already high. |
| AnnaBridge | 171:3a7713b1edbc | 198 | * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was |
| AnnaBridge | 171:3a7713b1edbc | 199 | * resumed from StandBy mode. |
| AnnaBridge | 171:3a7713b1edbc | 200 | * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled |
| AnnaBridge | 171:3a7713b1edbc | 201 | * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode |
| AnnaBridge | 171:3a7713b1edbc | 202 | * For this reason, this bit is equal to 0 after Standby or reset |
| AnnaBridge | 171:3a7713b1edbc | 203 | * until the PVDE bit is set. |
| AnnaBridge | 171:3a7713b1edbc | 204 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| AnnaBridge | 171:3a7713b1edbc | 205 | */ |
| AnnaBridge | 171:3a7713b1edbc | 206 | #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) |
| AnnaBridge | 171:3a7713b1edbc | 207 | |
| AnnaBridge | 171:3a7713b1edbc | 208 | /** @brief Clear the PWR's pending flags. |
| AnnaBridge | 171:3a7713b1edbc | 209 | * @param __FLAG__: specifies the flag to clear. |
| AnnaBridge | 171:3a7713b1edbc | 210 | * This parameter can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 211 | * @arg PWR_FLAG_WU: Wake Up flag |
| AnnaBridge | 171:3a7713b1edbc | 212 | * @arg PWR_FLAG_SB: StandBy flag |
| AnnaBridge | 171:3a7713b1edbc | 213 | */ |
| AnnaBridge | 171:3a7713b1edbc | 214 | #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2)) |
| AnnaBridge | 171:3a7713b1edbc | 215 | |
| AnnaBridge | 171:3a7713b1edbc | 216 | /** |
| AnnaBridge | 171:3a7713b1edbc | 217 | * @brief Enable interrupt on PVD Exti Line 16. |
| AnnaBridge | 171:3a7713b1edbc | 218 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 219 | */ |
| AnnaBridge | 171:3a7713b1edbc | 220 | #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 171:3a7713b1edbc | 221 | |
| AnnaBridge | 171:3a7713b1edbc | 222 | /** |
| AnnaBridge | 171:3a7713b1edbc | 223 | * @brief Disable interrupt on PVD Exti Line 16. |
| AnnaBridge | 171:3a7713b1edbc | 224 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 225 | */ |
| AnnaBridge | 171:3a7713b1edbc | 226 | #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 171:3a7713b1edbc | 227 | |
| AnnaBridge | 171:3a7713b1edbc | 228 | /** |
| AnnaBridge | 171:3a7713b1edbc | 229 | * @brief Enable event on PVD Exti Line 16. |
| AnnaBridge | 171:3a7713b1edbc | 230 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 231 | */ |
| AnnaBridge | 171:3a7713b1edbc | 232 | #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 171:3a7713b1edbc | 233 | |
| AnnaBridge | 171:3a7713b1edbc | 234 | /** |
| AnnaBridge | 171:3a7713b1edbc | 235 | * @brief Disable event on PVD Exti Line 16. |
| AnnaBridge | 171:3a7713b1edbc | 236 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 237 | */ |
| AnnaBridge | 171:3a7713b1edbc | 238 | #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 171:3a7713b1edbc | 239 | |
| AnnaBridge | 171:3a7713b1edbc | 240 | |
| AnnaBridge | 171:3a7713b1edbc | 241 | /** |
| AnnaBridge | 171:3a7713b1edbc | 242 | * @brief PVD EXTI line configuration: set falling edge trigger. |
| AnnaBridge | 171:3a7713b1edbc | 243 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 244 | */ |
| AnnaBridge | 171:3a7713b1edbc | 245 | #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 171:3a7713b1edbc | 246 | |
| AnnaBridge | 171:3a7713b1edbc | 247 | |
| AnnaBridge | 171:3a7713b1edbc | 248 | /** |
| AnnaBridge | 171:3a7713b1edbc | 249 | * @brief Disable the PVD Extended Interrupt Falling Trigger. |
| AnnaBridge | 171:3a7713b1edbc | 250 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 251 | */ |
| AnnaBridge | 171:3a7713b1edbc | 252 | #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 171:3a7713b1edbc | 253 | |
| AnnaBridge | 171:3a7713b1edbc | 254 | |
| AnnaBridge | 171:3a7713b1edbc | 255 | /** |
| AnnaBridge | 171:3a7713b1edbc | 256 | * @brief PVD EXTI line configuration: set rising edge trigger. |
| AnnaBridge | 171:3a7713b1edbc | 257 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 258 | */ |
| AnnaBridge | 171:3a7713b1edbc | 259 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 171:3a7713b1edbc | 260 | |
| AnnaBridge | 171:3a7713b1edbc | 261 | /** |
| AnnaBridge | 171:3a7713b1edbc | 262 | * @brief Disable the PVD Extended Interrupt Rising Trigger. |
| AnnaBridge | 171:3a7713b1edbc | 263 | * This parameter can be: |
| AnnaBridge | 171:3a7713b1edbc | 264 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 265 | */ |
| AnnaBridge | 171:3a7713b1edbc | 266 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 171:3a7713b1edbc | 267 | |
| AnnaBridge | 171:3a7713b1edbc | 268 | /** |
| AnnaBridge | 171:3a7713b1edbc | 269 | * @brief PVD EXTI line configuration: set rising & falling edge trigger. |
| AnnaBridge | 171:3a7713b1edbc | 270 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 271 | */ |
| AnnaBridge | 171:3a7713b1edbc | 272 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); |
| AnnaBridge | 171:3a7713b1edbc | 273 | |
| AnnaBridge | 171:3a7713b1edbc | 274 | /** |
| AnnaBridge | 171:3a7713b1edbc | 275 | * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. |
| AnnaBridge | 171:3a7713b1edbc | 276 | * This parameter can be: |
| AnnaBridge | 171:3a7713b1edbc | 277 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 278 | */ |
| AnnaBridge | 171:3a7713b1edbc | 279 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); |
| AnnaBridge | 171:3a7713b1edbc | 280 | |
| AnnaBridge | 171:3a7713b1edbc | 281 | |
| AnnaBridge | 171:3a7713b1edbc | 282 | |
| AnnaBridge | 171:3a7713b1edbc | 283 | /** |
| AnnaBridge | 171:3a7713b1edbc | 284 | * @brief Check whether the specified PVD EXTI interrupt flag is set or not. |
| AnnaBridge | 171:3a7713b1edbc | 285 | * @retval EXTI PVD Line Status. |
| AnnaBridge | 171:3a7713b1edbc | 286 | */ |
| AnnaBridge | 171:3a7713b1edbc | 287 | #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) |
| AnnaBridge | 171:3a7713b1edbc | 288 | |
| AnnaBridge | 171:3a7713b1edbc | 289 | /** |
| AnnaBridge | 171:3a7713b1edbc | 290 | * @brief Clear the PVD EXTI flag. |
| AnnaBridge | 171:3a7713b1edbc | 291 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 292 | */ |
| AnnaBridge | 171:3a7713b1edbc | 293 | #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) |
| AnnaBridge | 171:3a7713b1edbc | 294 | |
| AnnaBridge | 171:3a7713b1edbc | 295 | /** |
| AnnaBridge | 171:3a7713b1edbc | 296 | * @brief Generate a Software interrupt on selected EXTI line. |
| AnnaBridge | 171:3a7713b1edbc | 297 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 298 | */ |
| AnnaBridge | 171:3a7713b1edbc | 299 | #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 171:3a7713b1edbc | 300 | /** |
| AnnaBridge | 171:3a7713b1edbc | 301 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 302 | */ |
| AnnaBridge | 171:3a7713b1edbc | 303 | |
| AnnaBridge | 171:3a7713b1edbc | 304 | /* Private macro -------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 305 | /** @defgroup PWR_Private_Macros PWR Private Macros |
| AnnaBridge | 171:3a7713b1edbc | 306 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 307 | */ |
| AnnaBridge | 171:3a7713b1edbc | 308 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ |
| AnnaBridge | 171:3a7713b1edbc | 309 | ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ |
| AnnaBridge | 171:3a7713b1edbc | 310 | ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ |
| AnnaBridge | 171:3a7713b1edbc | 311 | ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) |
| AnnaBridge | 171:3a7713b1edbc | 312 | |
| AnnaBridge | 171:3a7713b1edbc | 313 | |
| AnnaBridge | 171:3a7713b1edbc | 314 | #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ |
| AnnaBridge | 171:3a7713b1edbc | 315 | ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ |
| AnnaBridge | 171:3a7713b1edbc | 316 | ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ |
| AnnaBridge | 171:3a7713b1edbc | 317 | ((MODE) == PWR_PVD_MODE_NORMAL)) |
| AnnaBridge | 171:3a7713b1edbc | 318 | |
| AnnaBridge | 171:3a7713b1edbc | 319 | #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1)) |
| AnnaBridge | 171:3a7713b1edbc | 320 | |
| AnnaBridge | 171:3a7713b1edbc | 321 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ |
| AnnaBridge | 171:3a7713b1edbc | 322 | ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) |
| AnnaBridge | 171:3a7713b1edbc | 323 | |
| AnnaBridge | 171:3a7713b1edbc | 324 | #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) |
| AnnaBridge | 171:3a7713b1edbc | 325 | |
| AnnaBridge | 171:3a7713b1edbc | 326 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) |
| AnnaBridge | 171:3a7713b1edbc | 327 | |
| AnnaBridge | 171:3a7713b1edbc | 328 | /** |
| AnnaBridge | 171:3a7713b1edbc | 329 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 330 | */ |
| AnnaBridge | 171:3a7713b1edbc | 331 | |
| AnnaBridge | 171:3a7713b1edbc | 332 | |
| AnnaBridge | 171:3a7713b1edbc | 333 | |
| AnnaBridge | 171:3a7713b1edbc | 334 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 335 | |
| AnnaBridge | 171:3a7713b1edbc | 336 | /** @addtogroup PWR_Exported_Functions PWR Exported Functions |
| AnnaBridge | 171:3a7713b1edbc | 337 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 338 | */ |
| AnnaBridge | 171:3a7713b1edbc | 339 | |
| AnnaBridge | 171:3a7713b1edbc | 340 | /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions |
| AnnaBridge | 171:3a7713b1edbc | 341 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 342 | */ |
| AnnaBridge | 171:3a7713b1edbc | 343 | |
| AnnaBridge | 171:3a7713b1edbc | 344 | /* Initialization and de-initialization functions *******************************/ |
| AnnaBridge | 171:3a7713b1edbc | 345 | void HAL_PWR_DeInit(void); |
| AnnaBridge | 171:3a7713b1edbc | 346 | void HAL_PWR_EnableBkUpAccess(void); |
| AnnaBridge | 171:3a7713b1edbc | 347 | void HAL_PWR_DisableBkUpAccess(void); |
| AnnaBridge | 171:3a7713b1edbc | 348 | |
| AnnaBridge | 171:3a7713b1edbc | 349 | /** |
| AnnaBridge | 171:3a7713b1edbc | 350 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 351 | */ |
| AnnaBridge | 171:3a7713b1edbc | 352 | |
| AnnaBridge | 171:3a7713b1edbc | 353 | /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions |
| AnnaBridge | 171:3a7713b1edbc | 354 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 355 | */ |
| AnnaBridge | 171:3a7713b1edbc | 356 | |
| AnnaBridge | 171:3a7713b1edbc | 357 | /* Peripheral Control functions ************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 358 | void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); |
| AnnaBridge | 171:3a7713b1edbc | 359 | /* #define HAL_PWR_ConfigPVD 12*/ |
| AnnaBridge | 171:3a7713b1edbc | 360 | void HAL_PWR_EnablePVD(void); |
| AnnaBridge | 171:3a7713b1edbc | 361 | void HAL_PWR_DisablePVD(void); |
| AnnaBridge | 171:3a7713b1edbc | 362 | |
| AnnaBridge | 171:3a7713b1edbc | 363 | /* WakeUp pins configuration functions ****************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 364 | void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); |
| AnnaBridge | 171:3a7713b1edbc | 365 | void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); |
| AnnaBridge | 171:3a7713b1edbc | 366 | |
| AnnaBridge | 171:3a7713b1edbc | 367 | /* Low Power modes configuration functions ************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 368 | void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); |
| AnnaBridge | 171:3a7713b1edbc | 369 | void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); |
| AnnaBridge | 171:3a7713b1edbc | 370 | void HAL_PWR_EnterSTANDBYMode(void); |
| AnnaBridge | 171:3a7713b1edbc | 371 | |
| AnnaBridge | 171:3a7713b1edbc | 372 | void HAL_PWR_EnableSleepOnExit(void); |
| AnnaBridge | 171:3a7713b1edbc | 373 | void HAL_PWR_DisableSleepOnExit(void); |
| AnnaBridge | 171:3a7713b1edbc | 374 | void HAL_PWR_EnableSEVOnPend(void); |
| AnnaBridge | 171:3a7713b1edbc | 375 | void HAL_PWR_DisableSEVOnPend(void); |
| AnnaBridge | 171:3a7713b1edbc | 376 | |
| AnnaBridge | 171:3a7713b1edbc | 377 | |
| AnnaBridge | 171:3a7713b1edbc | 378 | |
| AnnaBridge | 171:3a7713b1edbc | 379 | void HAL_PWR_PVD_IRQHandler(void); |
| AnnaBridge | 171:3a7713b1edbc | 380 | void HAL_PWR_PVDCallback(void); |
| AnnaBridge | 171:3a7713b1edbc | 381 | /** |
| AnnaBridge | 171:3a7713b1edbc | 382 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 383 | */ |
| AnnaBridge | 171:3a7713b1edbc | 384 | |
| AnnaBridge | 171:3a7713b1edbc | 385 | /** |
| AnnaBridge | 171:3a7713b1edbc | 386 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 387 | */ |
| AnnaBridge | 171:3a7713b1edbc | 388 | |
| AnnaBridge | 171:3a7713b1edbc | 389 | /** |
| AnnaBridge | 171:3a7713b1edbc | 390 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 391 | */ |
| AnnaBridge | 171:3a7713b1edbc | 392 | |
| AnnaBridge | 171:3a7713b1edbc | 393 | /** |
| AnnaBridge | 171:3a7713b1edbc | 394 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 395 | */ |
| AnnaBridge | 171:3a7713b1edbc | 396 | |
| AnnaBridge | 171:3a7713b1edbc | 397 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 398 | } |
| AnnaBridge | 171:3a7713b1edbc | 399 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 400 | |
| AnnaBridge | 171:3a7713b1edbc | 401 | |
| AnnaBridge | 171:3a7713b1edbc | 402 | #endif /* __STM32F1xx_HAL_PWR_H */ |
| AnnaBridge | 171:3a7713b1edbc | 403 | |
| AnnaBridge | 171:3a7713b1edbc | 404 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
