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TARGET_NUCLEO_F030R8/TOOLCHAIN_IAR/stm32f0xx_ll_tim.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	171:3a7713b1edbc	1	/**
AnnaBridge	171:3a7713b1edbc	2	******************************************************************************
AnnaBridge	171:3a7713b1edbc	3	* @file stm32f0xx_ll_tim.h
AnnaBridge	171:3a7713b1edbc	4	* @author MCD Application Team
AnnaBridge	171:3a7713b1edbc	5	* @brief Header file of TIM LL module.
AnnaBridge	171:3a7713b1edbc	6	******************************************************************************
AnnaBridge	171:3a7713b1edbc	7	* @attention
AnnaBridge	171:3a7713b1edbc	8	*
AnnaBridge	171:3a7713b1edbc	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	171:3a7713b1edbc	10	*
AnnaBridge	171:3a7713b1edbc	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	171:3a7713b1edbc	12	* are permitted provided that the following conditions are met:
AnnaBridge	171:3a7713b1edbc	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	171:3a7713b1edbc	14	* this list of conditions and the following disclaimer.
AnnaBridge	171:3a7713b1edbc	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	171:3a7713b1edbc	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	171:3a7713b1edbc	17	* and/or other materials provided with the distribution.
AnnaBridge	171:3a7713b1edbc	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	171:3a7713b1edbc	19	* may be used to endorse or promote products derived from this software
AnnaBridge	171:3a7713b1edbc	20	* without specific prior written permission.
AnnaBridge	171:3a7713b1edbc	21	*
AnnaBridge	171:3a7713b1edbc	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	171:3a7713b1edbc	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	171:3a7713b1edbc	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	171:3a7713b1edbc	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	171:3a7713b1edbc	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	171:3a7713b1edbc	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	171:3a7713b1edbc	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	171:3a7713b1edbc	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	171:3a7713b1edbc	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	171:3a7713b1edbc	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	171:3a7713b1edbc	32	*
AnnaBridge	171:3a7713b1edbc	33	******************************************************************************
AnnaBridge	171:3a7713b1edbc	34	*/
AnnaBridge	171:3a7713b1edbc	35
AnnaBridge	171:3a7713b1edbc	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	171:3a7713b1edbc	37	#ifndef __STM32F0xx_LL_TIM_H
AnnaBridge	171:3a7713b1edbc	38	#define __STM32F0xx_LL_TIM_H
AnnaBridge	171:3a7713b1edbc	39
AnnaBridge	171:3a7713b1edbc	40	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	41	extern "C" {
AnnaBridge	171:3a7713b1edbc	42	#endif
AnnaBridge	171:3a7713b1edbc	43
AnnaBridge	171:3a7713b1edbc	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	45	#include "stm32f0xx.h"
AnnaBridge	171:3a7713b1edbc	46
AnnaBridge	171:3a7713b1edbc	47	/** @addtogroup STM32F0xx_LL_Driver
AnnaBridge	171:3a7713b1edbc	48	* @{
AnnaBridge	171:3a7713b1edbc	49	*/
AnnaBridge	171:3a7713b1edbc	50
AnnaBridge	171:3a7713b1edbc	51	#if defined (TIM1) \|\| defined (TIM2) \|\| defined (TIM3) \|\| defined (TIM14) \|\| defined (TIM15) \|\| defined (TIM16) \|\| defined (TIM17) \|\| defined (TIM6) \|\| defined (TIM7)
AnnaBridge	171:3a7713b1edbc	52
AnnaBridge	171:3a7713b1edbc	53	/** @defgroup TIM_LL TIM
AnnaBridge	171:3a7713b1edbc	54	* @{
AnnaBridge	171:3a7713b1edbc	55	*/
AnnaBridge	171:3a7713b1edbc	56
AnnaBridge	171:3a7713b1edbc	57	/* Private types -------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	58	/* Private variables ---------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	59	/** @defgroup TIM_LL_Private_Variables TIM Private Variables
AnnaBridge	171:3a7713b1edbc	60	* @{
AnnaBridge	171:3a7713b1edbc	61	*/
AnnaBridge	171:3a7713b1edbc	62	static const uint8_t OFFSET_TAB_CCMRx[] =
AnnaBridge	171:3a7713b1edbc	63	{
AnnaBridge	171:3a7713b1edbc	64	0x00U, /* 0: TIMx_CH1 */
AnnaBridge	171:3a7713b1edbc	65	0x00U, /* 1: TIMx_CH1N */
AnnaBridge	171:3a7713b1edbc	66	0x00U, /* 2: TIMx_CH2 */
AnnaBridge	171:3a7713b1edbc	67	0x00U, /* 3: TIMx_CH2N */
AnnaBridge	171:3a7713b1edbc	68	0x04U, /* 4: TIMx_CH3 */
AnnaBridge	171:3a7713b1edbc	69	0x04U, /* 5: TIMx_CH3N */
AnnaBridge	171:3a7713b1edbc	70	0x04U /* 6: TIMx_CH4 */
AnnaBridge	171:3a7713b1edbc	71	};
AnnaBridge	171:3a7713b1edbc	72
AnnaBridge	171:3a7713b1edbc	73	static const uint8_t SHIFT_TAB_OCxx[] =
AnnaBridge	171:3a7713b1edbc	74	{
AnnaBridge	171:3a7713b1edbc	75	0U, /* 0: OC1M, OC1FE, OC1PE */
AnnaBridge	171:3a7713b1edbc	76	0U, /* 1: - NA */
AnnaBridge	171:3a7713b1edbc	77	8U, /* 2: OC2M, OC2FE, OC2PE */
AnnaBridge	171:3a7713b1edbc	78	0U, /* 3: - NA */
AnnaBridge	171:3a7713b1edbc	79	0U, /* 4: OC3M, OC3FE, OC3PE */
AnnaBridge	171:3a7713b1edbc	80	0U, /* 5: - NA */
AnnaBridge	171:3a7713b1edbc	81	8U /* 6: OC4M, OC4FE, OC4PE */
AnnaBridge	171:3a7713b1edbc	82	};
AnnaBridge	171:3a7713b1edbc	83
AnnaBridge	171:3a7713b1edbc	84	static const uint8_t SHIFT_TAB_ICxx[] =
AnnaBridge	171:3a7713b1edbc	85	{
AnnaBridge	171:3a7713b1edbc	86	0U, /* 0: CC1S, IC1PSC, IC1F */
AnnaBridge	171:3a7713b1edbc	87	0U, /* 1: - NA */
AnnaBridge	171:3a7713b1edbc	88	8U, /* 2: CC2S, IC2PSC, IC2F */
AnnaBridge	171:3a7713b1edbc	89	0U, /* 3: - NA */
AnnaBridge	171:3a7713b1edbc	90	0U, /* 4: CC3S, IC3PSC, IC3F */
AnnaBridge	171:3a7713b1edbc	91	0U, /* 5: - NA */
AnnaBridge	171:3a7713b1edbc	92	8U /* 6: CC4S, IC4PSC, IC4F */
AnnaBridge	171:3a7713b1edbc	93	};
AnnaBridge	171:3a7713b1edbc	94
AnnaBridge	171:3a7713b1edbc	95	static const uint8_t SHIFT_TAB_CCxP[] =
AnnaBridge	171:3a7713b1edbc	96	{
AnnaBridge	171:3a7713b1edbc	97	0U, /* 0: CC1P */
AnnaBridge	171:3a7713b1edbc	98	2U, /* 1: CC1NP */
AnnaBridge	171:3a7713b1edbc	99	4U, /* 2: CC2P */
AnnaBridge	171:3a7713b1edbc	100	6U, /* 3: CC2NP */
AnnaBridge	171:3a7713b1edbc	101	8U, /* 4: CC3P */
AnnaBridge	171:3a7713b1edbc	102	10U, /* 5: CC3NP */
AnnaBridge	171:3a7713b1edbc	103	12U /* 6: CC4P */
AnnaBridge	171:3a7713b1edbc	104	};
AnnaBridge	171:3a7713b1edbc	105
AnnaBridge	171:3a7713b1edbc	106	static const uint8_t SHIFT_TAB_OISx[] =
AnnaBridge	171:3a7713b1edbc	107	{
AnnaBridge	171:3a7713b1edbc	108	0U, /* 0: OIS1 */
AnnaBridge	171:3a7713b1edbc	109	1U, /* 1: OIS1N */
AnnaBridge	171:3a7713b1edbc	110	2U, /* 2: OIS2 */
AnnaBridge	171:3a7713b1edbc	111	3U, /* 3: OIS2N */
AnnaBridge	171:3a7713b1edbc	112	4U, /* 4: OIS3 */
AnnaBridge	171:3a7713b1edbc	113	5U, /* 5: OIS3N */
AnnaBridge	171:3a7713b1edbc	114	6U /* 6: OIS4 */
AnnaBridge	171:3a7713b1edbc	115	};
AnnaBridge	171:3a7713b1edbc	116	/**
AnnaBridge	171:3a7713b1edbc	117	* @}
AnnaBridge	171:3a7713b1edbc	118	*/
AnnaBridge	171:3a7713b1edbc	119
AnnaBridge	171:3a7713b1edbc	120
AnnaBridge	171:3a7713b1edbc	121	/* Private constants ---------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	122	/** @defgroup TIM_LL_Private_Constants TIM Private Constants
AnnaBridge	171:3a7713b1edbc	123	* @{
AnnaBridge	171:3a7713b1edbc	124	*/
AnnaBridge	171:3a7713b1edbc	125
AnnaBridge	171:3a7713b1edbc	126
AnnaBridge	171:3a7713b1edbc	127	#define TIMx_OR_RMP_SHIFT 16U
AnnaBridge	171:3a7713b1edbc	128	#define TIMx_OR_RMP_MASK 0x0000FFFFU
AnnaBridge	171:3a7713b1edbc	129	#define TIM14_OR_RMP_MASK (TIM14_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
AnnaBridge	171:3a7713b1edbc	130
AnnaBridge	171:3a7713b1edbc	131	/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
AnnaBridge	171:3a7713b1edbc	132	#define DT_DELAY_1 ((uint8_t)0x7FU)
AnnaBridge	171:3a7713b1edbc	133	#define DT_DELAY_2 ((uint8_t)0x3FU)
AnnaBridge	171:3a7713b1edbc	134	#define DT_DELAY_3 ((uint8_t)0x1FU)
AnnaBridge	171:3a7713b1edbc	135	#define DT_DELAY_4 ((uint8_t)0x1FU)
AnnaBridge	171:3a7713b1edbc	136
AnnaBridge	171:3a7713b1edbc	137	/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
AnnaBridge	171:3a7713b1edbc	138	#define DT_RANGE_1 ((uint8_t)0x00U)
AnnaBridge	171:3a7713b1edbc	139	#define DT_RANGE_2 ((uint8_t)0x80U)
AnnaBridge	171:3a7713b1edbc	140	#define DT_RANGE_3 ((uint8_t)0xC0U)
AnnaBridge	171:3a7713b1edbc	141	#define DT_RANGE_4 ((uint8_t)0xE0U)
AnnaBridge	171:3a7713b1edbc	142
AnnaBridge	171:3a7713b1edbc	143
AnnaBridge	171:3a7713b1edbc	144	/**
AnnaBridge	171:3a7713b1edbc	145	* @}
AnnaBridge	171:3a7713b1edbc	146	*/
AnnaBridge	171:3a7713b1edbc	147
AnnaBridge	171:3a7713b1edbc	148	/* Private macros ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	149	/** @defgroup TIM_LL_Private_Macros TIM Private Macros
AnnaBridge	171:3a7713b1edbc	150	* @{
AnnaBridge	171:3a7713b1edbc	151	*/
AnnaBridge	171:3a7713b1edbc	152	/** @brief Convert channel id into channel index.
AnnaBridge	171:3a7713b1edbc	153	* @param __CHANNEL__ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	154	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	155	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	171:3a7713b1edbc	156	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	157	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	171:3a7713b1edbc	158	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	159	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	171:3a7713b1edbc	160	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	161	* @retval none
AnnaBridge	171:3a7713b1edbc	162	*/
AnnaBridge	171:3a7713b1edbc	163	#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
AnnaBridge	171:3a7713b1edbc	164	(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
AnnaBridge	171:3a7713b1edbc	165	((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
AnnaBridge	171:3a7713b1edbc	166	((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
AnnaBridge	171:3a7713b1edbc	167	((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
AnnaBridge	171:3a7713b1edbc	168	((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
AnnaBridge	171:3a7713b1edbc	169	((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
AnnaBridge	171:3a7713b1edbc	170
AnnaBridge	171:3a7713b1edbc	171	/** @brief Calculate the deadtime sampling period(in ps).
AnnaBridge	171:3a7713b1edbc	172	* @param __TIMCLK__ timer input clock frequency (in Hz).
AnnaBridge	171:3a7713b1edbc	173	* @param __CKD__ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	174	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
AnnaBridge	171:3a7713b1edbc	175	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
AnnaBridge	171:3a7713b1edbc	176	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
AnnaBridge	171:3a7713b1edbc	177	* @retval none
AnnaBridge	171:3a7713b1edbc	178	*/
AnnaBridge	171:3a7713b1edbc	179	#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
AnnaBridge	171:3a7713b1edbc	180	(((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
AnnaBridge	171:3a7713b1edbc	181	((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
AnnaBridge	171:3a7713b1edbc	182	((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
AnnaBridge	171:3a7713b1edbc	183	/**
AnnaBridge	171:3a7713b1edbc	184	* @}
AnnaBridge	171:3a7713b1edbc	185	*/
AnnaBridge	171:3a7713b1edbc	186
AnnaBridge	171:3a7713b1edbc	187
AnnaBridge	171:3a7713b1edbc	188	/* Exported types ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	189	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	171:3a7713b1edbc	190	/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
AnnaBridge	171:3a7713b1edbc	191	* @{
AnnaBridge	171:3a7713b1edbc	192	*/
AnnaBridge	171:3a7713b1edbc	193
AnnaBridge	171:3a7713b1edbc	194	/**
AnnaBridge	171:3a7713b1edbc	195	* @brief TIM Time Base configuration structure definition.
AnnaBridge	171:3a7713b1edbc	196	*/
AnnaBridge	171:3a7713b1edbc	197	typedef struct
AnnaBridge	171:3a7713b1edbc	198	{
AnnaBridge	171:3a7713b1edbc	199	uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
AnnaBridge	171:3a7713b1edbc	200	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
AnnaBridge	171:3a7713b1edbc	201
AnnaBridge	171:3a7713b1edbc	202	This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
AnnaBridge	171:3a7713b1edbc	203
AnnaBridge	171:3a7713b1edbc	204	uint32_t CounterMode; /*!< Specifies the counter mode.
AnnaBridge	171:3a7713b1edbc	205	This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
AnnaBridge	171:3a7713b1edbc	206
AnnaBridge	171:3a7713b1edbc	207	This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
AnnaBridge	171:3a7713b1edbc	208
AnnaBridge	171:3a7713b1edbc	209	uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
AnnaBridge	171:3a7713b1edbc	210	Auto-Reload Register at the next update event.
AnnaBridge	171:3a7713b1edbc	211	This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
AnnaBridge	171:3a7713b1edbc	212	Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
AnnaBridge	171:3a7713b1edbc	213
AnnaBridge	171:3a7713b1edbc	214	This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
AnnaBridge	171:3a7713b1edbc	215
AnnaBridge	171:3a7713b1edbc	216	uint32_t ClockDivision; /*!< Specifies the clock division.
AnnaBridge	171:3a7713b1edbc	217	This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
AnnaBridge	171:3a7713b1edbc	218
AnnaBridge	171:3a7713b1edbc	219	This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
AnnaBridge	171:3a7713b1edbc	220
AnnaBridge	171:3a7713b1edbc	221	uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
AnnaBridge	171:3a7713b1edbc	222	reaches zero, an update event is generated and counting restarts
AnnaBridge	171:3a7713b1edbc	223	from the RCR value (N).
AnnaBridge	171:3a7713b1edbc	224	This means in PWM mode that (N+1) corresponds to:
AnnaBridge	171:3a7713b1edbc	225	- the number of PWM periods in edge-aligned mode
AnnaBridge	171:3a7713b1edbc	226	- the number of half PWM period in center-aligned mode
AnnaBridge	171:3a7713b1edbc	227	This parameter must be a number between 0x00 and 0xFF.
AnnaBridge	171:3a7713b1edbc	228
AnnaBridge	171:3a7713b1edbc	229	This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
AnnaBridge	171:3a7713b1edbc	230	} LL_TIM_InitTypeDef;
AnnaBridge	171:3a7713b1edbc	231
AnnaBridge	171:3a7713b1edbc	232	/**
AnnaBridge	171:3a7713b1edbc	233	* @brief TIM Output Compare configuration structure definition.
AnnaBridge	171:3a7713b1edbc	234	*/
AnnaBridge	171:3a7713b1edbc	235	typedef struct
AnnaBridge	171:3a7713b1edbc	236	{
AnnaBridge	171:3a7713b1edbc	237	uint32_t OCMode; /*!< Specifies the output mode.
AnnaBridge	171:3a7713b1edbc	238	This parameter can be a value of @ref TIM_LL_EC_OCMODE.
AnnaBridge	171:3a7713b1edbc	239
AnnaBridge	171:3a7713b1edbc	240	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
AnnaBridge	171:3a7713b1edbc	241
AnnaBridge	171:3a7713b1edbc	242	uint32_t OCState; /*!< Specifies the TIM Output Compare state.
AnnaBridge	171:3a7713b1edbc	243	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
AnnaBridge	171:3a7713b1edbc	244
AnnaBridge	171:3a7713b1edbc	245	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
AnnaBridge	171:3a7713b1edbc	246
AnnaBridge	171:3a7713b1edbc	247	uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
AnnaBridge	171:3a7713b1edbc	248	This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
AnnaBridge	171:3a7713b1edbc	249
AnnaBridge	171:3a7713b1edbc	250	This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
AnnaBridge	171:3a7713b1edbc	251
AnnaBridge	171:3a7713b1edbc	252	uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
AnnaBridge	171:3a7713b1edbc	253	This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
AnnaBridge	171:3a7713b1edbc	254
AnnaBridge	171:3a7713b1edbc	255	This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
AnnaBridge	171:3a7713b1edbc	256
AnnaBridge	171:3a7713b1edbc	257	uint32_t OCPolarity; /*!< Specifies the output polarity.
AnnaBridge	171:3a7713b1edbc	258	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
AnnaBridge	171:3a7713b1edbc	259
AnnaBridge	171:3a7713b1edbc	260	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
AnnaBridge	171:3a7713b1edbc	261
AnnaBridge	171:3a7713b1edbc	262	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
AnnaBridge	171:3a7713b1edbc	263	This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
AnnaBridge	171:3a7713b1edbc	264
AnnaBridge	171:3a7713b1edbc	265	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
AnnaBridge	171:3a7713b1edbc	266
AnnaBridge	171:3a7713b1edbc	267
AnnaBridge	171:3a7713b1edbc	268	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge	171:3a7713b1edbc	269	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
AnnaBridge	171:3a7713b1edbc	270
AnnaBridge	171:3a7713b1edbc	271	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
AnnaBridge	171:3a7713b1edbc	272
AnnaBridge	171:3a7713b1edbc	273	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
AnnaBridge	171:3a7713b1edbc	274	This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
AnnaBridge	171:3a7713b1edbc	275
AnnaBridge	171:3a7713b1edbc	276	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
AnnaBridge	171:3a7713b1edbc	277	} LL_TIM_OC_InitTypeDef;
AnnaBridge	171:3a7713b1edbc	278
AnnaBridge	171:3a7713b1edbc	279	/**
AnnaBridge	171:3a7713b1edbc	280	* @brief TIM Input Capture configuration structure definition.
AnnaBridge	171:3a7713b1edbc	281	*/
AnnaBridge	171:3a7713b1edbc	282
AnnaBridge	171:3a7713b1edbc	283	typedef struct
AnnaBridge	171:3a7713b1edbc	284	{
AnnaBridge	171:3a7713b1edbc	285
AnnaBridge	171:3a7713b1edbc	286	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
AnnaBridge	171:3a7713b1edbc	287	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
AnnaBridge	171:3a7713b1edbc	288
AnnaBridge	171:3a7713b1edbc	289	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
AnnaBridge	171:3a7713b1edbc	290
AnnaBridge	171:3a7713b1edbc	291	uint32_t ICActiveInput; /*!< Specifies the input.
AnnaBridge	171:3a7713b1edbc	292	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
AnnaBridge	171:3a7713b1edbc	293
AnnaBridge	171:3a7713b1edbc	294	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
AnnaBridge	171:3a7713b1edbc	295
AnnaBridge	171:3a7713b1edbc	296	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge	171:3a7713b1edbc	297	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
AnnaBridge	171:3a7713b1edbc	298
AnnaBridge	171:3a7713b1edbc	299	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
AnnaBridge	171:3a7713b1edbc	300
AnnaBridge	171:3a7713b1edbc	301	uint32_t ICFilter; /*!< Specifies the input capture filter.
AnnaBridge	171:3a7713b1edbc	302	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
AnnaBridge	171:3a7713b1edbc	303
AnnaBridge	171:3a7713b1edbc	304	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
AnnaBridge	171:3a7713b1edbc	305	} LL_TIM_IC_InitTypeDef;
AnnaBridge	171:3a7713b1edbc	306
AnnaBridge	171:3a7713b1edbc	307
AnnaBridge	171:3a7713b1edbc	308	/**
AnnaBridge	171:3a7713b1edbc	309	* @brief TIM Encoder interface configuration structure definition.
AnnaBridge	171:3a7713b1edbc	310	*/
AnnaBridge	171:3a7713b1edbc	311	typedef struct
AnnaBridge	171:3a7713b1edbc	312	{
AnnaBridge	171:3a7713b1edbc	313	uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
AnnaBridge	171:3a7713b1edbc	314	This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
AnnaBridge	171:3a7713b1edbc	315
AnnaBridge	171:3a7713b1edbc	316	This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
AnnaBridge	171:3a7713b1edbc	317
AnnaBridge	171:3a7713b1edbc	318	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
AnnaBridge	171:3a7713b1edbc	319	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
AnnaBridge	171:3a7713b1edbc	320
AnnaBridge	171:3a7713b1edbc	321	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
AnnaBridge	171:3a7713b1edbc	322
AnnaBridge	171:3a7713b1edbc	323	uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
AnnaBridge	171:3a7713b1edbc	324	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
AnnaBridge	171:3a7713b1edbc	325
AnnaBridge	171:3a7713b1edbc	326	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
AnnaBridge	171:3a7713b1edbc	327
AnnaBridge	171:3a7713b1edbc	328	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
AnnaBridge	171:3a7713b1edbc	329	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
AnnaBridge	171:3a7713b1edbc	330
AnnaBridge	171:3a7713b1edbc	331	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
AnnaBridge	171:3a7713b1edbc	332
AnnaBridge	171:3a7713b1edbc	333	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
AnnaBridge	171:3a7713b1edbc	334	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
AnnaBridge	171:3a7713b1edbc	335
AnnaBridge	171:3a7713b1edbc	336	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
AnnaBridge	171:3a7713b1edbc	337
AnnaBridge	171:3a7713b1edbc	338	uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
AnnaBridge	171:3a7713b1edbc	339	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
AnnaBridge	171:3a7713b1edbc	340
AnnaBridge	171:3a7713b1edbc	341	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
AnnaBridge	171:3a7713b1edbc	342
AnnaBridge	171:3a7713b1edbc	343	uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
AnnaBridge	171:3a7713b1edbc	344	This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
AnnaBridge	171:3a7713b1edbc	345
AnnaBridge	171:3a7713b1edbc	346	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
AnnaBridge	171:3a7713b1edbc	347
AnnaBridge	171:3a7713b1edbc	348	uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
AnnaBridge	171:3a7713b1edbc	349	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
AnnaBridge	171:3a7713b1edbc	350
AnnaBridge	171:3a7713b1edbc	351	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
AnnaBridge	171:3a7713b1edbc	352
AnnaBridge	171:3a7713b1edbc	353	uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
AnnaBridge	171:3a7713b1edbc	354	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
AnnaBridge	171:3a7713b1edbc	355
AnnaBridge	171:3a7713b1edbc	356	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
AnnaBridge	171:3a7713b1edbc	357
AnnaBridge	171:3a7713b1edbc	358	} LL_TIM_ENCODER_InitTypeDef;
AnnaBridge	171:3a7713b1edbc	359
AnnaBridge	171:3a7713b1edbc	360	/**
AnnaBridge	171:3a7713b1edbc	361	* @brief TIM Hall sensor interface configuration structure definition.
AnnaBridge	171:3a7713b1edbc	362	*/
AnnaBridge	171:3a7713b1edbc	363	typedef struct
AnnaBridge	171:3a7713b1edbc	364	{
AnnaBridge	171:3a7713b1edbc	365
AnnaBridge	171:3a7713b1edbc	366	uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
AnnaBridge	171:3a7713b1edbc	367	This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
AnnaBridge	171:3a7713b1edbc	368
AnnaBridge	171:3a7713b1edbc	369	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
AnnaBridge	171:3a7713b1edbc	370
AnnaBridge	171:3a7713b1edbc	371	uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
AnnaBridge	171:3a7713b1edbc	372	Prescaler must be set to get a maximum counter period longer than the
AnnaBridge	171:3a7713b1edbc	373	time interval between 2 consecutive changes on the Hall inputs.
AnnaBridge	171:3a7713b1edbc	374	This parameter can be a value of @ref TIM_LL_EC_ICPSC.
AnnaBridge	171:3a7713b1edbc	375
AnnaBridge	171:3a7713b1edbc	376	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
AnnaBridge	171:3a7713b1edbc	377
AnnaBridge	171:3a7713b1edbc	378	uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
AnnaBridge	171:3a7713b1edbc	379	This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
AnnaBridge	171:3a7713b1edbc	380
AnnaBridge	171:3a7713b1edbc	381	This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
AnnaBridge	171:3a7713b1edbc	382
AnnaBridge	171:3a7713b1edbc	383	uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
AnnaBridge	171:3a7713b1edbc	384	A positive pulse (TRGO event) is generated with a programmable delay every time
AnnaBridge	171:3a7713b1edbc	385	a change occurs on the Hall inputs.
AnnaBridge	171:3a7713b1edbc	386	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
AnnaBridge	171:3a7713b1edbc	387
AnnaBridge	171:3a7713b1edbc	388	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
AnnaBridge	171:3a7713b1edbc	389	} LL_TIM_HALLSENSOR_InitTypeDef;
AnnaBridge	171:3a7713b1edbc	390
AnnaBridge	171:3a7713b1edbc	391	/**
AnnaBridge	171:3a7713b1edbc	392	* @brief BDTR (Break and Dead Time) structure definition
AnnaBridge	171:3a7713b1edbc	393	*/
AnnaBridge	171:3a7713b1edbc	394	typedef struct
AnnaBridge	171:3a7713b1edbc	395	{
AnnaBridge	171:3a7713b1edbc	396	uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
AnnaBridge	171:3a7713b1edbc	397	This parameter can be a value of @ref TIM_LL_EC_OSSR
AnnaBridge	171:3a7713b1edbc	398
AnnaBridge	171:3a7713b1edbc	399	This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
AnnaBridge	171:3a7713b1edbc	400
AnnaBridge	171:3a7713b1edbc	401	@note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
AnnaBridge	171:3a7713b1edbc	402
AnnaBridge	171:3a7713b1edbc	403	uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
AnnaBridge	171:3a7713b1edbc	404	This parameter can be a value of @ref TIM_LL_EC_OSSI
AnnaBridge	171:3a7713b1edbc	405
AnnaBridge	171:3a7713b1edbc	406	This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
AnnaBridge	171:3a7713b1edbc	407
AnnaBridge	171:3a7713b1edbc	408	@note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
AnnaBridge	171:3a7713b1edbc	409
AnnaBridge	171:3a7713b1edbc	410	uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
AnnaBridge	171:3a7713b1edbc	411	This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
AnnaBridge	171:3a7713b1edbc	412
AnnaBridge	171:3a7713b1edbc	413	@note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
AnnaBridge	171:3a7713b1edbc	414	has been written, their content is frozen until the next reset.*/
AnnaBridge	171:3a7713b1edbc	415
AnnaBridge	171:3a7713b1edbc	416	uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
AnnaBridge	171:3a7713b1edbc	417	switching-on of the outputs.
AnnaBridge	171:3a7713b1edbc	418	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
AnnaBridge	171:3a7713b1edbc	419
AnnaBridge	171:3a7713b1edbc	420	This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
AnnaBridge	171:3a7713b1edbc	421
AnnaBridge	171:3a7713b1edbc	422	@note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
AnnaBridge	171:3a7713b1edbc	423
AnnaBridge	171:3a7713b1edbc	424	uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
AnnaBridge	171:3a7713b1edbc	425	This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
AnnaBridge	171:3a7713b1edbc	426
AnnaBridge	171:3a7713b1edbc	427	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
AnnaBridge	171:3a7713b1edbc	428
AnnaBridge	171:3a7713b1edbc	429	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	171:3a7713b1edbc	430
AnnaBridge	171:3a7713b1edbc	431	uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
AnnaBridge	171:3a7713b1edbc	432	This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
AnnaBridge	171:3a7713b1edbc	433
AnnaBridge	171:3a7713b1edbc	434	This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
AnnaBridge	171:3a7713b1edbc	435
AnnaBridge	171:3a7713b1edbc	436	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	171:3a7713b1edbc	437
AnnaBridge	171:3a7713b1edbc	438	uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
AnnaBridge	171:3a7713b1edbc	439	This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
AnnaBridge	171:3a7713b1edbc	440
AnnaBridge	171:3a7713b1edbc	441	This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
AnnaBridge	171:3a7713b1edbc	442
AnnaBridge	171:3a7713b1edbc	443	@note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
AnnaBridge	171:3a7713b1edbc	444	} LL_TIM_BDTR_InitTypeDef;
AnnaBridge	171:3a7713b1edbc	445
AnnaBridge	171:3a7713b1edbc	446	/**
AnnaBridge	171:3a7713b1edbc	447	* @}
AnnaBridge	171:3a7713b1edbc	448	*/
AnnaBridge	171:3a7713b1edbc	449	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	171:3a7713b1edbc	450
AnnaBridge	171:3a7713b1edbc	451	/* Exported constants --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	452	/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
AnnaBridge	171:3a7713b1edbc	453	* @{
AnnaBridge	171:3a7713b1edbc	454	*/
AnnaBridge	171:3a7713b1edbc	455
AnnaBridge	171:3a7713b1edbc	456	/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	171:3a7713b1edbc	457	* @brief Flags defines which can be used with LL_TIM_ReadReg function.
AnnaBridge	171:3a7713b1edbc	458	* @{
AnnaBridge	171:3a7713b1edbc	459	*/
AnnaBridge	171:3a7713b1edbc	460	#define LL_TIM_SR_UIF TIM_SR_UIF /!< Update interrupt flag /
AnnaBridge	171:3a7713b1edbc	461	#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /!< Capture/compare 1 interrupt flag /
AnnaBridge	171:3a7713b1edbc	462	#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /!< Capture/compare 2 interrupt flag /
AnnaBridge	171:3a7713b1edbc	463	#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /!< Capture/compare 3 interrupt flag /
AnnaBridge	171:3a7713b1edbc	464	#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /!< Capture/compare 4 interrupt flag /
AnnaBridge	171:3a7713b1edbc	465	#define LL_TIM_SR_COMIF TIM_SR_COMIF /!< COM interrupt flag /
AnnaBridge	171:3a7713b1edbc	466	#define LL_TIM_SR_TIF TIM_SR_TIF /!< Trigger interrupt flag /
AnnaBridge	171:3a7713b1edbc	467	#define LL_TIM_SR_BIF TIM_SR_BIF /!< Break interrupt flag /
AnnaBridge	171:3a7713b1edbc	468	#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /!< Capture/Compare 1 overcapture flag /
AnnaBridge	171:3a7713b1edbc	469	#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /!< Capture/Compare 2 overcapture flag /
AnnaBridge	171:3a7713b1edbc	470	#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /!< Capture/Compare 3 overcapture flag /
AnnaBridge	171:3a7713b1edbc	471	#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /!< Capture/Compare 4 overcapture flag /
AnnaBridge	171:3a7713b1edbc	472	/**
AnnaBridge	171:3a7713b1edbc	473	* @}
AnnaBridge	171:3a7713b1edbc	474	*/
AnnaBridge	171:3a7713b1edbc	475
AnnaBridge	171:3a7713b1edbc	476	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	171:3a7713b1edbc	477	/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
AnnaBridge	171:3a7713b1edbc	478	* @{
AnnaBridge	171:3a7713b1edbc	479	*/
AnnaBridge	171:3a7713b1edbc	480	#define LL_TIM_BREAK_DISABLE 0x00000000U /!< Break function disabled /
AnnaBridge	171:3a7713b1edbc	481	#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /!< Break function enabled /
AnnaBridge	171:3a7713b1edbc	482	/**
AnnaBridge	171:3a7713b1edbc	483	* @}
AnnaBridge	171:3a7713b1edbc	484	*/
AnnaBridge	171:3a7713b1edbc	485
AnnaBridge	171:3a7713b1edbc	486	/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
AnnaBridge	171:3a7713b1edbc	487	* @{
AnnaBridge	171:3a7713b1edbc	488	*/
AnnaBridge	171:3a7713b1edbc	489	#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /!< MOE can be set only by software /
AnnaBridge	171:3a7713b1edbc	490	#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /!< MOE can be set by software or automatically at the next update event /
AnnaBridge	171:3a7713b1edbc	491	/**
AnnaBridge	171:3a7713b1edbc	492	* @}
AnnaBridge	171:3a7713b1edbc	493	*/
AnnaBridge	171:3a7713b1edbc	494	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	171:3a7713b1edbc	495
AnnaBridge	171:3a7713b1edbc	496	/** @defgroup TIM_LL_EC_IT IT Defines
AnnaBridge	171:3a7713b1edbc	497	* @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
AnnaBridge	171:3a7713b1edbc	498	* @{
AnnaBridge	171:3a7713b1edbc	499	*/
AnnaBridge	171:3a7713b1edbc	500	#define LL_TIM_DIER_UIE TIM_DIER_UIE /!< Update interrupt enable /
AnnaBridge	171:3a7713b1edbc	501	#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /!< Capture/compare 1 interrupt enable /
AnnaBridge	171:3a7713b1edbc	502	#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /!< Capture/compare 2 interrupt enable /
AnnaBridge	171:3a7713b1edbc	503	#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /!< Capture/compare 3 interrupt enable /
AnnaBridge	171:3a7713b1edbc	504	#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /!< Capture/compare 4 interrupt enable /
AnnaBridge	171:3a7713b1edbc	505	#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /!< COM interrupt enable /
AnnaBridge	171:3a7713b1edbc	506	#define LL_TIM_DIER_TIE TIM_DIER_TIE /!< Trigger interrupt enable /
AnnaBridge	171:3a7713b1edbc	507	#define LL_TIM_DIER_BIE TIM_DIER_BIE /!< Break interrupt enable /
AnnaBridge	171:3a7713b1edbc	508	/**
AnnaBridge	171:3a7713b1edbc	509	* @}
AnnaBridge	171:3a7713b1edbc	510	*/
AnnaBridge	171:3a7713b1edbc	511
AnnaBridge	171:3a7713b1edbc	512	/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
AnnaBridge	171:3a7713b1edbc	513	* @{
AnnaBridge	171:3a7713b1edbc	514	*/
AnnaBridge	171:3a7713b1edbc	515	#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request /
AnnaBridge	171:3a7713b1edbc	516	#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /!< Only counter overflow/underflow generates an update request /
AnnaBridge	171:3a7713b1edbc	517	/**
AnnaBridge	171:3a7713b1edbc	518	* @}
AnnaBridge	171:3a7713b1edbc	519	*/
AnnaBridge	171:3a7713b1edbc	520
AnnaBridge	171:3a7713b1edbc	521	/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
AnnaBridge	171:3a7713b1edbc	522	* @{
AnnaBridge	171:3a7713b1edbc	523	*/
AnnaBridge	171:3a7713b1edbc	524	#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /!< Counter is not stopped at update event /
AnnaBridge	171:3a7713b1edbc	525	#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /!< Counter stops counting at the next update event /
AnnaBridge	171:3a7713b1edbc	526	/**
AnnaBridge	171:3a7713b1edbc	527	* @}
AnnaBridge	171:3a7713b1edbc	528	*/
AnnaBridge	171:3a7713b1edbc	529
AnnaBridge	171:3a7713b1edbc	530	/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
AnnaBridge	171:3a7713b1edbc	531	* @{
AnnaBridge	171:3a7713b1edbc	532	*/
AnnaBridge	171:3a7713b1edbc	533	#define LL_TIM_COUNTERMODE_UP 0x00000000U /!<Counter used as upcounter /
AnnaBridge	171:3a7713b1edbc	534	#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /!< Counter used as downcounter /
AnnaBridge	171:3a7713b1edbc	535	#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. /
AnnaBridge	171:3a7713b1edbc	536	#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up /
AnnaBridge	171:3a7713b1edbc	537	#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. /
AnnaBridge	171:3a7713b1edbc	538	/**
AnnaBridge	171:3a7713b1edbc	539	* @}
AnnaBridge	171:3a7713b1edbc	540	*/
AnnaBridge	171:3a7713b1edbc	541
AnnaBridge	171:3a7713b1edbc	542	/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
AnnaBridge	171:3a7713b1edbc	543	* @{
AnnaBridge	171:3a7713b1edbc	544	*/
AnnaBridge	171:3a7713b1edbc	545	#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /!< tDTS=tCK_INT /
AnnaBridge	171:3a7713b1edbc	546	#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /!< tDTS=2tCK_INT */
AnnaBridge	171:3a7713b1edbc	547	#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /!< tDTS=4tCK_INT */
AnnaBridge	171:3a7713b1edbc	548	/**
AnnaBridge	171:3a7713b1edbc	549	* @}
AnnaBridge	171:3a7713b1edbc	550	*/
AnnaBridge	171:3a7713b1edbc	551
AnnaBridge	171:3a7713b1edbc	552	/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
AnnaBridge	171:3a7713b1edbc	553	* @{
AnnaBridge	171:3a7713b1edbc	554	*/
AnnaBridge	171:3a7713b1edbc	555	#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /!< Timer counter counts up /
AnnaBridge	171:3a7713b1edbc	556	#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /!< Timer counter counts down /
AnnaBridge	171:3a7713b1edbc	557	/**
AnnaBridge	171:3a7713b1edbc	558	* @}
AnnaBridge	171:3a7713b1edbc	559	*/
AnnaBridge	171:3a7713b1edbc	560
AnnaBridge	171:3a7713b1edbc	561	/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
AnnaBridge	171:3a7713b1edbc	562	* @{
AnnaBridge	171:3a7713b1edbc	563	*/
AnnaBridge	171:3a7713b1edbc	564	#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /!< Capture/compare control bits are updated by setting the COMG bit only /
AnnaBridge	171:3a7713b1edbc	565	#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) /
AnnaBridge	171:3a7713b1edbc	566	/**
AnnaBridge	171:3a7713b1edbc	567	* @}
AnnaBridge	171:3a7713b1edbc	568	*/
AnnaBridge	171:3a7713b1edbc	569
AnnaBridge	171:3a7713b1edbc	570	/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
AnnaBridge	171:3a7713b1edbc	571	* @{
AnnaBridge	171:3a7713b1edbc	572	*/
AnnaBridge	171:3a7713b1edbc	573	#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /!< CCx DMA request sent when CCx event occurs /
AnnaBridge	171:3a7713b1edbc	574	#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /!< CCx DMA requests sent when update event occurs /
AnnaBridge	171:3a7713b1edbc	575	/**
AnnaBridge	171:3a7713b1edbc	576	* @}
AnnaBridge	171:3a7713b1edbc	577	*/
AnnaBridge	171:3a7713b1edbc	578
AnnaBridge	171:3a7713b1edbc	579	/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
AnnaBridge	171:3a7713b1edbc	580	* @{
AnnaBridge	171:3a7713b1edbc	581	*/
AnnaBridge	171:3a7713b1edbc	582	#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /!< LOCK OFF - No bit is write protected /
AnnaBridge	171:3a7713b1edbc	583	#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /!< LOCK Level 1 /
AnnaBridge	171:3a7713b1edbc	584	#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /!< LOCK Level 2 /
AnnaBridge	171:3a7713b1edbc	585	#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /!< LOCK Level 3 /
AnnaBridge	171:3a7713b1edbc	586	/**
AnnaBridge	171:3a7713b1edbc	587	* @}
AnnaBridge	171:3a7713b1edbc	588	*/
AnnaBridge	171:3a7713b1edbc	589
AnnaBridge	171:3a7713b1edbc	590	/** @defgroup TIM_LL_EC_CHANNEL Channel
AnnaBridge	171:3a7713b1edbc	591	* @{
AnnaBridge	171:3a7713b1edbc	592	*/
AnnaBridge	171:3a7713b1edbc	593	#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /!< Timer input/output channel 1 /
AnnaBridge	171:3a7713b1edbc	594	#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /!< Timer complementary output channel 1 /
AnnaBridge	171:3a7713b1edbc	595	#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /!< Timer input/output channel 2 /
AnnaBridge	171:3a7713b1edbc	596	#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /!< Timer complementary output channel 2 /
AnnaBridge	171:3a7713b1edbc	597	#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /!< Timer input/output channel 3 /
AnnaBridge	171:3a7713b1edbc	598	#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /!< Timer complementary output channel 3 /
AnnaBridge	171:3a7713b1edbc	599	#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /!< Timer input/output channel 4 /
AnnaBridge	171:3a7713b1edbc	600	/**
AnnaBridge	171:3a7713b1edbc	601	* @}
AnnaBridge	171:3a7713b1edbc	602	*/
AnnaBridge	171:3a7713b1edbc	603
AnnaBridge	171:3a7713b1edbc	604	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	171:3a7713b1edbc	605	/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
AnnaBridge	171:3a7713b1edbc	606	* @{
AnnaBridge	171:3a7713b1edbc	607	*/
AnnaBridge	171:3a7713b1edbc	608	#define LL_TIM_OCSTATE_DISABLE 0x00000000U /!< OCx is not active /
AnnaBridge	171:3a7713b1edbc	609	#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /!< OCx signal is output on the corresponding output pin /
AnnaBridge	171:3a7713b1edbc	610	/**
AnnaBridge	171:3a7713b1edbc	611	* @}
AnnaBridge	171:3a7713b1edbc	612	*/
AnnaBridge	171:3a7713b1edbc	613	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	171:3a7713b1edbc	614
AnnaBridge	171:3a7713b1edbc	615	/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
AnnaBridge	171:3a7713b1edbc	616	* @{
AnnaBridge	171:3a7713b1edbc	617	*/
AnnaBridge	171:3a7713b1edbc	618	#define LL_TIM_OCMODE_FROZEN 0x00000000U /!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level /
AnnaBridge	171:3a7713b1edbc	619	#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /!<OCyREF is forced high on compare match/
AnnaBridge	171:3a7713b1edbc	620	#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /!<OCyREF is forced low on compare match/
AnnaBridge	171:3a7713b1edbc	621	#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<OCyREF toggles on compare match/
AnnaBridge	171:3a7713b1edbc	622	#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /!<OCyREF is forced low/
AnnaBridge	171:3a7713b1edbc	623	#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_0) /!<OCyREF is forced high/
AnnaBridge	171:3a7713b1edbc	624	#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1) /!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active./
AnnaBridge	171:3a7713b1edbc	625	#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 \| TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_0) /!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive/
AnnaBridge	171:3a7713b1edbc	626	/**
AnnaBridge	171:3a7713b1edbc	627	* @}
AnnaBridge	171:3a7713b1edbc	628	*/
AnnaBridge	171:3a7713b1edbc	629
AnnaBridge	171:3a7713b1edbc	630	/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
AnnaBridge	171:3a7713b1edbc	631	* @{
AnnaBridge	171:3a7713b1edbc	632	*/
AnnaBridge	171:3a7713b1edbc	633	#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /!< OCxactive high/
AnnaBridge	171:3a7713b1edbc	634	#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /!< OCxactive low/
AnnaBridge	171:3a7713b1edbc	635	/**
AnnaBridge	171:3a7713b1edbc	636	* @}
AnnaBridge	171:3a7713b1edbc	637	*/
AnnaBridge	171:3a7713b1edbc	638
AnnaBridge	171:3a7713b1edbc	639	/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
AnnaBridge	171:3a7713b1edbc	640	* @{
AnnaBridge	171:3a7713b1edbc	641	*/
AnnaBridge	171:3a7713b1edbc	642	#define LL_TIM_OCIDLESTATE_LOW 0x00000000U /!<OCx=0 (after a dead-time if OC is implemented) when MOE=0/
AnnaBridge	171:3a7713b1edbc	643	#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /!<OCx=1 (after a dead-time if OC is implemented) when MOE=0/
AnnaBridge	171:3a7713b1edbc	644	/**
AnnaBridge	171:3a7713b1edbc	645	* @}
AnnaBridge	171:3a7713b1edbc	646	*/
AnnaBridge	171:3a7713b1edbc	647
AnnaBridge	171:3a7713b1edbc	648
AnnaBridge	171:3a7713b1edbc	649	/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
AnnaBridge	171:3a7713b1edbc	650	* @{
AnnaBridge	171:3a7713b1edbc	651	*/
AnnaBridge	171:3a7713b1edbc	652	#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /!< ICx is mapped on TIx /
AnnaBridge	171:3a7713b1edbc	653	#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /!< ICx is mapped on TIy /
AnnaBridge	171:3a7713b1edbc	654	#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /!< ICx is mapped on TRC /
AnnaBridge	171:3a7713b1edbc	655	/**
AnnaBridge	171:3a7713b1edbc	656	* @}
AnnaBridge	171:3a7713b1edbc	657	*/
AnnaBridge	171:3a7713b1edbc	658
AnnaBridge	171:3a7713b1edbc	659	/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
AnnaBridge	171:3a7713b1edbc	660	* @{
AnnaBridge	171:3a7713b1edbc	661	*/
AnnaBridge	171:3a7713b1edbc	662	#define LL_TIM_ICPSC_DIV1 0x00000000U /!< No prescaler, capture is done each time an edge is detected on the capture input /
AnnaBridge	171:3a7713b1edbc	663	#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /!< Capture is done once every 2 events /
AnnaBridge	171:3a7713b1edbc	664	#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /!< Capture is done once every 4 events /
AnnaBridge	171:3a7713b1edbc	665	#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /!< Capture is done once every 8 events /
AnnaBridge	171:3a7713b1edbc	666	/**
AnnaBridge	171:3a7713b1edbc	667	* @}
AnnaBridge	171:3a7713b1edbc	668	*/
AnnaBridge	171:3a7713b1edbc	669
AnnaBridge	171:3a7713b1edbc	670	/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
AnnaBridge	171:3a7713b1edbc	671	* @{
AnnaBridge	171:3a7713b1edbc	672	*/
AnnaBridge	171:3a7713b1edbc	673	#define LL_TIM_IC_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
AnnaBridge	171:3a7713b1edbc	674	#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /!< fSAMPLING=fCK_INT, N=2 /
AnnaBridge	171:3a7713b1edbc	675	#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /!< fSAMPLING=fCK_INT, N=4 /
AnnaBridge	171:3a7713b1edbc	676	#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fCK_INT, N=8 /
AnnaBridge	171:3a7713b1edbc	677	#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /!< fSAMPLING=fDTS/2, N=6 /
AnnaBridge	171:3a7713b1edbc	678	#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/2, N=8 /
AnnaBridge	171:3a7713b1edbc	679	#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/4, N=6 /
AnnaBridge	171:3a7713b1edbc	680	#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/4, N=8 /
AnnaBridge	171:3a7713b1edbc	681	#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /!< fSAMPLING=fDTS/8, N=6 /
AnnaBridge	171:3a7713b1edbc	682	#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/8, N=8 /
AnnaBridge	171:3a7713b1edbc	683	#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	171:3a7713b1edbc	684	#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_1 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/16, N=6 /
AnnaBridge	171:3a7713b1edbc	685	#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2) << 16U) /!< fSAMPLING=fDTS/16, N=8 /
AnnaBridge	171:3a7713b1edbc	686	#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_0) << 16U) /!< fSAMPLING=fDTS/32, N=5 /
AnnaBridge	171:3a7713b1edbc	687	#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 \| TIM_CCMR1_IC1F_2 \| TIM_CCMR1_IC1F_1) << 16U) /!< fSAMPLING=fDTS/32, N=6 /
AnnaBridge	171:3a7713b1edbc	688	#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /!< fSAMPLING=fDTS/32, N=8 /
AnnaBridge	171:3a7713b1edbc	689	/**
AnnaBridge	171:3a7713b1edbc	690	* @}
AnnaBridge	171:3a7713b1edbc	691	*/
AnnaBridge	171:3a7713b1edbc	692
AnnaBridge	171:3a7713b1edbc	693	/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
AnnaBridge	171:3a7713b1edbc	694	* @{
AnnaBridge	171:3a7713b1edbc	695	*/
AnnaBridge	171:3a7713b1edbc	696	#define LL_TIM_IC_POLARITY_RISING 0x00000000U /!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted /
AnnaBridge	171:3a7713b1edbc	697	#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted /
AnnaBridge	171:3a7713b1edbc	698	#define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted /
AnnaBridge	171:3a7713b1edbc	699	/**
AnnaBridge	171:3a7713b1edbc	700	* @}
AnnaBridge	171:3a7713b1edbc	701	*/
AnnaBridge	171:3a7713b1edbc	702
AnnaBridge	171:3a7713b1edbc	703	/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
AnnaBridge	171:3a7713b1edbc	704	* @{
AnnaBridge	171:3a7713b1edbc	705	*/
AnnaBridge	171:3a7713b1edbc	706	#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /!< The timer is clocked by the internal clock provided from the RCC /
AnnaBridge	171:3a7713b1edbc	707	#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Counter counts at each rising or falling edge on a selected inpu t/
AnnaBridge	171:3a7713b1edbc	708	#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /!< Counter counts at each rising or falling edge on the external trigger input ETR /
AnnaBridge	171:3a7713b1edbc	709	/**
AnnaBridge	171:3a7713b1edbc	710	* @}
AnnaBridge	171:3a7713b1edbc	711	*/
AnnaBridge	171:3a7713b1edbc	712
AnnaBridge	171:3a7713b1edbc	713	/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
AnnaBridge	171:3a7713b1edbc	714	* @{
AnnaBridge	171:3a7713b1edbc	715	*/
AnnaBridge	171:3a7713b1edbc	716	#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level /
AnnaBridge	171:3a7713b1edbc	717	#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level /
AnnaBridge	171:3a7713b1edbc	718	#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0) /!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l /
AnnaBridge	171:3a7713b1edbc	719	/**
AnnaBridge	171:3a7713b1edbc	720	* @}
AnnaBridge	171:3a7713b1edbc	721	*/
AnnaBridge	171:3a7713b1edbc	722
AnnaBridge	171:3a7713b1edbc	723	/** @defgroup TIM_LL_EC_TRGO Trigger Output
AnnaBridge	171:3a7713b1edbc	724	* @{
AnnaBridge	171:3a7713b1edbc	725	*/
AnnaBridge	171:3a7713b1edbc	726	#define LL_TIM_TRGO_RESET 0x00000000U /!< UG bit from the TIMx_EGR register is used as trigger output /
AnnaBridge	171:3a7713b1edbc	727	#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /!< Counter Enable signal (CNT_EN) is used as trigger output /
AnnaBridge	171:3a7713b1edbc	728	#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /!< Update event is used as trigger output /
AnnaBridge	171:3a7713b1edbc	729	#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< CC1 capture or a compare match is used as trigger output /
AnnaBridge	171:3a7713b1edbc	730	#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /!< OC1REF signal is used as trigger output /
AnnaBridge	171:3a7713b1edbc	731	#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_0) /!< OC2REF signal is used as trigger output /
AnnaBridge	171:3a7713b1edbc	732	#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1) /!< OC3REF signal is used as trigger output /
AnnaBridge	171:3a7713b1edbc	733	#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0) /!< OC4REF signal is used as trigger output /
AnnaBridge	171:3a7713b1edbc	734	/**
AnnaBridge	171:3a7713b1edbc	735	* @}
AnnaBridge	171:3a7713b1edbc	736	*/
AnnaBridge	171:3a7713b1edbc	737
AnnaBridge	171:3a7713b1edbc	738
AnnaBridge	171:3a7713b1edbc	739	/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
AnnaBridge	171:3a7713b1edbc	740	* @{
AnnaBridge	171:3a7713b1edbc	741	*/
AnnaBridge	171:3a7713b1edbc	742	#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /!< Slave mode disabled /
AnnaBridge	171:3a7713b1edbc	743	#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter /
AnnaBridge	171:3a7713b1edbc	744	#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_0) /!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high /
AnnaBridge	171:3a7713b1edbc	745	#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 \| TIM_SMCR_SMS_1) /!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI /
AnnaBridge	171:3a7713b1edbc	746	/**
AnnaBridge	171:3a7713b1edbc	747	* @}
AnnaBridge	171:3a7713b1edbc	748	*/
AnnaBridge	171:3a7713b1edbc	749
AnnaBridge	171:3a7713b1edbc	750	/** @defgroup TIM_LL_EC_TS Trigger Selection
AnnaBridge	171:3a7713b1edbc	751	* @{
AnnaBridge	171:3a7713b1edbc	752	*/
AnnaBridge	171:3a7713b1edbc	753	#define LL_TIM_TS_ITR0 0x00000000U /!< Internal Trigger 0 (ITR0) is used as trigger input /
AnnaBridge	171:3a7713b1edbc	754	#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /!< Internal Trigger 1 (ITR1) is used as trigger input /
AnnaBridge	171:3a7713b1edbc	755	#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /!< Internal Trigger 2 (ITR2) is used as trigger input /
AnnaBridge	171:3a7713b1edbc	756	#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1) /!< Internal Trigger 3 (ITR3) is used as trigger input /
AnnaBridge	171:3a7713b1edbc	757	#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /!< TI1 Edge Detector (TI1F_ED) is used as trigger input /
AnnaBridge	171:3a7713b1edbc	758	#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_0) /!< Filtered Timer Input 1 (TI1FP1) is used as trigger input /
AnnaBridge	171:3a7713b1edbc	759	#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1) /!< Filtered Timer Input 2 (TI12P2) is used as trigger input /
AnnaBridge	171:3a7713b1edbc	760	#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 \| TIM_SMCR_TS_1 \| TIM_SMCR_TS_0) /!< Filtered external Trigger (ETRF) is used as trigger input /
AnnaBridge	171:3a7713b1edbc	761	/**
AnnaBridge	171:3a7713b1edbc	762	* @}
AnnaBridge	171:3a7713b1edbc	763	*/
AnnaBridge	171:3a7713b1edbc	764
AnnaBridge	171:3a7713b1edbc	765	/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
AnnaBridge	171:3a7713b1edbc	766	* @{
AnnaBridge	171:3a7713b1edbc	767	*/
AnnaBridge	171:3a7713b1edbc	768	#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /!< ETR is non-inverted, active at high level or rising edge /
AnnaBridge	171:3a7713b1edbc	769	#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /!< ETR is inverted, active at low level or falling edge /
AnnaBridge	171:3a7713b1edbc	770	/**
AnnaBridge	171:3a7713b1edbc	771	* @}
AnnaBridge	171:3a7713b1edbc	772	*/
AnnaBridge	171:3a7713b1edbc	773
AnnaBridge	171:3a7713b1edbc	774	/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
AnnaBridge	171:3a7713b1edbc	775	* @{
AnnaBridge	171:3a7713b1edbc	776	*/
AnnaBridge	171:3a7713b1edbc	777	#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /!< ETR prescaler OFF /
AnnaBridge	171:3a7713b1edbc	778	#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /!< ETR frequency is divided by 2 /
AnnaBridge	171:3a7713b1edbc	779	#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /!< ETR frequency is divided by 4 /
AnnaBridge	171:3a7713b1edbc	780	#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /!< ETR frequency is divided by 8 /
AnnaBridge	171:3a7713b1edbc	781	/**
AnnaBridge	171:3a7713b1edbc	782	* @}
AnnaBridge	171:3a7713b1edbc	783	*/
AnnaBridge	171:3a7713b1edbc	784
AnnaBridge	171:3a7713b1edbc	785	/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
AnnaBridge	171:3a7713b1edbc	786	* @{
AnnaBridge	171:3a7713b1edbc	787	*/
AnnaBridge	171:3a7713b1edbc	788	#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /!< No filter, sampling is done at fDTS /
AnnaBridge	171:3a7713b1edbc	789	#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /!< fSAMPLING=fCK_INT, N=2 /
AnnaBridge	171:3a7713b1edbc	790	#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /!< fSAMPLING=fCK_INT, N=4 /
AnnaBridge	171:3a7713b1edbc	791	#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fCK_INT, N=8 /
AnnaBridge	171:3a7713b1edbc	792	#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /!< fSAMPLING=fDTS/2, N=6 /
AnnaBridge	171:3a7713b1edbc	793	#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/2, N=8 /
AnnaBridge	171:3a7713b1edbc	794	#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/4, N=6 /
AnnaBridge	171:3a7713b1edbc	795	#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/4, N=8 /
AnnaBridge	171:3a7713b1edbc	796	#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /!< fSAMPLING=fDTS/8, N=8 /
AnnaBridge	171:3a7713b1edbc	797	#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	171:3a7713b1edbc	798	#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/16, N=6 /
AnnaBridge	171:3a7713b1edbc	799	#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_1 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/16, N=8 /
AnnaBridge	171:3a7713b1edbc	800	#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2) /!< fSAMPLING=fDTS/16, N=5 /
AnnaBridge	171:3a7713b1edbc	801	#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_0) /!< fSAMPLING=fDTS/32, N=5 /
AnnaBridge	171:3a7713b1edbc	802	#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 \| TIM_SMCR_ETF_2 \| TIM_SMCR_ETF_1) /!< fSAMPLING=fDTS/32, N=6 /
AnnaBridge	171:3a7713b1edbc	803	#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /!< fSAMPLING=fDTS/32, N=8 /
AnnaBridge	171:3a7713b1edbc	804	/**
AnnaBridge	171:3a7713b1edbc	805	* @}
AnnaBridge	171:3a7713b1edbc	806	*/
AnnaBridge	171:3a7713b1edbc	807
AnnaBridge	171:3a7713b1edbc	808
AnnaBridge	171:3a7713b1edbc	809	/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
AnnaBridge	171:3a7713b1edbc	810	* @{
AnnaBridge	171:3a7713b1edbc	811	*/
AnnaBridge	171:3a7713b1edbc	812	#define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /!< Break input BRK is active low /
AnnaBridge	171:3a7713b1edbc	813	#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /!< Break input BRK is active high /
AnnaBridge	171:3a7713b1edbc	814	/**
AnnaBridge	171:3a7713b1edbc	815	* @}
AnnaBridge	171:3a7713b1edbc	816	*/
AnnaBridge	171:3a7713b1edbc	817
AnnaBridge	171:3a7713b1edbc	818
AnnaBridge	171:3a7713b1edbc	819
AnnaBridge	171:3a7713b1edbc	820
AnnaBridge	171:3a7713b1edbc	821	/** @defgroup TIM_LL_EC_OSSI OSSI
AnnaBridge	171:3a7713b1edbc	822	* @{
AnnaBridge	171:3a7713b1edbc	823	*/
AnnaBridge	171:3a7713b1edbc	824	#define LL_TIM_OSSI_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
AnnaBridge	171:3a7713b1edbc	825	#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime /
AnnaBridge	171:3a7713b1edbc	826	/**
AnnaBridge	171:3a7713b1edbc	827	* @}
AnnaBridge	171:3a7713b1edbc	828	*/
AnnaBridge	171:3a7713b1edbc	829
AnnaBridge	171:3a7713b1edbc	830	/** @defgroup TIM_LL_EC_OSSR OSSR
AnnaBridge	171:3a7713b1edbc	831	* @{
AnnaBridge	171:3a7713b1edbc	832	*/
AnnaBridge	171:3a7713b1edbc	833	#define LL_TIM_OSSR_DISABLE 0x00000000U /!< When inactive, OCx/OCxN outputs are disabled /
AnnaBridge	171:3a7713b1edbc	834	#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 /
AnnaBridge	171:3a7713b1edbc	835	/**
AnnaBridge	171:3a7713b1edbc	836	* @}
AnnaBridge	171:3a7713b1edbc	837	*/
AnnaBridge	171:3a7713b1edbc	838
AnnaBridge	171:3a7713b1edbc	839
AnnaBridge	171:3a7713b1edbc	840	/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
AnnaBridge	171:3a7713b1edbc	841	* @{
AnnaBridge	171:3a7713b1edbc	842	*/
AnnaBridge	171:3a7713b1edbc	843	#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /!< TIMx_CR1 register is the DMA base address for DMA burst /
AnnaBridge	171:3a7713b1edbc	844	#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /!< TIMx_CR2 register is the DMA base address for DMA burst /
AnnaBridge	171:3a7713b1edbc	845	#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /!< TIMx_SMCR register is the DMA base address for DMA burst /
AnnaBridge	171:3a7713b1edbc	846	#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_DIER register is the DMA base address for DMA burst /
AnnaBridge	171:3a7713b1edbc	847	#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /!< TIMx_SR register is the DMA base address for DMA burst /
AnnaBridge	171:3a7713b1edbc	848	#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_EGR register is the DMA base address for DMA burst /
AnnaBridge	171:3a7713b1edbc	849	#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCMR1 register is the DMA base address for DMA burst /
AnnaBridge	171:3a7713b1edbc	850	#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCMR2 register is the DMA base address for DMA burst /
AnnaBridge	171:3a7713b1edbc	851	#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /!< TIMx_CCER register is the DMA base address for DMA burst /
AnnaBridge	171:3a7713b1edbc	852	#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 \| TIM_DCR_DBA_0) /!< TIMx_CNT register is the DMA base address for DMA burst /
AnnaBridge	171:3a7713b1edbc	853	#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1) /!< TIMx_PSC register is the DMA base address for DMA burst /
AnnaBridge	171:3a7713b1edbc	854	#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_ARR register is the DMA base address for DMA burst /
AnnaBridge	171:3a7713b1edbc	855	#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2) /!< TIMx_RCR register is the DMA base address for DMA burst /
AnnaBridge	171:3a7713b1edbc	856	#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_0) /!< TIMx_CCR1 register is the DMA base address for DMA burst /
AnnaBridge	171:3a7713b1edbc	857	#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1) /!< TIMx_CCR2 register is the DMA base address for DMA burst /
AnnaBridge	171:3a7713b1edbc	858	#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 \| TIM_DCR_DBA_2 \| TIM_DCR_DBA_1 \| TIM_DCR_DBA_0) /!< TIMx_CCR3 register is the DMA base address for DMA burst /
AnnaBridge	171:3a7713b1edbc	859	#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /!< TIMx_CCR4 register is the DMA base address for DMA burst /
AnnaBridge	171:3a7713b1edbc	860	#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 \| TIM_DCR_DBA_0) /!< TIMx_BDTR register is the DMA base address for DMA burst /
AnnaBridge	171:3a7713b1edbc	861
AnnaBridge	171:3a7713b1edbc	862
AnnaBridge	171:3a7713b1edbc	863	/**
AnnaBridge	171:3a7713b1edbc	864	* @}
AnnaBridge	171:3a7713b1edbc	865	*/
AnnaBridge	171:3a7713b1edbc	866
AnnaBridge	171:3a7713b1edbc	867	/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
AnnaBridge	171:3a7713b1edbc	868	* @{
AnnaBridge	171:3a7713b1edbc	869	*/
AnnaBridge	171:3a7713b1edbc	870	#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /!< Transfer is done to 1 register starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	871	#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /!< Transfer is done to 2 registers starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	872	#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /!< Transfer is done to 3 registers starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	873	#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 4 registers starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	874	#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /!< Transfer is done to 5 registers starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	875	#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 6 registers starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	876	#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 7 registers starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	877	#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 1 registers starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	878	#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /!< Transfer is done to 9 registers starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	879	#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_0) /!< Transfer is done to 10 registers starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	880	#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1) /!< Transfer is done to 11 registers starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	881	#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 12 registers starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	882	#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2) /!< Transfer is done to 13 registers starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	883	#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_0) /!< Transfer is done to 14 registers starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	884	#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1) /!< Transfer is done to 15 registers starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	885	#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 \| TIM_DCR_DBL_2 \| TIM_DCR_DBL_1 \| TIM_DCR_DBL_0) /!< Transfer is done to 16 registers starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	886	#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /!< Transfer is done to 17 registers starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	887	#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 \| TIM_DCR_DBL_0) /!< Transfer is done to 18 registers starting from the DMA burst base address /
AnnaBridge	171:3a7713b1edbc	888	/**
AnnaBridge	171:3a7713b1edbc	889	* @}
AnnaBridge	171:3a7713b1edbc	890	*/
AnnaBridge	171:3a7713b1edbc	891
AnnaBridge	171:3a7713b1edbc	892
AnnaBridge	171:3a7713b1edbc	893	#define LL_TIM_TIM14_TI1_RMP_GPIO TIM14_OR_RMP_MASK /!< TIM14_TI1 is connected to Ored GPIO /
AnnaBridge	171:3a7713b1edbc	894	#define LL_TIM_TIM14_TI1_RMP_RTC_CLK (TIM14_OR_TI1_RMP_0 \| TIM14_OR_RMP_MASK) /!< TIM14_TI1 is connected to RTC clock /
AnnaBridge	171:3a7713b1edbc	895	#define LL_TIM_TIM14_TI1_RMP_HSE (TIM14_OR_TI1_RMP_1 \| TIM14_OR_RMP_MASK) /!< TIM14_TI1 is connected to HSE/32 clock /
AnnaBridge	171:3a7713b1edbc	896	#define LL_TIM_TIM14_TI1_RMP_MCO (TIM14_OR_TI1_RMP_0 \| TIM14_OR_TI1_RMP_1 \| TIM14_OR_RMP_MASK) /!< TIM14_TI1 is connected to MCO /
AnnaBridge	171:3a7713b1edbc	897
AnnaBridge	171:3a7713b1edbc	898
AnnaBridge	171:3a7713b1edbc	899	/** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
AnnaBridge	171:3a7713b1edbc	900	* @{
AnnaBridge	171:3a7713b1edbc	901	*/
AnnaBridge	171:3a7713b1edbc	902	#define LL_TIM_OCREF_CLR_INT_OCREF_CLR 0x00000000U /!< OCREF_CLR_INT is connected to the OCREF_CLR input /
AnnaBridge	171:3a7713b1edbc	903	#define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /!< OCREF_CLR_INT is connected to ETRF /
AnnaBridge	171:3a7713b1edbc	904	/**
AnnaBridge	171:3a7713b1edbc	905	* @}
AnnaBridge	171:3a7713b1edbc	906	*/
AnnaBridge	171:3a7713b1edbc	907
AnnaBridge	171:3a7713b1edbc	908	/**
AnnaBridge	171:3a7713b1edbc	909	* @}
AnnaBridge	171:3a7713b1edbc	910	*/
AnnaBridge	171:3a7713b1edbc	911
AnnaBridge	171:3a7713b1edbc	912	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	913	/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
AnnaBridge	171:3a7713b1edbc	914	* @{
AnnaBridge	171:3a7713b1edbc	915	*/
AnnaBridge	171:3a7713b1edbc	916
AnnaBridge	171:3a7713b1edbc	917	/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	171:3a7713b1edbc	918	* @{
AnnaBridge	171:3a7713b1edbc	919	*/
AnnaBridge	171:3a7713b1edbc	920	/**
AnnaBridge	171:3a7713b1edbc	921	* @brief Write a value in TIM register.
AnnaBridge	171:3a7713b1edbc	922	* @param __INSTANCE__ TIM Instance
AnnaBridge	171:3a7713b1edbc	923	* @param __REG__ Register to be written
AnnaBridge	171:3a7713b1edbc	924	* @param __VALUE__ Value to be written in the register
AnnaBridge	171:3a7713b1edbc	925	* @retval None
AnnaBridge	171:3a7713b1edbc	926	*/
AnnaBridge	171:3a7713b1edbc	927	#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	171:3a7713b1edbc	928
AnnaBridge	171:3a7713b1edbc	929	/**
AnnaBridge	171:3a7713b1edbc	930	* @brief Read a value in TIM register.
AnnaBridge	171:3a7713b1edbc	931	* @param __INSTANCE__ TIM Instance
AnnaBridge	171:3a7713b1edbc	932	* @param __REG__ Register to be read
AnnaBridge	171:3a7713b1edbc	933	* @retval Register value
AnnaBridge	171:3a7713b1edbc	934	*/
AnnaBridge	171:3a7713b1edbc	935	#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	171:3a7713b1edbc	936	/**
AnnaBridge	171:3a7713b1edbc	937	* @}
AnnaBridge	171:3a7713b1edbc	938	*/
AnnaBridge	171:3a7713b1edbc	939
AnnaBridge	171:3a7713b1edbc	940	/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
AnnaBridge	171:3a7713b1edbc	941	* @{
AnnaBridge	171:3a7713b1edbc	942	*/
AnnaBridge	171:3a7713b1edbc	943
AnnaBridge	171:3a7713b1edbc	944	/**
AnnaBridge	171:3a7713b1edbc	945	* @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
AnnaBridge	171:3a7713b1edbc	946	* @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
AnnaBridge	171:3a7713b1edbc	947	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	948	* @param __CKD__ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	949	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
AnnaBridge	171:3a7713b1edbc	950	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
AnnaBridge	171:3a7713b1edbc	951	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
AnnaBridge	171:3a7713b1edbc	952	* @param __DT__ deadtime duration (in ns)
AnnaBridge	171:3a7713b1edbc	953	* @retval DTG[0:7]
AnnaBridge	171:3a7713b1edbc	954	*/
AnnaBridge	171:3a7713b1edbc	955	#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
AnnaBridge	171:3a7713b1edbc	956	( (((uint64_t)((__DT__)1000U)) < ((DT_DELAY_1+1U) TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
AnnaBridge	171:3a7713b1edbc	957	(((uint64_t)((__DT__)1000U)) < (64U + (DT_DELAY_2+1U)) 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 \| ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\
AnnaBridge	171:3a7713b1edbc	958	(((uint64_t)((__DT__)1000U)) < (32U + (DT_DELAY_3+1U)) 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\
AnnaBridge	171:3a7713b1edbc	959	(((uint64_t)((__DT__)1000U)) < (32U + (DT_DELAY_4+1U)) 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 \| ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\
AnnaBridge	171:3a7713b1edbc	960	0U)
AnnaBridge	171:3a7713b1edbc	961
AnnaBridge	171:3a7713b1edbc	962	/**
AnnaBridge	171:3a7713b1edbc	963	* @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
AnnaBridge	171:3a7713b1edbc	964	* @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
AnnaBridge	171:3a7713b1edbc	965	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	966	* @param __CNTCLK__ counter clock frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	967	* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	171:3a7713b1edbc	968	*/
AnnaBridge	171:3a7713b1edbc	969	#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
AnnaBridge	171:3a7713b1edbc	970	((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
AnnaBridge	171:3a7713b1edbc	971
AnnaBridge	171:3a7713b1edbc	972	/**
AnnaBridge	171:3a7713b1edbc	973	* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
AnnaBridge	171:3a7713b1edbc	974	* @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
AnnaBridge	171:3a7713b1edbc	975	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	976	* @param __PSC__ prescaler
AnnaBridge	171:3a7713b1edbc	977	* @param __FREQ__ output signal frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	978	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	171:3a7713b1edbc	979	*/
AnnaBridge	171:3a7713b1edbc	980	#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
AnnaBridge	171:3a7713b1edbc	981	(((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
AnnaBridge	171:3a7713b1edbc	982
AnnaBridge	171:3a7713b1edbc	983	/**
AnnaBridge	171:3a7713b1edbc	984	* @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
AnnaBridge	171:3a7713b1edbc	985	* @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
AnnaBridge	171:3a7713b1edbc	986	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	987	* @param __PSC__ prescaler
AnnaBridge	171:3a7713b1edbc	988	* @param __DELAY__ timer output compare active/inactive delay (in us)
AnnaBridge	171:3a7713b1edbc	989	* @retval Compare value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	171:3a7713b1edbc	990	*/
AnnaBridge	171:3a7713b1edbc	991	#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
AnnaBridge	171:3a7713b1edbc	992	((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
AnnaBridge	171:3a7713b1edbc	993	/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
AnnaBridge	171:3a7713b1edbc	994
AnnaBridge	171:3a7713b1edbc	995	/**
AnnaBridge	171:3a7713b1edbc	996	* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
AnnaBridge	171:3a7713b1edbc	997	* @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
AnnaBridge	171:3a7713b1edbc	998	* @param __TIMCLK__ timer input clock frequency (in Hz)
AnnaBridge	171:3a7713b1edbc	999	* @param __PSC__ prescaler
AnnaBridge	171:3a7713b1edbc	1000	* @param __DELAY__ timer output compare active/inactive delay (in us)
AnnaBridge	171:3a7713b1edbc	1001	* @param __PULSE__ pulse duration (in us)
AnnaBridge	171:3a7713b1edbc	1002	* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
AnnaBridge	171:3a7713b1edbc	1003	*/
AnnaBridge	171:3a7713b1edbc	1004	#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
AnnaBridge	171:3a7713b1edbc	1005	((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
AnnaBridge	171:3a7713b1edbc	1006	+ __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
AnnaBridge	171:3a7713b1edbc	1007
AnnaBridge	171:3a7713b1edbc	1008	/**
AnnaBridge	171:3a7713b1edbc	1009	* @brief HELPER macro retrieving the ratio of the input capture prescaler
AnnaBridge	171:3a7713b1edbc	1010	* @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
AnnaBridge	171:3a7713b1edbc	1011	* @param __ICPSC__ This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1012	* @arg @ref LL_TIM_ICPSC_DIV1
AnnaBridge	171:3a7713b1edbc	1013	* @arg @ref LL_TIM_ICPSC_DIV2
AnnaBridge	171:3a7713b1edbc	1014	* @arg @ref LL_TIM_ICPSC_DIV4
AnnaBridge	171:3a7713b1edbc	1015	* @arg @ref LL_TIM_ICPSC_DIV8
AnnaBridge	171:3a7713b1edbc	1016	* @retval Input capture prescaler ratio (1, 2, 4 or 8)
AnnaBridge	171:3a7713b1edbc	1017	*/
AnnaBridge	171:3a7713b1edbc	1018	#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
AnnaBridge	171:3a7713b1edbc	1019	((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
AnnaBridge	171:3a7713b1edbc	1020
AnnaBridge	171:3a7713b1edbc	1021
AnnaBridge	171:3a7713b1edbc	1022	/**
AnnaBridge	171:3a7713b1edbc	1023	* @}
AnnaBridge	171:3a7713b1edbc	1024	*/
AnnaBridge	171:3a7713b1edbc	1025
AnnaBridge	171:3a7713b1edbc	1026
AnnaBridge	171:3a7713b1edbc	1027	/**
AnnaBridge	171:3a7713b1edbc	1028	* @}
AnnaBridge	171:3a7713b1edbc	1029	*/
AnnaBridge	171:3a7713b1edbc	1030
AnnaBridge	171:3a7713b1edbc	1031	/* Exported functions --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	1032	/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
AnnaBridge	171:3a7713b1edbc	1033	* @{
AnnaBridge	171:3a7713b1edbc	1034	*/
AnnaBridge	171:3a7713b1edbc	1035
AnnaBridge	171:3a7713b1edbc	1036	/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
AnnaBridge	171:3a7713b1edbc	1037	* @{
AnnaBridge	171:3a7713b1edbc	1038	*/
AnnaBridge	171:3a7713b1edbc	1039	/**
AnnaBridge	171:3a7713b1edbc	1040	* @brief Enable timer counter.
AnnaBridge	171:3a7713b1edbc	1041	* @rmtoll CR1 CEN LL_TIM_EnableCounter
AnnaBridge	171:3a7713b1edbc	1042	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1043	* @retval None
AnnaBridge	171:3a7713b1edbc	1044	*/
AnnaBridge	171:3a7713b1edbc	1045	__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1046	{
AnnaBridge	171:3a7713b1edbc	1047	SET_BIT(TIMx->CR1, TIM_CR1_CEN);
AnnaBridge	171:3a7713b1edbc	1048	}
AnnaBridge	171:3a7713b1edbc	1049
AnnaBridge	171:3a7713b1edbc	1050	/**
AnnaBridge	171:3a7713b1edbc	1051	* @brief Disable timer counter.
AnnaBridge	171:3a7713b1edbc	1052	* @rmtoll CR1 CEN LL_TIM_DisableCounter
AnnaBridge	171:3a7713b1edbc	1053	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1054	* @retval None
AnnaBridge	171:3a7713b1edbc	1055	*/
AnnaBridge	171:3a7713b1edbc	1056	__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1057	{
AnnaBridge	171:3a7713b1edbc	1058	CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
AnnaBridge	171:3a7713b1edbc	1059	}
AnnaBridge	171:3a7713b1edbc	1060
AnnaBridge	171:3a7713b1edbc	1061	/**
AnnaBridge	171:3a7713b1edbc	1062	* @brief Indicates whether the timer counter is enabled.
AnnaBridge	171:3a7713b1edbc	1063	* @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
AnnaBridge	171:3a7713b1edbc	1064	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1065	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1066	*/
AnnaBridge	171:3a7713b1edbc	1067	__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1068	{
AnnaBridge	171:3a7713b1edbc	1069	return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
AnnaBridge	171:3a7713b1edbc	1070	}
AnnaBridge	171:3a7713b1edbc	1071
AnnaBridge	171:3a7713b1edbc	1072	/**
AnnaBridge	171:3a7713b1edbc	1073	* @brief Enable update event generation.
AnnaBridge	171:3a7713b1edbc	1074	* @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
AnnaBridge	171:3a7713b1edbc	1075	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1076	* @retval None
AnnaBridge	171:3a7713b1edbc	1077	*/
AnnaBridge	171:3a7713b1edbc	1078	__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1079	{
AnnaBridge	171:3a7713b1edbc	1080	CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
AnnaBridge	171:3a7713b1edbc	1081	}
AnnaBridge	171:3a7713b1edbc	1082
AnnaBridge	171:3a7713b1edbc	1083	/**
AnnaBridge	171:3a7713b1edbc	1084	* @brief Disable update event generation.
AnnaBridge	171:3a7713b1edbc	1085	* @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
AnnaBridge	171:3a7713b1edbc	1086	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1087	* @retval None
AnnaBridge	171:3a7713b1edbc	1088	*/
AnnaBridge	171:3a7713b1edbc	1089	__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1090	{
AnnaBridge	171:3a7713b1edbc	1091	SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
AnnaBridge	171:3a7713b1edbc	1092	}
AnnaBridge	171:3a7713b1edbc	1093
AnnaBridge	171:3a7713b1edbc	1094	/**
AnnaBridge	171:3a7713b1edbc	1095	* @brief Indicates whether update event generation is enabled.
AnnaBridge	171:3a7713b1edbc	1096	* @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
AnnaBridge	171:3a7713b1edbc	1097	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1098	* @retval Inverted state of bit (0 or 1).
AnnaBridge	171:3a7713b1edbc	1099	*/
AnnaBridge	171:3a7713b1edbc	1100	__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1101	{
AnnaBridge	171:3a7713b1edbc	1102	return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == RESET);
AnnaBridge	171:3a7713b1edbc	1103	}
AnnaBridge	171:3a7713b1edbc	1104
AnnaBridge	171:3a7713b1edbc	1105	/**
AnnaBridge	171:3a7713b1edbc	1106	* @brief Set update event source
AnnaBridge	171:3a7713b1edbc	1107	* @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
AnnaBridge	171:3a7713b1edbc	1108	* generate an update interrupt or DMA request if enabled:
AnnaBridge	171:3a7713b1edbc	1109	* - Counter overflow/underflow
AnnaBridge	171:3a7713b1edbc	1110	* - Setting the UG bit
AnnaBridge	171:3a7713b1edbc	1111	* - Update generation through the slave mode controller
AnnaBridge	171:3a7713b1edbc	1112	* @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
AnnaBridge	171:3a7713b1edbc	1113	* overflow/underflow generates an update interrupt or DMA request if enabled.
AnnaBridge	171:3a7713b1edbc	1114	* @rmtoll CR1 URS LL_TIM_SetUpdateSource
AnnaBridge	171:3a7713b1edbc	1115	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1116	* @param UpdateSource This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1117	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
AnnaBridge	171:3a7713b1edbc	1118	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
AnnaBridge	171:3a7713b1edbc	1119	* @retval None
AnnaBridge	171:3a7713b1edbc	1120	*/
AnnaBridge	171:3a7713b1edbc	1121	__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
AnnaBridge	171:3a7713b1edbc	1122	{
AnnaBridge	171:3a7713b1edbc	1123	MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
AnnaBridge	171:3a7713b1edbc	1124	}
AnnaBridge	171:3a7713b1edbc	1125
AnnaBridge	171:3a7713b1edbc	1126	/**
AnnaBridge	171:3a7713b1edbc	1127	* @brief Get actual event update source
AnnaBridge	171:3a7713b1edbc	1128	* @rmtoll CR1 URS LL_TIM_GetUpdateSource
AnnaBridge	171:3a7713b1edbc	1129	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1130	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1131	* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
AnnaBridge	171:3a7713b1edbc	1132	* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
AnnaBridge	171:3a7713b1edbc	1133	*/
AnnaBridge	171:3a7713b1edbc	1134	__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1135	{
AnnaBridge	171:3a7713b1edbc	1136	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
AnnaBridge	171:3a7713b1edbc	1137	}
AnnaBridge	171:3a7713b1edbc	1138
AnnaBridge	171:3a7713b1edbc	1139	/**
AnnaBridge	171:3a7713b1edbc	1140	* @brief Set one pulse mode (one shot v.s. repetitive).
AnnaBridge	171:3a7713b1edbc	1141	* @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
AnnaBridge	171:3a7713b1edbc	1142	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1143	* @param OnePulseMode This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1144	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
AnnaBridge	171:3a7713b1edbc	1145	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
AnnaBridge	171:3a7713b1edbc	1146	* @retval None
AnnaBridge	171:3a7713b1edbc	1147	*/
AnnaBridge	171:3a7713b1edbc	1148	__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
AnnaBridge	171:3a7713b1edbc	1149	{
AnnaBridge	171:3a7713b1edbc	1150	MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
AnnaBridge	171:3a7713b1edbc	1151	}
AnnaBridge	171:3a7713b1edbc	1152
AnnaBridge	171:3a7713b1edbc	1153	/**
AnnaBridge	171:3a7713b1edbc	1154	* @brief Get actual one pulse mode.
AnnaBridge	171:3a7713b1edbc	1155	* @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
AnnaBridge	171:3a7713b1edbc	1156	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1157	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1158	* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
AnnaBridge	171:3a7713b1edbc	1159	* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
AnnaBridge	171:3a7713b1edbc	1160	*/
AnnaBridge	171:3a7713b1edbc	1161	__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1162	{
AnnaBridge	171:3a7713b1edbc	1163	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
AnnaBridge	171:3a7713b1edbc	1164	}
AnnaBridge	171:3a7713b1edbc	1165
AnnaBridge	171:3a7713b1edbc	1166	/**
AnnaBridge	171:3a7713b1edbc	1167	* @brief Set the timer counter counting mode.
AnnaBridge	171:3a7713b1edbc	1168	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
AnnaBridge	171:3a7713b1edbc	1169	* check whether or not the counter mode selection feature is supported
AnnaBridge	171:3a7713b1edbc	1170	* by a timer instance.
AnnaBridge	171:3a7713b1edbc	1171	* @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
AnnaBridge	171:3a7713b1edbc	1172	* CR1 CMS LL_TIM_SetCounterMode
AnnaBridge	171:3a7713b1edbc	1173	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1174	* @param CounterMode This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1175	* @arg @ref LL_TIM_COUNTERMODE_UP
AnnaBridge	171:3a7713b1edbc	1176	* @arg @ref LL_TIM_COUNTERMODE_DOWN
AnnaBridge	171:3a7713b1edbc	1177	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
AnnaBridge	171:3a7713b1edbc	1178	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
AnnaBridge	171:3a7713b1edbc	1179	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
AnnaBridge	171:3a7713b1edbc	1180	* @retval None
AnnaBridge	171:3a7713b1edbc	1181	*/
AnnaBridge	171:3a7713b1edbc	1182	__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
AnnaBridge	171:3a7713b1edbc	1183	{
AnnaBridge	171:3a7713b1edbc	1184	MODIFY_REG(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS, CounterMode);
AnnaBridge	171:3a7713b1edbc	1185	}
AnnaBridge	171:3a7713b1edbc	1186
AnnaBridge	171:3a7713b1edbc	1187	/**
AnnaBridge	171:3a7713b1edbc	1188	* @brief Get actual counter mode.
AnnaBridge	171:3a7713b1edbc	1189	* @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
AnnaBridge	171:3a7713b1edbc	1190	* check whether or not the counter mode selection feature is supported
AnnaBridge	171:3a7713b1edbc	1191	* by a timer instance.
AnnaBridge	171:3a7713b1edbc	1192	* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
AnnaBridge	171:3a7713b1edbc	1193	* CR1 CMS LL_TIM_GetCounterMode
AnnaBridge	171:3a7713b1edbc	1194	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1195	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1196	* @arg @ref LL_TIM_COUNTERMODE_UP
AnnaBridge	171:3a7713b1edbc	1197	* @arg @ref LL_TIM_COUNTERMODE_DOWN
AnnaBridge	171:3a7713b1edbc	1198	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
AnnaBridge	171:3a7713b1edbc	1199	* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
AnnaBridge	171:3a7713b1edbc	1200	* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
AnnaBridge	171:3a7713b1edbc	1201	*/
AnnaBridge	171:3a7713b1edbc	1202	__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1203	{
AnnaBridge	171:3a7713b1edbc	1204	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR \| TIM_CR1_CMS));
AnnaBridge	171:3a7713b1edbc	1205	}
AnnaBridge	171:3a7713b1edbc	1206
AnnaBridge	171:3a7713b1edbc	1207	/**
AnnaBridge	171:3a7713b1edbc	1208	* @brief Enable auto-reload (ARR) preload.
AnnaBridge	171:3a7713b1edbc	1209	* @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
AnnaBridge	171:3a7713b1edbc	1210	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1211	* @retval None
AnnaBridge	171:3a7713b1edbc	1212	*/
AnnaBridge	171:3a7713b1edbc	1213	__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1214	{
AnnaBridge	171:3a7713b1edbc	1215	SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
AnnaBridge	171:3a7713b1edbc	1216	}
AnnaBridge	171:3a7713b1edbc	1217
AnnaBridge	171:3a7713b1edbc	1218	/**
AnnaBridge	171:3a7713b1edbc	1219	* @brief Disable auto-reload (ARR) preload.
AnnaBridge	171:3a7713b1edbc	1220	* @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
AnnaBridge	171:3a7713b1edbc	1221	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1222	* @retval None
AnnaBridge	171:3a7713b1edbc	1223	*/
AnnaBridge	171:3a7713b1edbc	1224	__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1225	{
AnnaBridge	171:3a7713b1edbc	1226	CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
AnnaBridge	171:3a7713b1edbc	1227	}
AnnaBridge	171:3a7713b1edbc	1228
AnnaBridge	171:3a7713b1edbc	1229	/**
AnnaBridge	171:3a7713b1edbc	1230	* @brief Indicates whether auto-reload (ARR) preload is enabled.
AnnaBridge	171:3a7713b1edbc	1231	* @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
AnnaBridge	171:3a7713b1edbc	1232	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1233	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1234	*/
AnnaBridge	171:3a7713b1edbc	1235	__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1236	{
AnnaBridge	171:3a7713b1edbc	1237	return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
AnnaBridge	171:3a7713b1edbc	1238	}
AnnaBridge	171:3a7713b1edbc	1239
AnnaBridge	171:3a7713b1edbc	1240	/**
AnnaBridge	171:3a7713b1edbc	1241	* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
AnnaBridge	171:3a7713b1edbc	1242	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	1243	* whether or not the clock division feature is supported by the timer
AnnaBridge	171:3a7713b1edbc	1244	* instance.
AnnaBridge	171:3a7713b1edbc	1245	* @rmtoll CR1 CKD LL_TIM_SetClockDivision
AnnaBridge	171:3a7713b1edbc	1246	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1247	* @param ClockDivision This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1248	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
AnnaBridge	171:3a7713b1edbc	1249	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
AnnaBridge	171:3a7713b1edbc	1250	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
AnnaBridge	171:3a7713b1edbc	1251	* @retval None
AnnaBridge	171:3a7713b1edbc	1252	*/
AnnaBridge	171:3a7713b1edbc	1253	__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
AnnaBridge	171:3a7713b1edbc	1254	{
AnnaBridge	171:3a7713b1edbc	1255	MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
AnnaBridge	171:3a7713b1edbc	1256	}
AnnaBridge	171:3a7713b1edbc	1257
AnnaBridge	171:3a7713b1edbc	1258	/**
AnnaBridge	171:3a7713b1edbc	1259	* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
AnnaBridge	171:3a7713b1edbc	1260	* @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	1261	* whether or not the clock division feature is supported by the timer
AnnaBridge	171:3a7713b1edbc	1262	* instance.
AnnaBridge	171:3a7713b1edbc	1263	* @rmtoll CR1 CKD LL_TIM_GetClockDivision
AnnaBridge	171:3a7713b1edbc	1264	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1265	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1266	* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
AnnaBridge	171:3a7713b1edbc	1267	* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
AnnaBridge	171:3a7713b1edbc	1268	* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
AnnaBridge	171:3a7713b1edbc	1269	*/
AnnaBridge	171:3a7713b1edbc	1270	__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1271	{
AnnaBridge	171:3a7713b1edbc	1272	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
AnnaBridge	171:3a7713b1edbc	1273	}
AnnaBridge	171:3a7713b1edbc	1274
AnnaBridge	171:3a7713b1edbc	1275	/**
AnnaBridge	171:3a7713b1edbc	1276	* @brief Set the counter value.
AnnaBridge	171:3a7713b1edbc	1277	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	1278	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	171:3a7713b1edbc	1279	* @rmtoll CNT CNT LL_TIM_SetCounter
AnnaBridge	171:3a7713b1edbc	1280	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1281	* @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	1282	* @retval None
AnnaBridge	171:3a7713b1edbc	1283	*/
AnnaBridge	171:3a7713b1edbc	1284	__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
AnnaBridge	171:3a7713b1edbc	1285	{
AnnaBridge	171:3a7713b1edbc	1286	WRITE_REG(TIMx->CNT, Counter);
AnnaBridge	171:3a7713b1edbc	1287	}
AnnaBridge	171:3a7713b1edbc	1288
AnnaBridge	171:3a7713b1edbc	1289	/**
AnnaBridge	171:3a7713b1edbc	1290	* @brief Get the counter value.
AnnaBridge	171:3a7713b1edbc	1291	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	1292	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	171:3a7713b1edbc	1293	* @rmtoll CNT CNT LL_TIM_GetCounter
AnnaBridge	171:3a7713b1edbc	1294	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1295	* @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
AnnaBridge	171:3a7713b1edbc	1296	*/
AnnaBridge	171:3a7713b1edbc	1297	__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1298	{
AnnaBridge	171:3a7713b1edbc	1299	return (uint32_t)(READ_REG(TIMx->CNT));
AnnaBridge	171:3a7713b1edbc	1300	}
AnnaBridge	171:3a7713b1edbc	1301
AnnaBridge	171:3a7713b1edbc	1302	/**
AnnaBridge	171:3a7713b1edbc	1303	* @brief Get the current direction of the counter
AnnaBridge	171:3a7713b1edbc	1304	* @rmtoll CR1 DIR LL_TIM_GetDirection
AnnaBridge	171:3a7713b1edbc	1305	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1306	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1307	* @arg @ref LL_TIM_COUNTERDIRECTION_UP
AnnaBridge	171:3a7713b1edbc	1308	* @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
AnnaBridge	171:3a7713b1edbc	1309	*/
AnnaBridge	171:3a7713b1edbc	1310	__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1311	{
AnnaBridge	171:3a7713b1edbc	1312	return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
AnnaBridge	171:3a7713b1edbc	1313	}
AnnaBridge	171:3a7713b1edbc	1314
AnnaBridge	171:3a7713b1edbc	1315	/**
AnnaBridge	171:3a7713b1edbc	1316	* @brief Set the prescaler value.
AnnaBridge	171:3a7713b1edbc	1317	* @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
AnnaBridge	171:3a7713b1edbc	1318	* @note The prescaler can be changed on the fly as this control register is buffered. The new
AnnaBridge	171:3a7713b1edbc	1319	* prescaler ratio is taken into account at the next update event.
AnnaBridge	171:3a7713b1edbc	1320	* @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
AnnaBridge	171:3a7713b1edbc	1321	* @rmtoll PSC PSC LL_TIM_SetPrescaler
AnnaBridge	171:3a7713b1edbc	1322	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1323	* @param Prescaler between Min_Data=0 and Max_Data=65535
AnnaBridge	171:3a7713b1edbc	1324	* @retval None
AnnaBridge	171:3a7713b1edbc	1325	*/
AnnaBridge	171:3a7713b1edbc	1326	__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
AnnaBridge	171:3a7713b1edbc	1327	{
AnnaBridge	171:3a7713b1edbc	1328	WRITE_REG(TIMx->PSC, Prescaler);
AnnaBridge	171:3a7713b1edbc	1329	}
AnnaBridge	171:3a7713b1edbc	1330
AnnaBridge	171:3a7713b1edbc	1331	/**
AnnaBridge	171:3a7713b1edbc	1332	* @brief Get the prescaler value.
AnnaBridge	171:3a7713b1edbc	1333	* @rmtoll PSC PSC LL_TIM_GetPrescaler
AnnaBridge	171:3a7713b1edbc	1334	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1335	* @retval Prescaler value between Min_Data=0 and Max_Data=65535
AnnaBridge	171:3a7713b1edbc	1336	*/
AnnaBridge	171:3a7713b1edbc	1337	__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1338	{
AnnaBridge	171:3a7713b1edbc	1339	return (uint32_t)(READ_REG(TIMx->PSC));
AnnaBridge	171:3a7713b1edbc	1340	}
AnnaBridge	171:3a7713b1edbc	1341
AnnaBridge	171:3a7713b1edbc	1342	/**
AnnaBridge	171:3a7713b1edbc	1343	* @brief Set the auto-reload value.
AnnaBridge	171:3a7713b1edbc	1344	* @note The counter is blocked while the auto-reload value is null.
AnnaBridge	171:3a7713b1edbc	1345	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	1346	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	171:3a7713b1edbc	1347	* @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
AnnaBridge	171:3a7713b1edbc	1348	* @rmtoll ARR ARR LL_TIM_SetAutoReload
AnnaBridge	171:3a7713b1edbc	1349	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1350	* @param AutoReload between Min_Data=0 and Max_Data=65535
AnnaBridge	171:3a7713b1edbc	1351	* @retval None
AnnaBridge	171:3a7713b1edbc	1352	*/
AnnaBridge	171:3a7713b1edbc	1353	__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
AnnaBridge	171:3a7713b1edbc	1354	{
AnnaBridge	171:3a7713b1edbc	1355	WRITE_REG(TIMx->ARR, AutoReload);
AnnaBridge	171:3a7713b1edbc	1356	}
AnnaBridge	171:3a7713b1edbc	1357
AnnaBridge	171:3a7713b1edbc	1358	/**
AnnaBridge	171:3a7713b1edbc	1359	* @brief Get the auto-reload value.
AnnaBridge	171:3a7713b1edbc	1360	* @rmtoll ARR ARR LL_TIM_GetAutoReload
AnnaBridge	171:3a7713b1edbc	1361	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	1362	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	171:3a7713b1edbc	1363	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1364	* @retval Auto-reload value
AnnaBridge	171:3a7713b1edbc	1365	*/
AnnaBridge	171:3a7713b1edbc	1366	__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1367	{
AnnaBridge	171:3a7713b1edbc	1368	return (uint32_t)(READ_REG(TIMx->ARR));
AnnaBridge	171:3a7713b1edbc	1369	}
AnnaBridge	171:3a7713b1edbc	1370
AnnaBridge	171:3a7713b1edbc	1371	/**
AnnaBridge	171:3a7713b1edbc	1372	* @brief Set the repetition counter value.
AnnaBridge	171:3a7713b1edbc	1373	* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	1374	* whether or not a timer instance supports a repetition counter.
AnnaBridge	171:3a7713b1edbc	1375	* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
AnnaBridge	171:3a7713b1edbc	1376	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1377	* @param RepetitionCounter between Min_Data=0 and Max_Data=255
AnnaBridge	171:3a7713b1edbc	1378	* @retval None
AnnaBridge	171:3a7713b1edbc	1379	*/
AnnaBridge	171:3a7713b1edbc	1380	__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
AnnaBridge	171:3a7713b1edbc	1381	{
AnnaBridge	171:3a7713b1edbc	1382	WRITE_REG(TIMx->RCR, RepetitionCounter);
AnnaBridge	171:3a7713b1edbc	1383	}
AnnaBridge	171:3a7713b1edbc	1384
AnnaBridge	171:3a7713b1edbc	1385	/**
AnnaBridge	171:3a7713b1edbc	1386	* @brief Get the repetition counter value.
AnnaBridge	171:3a7713b1edbc	1387	* @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	1388	* whether or not a timer instance supports a repetition counter.
AnnaBridge	171:3a7713b1edbc	1389	* @rmtoll RCR REP LL_TIM_GetRepetitionCounter
AnnaBridge	171:3a7713b1edbc	1390	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1391	* @retval Repetition counter value
AnnaBridge	171:3a7713b1edbc	1392	*/
AnnaBridge	171:3a7713b1edbc	1393	__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1394	{
AnnaBridge	171:3a7713b1edbc	1395	return (uint32_t)(READ_REG(TIMx->RCR));
AnnaBridge	171:3a7713b1edbc	1396	}
AnnaBridge	171:3a7713b1edbc	1397
AnnaBridge	171:3a7713b1edbc	1398	/**
AnnaBridge	171:3a7713b1edbc	1399	* @}
AnnaBridge	171:3a7713b1edbc	1400	*/
AnnaBridge	171:3a7713b1edbc	1401
AnnaBridge	171:3a7713b1edbc	1402	/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
AnnaBridge	171:3a7713b1edbc	1403	* @{
AnnaBridge	171:3a7713b1edbc	1404	*/
AnnaBridge	171:3a7713b1edbc	1405	/**
AnnaBridge	171:3a7713b1edbc	1406	* @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
AnnaBridge	171:3a7713b1edbc	1407	* @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
AnnaBridge	171:3a7713b1edbc	1408	* they are updated only when a commutation event (COM) occurs.
AnnaBridge	171:3a7713b1edbc	1409	* @note Only on channels that have a complementary output.
AnnaBridge	171:3a7713b1edbc	1410	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	1411	* whether or not a timer instance is able to generate a commutation event.
AnnaBridge	171:3a7713b1edbc	1412	* @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
AnnaBridge	171:3a7713b1edbc	1413	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1414	* @retval None
AnnaBridge	171:3a7713b1edbc	1415	*/
AnnaBridge	171:3a7713b1edbc	1416	__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1417	{
AnnaBridge	171:3a7713b1edbc	1418	SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
AnnaBridge	171:3a7713b1edbc	1419	}
AnnaBridge	171:3a7713b1edbc	1420
AnnaBridge	171:3a7713b1edbc	1421	/**
AnnaBridge	171:3a7713b1edbc	1422	* @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
AnnaBridge	171:3a7713b1edbc	1423	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	1424	* whether or not a timer instance is able to generate a commutation event.
AnnaBridge	171:3a7713b1edbc	1425	* @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
AnnaBridge	171:3a7713b1edbc	1426	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1427	* @retval None
AnnaBridge	171:3a7713b1edbc	1428	*/
AnnaBridge	171:3a7713b1edbc	1429	__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1430	{
AnnaBridge	171:3a7713b1edbc	1431	CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
AnnaBridge	171:3a7713b1edbc	1432	}
AnnaBridge	171:3a7713b1edbc	1433
AnnaBridge	171:3a7713b1edbc	1434	/**
AnnaBridge	171:3a7713b1edbc	1435	* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
AnnaBridge	171:3a7713b1edbc	1436	* @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	1437	* whether or not a timer instance is able to generate a commutation event.
AnnaBridge	171:3a7713b1edbc	1438	* @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
AnnaBridge	171:3a7713b1edbc	1439	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1440	* @param CCUpdateSource This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1441	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
AnnaBridge	171:3a7713b1edbc	1442	* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
AnnaBridge	171:3a7713b1edbc	1443	* @retval None
AnnaBridge	171:3a7713b1edbc	1444	*/
AnnaBridge	171:3a7713b1edbc	1445	__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
AnnaBridge	171:3a7713b1edbc	1446	{
AnnaBridge	171:3a7713b1edbc	1447	MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
AnnaBridge	171:3a7713b1edbc	1448	}
AnnaBridge	171:3a7713b1edbc	1449
AnnaBridge	171:3a7713b1edbc	1450	/**
AnnaBridge	171:3a7713b1edbc	1451	* @brief Set the trigger of the capture/compare DMA request.
AnnaBridge	171:3a7713b1edbc	1452	* @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
AnnaBridge	171:3a7713b1edbc	1453	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1454	* @param DMAReqTrigger This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1455	* @arg @ref LL_TIM_CCDMAREQUEST_CC
AnnaBridge	171:3a7713b1edbc	1456	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
AnnaBridge	171:3a7713b1edbc	1457	* @retval None
AnnaBridge	171:3a7713b1edbc	1458	*/
AnnaBridge	171:3a7713b1edbc	1459	__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
AnnaBridge	171:3a7713b1edbc	1460	{
AnnaBridge	171:3a7713b1edbc	1461	MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
AnnaBridge	171:3a7713b1edbc	1462	}
AnnaBridge	171:3a7713b1edbc	1463
AnnaBridge	171:3a7713b1edbc	1464	/**
AnnaBridge	171:3a7713b1edbc	1465	* @brief Get actual trigger of the capture/compare DMA request.
AnnaBridge	171:3a7713b1edbc	1466	* @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
AnnaBridge	171:3a7713b1edbc	1467	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1468	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1469	* @arg @ref LL_TIM_CCDMAREQUEST_CC
AnnaBridge	171:3a7713b1edbc	1470	* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
AnnaBridge	171:3a7713b1edbc	1471	*/
AnnaBridge	171:3a7713b1edbc	1472	__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	1473	{
AnnaBridge	171:3a7713b1edbc	1474	return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
AnnaBridge	171:3a7713b1edbc	1475	}
AnnaBridge	171:3a7713b1edbc	1476
AnnaBridge	171:3a7713b1edbc	1477	/**
AnnaBridge	171:3a7713b1edbc	1478	* @brief Set the lock level to freeze the
AnnaBridge	171:3a7713b1edbc	1479	* configuration of several capture/compare parameters.
AnnaBridge	171:3a7713b1edbc	1480	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	1481	* the lock mechanism is supported by a timer instance.
AnnaBridge	171:3a7713b1edbc	1482	* @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
AnnaBridge	171:3a7713b1edbc	1483	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1484	* @param LockLevel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1485	* @arg @ref LL_TIM_LOCKLEVEL_OFF
AnnaBridge	171:3a7713b1edbc	1486	* @arg @ref LL_TIM_LOCKLEVEL_1
AnnaBridge	171:3a7713b1edbc	1487	* @arg @ref LL_TIM_LOCKLEVEL_2
AnnaBridge	171:3a7713b1edbc	1488	* @arg @ref LL_TIM_LOCKLEVEL_3
AnnaBridge	171:3a7713b1edbc	1489	* @retval None
AnnaBridge	171:3a7713b1edbc	1490	*/
AnnaBridge	171:3a7713b1edbc	1491	__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
AnnaBridge	171:3a7713b1edbc	1492	{
AnnaBridge	171:3a7713b1edbc	1493	MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
AnnaBridge	171:3a7713b1edbc	1494	}
AnnaBridge	171:3a7713b1edbc	1495
AnnaBridge	171:3a7713b1edbc	1496	/**
AnnaBridge	171:3a7713b1edbc	1497	* @brief Enable capture/compare channels.
AnnaBridge	171:3a7713b1edbc	1498	* @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
AnnaBridge	171:3a7713b1edbc	1499	* CCER CC1NE LL_TIM_CC_EnableChannel\n
AnnaBridge	171:3a7713b1edbc	1500	* CCER CC2E LL_TIM_CC_EnableChannel\n
AnnaBridge	171:3a7713b1edbc	1501	* CCER CC2NE LL_TIM_CC_EnableChannel\n
AnnaBridge	171:3a7713b1edbc	1502	* CCER CC3E LL_TIM_CC_EnableChannel\n
AnnaBridge	171:3a7713b1edbc	1503	* CCER CC3NE LL_TIM_CC_EnableChannel\n
AnnaBridge	171:3a7713b1edbc	1504	* CCER CC4E LL_TIM_CC_EnableChannel
AnnaBridge	171:3a7713b1edbc	1505	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1506	* @param Channels This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	1507	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1508	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	171:3a7713b1edbc	1509	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1510	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	171:3a7713b1edbc	1511	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1512	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	171:3a7713b1edbc	1513	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1514	* @retval None
AnnaBridge	171:3a7713b1edbc	1515	*/
AnnaBridge	171:3a7713b1edbc	1516	__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
AnnaBridge	171:3a7713b1edbc	1517	{
AnnaBridge	171:3a7713b1edbc	1518	SET_BIT(TIMx->CCER, Channels);
AnnaBridge	171:3a7713b1edbc	1519	}
AnnaBridge	171:3a7713b1edbc	1520
AnnaBridge	171:3a7713b1edbc	1521	/**
AnnaBridge	171:3a7713b1edbc	1522	* @brief Disable capture/compare channels.
AnnaBridge	171:3a7713b1edbc	1523	* @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
AnnaBridge	171:3a7713b1edbc	1524	* CCER CC1NE LL_TIM_CC_DisableChannel\n
AnnaBridge	171:3a7713b1edbc	1525	* CCER CC2E LL_TIM_CC_DisableChannel\n
AnnaBridge	171:3a7713b1edbc	1526	* CCER CC2NE LL_TIM_CC_DisableChannel\n
AnnaBridge	171:3a7713b1edbc	1527	* CCER CC3E LL_TIM_CC_DisableChannel\n
AnnaBridge	171:3a7713b1edbc	1528	* CCER CC3NE LL_TIM_CC_DisableChannel\n
AnnaBridge	171:3a7713b1edbc	1529	* CCER CC4E LL_TIM_CC_DisableChannel
AnnaBridge	171:3a7713b1edbc	1530	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1531	* @param Channels This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	1532	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1533	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	171:3a7713b1edbc	1534	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1535	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	171:3a7713b1edbc	1536	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1537	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	171:3a7713b1edbc	1538	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1539	* @retval None
AnnaBridge	171:3a7713b1edbc	1540	*/
AnnaBridge	171:3a7713b1edbc	1541	__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
AnnaBridge	171:3a7713b1edbc	1542	{
AnnaBridge	171:3a7713b1edbc	1543	CLEAR_BIT(TIMx->CCER, Channels);
AnnaBridge	171:3a7713b1edbc	1544	}
AnnaBridge	171:3a7713b1edbc	1545
AnnaBridge	171:3a7713b1edbc	1546	/**
AnnaBridge	171:3a7713b1edbc	1547	* @brief Indicate whether channel(s) is(are) enabled.
AnnaBridge	171:3a7713b1edbc	1548	* @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	171:3a7713b1edbc	1549	* CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	171:3a7713b1edbc	1550	* CCER CC2E LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	171:3a7713b1edbc	1551	* CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	171:3a7713b1edbc	1552	* CCER CC3E LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	171:3a7713b1edbc	1553	* CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
AnnaBridge	171:3a7713b1edbc	1554	* CCER CC4E LL_TIM_CC_IsEnabledChannel
AnnaBridge	171:3a7713b1edbc	1555	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1556	* @param Channels This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	1557	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1558	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	171:3a7713b1edbc	1559	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1560	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	171:3a7713b1edbc	1561	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1562	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	171:3a7713b1edbc	1563	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1564	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1565	*/
AnnaBridge	171:3a7713b1edbc	1566	__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
AnnaBridge	171:3a7713b1edbc	1567	{
AnnaBridge	171:3a7713b1edbc	1568	return (READ_BIT(TIMx->CCER, Channels) == (Channels));
AnnaBridge	171:3a7713b1edbc	1569	}
AnnaBridge	171:3a7713b1edbc	1570
AnnaBridge	171:3a7713b1edbc	1571	/**
AnnaBridge	171:3a7713b1edbc	1572	* @}
AnnaBridge	171:3a7713b1edbc	1573	*/
AnnaBridge	171:3a7713b1edbc	1574
AnnaBridge	171:3a7713b1edbc	1575	/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
AnnaBridge	171:3a7713b1edbc	1576	* @{
AnnaBridge	171:3a7713b1edbc	1577	*/
AnnaBridge	171:3a7713b1edbc	1578	/**
AnnaBridge	171:3a7713b1edbc	1579	* @brief Configure an output channel.
AnnaBridge	171:3a7713b1edbc	1580	* @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
AnnaBridge	171:3a7713b1edbc	1581	* CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
AnnaBridge	171:3a7713b1edbc	1582	* CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
AnnaBridge	171:3a7713b1edbc	1583	* CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
AnnaBridge	171:3a7713b1edbc	1584	* CCER CC1P LL_TIM_OC_ConfigOutput\n
AnnaBridge	171:3a7713b1edbc	1585	* CCER CC2P LL_TIM_OC_ConfigOutput\n
AnnaBridge	171:3a7713b1edbc	1586	* CCER CC3P LL_TIM_OC_ConfigOutput\n
AnnaBridge	171:3a7713b1edbc	1587	* CCER CC4P LL_TIM_OC_ConfigOutput\n
AnnaBridge	171:3a7713b1edbc	1588	* CR2 OIS1 LL_TIM_OC_ConfigOutput\n
AnnaBridge	171:3a7713b1edbc	1589	* CR2 OIS2 LL_TIM_OC_ConfigOutput\n
AnnaBridge	171:3a7713b1edbc	1590	* CR2 OIS3 LL_TIM_OC_ConfigOutput\n
AnnaBridge	171:3a7713b1edbc	1591	* CR2 OIS4 LL_TIM_OC_ConfigOutput
AnnaBridge	171:3a7713b1edbc	1592	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1593	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1594	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1595	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1596	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1597	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1598	* @param Configuration This parameter must be a combination of all the following values:
AnnaBridge	171:3a7713b1edbc	1599	* @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
AnnaBridge	171:3a7713b1edbc	1600	* @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
AnnaBridge	171:3a7713b1edbc	1601	* @retval None
AnnaBridge	171:3a7713b1edbc	1602	*/
AnnaBridge	171:3a7713b1edbc	1603	__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
AnnaBridge	171:3a7713b1edbc	1604	{
AnnaBridge	171:3a7713b1edbc	1605	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1606	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1607	CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1608	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
AnnaBridge	171:3a7713b1edbc	1609	(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	171:3a7713b1edbc	1610	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
AnnaBridge	171:3a7713b1edbc	1611	(Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
AnnaBridge	171:3a7713b1edbc	1612	}
AnnaBridge	171:3a7713b1edbc	1613
AnnaBridge	171:3a7713b1edbc	1614	/**
AnnaBridge	171:3a7713b1edbc	1615	* @brief Define the behavior of the output reference signal OCxREF from which
AnnaBridge	171:3a7713b1edbc	1616	* OCx and OCxN (when relevant) are derived.
AnnaBridge	171:3a7713b1edbc	1617	* @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
AnnaBridge	171:3a7713b1edbc	1618	* CCMR1 OC2M LL_TIM_OC_SetMode\n
AnnaBridge	171:3a7713b1edbc	1619	* CCMR2 OC3M LL_TIM_OC_SetMode\n
AnnaBridge	171:3a7713b1edbc	1620	* CCMR2 OC4M LL_TIM_OC_SetMode
AnnaBridge	171:3a7713b1edbc	1621	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1622	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1623	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1624	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1625	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1626	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1627	* @param Mode This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1628	* @arg @ref LL_TIM_OCMODE_FROZEN
AnnaBridge	171:3a7713b1edbc	1629	* @arg @ref LL_TIM_OCMODE_ACTIVE
AnnaBridge	171:3a7713b1edbc	1630	* @arg @ref LL_TIM_OCMODE_INACTIVE
AnnaBridge	171:3a7713b1edbc	1631	* @arg @ref LL_TIM_OCMODE_TOGGLE
AnnaBridge	171:3a7713b1edbc	1632	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
AnnaBridge	171:3a7713b1edbc	1633	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
AnnaBridge	171:3a7713b1edbc	1634	* @arg @ref LL_TIM_OCMODE_PWM1
AnnaBridge	171:3a7713b1edbc	1635	* @arg @ref LL_TIM_OCMODE_PWM2
AnnaBridge	171:3a7713b1edbc	1636	* @retval None
AnnaBridge	171:3a7713b1edbc	1637	*/
AnnaBridge	171:3a7713b1edbc	1638	__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
AnnaBridge	171:3a7713b1edbc	1639	{
AnnaBridge	171:3a7713b1edbc	1640	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1641	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1642	MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
AnnaBridge	171:3a7713b1edbc	1643	}
AnnaBridge	171:3a7713b1edbc	1644
AnnaBridge	171:3a7713b1edbc	1645	/**
AnnaBridge	171:3a7713b1edbc	1646	* @brief Get the output compare mode of an output channel.
AnnaBridge	171:3a7713b1edbc	1647	* @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
AnnaBridge	171:3a7713b1edbc	1648	* CCMR1 OC2M LL_TIM_OC_GetMode\n
AnnaBridge	171:3a7713b1edbc	1649	* CCMR2 OC3M LL_TIM_OC_GetMode\n
AnnaBridge	171:3a7713b1edbc	1650	* CCMR2 OC4M LL_TIM_OC_GetMode
AnnaBridge	171:3a7713b1edbc	1651	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1652	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1653	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1654	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1655	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1656	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1657	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1658	* @arg @ref LL_TIM_OCMODE_FROZEN
AnnaBridge	171:3a7713b1edbc	1659	* @arg @ref LL_TIM_OCMODE_ACTIVE
AnnaBridge	171:3a7713b1edbc	1660	* @arg @ref LL_TIM_OCMODE_INACTIVE
AnnaBridge	171:3a7713b1edbc	1661	* @arg @ref LL_TIM_OCMODE_TOGGLE
AnnaBridge	171:3a7713b1edbc	1662	* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
AnnaBridge	171:3a7713b1edbc	1663	* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
AnnaBridge	171:3a7713b1edbc	1664	* @arg @ref LL_TIM_OCMODE_PWM1
AnnaBridge	171:3a7713b1edbc	1665	* @arg @ref LL_TIM_OCMODE_PWM2
AnnaBridge	171:3a7713b1edbc	1666	*/
AnnaBridge	171:3a7713b1edbc	1667	__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1668	{
AnnaBridge	171:3a7713b1edbc	1669	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1670	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1671	return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M \| TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
AnnaBridge	171:3a7713b1edbc	1672	}
AnnaBridge	171:3a7713b1edbc	1673
AnnaBridge	171:3a7713b1edbc	1674	/**
AnnaBridge	171:3a7713b1edbc	1675	* @brief Set the polarity of an output channel.
AnnaBridge	171:3a7713b1edbc	1676	* @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
AnnaBridge	171:3a7713b1edbc	1677	* CCER CC1NP LL_TIM_OC_SetPolarity\n
AnnaBridge	171:3a7713b1edbc	1678	* CCER CC2P LL_TIM_OC_SetPolarity\n
AnnaBridge	171:3a7713b1edbc	1679	* CCER CC2NP LL_TIM_OC_SetPolarity\n
AnnaBridge	171:3a7713b1edbc	1680	* CCER CC3P LL_TIM_OC_SetPolarity\n
AnnaBridge	171:3a7713b1edbc	1681	* CCER CC3NP LL_TIM_OC_SetPolarity\n
AnnaBridge	171:3a7713b1edbc	1682	* CCER CC4P LL_TIM_OC_SetPolarity
AnnaBridge	171:3a7713b1edbc	1683	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1684	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1685	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1686	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	171:3a7713b1edbc	1687	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1688	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	171:3a7713b1edbc	1689	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1690	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	171:3a7713b1edbc	1691	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1692	* @param Polarity This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1693	* @arg @ref LL_TIM_OCPOLARITY_HIGH
AnnaBridge	171:3a7713b1edbc	1694	* @arg @ref LL_TIM_OCPOLARITY_LOW
AnnaBridge	171:3a7713b1edbc	1695	* @retval None
AnnaBridge	171:3a7713b1edbc	1696	*/
AnnaBridge	171:3a7713b1edbc	1697	__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
AnnaBridge	171:3a7713b1edbc	1698	{
AnnaBridge	171:3a7713b1edbc	1699	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1700	MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	171:3a7713b1edbc	1701	}
AnnaBridge	171:3a7713b1edbc	1702
AnnaBridge	171:3a7713b1edbc	1703	/**
AnnaBridge	171:3a7713b1edbc	1704	* @brief Get the polarity of an output channel.
AnnaBridge	171:3a7713b1edbc	1705	* @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
AnnaBridge	171:3a7713b1edbc	1706	* CCER CC1NP LL_TIM_OC_GetPolarity\n
AnnaBridge	171:3a7713b1edbc	1707	* CCER CC2P LL_TIM_OC_GetPolarity\n
AnnaBridge	171:3a7713b1edbc	1708	* CCER CC2NP LL_TIM_OC_GetPolarity\n
AnnaBridge	171:3a7713b1edbc	1709	* CCER CC3P LL_TIM_OC_GetPolarity\n
AnnaBridge	171:3a7713b1edbc	1710	* CCER CC3NP LL_TIM_OC_GetPolarity\n
AnnaBridge	171:3a7713b1edbc	1711	* CCER CC4P LL_TIM_OC_GetPolarity
AnnaBridge	171:3a7713b1edbc	1712	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1713	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1714	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1715	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	171:3a7713b1edbc	1716	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1717	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	171:3a7713b1edbc	1718	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1719	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	171:3a7713b1edbc	1720	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1721	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1722	* @arg @ref LL_TIM_OCPOLARITY_HIGH
AnnaBridge	171:3a7713b1edbc	1723	* @arg @ref LL_TIM_OCPOLARITY_LOW
AnnaBridge	171:3a7713b1edbc	1724	*/
AnnaBridge	171:3a7713b1edbc	1725	__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1726	{
AnnaBridge	171:3a7713b1edbc	1727	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1728	return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	171:3a7713b1edbc	1729	}
AnnaBridge	171:3a7713b1edbc	1730
AnnaBridge	171:3a7713b1edbc	1731	/**
AnnaBridge	171:3a7713b1edbc	1732	* @brief Set the IDLE state of an output channel
AnnaBridge	171:3a7713b1edbc	1733	* @note This function is significant only for the timer instances
AnnaBridge	171:3a7713b1edbc	1734	* supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
AnnaBridge	171:3a7713b1edbc	1735	* can be used to check whether or not a timer instance provides
AnnaBridge	171:3a7713b1edbc	1736	* a break input.
AnnaBridge	171:3a7713b1edbc	1737	* @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
AnnaBridge	171:3a7713b1edbc	1738	* CR2 OIS1N LL_TIM_OC_SetIdleState\n
AnnaBridge	171:3a7713b1edbc	1739	* CR2 OIS2 LL_TIM_OC_SetIdleState\n
AnnaBridge	171:3a7713b1edbc	1740	* CR2 OIS2N LL_TIM_OC_SetIdleState\n
AnnaBridge	171:3a7713b1edbc	1741	* CR2 OIS3 LL_TIM_OC_SetIdleState\n
AnnaBridge	171:3a7713b1edbc	1742	* CR2 OIS3N LL_TIM_OC_SetIdleState\n
AnnaBridge	171:3a7713b1edbc	1743	* CR2 OIS4 LL_TIM_OC_SetIdleState
AnnaBridge	171:3a7713b1edbc	1744	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1745	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1746	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1747	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	171:3a7713b1edbc	1748	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1749	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	171:3a7713b1edbc	1750	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1751	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	171:3a7713b1edbc	1752	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1753	* @param IdleState This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1754	* @arg @ref LL_TIM_OCIDLESTATE_LOW
AnnaBridge	171:3a7713b1edbc	1755	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
AnnaBridge	171:3a7713b1edbc	1756	* @retval None
AnnaBridge	171:3a7713b1edbc	1757	*/
AnnaBridge	171:3a7713b1edbc	1758	__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
AnnaBridge	171:3a7713b1edbc	1759	{
AnnaBridge	171:3a7713b1edbc	1760	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1761	MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
AnnaBridge	171:3a7713b1edbc	1762	}
AnnaBridge	171:3a7713b1edbc	1763
AnnaBridge	171:3a7713b1edbc	1764	/**
AnnaBridge	171:3a7713b1edbc	1765	* @brief Get the IDLE state of an output channel
AnnaBridge	171:3a7713b1edbc	1766	* @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
AnnaBridge	171:3a7713b1edbc	1767	* CR2 OIS1N LL_TIM_OC_GetIdleState\n
AnnaBridge	171:3a7713b1edbc	1768	* CR2 OIS2 LL_TIM_OC_GetIdleState\n
AnnaBridge	171:3a7713b1edbc	1769	* CR2 OIS2N LL_TIM_OC_GetIdleState\n
AnnaBridge	171:3a7713b1edbc	1770	* CR2 OIS3 LL_TIM_OC_GetIdleState\n
AnnaBridge	171:3a7713b1edbc	1771	* CR2 OIS3N LL_TIM_OC_GetIdleState\n
AnnaBridge	171:3a7713b1edbc	1772	* CR2 OIS4 LL_TIM_OC_GetIdleState
AnnaBridge	171:3a7713b1edbc	1773	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1774	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1775	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1776	* @arg @ref LL_TIM_CHANNEL_CH1N
AnnaBridge	171:3a7713b1edbc	1777	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1778	* @arg @ref LL_TIM_CHANNEL_CH2N
AnnaBridge	171:3a7713b1edbc	1779	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1780	* @arg @ref LL_TIM_CHANNEL_CH3N
AnnaBridge	171:3a7713b1edbc	1781	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1782	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1783	* @arg @ref LL_TIM_OCIDLESTATE_LOW
AnnaBridge	171:3a7713b1edbc	1784	* @arg @ref LL_TIM_OCIDLESTATE_HIGH
AnnaBridge	171:3a7713b1edbc	1785	*/
AnnaBridge	171:3a7713b1edbc	1786	__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1787	{
AnnaBridge	171:3a7713b1edbc	1788	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1789	return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
AnnaBridge	171:3a7713b1edbc	1790	}
AnnaBridge	171:3a7713b1edbc	1791
AnnaBridge	171:3a7713b1edbc	1792	/**
AnnaBridge	171:3a7713b1edbc	1793	* @brief Enable fast mode for the output channel.
AnnaBridge	171:3a7713b1edbc	1794	* @note Acts only if the channel is configured in PWM1 or PWM2 mode.
AnnaBridge	171:3a7713b1edbc	1795	* @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
AnnaBridge	171:3a7713b1edbc	1796	* CCMR1 OC2FE LL_TIM_OC_EnableFast\n
AnnaBridge	171:3a7713b1edbc	1797	* CCMR2 OC3FE LL_TIM_OC_EnableFast\n
AnnaBridge	171:3a7713b1edbc	1798	* CCMR2 OC4FE LL_TIM_OC_EnableFast
AnnaBridge	171:3a7713b1edbc	1799	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1800	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1801	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1802	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1803	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1804	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1805	* @retval None
AnnaBridge	171:3a7713b1edbc	1806	*/
AnnaBridge	171:3a7713b1edbc	1807	__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1808	{
AnnaBridge	171:3a7713b1edbc	1809	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1810	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1811	SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1812
AnnaBridge	171:3a7713b1edbc	1813	}
AnnaBridge	171:3a7713b1edbc	1814
AnnaBridge	171:3a7713b1edbc	1815	/**
AnnaBridge	171:3a7713b1edbc	1816	* @brief Disable fast mode for the output channel.
AnnaBridge	171:3a7713b1edbc	1817	* @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
AnnaBridge	171:3a7713b1edbc	1818	* CCMR1 OC2FE LL_TIM_OC_DisableFast\n
AnnaBridge	171:3a7713b1edbc	1819	* CCMR2 OC3FE LL_TIM_OC_DisableFast\n
AnnaBridge	171:3a7713b1edbc	1820	* CCMR2 OC4FE LL_TIM_OC_DisableFast
AnnaBridge	171:3a7713b1edbc	1821	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1822	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1823	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1824	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1825	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1826	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1827	* @retval None
AnnaBridge	171:3a7713b1edbc	1828	*/
AnnaBridge	171:3a7713b1edbc	1829	__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1830	{
AnnaBridge	171:3a7713b1edbc	1831	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1832	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1833	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1834
AnnaBridge	171:3a7713b1edbc	1835	}
AnnaBridge	171:3a7713b1edbc	1836
AnnaBridge	171:3a7713b1edbc	1837	/**
AnnaBridge	171:3a7713b1edbc	1838	* @brief Indicates whether fast mode is enabled for the output channel.
AnnaBridge	171:3a7713b1edbc	1839	* @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	171:3a7713b1edbc	1840	* CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	171:3a7713b1edbc	1841	* CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	171:3a7713b1edbc	1842	* CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
AnnaBridge	171:3a7713b1edbc	1843	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1844	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1845	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1846	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1847	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1848	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1849	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1850	*/
AnnaBridge	171:3a7713b1edbc	1851	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1852	{
AnnaBridge	171:3a7713b1edbc	1853	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1854	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1855	register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
AnnaBridge	171:3a7713b1edbc	1856	return (READ_BIT(*pReg, bitfield) == bitfield);
AnnaBridge	171:3a7713b1edbc	1857	}
AnnaBridge	171:3a7713b1edbc	1858
AnnaBridge	171:3a7713b1edbc	1859	/**
AnnaBridge	171:3a7713b1edbc	1860	* @brief Enable compare register (TIMx_CCRx) preload for the output channel.
AnnaBridge	171:3a7713b1edbc	1861	* @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
AnnaBridge	171:3a7713b1edbc	1862	* CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
AnnaBridge	171:3a7713b1edbc	1863	* CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
AnnaBridge	171:3a7713b1edbc	1864	* CCMR2 OC4PE LL_TIM_OC_EnablePreload
AnnaBridge	171:3a7713b1edbc	1865	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1866	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1867	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1868	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1869	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1870	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1871	* @retval None
AnnaBridge	171:3a7713b1edbc	1872	*/
AnnaBridge	171:3a7713b1edbc	1873	__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1874	{
AnnaBridge	171:3a7713b1edbc	1875	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1876	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1877	SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1878	}
AnnaBridge	171:3a7713b1edbc	1879
AnnaBridge	171:3a7713b1edbc	1880	/**
AnnaBridge	171:3a7713b1edbc	1881	* @brief Disable compare register (TIMx_CCRx) preload for the output channel.
AnnaBridge	171:3a7713b1edbc	1882	* @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
AnnaBridge	171:3a7713b1edbc	1883	* CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
AnnaBridge	171:3a7713b1edbc	1884	* CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
AnnaBridge	171:3a7713b1edbc	1885	* CCMR2 OC4PE LL_TIM_OC_DisablePreload
AnnaBridge	171:3a7713b1edbc	1886	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1887	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1888	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1889	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1890	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1891	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1892	* @retval None
AnnaBridge	171:3a7713b1edbc	1893	*/
AnnaBridge	171:3a7713b1edbc	1894	__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1895	{
AnnaBridge	171:3a7713b1edbc	1896	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1897	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1898	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1899	}
AnnaBridge	171:3a7713b1edbc	1900
AnnaBridge	171:3a7713b1edbc	1901	/**
AnnaBridge	171:3a7713b1edbc	1902	* @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
AnnaBridge	171:3a7713b1edbc	1903	* @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	171:3a7713b1edbc	1904	* CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	171:3a7713b1edbc	1905	* CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	171:3a7713b1edbc	1906	* CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
AnnaBridge	171:3a7713b1edbc	1907	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1908	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1909	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1910	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1911	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1912	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1913	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1914	*/
AnnaBridge	171:3a7713b1edbc	1915	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1916	{
AnnaBridge	171:3a7713b1edbc	1917	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1918	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1919	register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
AnnaBridge	171:3a7713b1edbc	1920	return (READ_BIT(*pReg, bitfield) == bitfield);
AnnaBridge	171:3a7713b1edbc	1921	}
AnnaBridge	171:3a7713b1edbc	1922
AnnaBridge	171:3a7713b1edbc	1923	/**
AnnaBridge	171:3a7713b1edbc	1924	* @brief Enable clearing the output channel on an external event.
AnnaBridge	171:3a7713b1edbc	1925	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
AnnaBridge	171:3a7713b1edbc	1926	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
AnnaBridge	171:3a7713b1edbc	1927	* or not a timer instance can clear the OCxREF signal on an external event.
AnnaBridge	171:3a7713b1edbc	1928	* @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
AnnaBridge	171:3a7713b1edbc	1929	* CCMR1 OC2CE LL_TIM_OC_EnableClear\n
AnnaBridge	171:3a7713b1edbc	1930	* CCMR2 OC3CE LL_TIM_OC_EnableClear\n
AnnaBridge	171:3a7713b1edbc	1931	* CCMR2 OC4CE LL_TIM_OC_EnableClear
AnnaBridge	171:3a7713b1edbc	1932	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1933	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1934	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1935	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1936	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1937	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1938	* @retval None
AnnaBridge	171:3a7713b1edbc	1939	*/
AnnaBridge	171:3a7713b1edbc	1940	__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1941	{
AnnaBridge	171:3a7713b1edbc	1942	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1943	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1944	SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1945	}
AnnaBridge	171:3a7713b1edbc	1946
AnnaBridge	171:3a7713b1edbc	1947	/**
AnnaBridge	171:3a7713b1edbc	1948	* @brief Disable clearing the output channel on an external event.
AnnaBridge	171:3a7713b1edbc	1949	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
AnnaBridge	171:3a7713b1edbc	1950	* or not a timer instance can clear the OCxREF signal on an external event.
AnnaBridge	171:3a7713b1edbc	1951	* @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
AnnaBridge	171:3a7713b1edbc	1952	* CCMR1 OC2CE LL_TIM_OC_DisableClear\n
AnnaBridge	171:3a7713b1edbc	1953	* CCMR2 OC3CE LL_TIM_OC_DisableClear\n
AnnaBridge	171:3a7713b1edbc	1954	* CCMR2 OC4CE LL_TIM_OC_DisableClear
AnnaBridge	171:3a7713b1edbc	1955	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1956	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1957	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1958	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1959	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1960	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1961	* @retval None
AnnaBridge	171:3a7713b1edbc	1962	*/
AnnaBridge	171:3a7713b1edbc	1963	__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1964	{
AnnaBridge	171:3a7713b1edbc	1965	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1966	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1967	CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1968	}
AnnaBridge	171:3a7713b1edbc	1969
AnnaBridge	171:3a7713b1edbc	1970	/**
AnnaBridge	171:3a7713b1edbc	1971	* @brief Indicates clearing the output channel on an external event is enabled for the output channel.
AnnaBridge	171:3a7713b1edbc	1972	* @note This function enables clearing the output channel on an external event.
AnnaBridge	171:3a7713b1edbc	1973	* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
AnnaBridge	171:3a7713b1edbc	1974	* @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
AnnaBridge	171:3a7713b1edbc	1975	* or not a timer instance can clear the OCxREF signal on an external event.
AnnaBridge	171:3a7713b1edbc	1976	* @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	171:3a7713b1edbc	1977	* CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	171:3a7713b1edbc	1978	* CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	171:3a7713b1edbc	1979	* CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
AnnaBridge	171:3a7713b1edbc	1980	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	1981	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1982	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	1983	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	1984	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	1985	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	1986	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1987	*/
AnnaBridge	171:3a7713b1edbc	1988	__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	1989	{
AnnaBridge	171:3a7713b1edbc	1990	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	1991	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	1992	register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
AnnaBridge	171:3a7713b1edbc	1993	return (READ_BIT(*pReg, bitfield) == bitfield);
AnnaBridge	171:3a7713b1edbc	1994	}
AnnaBridge	171:3a7713b1edbc	1995
AnnaBridge	171:3a7713b1edbc	1996	/**
AnnaBridge	171:3a7713b1edbc	1997	* @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
AnnaBridge	171:3a7713b1edbc	1998	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	1999	* dead-time insertion feature is supported by a timer instance.
AnnaBridge	171:3a7713b1edbc	2000	* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
AnnaBridge	171:3a7713b1edbc	2001	* @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
AnnaBridge	171:3a7713b1edbc	2002	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2003	* @param DeadTime between Min_Data=0 and Max_Data=255
AnnaBridge	171:3a7713b1edbc	2004	* @retval None
AnnaBridge	171:3a7713b1edbc	2005	*/
AnnaBridge	171:3a7713b1edbc	2006	__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
AnnaBridge	171:3a7713b1edbc	2007	{
AnnaBridge	171:3a7713b1edbc	2008	MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
AnnaBridge	171:3a7713b1edbc	2009	}
AnnaBridge	171:3a7713b1edbc	2010
AnnaBridge	171:3a7713b1edbc	2011	/**
AnnaBridge	171:3a7713b1edbc	2012	* @brief Set compare value for output channel 1 (TIMx_CCR1).
AnnaBridge	171:3a7713b1edbc	2013	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	171:3a7713b1edbc	2014	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	2015	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	171:3a7713b1edbc	2016	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2017	* output channel 1 is supported by a timer instance.
AnnaBridge	171:3a7713b1edbc	2018	* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
AnnaBridge	171:3a7713b1edbc	2019	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2020	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	171:3a7713b1edbc	2021	* @retval None
AnnaBridge	171:3a7713b1edbc	2022	*/
AnnaBridge	171:3a7713b1edbc	2023	__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	171:3a7713b1edbc	2024	{
AnnaBridge	171:3a7713b1edbc	2025	WRITE_REG(TIMx->CCR1, CompareValue);
AnnaBridge	171:3a7713b1edbc	2026	}
AnnaBridge	171:3a7713b1edbc	2027
AnnaBridge	171:3a7713b1edbc	2028	/**
AnnaBridge	171:3a7713b1edbc	2029	* @brief Set compare value for output channel 2 (TIMx_CCR2).
AnnaBridge	171:3a7713b1edbc	2030	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	171:3a7713b1edbc	2031	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	2032	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	171:3a7713b1edbc	2033	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2034	* output channel 2 is supported by a timer instance.
AnnaBridge	171:3a7713b1edbc	2035	* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
AnnaBridge	171:3a7713b1edbc	2036	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2037	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	171:3a7713b1edbc	2038	* @retval None
AnnaBridge	171:3a7713b1edbc	2039	*/
AnnaBridge	171:3a7713b1edbc	2040	__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	171:3a7713b1edbc	2041	{
AnnaBridge	171:3a7713b1edbc	2042	WRITE_REG(TIMx->CCR2, CompareValue);
AnnaBridge	171:3a7713b1edbc	2043	}
AnnaBridge	171:3a7713b1edbc	2044
AnnaBridge	171:3a7713b1edbc	2045	/**
AnnaBridge	171:3a7713b1edbc	2046	* @brief Set compare value for output channel 3 (TIMx_CCR3).
AnnaBridge	171:3a7713b1edbc	2047	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	171:3a7713b1edbc	2048	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	2049	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	171:3a7713b1edbc	2050	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2051	* output channel is supported by a timer instance.
AnnaBridge	171:3a7713b1edbc	2052	* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
AnnaBridge	171:3a7713b1edbc	2053	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2054	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	171:3a7713b1edbc	2055	* @retval None
AnnaBridge	171:3a7713b1edbc	2056	*/
AnnaBridge	171:3a7713b1edbc	2057	__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	171:3a7713b1edbc	2058	{
AnnaBridge	171:3a7713b1edbc	2059	WRITE_REG(TIMx->CCR3, CompareValue);
AnnaBridge	171:3a7713b1edbc	2060	}
AnnaBridge	171:3a7713b1edbc	2061
AnnaBridge	171:3a7713b1edbc	2062	/**
AnnaBridge	171:3a7713b1edbc	2063	* @brief Set compare value for output channel 4 (TIMx_CCR4).
AnnaBridge	171:3a7713b1edbc	2064	* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	171:3a7713b1edbc	2065	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	2066	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	171:3a7713b1edbc	2067	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2068	* output channel 4 is supported by a timer instance.
AnnaBridge	171:3a7713b1edbc	2069	* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
AnnaBridge	171:3a7713b1edbc	2070	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2071	* @param CompareValue between Min_Data=0 and Max_Data=65535
AnnaBridge	171:3a7713b1edbc	2072	* @retval None
AnnaBridge	171:3a7713b1edbc	2073	*/
AnnaBridge	171:3a7713b1edbc	2074	__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
AnnaBridge	171:3a7713b1edbc	2075	{
AnnaBridge	171:3a7713b1edbc	2076	WRITE_REG(TIMx->CCR4, CompareValue);
AnnaBridge	171:3a7713b1edbc	2077	}
AnnaBridge	171:3a7713b1edbc	2078
AnnaBridge	171:3a7713b1edbc	2079	/**
AnnaBridge	171:3a7713b1edbc	2080	* @brief Get compare value (TIMx_CCR1) set for output channel 1.
AnnaBridge	171:3a7713b1edbc	2081	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	171:3a7713b1edbc	2082	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	2083	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	171:3a7713b1edbc	2084	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2085	* output channel 1 is supported by a timer instance.
AnnaBridge	171:3a7713b1edbc	2086	* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
AnnaBridge	171:3a7713b1edbc	2087	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2088	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	171:3a7713b1edbc	2089	*/
AnnaBridge	171:3a7713b1edbc	2090	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2091	{
AnnaBridge	171:3a7713b1edbc	2092	return (uint32_t)(READ_REG(TIMx->CCR1));
AnnaBridge	171:3a7713b1edbc	2093	}
AnnaBridge	171:3a7713b1edbc	2094
AnnaBridge	171:3a7713b1edbc	2095	/**
AnnaBridge	171:3a7713b1edbc	2096	* @brief Get compare value (TIMx_CCR2) set for output channel 2.
AnnaBridge	171:3a7713b1edbc	2097	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	171:3a7713b1edbc	2098	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	2099	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	171:3a7713b1edbc	2100	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2101	* output channel 2 is supported by a timer instance.
AnnaBridge	171:3a7713b1edbc	2102	* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
AnnaBridge	171:3a7713b1edbc	2103	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2104	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	171:3a7713b1edbc	2105	*/
AnnaBridge	171:3a7713b1edbc	2106	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2107	{
AnnaBridge	171:3a7713b1edbc	2108	return (uint32_t)(READ_REG(TIMx->CCR2));
AnnaBridge	171:3a7713b1edbc	2109	}
AnnaBridge	171:3a7713b1edbc	2110
AnnaBridge	171:3a7713b1edbc	2111	/**
AnnaBridge	171:3a7713b1edbc	2112	* @brief Get compare value (TIMx_CCR3) set for output channel 3.
AnnaBridge	171:3a7713b1edbc	2113	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	171:3a7713b1edbc	2114	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	2115	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	171:3a7713b1edbc	2116	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2117	* output channel 3 is supported by a timer instance.
AnnaBridge	171:3a7713b1edbc	2118	* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
AnnaBridge	171:3a7713b1edbc	2119	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2120	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	171:3a7713b1edbc	2121	*/
AnnaBridge	171:3a7713b1edbc	2122	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2123	{
AnnaBridge	171:3a7713b1edbc	2124	return (uint32_t)(READ_REG(TIMx->CCR3));
AnnaBridge	171:3a7713b1edbc	2125	}
AnnaBridge	171:3a7713b1edbc	2126
AnnaBridge	171:3a7713b1edbc	2127	/**
AnnaBridge	171:3a7713b1edbc	2128	* @brief Get compare value (TIMx_CCR4) set for output channel 4.
AnnaBridge	171:3a7713b1edbc	2129	* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	171:3a7713b1edbc	2130	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	2131	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	171:3a7713b1edbc	2132	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2133	* output channel 4 is supported by a timer instance.
AnnaBridge	171:3a7713b1edbc	2134	* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
AnnaBridge	171:3a7713b1edbc	2135	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2136	* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	171:3a7713b1edbc	2137	*/
AnnaBridge	171:3a7713b1edbc	2138	__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2139	{
AnnaBridge	171:3a7713b1edbc	2140	return (uint32_t)(READ_REG(TIMx->CCR4));
AnnaBridge	171:3a7713b1edbc	2141	}
AnnaBridge	171:3a7713b1edbc	2142
AnnaBridge	171:3a7713b1edbc	2143	/**
AnnaBridge	171:3a7713b1edbc	2144	* @}
AnnaBridge	171:3a7713b1edbc	2145	*/
AnnaBridge	171:3a7713b1edbc	2146
AnnaBridge	171:3a7713b1edbc	2147	/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
AnnaBridge	171:3a7713b1edbc	2148	* @{
AnnaBridge	171:3a7713b1edbc	2149	*/
AnnaBridge	171:3a7713b1edbc	2150	/**
AnnaBridge	171:3a7713b1edbc	2151	* @brief Configure input channel.
AnnaBridge	171:3a7713b1edbc	2152	* @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	2153	* CCMR1 IC1PSC LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	2154	* CCMR1 IC1F LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	2155	* CCMR1 CC2S LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	2156	* CCMR1 IC2PSC LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	2157	* CCMR1 IC2F LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	2158	* CCMR2 CC3S LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	2159	* CCMR2 IC3PSC LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	2160	* CCMR2 IC3F LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	2161	* CCMR2 CC4S LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	2162	* CCMR2 IC4PSC LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	2163	* CCMR2 IC4F LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	2164	* CCER CC1P LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	2165	* CCER CC1NP LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	2166	* CCER CC2P LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	2167	* CCER CC2NP LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	2168	* CCER CC3P LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	2169	* CCER CC3NP LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	2170	* CCER CC4P LL_TIM_IC_Config\n
AnnaBridge	171:3a7713b1edbc	2171	* CCER CC4NP LL_TIM_IC_Config
AnnaBridge	171:3a7713b1edbc	2172	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2173	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2174	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	2175	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	2176	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	2177	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	2178	* @param Configuration This parameter must be a combination of all the following values:
AnnaBridge	171:3a7713b1edbc	2179	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
AnnaBridge	171:3a7713b1edbc	2180	* @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
AnnaBridge	171:3a7713b1edbc	2181	* @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
AnnaBridge	171:3a7713b1edbc	2182	* @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
AnnaBridge	171:3a7713b1edbc	2183	* @retval None
AnnaBridge	171:3a7713b1edbc	2184	*/
AnnaBridge	171:3a7713b1edbc	2185	__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
AnnaBridge	171:3a7713b1edbc	2186	{
AnnaBridge	171:3a7713b1edbc	2187	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	2188	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	2189	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
AnnaBridge	171:3a7713b1edbc	2190	((Configuration >> 16U) & (TIM_CCMR1_IC1F \| TIM_CCMR1_IC1PSC \| TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	171:3a7713b1edbc	2191	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
AnnaBridge	171:3a7713b1edbc	2192	(Configuration & (TIM_CCER_CC1NP \| TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	171:3a7713b1edbc	2193	}
AnnaBridge	171:3a7713b1edbc	2194
AnnaBridge	171:3a7713b1edbc	2195	/**
AnnaBridge	171:3a7713b1edbc	2196	* @brief Set the active input.
AnnaBridge	171:3a7713b1edbc	2197	* @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
AnnaBridge	171:3a7713b1edbc	2198	* CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
AnnaBridge	171:3a7713b1edbc	2199	* CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
AnnaBridge	171:3a7713b1edbc	2200	* CCMR2 CC4S LL_TIM_IC_SetActiveInput
AnnaBridge	171:3a7713b1edbc	2201	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2202	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2203	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	2204	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	2205	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	2206	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	2207	* @param ICActiveInput This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2208	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
AnnaBridge	171:3a7713b1edbc	2209	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
AnnaBridge	171:3a7713b1edbc	2210	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
AnnaBridge	171:3a7713b1edbc	2211	* @retval None
AnnaBridge	171:3a7713b1edbc	2212	*/
AnnaBridge	171:3a7713b1edbc	2213	__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
AnnaBridge	171:3a7713b1edbc	2214	{
AnnaBridge	171:3a7713b1edbc	2215	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	2216	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	2217	MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	171:3a7713b1edbc	2218	}
AnnaBridge	171:3a7713b1edbc	2219
AnnaBridge	171:3a7713b1edbc	2220	/**
AnnaBridge	171:3a7713b1edbc	2221	* @brief Get the current active input.
AnnaBridge	171:3a7713b1edbc	2222	* @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
AnnaBridge	171:3a7713b1edbc	2223	* CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
AnnaBridge	171:3a7713b1edbc	2224	* CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
AnnaBridge	171:3a7713b1edbc	2225	* CCMR2 CC4S LL_TIM_IC_GetActiveInput
AnnaBridge	171:3a7713b1edbc	2226	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2227	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2228	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	2229	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	2230	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	2231	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	2232	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2233	* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
AnnaBridge	171:3a7713b1edbc	2234	* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
AnnaBridge	171:3a7713b1edbc	2235	* @arg @ref LL_TIM_ACTIVEINPUT_TRC
AnnaBridge	171:3a7713b1edbc	2236	*/
AnnaBridge	171:3a7713b1edbc	2237	__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	2238	{
AnnaBridge	171:3a7713b1edbc	2239	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	2240	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	2241	return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
AnnaBridge	171:3a7713b1edbc	2242	}
AnnaBridge	171:3a7713b1edbc	2243
AnnaBridge	171:3a7713b1edbc	2244	/**
AnnaBridge	171:3a7713b1edbc	2245	* @brief Set the prescaler of input channel.
AnnaBridge	171:3a7713b1edbc	2246	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
AnnaBridge	171:3a7713b1edbc	2247	* CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
AnnaBridge	171:3a7713b1edbc	2248	* CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
AnnaBridge	171:3a7713b1edbc	2249	* CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
AnnaBridge	171:3a7713b1edbc	2250	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2251	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2252	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	2253	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	2254	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	2255	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	2256	* @param ICPrescaler This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2257	* @arg @ref LL_TIM_ICPSC_DIV1
AnnaBridge	171:3a7713b1edbc	2258	* @arg @ref LL_TIM_ICPSC_DIV2
AnnaBridge	171:3a7713b1edbc	2259	* @arg @ref LL_TIM_ICPSC_DIV4
AnnaBridge	171:3a7713b1edbc	2260	* @arg @ref LL_TIM_ICPSC_DIV8
AnnaBridge	171:3a7713b1edbc	2261	* @retval None
AnnaBridge	171:3a7713b1edbc	2262	*/
AnnaBridge	171:3a7713b1edbc	2263	__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
AnnaBridge	171:3a7713b1edbc	2264	{
AnnaBridge	171:3a7713b1edbc	2265	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	2266	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	2267	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	171:3a7713b1edbc	2268	}
AnnaBridge	171:3a7713b1edbc	2269
AnnaBridge	171:3a7713b1edbc	2270	/**
AnnaBridge	171:3a7713b1edbc	2271	* @brief Get the current prescaler value acting on an input channel.
AnnaBridge	171:3a7713b1edbc	2272	* @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
AnnaBridge	171:3a7713b1edbc	2273	* CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
AnnaBridge	171:3a7713b1edbc	2274	* CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
AnnaBridge	171:3a7713b1edbc	2275	* CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
AnnaBridge	171:3a7713b1edbc	2276	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2277	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2278	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	2279	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	2280	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	2281	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	2282	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2283	* @arg @ref LL_TIM_ICPSC_DIV1
AnnaBridge	171:3a7713b1edbc	2284	* @arg @ref LL_TIM_ICPSC_DIV2
AnnaBridge	171:3a7713b1edbc	2285	* @arg @ref LL_TIM_ICPSC_DIV4
AnnaBridge	171:3a7713b1edbc	2286	* @arg @ref LL_TIM_ICPSC_DIV8
AnnaBridge	171:3a7713b1edbc	2287	*/
AnnaBridge	171:3a7713b1edbc	2288	__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	2289	{
AnnaBridge	171:3a7713b1edbc	2290	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	2291	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	2292	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
AnnaBridge	171:3a7713b1edbc	2293	}
AnnaBridge	171:3a7713b1edbc	2294
AnnaBridge	171:3a7713b1edbc	2295	/**
AnnaBridge	171:3a7713b1edbc	2296	* @brief Set the input filter duration.
AnnaBridge	171:3a7713b1edbc	2297	* @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
AnnaBridge	171:3a7713b1edbc	2298	* CCMR1 IC2F LL_TIM_IC_SetFilter\n
AnnaBridge	171:3a7713b1edbc	2299	* CCMR2 IC3F LL_TIM_IC_SetFilter\n
AnnaBridge	171:3a7713b1edbc	2300	* CCMR2 IC4F LL_TIM_IC_SetFilter
AnnaBridge	171:3a7713b1edbc	2301	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2302	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2303	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	2304	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	2305	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	2306	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	2307	* @param ICFilter This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2308	* @arg @ref LL_TIM_IC_FILTER_FDIV1
AnnaBridge	171:3a7713b1edbc	2309	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
AnnaBridge	171:3a7713b1edbc	2310	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
AnnaBridge	171:3a7713b1edbc	2311	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
AnnaBridge	171:3a7713b1edbc	2312	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
AnnaBridge	171:3a7713b1edbc	2313	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
AnnaBridge	171:3a7713b1edbc	2314	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
AnnaBridge	171:3a7713b1edbc	2315	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
AnnaBridge	171:3a7713b1edbc	2316	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
AnnaBridge	171:3a7713b1edbc	2317	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
AnnaBridge	171:3a7713b1edbc	2318	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
AnnaBridge	171:3a7713b1edbc	2319	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
AnnaBridge	171:3a7713b1edbc	2320	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
AnnaBridge	171:3a7713b1edbc	2321	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
AnnaBridge	171:3a7713b1edbc	2322	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
AnnaBridge	171:3a7713b1edbc	2323	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
AnnaBridge	171:3a7713b1edbc	2324	* @retval None
AnnaBridge	171:3a7713b1edbc	2325	*/
AnnaBridge	171:3a7713b1edbc	2326	__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
AnnaBridge	171:3a7713b1edbc	2327	{
AnnaBridge	171:3a7713b1edbc	2328	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	2329	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	2330	MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
AnnaBridge	171:3a7713b1edbc	2331	}
AnnaBridge	171:3a7713b1edbc	2332
AnnaBridge	171:3a7713b1edbc	2333	/**
AnnaBridge	171:3a7713b1edbc	2334	* @brief Get the input filter duration.
AnnaBridge	171:3a7713b1edbc	2335	* @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
AnnaBridge	171:3a7713b1edbc	2336	* CCMR1 IC2F LL_TIM_IC_GetFilter\n
AnnaBridge	171:3a7713b1edbc	2337	* CCMR2 IC3F LL_TIM_IC_GetFilter\n
AnnaBridge	171:3a7713b1edbc	2338	* CCMR2 IC4F LL_TIM_IC_GetFilter
AnnaBridge	171:3a7713b1edbc	2339	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2340	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2341	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	2342	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	2343	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	2344	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	2345	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2346	* @arg @ref LL_TIM_IC_FILTER_FDIV1
AnnaBridge	171:3a7713b1edbc	2347	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
AnnaBridge	171:3a7713b1edbc	2348	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
AnnaBridge	171:3a7713b1edbc	2349	* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
AnnaBridge	171:3a7713b1edbc	2350	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
AnnaBridge	171:3a7713b1edbc	2351	* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
AnnaBridge	171:3a7713b1edbc	2352	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
AnnaBridge	171:3a7713b1edbc	2353	* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
AnnaBridge	171:3a7713b1edbc	2354	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
AnnaBridge	171:3a7713b1edbc	2355	* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
AnnaBridge	171:3a7713b1edbc	2356	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
AnnaBridge	171:3a7713b1edbc	2357	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
AnnaBridge	171:3a7713b1edbc	2358	* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
AnnaBridge	171:3a7713b1edbc	2359	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
AnnaBridge	171:3a7713b1edbc	2360	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
AnnaBridge	171:3a7713b1edbc	2361	* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
AnnaBridge	171:3a7713b1edbc	2362	*/
AnnaBridge	171:3a7713b1edbc	2363	__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	2364	{
AnnaBridge	171:3a7713b1edbc	2365	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	2366	register uint32_t pReg = (uint32_t )((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
AnnaBridge	171:3a7713b1edbc	2367	return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
AnnaBridge	171:3a7713b1edbc	2368	}
AnnaBridge	171:3a7713b1edbc	2369
AnnaBridge	171:3a7713b1edbc	2370	/**
AnnaBridge	171:3a7713b1edbc	2371	* @brief Set the input channel polarity.
AnnaBridge	171:3a7713b1edbc	2372	* @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
AnnaBridge	171:3a7713b1edbc	2373	* CCER CC1NP LL_TIM_IC_SetPolarity\n
AnnaBridge	171:3a7713b1edbc	2374	* CCER CC2P LL_TIM_IC_SetPolarity\n
AnnaBridge	171:3a7713b1edbc	2375	* CCER CC2NP LL_TIM_IC_SetPolarity\n
AnnaBridge	171:3a7713b1edbc	2376	* CCER CC3P LL_TIM_IC_SetPolarity\n
AnnaBridge	171:3a7713b1edbc	2377	* CCER CC3NP LL_TIM_IC_SetPolarity\n
AnnaBridge	171:3a7713b1edbc	2378	* CCER CC4P LL_TIM_IC_SetPolarity\n
AnnaBridge	171:3a7713b1edbc	2379	* CCER CC4NP LL_TIM_IC_SetPolarity
AnnaBridge	171:3a7713b1edbc	2380	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2381	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2382	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	2383	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	2384	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	2385	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	2386	* @param ICPolarity This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2387	* @arg @ref LL_TIM_IC_POLARITY_RISING
AnnaBridge	171:3a7713b1edbc	2388	* @arg @ref LL_TIM_IC_POLARITY_FALLING
AnnaBridge	171:3a7713b1edbc	2389	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
AnnaBridge	171:3a7713b1edbc	2390	* @retval None
AnnaBridge	171:3a7713b1edbc	2391	*/
AnnaBridge	171:3a7713b1edbc	2392	__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
AnnaBridge	171:3a7713b1edbc	2393	{
AnnaBridge	171:3a7713b1edbc	2394	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	2395	MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
AnnaBridge	171:3a7713b1edbc	2396	ICPolarity << SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	171:3a7713b1edbc	2397	}
AnnaBridge	171:3a7713b1edbc	2398
AnnaBridge	171:3a7713b1edbc	2399	/**
AnnaBridge	171:3a7713b1edbc	2400	* @brief Get the current input channel polarity.
AnnaBridge	171:3a7713b1edbc	2401	* @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
AnnaBridge	171:3a7713b1edbc	2402	* CCER CC1NP LL_TIM_IC_GetPolarity\n
AnnaBridge	171:3a7713b1edbc	2403	* CCER CC2P LL_TIM_IC_GetPolarity\n
AnnaBridge	171:3a7713b1edbc	2404	* CCER CC2NP LL_TIM_IC_GetPolarity\n
AnnaBridge	171:3a7713b1edbc	2405	* CCER CC3P LL_TIM_IC_GetPolarity\n
AnnaBridge	171:3a7713b1edbc	2406	* CCER CC3NP LL_TIM_IC_GetPolarity\n
AnnaBridge	171:3a7713b1edbc	2407	* CCER CC4P LL_TIM_IC_GetPolarity\n
AnnaBridge	171:3a7713b1edbc	2408	* CCER CC4NP LL_TIM_IC_GetPolarity
AnnaBridge	171:3a7713b1edbc	2409	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2410	* @param Channel This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2411	* @arg @ref LL_TIM_CHANNEL_CH1
AnnaBridge	171:3a7713b1edbc	2412	* @arg @ref LL_TIM_CHANNEL_CH2
AnnaBridge	171:3a7713b1edbc	2413	* @arg @ref LL_TIM_CHANNEL_CH3
AnnaBridge	171:3a7713b1edbc	2414	* @arg @ref LL_TIM_CHANNEL_CH4
AnnaBridge	171:3a7713b1edbc	2415	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2416	* @arg @ref LL_TIM_IC_POLARITY_RISING
AnnaBridge	171:3a7713b1edbc	2417	* @arg @ref LL_TIM_IC_POLARITY_FALLING
AnnaBridge	171:3a7713b1edbc	2418	* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
AnnaBridge	171:3a7713b1edbc	2419	*/
AnnaBridge	171:3a7713b1edbc	2420	__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
AnnaBridge	171:3a7713b1edbc	2421	{
AnnaBridge	171:3a7713b1edbc	2422	register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
AnnaBridge	171:3a7713b1edbc	2423	return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP \| TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
AnnaBridge	171:3a7713b1edbc	2424	SHIFT_TAB_CCxP[iChannel]);
AnnaBridge	171:3a7713b1edbc	2425	}
AnnaBridge	171:3a7713b1edbc	2426
AnnaBridge	171:3a7713b1edbc	2427	/**
AnnaBridge	171:3a7713b1edbc	2428	* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
AnnaBridge	171:3a7713b1edbc	2429	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2430	* a timer instance provides an XOR input.
AnnaBridge	171:3a7713b1edbc	2431	* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
AnnaBridge	171:3a7713b1edbc	2432	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2433	* @retval None
AnnaBridge	171:3a7713b1edbc	2434	*/
AnnaBridge	171:3a7713b1edbc	2435	__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2436	{
AnnaBridge	171:3a7713b1edbc	2437	SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
AnnaBridge	171:3a7713b1edbc	2438	}
AnnaBridge	171:3a7713b1edbc	2439
AnnaBridge	171:3a7713b1edbc	2440	/**
AnnaBridge	171:3a7713b1edbc	2441	* @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
AnnaBridge	171:3a7713b1edbc	2442	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2443	* a timer instance provides an XOR input.
AnnaBridge	171:3a7713b1edbc	2444	* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
AnnaBridge	171:3a7713b1edbc	2445	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2446	* @retval None
AnnaBridge	171:3a7713b1edbc	2447	*/
AnnaBridge	171:3a7713b1edbc	2448	__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2449	{
AnnaBridge	171:3a7713b1edbc	2450	CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
AnnaBridge	171:3a7713b1edbc	2451	}
AnnaBridge	171:3a7713b1edbc	2452
AnnaBridge	171:3a7713b1edbc	2453	/**
AnnaBridge	171:3a7713b1edbc	2454	* @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
AnnaBridge	171:3a7713b1edbc	2455	* @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2456	* a timer instance provides an XOR input.
AnnaBridge	171:3a7713b1edbc	2457	* @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
AnnaBridge	171:3a7713b1edbc	2458	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2459	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2460	*/
AnnaBridge	171:3a7713b1edbc	2461	__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2462	{
AnnaBridge	171:3a7713b1edbc	2463	return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
AnnaBridge	171:3a7713b1edbc	2464	}
AnnaBridge	171:3a7713b1edbc	2465
AnnaBridge	171:3a7713b1edbc	2466	/**
AnnaBridge	171:3a7713b1edbc	2467	* @brief Get captured value for input channel 1.
AnnaBridge	171:3a7713b1edbc	2468	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	171:3a7713b1edbc	2469	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	2470	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	171:3a7713b1edbc	2471	* @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2472	* input channel 1 is supported by a timer instance.
AnnaBridge	171:3a7713b1edbc	2473	* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
AnnaBridge	171:3a7713b1edbc	2474	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2475	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	171:3a7713b1edbc	2476	*/
AnnaBridge	171:3a7713b1edbc	2477	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2478	{
AnnaBridge	171:3a7713b1edbc	2479	return (uint32_t)(READ_REG(TIMx->CCR1));
AnnaBridge	171:3a7713b1edbc	2480	}
AnnaBridge	171:3a7713b1edbc	2481
AnnaBridge	171:3a7713b1edbc	2482	/**
AnnaBridge	171:3a7713b1edbc	2483	* @brief Get captured value for input channel 2.
AnnaBridge	171:3a7713b1edbc	2484	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	171:3a7713b1edbc	2485	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	2486	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	171:3a7713b1edbc	2487	* @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2488	* input channel 2 is supported by a timer instance.
AnnaBridge	171:3a7713b1edbc	2489	* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
AnnaBridge	171:3a7713b1edbc	2490	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2491	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	171:3a7713b1edbc	2492	*/
AnnaBridge	171:3a7713b1edbc	2493	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2494	{
AnnaBridge	171:3a7713b1edbc	2495	return (uint32_t)(READ_REG(TIMx->CCR2));
AnnaBridge	171:3a7713b1edbc	2496	}
AnnaBridge	171:3a7713b1edbc	2497
AnnaBridge	171:3a7713b1edbc	2498	/**
AnnaBridge	171:3a7713b1edbc	2499	* @brief Get captured value for input channel 3.
AnnaBridge	171:3a7713b1edbc	2500	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	171:3a7713b1edbc	2501	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	2502	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	171:3a7713b1edbc	2503	* @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2504	* input channel 3 is supported by a timer instance.
AnnaBridge	171:3a7713b1edbc	2505	* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
AnnaBridge	171:3a7713b1edbc	2506	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2507	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	171:3a7713b1edbc	2508	*/
AnnaBridge	171:3a7713b1edbc	2509	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2510	{
AnnaBridge	171:3a7713b1edbc	2511	return (uint32_t)(READ_REG(TIMx->CCR3));
AnnaBridge	171:3a7713b1edbc	2512	}
AnnaBridge	171:3a7713b1edbc	2513
AnnaBridge	171:3a7713b1edbc	2514	/**
AnnaBridge	171:3a7713b1edbc	2515	* @brief Get captured value for input channel 4.
AnnaBridge	171:3a7713b1edbc	2516	* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
AnnaBridge	171:3a7713b1edbc	2517	* @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	2518	* whether or not a timer instance supports a 32 bits counter.
AnnaBridge	171:3a7713b1edbc	2519	* @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2520	* input channel 4 is supported by a timer instance.
AnnaBridge	171:3a7713b1edbc	2521	* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
AnnaBridge	171:3a7713b1edbc	2522	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2523	* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
AnnaBridge	171:3a7713b1edbc	2524	*/
AnnaBridge	171:3a7713b1edbc	2525	__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2526	{
AnnaBridge	171:3a7713b1edbc	2527	return (uint32_t)(READ_REG(TIMx->CCR4));
AnnaBridge	171:3a7713b1edbc	2528	}
AnnaBridge	171:3a7713b1edbc	2529
AnnaBridge	171:3a7713b1edbc	2530	/**
AnnaBridge	171:3a7713b1edbc	2531	* @}
AnnaBridge	171:3a7713b1edbc	2532	*/
AnnaBridge	171:3a7713b1edbc	2533
AnnaBridge	171:3a7713b1edbc	2534	/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
AnnaBridge	171:3a7713b1edbc	2535	* @{
AnnaBridge	171:3a7713b1edbc	2536	*/
AnnaBridge	171:3a7713b1edbc	2537	/**
AnnaBridge	171:3a7713b1edbc	2538	* @brief Enable external clock mode 2.
AnnaBridge	171:3a7713b1edbc	2539	* @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
AnnaBridge	171:3a7713b1edbc	2540	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	2541	* whether or not a timer instance supports external clock mode2.
AnnaBridge	171:3a7713b1edbc	2542	* @rmtoll SMCR ECE LL_TIM_EnableExternalClock
AnnaBridge	171:3a7713b1edbc	2543	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2544	* @retval None
AnnaBridge	171:3a7713b1edbc	2545	*/
AnnaBridge	171:3a7713b1edbc	2546	__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2547	{
AnnaBridge	171:3a7713b1edbc	2548	SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
AnnaBridge	171:3a7713b1edbc	2549	}
AnnaBridge	171:3a7713b1edbc	2550
AnnaBridge	171:3a7713b1edbc	2551	/**
AnnaBridge	171:3a7713b1edbc	2552	* @brief Disable external clock mode 2.
AnnaBridge	171:3a7713b1edbc	2553	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	2554	* whether or not a timer instance supports external clock mode2.
AnnaBridge	171:3a7713b1edbc	2555	* @rmtoll SMCR ECE LL_TIM_DisableExternalClock
AnnaBridge	171:3a7713b1edbc	2556	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2557	* @retval None
AnnaBridge	171:3a7713b1edbc	2558	*/
AnnaBridge	171:3a7713b1edbc	2559	__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2560	{
AnnaBridge	171:3a7713b1edbc	2561	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
AnnaBridge	171:3a7713b1edbc	2562	}
AnnaBridge	171:3a7713b1edbc	2563
AnnaBridge	171:3a7713b1edbc	2564	/**
AnnaBridge	171:3a7713b1edbc	2565	* @brief Indicate whether external clock mode 2 is enabled.
AnnaBridge	171:3a7713b1edbc	2566	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	2567	* whether or not a timer instance supports external clock mode2.
AnnaBridge	171:3a7713b1edbc	2568	* @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
AnnaBridge	171:3a7713b1edbc	2569	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2570	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2571	*/
AnnaBridge	171:3a7713b1edbc	2572	__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2573	{
AnnaBridge	171:3a7713b1edbc	2574	return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
AnnaBridge	171:3a7713b1edbc	2575	}
AnnaBridge	171:3a7713b1edbc	2576
AnnaBridge	171:3a7713b1edbc	2577	/**
AnnaBridge	171:3a7713b1edbc	2578	* @brief Set the clock source of the counter clock.
AnnaBridge	171:3a7713b1edbc	2579	* @note when selected clock source is external clock mode 1, the timer input
AnnaBridge	171:3a7713b1edbc	2580	* the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
AnnaBridge	171:3a7713b1edbc	2581	* function. This timer input must be configured by calling
AnnaBridge	171:3a7713b1edbc	2582	* the @ref LL_TIM_IC_Config() function.
AnnaBridge	171:3a7713b1edbc	2583	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	2584	* whether or not a timer instance supports external clock mode1.
AnnaBridge	171:3a7713b1edbc	2585	* @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	2586	* whether or not a timer instance supports external clock mode2.
AnnaBridge	171:3a7713b1edbc	2587	* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
AnnaBridge	171:3a7713b1edbc	2588	* SMCR ECE LL_TIM_SetClockSource
AnnaBridge	171:3a7713b1edbc	2589	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2590	* @param ClockSource This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2591	* @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
AnnaBridge	171:3a7713b1edbc	2592	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
AnnaBridge	171:3a7713b1edbc	2593	* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
AnnaBridge	171:3a7713b1edbc	2594	* @retval None
AnnaBridge	171:3a7713b1edbc	2595	*/
AnnaBridge	171:3a7713b1edbc	2596	__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
AnnaBridge	171:3a7713b1edbc	2597	{
AnnaBridge	171:3a7713b1edbc	2598	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS \| TIM_SMCR_ECE, ClockSource);
AnnaBridge	171:3a7713b1edbc	2599	}
AnnaBridge	171:3a7713b1edbc	2600
AnnaBridge	171:3a7713b1edbc	2601	/**
AnnaBridge	171:3a7713b1edbc	2602	* @brief Set the encoder interface mode.
AnnaBridge	171:3a7713b1edbc	2603	* @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	2604	* whether or not a timer instance supports the encoder mode.
AnnaBridge	171:3a7713b1edbc	2605	* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
AnnaBridge	171:3a7713b1edbc	2606	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2607	* @param EncoderMode This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2608	* @arg @ref LL_TIM_ENCODERMODE_X2_TI1
AnnaBridge	171:3a7713b1edbc	2609	* @arg @ref LL_TIM_ENCODERMODE_X2_TI2
AnnaBridge	171:3a7713b1edbc	2610	* @arg @ref LL_TIM_ENCODERMODE_X4_TI12
AnnaBridge	171:3a7713b1edbc	2611	* @retval None
AnnaBridge	171:3a7713b1edbc	2612	*/
AnnaBridge	171:3a7713b1edbc	2613	__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
AnnaBridge	171:3a7713b1edbc	2614	{
AnnaBridge	171:3a7713b1edbc	2615	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
AnnaBridge	171:3a7713b1edbc	2616	}
AnnaBridge	171:3a7713b1edbc	2617
AnnaBridge	171:3a7713b1edbc	2618	/**
AnnaBridge	171:3a7713b1edbc	2619	* @}
AnnaBridge	171:3a7713b1edbc	2620	*/
AnnaBridge	171:3a7713b1edbc	2621
AnnaBridge	171:3a7713b1edbc	2622	/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
AnnaBridge	171:3a7713b1edbc	2623	* @{
AnnaBridge	171:3a7713b1edbc	2624	*/
AnnaBridge	171:3a7713b1edbc	2625	/**
AnnaBridge	171:3a7713b1edbc	2626	* @brief Set the trigger output (TRGO) used for timer synchronization .
AnnaBridge	171:3a7713b1edbc	2627	* @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
AnnaBridge	171:3a7713b1edbc	2628	* whether or not a timer instance can operate as a master timer.
AnnaBridge	171:3a7713b1edbc	2629	* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
AnnaBridge	171:3a7713b1edbc	2630	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2631	* @param TimerSynchronization This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2632	* @arg @ref LL_TIM_TRGO_RESET
AnnaBridge	171:3a7713b1edbc	2633	* @arg @ref LL_TIM_TRGO_ENABLE
AnnaBridge	171:3a7713b1edbc	2634	* @arg @ref LL_TIM_TRGO_UPDATE
AnnaBridge	171:3a7713b1edbc	2635	* @arg @ref LL_TIM_TRGO_CC1IF
AnnaBridge	171:3a7713b1edbc	2636	* @arg @ref LL_TIM_TRGO_OC1REF
AnnaBridge	171:3a7713b1edbc	2637	* @arg @ref LL_TIM_TRGO_OC2REF
AnnaBridge	171:3a7713b1edbc	2638	* @arg @ref LL_TIM_TRGO_OC3REF
AnnaBridge	171:3a7713b1edbc	2639	* @arg @ref LL_TIM_TRGO_OC4REF
AnnaBridge	171:3a7713b1edbc	2640	* @retval None
AnnaBridge	171:3a7713b1edbc	2641	*/
AnnaBridge	171:3a7713b1edbc	2642	__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
AnnaBridge	171:3a7713b1edbc	2643	{
AnnaBridge	171:3a7713b1edbc	2644	MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
AnnaBridge	171:3a7713b1edbc	2645	}
AnnaBridge	171:3a7713b1edbc	2646
AnnaBridge	171:3a7713b1edbc	2647	/**
AnnaBridge	171:3a7713b1edbc	2648	* @brief Set the synchronization mode of a slave timer.
AnnaBridge	171:3a7713b1edbc	2649	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2650	* a timer instance can operate as a slave timer.
AnnaBridge	171:3a7713b1edbc	2651	* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
AnnaBridge	171:3a7713b1edbc	2652	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2653	* @param SlaveMode This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2654	* @arg @ref LL_TIM_SLAVEMODE_DISABLED
AnnaBridge	171:3a7713b1edbc	2655	* @arg @ref LL_TIM_SLAVEMODE_RESET
AnnaBridge	171:3a7713b1edbc	2656	* @arg @ref LL_TIM_SLAVEMODE_GATED
AnnaBridge	171:3a7713b1edbc	2657	* @arg @ref LL_TIM_SLAVEMODE_TRIGGER
AnnaBridge	171:3a7713b1edbc	2658	* @retval None
AnnaBridge	171:3a7713b1edbc	2659	*/
AnnaBridge	171:3a7713b1edbc	2660	__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
AnnaBridge	171:3a7713b1edbc	2661	{
AnnaBridge	171:3a7713b1edbc	2662	MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
AnnaBridge	171:3a7713b1edbc	2663	}
AnnaBridge	171:3a7713b1edbc	2664
AnnaBridge	171:3a7713b1edbc	2665	/**
AnnaBridge	171:3a7713b1edbc	2666	* @brief Set the selects the trigger input to be used to synchronize the counter.
AnnaBridge	171:3a7713b1edbc	2667	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2668	* a timer instance can operate as a slave timer.
AnnaBridge	171:3a7713b1edbc	2669	* @rmtoll SMCR TS LL_TIM_SetTriggerInput
AnnaBridge	171:3a7713b1edbc	2670	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2671	* @param TriggerInput This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2672	* @arg @ref LL_TIM_TS_ITR0
AnnaBridge	171:3a7713b1edbc	2673	* @arg @ref LL_TIM_TS_ITR1
AnnaBridge	171:3a7713b1edbc	2674	* @arg @ref LL_TIM_TS_ITR2
AnnaBridge	171:3a7713b1edbc	2675	* @arg @ref LL_TIM_TS_ITR3
AnnaBridge	171:3a7713b1edbc	2676	* @arg @ref LL_TIM_TS_TI1F_ED
AnnaBridge	171:3a7713b1edbc	2677	* @arg @ref LL_TIM_TS_TI1FP1
AnnaBridge	171:3a7713b1edbc	2678	* @arg @ref LL_TIM_TS_TI2FP2
AnnaBridge	171:3a7713b1edbc	2679	* @arg @ref LL_TIM_TS_ETRF
AnnaBridge	171:3a7713b1edbc	2680	* @retval None
AnnaBridge	171:3a7713b1edbc	2681	*/
AnnaBridge	171:3a7713b1edbc	2682	__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
AnnaBridge	171:3a7713b1edbc	2683	{
AnnaBridge	171:3a7713b1edbc	2684	MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
AnnaBridge	171:3a7713b1edbc	2685	}
AnnaBridge	171:3a7713b1edbc	2686
AnnaBridge	171:3a7713b1edbc	2687	/**
AnnaBridge	171:3a7713b1edbc	2688	* @brief Enable the Master/Slave mode.
AnnaBridge	171:3a7713b1edbc	2689	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2690	* a timer instance can operate as a slave timer.
AnnaBridge	171:3a7713b1edbc	2691	* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
AnnaBridge	171:3a7713b1edbc	2692	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2693	* @retval None
AnnaBridge	171:3a7713b1edbc	2694	*/
AnnaBridge	171:3a7713b1edbc	2695	__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2696	{
AnnaBridge	171:3a7713b1edbc	2697	SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
AnnaBridge	171:3a7713b1edbc	2698	}
AnnaBridge	171:3a7713b1edbc	2699
AnnaBridge	171:3a7713b1edbc	2700	/**
AnnaBridge	171:3a7713b1edbc	2701	* @brief Disable the Master/Slave mode.
AnnaBridge	171:3a7713b1edbc	2702	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2703	* a timer instance can operate as a slave timer.
AnnaBridge	171:3a7713b1edbc	2704	* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
AnnaBridge	171:3a7713b1edbc	2705	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2706	* @retval None
AnnaBridge	171:3a7713b1edbc	2707	*/
AnnaBridge	171:3a7713b1edbc	2708	__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2709	{
AnnaBridge	171:3a7713b1edbc	2710	CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
AnnaBridge	171:3a7713b1edbc	2711	}
AnnaBridge	171:3a7713b1edbc	2712
AnnaBridge	171:3a7713b1edbc	2713	/**
AnnaBridge	171:3a7713b1edbc	2714	* @brief Indicates whether the Master/Slave mode is enabled.
AnnaBridge	171:3a7713b1edbc	2715	* @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2716	* a timer instance can operate as a slave timer.
AnnaBridge	171:3a7713b1edbc	2717	* @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
AnnaBridge	171:3a7713b1edbc	2718	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2719	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2720	*/
AnnaBridge	171:3a7713b1edbc	2721	__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2722	{
AnnaBridge	171:3a7713b1edbc	2723	return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
AnnaBridge	171:3a7713b1edbc	2724	}
AnnaBridge	171:3a7713b1edbc	2725
AnnaBridge	171:3a7713b1edbc	2726	/**
AnnaBridge	171:3a7713b1edbc	2727	* @brief Configure the external trigger (ETR) input.
AnnaBridge	171:3a7713b1edbc	2728	* @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2729	* a timer instance provides an external trigger input.
AnnaBridge	171:3a7713b1edbc	2730	* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
AnnaBridge	171:3a7713b1edbc	2731	* SMCR ETPS LL_TIM_ConfigETR\n
AnnaBridge	171:3a7713b1edbc	2732	* SMCR ETF LL_TIM_ConfigETR
AnnaBridge	171:3a7713b1edbc	2733	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2734	* @param ETRPolarity This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2735	* @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
AnnaBridge	171:3a7713b1edbc	2736	* @arg @ref LL_TIM_ETR_POLARITY_INVERTED
AnnaBridge	171:3a7713b1edbc	2737	* @param ETRPrescaler This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2738	* @arg @ref LL_TIM_ETR_PRESCALER_DIV1
AnnaBridge	171:3a7713b1edbc	2739	* @arg @ref LL_TIM_ETR_PRESCALER_DIV2
AnnaBridge	171:3a7713b1edbc	2740	* @arg @ref LL_TIM_ETR_PRESCALER_DIV4
AnnaBridge	171:3a7713b1edbc	2741	* @arg @ref LL_TIM_ETR_PRESCALER_DIV8
AnnaBridge	171:3a7713b1edbc	2742	* @param ETRFilter This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2743	* @arg @ref LL_TIM_ETR_FILTER_FDIV1
AnnaBridge	171:3a7713b1edbc	2744	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
AnnaBridge	171:3a7713b1edbc	2745	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
AnnaBridge	171:3a7713b1edbc	2746	* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
AnnaBridge	171:3a7713b1edbc	2747	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
AnnaBridge	171:3a7713b1edbc	2748	* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
AnnaBridge	171:3a7713b1edbc	2749	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
AnnaBridge	171:3a7713b1edbc	2750	* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
AnnaBridge	171:3a7713b1edbc	2751	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
AnnaBridge	171:3a7713b1edbc	2752	* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
AnnaBridge	171:3a7713b1edbc	2753	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
AnnaBridge	171:3a7713b1edbc	2754	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
AnnaBridge	171:3a7713b1edbc	2755	* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
AnnaBridge	171:3a7713b1edbc	2756	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
AnnaBridge	171:3a7713b1edbc	2757	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
AnnaBridge	171:3a7713b1edbc	2758	* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
AnnaBridge	171:3a7713b1edbc	2759	* @retval None
AnnaBridge	171:3a7713b1edbc	2760	*/
AnnaBridge	171:3a7713b1edbc	2761	__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
AnnaBridge	171:3a7713b1edbc	2762	uint32_t ETRFilter)
AnnaBridge	171:3a7713b1edbc	2763	{
AnnaBridge	171:3a7713b1edbc	2764	MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP \| TIM_SMCR_ETPS \| TIM_SMCR_ETF, ETRPolarity \| ETRPrescaler \| ETRFilter);
AnnaBridge	171:3a7713b1edbc	2765	}
AnnaBridge	171:3a7713b1edbc	2766
AnnaBridge	171:3a7713b1edbc	2767	/**
AnnaBridge	171:3a7713b1edbc	2768	* @}
AnnaBridge	171:3a7713b1edbc	2769	*/
AnnaBridge	171:3a7713b1edbc	2770
AnnaBridge	171:3a7713b1edbc	2771	/** @defgroup TIM_LL_EF_Break_Function Break function configuration
AnnaBridge	171:3a7713b1edbc	2772	* @{
AnnaBridge	171:3a7713b1edbc	2773	*/
AnnaBridge	171:3a7713b1edbc	2774	/**
AnnaBridge	171:3a7713b1edbc	2775	* @brief Enable the break function.
AnnaBridge	171:3a7713b1edbc	2776	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2777	* a timer instance provides a break input.
AnnaBridge	171:3a7713b1edbc	2778	* @rmtoll BDTR BKE LL_TIM_EnableBRK
AnnaBridge	171:3a7713b1edbc	2779	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2780	* @retval None
AnnaBridge	171:3a7713b1edbc	2781	*/
AnnaBridge	171:3a7713b1edbc	2782	__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2783	{
AnnaBridge	171:3a7713b1edbc	2784	__IO uint32_t tmpreg;
AnnaBridge	171:3a7713b1edbc	2785
AnnaBridge	171:3a7713b1edbc	2786	SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
AnnaBridge	171:3a7713b1edbc	2787
AnnaBridge	171:3a7713b1edbc	2788	/* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
AnnaBridge	171:3a7713b1edbc	2789	tmpreg = READ_REG(TIMx->BDTR);
AnnaBridge	171:3a7713b1edbc	2790	(void)(tmpreg);
AnnaBridge	171:3a7713b1edbc	2791	}
AnnaBridge	171:3a7713b1edbc	2792
AnnaBridge	171:3a7713b1edbc	2793	/**
AnnaBridge	171:3a7713b1edbc	2794	* @brief Disable the break function.
AnnaBridge	171:3a7713b1edbc	2795	* @rmtoll BDTR BKE LL_TIM_DisableBRK
AnnaBridge	171:3a7713b1edbc	2796	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2797	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2798	* a timer instance provides a break input.
AnnaBridge	171:3a7713b1edbc	2799	* @retval None
AnnaBridge	171:3a7713b1edbc	2800	*/
AnnaBridge	171:3a7713b1edbc	2801	__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2802	{
AnnaBridge	171:3a7713b1edbc	2803	__IO uint32_t tmpreg;
AnnaBridge	171:3a7713b1edbc	2804
AnnaBridge	171:3a7713b1edbc	2805	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
AnnaBridge	171:3a7713b1edbc	2806
AnnaBridge	171:3a7713b1edbc	2807	/* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
AnnaBridge	171:3a7713b1edbc	2808	tmpreg = READ_REG(TIMx->BDTR);
AnnaBridge	171:3a7713b1edbc	2809	(void)(tmpreg);
AnnaBridge	171:3a7713b1edbc	2810	}
AnnaBridge	171:3a7713b1edbc	2811
AnnaBridge	171:3a7713b1edbc	2812	/**
AnnaBridge	171:3a7713b1edbc	2813	* @brief Configure the break input.
AnnaBridge	171:3a7713b1edbc	2814	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2815	* a timer instance provides a break input.
AnnaBridge	171:3a7713b1edbc	2816	* @rmtoll BDTR BKP LL_TIM_ConfigBRK
AnnaBridge	171:3a7713b1edbc	2817	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2818	* @param BreakPolarity This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2819	* @arg @ref LL_TIM_BREAK_POLARITY_LOW
AnnaBridge	171:3a7713b1edbc	2820	* @arg @ref LL_TIM_BREAK_POLARITY_HIGH
AnnaBridge	171:3a7713b1edbc	2821	* @retval None
AnnaBridge	171:3a7713b1edbc	2822	*/
AnnaBridge	171:3a7713b1edbc	2823	__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
AnnaBridge	171:3a7713b1edbc	2824	{
AnnaBridge	171:3a7713b1edbc	2825	__IO uint32_t tmpreg;
AnnaBridge	171:3a7713b1edbc	2826
AnnaBridge	171:3a7713b1edbc	2827	MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
AnnaBridge	171:3a7713b1edbc	2828
AnnaBridge	171:3a7713b1edbc	2829	/* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
AnnaBridge	171:3a7713b1edbc	2830	tmpreg = READ_REG(TIMx->BDTR);
AnnaBridge	171:3a7713b1edbc	2831	(void)(tmpreg);
AnnaBridge	171:3a7713b1edbc	2832	}
AnnaBridge	171:3a7713b1edbc	2833
AnnaBridge	171:3a7713b1edbc	2834	/**
AnnaBridge	171:3a7713b1edbc	2835	* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
AnnaBridge	171:3a7713b1edbc	2836	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2837	* a timer instance provides a break input.
AnnaBridge	171:3a7713b1edbc	2838	* @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
AnnaBridge	171:3a7713b1edbc	2839	* BDTR OSSR LL_TIM_SetOffStates
AnnaBridge	171:3a7713b1edbc	2840	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2841	* @param OffStateIdle This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2842	* @arg @ref LL_TIM_OSSI_DISABLE
AnnaBridge	171:3a7713b1edbc	2843	* @arg @ref LL_TIM_OSSI_ENABLE
AnnaBridge	171:3a7713b1edbc	2844	* @param OffStateRun This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2845	* @arg @ref LL_TIM_OSSR_DISABLE
AnnaBridge	171:3a7713b1edbc	2846	* @arg @ref LL_TIM_OSSR_ENABLE
AnnaBridge	171:3a7713b1edbc	2847	* @retval None
AnnaBridge	171:3a7713b1edbc	2848	*/
AnnaBridge	171:3a7713b1edbc	2849	__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
AnnaBridge	171:3a7713b1edbc	2850	{
AnnaBridge	171:3a7713b1edbc	2851	MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI \| TIM_BDTR_OSSR, OffStateIdle \| OffStateRun);
AnnaBridge	171:3a7713b1edbc	2852	}
AnnaBridge	171:3a7713b1edbc	2853
AnnaBridge	171:3a7713b1edbc	2854	/**
AnnaBridge	171:3a7713b1edbc	2855	* @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
AnnaBridge	171:3a7713b1edbc	2856	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2857	* a timer instance provides a break input.
AnnaBridge	171:3a7713b1edbc	2858	* @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
AnnaBridge	171:3a7713b1edbc	2859	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2860	* @retval None
AnnaBridge	171:3a7713b1edbc	2861	*/
AnnaBridge	171:3a7713b1edbc	2862	__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2863	{
AnnaBridge	171:3a7713b1edbc	2864	SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
AnnaBridge	171:3a7713b1edbc	2865	}
AnnaBridge	171:3a7713b1edbc	2866
AnnaBridge	171:3a7713b1edbc	2867	/**
AnnaBridge	171:3a7713b1edbc	2868	* @brief Disable automatic output (MOE can be set only by software).
AnnaBridge	171:3a7713b1edbc	2869	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2870	* a timer instance provides a break input.
AnnaBridge	171:3a7713b1edbc	2871	* @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
AnnaBridge	171:3a7713b1edbc	2872	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2873	* @retval None
AnnaBridge	171:3a7713b1edbc	2874	*/
AnnaBridge	171:3a7713b1edbc	2875	__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2876	{
AnnaBridge	171:3a7713b1edbc	2877	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
AnnaBridge	171:3a7713b1edbc	2878	}
AnnaBridge	171:3a7713b1edbc	2879
AnnaBridge	171:3a7713b1edbc	2880	/**
AnnaBridge	171:3a7713b1edbc	2881	* @brief Indicate whether automatic output is enabled.
AnnaBridge	171:3a7713b1edbc	2882	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2883	* a timer instance provides a break input.
AnnaBridge	171:3a7713b1edbc	2884	* @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
AnnaBridge	171:3a7713b1edbc	2885	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2886	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2887	*/
AnnaBridge	171:3a7713b1edbc	2888	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2889	{
AnnaBridge	171:3a7713b1edbc	2890	return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE));
AnnaBridge	171:3a7713b1edbc	2891	}
AnnaBridge	171:3a7713b1edbc	2892
AnnaBridge	171:3a7713b1edbc	2893	/**
AnnaBridge	171:3a7713b1edbc	2894	* @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
AnnaBridge	171:3a7713b1edbc	2895	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
AnnaBridge	171:3a7713b1edbc	2896	* software and is reset in case of break or break2 event
AnnaBridge	171:3a7713b1edbc	2897	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2898	* a timer instance provides a break input.
AnnaBridge	171:3a7713b1edbc	2899	* @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
AnnaBridge	171:3a7713b1edbc	2900	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2901	* @retval None
AnnaBridge	171:3a7713b1edbc	2902	*/
AnnaBridge	171:3a7713b1edbc	2903	__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2904	{
AnnaBridge	171:3a7713b1edbc	2905	SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
AnnaBridge	171:3a7713b1edbc	2906	}
AnnaBridge	171:3a7713b1edbc	2907
AnnaBridge	171:3a7713b1edbc	2908	/**
AnnaBridge	171:3a7713b1edbc	2909	* @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
AnnaBridge	171:3a7713b1edbc	2910	* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
AnnaBridge	171:3a7713b1edbc	2911	* software and is reset in case of break or break2 event.
AnnaBridge	171:3a7713b1edbc	2912	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2913	* a timer instance provides a break input.
AnnaBridge	171:3a7713b1edbc	2914	* @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
AnnaBridge	171:3a7713b1edbc	2915	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2916	* @retval None
AnnaBridge	171:3a7713b1edbc	2917	*/
AnnaBridge	171:3a7713b1edbc	2918	__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2919	{
AnnaBridge	171:3a7713b1edbc	2920	CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
AnnaBridge	171:3a7713b1edbc	2921	}
AnnaBridge	171:3a7713b1edbc	2922
AnnaBridge	171:3a7713b1edbc	2923	/**
AnnaBridge	171:3a7713b1edbc	2924	* @brief Indicates whether outputs are enabled.
AnnaBridge	171:3a7713b1edbc	2925	* @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	2926	* a timer instance provides a break input.
AnnaBridge	171:3a7713b1edbc	2927	* @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
AnnaBridge	171:3a7713b1edbc	2928	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2929	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	2930	*/
AnnaBridge	171:3a7713b1edbc	2931	__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	2932	{
AnnaBridge	171:3a7713b1edbc	2933	return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE));
AnnaBridge	171:3a7713b1edbc	2934	}
AnnaBridge	171:3a7713b1edbc	2935
AnnaBridge	171:3a7713b1edbc	2936	/**
AnnaBridge	171:3a7713b1edbc	2937	* @}
AnnaBridge	171:3a7713b1edbc	2938	*/
AnnaBridge	171:3a7713b1edbc	2939
AnnaBridge	171:3a7713b1edbc	2940	/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
AnnaBridge	171:3a7713b1edbc	2941	* @{
AnnaBridge	171:3a7713b1edbc	2942	*/
AnnaBridge	171:3a7713b1edbc	2943	/**
AnnaBridge	171:3a7713b1edbc	2944	* @brief Configures the timer DMA burst feature.
AnnaBridge	171:3a7713b1edbc	2945	* @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
AnnaBridge	171:3a7713b1edbc	2946	* not a timer instance supports the DMA burst mode.
AnnaBridge	171:3a7713b1edbc	2947	* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
AnnaBridge	171:3a7713b1edbc	2948	* DCR DBA LL_TIM_ConfigDMABurst
AnnaBridge	171:3a7713b1edbc	2949	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	2950	* @param DMABurstBaseAddress This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2951	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
AnnaBridge	171:3a7713b1edbc	2952	* @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
AnnaBridge	171:3a7713b1edbc	2953	* @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
AnnaBridge	171:3a7713b1edbc	2954	* @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
AnnaBridge	171:3a7713b1edbc	2955	* @arg @ref LL_TIM_DMABURST_BASEADDR_SR
AnnaBridge	171:3a7713b1edbc	2956	* @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
AnnaBridge	171:3a7713b1edbc	2957	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
AnnaBridge	171:3a7713b1edbc	2958	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
AnnaBridge	171:3a7713b1edbc	2959	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
AnnaBridge	171:3a7713b1edbc	2960	* @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
AnnaBridge	171:3a7713b1edbc	2961	* @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
AnnaBridge	171:3a7713b1edbc	2962	* @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
AnnaBridge	171:3a7713b1edbc	2963	* @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
AnnaBridge	171:3a7713b1edbc	2964	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
AnnaBridge	171:3a7713b1edbc	2965	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
AnnaBridge	171:3a7713b1edbc	2966	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
AnnaBridge	171:3a7713b1edbc	2967	* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
AnnaBridge	171:3a7713b1edbc	2968	* @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
AnnaBridge	171:3a7713b1edbc	2969	* @param DMABurstLength This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	2970	* @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
AnnaBridge	171:3a7713b1edbc	2971	* @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
AnnaBridge	171:3a7713b1edbc	2972	* @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
AnnaBridge	171:3a7713b1edbc	2973	* @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
AnnaBridge	171:3a7713b1edbc	2974	* @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
AnnaBridge	171:3a7713b1edbc	2975	* @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
AnnaBridge	171:3a7713b1edbc	2976	* @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
AnnaBridge	171:3a7713b1edbc	2977	* @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
AnnaBridge	171:3a7713b1edbc	2978	* @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
AnnaBridge	171:3a7713b1edbc	2979	* @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
AnnaBridge	171:3a7713b1edbc	2980	* @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
AnnaBridge	171:3a7713b1edbc	2981	* @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
AnnaBridge	171:3a7713b1edbc	2982	* @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
AnnaBridge	171:3a7713b1edbc	2983	* @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
AnnaBridge	171:3a7713b1edbc	2984	* @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
AnnaBridge	171:3a7713b1edbc	2985	* @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
AnnaBridge	171:3a7713b1edbc	2986	* @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
AnnaBridge	171:3a7713b1edbc	2987	* @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
AnnaBridge	171:3a7713b1edbc	2988	* @retval None
AnnaBridge	171:3a7713b1edbc	2989	*/
AnnaBridge	171:3a7713b1edbc	2990	__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
AnnaBridge	171:3a7713b1edbc	2991	{
AnnaBridge	171:3a7713b1edbc	2992	MODIFY_REG(TIMx->DCR, TIM_DCR_DBL \| TIM_DCR_DBA, DMABurstBaseAddress \| DMABurstLength);
AnnaBridge	171:3a7713b1edbc	2993	}
AnnaBridge	171:3a7713b1edbc	2994
AnnaBridge	171:3a7713b1edbc	2995	/**
AnnaBridge	171:3a7713b1edbc	2996	* @}
AnnaBridge	171:3a7713b1edbc	2997	*/
AnnaBridge	171:3a7713b1edbc	2998
AnnaBridge	171:3a7713b1edbc	2999	/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
AnnaBridge	171:3a7713b1edbc	3000	* @{
AnnaBridge	171:3a7713b1edbc	3001	*/
AnnaBridge	171:3a7713b1edbc	3002	/**
AnnaBridge	171:3a7713b1edbc	3003	* @brief Remap TIM inputs (input channel, internal/external triggers).
AnnaBridge	171:3a7713b1edbc	3004	* @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
AnnaBridge	171:3a7713b1edbc	3005	* a some timer inputs can be remapped.
AnnaBridge	171:3a7713b1edbc	3006	* @rmtoll TIM14_OR TI1_RMP LL_TIM_SetRemap
AnnaBridge	171:3a7713b1edbc	3007	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3008	* @param Remap This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	3009	* @arg @ref LL_TIM_TIM14_TI1_RMP_GPIO
AnnaBridge	171:3a7713b1edbc	3010	* @arg @ref LL_TIM_TIM14_TI1_RMP_RTC_CLK
AnnaBridge	171:3a7713b1edbc	3011	* @arg @ref LL_TIM_TIM14_TI1_RMP_HSE
AnnaBridge	171:3a7713b1edbc	3012	* @arg @ref LL_TIM_TIM14_TI1_RMP_MCO
AnnaBridge	171:3a7713b1edbc	3013	*
AnnaBridge	171:3a7713b1edbc	3014	* @retval None
AnnaBridge	171:3a7713b1edbc	3015	*/
AnnaBridge	171:3a7713b1edbc	3016	__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
AnnaBridge	171:3a7713b1edbc	3017	{
AnnaBridge	171:3a7713b1edbc	3018	MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
AnnaBridge	171:3a7713b1edbc	3019	}
AnnaBridge	171:3a7713b1edbc	3020
AnnaBridge	171:3a7713b1edbc	3021	/**
AnnaBridge	171:3a7713b1edbc	3022	* @}
AnnaBridge	171:3a7713b1edbc	3023	*/
AnnaBridge	171:3a7713b1edbc	3024
AnnaBridge	171:3a7713b1edbc	3025	/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
AnnaBridge	171:3a7713b1edbc	3026	* @{
AnnaBridge	171:3a7713b1edbc	3027	*/
AnnaBridge	171:3a7713b1edbc	3028	/**
AnnaBridge	171:3a7713b1edbc	3029	* @brief Set the OCREF clear input source
AnnaBridge	171:3a7713b1edbc	3030	* @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
AnnaBridge	171:3a7713b1edbc	3031	* @note This function can only be used in Output compare and PWM modes.
AnnaBridge	171:3a7713b1edbc	3032	* @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
AnnaBridge	171:3a7713b1edbc	3033	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3034	* @param OCRefClearInputSource This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	3035	* @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR
AnnaBridge	171:3a7713b1edbc	3036	* @arg @ref LL_TIM_OCREF_CLR_INT_ETR
AnnaBridge	171:3a7713b1edbc	3037	* @retval None
AnnaBridge	171:3a7713b1edbc	3038	*/
AnnaBridge	171:3a7713b1edbc	3039	__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
AnnaBridge	171:3a7713b1edbc	3040	{
AnnaBridge	171:3a7713b1edbc	3041	MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
AnnaBridge	171:3a7713b1edbc	3042	}
AnnaBridge	171:3a7713b1edbc	3043	/**
AnnaBridge	171:3a7713b1edbc	3044	* @}
AnnaBridge	171:3a7713b1edbc	3045	*/
AnnaBridge	171:3a7713b1edbc	3046
AnnaBridge	171:3a7713b1edbc	3047	/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
AnnaBridge	171:3a7713b1edbc	3048	* @{
AnnaBridge	171:3a7713b1edbc	3049	*/
AnnaBridge	171:3a7713b1edbc	3050	/**
AnnaBridge	171:3a7713b1edbc	3051	* @brief Clear the update interrupt flag (UIF).
AnnaBridge	171:3a7713b1edbc	3052	* @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
AnnaBridge	171:3a7713b1edbc	3053	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3054	* @retval None
AnnaBridge	171:3a7713b1edbc	3055	*/
AnnaBridge	171:3a7713b1edbc	3056	__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3057	{
AnnaBridge	171:3a7713b1edbc	3058	WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
AnnaBridge	171:3a7713b1edbc	3059	}
AnnaBridge	171:3a7713b1edbc	3060
AnnaBridge	171:3a7713b1edbc	3061	/**
AnnaBridge	171:3a7713b1edbc	3062	* @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
AnnaBridge	171:3a7713b1edbc	3063	* @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
AnnaBridge	171:3a7713b1edbc	3064	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3065	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3066	*/
AnnaBridge	171:3a7713b1edbc	3067	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3068	{
AnnaBridge	171:3a7713b1edbc	3069	return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
AnnaBridge	171:3a7713b1edbc	3070	}
AnnaBridge	171:3a7713b1edbc	3071
AnnaBridge	171:3a7713b1edbc	3072	/**
AnnaBridge	171:3a7713b1edbc	3073	* @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
AnnaBridge	171:3a7713b1edbc	3074	* @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
AnnaBridge	171:3a7713b1edbc	3075	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3076	* @retval None
AnnaBridge	171:3a7713b1edbc	3077	*/
AnnaBridge	171:3a7713b1edbc	3078	__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3079	{
AnnaBridge	171:3a7713b1edbc	3080	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
AnnaBridge	171:3a7713b1edbc	3081	}
AnnaBridge	171:3a7713b1edbc	3082
AnnaBridge	171:3a7713b1edbc	3083	/**
AnnaBridge	171:3a7713b1edbc	3084	* @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
AnnaBridge	171:3a7713b1edbc	3085	* @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
AnnaBridge	171:3a7713b1edbc	3086	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3087	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3088	*/
AnnaBridge	171:3a7713b1edbc	3089	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3090	{
AnnaBridge	171:3a7713b1edbc	3091	return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
AnnaBridge	171:3a7713b1edbc	3092	}
AnnaBridge	171:3a7713b1edbc	3093
AnnaBridge	171:3a7713b1edbc	3094	/**
AnnaBridge	171:3a7713b1edbc	3095	* @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
AnnaBridge	171:3a7713b1edbc	3096	* @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
AnnaBridge	171:3a7713b1edbc	3097	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3098	* @retval None
AnnaBridge	171:3a7713b1edbc	3099	*/
AnnaBridge	171:3a7713b1edbc	3100	__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3101	{
AnnaBridge	171:3a7713b1edbc	3102	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
AnnaBridge	171:3a7713b1edbc	3103	}
AnnaBridge	171:3a7713b1edbc	3104
AnnaBridge	171:3a7713b1edbc	3105	/**
AnnaBridge	171:3a7713b1edbc	3106	* @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
AnnaBridge	171:3a7713b1edbc	3107	* @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
AnnaBridge	171:3a7713b1edbc	3108	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3109	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3110	*/
AnnaBridge	171:3a7713b1edbc	3111	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3112	{
AnnaBridge	171:3a7713b1edbc	3113	return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
AnnaBridge	171:3a7713b1edbc	3114	}
AnnaBridge	171:3a7713b1edbc	3115
AnnaBridge	171:3a7713b1edbc	3116	/**
AnnaBridge	171:3a7713b1edbc	3117	* @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
AnnaBridge	171:3a7713b1edbc	3118	* @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
AnnaBridge	171:3a7713b1edbc	3119	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3120	* @retval None
AnnaBridge	171:3a7713b1edbc	3121	*/
AnnaBridge	171:3a7713b1edbc	3122	__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3123	{
AnnaBridge	171:3a7713b1edbc	3124	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
AnnaBridge	171:3a7713b1edbc	3125	}
AnnaBridge	171:3a7713b1edbc	3126
AnnaBridge	171:3a7713b1edbc	3127	/**
AnnaBridge	171:3a7713b1edbc	3128	* @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
AnnaBridge	171:3a7713b1edbc	3129	* @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
AnnaBridge	171:3a7713b1edbc	3130	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3131	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3132	*/
AnnaBridge	171:3a7713b1edbc	3133	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3134	{
AnnaBridge	171:3a7713b1edbc	3135	return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
AnnaBridge	171:3a7713b1edbc	3136	}
AnnaBridge	171:3a7713b1edbc	3137
AnnaBridge	171:3a7713b1edbc	3138	/**
AnnaBridge	171:3a7713b1edbc	3139	* @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
AnnaBridge	171:3a7713b1edbc	3140	* @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
AnnaBridge	171:3a7713b1edbc	3141	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3142	* @retval None
AnnaBridge	171:3a7713b1edbc	3143	*/
AnnaBridge	171:3a7713b1edbc	3144	__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3145	{
AnnaBridge	171:3a7713b1edbc	3146	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
AnnaBridge	171:3a7713b1edbc	3147	}
AnnaBridge	171:3a7713b1edbc	3148
AnnaBridge	171:3a7713b1edbc	3149	/**
AnnaBridge	171:3a7713b1edbc	3150	* @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
AnnaBridge	171:3a7713b1edbc	3151	* @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
AnnaBridge	171:3a7713b1edbc	3152	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3153	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3154	*/
AnnaBridge	171:3a7713b1edbc	3155	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3156	{
AnnaBridge	171:3a7713b1edbc	3157	return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
AnnaBridge	171:3a7713b1edbc	3158	}
AnnaBridge	171:3a7713b1edbc	3159
AnnaBridge	171:3a7713b1edbc	3160	/**
AnnaBridge	171:3a7713b1edbc	3161	* @brief Clear the commutation interrupt flag (COMIF).
AnnaBridge	171:3a7713b1edbc	3162	* @rmtoll SR COMIF LL_TIM_ClearFlag_COM
AnnaBridge	171:3a7713b1edbc	3163	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3164	* @retval None
AnnaBridge	171:3a7713b1edbc	3165	*/
AnnaBridge	171:3a7713b1edbc	3166	__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3167	{
AnnaBridge	171:3a7713b1edbc	3168	WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
AnnaBridge	171:3a7713b1edbc	3169	}
AnnaBridge	171:3a7713b1edbc	3170
AnnaBridge	171:3a7713b1edbc	3171	/**
AnnaBridge	171:3a7713b1edbc	3172	* @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
AnnaBridge	171:3a7713b1edbc	3173	* @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
AnnaBridge	171:3a7713b1edbc	3174	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3175	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3176	*/
AnnaBridge	171:3a7713b1edbc	3177	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3178	{
AnnaBridge	171:3a7713b1edbc	3179	return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF));
AnnaBridge	171:3a7713b1edbc	3180	}
AnnaBridge	171:3a7713b1edbc	3181
AnnaBridge	171:3a7713b1edbc	3182	/**
AnnaBridge	171:3a7713b1edbc	3183	* @brief Clear the trigger interrupt flag (TIF).
AnnaBridge	171:3a7713b1edbc	3184	* @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
AnnaBridge	171:3a7713b1edbc	3185	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3186	* @retval None
AnnaBridge	171:3a7713b1edbc	3187	*/
AnnaBridge	171:3a7713b1edbc	3188	__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3189	{
AnnaBridge	171:3a7713b1edbc	3190	WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
AnnaBridge	171:3a7713b1edbc	3191	}
AnnaBridge	171:3a7713b1edbc	3192
AnnaBridge	171:3a7713b1edbc	3193	/**
AnnaBridge	171:3a7713b1edbc	3194	* @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
AnnaBridge	171:3a7713b1edbc	3195	* @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
AnnaBridge	171:3a7713b1edbc	3196	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3197	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3198	*/
AnnaBridge	171:3a7713b1edbc	3199	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3200	{
AnnaBridge	171:3a7713b1edbc	3201	return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
AnnaBridge	171:3a7713b1edbc	3202	}
AnnaBridge	171:3a7713b1edbc	3203
AnnaBridge	171:3a7713b1edbc	3204	/**
AnnaBridge	171:3a7713b1edbc	3205	* @brief Clear the break interrupt flag (BIF).
AnnaBridge	171:3a7713b1edbc	3206	* @rmtoll SR BIF LL_TIM_ClearFlag_BRK
AnnaBridge	171:3a7713b1edbc	3207	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3208	* @retval None
AnnaBridge	171:3a7713b1edbc	3209	*/
AnnaBridge	171:3a7713b1edbc	3210	__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3211	{
AnnaBridge	171:3a7713b1edbc	3212	WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
AnnaBridge	171:3a7713b1edbc	3213	}
AnnaBridge	171:3a7713b1edbc	3214
AnnaBridge	171:3a7713b1edbc	3215	/**
AnnaBridge	171:3a7713b1edbc	3216	* @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
AnnaBridge	171:3a7713b1edbc	3217	* @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
AnnaBridge	171:3a7713b1edbc	3218	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3219	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3220	*/
AnnaBridge	171:3a7713b1edbc	3221	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3222	{
AnnaBridge	171:3a7713b1edbc	3223	return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF));
AnnaBridge	171:3a7713b1edbc	3224	}
AnnaBridge	171:3a7713b1edbc	3225
AnnaBridge	171:3a7713b1edbc	3226	/**
AnnaBridge	171:3a7713b1edbc	3227	* @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
AnnaBridge	171:3a7713b1edbc	3228	* @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
AnnaBridge	171:3a7713b1edbc	3229	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3230	* @retval None
AnnaBridge	171:3a7713b1edbc	3231	*/
AnnaBridge	171:3a7713b1edbc	3232	__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3233	{
AnnaBridge	171:3a7713b1edbc	3234	WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
AnnaBridge	171:3a7713b1edbc	3235	}
AnnaBridge	171:3a7713b1edbc	3236
AnnaBridge	171:3a7713b1edbc	3237	/**
AnnaBridge	171:3a7713b1edbc	3238	* @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
AnnaBridge	171:3a7713b1edbc	3239	* @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
AnnaBridge	171:3a7713b1edbc	3240	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3241	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3242	*/
AnnaBridge	171:3a7713b1edbc	3243	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3244	{
AnnaBridge	171:3a7713b1edbc	3245	return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
AnnaBridge	171:3a7713b1edbc	3246	}
AnnaBridge	171:3a7713b1edbc	3247
AnnaBridge	171:3a7713b1edbc	3248	/**
AnnaBridge	171:3a7713b1edbc	3249	* @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
AnnaBridge	171:3a7713b1edbc	3250	* @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
AnnaBridge	171:3a7713b1edbc	3251	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3252	* @retval None
AnnaBridge	171:3a7713b1edbc	3253	*/
AnnaBridge	171:3a7713b1edbc	3254	__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3255	{
AnnaBridge	171:3a7713b1edbc	3256	WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
AnnaBridge	171:3a7713b1edbc	3257	}
AnnaBridge	171:3a7713b1edbc	3258
AnnaBridge	171:3a7713b1edbc	3259	/**
AnnaBridge	171:3a7713b1edbc	3260	* @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
AnnaBridge	171:3a7713b1edbc	3261	* @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
AnnaBridge	171:3a7713b1edbc	3262	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3263	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3264	*/
AnnaBridge	171:3a7713b1edbc	3265	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3266	{
AnnaBridge	171:3a7713b1edbc	3267	return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
AnnaBridge	171:3a7713b1edbc	3268	}
AnnaBridge	171:3a7713b1edbc	3269
AnnaBridge	171:3a7713b1edbc	3270	/**
AnnaBridge	171:3a7713b1edbc	3271	* @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
AnnaBridge	171:3a7713b1edbc	3272	* @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
AnnaBridge	171:3a7713b1edbc	3273	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3274	* @retval None
AnnaBridge	171:3a7713b1edbc	3275	*/
AnnaBridge	171:3a7713b1edbc	3276	__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3277	{
AnnaBridge	171:3a7713b1edbc	3278	WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
AnnaBridge	171:3a7713b1edbc	3279	}
AnnaBridge	171:3a7713b1edbc	3280
AnnaBridge	171:3a7713b1edbc	3281	/**
AnnaBridge	171:3a7713b1edbc	3282	* @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
AnnaBridge	171:3a7713b1edbc	3283	* @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
AnnaBridge	171:3a7713b1edbc	3284	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3285	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3286	*/
AnnaBridge	171:3a7713b1edbc	3287	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3288	{
AnnaBridge	171:3a7713b1edbc	3289	return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
AnnaBridge	171:3a7713b1edbc	3290	}
AnnaBridge	171:3a7713b1edbc	3291
AnnaBridge	171:3a7713b1edbc	3292	/**
AnnaBridge	171:3a7713b1edbc	3293	* @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
AnnaBridge	171:3a7713b1edbc	3294	* @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
AnnaBridge	171:3a7713b1edbc	3295	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3296	* @retval None
AnnaBridge	171:3a7713b1edbc	3297	*/
AnnaBridge	171:3a7713b1edbc	3298	__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3299	{
AnnaBridge	171:3a7713b1edbc	3300	WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
AnnaBridge	171:3a7713b1edbc	3301	}
AnnaBridge	171:3a7713b1edbc	3302
AnnaBridge	171:3a7713b1edbc	3303	/**
AnnaBridge	171:3a7713b1edbc	3304	* @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
AnnaBridge	171:3a7713b1edbc	3305	* @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
AnnaBridge	171:3a7713b1edbc	3306	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3307	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3308	*/
AnnaBridge	171:3a7713b1edbc	3309	__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3310	{
AnnaBridge	171:3a7713b1edbc	3311	return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
AnnaBridge	171:3a7713b1edbc	3312	}
AnnaBridge	171:3a7713b1edbc	3313
AnnaBridge	171:3a7713b1edbc	3314	/**
AnnaBridge	171:3a7713b1edbc	3315	* @}
AnnaBridge	171:3a7713b1edbc	3316	*/
AnnaBridge	171:3a7713b1edbc	3317
AnnaBridge	171:3a7713b1edbc	3318	/** @defgroup TIM_LL_EF_IT_Management IT-Management
AnnaBridge	171:3a7713b1edbc	3319	* @{
AnnaBridge	171:3a7713b1edbc	3320	*/
AnnaBridge	171:3a7713b1edbc	3321	/**
AnnaBridge	171:3a7713b1edbc	3322	* @brief Enable update interrupt (UIE).
AnnaBridge	171:3a7713b1edbc	3323	* @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
AnnaBridge	171:3a7713b1edbc	3324	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3325	* @retval None
AnnaBridge	171:3a7713b1edbc	3326	*/
AnnaBridge	171:3a7713b1edbc	3327	__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3328	{
AnnaBridge	171:3a7713b1edbc	3329	SET_BIT(TIMx->DIER, TIM_DIER_UIE);
AnnaBridge	171:3a7713b1edbc	3330	}
AnnaBridge	171:3a7713b1edbc	3331
AnnaBridge	171:3a7713b1edbc	3332	/**
AnnaBridge	171:3a7713b1edbc	3333	* @brief Disable update interrupt (UIE).
AnnaBridge	171:3a7713b1edbc	3334	* @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
AnnaBridge	171:3a7713b1edbc	3335	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3336	* @retval None
AnnaBridge	171:3a7713b1edbc	3337	*/
AnnaBridge	171:3a7713b1edbc	3338	__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3339	{
AnnaBridge	171:3a7713b1edbc	3340	CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
AnnaBridge	171:3a7713b1edbc	3341	}
AnnaBridge	171:3a7713b1edbc	3342
AnnaBridge	171:3a7713b1edbc	3343	/**
AnnaBridge	171:3a7713b1edbc	3344	* @brief Indicates whether the update interrupt (UIE) is enabled.
AnnaBridge	171:3a7713b1edbc	3345	* @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
AnnaBridge	171:3a7713b1edbc	3346	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3347	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3348	*/
AnnaBridge	171:3a7713b1edbc	3349	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3350	{
AnnaBridge	171:3a7713b1edbc	3351	return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
AnnaBridge	171:3a7713b1edbc	3352	}
AnnaBridge	171:3a7713b1edbc	3353
AnnaBridge	171:3a7713b1edbc	3354	/**
AnnaBridge	171:3a7713b1edbc	3355	* @brief Enable capture/compare 1 interrupt (CC1IE).
AnnaBridge	171:3a7713b1edbc	3356	* @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
AnnaBridge	171:3a7713b1edbc	3357	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3358	* @retval None
AnnaBridge	171:3a7713b1edbc	3359	*/
AnnaBridge	171:3a7713b1edbc	3360	__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3361	{
AnnaBridge	171:3a7713b1edbc	3362	SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
AnnaBridge	171:3a7713b1edbc	3363	}
AnnaBridge	171:3a7713b1edbc	3364
AnnaBridge	171:3a7713b1edbc	3365	/**
AnnaBridge	171:3a7713b1edbc	3366	* @brief Disable capture/compare 1 interrupt (CC1IE).
AnnaBridge	171:3a7713b1edbc	3367	* @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
AnnaBridge	171:3a7713b1edbc	3368	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3369	* @retval None
AnnaBridge	171:3a7713b1edbc	3370	*/
AnnaBridge	171:3a7713b1edbc	3371	__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3372	{
AnnaBridge	171:3a7713b1edbc	3373	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
AnnaBridge	171:3a7713b1edbc	3374	}
AnnaBridge	171:3a7713b1edbc	3375
AnnaBridge	171:3a7713b1edbc	3376	/**
AnnaBridge	171:3a7713b1edbc	3377	* @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
AnnaBridge	171:3a7713b1edbc	3378	* @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
AnnaBridge	171:3a7713b1edbc	3379	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3380	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3381	*/
AnnaBridge	171:3a7713b1edbc	3382	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3383	{
AnnaBridge	171:3a7713b1edbc	3384	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
AnnaBridge	171:3a7713b1edbc	3385	}
AnnaBridge	171:3a7713b1edbc	3386
AnnaBridge	171:3a7713b1edbc	3387	/**
AnnaBridge	171:3a7713b1edbc	3388	* @brief Enable capture/compare 2 interrupt (CC2IE).
AnnaBridge	171:3a7713b1edbc	3389	* @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
AnnaBridge	171:3a7713b1edbc	3390	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3391	* @retval None
AnnaBridge	171:3a7713b1edbc	3392	*/
AnnaBridge	171:3a7713b1edbc	3393	__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3394	{
AnnaBridge	171:3a7713b1edbc	3395	SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
AnnaBridge	171:3a7713b1edbc	3396	}
AnnaBridge	171:3a7713b1edbc	3397
AnnaBridge	171:3a7713b1edbc	3398	/**
AnnaBridge	171:3a7713b1edbc	3399	* @brief Disable capture/compare 2 interrupt (CC2IE).
AnnaBridge	171:3a7713b1edbc	3400	* @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
AnnaBridge	171:3a7713b1edbc	3401	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3402	* @retval None
AnnaBridge	171:3a7713b1edbc	3403	*/
AnnaBridge	171:3a7713b1edbc	3404	__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3405	{
AnnaBridge	171:3a7713b1edbc	3406	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
AnnaBridge	171:3a7713b1edbc	3407	}
AnnaBridge	171:3a7713b1edbc	3408
AnnaBridge	171:3a7713b1edbc	3409	/**
AnnaBridge	171:3a7713b1edbc	3410	* @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
AnnaBridge	171:3a7713b1edbc	3411	* @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
AnnaBridge	171:3a7713b1edbc	3412	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3413	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3414	*/
AnnaBridge	171:3a7713b1edbc	3415	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3416	{
AnnaBridge	171:3a7713b1edbc	3417	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
AnnaBridge	171:3a7713b1edbc	3418	}
AnnaBridge	171:3a7713b1edbc	3419
AnnaBridge	171:3a7713b1edbc	3420	/**
AnnaBridge	171:3a7713b1edbc	3421	* @brief Enable capture/compare 3 interrupt (CC3IE).
AnnaBridge	171:3a7713b1edbc	3422	* @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
AnnaBridge	171:3a7713b1edbc	3423	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3424	* @retval None
AnnaBridge	171:3a7713b1edbc	3425	*/
AnnaBridge	171:3a7713b1edbc	3426	__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3427	{
AnnaBridge	171:3a7713b1edbc	3428	SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
AnnaBridge	171:3a7713b1edbc	3429	}
AnnaBridge	171:3a7713b1edbc	3430
AnnaBridge	171:3a7713b1edbc	3431	/**
AnnaBridge	171:3a7713b1edbc	3432	* @brief Disable capture/compare 3 interrupt (CC3IE).
AnnaBridge	171:3a7713b1edbc	3433	* @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
AnnaBridge	171:3a7713b1edbc	3434	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3435	* @retval None
AnnaBridge	171:3a7713b1edbc	3436	*/
AnnaBridge	171:3a7713b1edbc	3437	__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3438	{
AnnaBridge	171:3a7713b1edbc	3439	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
AnnaBridge	171:3a7713b1edbc	3440	}
AnnaBridge	171:3a7713b1edbc	3441
AnnaBridge	171:3a7713b1edbc	3442	/**
AnnaBridge	171:3a7713b1edbc	3443	* @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
AnnaBridge	171:3a7713b1edbc	3444	* @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
AnnaBridge	171:3a7713b1edbc	3445	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3446	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3447	*/
AnnaBridge	171:3a7713b1edbc	3448	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3449	{
AnnaBridge	171:3a7713b1edbc	3450	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
AnnaBridge	171:3a7713b1edbc	3451	}
AnnaBridge	171:3a7713b1edbc	3452
AnnaBridge	171:3a7713b1edbc	3453	/**
AnnaBridge	171:3a7713b1edbc	3454	* @brief Enable capture/compare 4 interrupt (CC4IE).
AnnaBridge	171:3a7713b1edbc	3455	* @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
AnnaBridge	171:3a7713b1edbc	3456	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3457	* @retval None
AnnaBridge	171:3a7713b1edbc	3458	*/
AnnaBridge	171:3a7713b1edbc	3459	__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3460	{
AnnaBridge	171:3a7713b1edbc	3461	SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
AnnaBridge	171:3a7713b1edbc	3462	}
AnnaBridge	171:3a7713b1edbc	3463
AnnaBridge	171:3a7713b1edbc	3464	/**
AnnaBridge	171:3a7713b1edbc	3465	* @brief Disable capture/compare 4 interrupt (CC4IE).
AnnaBridge	171:3a7713b1edbc	3466	* @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
AnnaBridge	171:3a7713b1edbc	3467	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3468	* @retval None
AnnaBridge	171:3a7713b1edbc	3469	*/
AnnaBridge	171:3a7713b1edbc	3470	__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3471	{
AnnaBridge	171:3a7713b1edbc	3472	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
AnnaBridge	171:3a7713b1edbc	3473	}
AnnaBridge	171:3a7713b1edbc	3474
AnnaBridge	171:3a7713b1edbc	3475	/**
AnnaBridge	171:3a7713b1edbc	3476	* @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
AnnaBridge	171:3a7713b1edbc	3477	* @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
AnnaBridge	171:3a7713b1edbc	3478	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3479	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3480	*/
AnnaBridge	171:3a7713b1edbc	3481	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3482	{
AnnaBridge	171:3a7713b1edbc	3483	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
AnnaBridge	171:3a7713b1edbc	3484	}
AnnaBridge	171:3a7713b1edbc	3485
AnnaBridge	171:3a7713b1edbc	3486	/**
AnnaBridge	171:3a7713b1edbc	3487	* @brief Enable commutation interrupt (COMIE).
AnnaBridge	171:3a7713b1edbc	3488	* @rmtoll DIER COMIE LL_TIM_EnableIT_COM
AnnaBridge	171:3a7713b1edbc	3489	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3490	* @retval None
AnnaBridge	171:3a7713b1edbc	3491	*/
AnnaBridge	171:3a7713b1edbc	3492	__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3493	{
AnnaBridge	171:3a7713b1edbc	3494	SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
AnnaBridge	171:3a7713b1edbc	3495	}
AnnaBridge	171:3a7713b1edbc	3496
AnnaBridge	171:3a7713b1edbc	3497	/**
AnnaBridge	171:3a7713b1edbc	3498	* @brief Disable commutation interrupt (COMIE).
AnnaBridge	171:3a7713b1edbc	3499	* @rmtoll DIER COMIE LL_TIM_DisableIT_COM
AnnaBridge	171:3a7713b1edbc	3500	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3501	* @retval None
AnnaBridge	171:3a7713b1edbc	3502	*/
AnnaBridge	171:3a7713b1edbc	3503	__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3504	{
AnnaBridge	171:3a7713b1edbc	3505	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
AnnaBridge	171:3a7713b1edbc	3506	}
AnnaBridge	171:3a7713b1edbc	3507
AnnaBridge	171:3a7713b1edbc	3508	/**
AnnaBridge	171:3a7713b1edbc	3509	* @brief Indicates whether the commutation interrupt (COMIE) is enabled.
AnnaBridge	171:3a7713b1edbc	3510	* @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
AnnaBridge	171:3a7713b1edbc	3511	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3512	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3513	*/
AnnaBridge	171:3a7713b1edbc	3514	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3515	{
AnnaBridge	171:3a7713b1edbc	3516	return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE));
AnnaBridge	171:3a7713b1edbc	3517	}
AnnaBridge	171:3a7713b1edbc	3518
AnnaBridge	171:3a7713b1edbc	3519	/**
AnnaBridge	171:3a7713b1edbc	3520	* @brief Enable trigger interrupt (TIE).
AnnaBridge	171:3a7713b1edbc	3521	* @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
AnnaBridge	171:3a7713b1edbc	3522	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3523	* @retval None
AnnaBridge	171:3a7713b1edbc	3524	*/
AnnaBridge	171:3a7713b1edbc	3525	__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3526	{
AnnaBridge	171:3a7713b1edbc	3527	SET_BIT(TIMx->DIER, TIM_DIER_TIE);
AnnaBridge	171:3a7713b1edbc	3528	}
AnnaBridge	171:3a7713b1edbc	3529
AnnaBridge	171:3a7713b1edbc	3530	/**
AnnaBridge	171:3a7713b1edbc	3531	* @brief Disable trigger interrupt (TIE).
AnnaBridge	171:3a7713b1edbc	3532	* @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
AnnaBridge	171:3a7713b1edbc	3533	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3534	* @retval None
AnnaBridge	171:3a7713b1edbc	3535	*/
AnnaBridge	171:3a7713b1edbc	3536	__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3537	{
AnnaBridge	171:3a7713b1edbc	3538	CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
AnnaBridge	171:3a7713b1edbc	3539	}
AnnaBridge	171:3a7713b1edbc	3540
AnnaBridge	171:3a7713b1edbc	3541	/**
AnnaBridge	171:3a7713b1edbc	3542	* @brief Indicates whether the trigger interrupt (TIE) is enabled.
AnnaBridge	171:3a7713b1edbc	3543	* @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
AnnaBridge	171:3a7713b1edbc	3544	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3545	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3546	*/
AnnaBridge	171:3a7713b1edbc	3547	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3548	{
AnnaBridge	171:3a7713b1edbc	3549	return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
AnnaBridge	171:3a7713b1edbc	3550	}
AnnaBridge	171:3a7713b1edbc	3551
AnnaBridge	171:3a7713b1edbc	3552	/**
AnnaBridge	171:3a7713b1edbc	3553	* @brief Enable break interrupt (BIE).
AnnaBridge	171:3a7713b1edbc	3554	* @rmtoll DIER BIE LL_TIM_EnableIT_BRK
AnnaBridge	171:3a7713b1edbc	3555	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3556	* @retval None
AnnaBridge	171:3a7713b1edbc	3557	*/
AnnaBridge	171:3a7713b1edbc	3558	__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3559	{
AnnaBridge	171:3a7713b1edbc	3560	SET_BIT(TIMx->DIER, TIM_DIER_BIE);
AnnaBridge	171:3a7713b1edbc	3561	}
AnnaBridge	171:3a7713b1edbc	3562
AnnaBridge	171:3a7713b1edbc	3563	/**
AnnaBridge	171:3a7713b1edbc	3564	* @brief Disable break interrupt (BIE).
AnnaBridge	171:3a7713b1edbc	3565	* @rmtoll DIER BIE LL_TIM_DisableIT_BRK
AnnaBridge	171:3a7713b1edbc	3566	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3567	* @retval None
AnnaBridge	171:3a7713b1edbc	3568	*/
AnnaBridge	171:3a7713b1edbc	3569	__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3570	{
AnnaBridge	171:3a7713b1edbc	3571	CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
AnnaBridge	171:3a7713b1edbc	3572	}
AnnaBridge	171:3a7713b1edbc	3573
AnnaBridge	171:3a7713b1edbc	3574	/**
AnnaBridge	171:3a7713b1edbc	3575	* @brief Indicates whether the break interrupt (BIE) is enabled.
AnnaBridge	171:3a7713b1edbc	3576	* @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
AnnaBridge	171:3a7713b1edbc	3577	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3578	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3579	*/
AnnaBridge	171:3a7713b1edbc	3580	__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3581	{
AnnaBridge	171:3a7713b1edbc	3582	return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE));
AnnaBridge	171:3a7713b1edbc	3583	}
AnnaBridge	171:3a7713b1edbc	3584
AnnaBridge	171:3a7713b1edbc	3585	/**
AnnaBridge	171:3a7713b1edbc	3586	* @}
AnnaBridge	171:3a7713b1edbc	3587	*/
AnnaBridge	171:3a7713b1edbc	3588
AnnaBridge	171:3a7713b1edbc	3589	/** @defgroup TIM_LL_EF_DMA_Management DMA-Management
AnnaBridge	171:3a7713b1edbc	3590	* @{
AnnaBridge	171:3a7713b1edbc	3591	*/
AnnaBridge	171:3a7713b1edbc	3592	/**
AnnaBridge	171:3a7713b1edbc	3593	* @brief Enable update DMA request (UDE).
AnnaBridge	171:3a7713b1edbc	3594	* @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
AnnaBridge	171:3a7713b1edbc	3595	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3596	* @retval None
AnnaBridge	171:3a7713b1edbc	3597	*/
AnnaBridge	171:3a7713b1edbc	3598	__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3599	{
AnnaBridge	171:3a7713b1edbc	3600	SET_BIT(TIMx->DIER, TIM_DIER_UDE);
AnnaBridge	171:3a7713b1edbc	3601	}
AnnaBridge	171:3a7713b1edbc	3602
AnnaBridge	171:3a7713b1edbc	3603	/**
AnnaBridge	171:3a7713b1edbc	3604	* @brief Disable update DMA request (UDE).
AnnaBridge	171:3a7713b1edbc	3605	* @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
AnnaBridge	171:3a7713b1edbc	3606	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3607	* @retval None
AnnaBridge	171:3a7713b1edbc	3608	*/
AnnaBridge	171:3a7713b1edbc	3609	__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3610	{
AnnaBridge	171:3a7713b1edbc	3611	CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
AnnaBridge	171:3a7713b1edbc	3612	}
AnnaBridge	171:3a7713b1edbc	3613
AnnaBridge	171:3a7713b1edbc	3614	/**
AnnaBridge	171:3a7713b1edbc	3615	* @brief Indicates whether the update DMA request (UDE) is enabled.
AnnaBridge	171:3a7713b1edbc	3616	* @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
AnnaBridge	171:3a7713b1edbc	3617	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3618	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3619	*/
AnnaBridge	171:3a7713b1edbc	3620	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3621	{
AnnaBridge	171:3a7713b1edbc	3622	return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
AnnaBridge	171:3a7713b1edbc	3623	}
AnnaBridge	171:3a7713b1edbc	3624
AnnaBridge	171:3a7713b1edbc	3625	/**
AnnaBridge	171:3a7713b1edbc	3626	* @brief Enable capture/compare 1 DMA request (CC1DE).
AnnaBridge	171:3a7713b1edbc	3627	* @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
AnnaBridge	171:3a7713b1edbc	3628	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3629	* @retval None
AnnaBridge	171:3a7713b1edbc	3630	*/
AnnaBridge	171:3a7713b1edbc	3631	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3632	{
AnnaBridge	171:3a7713b1edbc	3633	SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
AnnaBridge	171:3a7713b1edbc	3634	}
AnnaBridge	171:3a7713b1edbc	3635
AnnaBridge	171:3a7713b1edbc	3636	/**
AnnaBridge	171:3a7713b1edbc	3637	* @brief Disable capture/compare 1 DMA request (CC1DE).
AnnaBridge	171:3a7713b1edbc	3638	* @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
AnnaBridge	171:3a7713b1edbc	3639	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3640	* @retval None
AnnaBridge	171:3a7713b1edbc	3641	*/
AnnaBridge	171:3a7713b1edbc	3642	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3643	{
AnnaBridge	171:3a7713b1edbc	3644	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
AnnaBridge	171:3a7713b1edbc	3645	}
AnnaBridge	171:3a7713b1edbc	3646
AnnaBridge	171:3a7713b1edbc	3647	/**
AnnaBridge	171:3a7713b1edbc	3648	* @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
AnnaBridge	171:3a7713b1edbc	3649	* @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
AnnaBridge	171:3a7713b1edbc	3650	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3651	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3652	*/
AnnaBridge	171:3a7713b1edbc	3653	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3654	{
AnnaBridge	171:3a7713b1edbc	3655	return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
AnnaBridge	171:3a7713b1edbc	3656	}
AnnaBridge	171:3a7713b1edbc	3657
AnnaBridge	171:3a7713b1edbc	3658	/**
AnnaBridge	171:3a7713b1edbc	3659	* @brief Enable capture/compare 2 DMA request (CC2DE).
AnnaBridge	171:3a7713b1edbc	3660	* @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
AnnaBridge	171:3a7713b1edbc	3661	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3662	* @retval None
AnnaBridge	171:3a7713b1edbc	3663	*/
AnnaBridge	171:3a7713b1edbc	3664	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3665	{
AnnaBridge	171:3a7713b1edbc	3666	SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
AnnaBridge	171:3a7713b1edbc	3667	}
AnnaBridge	171:3a7713b1edbc	3668
AnnaBridge	171:3a7713b1edbc	3669	/**
AnnaBridge	171:3a7713b1edbc	3670	* @brief Disable capture/compare 2 DMA request (CC2DE).
AnnaBridge	171:3a7713b1edbc	3671	* @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
AnnaBridge	171:3a7713b1edbc	3672	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3673	* @retval None
AnnaBridge	171:3a7713b1edbc	3674	*/
AnnaBridge	171:3a7713b1edbc	3675	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3676	{
AnnaBridge	171:3a7713b1edbc	3677	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
AnnaBridge	171:3a7713b1edbc	3678	}
AnnaBridge	171:3a7713b1edbc	3679
AnnaBridge	171:3a7713b1edbc	3680	/**
AnnaBridge	171:3a7713b1edbc	3681	* @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
AnnaBridge	171:3a7713b1edbc	3682	* @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
AnnaBridge	171:3a7713b1edbc	3683	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3684	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3685	*/
AnnaBridge	171:3a7713b1edbc	3686	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3687	{
AnnaBridge	171:3a7713b1edbc	3688	return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
AnnaBridge	171:3a7713b1edbc	3689	}
AnnaBridge	171:3a7713b1edbc	3690
AnnaBridge	171:3a7713b1edbc	3691	/**
AnnaBridge	171:3a7713b1edbc	3692	* @brief Enable capture/compare 3 DMA request (CC3DE).
AnnaBridge	171:3a7713b1edbc	3693	* @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
AnnaBridge	171:3a7713b1edbc	3694	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3695	* @retval None
AnnaBridge	171:3a7713b1edbc	3696	*/
AnnaBridge	171:3a7713b1edbc	3697	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3698	{
AnnaBridge	171:3a7713b1edbc	3699	SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
AnnaBridge	171:3a7713b1edbc	3700	}
AnnaBridge	171:3a7713b1edbc	3701
AnnaBridge	171:3a7713b1edbc	3702	/**
AnnaBridge	171:3a7713b1edbc	3703	* @brief Disable capture/compare 3 DMA request (CC3DE).
AnnaBridge	171:3a7713b1edbc	3704	* @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
AnnaBridge	171:3a7713b1edbc	3705	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3706	* @retval None
AnnaBridge	171:3a7713b1edbc	3707	*/
AnnaBridge	171:3a7713b1edbc	3708	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3709	{
AnnaBridge	171:3a7713b1edbc	3710	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
AnnaBridge	171:3a7713b1edbc	3711	}
AnnaBridge	171:3a7713b1edbc	3712
AnnaBridge	171:3a7713b1edbc	3713	/**
AnnaBridge	171:3a7713b1edbc	3714	* @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
AnnaBridge	171:3a7713b1edbc	3715	* @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
AnnaBridge	171:3a7713b1edbc	3716	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3717	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3718	*/
AnnaBridge	171:3a7713b1edbc	3719	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3720	{
AnnaBridge	171:3a7713b1edbc	3721	return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
AnnaBridge	171:3a7713b1edbc	3722	}
AnnaBridge	171:3a7713b1edbc	3723
AnnaBridge	171:3a7713b1edbc	3724	/**
AnnaBridge	171:3a7713b1edbc	3725	* @brief Enable capture/compare 4 DMA request (CC4DE).
AnnaBridge	171:3a7713b1edbc	3726	* @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
AnnaBridge	171:3a7713b1edbc	3727	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3728	* @retval None
AnnaBridge	171:3a7713b1edbc	3729	*/
AnnaBridge	171:3a7713b1edbc	3730	__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3731	{
AnnaBridge	171:3a7713b1edbc	3732	SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
AnnaBridge	171:3a7713b1edbc	3733	}
AnnaBridge	171:3a7713b1edbc	3734
AnnaBridge	171:3a7713b1edbc	3735	/**
AnnaBridge	171:3a7713b1edbc	3736	* @brief Disable capture/compare 4 DMA request (CC4DE).
AnnaBridge	171:3a7713b1edbc	3737	* @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
AnnaBridge	171:3a7713b1edbc	3738	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3739	* @retval None
AnnaBridge	171:3a7713b1edbc	3740	*/
AnnaBridge	171:3a7713b1edbc	3741	__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3742	{
AnnaBridge	171:3a7713b1edbc	3743	CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
AnnaBridge	171:3a7713b1edbc	3744	}
AnnaBridge	171:3a7713b1edbc	3745
AnnaBridge	171:3a7713b1edbc	3746	/**
AnnaBridge	171:3a7713b1edbc	3747	* @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
AnnaBridge	171:3a7713b1edbc	3748	* @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
AnnaBridge	171:3a7713b1edbc	3749	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3750	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3751	*/
AnnaBridge	171:3a7713b1edbc	3752	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3753	{
AnnaBridge	171:3a7713b1edbc	3754	return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
AnnaBridge	171:3a7713b1edbc	3755	}
AnnaBridge	171:3a7713b1edbc	3756
AnnaBridge	171:3a7713b1edbc	3757	/**
AnnaBridge	171:3a7713b1edbc	3758	* @brief Enable commutation DMA request (COMDE).
AnnaBridge	171:3a7713b1edbc	3759	* @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
AnnaBridge	171:3a7713b1edbc	3760	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3761	* @retval None
AnnaBridge	171:3a7713b1edbc	3762	*/
AnnaBridge	171:3a7713b1edbc	3763	__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3764	{
AnnaBridge	171:3a7713b1edbc	3765	SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
AnnaBridge	171:3a7713b1edbc	3766	}
AnnaBridge	171:3a7713b1edbc	3767
AnnaBridge	171:3a7713b1edbc	3768	/**
AnnaBridge	171:3a7713b1edbc	3769	* @brief Disable commutation DMA request (COMDE).
AnnaBridge	171:3a7713b1edbc	3770	* @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
AnnaBridge	171:3a7713b1edbc	3771	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3772	* @retval None
AnnaBridge	171:3a7713b1edbc	3773	*/
AnnaBridge	171:3a7713b1edbc	3774	__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3775	{
AnnaBridge	171:3a7713b1edbc	3776	CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
AnnaBridge	171:3a7713b1edbc	3777	}
AnnaBridge	171:3a7713b1edbc	3778
AnnaBridge	171:3a7713b1edbc	3779	/**
AnnaBridge	171:3a7713b1edbc	3780	* @brief Indicates whether the commutation DMA request (COMDE) is enabled.
AnnaBridge	171:3a7713b1edbc	3781	* @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
AnnaBridge	171:3a7713b1edbc	3782	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3783	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3784	*/
AnnaBridge	171:3a7713b1edbc	3785	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3786	{
AnnaBridge	171:3a7713b1edbc	3787	return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE));
AnnaBridge	171:3a7713b1edbc	3788	}
AnnaBridge	171:3a7713b1edbc	3789
AnnaBridge	171:3a7713b1edbc	3790	/**
AnnaBridge	171:3a7713b1edbc	3791	* @brief Enable trigger interrupt (TDE).
AnnaBridge	171:3a7713b1edbc	3792	* @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
AnnaBridge	171:3a7713b1edbc	3793	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3794	* @retval None
AnnaBridge	171:3a7713b1edbc	3795	*/
AnnaBridge	171:3a7713b1edbc	3796	__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3797	{
AnnaBridge	171:3a7713b1edbc	3798	SET_BIT(TIMx->DIER, TIM_DIER_TDE);
AnnaBridge	171:3a7713b1edbc	3799	}
AnnaBridge	171:3a7713b1edbc	3800
AnnaBridge	171:3a7713b1edbc	3801	/**
AnnaBridge	171:3a7713b1edbc	3802	* @brief Disable trigger interrupt (TDE).
AnnaBridge	171:3a7713b1edbc	3803	* @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
AnnaBridge	171:3a7713b1edbc	3804	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3805	* @retval None
AnnaBridge	171:3a7713b1edbc	3806	*/
AnnaBridge	171:3a7713b1edbc	3807	__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3808	{
AnnaBridge	171:3a7713b1edbc	3809	CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
AnnaBridge	171:3a7713b1edbc	3810	}
AnnaBridge	171:3a7713b1edbc	3811
AnnaBridge	171:3a7713b1edbc	3812	/**
AnnaBridge	171:3a7713b1edbc	3813	* @brief Indicates whether the trigger interrupt (TDE) is enabled.
AnnaBridge	171:3a7713b1edbc	3814	* @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
AnnaBridge	171:3a7713b1edbc	3815	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3816	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	3817	*/
AnnaBridge	171:3a7713b1edbc	3818	__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3819	{
AnnaBridge	171:3a7713b1edbc	3820	return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
AnnaBridge	171:3a7713b1edbc	3821	}
AnnaBridge	171:3a7713b1edbc	3822
AnnaBridge	171:3a7713b1edbc	3823	/**
AnnaBridge	171:3a7713b1edbc	3824	* @}
AnnaBridge	171:3a7713b1edbc	3825	*/
AnnaBridge	171:3a7713b1edbc	3826
AnnaBridge	171:3a7713b1edbc	3827	/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
AnnaBridge	171:3a7713b1edbc	3828	* @{
AnnaBridge	171:3a7713b1edbc	3829	*/
AnnaBridge	171:3a7713b1edbc	3830	/**
AnnaBridge	171:3a7713b1edbc	3831	* @brief Generate an update event.
AnnaBridge	171:3a7713b1edbc	3832	* @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
AnnaBridge	171:3a7713b1edbc	3833	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3834	* @retval None
AnnaBridge	171:3a7713b1edbc	3835	*/
AnnaBridge	171:3a7713b1edbc	3836	__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3837	{
AnnaBridge	171:3a7713b1edbc	3838	SET_BIT(TIMx->EGR, TIM_EGR_UG);
AnnaBridge	171:3a7713b1edbc	3839	}
AnnaBridge	171:3a7713b1edbc	3840
AnnaBridge	171:3a7713b1edbc	3841	/**
AnnaBridge	171:3a7713b1edbc	3842	* @brief Generate Capture/Compare 1 event.
AnnaBridge	171:3a7713b1edbc	3843	* @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
AnnaBridge	171:3a7713b1edbc	3844	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3845	* @retval None
AnnaBridge	171:3a7713b1edbc	3846	*/
AnnaBridge	171:3a7713b1edbc	3847	__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3848	{
AnnaBridge	171:3a7713b1edbc	3849	SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
AnnaBridge	171:3a7713b1edbc	3850	}
AnnaBridge	171:3a7713b1edbc	3851
AnnaBridge	171:3a7713b1edbc	3852	/**
AnnaBridge	171:3a7713b1edbc	3853	* @brief Generate Capture/Compare 2 event.
AnnaBridge	171:3a7713b1edbc	3854	* @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
AnnaBridge	171:3a7713b1edbc	3855	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3856	* @retval None
AnnaBridge	171:3a7713b1edbc	3857	*/
AnnaBridge	171:3a7713b1edbc	3858	__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3859	{
AnnaBridge	171:3a7713b1edbc	3860	SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
AnnaBridge	171:3a7713b1edbc	3861	}
AnnaBridge	171:3a7713b1edbc	3862
AnnaBridge	171:3a7713b1edbc	3863	/**
AnnaBridge	171:3a7713b1edbc	3864	* @brief Generate Capture/Compare 3 event.
AnnaBridge	171:3a7713b1edbc	3865	* @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
AnnaBridge	171:3a7713b1edbc	3866	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3867	* @retval None
AnnaBridge	171:3a7713b1edbc	3868	*/
AnnaBridge	171:3a7713b1edbc	3869	__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3870	{
AnnaBridge	171:3a7713b1edbc	3871	SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
AnnaBridge	171:3a7713b1edbc	3872	}
AnnaBridge	171:3a7713b1edbc	3873
AnnaBridge	171:3a7713b1edbc	3874	/**
AnnaBridge	171:3a7713b1edbc	3875	* @brief Generate Capture/Compare 4 event.
AnnaBridge	171:3a7713b1edbc	3876	* @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
AnnaBridge	171:3a7713b1edbc	3877	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3878	* @retval None
AnnaBridge	171:3a7713b1edbc	3879	*/
AnnaBridge	171:3a7713b1edbc	3880	__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3881	{
AnnaBridge	171:3a7713b1edbc	3882	SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
AnnaBridge	171:3a7713b1edbc	3883	}
AnnaBridge	171:3a7713b1edbc	3884
AnnaBridge	171:3a7713b1edbc	3885	/**
AnnaBridge	171:3a7713b1edbc	3886	* @brief Generate commutation event.
AnnaBridge	171:3a7713b1edbc	3887	* @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
AnnaBridge	171:3a7713b1edbc	3888	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3889	* @retval None
AnnaBridge	171:3a7713b1edbc	3890	*/
AnnaBridge	171:3a7713b1edbc	3891	__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3892	{
AnnaBridge	171:3a7713b1edbc	3893	SET_BIT(TIMx->EGR, TIM_EGR_COMG);
AnnaBridge	171:3a7713b1edbc	3894	}
AnnaBridge	171:3a7713b1edbc	3895
AnnaBridge	171:3a7713b1edbc	3896	/**
AnnaBridge	171:3a7713b1edbc	3897	* @brief Generate trigger event.
AnnaBridge	171:3a7713b1edbc	3898	* @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
AnnaBridge	171:3a7713b1edbc	3899	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3900	* @retval None
AnnaBridge	171:3a7713b1edbc	3901	*/
AnnaBridge	171:3a7713b1edbc	3902	__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3903	{
AnnaBridge	171:3a7713b1edbc	3904	SET_BIT(TIMx->EGR, TIM_EGR_TG);
AnnaBridge	171:3a7713b1edbc	3905	}
AnnaBridge	171:3a7713b1edbc	3906
AnnaBridge	171:3a7713b1edbc	3907	/**
AnnaBridge	171:3a7713b1edbc	3908	* @brief Generate break event.
AnnaBridge	171:3a7713b1edbc	3909	* @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
AnnaBridge	171:3a7713b1edbc	3910	* @param TIMx Timer instance
AnnaBridge	171:3a7713b1edbc	3911	* @retval None
AnnaBridge	171:3a7713b1edbc	3912	*/
AnnaBridge	171:3a7713b1edbc	3913	__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
AnnaBridge	171:3a7713b1edbc	3914	{
AnnaBridge	171:3a7713b1edbc	3915	SET_BIT(TIMx->EGR, TIM_EGR_BG);
AnnaBridge	171:3a7713b1edbc	3916	}
AnnaBridge	171:3a7713b1edbc	3917
AnnaBridge	171:3a7713b1edbc	3918	/**
AnnaBridge	171:3a7713b1edbc	3919	* @}
AnnaBridge	171:3a7713b1edbc	3920	*/
AnnaBridge	171:3a7713b1edbc	3921
AnnaBridge	171:3a7713b1edbc	3922	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	171:3a7713b1edbc	3923	/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
AnnaBridge	171:3a7713b1edbc	3924	* @{
AnnaBridge	171:3a7713b1edbc	3925	*/
AnnaBridge	171:3a7713b1edbc	3926
AnnaBridge	171:3a7713b1edbc	3927	ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
AnnaBridge	171:3a7713b1edbc	3928	void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
AnnaBridge	171:3a7713b1edbc	3929	ErrorStatus LL_TIM_Init(TIM_TypeDef TIMx, LL_TIM_InitTypeDef TIM_InitStruct);
AnnaBridge	171:3a7713b1edbc	3930	void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
AnnaBridge	171:3a7713b1edbc	3931	ErrorStatus LL_TIM_OC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef TIM_OC_InitStruct);
AnnaBridge	171:3a7713b1edbc	3932	void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
AnnaBridge	171:3a7713b1edbc	3933	ErrorStatus LL_TIM_IC_Init(TIM_TypeDef TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef TIM_IC_InitStruct);
AnnaBridge	171:3a7713b1edbc	3934	void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
AnnaBridge	171:3a7713b1edbc	3935	ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef TIMx, LL_TIM_ENCODER_InitTypeDef TIM_EncoderInitStruct);
AnnaBridge	171:3a7713b1edbc	3936	void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
AnnaBridge	171:3a7713b1edbc	3937	ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef TIMx, LL_TIM_HALLSENSOR_InitTypeDef TIM_HallSensorInitStruct);
AnnaBridge	171:3a7713b1edbc	3938	void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
AnnaBridge	171:3a7713b1edbc	3939	ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef TIMx, LL_TIM_BDTR_InitTypeDef TIM_BDTRInitStruct);
AnnaBridge	171:3a7713b1edbc	3940	/**
AnnaBridge	171:3a7713b1edbc	3941	* @}
AnnaBridge	171:3a7713b1edbc	3942	*/
AnnaBridge	171:3a7713b1edbc	3943	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	171:3a7713b1edbc	3944
AnnaBridge	171:3a7713b1edbc	3945	/**
AnnaBridge	171:3a7713b1edbc	3946	* @}
AnnaBridge	171:3a7713b1edbc	3947	*/
AnnaBridge	171:3a7713b1edbc	3948
AnnaBridge	171:3a7713b1edbc	3949	/**
AnnaBridge	171:3a7713b1edbc	3950	* @}
AnnaBridge	171:3a7713b1edbc	3951	*/
AnnaBridge	171:3a7713b1edbc	3952
AnnaBridge	171:3a7713b1edbc	3953	#endif /* TIM1 \|\| TIM2 \|\| TIM3 \|\| TIM14 \|\| TIM15 \|\| TIM16 \|\| TIM17 \|\| TIM6 \|\| TIM7 */
AnnaBridge	171:3a7713b1edbc	3954
AnnaBridge	171:3a7713b1edbc	3955	/**
AnnaBridge	171:3a7713b1edbc	3956	* @}
AnnaBridge	171:3a7713b1edbc	3957	*/
AnnaBridge	171:3a7713b1edbc	3958
AnnaBridge	171:3a7713b1edbc	3959	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	3960	}
AnnaBridge	171:3a7713b1edbc	3961	#endif
AnnaBridge	171:3a7713b1edbc	3962
AnnaBridge	171:3a7713b1edbc	3963	#endif /* __STM32F0xx_LL_TIM_H */
AnnaBridge	171:3a7713b1edbc	3964	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/