mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F030R8/TOOLCHAIN_IAR/stm32f0xx_ll_crs.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file stm32f0xx_ll_crs.h
AnnaBridge 171:3a7713b1edbc 4 * @author MCD Application Team
AnnaBridge 171:3a7713b1edbc 5 * @brief Header file of CRS LL module.
AnnaBridge 171:3a7713b1edbc 6 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 7 * @attention
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 12 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 14 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 17 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 171:3a7713b1edbc 19 * may be used to endorse or promote products derived from this software
AnnaBridge 171:3a7713b1edbc 20 * without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 171:3a7713b1edbc 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 171:3a7713b1edbc 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 171:3a7713b1edbc 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 171:3a7713b1edbc 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 171:3a7713b1edbc 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 171:3a7713b1edbc 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 171:3a7713b1edbc 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 32 *
AnnaBridge 171:3a7713b1edbc 33 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 34 */
AnnaBridge 171:3a7713b1edbc 35
AnnaBridge 171:3a7713b1edbc 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 171:3a7713b1edbc 37 #ifndef __STM32F0xx_LL_CRS_H
AnnaBridge 171:3a7713b1edbc 38 #define __STM32F0xx_LL_CRS_H
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 41 extern "C" {
AnnaBridge 171:3a7713b1edbc 42 #endif
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 /* Includes ------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 45 #include "stm32f0xx.h"
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /** @addtogroup STM32F0xx_LL_Driver
AnnaBridge 171:3a7713b1edbc 48 * @{
AnnaBridge 171:3a7713b1edbc 49 */
AnnaBridge 171:3a7713b1edbc 50
AnnaBridge 171:3a7713b1edbc 51 #if defined(CRS)
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 /** @defgroup CRS_LL CRS
AnnaBridge 171:3a7713b1edbc 54 * @{
AnnaBridge 171:3a7713b1edbc 55 */
AnnaBridge 171:3a7713b1edbc 56
AnnaBridge 171:3a7713b1edbc 57 /* Private types -------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 58 /* Private variables ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 59 /* Private constants ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 60 /* Private macros ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 61
AnnaBridge 171:3a7713b1edbc 62 /* Exported types ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 63 /* Exported constants --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 64 /** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
AnnaBridge 171:3a7713b1edbc 65 * @{
AnnaBridge 171:3a7713b1edbc 66 */
AnnaBridge 171:3a7713b1edbc 67
AnnaBridge 171:3a7713b1edbc 68 /** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge 171:3a7713b1edbc 69 * @brief Flags defines which can be used with LL_CRS_ReadReg function
AnnaBridge 171:3a7713b1edbc 70 * @{
AnnaBridge 171:3a7713b1edbc 71 */
AnnaBridge 171:3a7713b1edbc 72 #define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
AnnaBridge 171:3a7713b1edbc 73 #define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
AnnaBridge 171:3a7713b1edbc 74 #define LL_CRS_ISR_ERRF CRS_ISR_ERRF
AnnaBridge 171:3a7713b1edbc 75 #define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
AnnaBridge 171:3a7713b1edbc 76 #define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
AnnaBridge 171:3a7713b1edbc 77 #define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
AnnaBridge 171:3a7713b1edbc 78 #define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF
AnnaBridge 171:3a7713b1edbc 79 /**
AnnaBridge 171:3a7713b1edbc 80 * @}
AnnaBridge 171:3a7713b1edbc 81 */
AnnaBridge 171:3a7713b1edbc 82
AnnaBridge 171:3a7713b1edbc 83 /** @defgroup CRS_LL_EC_IT IT Defines
AnnaBridge 171:3a7713b1edbc 84 * @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions
AnnaBridge 171:3a7713b1edbc 85 * @{
AnnaBridge 171:3a7713b1edbc 86 */
AnnaBridge 171:3a7713b1edbc 87 #define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
AnnaBridge 171:3a7713b1edbc 88 #define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
AnnaBridge 171:3a7713b1edbc 89 #define LL_CRS_CR_ERRIE CRS_CR_ERRIE
AnnaBridge 171:3a7713b1edbc 90 #define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE
AnnaBridge 171:3a7713b1edbc 91 /**
AnnaBridge 171:3a7713b1edbc 92 * @}
AnnaBridge 171:3a7713b1edbc 93 */
AnnaBridge 171:3a7713b1edbc 94
AnnaBridge 171:3a7713b1edbc 95 /** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
AnnaBridge 171:3a7713b1edbc 96 * @{
AnnaBridge 171:3a7713b1edbc 97 */
AnnaBridge 171:3a7713b1edbc 98 #define LL_CRS_SYNC_DIV_1 ((uint32_t)0x00U) /*!< Synchro Signal not divided (default) */
AnnaBridge 171:3a7713b1edbc 99 #define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
AnnaBridge 171:3a7713b1edbc 100 #define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
AnnaBridge 171:3a7713b1edbc 101 #define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
AnnaBridge 171:3a7713b1edbc 102 #define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
AnnaBridge 171:3a7713b1edbc 103 #define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
AnnaBridge 171:3a7713b1edbc 104 #define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
AnnaBridge 171:3a7713b1edbc 105 #define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
AnnaBridge 171:3a7713b1edbc 106 /**
AnnaBridge 171:3a7713b1edbc 107 * @}
AnnaBridge 171:3a7713b1edbc 108 */
AnnaBridge 171:3a7713b1edbc 109
AnnaBridge 171:3a7713b1edbc 110 /** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
AnnaBridge 171:3a7713b1edbc 111 * @{
AnnaBridge 171:3a7713b1edbc 112 */
AnnaBridge 171:3a7713b1edbc 113 #define LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal soucre GPIO */
AnnaBridge 171:3a7713b1edbc 114 #define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
AnnaBridge 171:3a7713b1edbc 115 #define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
AnnaBridge 171:3a7713b1edbc 116 /**
AnnaBridge 171:3a7713b1edbc 117 * @}
AnnaBridge 171:3a7713b1edbc 118 */
AnnaBridge 171:3a7713b1edbc 119
AnnaBridge 171:3a7713b1edbc 120 /** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
AnnaBridge 171:3a7713b1edbc 121 * @{
AnnaBridge 171:3a7713b1edbc 122 */
AnnaBridge 171:3a7713b1edbc 123 #define LL_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00U) /*!< Synchro Active on rising edge (default) */
AnnaBridge 171:3a7713b1edbc 124 #define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
AnnaBridge 171:3a7713b1edbc 125 /**
AnnaBridge 171:3a7713b1edbc 126 * @}
AnnaBridge 171:3a7713b1edbc 127 */
AnnaBridge 171:3a7713b1edbc 128
AnnaBridge 171:3a7713b1edbc 129 /** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
AnnaBridge 171:3a7713b1edbc 130 * @{
AnnaBridge 171:3a7713b1edbc 131 */
AnnaBridge 171:3a7713b1edbc 132 #define LL_CRS_FREQ_ERROR_DIR_UP ((uint32_t)0x00U) /*!< Upcounting direction, the actual frequency is above the target */
AnnaBridge 171:3a7713b1edbc 133 #define LL_CRS_FREQ_ERROR_DIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
AnnaBridge 171:3a7713b1edbc 134 /**
AnnaBridge 171:3a7713b1edbc 135 * @}
AnnaBridge 171:3a7713b1edbc 136 */
AnnaBridge 171:3a7713b1edbc 137
AnnaBridge 171:3a7713b1edbc 138 /** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
AnnaBridge 171:3a7713b1edbc 139 * @{
AnnaBridge 171:3a7713b1edbc 140 */
AnnaBridge 171:3a7713b1edbc 141 /**
AnnaBridge 171:3a7713b1edbc 142 * @brief Reset value of the RELOAD field
AnnaBridge 171:3a7713b1edbc 143 * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
AnnaBridge 171:3a7713b1edbc 144 * and a synchronization signal frequency of 1 kHz (SOF signal from USB)
AnnaBridge 171:3a7713b1edbc 145 */
AnnaBridge 171:3a7713b1edbc 146 #define LL_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU)
AnnaBridge 171:3a7713b1edbc 147
AnnaBridge 171:3a7713b1edbc 148 /**
AnnaBridge 171:3a7713b1edbc 149 * @brief Reset value of Frequency error limit.
AnnaBridge 171:3a7713b1edbc 150 */
AnnaBridge 171:3a7713b1edbc 151 #define LL_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U)
AnnaBridge 171:3a7713b1edbc 152
AnnaBridge 171:3a7713b1edbc 153 /**
AnnaBridge 171:3a7713b1edbc 154 * @brief Reset value of the HSI48 Calibration field
AnnaBridge 171:3a7713b1edbc 155 * @note The default value is 32, which corresponds to the middle of the trimming interval.
AnnaBridge 171:3a7713b1edbc 156 * The trimming step is around 67 kHz between two consecutive TRIM steps.
AnnaBridge 171:3a7713b1edbc 157 * A higher TRIM value corresponds to a higher output frequency
AnnaBridge 171:3a7713b1edbc 158 */
AnnaBridge 171:3a7713b1edbc 159 #define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20U)
AnnaBridge 171:3a7713b1edbc 160 /**
AnnaBridge 171:3a7713b1edbc 161 * @}
AnnaBridge 171:3a7713b1edbc 162 */
AnnaBridge 171:3a7713b1edbc 163
AnnaBridge 171:3a7713b1edbc 164 /**
AnnaBridge 171:3a7713b1edbc 165 * @}
AnnaBridge 171:3a7713b1edbc 166 */
AnnaBridge 171:3a7713b1edbc 167
AnnaBridge 171:3a7713b1edbc 168 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 169 /** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
AnnaBridge 171:3a7713b1edbc 170 * @{
AnnaBridge 171:3a7713b1edbc 171 */
AnnaBridge 171:3a7713b1edbc 172
AnnaBridge 171:3a7713b1edbc 173 /** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge 171:3a7713b1edbc 174 * @{
AnnaBridge 171:3a7713b1edbc 175 */
AnnaBridge 171:3a7713b1edbc 176
AnnaBridge 171:3a7713b1edbc 177 /**
AnnaBridge 171:3a7713b1edbc 178 * @brief Write a value in CRS register
AnnaBridge 171:3a7713b1edbc 179 * @param __INSTANCE__ CRS Instance
AnnaBridge 171:3a7713b1edbc 180 * @param __REG__ Register to be written
AnnaBridge 171:3a7713b1edbc 181 * @param __VALUE__ Value to be written in the register
AnnaBridge 171:3a7713b1edbc 182 * @retval None
AnnaBridge 171:3a7713b1edbc 183 */
AnnaBridge 171:3a7713b1edbc 184 #define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge 171:3a7713b1edbc 185
AnnaBridge 171:3a7713b1edbc 186 /**
AnnaBridge 171:3a7713b1edbc 187 * @brief Read a value in CRS register
AnnaBridge 171:3a7713b1edbc 188 * @param __INSTANCE__ CRS Instance
AnnaBridge 171:3a7713b1edbc 189 * @param __REG__ Register to be read
AnnaBridge 171:3a7713b1edbc 190 * @retval Register value
AnnaBridge 171:3a7713b1edbc 191 */
AnnaBridge 171:3a7713b1edbc 192 #define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge 171:3a7713b1edbc 193 /**
AnnaBridge 171:3a7713b1edbc 194 * @}
AnnaBridge 171:3a7713b1edbc 195 */
AnnaBridge 171:3a7713b1edbc 196
AnnaBridge 171:3a7713b1edbc 197 /** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
AnnaBridge 171:3a7713b1edbc 198 * @{
AnnaBridge 171:3a7713b1edbc 199 */
AnnaBridge 171:3a7713b1edbc 200
AnnaBridge 171:3a7713b1edbc 201 /**
AnnaBridge 171:3a7713b1edbc 202 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
AnnaBridge 171:3a7713b1edbc 203 * @note The RELOAD value should be selected according to the ratio between
AnnaBridge 171:3a7713b1edbc 204 * the target frequency and the frequency of the synchronization source after
AnnaBridge 171:3a7713b1edbc 205 * prescaling. It is then decreased by one in order to reach the expected
AnnaBridge 171:3a7713b1edbc 206 * synchronization on the zero value. The formula is the following:
AnnaBridge 171:3a7713b1edbc 207 * RELOAD = (fTARGET / fSYNC) -1
AnnaBridge 171:3a7713b1edbc 208 * @param __FTARGET__ Target frequency (value in Hz)
AnnaBridge 171:3a7713b1edbc 209 * @param __FSYNC__ Synchronization signal frequency (value in Hz)
AnnaBridge 171:3a7713b1edbc 210 * @retval Reload value (in Hz)
AnnaBridge 171:3a7713b1edbc 211 */
AnnaBridge 171:3a7713b1edbc 212 #define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
AnnaBridge 171:3a7713b1edbc 213
AnnaBridge 171:3a7713b1edbc 214 /**
AnnaBridge 171:3a7713b1edbc 215 * @}
AnnaBridge 171:3a7713b1edbc 216 */
AnnaBridge 171:3a7713b1edbc 217
AnnaBridge 171:3a7713b1edbc 218 /**
AnnaBridge 171:3a7713b1edbc 219 * @}
AnnaBridge 171:3a7713b1edbc 220 */
AnnaBridge 171:3a7713b1edbc 221
AnnaBridge 171:3a7713b1edbc 222 /* Exported functions --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 223 /** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
AnnaBridge 171:3a7713b1edbc 224 * @{
AnnaBridge 171:3a7713b1edbc 225 */
AnnaBridge 171:3a7713b1edbc 226
AnnaBridge 171:3a7713b1edbc 227 /** @defgroup CRS_LL_EF_Configuration Configuration
AnnaBridge 171:3a7713b1edbc 228 * @{
AnnaBridge 171:3a7713b1edbc 229 */
AnnaBridge 171:3a7713b1edbc 230
AnnaBridge 171:3a7713b1edbc 231 /**
AnnaBridge 171:3a7713b1edbc 232 * @brief Enable Frequency error counter
AnnaBridge 171:3a7713b1edbc 233 * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
AnnaBridge 171:3a7713b1edbc 234 * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter
AnnaBridge 171:3a7713b1edbc 235 * @retval None
AnnaBridge 171:3a7713b1edbc 236 */
AnnaBridge 171:3a7713b1edbc 237 __STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
AnnaBridge 171:3a7713b1edbc 238 {
AnnaBridge 171:3a7713b1edbc 239 SET_BIT(CRS->CR, CRS_CR_CEN);
AnnaBridge 171:3a7713b1edbc 240 }
AnnaBridge 171:3a7713b1edbc 241
AnnaBridge 171:3a7713b1edbc 242 /**
AnnaBridge 171:3a7713b1edbc 243 * @brief Disable Frequency error counter
AnnaBridge 171:3a7713b1edbc 244 * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter
AnnaBridge 171:3a7713b1edbc 245 * @retval None
AnnaBridge 171:3a7713b1edbc 246 */
AnnaBridge 171:3a7713b1edbc 247 __STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
AnnaBridge 171:3a7713b1edbc 248 {
AnnaBridge 171:3a7713b1edbc 249 CLEAR_BIT(CRS->CR, CRS_CR_CEN);
AnnaBridge 171:3a7713b1edbc 250 }
AnnaBridge 171:3a7713b1edbc 251
AnnaBridge 171:3a7713b1edbc 252 /**
AnnaBridge 171:3a7713b1edbc 253 * @brief Check if Frequency error counter is enabled or not
AnnaBridge 171:3a7713b1edbc 254 * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter
AnnaBridge 171:3a7713b1edbc 255 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 256 */
AnnaBridge 171:3a7713b1edbc 257 __STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
AnnaBridge 171:3a7713b1edbc 258 {
AnnaBridge 171:3a7713b1edbc 259 return (READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN));
AnnaBridge 171:3a7713b1edbc 260 }
AnnaBridge 171:3a7713b1edbc 261
AnnaBridge 171:3a7713b1edbc 262 /**
AnnaBridge 171:3a7713b1edbc 263 * @brief Enable Automatic trimming counter
AnnaBridge 171:3a7713b1edbc 264 * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming
AnnaBridge 171:3a7713b1edbc 265 * @retval None
AnnaBridge 171:3a7713b1edbc 266 */
AnnaBridge 171:3a7713b1edbc 267 __STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
AnnaBridge 171:3a7713b1edbc 268 {
AnnaBridge 171:3a7713b1edbc 269 SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
AnnaBridge 171:3a7713b1edbc 270 }
AnnaBridge 171:3a7713b1edbc 271
AnnaBridge 171:3a7713b1edbc 272 /**
AnnaBridge 171:3a7713b1edbc 273 * @brief Disable Automatic trimming counter
AnnaBridge 171:3a7713b1edbc 274 * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming
AnnaBridge 171:3a7713b1edbc 275 * @retval None
AnnaBridge 171:3a7713b1edbc 276 */
AnnaBridge 171:3a7713b1edbc 277 __STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
AnnaBridge 171:3a7713b1edbc 278 {
AnnaBridge 171:3a7713b1edbc 279 CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
AnnaBridge 171:3a7713b1edbc 280 }
AnnaBridge 171:3a7713b1edbc 281
AnnaBridge 171:3a7713b1edbc 282 /**
AnnaBridge 171:3a7713b1edbc 283 * @brief Check if Automatic trimming is enabled or not
AnnaBridge 171:3a7713b1edbc 284 * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming
AnnaBridge 171:3a7713b1edbc 285 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 286 */
AnnaBridge 171:3a7713b1edbc 287 __STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
AnnaBridge 171:3a7713b1edbc 288 {
AnnaBridge 171:3a7713b1edbc 289 return (READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN));
AnnaBridge 171:3a7713b1edbc 290 }
AnnaBridge 171:3a7713b1edbc 291
AnnaBridge 171:3a7713b1edbc 292 /**
AnnaBridge 171:3a7713b1edbc 293 * @brief Set HSI48 oscillator smooth trimming
AnnaBridge 171:3a7713b1edbc 294 * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
AnnaBridge 171:3a7713b1edbc 295 * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming
AnnaBridge 171:3a7713b1edbc 296 * @param Value a number between Min_Data = 0 and Max_Data = 63
AnnaBridge 171:3a7713b1edbc 297 * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
AnnaBridge 171:3a7713b1edbc 298 * @retval None
AnnaBridge 171:3a7713b1edbc 299 */
AnnaBridge 171:3a7713b1edbc 300 __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
AnnaBridge 171:3a7713b1edbc 301 {
AnnaBridge 171:3a7713b1edbc 302 MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos);
AnnaBridge 171:3a7713b1edbc 303 }
AnnaBridge 171:3a7713b1edbc 304
AnnaBridge 171:3a7713b1edbc 305 /**
AnnaBridge 171:3a7713b1edbc 306 * @brief Get HSI48 oscillator smooth trimming
AnnaBridge 171:3a7713b1edbc 307 * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming
AnnaBridge 171:3a7713b1edbc 308 * @retval a number between Min_Data = 0 and Max_Data = 63
AnnaBridge 171:3a7713b1edbc 309 */
AnnaBridge 171:3a7713b1edbc 310 __STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
AnnaBridge 171:3a7713b1edbc 311 {
AnnaBridge 171:3a7713b1edbc 312 return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
AnnaBridge 171:3a7713b1edbc 313 }
AnnaBridge 171:3a7713b1edbc 314
AnnaBridge 171:3a7713b1edbc 315 /**
AnnaBridge 171:3a7713b1edbc 316 * @brief Set counter reload value
AnnaBridge 171:3a7713b1edbc 317 * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter
AnnaBridge 171:3a7713b1edbc 318 * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF
AnnaBridge 171:3a7713b1edbc 319 * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
AnnaBridge 171:3a7713b1edbc 320 * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
AnnaBridge 171:3a7713b1edbc 321 * @retval None
AnnaBridge 171:3a7713b1edbc 322 */
AnnaBridge 171:3a7713b1edbc 323 __STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
AnnaBridge 171:3a7713b1edbc 324 {
AnnaBridge 171:3a7713b1edbc 325 MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
AnnaBridge 171:3a7713b1edbc 326 }
AnnaBridge 171:3a7713b1edbc 327
AnnaBridge 171:3a7713b1edbc 328 /**
AnnaBridge 171:3a7713b1edbc 329 * @brief Get counter reload value
AnnaBridge 171:3a7713b1edbc 330 * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter
AnnaBridge 171:3a7713b1edbc 331 * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
AnnaBridge 171:3a7713b1edbc 332 */
AnnaBridge 171:3a7713b1edbc 333 __STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
AnnaBridge 171:3a7713b1edbc 334 {
AnnaBridge 171:3a7713b1edbc 335 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
AnnaBridge 171:3a7713b1edbc 336 }
AnnaBridge 171:3a7713b1edbc 337
AnnaBridge 171:3a7713b1edbc 338 /**
AnnaBridge 171:3a7713b1edbc 339 * @brief Set frequency error limit
AnnaBridge 171:3a7713b1edbc 340 * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit
AnnaBridge 171:3a7713b1edbc 341 * @param Value a number between Min_Data = 0 and Max_Data = 255
AnnaBridge 171:3a7713b1edbc 342 * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
AnnaBridge 171:3a7713b1edbc 343 * @retval None
AnnaBridge 171:3a7713b1edbc 344 */
AnnaBridge 171:3a7713b1edbc 345 __STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
AnnaBridge 171:3a7713b1edbc 346 {
AnnaBridge 171:3a7713b1edbc 347 MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos);
AnnaBridge 171:3a7713b1edbc 348 }
AnnaBridge 171:3a7713b1edbc 349
AnnaBridge 171:3a7713b1edbc 350 /**
AnnaBridge 171:3a7713b1edbc 351 * @brief Get frequency error limit
AnnaBridge 171:3a7713b1edbc 352 * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit
AnnaBridge 171:3a7713b1edbc 353 * @retval A number between Min_Data = 0 and Max_Data = 255
AnnaBridge 171:3a7713b1edbc 354 */
AnnaBridge 171:3a7713b1edbc 355 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
AnnaBridge 171:3a7713b1edbc 356 {
AnnaBridge 171:3a7713b1edbc 357 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos);
AnnaBridge 171:3a7713b1edbc 358 }
AnnaBridge 171:3a7713b1edbc 359
AnnaBridge 171:3a7713b1edbc 360 /**
AnnaBridge 171:3a7713b1edbc 361 * @brief Set division factor for SYNC signal
AnnaBridge 171:3a7713b1edbc 362 * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider
AnnaBridge 171:3a7713b1edbc 363 * @param Divider This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 364 * @arg @ref LL_CRS_SYNC_DIV_1
AnnaBridge 171:3a7713b1edbc 365 * @arg @ref LL_CRS_SYNC_DIV_2
AnnaBridge 171:3a7713b1edbc 366 * @arg @ref LL_CRS_SYNC_DIV_4
AnnaBridge 171:3a7713b1edbc 367 * @arg @ref LL_CRS_SYNC_DIV_8
AnnaBridge 171:3a7713b1edbc 368 * @arg @ref LL_CRS_SYNC_DIV_16
AnnaBridge 171:3a7713b1edbc 369 * @arg @ref LL_CRS_SYNC_DIV_32
AnnaBridge 171:3a7713b1edbc 370 * @arg @ref LL_CRS_SYNC_DIV_64
AnnaBridge 171:3a7713b1edbc 371 * @arg @ref LL_CRS_SYNC_DIV_128
AnnaBridge 171:3a7713b1edbc 372 * @retval None
AnnaBridge 171:3a7713b1edbc 373 */
AnnaBridge 171:3a7713b1edbc 374 __STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
AnnaBridge 171:3a7713b1edbc 375 {
AnnaBridge 171:3a7713b1edbc 376 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
AnnaBridge 171:3a7713b1edbc 377 }
AnnaBridge 171:3a7713b1edbc 378
AnnaBridge 171:3a7713b1edbc 379 /**
AnnaBridge 171:3a7713b1edbc 380 * @brief Get division factor for SYNC signal
AnnaBridge 171:3a7713b1edbc 381 * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider
AnnaBridge 171:3a7713b1edbc 382 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 383 * @arg @ref LL_CRS_SYNC_DIV_1
AnnaBridge 171:3a7713b1edbc 384 * @arg @ref LL_CRS_SYNC_DIV_2
AnnaBridge 171:3a7713b1edbc 385 * @arg @ref LL_CRS_SYNC_DIV_4
AnnaBridge 171:3a7713b1edbc 386 * @arg @ref LL_CRS_SYNC_DIV_8
AnnaBridge 171:3a7713b1edbc 387 * @arg @ref LL_CRS_SYNC_DIV_16
AnnaBridge 171:3a7713b1edbc 388 * @arg @ref LL_CRS_SYNC_DIV_32
AnnaBridge 171:3a7713b1edbc 389 * @arg @ref LL_CRS_SYNC_DIV_64
AnnaBridge 171:3a7713b1edbc 390 * @arg @ref LL_CRS_SYNC_DIV_128
AnnaBridge 171:3a7713b1edbc 391 */
AnnaBridge 171:3a7713b1edbc 392 __STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
AnnaBridge 171:3a7713b1edbc 393 {
AnnaBridge 171:3a7713b1edbc 394 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
AnnaBridge 171:3a7713b1edbc 395 }
AnnaBridge 171:3a7713b1edbc 396
AnnaBridge 171:3a7713b1edbc 397 /**
AnnaBridge 171:3a7713b1edbc 398 * @brief Set SYNC signal source
AnnaBridge 171:3a7713b1edbc 399 * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource
AnnaBridge 171:3a7713b1edbc 400 * @param Source This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 401 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
AnnaBridge 171:3a7713b1edbc 402 * @arg @ref LL_CRS_SYNC_SOURCE_LSE
AnnaBridge 171:3a7713b1edbc 403 * @arg @ref LL_CRS_SYNC_SOURCE_USB
AnnaBridge 171:3a7713b1edbc 404 * @retval None
AnnaBridge 171:3a7713b1edbc 405 */
AnnaBridge 171:3a7713b1edbc 406 __STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
AnnaBridge 171:3a7713b1edbc 407 {
AnnaBridge 171:3a7713b1edbc 408 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
AnnaBridge 171:3a7713b1edbc 409 }
AnnaBridge 171:3a7713b1edbc 410
AnnaBridge 171:3a7713b1edbc 411 /**
AnnaBridge 171:3a7713b1edbc 412 * @brief Get SYNC signal source
AnnaBridge 171:3a7713b1edbc 413 * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource
AnnaBridge 171:3a7713b1edbc 414 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 415 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
AnnaBridge 171:3a7713b1edbc 416 * @arg @ref LL_CRS_SYNC_SOURCE_LSE
AnnaBridge 171:3a7713b1edbc 417 * @arg @ref LL_CRS_SYNC_SOURCE_USB
AnnaBridge 171:3a7713b1edbc 418 */
AnnaBridge 171:3a7713b1edbc 419 __STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
AnnaBridge 171:3a7713b1edbc 420 {
AnnaBridge 171:3a7713b1edbc 421 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
AnnaBridge 171:3a7713b1edbc 422 }
AnnaBridge 171:3a7713b1edbc 423
AnnaBridge 171:3a7713b1edbc 424 /**
AnnaBridge 171:3a7713b1edbc 425 * @brief Set input polarity for the SYNC signal source
AnnaBridge 171:3a7713b1edbc 426 * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity
AnnaBridge 171:3a7713b1edbc 427 * @param Polarity This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 428 * @arg @ref LL_CRS_SYNC_POLARITY_RISING
AnnaBridge 171:3a7713b1edbc 429 * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
AnnaBridge 171:3a7713b1edbc 430 * @retval None
AnnaBridge 171:3a7713b1edbc 431 */
AnnaBridge 171:3a7713b1edbc 432 __STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
AnnaBridge 171:3a7713b1edbc 433 {
AnnaBridge 171:3a7713b1edbc 434 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
AnnaBridge 171:3a7713b1edbc 435 }
AnnaBridge 171:3a7713b1edbc 436
AnnaBridge 171:3a7713b1edbc 437 /**
AnnaBridge 171:3a7713b1edbc 438 * @brief Get input polarity for the SYNC signal source
AnnaBridge 171:3a7713b1edbc 439 * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity
AnnaBridge 171:3a7713b1edbc 440 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 441 * @arg @ref LL_CRS_SYNC_POLARITY_RISING
AnnaBridge 171:3a7713b1edbc 442 * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
AnnaBridge 171:3a7713b1edbc 443 */
AnnaBridge 171:3a7713b1edbc 444 __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
AnnaBridge 171:3a7713b1edbc 445 {
AnnaBridge 171:3a7713b1edbc 446 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
AnnaBridge 171:3a7713b1edbc 447 }
AnnaBridge 171:3a7713b1edbc 448
AnnaBridge 171:3a7713b1edbc 449 /**
AnnaBridge 171:3a7713b1edbc 450 * @brief Configure CRS for the synchronization
AnnaBridge 171:3a7713b1edbc 451 * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n
AnnaBridge 171:3a7713b1edbc 452 * CFGR RELOAD LL_CRS_ConfigSynchronization\n
AnnaBridge 171:3a7713b1edbc 453 * CFGR FELIM LL_CRS_ConfigSynchronization\n
AnnaBridge 171:3a7713b1edbc 454 * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n
AnnaBridge 171:3a7713b1edbc 455 * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n
AnnaBridge 171:3a7713b1edbc 456 * CFGR SYNCPOL LL_CRS_ConfigSynchronization
AnnaBridge 171:3a7713b1edbc 457 * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
AnnaBridge 171:3a7713b1edbc 458 * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
AnnaBridge 171:3a7713b1edbc 459 * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255
AnnaBridge 171:3a7713b1edbc 460 * @param Settings This parameter can be a combination of the following values:
AnnaBridge 171:3a7713b1edbc 461 * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
AnnaBridge 171:3a7713b1edbc 462 * or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
AnnaBridge 171:3a7713b1edbc 463 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
AnnaBridge 171:3a7713b1edbc 464 * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
AnnaBridge 171:3a7713b1edbc 465 * @retval None
AnnaBridge 171:3a7713b1edbc 466 */
AnnaBridge 171:3a7713b1edbc 467 __STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
AnnaBridge 171:3a7713b1edbc 468 {
AnnaBridge 171:3a7713b1edbc 469 MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue << CRS_CR_TRIM_Pos);
AnnaBridge 171:3a7713b1edbc 470 MODIFY_REG(CRS->CFGR,
AnnaBridge 171:3a7713b1edbc 471 CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
AnnaBridge 171:3a7713b1edbc 472 ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings);
AnnaBridge 171:3a7713b1edbc 473 }
AnnaBridge 171:3a7713b1edbc 474
AnnaBridge 171:3a7713b1edbc 475 /**
AnnaBridge 171:3a7713b1edbc 476 * @}
AnnaBridge 171:3a7713b1edbc 477 */
AnnaBridge 171:3a7713b1edbc 478
AnnaBridge 171:3a7713b1edbc 479 /** @defgroup CRS_LL_EF_CRS_Management CRS_Management
AnnaBridge 171:3a7713b1edbc 480 * @{
AnnaBridge 171:3a7713b1edbc 481 */
AnnaBridge 171:3a7713b1edbc 482
AnnaBridge 171:3a7713b1edbc 483 /**
AnnaBridge 171:3a7713b1edbc 484 * @brief Generate software SYNC event
AnnaBridge 171:3a7713b1edbc 485 * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC
AnnaBridge 171:3a7713b1edbc 486 * @retval None
AnnaBridge 171:3a7713b1edbc 487 */
AnnaBridge 171:3a7713b1edbc 488 __STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
AnnaBridge 171:3a7713b1edbc 489 {
AnnaBridge 171:3a7713b1edbc 490 SET_BIT(CRS->CR, CRS_CR_SWSYNC);
AnnaBridge 171:3a7713b1edbc 491 }
AnnaBridge 171:3a7713b1edbc 492
AnnaBridge 171:3a7713b1edbc 493 /**
AnnaBridge 171:3a7713b1edbc 494 * @brief Get the frequency error direction latched in the time of the last
AnnaBridge 171:3a7713b1edbc 495 * SYNC event
AnnaBridge 171:3a7713b1edbc 496 * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection
AnnaBridge 171:3a7713b1edbc 497 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 498 * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
AnnaBridge 171:3a7713b1edbc 499 * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
AnnaBridge 171:3a7713b1edbc 500 */
AnnaBridge 171:3a7713b1edbc 501 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
AnnaBridge 171:3a7713b1edbc 502 {
AnnaBridge 171:3a7713b1edbc 503 return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
AnnaBridge 171:3a7713b1edbc 504 }
AnnaBridge 171:3a7713b1edbc 505
AnnaBridge 171:3a7713b1edbc 506 /**
AnnaBridge 171:3a7713b1edbc 507 * @brief Get the frequency error counter value latched in the time of the last SYNC event
AnnaBridge 171:3a7713b1edbc 508 * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture
AnnaBridge 171:3a7713b1edbc 509 * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
AnnaBridge 171:3a7713b1edbc 510 */
AnnaBridge 171:3a7713b1edbc 511 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
AnnaBridge 171:3a7713b1edbc 512 {
AnnaBridge 171:3a7713b1edbc 513 return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
AnnaBridge 171:3a7713b1edbc 514 }
AnnaBridge 171:3a7713b1edbc 515
AnnaBridge 171:3a7713b1edbc 516 /**
AnnaBridge 171:3a7713b1edbc 517 * @}
AnnaBridge 171:3a7713b1edbc 518 */
AnnaBridge 171:3a7713b1edbc 519
AnnaBridge 171:3a7713b1edbc 520 /** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
AnnaBridge 171:3a7713b1edbc 521 * @{
AnnaBridge 171:3a7713b1edbc 522 */
AnnaBridge 171:3a7713b1edbc 523
AnnaBridge 171:3a7713b1edbc 524 /**
AnnaBridge 171:3a7713b1edbc 525 * @brief Check if SYNC event OK signal occurred or not
AnnaBridge 171:3a7713b1edbc 526 * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK
AnnaBridge 171:3a7713b1edbc 527 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 528 */
AnnaBridge 171:3a7713b1edbc 529 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
AnnaBridge 171:3a7713b1edbc 530 {
AnnaBridge 171:3a7713b1edbc 531 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF));
AnnaBridge 171:3a7713b1edbc 532 }
AnnaBridge 171:3a7713b1edbc 533
AnnaBridge 171:3a7713b1edbc 534 /**
AnnaBridge 171:3a7713b1edbc 535 * @brief Check if SYNC warning signal occurred or not
AnnaBridge 171:3a7713b1edbc 536 * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN
AnnaBridge 171:3a7713b1edbc 537 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 538 */
AnnaBridge 171:3a7713b1edbc 539 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
AnnaBridge 171:3a7713b1edbc 540 {
AnnaBridge 171:3a7713b1edbc 541 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF));
AnnaBridge 171:3a7713b1edbc 542 }
AnnaBridge 171:3a7713b1edbc 543
AnnaBridge 171:3a7713b1edbc 544 /**
AnnaBridge 171:3a7713b1edbc 545 * @brief Check if Synchronization or trimming error signal occurred or not
AnnaBridge 171:3a7713b1edbc 546 * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR
AnnaBridge 171:3a7713b1edbc 547 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 548 */
AnnaBridge 171:3a7713b1edbc 549 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
AnnaBridge 171:3a7713b1edbc 550 {
AnnaBridge 171:3a7713b1edbc 551 return (READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF));
AnnaBridge 171:3a7713b1edbc 552 }
AnnaBridge 171:3a7713b1edbc 553
AnnaBridge 171:3a7713b1edbc 554 /**
AnnaBridge 171:3a7713b1edbc 555 * @brief Check if Expected SYNC signal occurred or not
AnnaBridge 171:3a7713b1edbc 556 * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC
AnnaBridge 171:3a7713b1edbc 557 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 558 */
AnnaBridge 171:3a7713b1edbc 559 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
AnnaBridge 171:3a7713b1edbc 560 {
AnnaBridge 171:3a7713b1edbc 561 return (READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF));
AnnaBridge 171:3a7713b1edbc 562 }
AnnaBridge 171:3a7713b1edbc 563
AnnaBridge 171:3a7713b1edbc 564 /**
AnnaBridge 171:3a7713b1edbc 565 * @brief Check if SYNC error signal occurred or not
AnnaBridge 171:3a7713b1edbc 566 * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR
AnnaBridge 171:3a7713b1edbc 567 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 568 */
AnnaBridge 171:3a7713b1edbc 569 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
AnnaBridge 171:3a7713b1edbc 570 {
AnnaBridge 171:3a7713b1edbc 571 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR));
AnnaBridge 171:3a7713b1edbc 572 }
AnnaBridge 171:3a7713b1edbc 573
AnnaBridge 171:3a7713b1edbc 574 /**
AnnaBridge 171:3a7713b1edbc 575 * @brief Check if SYNC missed error signal occurred or not
AnnaBridge 171:3a7713b1edbc 576 * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS
AnnaBridge 171:3a7713b1edbc 577 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 578 */
AnnaBridge 171:3a7713b1edbc 579 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
AnnaBridge 171:3a7713b1edbc 580 {
AnnaBridge 171:3a7713b1edbc 581 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS));
AnnaBridge 171:3a7713b1edbc 582 }
AnnaBridge 171:3a7713b1edbc 583
AnnaBridge 171:3a7713b1edbc 584 /**
AnnaBridge 171:3a7713b1edbc 585 * @brief Check if Trimming overflow or underflow occurred or not
AnnaBridge 171:3a7713b1edbc 586 * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF
AnnaBridge 171:3a7713b1edbc 587 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 588 */
AnnaBridge 171:3a7713b1edbc 589 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
AnnaBridge 171:3a7713b1edbc 590 {
AnnaBridge 171:3a7713b1edbc 591 return (READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF));
AnnaBridge 171:3a7713b1edbc 592 }
AnnaBridge 171:3a7713b1edbc 593
AnnaBridge 171:3a7713b1edbc 594 /**
AnnaBridge 171:3a7713b1edbc 595 * @brief Clear the SYNC event OK flag
AnnaBridge 171:3a7713b1edbc 596 * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK
AnnaBridge 171:3a7713b1edbc 597 * @retval None
AnnaBridge 171:3a7713b1edbc 598 */
AnnaBridge 171:3a7713b1edbc 599 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
AnnaBridge 171:3a7713b1edbc 600 {
AnnaBridge 171:3a7713b1edbc 601 WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
AnnaBridge 171:3a7713b1edbc 602 }
AnnaBridge 171:3a7713b1edbc 603
AnnaBridge 171:3a7713b1edbc 604 /**
AnnaBridge 171:3a7713b1edbc 605 * @brief Clear the SYNC warning flag
AnnaBridge 171:3a7713b1edbc 606 * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN
AnnaBridge 171:3a7713b1edbc 607 * @retval None
AnnaBridge 171:3a7713b1edbc 608 */
AnnaBridge 171:3a7713b1edbc 609 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
AnnaBridge 171:3a7713b1edbc 610 {
AnnaBridge 171:3a7713b1edbc 611 WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
AnnaBridge 171:3a7713b1edbc 612 }
AnnaBridge 171:3a7713b1edbc 613
AnnaBridge 171:3a7713b1edbc 614 /**
AnnaBridge 171:3a7713b1edbc 615 * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
AnnaBridge 171:3a7713b1edbc 616 * the ERR flag
AnnaBridge 171:3a7713b1edbc 617 * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR
AnnaBridge 171:3a7713b1edbc 618 * @retval None
AnnaBridge 171:3a7713b1edbc 619 */
AnnaBridge 171:3a7713b1edbc 620 __STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
AnnaBridge 171:3a7713b1edbc 621 {
AnnaBridge 171:3a7713b1edbc 622 WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
AnnaBridge 171:3a7713b1edbc 623 }
AnnaBridge 171:3a7713b1edbc 624
AnnaBridge 171:3a7713b1edbc 625 /**
AnnaBridge 171:3a7713b1edbc 626 * @brief Clear Expected SYNC flag
AnnaBridge 171:3a7713b1edbc 627 * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC
AnnaBridge 171:3a7713b1edbc 628 * @retval None
AnnaBridge 171:3a7713b1edbc 629 */
AnnaBridge 171:3a7713b1edbc 630 __STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
AnnaBridge 171:3a7713b1edbc 631 {
AnnaBridge 171:3a7713b1edbc 632 WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
AnnaBridge 171:3a7713b1edbc 633 }
AnnaBridge 171:3a7713b1edbc 634
AnnaBridge 171:3a7713b1edbc 635 /**
AnnaBridge 171:3a7713b1edbc 636 * @}
AnnaBridge 171:3a7713b1edbc 637 */
AnnaBridge 171:3a7713b1edbc 638
AnnaBridge 171:3a7713b1edbc 639 /** @defgroup CRS_LL_EF_IT_Management IT_Management
AnnaBridge 171:3a7713b1edbc 640 * @{
AnnaBridge 171:3a7713b1edbc 641 */
AnnaBridge 171:3a7713b1edbc 642
AnnaBridge 171:3a7713b1edbc 643 /**
AnnaBridge 171:3a7713b1edbc 644 * @brief Enable SYNC event OK interrupt
AnnaBridge 171:3a7713b1edbc 645 * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK
AnnaBridge 171:3a7713b1edbc 646 * @retval None
AnnaBridge 171:3a7713b1edbc 647 */
AnnaBridge 171:3a7713b1edbc 648 __STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
AnnaBridge 171:3a7713b1edbc 649 {
AnnaBridge 171:3a7713b1edbc 650 SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
AnnaBridge 171:3a7713b1edbc 651 }
AnnaBridge 171:3a7713b1edbc 652
AnnaBridge 171:3a7713b1edbc 653 /**
AnnaBridge 171:3a7713b1edbc 654 * @brief Disable SYNC event OK interrupt
AnnaBridge 171:3a7713b1edbc 655 * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK
AnnaBridge 171:3a7713b1edbc 656 * @retval None
AnnaBridge 171:3a7713b1edbc 657 */
AnnaBridge 171:3a7713b1edbc 658 __STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
AnnaBridge 171:3a7713b1edbc 659 {
AnnaBridge 171:3a7713b1edbc 660 CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
AnnaBridge 171:3a7713b1edbc 661 }
AnnaBridge 171:3a7713b1edbc 662
AnnaBridge 171:3a7713b1edbc 663 /**
AnnaBridge 171:3a7713b1edbc 664 * @brief Check if SYNC event OK interrupt is enabled or not
AnnaBridge 171:3a7713b1edbc 665 * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK
AnnaBridge 171:3a7713b1edbc 666 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 667 */
AnnaBridge 171:3a7713b1edbc 668 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
AnnaBridge 171:3a7713b1edbc 669 {
AnnaBridge 171:3a7713b1edbc 670 return (READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE));
AnnaBridge 171:3a7713b1edbc 671 }
AnnaBridge 171:3a7713b1edbc 672
AnnaBridge 171:3a7713b1edbc 673 /**
AnnaBridge 171:3a7713b1edbc 674 * @brief Enable SYNC warning interrupt
AnnaBridge 171:3a7713b1edbc 675 * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN
AnnaBridge 171:3a7713b1edbc 676 * @retval None
AnnaBridge 171:3a7713b1edbc 677 */
AnnaBridge 171:3a7713b1edbc 678 __STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
AnnaBridge 171:3a7713b1edbc 679 {
AnnaBridge 171:3a7713b1edbc 680 SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
AnnaBridge 171:3a7713b1edbc 681 }
AnnaBridge 171:3a7713b1edbc 682
AnnaBridge 171:3a7713b1edbc 683 /**
AnnaBridge 171:3a7713b1edbc 684 * @brief Disable SYNC warning interrupt
AnnaBridge 171:3a7713b1edbc 685 * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN
AnnaBridge 171:3a7713b1edbc 686 * @retval None
AnnaBridge 171:3a7713b1edbc 687 */
AnnaBridge 171:3a7713b1edbc 688 __STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
AnnaBridge 171:3a7713b1edbc 689 {
AnnaBridge 171:3a7713b1edbc 690 CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
AnnaBridge 171:3a7713b1edbc 691 }
AnnaBridge 171:3a7713b1edbc 692
AnnaBridge 171:3a7713b1edbc 693 /**
AnnaBridge 171:3a7713b1edbc 694 * @brief Check if SYNC warning interrupt is enabled or not
AnnaBridge 171:3a7713b1edbc 695 * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN
AnnaBridge 171:3a7713b1edbc 696 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 697 */
AnnaBridge 171:3a7713b1edbc 698 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
AnnaBridge 171:3a7713b1edbc 699 {
AnnaBridge 171:3a7713b1edbc 700 return (READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE));
AnnaBridge 171:3a7713b1edbc 701 }
AnnaBridge 171:3a7713b1edbc 702
AnnaBridge 171:3a7713b1edbc 703 /**
AnnaBridge 171:3a7713b1edbc 704 * @brief Enable Synchronization or trimming error interrupt
AnnaBridge 171:3a7713b1edbc 705 * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR
AnnaBridge 171:3a7713b1edbc 706 * @retval None
AnnaBridge 171:3a7713b1edbc 707 */
AnnaBridge 171:3a7713b1edbc 708 __STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
AnnaBridge 171:3a7713b1edbc 709 {
AnnaBridge 171:3a7713b1edbc 710 SET_BIT(CRS->CR, CRS_CR_ERRIE);
AnnaBridge 171:3a7713b1edbc 711 }
AnnaBridge 171:3a7713b1edbc 712
AnnaBridge 171:3a7713b1edbc 713 /**
AnnaBridge 171:3a7713b1edbc 714 * @brief Disable Synchronization or trimming error interrupt
AnnaBridge 171:3a7713b1edbc 715 * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR
AnnaBridge 171:3a7713b1edbc 716 * @retval None
AnnaBridge 171:3a7713b1edbc 717 */
AnnaBridge 171:3a7713b1edbc 718 __STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
AnnaBridge 171:3a7713b1edbc 719 {
AnnaBridge 171:3a7713b1edbc 720 CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
AnnaBridge 171:3a7713b1edbc 721 }
AnnaBridge 171:3a7713b1edbc 722
AnnaBridge 171:3a7713b1edbc 723 /**
AnnaBridge 171:3a7713b1edbc 724 * @brief Check if Synchronization or trimming error interrupt is enabled or not
AnnaBridge 171:3a7713b1edbc 725 * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR
AnnaBridge 171:3a7713b1edbc 726 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 727 */
AnnaBridge 171:3a7713b1edbc 728 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
AnnaBridge 171:3a7713b1edbc 729 {
AnnaBridge 171:3a7713b1edbc 730 return (READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE));
AnnaBridge 171:3a7713b1edbc 731 }
AnnaBridge 171:3a7713b1edbc 732
AnnaBridge 171:3a7713b1edbc 733 /**
AnnaBridge 171:3a7713b1edbc 734 * @brief Enable Expected SYNC interrupt
AnnaBridge 171:3a7713b1edbc 735 * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC
AnnaBridge 171:3a7713b1edbc 736 * @retval None
AnnaBridge 171:3a7713b1edbc 737 */
AnnaBridge 171:3a7713b1edbc 738 __STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
AnnaBridge 171:3a7713b1edbc 739 {
AnnaBridge 171:3a7713b1edbc 740 SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
AnnaBridge 171:3a7713b1edbc 741 }
AnnaBridge 171:3a7713b1edbc 742
AnnaBridge 171:3a7713b1edbc 743 /**
AnnaBridge 171:3a7713b1edbc 744 * @brief Disable Expected SYNC interrupt
AnnaBridge 171:3a7713b1edbc 745 * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC
AnnaBridge 171:3a7713b1edbc 746 * @retval None
AnnaBridge 171:3a7713b1edbc 747 */
AnnaBridge 171:3a7713b1edbc 748 __STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
AnnaBridge 171:3a7713b1edbc 749 {
AnnaBridge 171:3a7713b1edbc 750 CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
AnnaBridge 171:3a7713b1edbc 751 }
AnnaBridge 171:3a7713b1edbc 752
AnnaBridge 171:3a7713b1edbc 753 /**
AnnaBridge 171:3a7713b1edbc 754 * @brief Check if Expected SYNC interrupt is enabled or not
AnnaBridge 171:3a7713b1edbc 755 * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC
AnnaBridge 171:3a7713b1edbc 756 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 757 */
AnnaBridge 171:3a7713b1edbc 758 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
AnnaBridge 171:3a7713b1edbc 759 {
AnnaBridge 171:3a7713b1edbc 760 return (READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE));
AnnaBridge 171:3a7713b1edbc 761 }
AnnaBridge 171:3a7713b1edbc 762
AnnaBridge 171:3a7713b1edbc 763 /**
AnnaBridge 171:3a7713b1edbc 764 * @}
AnnaBridge 171:3a7713b1edbc 765 */
AnnaBridge 171:3a7713b1edbc 766
AnnaBridge 171:3a7713b1edbc 767 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 171:3a7713b1edbc 768 /** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
AnnaBridge 171:3a7713b1edbc 769 * @{
AnnaBridge 171:3a7713b1edbc 770 */
AnnaBridge 171:3a7713b1edbc 771
AnnaBridge 171:3a7713b1edbc 772 ErrorStatus LL_CRS_DeInit(void);
AnnaBridge 171:3a7713b1edbc 773
AnnaBridge 171:3a7713b1edbc 774 /**
AnnaBridge 171:3a7713b1edbc 775 * @}
AnnaBridge 171:3a7713b1edbc 776 */
AnnaBridge 171:3a7713b1edbc 777 #endif /* USE_FULL_LL_DRIVER */
AnnaBridge 171:3a7713b1edbc 778
AnnaBridge 171:3a7713b1edbc 779 /**
AnnaBridge 171:3a7713b1edbc 780 * @}
AnnaBridge 171:3a7713b1edbc 781 */
AnnaBridge 171:3a7713b1edbc 782
AnnaBridge 171:3a7713b1edbc 783 /**
AnnaBridge 171:3a7713b1edbc 784 * @}
AnnaBridge 171:3a7713b1edbc 785 */
AnnaBridge 171:3a7713b1edbc 786
AnnaBridge 171:3a7713b1edbc 787 #endif /* defined(CRS) */
AnnaBridge 171:3a7713b1edbc 788
AnnaBridge 171:3a7713b1edbc 789 /**
AnnaBridge 171:3a7713b1edbc 790 * @}
AnnaBridge 171:3a7713b1edbc 791 */
AnnaBridge 171:3a7713b1edbc 792
AnnaBridge 171:3a7713b1edbc 793 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 794 }
AnnaBridge 171:3a7713b1edbc 795 #endif
AnnaBridge 171:3a7713b1edbc 796
AnnaBridge 171:3a7713b1edbc 797 #endif /* __STM32F0xx_LL_CRS_H */
AnnaBridge 171:3a7713b1edbc 798
AnnaBridge 171:3a7713b1edbc 799 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/