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TARGET_NUCLEO_F030R8/TOOLCHAIN_IAR/stm32f0xx_ll_cortex.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file stm32f0xx_ll_cortex.h
AnnaBridge 171:3a7713b1edbc 4 * @author MCD Application Team
AnnaBridge 171:3a7713b1edbc 5 * @brief Header file of CORTEX LL module.
AnnaBridge 171:3a7713b1edbc 6 @verbatim
AnnaBridge 171:3a7713b1edbc 7 ==============================================================================
AnnaBridge 171:3a7713b1edbc 8 ##### How to use this driver #####
AnnaBridge 171:3a7713b1edbc 9 ==============================================================================
AnnaBridge 171:3a7713b1edbc 10 [..]
AnnaBridge 171:3a7713b1edbc 11 The LL CORTEX driver contains a set of generic APIs that can be
AnnaBridge 171:3a7713b1edbc 12 used by user:
AnnaBridge 171:3a7713b1edbc 13 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
AnnaBridge 171:3a7713b1edbc 14 functions
AnnaBridge 171:3a7713b1edbc 15 (+) Low power mode configuration (SCB register of Cortex-MCU)
AnnaBridge 171:3a7713b1edbc 16 (+) API to access to MCU info (CPUID register)
AnnaBridge 171:3a7713b1edbc 17
AnnaBridge 171:3a7713b1edbc 18 @endverbatim
AnnaBridge 171:3a7713b1edbc 19 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 20 * @attention
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 171:3a7713b1edbc 23 *
AnnaBridge 171:3a7713b1edbc 24 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 25 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 26 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 27 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 28 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 29 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 30 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 31 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 171:3a7713b1edbc 32 * may be used to endorse or promote products derived from this software
AnnaBridge 171:3a7713b1edbc 33 * without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 34 *
AnnaBridge 171:3a7713b1edbc 35 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 171:3a7713b1edbc 36 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 171:3a7713b1edbc 37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 38 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 171:3a7713b1edbc 39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 171:3a7713b1edbc 41 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 171:3a7713b1edbc 42 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 171:3a7713b1edbc 43 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 171:3a7713b1edbc 44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 45 *
AnnaBridge 171:3a7713b1edbc 46 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 47 */
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 171:3a7713b1edbc 50 #ifndef __STM32F0xx_LL_CORTEX_H
AnnaBridge 171:3a7713b1edbc 51 #define __STM32F0xx_LL_CORTEX_H
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 54 extern "C" {
AnnaBridge 171:3a7713b1edbc 55 #endif
AnnaBridge 171:3a7713b1edbc 56
AnnaBridge 171:3a7713b1edbc 57 /* Includes ------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 58 #include "stm32f0xx.h"
AnnaBridge 171:3a7713b1edbc 59
AnnaBridge 171:3a7713b1edbc 60 /** @addtogroup STM32F0xx_LL_Driver
AnnaBridge 171:3a7713b1edbc 61 * @{
AnnaBridge 171:3a7713b1edbc 62 */
AnnaBridge 171:3a7713b1edbc 63
AnnaBridge 171:3a7713b1edbc 64 /** @defgroup CORTEX_LL CORTEX
AnnaBridge 171:3a7713b1edbc 65 * @{
AnnaBridge 171:3a7713b1edbc 66 */
AnnaBridge 171:3a7713b1edbc 67
AnnaBridge 171:3a7713b1edbc 68 /* Private types -------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 69 /* Private variables ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 70
AnnaBridge 171:3a7713b1edbc 71 /* Private constants ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 72
AnnaBridge 171:3a7713b1edbc 73 /* Private macros ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 74
AnnaBridge 171:3a7713b1edbc 75 /* Exported types ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 76 /* Exported constants --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 77 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
AnnaBridge 171:3a7713b1edbc 78 * @{
AnnaBridge 171:3a7713b1edbc 79 */
AnnaBridge 171:3a7713b1edbc 80
AnnaBridge 171:3a7713b1edbc 81 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
AnnaBridge 171:3a7713b1edbc 82 * @{
AnnaBridge 171:3a7713b1edbc 83 */
AnnaBridge 171:3a7713b1edbc 84 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
AnnaBridge 171:3a7713b1edbc 85 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
AnnaBridge 171:3a7713b1edbc 86 /**
AnnaBridge 171:3a7713b1edbc 87 * @}
AnnaBridge 171:3a7713b1edbc 88 */
AnnaBridge 171:3a7713b1edbc 89
AnnaBridge 171:3a7713b1edbc 90 /**
AnnaBridge 171:3a7713b1edbc 91 * @}
AnnaBridge 171:3a7713b1edbc 92 */
AnnaBridge 171:3a7713b1edbc 93
AnnaBridge 171:3a7713b1edbc 94 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 95
AnnaBridge 171:3a7713b1edbc 96 /* Exported functions --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 97 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
AnnaBridge 171:3a7713b1edbc 98 * @{
AnnaBridge 171:3a7713b1edbc 99 */
AnnaBridge 171:3a7713b1edbc 100
AnnaBridge 171:3a7713b1edbc 101 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
AnnaBridge 171:3a7713b1edbc 102 * @{
AnnaBridge 171:3a7713b1edbc 103 */
AnnaBridge 171:3a7713b1edbc 104
AnnaBridge 171:3a7713b1edbc 105 /**
AnnaBridge 171:3a7713b1edbc 106 * @brief This function checks if the Systick counter flag is active or not.
AnnaBridge 171:3a7713b1edbc 107 * @note It can be used in timeout function on application side.
AnnaBridge 171:3a7713b1edbc 108 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
AnnaBridge 171:3a7713b1edbc 109 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 110 */
AnnaBridge 171:3a7713b1edbc 111 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
AnnaBridge 171:3a7713b1edbc 112 {
AnnaBridge 171:3a7713b1edbc 113 return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
AnnaBridge 171:3a7713b1edbc 114 }
AnnaBridge 171:3a7713b1edbc 115
AnnaBridge 171:3a7713b1edbc 116 /**
AnnaBridge 171:3a7713b1edbc 117 * @brief Configures the SysTick clock source
AnnaBridge 171:3a7713b1edbc 118 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
AnnaBridge 171:3a7713b1edbc 119 * @param Source This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 120 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
AnnaBridge 171:3a7713b1edbc 121 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
AnnaBridge 171:3a7713b1edbc 122 * @retval None
AnnaBridge 171:3a7713b1edbc 123 */
AnnaBridge 171:3a7713b1edbc 124 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
AnnaBridge 171:3a7713b1edbc 125 {
AnnaBridge 171:3a7713b1edbc 126 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
AnnaBridge 171:3a7713b1edbc 127 {
AnnaBridge 171:3a7713b1edbc 128 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
AnnaBridge 171:3a7713b1edbc 129 }
AnnaBridge 171:3a7713b1edbc 130 else
AnnaBridge 171:3a7713b1edbc 131 {
AnnaBridge 171:3a7713b1edbc 132 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
AnnaBridge 171:3a7713b1edbc 133 }
AnnaBridge 171:3a7713b1edbc 134 }
AnnaBridge 171:3a7713b1edbc 135
AnnaBridge 171:3a7713b1edbc 136 /**
AnnaBridge 171:3a7713b1edbc 137 * @brief Get the SysTick clock source
AnnaBridge 171:3a7713b1edbc 138 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
AnnaBridge 171:3a7713b1edbc 139 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 140 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
AnnaBridge 171:3a7713b1edbc 141 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
AnnaBridge 171:3a7713b1edbc 142 */
AnnaBridge 171:3a7713b1edbc 143 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
AnnaBridge 171:3a7713b1edbc 144 {
AnnaBridge 171:3a7713b1edbc 145 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
AnnaBridge 171:3a7713b1edbc 146 }
AnnaBridge 171:3a7713b1edbc 147
AnnaBridge 171:3a7713b1edbc 148 /**
AnnaBridge 171:3a7713b1edbc 149 * @brief Enable SysTick exception request
AnnaBridge 171:3a7713b1edbc 150 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
AnnaBridge 171:3a7713b1edbc 151 * @retval None
AnnaBridge 171:3a7713b1edbc 152 */
AnnaBridge 171:3a7713b1edbc 153 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
AnnaBridge 171:3a7713b1edbc 154 {
AnnaBridge 171:3a7713b1edbc 155 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
AnnaBridge 171:3a7713b1edbc 156 }
AnnaBridge 171:3a7713b1edbc 157
AnnaBridge 171:3a7713b1edbc 158 /**
AnnaBridge 171:3a7713b1edbc 159 * @brief Disable SysTick exception request
AnnaBridge 171:3a7713b1edbc 160 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
AnnaBridge 171:3a7713b1edbc 161 * @retval None
AnnaBridge 171:3a7713b1edbc 162 */
AnnaBridge 171:3a7713b1edbc 163 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
AnnaBridge 171:3a7713b1edbc 164 {
AnnaBridge 171:3a7713b1edbc 165 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
AnnaBridge 171:3a7713b1edbc 166 }
AnnaBridge 171:3a7713b1edbc 167
AnnaBridge 171:3a7713b1edbc 168 /**
AnnaBridge 171:3a7713b1edbc 169 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
AnnaBridge 171:3a7713b1edbc 170 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
AnnaBridge 171:3a7713b1edbc 171 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 172 */
AnnaBridge 171:3a7713b1edbc 173 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
AnnaBridge 171:3a7713b1edbc 174 {
AnnaBridge 171:3a7713b1edbc 175 return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
AnnaBridge 171:3a7713b1edbc 176 }
AnnaBridge 171:3a7713b1edbc 177
AnnaBridge 171:3a7713b1edbc 178 /**
AnnaBridge 171:3a7713b1edbc 179 * @}
AnnaBridge 171:3a7713b1edbc 180 */
AnnaBridge 171:3a7713b1edbc 181
AnnaBridge 171:3a7713b1edbc 182 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
AnnaBridge 171:3a7713b1edbc 183 * @{
AnnaBridge 171:3a7713b1edbc 184 */
AnnaBridge 171:3a7713b1edbc 185
AnnaBridge 171:3a7713b1edbc 186 /**
AnnaBridge 171:3a7713b1edbc 187 * @brief Processor uses sleep as its low power mode
AnnaBridge 171:3a7713b1edbc 188 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
AnnaBridge 171:3a7713b1edbc 189 * @retval None
AnnaBridge 171:3a7713b1edbc 190 */
AnnaBridge 171:3a7713b1edbc 191 __STATIC_INLINE void LL_LPM_EnableSleep(void)
AnnaBridge 171:3a7713b1edbc 192 {
AnnaBridge 171:3a7713b1edbc 193 /* Clear SLEEPDEEP bit of Cortex System Control Register */
AnnaBridge 171:3a7713b1edbc 194 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
AnnaBridge 171:3a7713b1edbc 195 }
AnnaBridge 171:3a7713b1edbc 196
AnnaBridge 171:3a7713b1edbc 197 /**
AnnaBridge 171:3a7713b1edbc 198 * @brief Processor uses deep sleep as its low power mode
AnnaBridge 171:3a7713b1edbc 199 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
AnnaBridge 171:3a7713b1edbc 200 * @retval None
AnnaBridge 171:3a7713b1edbc 201 */
AnnaBridge 171:3a7713b1edbc 202 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
AnnaBridge 171:3a7713b1edbc 203 {
AnnaBridge 171:3a7713b1edbc 204 /* Set SLEEPDEEP bit of Cortex System Control Register */
AnnaBridge 171:3a7713b1edbc 205 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
AnnaBridge 171:3a7713b1edbc 206 }
AnnaBridge 171:3a7713b1edbc 207
AnnaBridge 171:3a7713b1edbc 208 /**
AnnaBridge 171:3a7713b1edbc 209 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
AnnaBridge 171:3a7713b1edbc 210 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
AnnaBridge 171:3a7713b1edbc 211 * empty main application.
AnnaBridge 171:3a7713b1edbc 212 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
AnnaBridge 171:3a7713b1edbc 213 * @retval None
AnnaBridge 171:3a7713b1edbc 214 */
AnnaBridge 171:3a7713b1edbc 215 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
AnnaBridge 171:3a7713b1edbc 216 {
AnnaBridge 171:3a7713b1edbc 217 /* Set SLEEPONEXIT bit of Cortex System Control Register */
AnnaBridge 171:3a7713b1edbc 218 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
AnnaBridge 171:3a7713b1edbc 219 }
AnnaBridge 171:3a7713b1edbc 220
AnnaBridge 171:3a7713b1edbc 221 /**
AnnaBridge 171:3a7713b1edbc 222 * @brief Do not sleep when returning to Thread mode.
AnnaBridge 171:3a7713b1edbc 223 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
AnnaBridge 171:3a7713b1edbc 224 * @retval None
AnnaBridge 171:3a7713b1edbc 225 */
AnnaBridge 171:3a7713b1edbc 226 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
AnnaBridge 171:3a7713b1edbc 227 {
AnnaBridge 171:3a7713b1edbc 228 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
AnnaBridge 171:3a7713b1edbc 229 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
AnnaBridge 171:3a7713b1edbc 230 }
AnnaBridge 171:3a7713b1edbc 231
AnnaBridge 171:3a7713b1edbc 232 /**
AnnaBridge 171:3a7713b1edbc 233 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
AnnaBridge 171:3a7713b1edbc 234 * processor.
AnnaBridge 171:3a7713b1edbc 235 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
AnnaBridge 171:3a7713b1edbc 236 * @retval None
AnnaBridge 171:3a7713b1edbc 237 */
AnnaBridge 171:3a7713b1edbc 238 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
AnnaBridge 171:3a7713b1edbc 239 {
AnnaBridge 171:3a7713b1edbc 240 /* Set SEVEONPEND bit of Cortex System Control Register */
AnnaBridge 171:3a7713b1edbc 241 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
AnnaBridge 171:3a7713b1edbc 242 }
AnnaBridge 171:3a7713b1edbc 243
AnnaBridge 171:3a7713b1edbc 244 /**
AnnaBridge 171:3a7713b1edbc 245 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
AnnaBridge 171:3a7713b1edbc 246 * excluded
AnnaBridge 171:3a7713b1edbc 247 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
AnnaBridge 171:3a7713b1edbc 248 * @retval None
AnnaBridge 171:3a7713b1edbc 249 */
AnnaBridge 171:3a7713b1edbc 250 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
AnnaBridge 171:3a7713b1edbc 251 {
AnnaBridge 171:3a7713b1edbc 252 /* Clear SEVEONPEND bit of Cortex System Control Register */
AnnaBridge 171:3a7713b1edbc 253 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
AnnaBridge 171:3a7713b1edbc 254 }
AnnaBridge 171:3a7713b1edbc 255
AnnaBridge 171:3a7713b1edbc 256 /**
AnnaBridge 171:3a7713b1edbc 257 * @}
AnnaBridge 171:3a7713b1edbc 258 */
AnnaBridge 171:3a7713b1edbc 259
AnnaBridge 171:3a7713b1edbc 260 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
AnnaBridge 171:3a7713b1edbc 261 * @{
AnnaBridge 171:3a7713b1edbc 262 */
AnnaBridge 171:3a7713b1edbc 263
AnnaBridge 171:3a7713b1edbc 264 /**
AnnaBridge 171:3a7713b1edbc 265 * @brief Get Implementer code
AnnaBridge 171:3a7713b1edbc 266 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
AnnaBridge 171:3a7713b1edbc 267 * @retval Value should be equal to 0x41 for ARM
AnnaBridge 171:3a7713b1edbc 268 */
AnnaBridge 171:3a7713b1edbc 269 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
AnnaBridge 171:3a7713b1edbc 270 {
AnnaBridge 171:3a7713b1edbc 271 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
AnnaBridge 171:3a7713b1edbc 272 }
AnnaBridge 171:3a7713b1edbc 273
AnnaBridge 171:3a7713b1edbc 274 /**
AnnaBridge 171:3a7713b1edbc 275 * @brief Get Variant number (The r value in the rnpn product revision identifier)
AnnaBridge 171:3a7713b1edbc 276 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
AnnaBridge 171:3a7713b1edbc 277 * @retval Value between 0 and 255 (0x0: revision 0)
AnnaBridge 171:3a7713b1edbc 278 */
AnnaBridge 171:3a7713b1edbc 279 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
AnnaBridge 171:3a7713b1edbc 280 {
AnnaBridge 171:3a7713b1edbc 281 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
AnnaBridge 171:3a7713b1edbc 282 }
AnnaBridge 171:3a7713b1edbc 283
AnnaBridge 171:3a7713b1edbc 284 /**
AnnaBridge 171:3a7713b1edbc 285 * @brief Get Architecture number
AnnaBridge 171:3a7713b1edbc 286 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture
AnnaBridge 171:3a7713b1edbc 287 * @retval Value should be equal to 0xC for Cortex-M0 devices
AnnaBridge 171:3a7713b1edbc 288 */
AnnaBridge 171:3a7713b1edbc 289 __STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void)
AnnaBridge 171:3a7713b1edbc 290 {
AnnaBridge 171:3a7713b1edbc 291 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
AnnaBridge 171:3a7713b1edbc 292 }
AnnaBridge 171:3a7713b1edbc 293
AnnaBridge 171:3a7713b1edbc 294 /**
AnnaBridge 171:3a7713b1edbc 295 * @brief Get Part number
AnnaBridge 171:3a7713b1edbc 296 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
AnnaBridge 171:3a7713b1edbc 297 * @retval Value should be equal to 0xC20 for Cortex-M0
AnnaBridge 171:3a7713b1edbc 298 */
AnnaBridge 171:3a7713b1edbc 299 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
AnnaBridge 171:3a7713b1edbc 300 {
AnnaBridge 171:3a7713b1edbc 301 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
AnnaBridge 171:3a7713b1edbc 302 }
AnnaBridge 171:3a7713b1edbc 303
AnnaBridge 171:3a7713b1edbc 304 /**
AnnaBridge 171:3a7713b1edbc 305 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
AnnaBridge 171:3a7713b1edbc 306 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
AnnaBridge 171:3a7713b1edbc 307 * @retval Value between 0 and 255 (0x1: patch 1)
AnnaBridge 171:3a7713b1edbc 308 */
AnnaBridge 171:3a7713b1edbc 309 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
AnnaBridge 171:3a7713b1edbc 310 {
AnnaBridge 171:3a7713b1edbc 311 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
AnnaBridge 171:3a7713b1edbc 312 }
AnnaBridge 171:3a7713b1edbc 313
AnnaBridge 171:3a7713b1edbc 314 /**
AnnaBridge 171:3a7713b1edbc 315 * @}
AnnaBridge 171:3a7713b1edbc 316 */
AnnaBridge 171:3a7713b1edbc 317
AnnaBridge 171:3a7713b1edbc 318 /**
AnnaBridge 171:3a7713b1edbc 319 * @}
AnnaBridge 171:3a7713b1edbc 320 */
AnnaBridge 171:3a7713b1edbc 321
AnnaBridge 171:3a7713b1edbc 322 /**
AnnaBridge 171:3a7713b1edbc 323 * @}
AnnaBridge 171:3a7713b1edbc 324 */
AnnaBridge 171:3a7713b1edbc 325
AnnaBridge 171:3a7713b1edbc 326 /**
AnnaBridge 171:3a7713b1edbc 327 * @}
AnnaBridge 171:3a7713b1edbc 328 */
AnnaBridge 171:3a7713b1edbc 329
AnnaBridge 171:3a7713b1edbc 330 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 331 }
AnnaBridge 171:3a7713b1edbc 332 #endif
AnnaBridge 171:3a7713b1edbc 333
AnnaBridge 171:3a7713b1edbc 334 #endif /* __STM32F0xx_LL_CORTEX_H */
AnnaBridge 171:3a7713b1edbc 335
AnnaBridge 171:3a7713b1edbc 336 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/