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TARGET_NUCLEO_F030R8/TOOLCHAIN_IAR/stm32f0xx_ll_bus.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /** |
| AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32f0xx_ll_bus.h |
| AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
| AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of BUS LL module. |
| AnnaBridge | 171:3a7713b1edbc | 6 | |
| AnnaBridge | 171:3a7713b1edbc | 7 | @verbatim |
| AnnaBridge | 171:3a7713b1edbc | 8 | ##### RCC Limitations ##### |
| AnnaBridge | 171:3a7713b1edbc | 9 | ============================================================================== |
| AnnaBridge | 171:3a7713b1edbc | 10 | [..] |
| AnnaBridge | 171:3a7713b1edbc | 11 | A delay between an RCC peripheral clock enable and the effective peripheral |
| AnnaBridge | 171:3a7713b1edbc | 12 | enabling should be taken into account in order to manage the peripheral read/write |
| AnnaBridge | 171:3a7713b1edbc | 13 | from/to registers. |
| AnnaBridge | 171:3a7713b1edbc | 14 | (+) This delay depends on the peripheral mapping. |
| AnnaBridge | 171:3a7713b1edbc | 15 | (++) AHB & APB peripherals, 1 dummy read is necessary |
| AnnaBridge | 171:3a7713b1edbc | 16 | |
| AnnaBridge | 171:3a7713b1edbc | 17 | [..] |
| AnnaBridge | 171:3a7713b1edbc | 18 | Workarounds: |
| AnnaBridge | 171:3a7713b1edbc | 19 | (#) For AHB & APB peripherals, a dummy read to the peripheral register has been |
| AnnaBridge | 171:3a7713b1edbc | 20 | inserted in each LL_{BUS}_GRP{x}_EnableClock() function. |
| AnnaBridge | 171:3a7713b1edbc | 21 | |
| AnnaBridge | 171:3a7713b1edbc | 22 | @endverbatim |
| AnnaBridge | 171:3a7713b1edbc | 23 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 24 | * @attention |
| AnnaBridge | 171:3a7713b1edbc | 25 | * |
| AnnaBridge | 171:3a7713b1edbc | 26 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| AnnaBridge | 171:3a7713b1edbc | 27 | * |
| AnnaBridge | 171:3a7713b1edbc | 28 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 171:3a7713b1edbc | 29 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 171:3a7713b1edbc | 30 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 31 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 171:3a7713b1edbc | 32 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 33 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 171:3a7713b1edbc | 34 | * and/or other materials provided with the distribution. |
| AnnaBridge | 171:3a7713b1edbc | 35 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 171:3a7713b1edbc | 36 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 171:3a7713b1edbc | 37 | * without specific prior written permission. |
| AnnaBridge | 171:3a7713b1edbc | 38 | * |
| AnnaBridge | 171:3a7713b1edbc | 39 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 171:3a7713b1edbc | 40 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 171:3a7713b1edbc | 41 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 171:3a7713b1edbc | 42 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 171:3a7713b1edbc | 43 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 171:3a7713b1edbc | 44 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 171:3a7713b1edbc | 45 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 171:3a7713b1edbc | 46 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 171:3a7713b1edbc | 47 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 171:3a7713b1edbc | 48 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 171:3a7713b1edbc | 49 | * |
| AnnaBridge | 171:3a7713b1edbc | 50 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 51 | */ |
| AnnaBridge | 171:3a7713b1edbc | 52 | |
| AnnaBridge | 171:3a7713b1edbc | 53 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 54 | #ifndef __STM32F0xx_LL_BUS_H |
| AnnaBridge | 171:3a7713b1edbc | 55 | #define __STM32F0xx_LL_BUS_H |
| AnnaBridge | 171:3a7713b1edbc | 56 | |
| AnnaBridge | 171:3a7713b1edbc | 57 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 58 | extern "C" { |
| AnnaBridge | 171:3a7713b1edbc | 59 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 60 | |
| AnnaBridge | 171:3a7713b1edbc | 61 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 62 | #include "stm32f0xx.h" |
| AnnaBridge | 171:3a7713b1edbc | 63 | |
| AnnaBridge | 171:3a7713b1edbc | 64 | /** @addtogroup STM32F0xx_LL_Driver |
| AnnaBridge | 171:3a7713b1edbc | 65 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 66 | */ |
| AnnaBridge | 171:3a7713b1edbc | 67 | |
| AnnaBridge | 171:3a7713b1edbc | 68 | #if defined(RCC) |
| AnnaBridge | 171:3a7713b1edbc | 69 | |
| AnnaBridge | 171:3a7713b1edbc | 70 | /** @defgroup BUS_LL BUS |
| AnnaBridge | 171:3a7713b1edbc | 71 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 72 | */ |
| AnnaBridge | 171:3a7713b1edbc | 73 | |
| AnnaBridge | 171:3a7713b1edbc | 74 | /* Private types -------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 75 | /* Private variables ---------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 76 | |
| AnnaBridge | 171:3a7713b1edbc | 77 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 78 | |
| AnnaBridge | 171:3a7713b1edbc | 79 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 80 | |
| AnnaBridge | 171:3a7713b1edbc | 81 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 82 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 83 | /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants |
| AnnaBridge | 171:3a7713b1edbc | 84 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 85 | */ |
| AnnaBridge | 171:3a7713b1edbc | 86 | |
| AnnaBridge | 171:3a7713b1edbc | 87 | /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH |
| AnnaBridge | 171:3a7713b1edbc | 88 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 89 | */ |
| AnnaBridge | 171:3a7713b1edbc | 90 | #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU |
| AnnaBridge | 171:3a7713b1edbc | 91 | #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN |
| AnnaBridge | 171:3a7713b1edbc | 92 | #if defined(DMA2) |
| AnnaBridge | 171:3a7713b1edbc | 93 | #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN |
| AnnaBridge | 171:3a7713b1edbc | 94 | #endif /*DMA2*/ |
| AnnaBridge | 171:3a7713b1edbc | 95 | #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN |
| AnnaBridge | 171:3a7713b1edbc | 96 | #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN |
| AnnaBridge | 171:3a7713b1edbc | 97 | #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN |
| AnnaBridge | 171:3a7713b1edbc | 98 | #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN |
| AnnaBridge | 171:3a7713b1edbc | 99 | #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN |
| AnnaBridge | 171:3a7713b1edbc | 100 | #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN |
| AnnaBridge | 171:3a7713b1edbc | 101 | #if defined(GPIOD) |
| AnnaBridge | 171:3a7713b1edbc | 102 | #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN |
| AnnaBridge | 171:3a7713b1edbc | 103 | #endif /*GPIOD*/ |
| AnnaBridge | 171:3a7713b1edbc | 104 | #if defined(GPIOE) |
| AnnaBridge | 171:3a7713b1edbc | 105 | #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN |
| AnnaBridge | 171:3a7713b1edbc | 106 | #endif /*GPIOE*/ |
| AnnaBridge | 171:3a7713b1edbc | 107 | #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN |
| AnnaBridge | 171:3a7713b1edbc | 108 | #if defined(TSC) |
| AnnaBridge | 171:3a7713b1edbc | 109 | #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHBENR_TSCEN |
| AnnaBridge | 171:3a7713b1edbc | 110 | #endif /*TSC*/ |
| AnnaBridge | 171:3a7713b1edbc | 111 | /** |
| AnnaBridge | 171:3a7713b1edbc | 112 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 113 | */ |
| AnnaBridge | 171:3a7713b1edbc | 114 | |
| AnnaBridge | 171:3a7713b1edbc | 115 | /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH |
| AnnaBridge | 171:3a7713b1edbc | 116 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 117 | */ |
| AnnaBridge | 171:3a7713b1edbc | 118 | #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU |
| AnnaBridge | 171:3a7713b1edbc | 119 | #if defined(TIM2) |
| AnnaBridge | 171:3a7713b1edbc | 120 | #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN |
| AnnaBridge | 171:3a7713b1edbc | 121 | #endif /*TIM2*/ |
| AnnaBridge | 171:3a7713b1edbc | 122 | #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN |
| AnnaBridge | 171:3a7713b1edbc | 123 | #if defined(TIM6) |
| AnnaBridge | 171:3a7713b1edbc | 124 | #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN |
| AnnaBridge | 171:3a7713b1edbc | 125 | #endif /*TIM6*/ |
| AnnaBridge | 171:3a7713b1edbc | 126 | #if defined(TIM7) |
| AnnaBridge | 171:3a7713b1edbc | 127 | #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN |
| AnnaBridge | 171:3a7713b1edbc | 128 | #endif /*TIM7*/ |
| AnnaBridge | 171:3a7713b1edbc | 129 | #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN |
| AnnaBridge | 171:3a7713b1edbc | 130 | #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN |
| AnnaBridge | 171:3a7713b1edbc | 131 | #if defined(SPI2) |
| AnnaBridge | 171:3a7713b1edbc | 132 | #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN |
| AnnaBridge | 171:3a7713b1edbc | 133 | #endif /*SPI2*/ |
| AnnaBridge | 171:3a7713b1edbc | 134 | #if defined(USART2) |
| AnnaBridge | 171:3a7713b1edbc | 135 | #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN |
| AnnaBridge | 171:3a7713b1edbc | 136 | #endif /* USART2 */ |
| AnnaBridge | 171:3a7713b1edbc | 137 | #if defined(USART3) |
| AnnaBridge | 171:3a7713b1edbc | 138 | #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN |
| AnnaBridge | 171:3a7713b1edbc | 139 | #endif /* USART3 */ |
| AnnaBridge | 171:3a7713b1edbc | 140 | #if defined(USART4) |
| AnnaBridge | 171:3a7713b1edbc | 141 | #define LL_APB1_GRP1_PERIPH_USART4 RCC_APB1ENR_USART4EN |
| AnnaBridge | 171:3a7713b1edbc | 142 | #endif /* USART4 */ |
| AnnaBridge | 171:3a7713b1edbc | 143 | #if defined(USART5) |
| AnnaBridge | 171:3a7713b1edbc | 144 | #define LL_APB1_GRP1_PERIPH_USART5 RCC_APB1ENR_USART5EN |
| AnnaBridge | 171:3a7713b1edbc | 145 | #endif /* USART5 */ |
| AnnaBridge | 171:3a7713b1edbc | 146 | #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN |
| AnnaBridge | 171:3a7713b1edbc | 147 | #if defined(I2C2) |
| AnnaBridge | 171:3a7713b1edbc | 148 | #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN |
| AnnaBridge | 171:3a7713b1edbc | 149 | #endif /*I2C2*/ |
| AnnaBridge | 171:3a7713b1edbc | 150 | #if defined(USB) |
| AnnaBridge | 171:3a7713b1edbc | 151 | #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN |
| AnnaBridge | 171:3a7713b1edbc | 152 | #endif /* USB */ |
| AnnaBridge | 171:3a7713b1edbc | 153 | #if defined(CAN) |
| AnnaBridge | 171:3a7713b1edbc | 154 | #define LL_APB1_GRP1_PERIPH_CAN RCC_APB1ENR_CANEN |
| AnnaBridge | 171:3a7713b1edbc | 155 | #endif /*CAN*/ |
| AnnaBridge | 171:3a7713b1edbc | 156 | #if defined(CRS) |
| AnnaBridge | 171:3a7713b1edbc | 157 | #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR_CRSEN |
| AnnaBridge | 171:3a7713b1edbc | 158 | #endif /*CRS*/ |
| AnnaBridge | 171:3a7713b1edbc | 159 | #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN |
| AnnaBridge | 171:3a7713b1edbc | 160 | #if defined(DAC) |
| AnnaBridge | 171:3a7713b1edbc | 161 | #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN |
| AnnaBridge | 171:3a7713b1edbc | 162 | #endif /*DAC*/ |
| AnnaBridge | 171:3a7713b1edbc | 163 | #if defined(CEC) |
| AnnaBridge | 171:3a7713b1edbc | 164 | #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN |
| AnnaBridge | 171:3a7713b1edbc | 165 | #endif /*CEC*/ |
| AnnaBridge | 171:3a7713b1edbc | 166 | /** |
| AnnaBridge | 171:3a7713b1edbc | 167 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 168 | */ |
| AnnaBridge | 171:3a7713b1edbc | 169 | |
| AnnaBridge | 171:3a7713b1edbc | 170 | /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH |
| AnnaBridge | 171:3a7713b1edbc | 171 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 172 | */ |
| AnnaBridge | 171:3a7713b1edbc | 173 | #define LL_APB1_GRP2_PERIPH_ALL (uint32_t)0xFFFFFFFFU |
| AnnaBridge | 171:3a7713b1edbc | 174 | #define LL_APB1_GRP2_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN |
| AnnaBridge | 171:3a7713b1edbc | 175 | #define LL_APB1_GRP2_PERIPH_ADC1 RCC_APB2ENR_ADC1EN |
| AnnaBridge | 171:3a7713b1edbc | 176 | #if defined(USART8) |
| AnnaBridge | 171:3a7713b1edbc | 177 | #define LL_APB1_GRP2_PERIPH_USART8 RCC_APB2ENR_USART8EN |
| AnnaBridge | 171:3a7713b1edbc | 178 | #endif /*USART8*/ |
| AnnaBridge | 171:3a7713b1edbc | 179 | #if defined(USART7) |
| AnnaBridge | 171:3a7713b1edbc | 180 | #define LL_APB1_GRP2_PERIPH_USART7 RCC_APB2ENR_USART7EN |
| AnnaBridge | 171:3a7713b1edbc | 181 | #endif /*USART7*/ |
| AnnaBridge | 171:3a7713b1edbc | 182 | #if defined(USART6) |
| AnnaBridge | 171:3a7713b1edbc | 183 | #define LL_APB1_GRP2_PERIPH_USART6 RCC_APB2ENR_USART6EN |
| AnnaBridge | 171:3a7713b1edbc | 184 | #endif /*USART6*/ |
| AnnaBridge | 171:3a7713b1edbc | 185 | #define LL_APB1_GRP2_PERIPH_TIM1 RCC_APB2ENR_TIM1EN |
| AnnaBridge | 171:3a7713b1edbc | 186 | #define LL_APB1_GRP2_PERIPH_SPI1 RCC_APB2ENR_SPI1EN |
| AnnaBridge | 171:3a7713b1edbc | 187 | #define LL_APB1_GRP2_PERIPH_USART1 RCC_APB2ENR_USART1EN |
| AnnaBridge | 171:3a7713b1edbc | 188 | #if defined(TIM15) |
| AnnaBridge | 171:3a7713b1edbc | 189 | #define LL_APB1_GRP2_PERIPH_TIM15 RCC_APB2ENR_TIM15EN |
| AnnaBridge | 171:3a7713b1edbc | 190 | #endif /*TIM15*/ |
| AnnaBridge | 171:3a7713b1edbc | 191 | #define LL_APB1_GRP2_PERIPH_TIM16 RCC_APB2ENR_TIM16EN |
| AnnaBridge | 171:3a7713b1edbc | 192 | #define LL_APB1_GRP2_PERIPH_TIM17 RCC_APB2ENR_TIM17EN |
| AnnaBridge | 171:3a7713b1edbc | 193 | #define LL_APB1_GRP2_PERIPH_DBGMCU RCC_APB2ENR_DBGMCUEN |
| AnnaBridge | 171:3a7713b1edbc | 194 | /** |
| AnnaBridge | 171:3a7713b1edbc | 195 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 196 | */ |
| AnnaBridge | 171:3a7713b1edbc | 197 | |
| AnnaBridge | 171:3a7713b1edbc | 198 | /** |
| AnnaBridge | 171:3a7713b1edbc | 199 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 200 | */ |
| AnnaBridge | 171:3a7713b1edbc | 201 | |
| AnnaBridge | 171:3a7713b1edbc | 202 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 203 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 204 | /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions |
| AnnaBridge | 171:3a7713b1edbc | 205 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 206 | */ |
| AnnaBridge | 171:3a7713b1edbc | 207 | |
| AnnaBridge | 171:3a7713b1edbc | 208 | /** @defgroup BUS_LL_EF_AHB1 AHB1 |
| AnnaBridge | 171:3a7713b1edbc | 209 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 210 | */ |
| AnnaBridge | 171:3a7713b1edbc | 211 | |
| AnnaBridge | 171:3a7713b1edbc | 212 | /** |
| AnnaBridge | 171:3a7713b1edbc | 213 | * @brief Enable AHB1 peripherals clock. |
| AnnaBridge | 171:3a7713b1edbc | 214 | * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 215 | * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 216 | * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 217 | * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 218 | * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 219 | * AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 220 | * AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 221 | * AHBENR GPIOCEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 222 | * AHBENR GPIODEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 223 | * AHBENR GPIOEEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 224 | * AHBENR GPIOFEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 225 | * AHBENR TSCEN LL_AHB1_GRP1_EnableClock |
| AnnaBridge | 171:3a7713b1edbc | 226 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 227 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 171:3a7713b1edbc | 228 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 229 | * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM |
| AnnaBridge | 171:3a7713b1edbc | 230 | * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH |
| AnnaBridge | 171:3a7713b1edbc | 231 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 171:3a7713b1edbc | 232 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| AnnaBridge | 171:3a7713b1edbc | 233 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| AnnaBridge | 171:3a7713b1edbc | 234 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| AnnaBridge | 171:3a7713b1edbc | 235 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) |
| AnnaBridge | 171:3a7713b1edbc | 236 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) |
| AnnaBridge | 171:3a7713b1edbc | 237 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF |
| AnnaBridge | 171:3a7713b1edbc | 238 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) |
| AnnaBridge | 171:3a7713b1edbc | 239 | * |
| AnnaBridge | 171:3a7713b1edbc | 240 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 241 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 242 | */ |
| AnnaBridge | 171:3a7713b1edbc | 243 | __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 244 | { |
| AnnaBridge | 171:3a7713b1edbc | 245 | __IO uint32_t tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 246 | SET_BIT(RCC->AHBENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 247 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 171:3a7713b1edbc | 248 | tmpreg = READ_BIT(RCC->AHBENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 249 | (void)tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 250 | } |
| AnnaBridge | 171:3a7713b1edbc | 251 | |
| AnnaBridge | 171:3a7713b1edbc | 252 | /** |
| AnnaBridge | 171:3a7713b1edbc | 253 | * @brief Check if AHB1 peripheral clock is enabled or not |
| AnnaBridge | 171:3a7713b1edbc | 254 | * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 255 | * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 256 | * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 257 | * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 258 | * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 259 | * AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 260 | * AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 261 | * AHBENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 262 | * AHBENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 263 | * AHBENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 264 | * AHBENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 265 | * AHBENR TSCEN LL_AHB1_GRP1_IsEnabledClock |
| AnnaBridge | 171:3a7713b1edbc | 266 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 267 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 171:3a7713b1edbc | 268 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 269 | * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM |
| AnnaBridge | 171:3a7713b1edbc | 270 | * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH |
| AnnaBridge | 171:3a7713b1edbc | 271 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 171:3a7713b1edbc | 272 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| AnnaBridge | 171:3a7713b1edbc | 273 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| AnnaBridge | 171:3a7713b1edbc | 274 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| AnnaBridge | 171:3a7713b1edbc | 275 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) |
| AnnaBridge | 171:3a7713b1edbc | 276 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) |
| AnnaBridge | 171:3a7713b1edbc | 277 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF |
| AnnaBridge | 171:3a7713b1edbc | 278 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) |
| AnnaBridge | 171:3a7713b1edbc | 279 | * |
| AnnaBridge | 171:3a7713b1edbc | 280 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 281 | * @retval State of Periphs (1 or 0). |
| AnnaBridge | 171:3a7713b1edbc | 282 | */ |
| AnnaBridge | 171:3a7713b1edbc | 283 | __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 284 | { |
| AnnaBridge | 171:3a7713b1edbc | 285 | return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 286 | } |
| AnnaBridge | 171:3a7713b1edbc | 287 | |
| AnnaBridge | 171:3a7713b1edbc | 288 | /** |
| AnnaBridge | 171:3a7713b1edbc | 289 | * @brief Disable AHB1 peripherals clock. |
| AnnaBridge | 171:3a7713b1edbc | 290 | * @rmtoll AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 291 | * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 292 | * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 293 | * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 294 | * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 295 | * AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 296 | * AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 297 | * AHBENR GPIOCEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 298 | * AHBENR GPIODEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 299 | * AHBENR GPIOEEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 300 | * AHBENR GPIOFEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 301 | * AHBENR TSCEN LL_AHB1_GRP1_DisableClock |
| AnnaBridge | 171:3a7713b1edbc | 302 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 303 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 171:3a7713b1edbc | 304 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 305 | * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM |
| AnnaBridge | 171:3a7713b1edbc | 306 | * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH |
| AnnaBridge | 171:3a7713b1edbc | 307 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 171:3a7713b1edbc | 308 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| AnnaBridge | 171:3a7713b1edbc | 309 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| AnnaBridge | 171:3a7713b1edbc | 310 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| AnnaBridge | 171:3a7713b1edbc | 311 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) |
| AnnaBridge | 171:3a7713b1edbc | 312 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) |
| AnnaBridge | 171:3a7713b1edbc | 313 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF |
| AnnaBridge | 171:3a7713b1edbc | 314 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) |
| AnnaBridge | 171:3a7713b1edbc | 315 | * |
| AnnaBridge | 171:3a7713b1edbc | 316 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 317 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 318 | */ |
| AnnaBridge | 171:3a7713b1edbc | 319 | __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 320 | { |
| AnnaBridge | 171:3a7713b1edbc | 321 | CLEAR_BIT(RCC->AHBENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 322 | } |
| AnnaBridge | 171:3a7713b1edbc | 323 | |
| AnnaBridge | 171:3a7713b1edbc | 324 | /** |
| AnnaBridge | 171:3a7713b1edbc | 325 | * @brief Force AHB1 peripherals reset. |
| AnnaBridge | 171:3a7713b1edbc | 326 | * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 327 | * AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 328 | * AHBRSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 329 | * AHBRSTR GPIODRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 330 | * AHBRSTR GPIOERST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 331 | * AHBRSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 332 | * AHBRSTR TSCRST LL_AHB1_GRP1_ForceReset |
| AnnaBridge | 171:3a7713b1edbc | 333 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 334 | * @arg @ref LL_AHB1_GRP1_PERIPH_ALL |
| AnnaBridge | 171:3a7713b1edbc | 335 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| AnnaBridge | 171:3a7713b1edbc | 336 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| AnnaBridge | 171:3a7713b1edbc | 337 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| AnnaBridge | 171:3a7713b1edbc | 338 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) |
| AnnaBridge | 171:3a7713b1edbc | 339 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) |
| AnnaBridge | 171:3a7713b1edbc | 340 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF |
| AnnaBridge | 171:3a7713b1edbc | 341 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) |
| AnnaBridge | 171:3a7713b1edbc | 342 | * |
| AnnaBridge | 171:3a7713b1edbc | 343 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 344 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 345 | */ |
| AnnaBridge | 171:3a7713b1edbc | 346 | __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 347 | { |
| AnnaBridge | 171:3a7713b1edbc | 348 | SET_BIT(RCC->AHBRSTR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 349 | } |
| AnnaBridge | 171:3a7713b1edbc | 350 | |
| AnnaBridge | 171:3a7713b1edbc | 351 | /** |
| AnnaBridge | 171:3a7713b1edbc | 352 | * @brief Release AHB1 peripherals reset. |
| AnnaBridge | 171:3a7713b1edbc | 353 | * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 354 | * AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 355 | * AHBRSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 356 | * AHBRSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 357 | * AHBRSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 358 | * AHBRSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 359 | * AHBRSTR TSCRST LL_AHB1_GRP1_ReleaseReset |
| AnnaBridge | 171:3a7713b1edbc | 360 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 361 | * @arg @ref LL_AHB1_GRP1_PERIPH_ALL |
| AnnaBridge | 171:3a7713b1edbc | 362 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| AnnaBridge | 171:3a7713b1edbc | 363 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| AnnaBridge | 171:3a7713b1edbc | 364 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| AnnaBridge | 171:3a7713b1edbc | 365 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*) |
| AnnaBridge | 171:3a7713b1edbc | 366 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) |
| AnnaBridge | 171:3a7713b1edbc | 367 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF |
| AnnaBridge | 171:3a7713b1edbc | 368 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*) |
| AnnaBridge | 171:3a7713b1edbc | 369 | * |
| AnnaBridge | 171:3a7713b1edbc | 370 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 371 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 372 | */ |
| AnnaBridge | 171:3a7713b1edbc | 373 | __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 374 | { |
| AnnaBridge | 171:3a7713b1edbc | 375 | CLEAR_BIT(RCC->AHBRSTR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 376 | } |
| AnnaBridge | 171:3a7713b1edbc | 377 | |
| AnnaBridge | 171:3a7713b1edbc | 378 | /** |
| AnnaBridge | 171:3a7713b1edbc | 379 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 380 | */ |
| AnnaBridge | 171:3a7713b1edbc | 381 | |
| AnnaBridge | 171:3a7713b1edbc | 382 | /** @defgroup BUS_LL_EF_APB1_GRP1 APB1 GRP1 |
| AnnaBridge | 171:3a7713b1edbc | 383 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 384 | */ |
| AnnaBridge | 171:3a7713b1edbc | 385 | |
| AnnaBridge | 171:3a7713b1edbc | 386 | /** |
| AnnaBridge | 171:3a7713b1edbc | 387 | * @brief Enable APB1 peripherals clock (available in register 1). |
| AnnaBridge | 171:3a7713b1edbc | 388 | * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 389 | * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 390 | * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 391 | * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 392 | * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 393 | * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 394 | * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 395 | * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 396 | * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 397 | * APB1ENR USART4EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 398 | * APB1ENR USART5EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 399 | * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 400 | * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 401 | * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 402 | * APB1ENR CANEN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 403 | * APB1ENR CRSEN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 404 | * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 405 | * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 406 | * APB1ENR CECEN LL_APB1_GRP1_EnableClock |
| AnnaBridge | 171:3a7713b1edbc | 407 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 408 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 409 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 |
| AnnaBridge | 171:3a7713b1edbc | 410 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) |
| AnnaBridge | 171:3a7713b1edbc | 411 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
| AnnaBridge | 171:3a7713b1edbc | 412 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 |
| AnnaBridge | 171:3a7713b1edbc | 413 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 171:3a7713b1edbc | 414 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 415 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 416 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) |
| AnnaBridge | 171:3a7713b1edbc | 417 | * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) |
| AnnaBridge | 171:3a7713b1edbc | 418 | * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) |
| AnnaBridge | 171:3a7713b1edbc | 419 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 171:3a7713b1edbc | 420 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 421 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
| AnnaBridge | 171:3a7713b1edbc | 422 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) |
| AnnaBridge | 171:3a7713b1edbc | 423 | * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) |
| AnnaBridge | 171:3a7713b1edbc | 424 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 171:3a7713b1edbc | 425 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) |
| AnnaBridge | 171:3a7713b1edbc | 426 | * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) |
| AnnaBridge | 171:3a7713b1edbc | 427 | * |
| AnnaBridge | 171:3a7713b1edbc | 428 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 429 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 430 | */ |
| AnnaBridge | 171:3a7713b1edbc | 431 | __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 432 | { |
| AnnaBridge | 171:3a7713b1edbc | 433 | __IO uint32_t tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 434 | SET_BIT(RCC->APB1ENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 435 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 171:3a7713b1edbc | 436 | tmpreg = READ_BIT(RCC->APB1ENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 437 | (void)tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 438 | } |
| AnnaBridge | 171:3a7713b1edbc | 439 | |
| AnnaBridge | 171:3a7713b1edbc | 440 | /** |
| AnnaBridge | 171:3a7713b1edbc | 441 | * @brief Check if APB1 peripheral clock is enabled or not (available in register 1). |
| AnnaBridge | 171:3a7713b1edbc | 442 | * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 443 | * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 444 | * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 445 | * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 446 | * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 447 | * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 448 | * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 449 | * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 450 | * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 451 | * APB1ENR USART4EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 452 | * APB1ENR USART5EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 453 | * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 454 | * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 455 | * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 456 | * APB1ENR CANEN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 457 | * APB1ENR CRSEN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 458 | * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 459 | * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 460 | * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock |
| AnnaBridge | 171:3a7713b1edbc | 461 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 462 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 463 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 |
| AnnaBridge | 171:3a7713b1edbc | 464 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) |
| AnnaBridge | 171:3a7713b1edbc | 465 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
| AnnaBridge | 171:3a7713b1edbc | 466 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 |
| AnnaBridge | 171:3a7713b1edbc | 467 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 171:3a7713b1edbc | 468 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 469 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 470 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) |
| AnnaBridge | 171:3a7713b1edbc | 471 | * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) |
| AnnaBridge | 171:3a7713b1edbc | 472 | * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) |
| AnnaBridge | 171:3a7713b1edbc | 473 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 171:3a7713b1edbc | 474 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 475 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
| AnnaBridge | 171:3a7713b1edbc | 476 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) |
| AnnaBridge | 171:3a7713b1edbc | 477 | * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) |
| AnnaBridge | 171:3a7713b1edbc | 478 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 171:3a7713b1edbc | 479 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) |
| AnnaBridge | 171:3a7713b1edbc | 480 | * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) |
| AnnaBridge | 171:3a7713b1edbc | 481 | * |
| AnnaBridge | 171:3a7713b1edbc | 482 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 483 | * @retval State of Periphs (1 or 0). |
| AnnaBridge | 171:3a7713b1edbc | 484 | */ |
| AnnaBridge | 171:3a7713b1edbc | 485 | __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 486 | { |
| AnnaBridge | 171:3a7713b1edbc | 487 | return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 488 | } |
| AnnaBridge | 171:3a7713b1edbc | 489 | |
| AnnaBridge | 171:3a7713b1edbc | 490 | /** |
| AnnaBridge | 171:3a7713b1edbc | 491 | * @brief Disable APB1 peripherals clock (available in register 1). |
| AnnaBridge | 171:3a7713b1edbc | 492 | * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 493 | * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 494 | * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 495 | * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 496 | * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 497 | * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 498 | * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 499 | * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 500 | * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 501 | * APB1ENR USART4EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 502 | * APB1ENR USART5EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 503 | * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 504 | * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 505 | * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 506 | * APB1ENR CANEN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 507 | * APB1ENR CRSEN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 508 | * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 509 | * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 510 | * APB1ENR CECEN LL_APB1_GRP1_DisableClock |
| AnnaBridge | 171:3a7713b1edbc | 511 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 512 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 513 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 |
| AnnaBridge | 171:3a7713b1edbc | 514 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) |
| AnnaBridge | 171:3a7713b1edbc | 515 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
| AnnaBridge | 171:3a7713b1edbc | 516 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 |
| AnnaBridge | 171:3a7713b1edbc | 517 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 171:3a7713b1edbc | 518 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 519 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 520 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) |
| AnnaBridge | 171:3a7713b1edbc | 521 | * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) |
| AnnaBridge | 171:3a7713b1edbc | 522 | * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) |
| AnnaBridge | 171:3a7713b1edbc | 523 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 171:3a7713b1edbc | 524 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 525 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
| AnnaBridge | 171:3a7713b1edbc | 526 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) |
| AnnaBridge | 171:3a7713b1edbc | 527 | * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) |
| AnnaBridge | 171:3a7713b1edbc | 528 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 171:3a7713b1edbc | 529 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) |
| AnnaBridge | 171:3a7713b1edbc | 530 | * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) |
| AnnaBridge | 171:3a7713b1edbc | 531 | * |
| AnnaBridge | 171:3a7713b1edbc | 532 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 533 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 534 | */ |
| AnnaBridge | 171:3a7713b1edbc | 535 | __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 536 | { |
| AnnaBridge | 171:3a7713b1edbc | 537 | CLEAR_BIT(RCC->APB1ENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 538 | } |
| AnnaBridge | 171:3a7713b1edbc | 539 | |
| AnnaBridge | 171:3a7713b1edbc | 540 | /** |
| AnnaBridge | 171:3a7713b1edbc | 541 | * @brief Force APB1 peripherals reset (available in register 1). |
| AnnaBridge | 171:3a7713b1edbc | 542 | * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 543 | * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 544 | * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 545 | * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 546 | * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 547 | * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 548 | * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 549 | * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 550 | * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 551 | * APB1RSTR USART4RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 552 | * APB1RSTR USART5RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 553 | * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 554 | * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 555 | * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 556 | * APB1RSTR CANRST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 557 | * APB1RSTR CRSRST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 558 | * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 559 | * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 560 | * APB1RSTR CECRST LL_APB1_GRP1_ForceReset |
| AnnaBridge | 171:3a7713b1edbc | 561 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 562 | * @arg @ref LL_APB1_GRP1_PERIPH_ALL |
| AnnaBridge | 171:3a7713b1edbc | 563 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 564 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 |
| AnnaBridge | 171:3a7713b1edbc | 565 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) |
| AnnaBridge | 171:3a7713b1edbc | 566 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
| AnnaBridge | 171:3a7713b1edbc | 567 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 |
| AnnaBridge | 171:3a7713b1edbc | 568 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 171:3a7713b1edbc | 569 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 570 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 571 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) |
| AnnaBridge | 171:3a7713b1edbc | 572 | * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) |
| AnnaBridge | 171:3a7713b1edbc | 573 | * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) |
| AnnaBridge | 171:3a7713b1edbc | 574 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 171:3a7713b1edbc | 575 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 576 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
| AnnaBridge | 171:3a7713b1edbc | 577 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) |
| AnnaBridge | 171:3a7713b1edbc | 578 | * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) |
| AnnaBridge | 171:3a7713b1edbc | 579 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 171:3a7713b1edbc | 580 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) |
| AnnaBridge | 171:3a7713b1edbc | 581 | * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) |
| AnnaBridge | 171:3a7713b1edbc | 582 | * |
| AnnaBridge | 171:3a7713b1edbc | 583 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 584 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 585 | */ |
| AnnaBridge | 171:3a7713b1edbc | 586 | __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 587 | { |
| AnnaBridge | 171:3a7713b1edbc | 588 | SET_BIT(RCC->APB1RSTR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 589 | } |
| AnnaBridge | 171:3a7713b1edbc | 590 | |
| AnnaBridge | 171:3a7713b1edbc | 591 | /** |
| AnnaBridge | 171:3a7713b1edbc | 592 | * @brief Release APB1 peripherals reset (available in register 1). |
| AnnaBridge | 171:3a7713b1edbc | 593 | * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 594 | * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 595 | * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 596 | * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 597 | * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 598 | * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 599 | * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 600 | * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 601 | * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 602 | * APB1RSTR USART4RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 603 | * APB1RSTR USART5RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 604 | * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 605 | * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 606 | * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 607 | * APB1RSTR CANRST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 608 | * APB1RSTR CRSRST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 609 | * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 610 | * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 611 | * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset |
| AnnaBridge | 171:3a7713b1edbc | 612 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 613 | * @arg @ref LL_APB1_GRP1_PERIPH_ALL |
| AnnaBridge | 171:3a7713b1edbc | 614 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 615 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 |
| AnnaBridge | 171:3a7713b1edbc | 616 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) |
| AnnaBridge | 171:3a7713b1edbc | 617 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) |
| AnnaBridge | 171:3a7713b1edbc | 618 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 |
| AnnaBridge | 171:3a7713b1edbc | 619 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 171:3a7713b1edbc | 620 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 621 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 622 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) |
| AnnaBridge | 171:3a7713b1edbc | 623 | * @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*) |
| AnnaBridge | 171:3a7713b1edbc | 624 | * @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*) |
| AnnaBridge | 171:3a7713b1edbc | 625 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 171:3a7713b1edbc | 626 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 627 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
| AnnaBridge | 171:3a7713b1edbc | 628 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN (*) |
| AnnaBridge | 171:3a7713b1edbc | 629 | * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) |
| AnnaBridge | 171:3a7713b1edbc | 630 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 171:3a7713b1edbc | 631 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) |
| AnnaBridge | 171:3a7713b1edbc | 632 | * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) |
| AnnaBridge | 171:3a7713b1edbc | 633 | * |
| AnnaBridge | 171:3a7713b1edbc | 634 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 635 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 636 | */ |
| AnnaBridge | 171:3a7713b1edbc | 637 | __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 638 | { |
| AnnaBridge | 171:3a7713b1edbc | 639 | CLEAR_BIT(RCC->APB1RSTR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 640 | } |
| AnnaBridge | 171:3a7713b1edbc | 641 | |
| AnnaBridge | 171:3a7713b1edbc | 642 | /** |
| AnnaBridge | 171:3a7713b1edbc | 643 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 644 | */ |
| AnnaBridge | 171:3a7713b1edbc | 645 | |
| AnnaBridge | 171:3a7713b1edbc | 646 | /** @defgroup BUS_LL_EF_APB1_GRP2 APB1 GRP2 |
| AnnaBridge | 171:3a7713b1edbc | 647 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 648 | */ |
| AnnaBridge | 171:3a7713b1edbc | 649 | |
| AnnaBridge | 171:3a7713b1edbc | 650 | /** |
| AnnaBridge | 171:3a7713b1edbc | 651 | * @brief Enable APB1 peripherals clock (available in register 2). |
| AnnaBridge | 171:3a7713b1edbc | 652 | * @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 653 | * APB2ENR ADC1EN LL_APB1_GRP2_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 654 | * APB2ENR USART8EN LL_APB1_GRP2_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 655 | * APB2ENR USART7EN LL_APB1_GRP2_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 656 | * APB2ENR USART6EN LL_APB1_GRP2_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 657 | * APB2ENR TIM1EN LL_APB1_GRP2_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 658 | * APB2ENR SPI1EN LL_APB1_GRP2_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 659 | * APB2ENR USART1EN LL_APB1_GRP2_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 660 | * APB2ENR TIM15EN LL_APB1_GRP2_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 661 | * APB2ENR TIM16EN LL_APB1_GRP2_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 662 | * APB2ENR TIM17EN LL_APB1_GRP2_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 663 | * APB2ENR DBGMCUEN LL_APB1_GRP2_EnableClock |
| AnnaBridge | 171:3a7713b1edbc | 664 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 665 | * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG |
| AnnaBridge | 171:3a7713b1edbc | 666 | * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 |
| AnnaBridge | 171:3a7713b1edbc | 667 | * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*) |
| AnnaBridge | 171:3a7713b1edbc | 668 | * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*) |
| AnnaBridge | 171:3a7713b1edbc | 669 | * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*) |
| AnnaBridge | 171:3a7713b1edbc | 670 | * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 |
| AnnaBridge | 171:3a7713b1edbc | 671 | * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 |
| AnnaBridge | 171:3a7713b1edbc | 672 | * @arg @ref LL_APB1_GRP2_PERIPH_USART1 |
| AnnaBridge | 171:3a7713b1edbc | 673 | * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) |
| AnnaBridge | 171:3a7713b1edbc | 674 | * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 |
| AnnaBridge | 171:3a7713b1edbc | 675 | * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 |
| AnnaBridge | 171:3a7713b1edbc | 676 | * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU |
| AnnaBridge | 171:3a7713b1edbc | 677 | * |
| AnnaBridge | 171:3a7713b1edbc | 678 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 679 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 680 | */ |
| AnnaBridge | 171:3a7713b1edbc | 681 | __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 682 | { |
| AnnaBridge | 171:3a7713b1edbc | 683 | __IO uint32_t tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 684 | SET_BIT(RCC->APB2ENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 685 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 171:3a7713b1edbc | 686 | tmpreg = READ_BIT(RCC->APB2ENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 687 | (void)tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 688 | } |
| AnnaBridge | 171:3a7713b1edbc | 689 | |
| AnnaBridge | 171:3a7713b1edbc | 690 | /** |
| AnnaBridge | 171:3a7713b1edbc | 691 | * @brief Check if APB1 peripheral clock is enabled or not (available in register 2). |
| AnnaBridge | 171:3a7713b1edbc | 692 | * @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 693 | * APB2ENR ADC1EN LL_APB1_GRP2_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 694 | * APB2ENR USART8EN LL_APB1_GRP2_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 695 | * APB2ENR USART7EN LL_APB1_GRP2_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 696 | * APB2ENR USART6EN LL_APB1_GRP2_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 697 | * APB2ENR TIM1EN LL_APB1_GRP2_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 698 | * APB2ENR SPI1EN LL_APB1_GRP2_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 699 | * APB2ENR USART1EN LL_APB1_GRP2_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 700 | * APB2ENR TIM15EN LL_APB1_GRP2_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 701 | * APB2ENR TIM16EN LL_APB1_GRP2_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 702 | * APB2ENR TIM17EN LL_APB1_GRP2_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 703 | * APB2ENR DBGMCUEN LL_APB1_GRP2_IsEnabledClock |
| AnnaBridge | 171:3a7713b1edbc | 704 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 705 | * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG |
| AnnaBridge | 171:3a7713b1edbc | 706 | * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 |
| AnnaBridge | 171:3a7713b1edbc | 707 | * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*) |
| AnnaBridge | 171:3a7713b1edbc | 708 | * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*) |
| AnnaBridge | 171:3a7713b1edbc | 709 | * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*) |
| AnnaBridge | 171:3a7713b1edbc | 710 | * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 |
| AnnaBridge | 171:3a7713b1edbc | 711 | * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 |
| AnnaBridge | 171:3a7713b1edbc | 712 | * @arg @ref LL_APB1_GRP2_PERIPH_USART1 |
| AnnaBridge | 171:3a7713b1edbc | 713 | * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) |
| AnnaBridge | 171:3a7713b1edbc | 714 | * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 |
| AnnaBridge | 171:3a7713b1edbc | 715 | * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 |
| AnnaBridge | 171:3a7713b1edbc | 716 | * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU |
| AnnaBridge | 171:3a7713b1edbc | 717 | * |
| AnnaBridge | 171:3a7713b1edbc | 718 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 719 | * @retval State of Periphs (1 or 0). |
| AnnaBridge | 171:3a7713b1edbc | 720 | */ |
| AnnaBridge | 171:3a7713b1edbc | 721 | __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 722 | { |
| AnnaBridge | 171:3a7713b1edbc | 723 | return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 724 | } |
| AnnaBridge | 171:3a7713b1edbc | 725 | |
| AnnaBridge | 171:3a7713b1edbc | 726 | /** |
| AnnaBridge | 171:3a7713b1edbc | 727 | * @brief Disable APB1 peripherals clock (available in register 2). |
| AnnaBridge | 171:3a7713b1edbc | 728 | * @rmtoll APB2ENR SYSCFGEN LL_APB1_GRP2_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 729 | * APB2ENR ADC1EN LL_APB1_GRP2_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 730 | * APB2ENR USART8EN LL_APB1_GRP2_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 731 | * APB2ENR USART7EN LL_APB1_GRP2_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 732 | * APB2ENR USART6EN LL_APB1_GRP2_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 733 | * APB2ENR TIM1EN LL_APB1_GRP2_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 734 | * APB2ENR SPI1EN LL_APB1_GRP2_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 735 | * APB2ENR USART1EN LL_APB1_GRP2_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 736 | * APB2ENR TIM15EN LL_APB1_GRP2_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 737 | * APB2ENR TIM16EN LL_APB1_GRP2_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 738 | * APB2ENR TIM17EN LL_APB1_GRP2_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 739 | * APB2ENR DBGMCUEN LL_APB1_GRP2_DisableClock |
| AnnaBridge | 171:3a7713b1edbc | 740 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 741 | * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG |
| AnnaBridge | 171:3a7713b1edbc | 742 | * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 |
| AnnaBridge | 171:3a7713b1edbc | 743 | * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*) |
| AnnaBridge | 171:3a7713b1edbc | 744 | * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*) |
| AnnaBridge | 171:3a7713b1edbc | 745 | * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*) |
| AnnaBridge | 171:3a7713b1edbc | 746 | * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 |
| AnnaBridge | 171:3a7713b1edbc | 747 | * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 |
| AnnaBridge | 171:3a7713b1edbc | 748 | * @arg @ref LL_APB1_GRP2_PERIPH_USART1 |
| AnnaBridge | 171:3a7713b1edbc | 749 | * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) |
| AnnaBridge | 171:3a7713b1edbc | 750 | * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 |
| AnnaBridge | 171:3a7713b1edbc | 751 | * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 |
| AnnaBridge | 171:3a7713b1edbc | 752 | * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU |
| AnnaBridge | 171:3a7713b1edbc | 753 | * |
| AnnaBridge | 171:3a7713b1edbc | 754 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 755 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 756 | */ |
| AnnaBridge | 171:3a7713b1edbc | 757 | __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 758 | { |
| AnnaBridge | 171:3a7713b1edbc | 759 | CLEAR_BIT(RCC->APB2ENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 760 | } |
| AnnaBridge | 171:3a7713b1edbc | 761 | |
| AnnaBridge | 171:3a7713b1edbc | 762 | /** |
| AnnaBridge | 171:3a7713b1edbc | 763 | * @brief Force APB1 peripherals reset (available in register 2). |
| AnnaBridge | 171:3a7713b1edbc | 764 | * @rmtoll APB2RSTR SYSCFGRST LL_APB1_GRP2_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 765 | * APB2RSTR ADC1RST LL_APB1_GRP2_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 766 | * APB2RSTR USART8RST LL_APB1_GRP2_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 767 | * APB2RSTR USART7RST LL_APB1_GRP2_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 768 | * APB2RSTR USART6RST LL_APB1_GRP2_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 769 | * APB2RSTR TIM1RST LL_APB1_GRP2_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 770 | * APB2RSTR SPI1RST LL_APB1_GRP2_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 771 | * APB2RSTR USART1RST LL_APB1_GRP2_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 772 | * APB2RSTR TIM15RST LL_APB1_GRP2_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 773 | * APB2RSTR TIM16RST LL_APB1_GRP2_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 774 | * APB2RSTR TIM17RST LL_APB1_GRP2_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 775 | * APB2RSTR DBGMCURST LL_APB1_GRP2_ForceReset |
| AnnaBridge | 171:3a7713b1edbc | 776 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 777 | * @arg @ref LL_APB1_GRP2_PERIPH_ALL |
| AnnaBridge | 171:3a7713b1edbc | 778 | * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG |
| AnnaBridge | 171:3a7713b1edbc | 779 | * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 |
| AnnaBridge | 171:3a7713b1edbc | 780 | * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*) |
| AnnaBridge | 171:3a7713b1edbc | 781 | * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*) |
| AnnaBridge | 171:3a7713b1edbc | 782 | * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*) |
| AnnaBridge | 171:3a7713b1edbc | 783 | * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 |
| AnnaBridge | 171:3a7713b1edbc | 784 | * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 |
| AnnaBridge | 171:3a7713b1edbc | 785 | * @arg @ref LL_APB1_GRP2_PERIPH_USART1 |
| AnnaBridge | 171:3a7713b1edbc | 786 | * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) |
| AnnaBridge | 171:3a7713b1edbc | 787 | * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 |
| AnnaBridge | 171:3a7713b1edbc | 788 | * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 |
| AnnaBridge | 171:3a7713b1edbc | 789 | * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU |
| AnnaBridge | 171:3a7713b1edbc | 790 | * |
| AnnaBridge | 171:3a7713b1edbc | 791 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 792 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 793 | */ |
| AnnaBridge | 171:3a7713b1edbc | 794 | __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 795 | { |
| AnnaBridge | 171:3a7713b1edbc | 796 | SET_BIT(RCC->APB2RSTR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 797 | } |
| AnnaBridge | 171:3a7713b1edbc | 798 | |
| AnnaBridge | 171:3a7713b1edbc | 799 | /** |
| AnnaBridge | 171:3a7713b1edbc | 800 | * @brief Release APB1 peripherals reset (available in register 2). |
| AnnaBridge | 171:3a7713b1edbc | 801 | * @rmtoll APB2RSTR SYSCFGRST LL_APB1_GRP2_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 802 | * APB2RSTR ADC1RST LL_APB1_GRP2_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 803 | * APB2RSTR USART8RST LL_APB1_GRP2_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 804 | * APB2RSTR USART7RST LL_APB1_GRP2_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 805 | * APB2RSTR USART6RST LL_APB1_GRP2_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 806 | * APB2RSTR TIM1RST LL_APB1_GRP2_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 807 | * APB2RSTR SPI1RST LL_APB1_GRP2_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 808 | * APB2RSTR USART1RST LL_APB1_GRP2_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 809 | * APB2RSTR TIM15RST LL_APB1_GRP2_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 810 | * APB2RSTR TIM16RST LL_APB1_GRP2_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 811 | * APB2RSTR TIM17RST LL_APB1_GRP2_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 812 | * APB2RSTR DBGMCURST LL_APB1_GRP2_ReleaseReset |
| AnnaBridge | 171:3a7713b1edbc | 813 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 814 | * @arg @ref LL_APB1_GRP2_PERIPH_ALL |
| AnnaBridge | 171:3a7713b1edbc | 815 | * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG |
| AnnaBridge | 171:3a7713b1edbc | 816 | * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 |
| AnnaBridge | 171:3a7713b1edbc | 817 | * @arg @ref LL_APB1_GRP2_PERIPH_USART8 (*) |
| AnnaBridge | 171:3a7713b1edbc | 818 | * @arg @ref LL_APB1_GRP2_PERIPH_USART7 (*) |
| AnnaBridge | 171:3a7713b1edbc | 819 | * @arg @ref LL_APB1_GRP2_PERIPH_USART6 (*) |
| AnnaBridge | 171:3a7713b1edbc | 820 | * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 |
| AnnaBridge | 171:3a7713b1edbc | 821 | * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 |
| AnnaBridge | 171:3a7713b1edbc | 822 | * @arg @ref LL_APB1_GRP2_PERIPH_USART1 |
| AnnaBridge | 171:3a7713b1edbc | 823 | * @arg @ref LL_APB1_GRP2_PERIPH_TIM15 (*) |
| AnnaBridge | 171:3a7713b1edbc | 824 | * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 |
| AnnaBridge | 171:3a7713b1edbc | 825 | * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 |
| AnnaBridge | 171:3a7713b1edbc | 826 | * @arg @ref LL_APB1_GRP2_PERIPH_DBGMCU |
| AnnaBridge | 171:3a7713b1edbc | 827 | * |
| AnnaBridge | 171:3a7713b1edbc | 828 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 829 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 830 | */ |
| AnnaBridge | 171:3a7713b1edbc | 831 | __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 832 | { |
| AnnaBridge | 171:3a7713b1edbc | 833 | CLEAR_BIT(RCC->APB2RSTR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 834 | } |
| AnnaBridge | 171:3a7713b1edbc | 835 | |
| AnnaBridge | 171:3a7713b1edbc | 836 | /** |
| AnnaBridge | 171:3a7713b1edbc | 837 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 838 | */ |
| AnnaBridge | 171:3a7713b1edbc | 839 | |
| AnnaBridge | 171:3a7713b1edbc | 840 | |
| AnnaBridge | 171:3a7713b1edbc | 841 | /** |
| AnnaBridge | 171:3a7713b1edbc | 842 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 843 | */ |
| AnnaBridge | 171:3a7713b1edbc | 844 | |
| AnnaBridge | 171:3a7713b1edbc | 845 | /** |
| AnnaBridge | 171:3a7713b1edbc | 846 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 847 | */ |
| AnnaBridge | 171:3a7713b1edbc | 848 | |
| AnnaBridge | 171:3a7713b1edbc | 849 | #endif /* defined(RCC) */ |
| AnnaBridge | 171:3a7713b1edbc | 850 | |
| AnnaBridge | 171:3a7713b1edbc | 851 | /** |
| AnnaBridge | 171:3a7713b1edbc | 852 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 853 | */ |
| AnnaBridge | 171:3a7713b1edbc | 854 | |
| AnnaBridge | 171:3a7713b1edbc | 855 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 856 | } |
| AnnaBridge | 171:3a7713b1edbc | 857 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 858 | |
| AnnaBridge | 171:3a7713b1edbc | 859 | #endif /* __STM32F0xx_LL_BUS_H */ |
| AnnaBridge | 171:3a7713b1edbc | 860 | |
| AnnaBridge | 171:3a7713b1edbc | 861 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
