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TARGET_NUCLEO_F030R8/TOOLCHAIN_IAR/stm32f0xx_hal_tim_ex.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file stm32f0xx_hal_tim_ex.h
AnnaBridge 171:3a7713b1edbc 4 * @author MCD Application Team
AnnaBridge 171:3a7713b1edbc 5 * @brief Header file of TIM HAL Extended module.
AnnaBridge 171:3a7713b1edbc 6 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 7 * @attention
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 12 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 14 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 17 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 171:3a7713b1edbc 19 * may be used to endorse or promote products derived from this software
AnnaBridge 171:3a7713b1edbc 20 * without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 171:3a7713b1edbc 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 171:3a7713b1edbc 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 171:3a7713b1edbc 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 171:3a7713b1edbc 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 171:3a7713b1edbc 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 171:3a7713b1edbc 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 171:3a7713b1edbc 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 32 *
AnnaBridge 171:3a7713b1edbc 33 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 34 */
AnnaBridge 171:3a7713b1edbc 35
AnnaBridge 171:3a7713b1edbc 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 171:3a7713b1edbc 37 #ifndef __STM32F0xx_HAL_TIM_EX_H
AnnaBridge 171:3a7713b1edbc 38 #define __STM32F0xx_HAL_TIM_EX_H
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 41 extern "C" {
AnnaBridge 171:3a7713b1edbc 42 #endif
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 /* Includes ------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 45 #include "stm32f0xx_hal_def.h"
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /** @addtogroup STM32F0xx_HAL_Driver
AnnaBridge 171:3a7713b1edbc 48 * @{
AnnaBridge 171:3a7713b1edbc 49 */
AnnaBridge 171:3a7713b1edbc 50
AnnaBridge 171:3a7713b1edbc 51 /** @addtogroup TIMEx
AnnaBridge 171:3a7713b1edbc 52 * @{
AnnaBridge 171:3a7713b1edbc 53 */
AnnaBridge 171:3a7713b1edbc 54
AnnaBridge 171:3a7713b1edbc 55 /* Exported types ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 56 /** @defgroup TIMEx_Exported_Types TIMEx Exported Types
AnnaBridge 171:3a7713b1edbc 57 * @{
AnnaBridge 171:3a7713b1edbc 58 */
AnnaBridge 171:3a7713b1edbc 59
AnnaBridge 171:3a7713b1edbc 60
AnnaBridge 171:3a7713b1edbc 61 /**
AnnaBridge 171:3a7713b1edbc 62 * @brief TIM Hall sensor Configuration Structure definition
AnnaBridge 171:3a7713b1edbc 63 */
AnnaBridge 171:3a7713b1edbc 64
AnnaBridge 171:3a7713b1edbc 65 typedef struct
AnnaBridge 171:3a7713b1edbc 66 {
AnnaBridge 171:3a7713b1edbc 67
AnnaBridge 171:3a7713b1edbc 68 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
AnnaBridge 171:3a7713b1edbc 69 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
AnnaBridge 171:3a7713b1edbc 70
AnnaBridge 171:3a7713b1edbc 71 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
AnnaBridge 171:3a7713b1edbc 72 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
AnnaBridge 171:3a7713b1edbc 73
AnnaBridge 171:3a7713b1edbc 74 uint32_t IC1Filter; /*!< Specifies the input capture filter.
AnnaBridge 171:3a7713b1edbc 75 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
AnnaBridge 171:3a7713b1edbc 76 uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
AnnaBridge 171:3a7713b1edbc 77 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
AnnaBridge 171:3a7713b1edbc 78 } TIM_HallSensor_InitTypeDef;
AnnaBridge 171:3a7713b1edbc 79
AnnaBridge 171:3a7713b1edbc 80 /**
AnnaBridge 171:3a7713b1edbc 81 * @brief TIM Master configuration Structure definition
AnnaBridge 171:3a7713b1edbc 82 */
AnnaBridge 171:3a7713b1edbc 83 typedef struct {
AnnaBridge 171:3a7713b1edbc 84 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
AnnaBridge 171:3a7713b1edbc 85 This parameter can be a value of @ref TIM_Master_Mode_Selection */
AnnaBridge 171:3a7713b1edbc 86 uint32_t MasterSlaveMode; /*!< Master/slave mode selection
AnnaBridge 171:3a7713b1edbc 87 This parameter can be a value of @ref TIM_Master_Slave_Mode */
AnnaBridge 171:3a7713b1edbc 88 }TIM_MasterConfigTypeDef;
AnnaBridge 171:3a7713b1edbc 89
AnnaBridge 171:3a7713b1edbc 90 /**
AnnaBridge 171:3a7713b1edbc 91 * @brief TIM Break and Dead time configuration Structure definition
AnnaBridge 171:3a7713b1edbc 92 */
AnnaBridge 171:3a7713b1edbc 93 typedef struct
AnnaBridge 171:3a7713b1edbc 94 {
AnnaBridge 171:3a7713b1edbc 95 uint32_t OffStateRunMode; /*!< TIM off state in run mode
AnnaBridge 171:3a7713b1edbc 96 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
AnnaBridge 171:3a7713b1edbc 97 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
AnnaBridge 171:3a7713b1edbc 98 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
AnnaBridge 171:3a7713b1edbc 99 uint32_t LockLevel; /*!< TIM Lock level
AnnaBridge 171:3a7713b1edbc 100 This parameter can be a value of @ref TIM_Lock_level */
AnnaBridge 171:3a7713b1edbc 101 uint32_t DeadTime; /*!< TIM dead Time
AnnaBridge 171:3a7713b1edbc 102 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
AnnaBridge 171:3a7713b1edbc 103 uint32_t BreakState; /*!< TIM Break State
AnnaBridge 171:3a7713b1edbc 104 This parameter can be a value of @ref TIM_Break_Input_enable_disable */
AnnaBridge 171:3a7713b1edbc 105 uint32_t BreakPolarity; /*!< TIM Break input polarity
AnnaBridge 171:3a7713b1edbc 106 This parameter can be a value of @ref TIM_Break_Polarity */
AnnaBridge 171:3a7713b1edbc 107 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
AnnaBridge 171:3a7713b1edbc 108 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
AnnaBridge 171:3a7713b1edbc 109 } TIM_BreakDeadTimeConfigTypeDef;
AnnaBridge 171:3a7713b1edbc 110
AnnaBridge 171:3a7713b1edbc 111 /**
AnnaBridge 171:3a7713b1edbc 112 * @}
AnnaBridge 171:3a7713b1edbc 113 */
AnnaBridge 171:3a7713b1edbc 114
AnnaBridge 171:3a7713b1edbc 115 /* Exported constants --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 116 /** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants
AnnaBridge 171:3a7713b1edbc 117 * @{
AnnaBridge 171:3a7713b1edbc 118 */
AnnaBridge 171:3a7713b1edbc 119
AnnaBridge 171:3a7713b1edbc 120 /** @defgroup TIMEx_Remap TIMEx Remap
AnnaBridge 171:3a7713b1edbc 121 * @{
AnnaBridge 171:3a7713b1edbc 122 */
AnnaBridge 171:3a7713b1edbc 123
AnnaBridge 171:3a7713b1edbc 124 #define TIM_TIM14_GPIO (0x00000000) /*!< TIM14 TI1 is connected to GPIO */
AnnaBridge 171:3a7713b1edbc 125 #define TIM_TIM14_RTC (0x00000001) /*!< TIM14 TI1 is connected to RTC_clock */
AnnaBridge 171:3a7713b1edbc 126 #define TIM_TIM14_HSE (0x00000002) /*!< TIM14 TI1 is connected to HSE/32 */
AnnaBridge 171:3a7713b1edbc 127 #define TIM_TIM14_MCO (0x00000003) /*!< TIM14 TI1 is connected to MCO */
AnnaBridge 171:3a7713b1edbc 128 /**
AnnaBridge 171:3a7713b1edbc 129 * @}
AnnaBridge 171:3a7713b1edbc 130 */
AnnaBridge 171:3a7713b1edbc 131
AnnaBridge 171:3a7713b1edbc 132 /** @defgroup TIMEx_Clock_Clear_Input_Source TIMEx Clear Input Source
AnnaBridge 171:3a7713b1edbc 133 * @{
AnnaBridge 171:3a7713b1edbc 134 */
AnnaBridge 171:3a7713b1edbc 135 #define TIM_CLEARINPUTSOURCE_NONE (0x00000000U)
AnnaBridge 171:3a7713b1edbc 136 #define TIM_CLEARINPUTSOURCE_ETR (0x00000001U)
AnnaBridge 171:3a7713b1edbc 137 #if defined(STM32F051x8) || defined(STM32F058xx) || \
AnnaBridge 171:3a7713b1edbc 138 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
AnnaBridge 171:3a7713b1edbc 139 defined(STM32F091xC) || defined (STM32F098xx)
AnnaBridge 171:3a7713b1edbc 140 #define TIM_CLEARINPUTSOURCE_OCREFCLR (0x00000002U)
AnnaBridge 171:3a7713b1edbc 141 #endif /* STM32F051x8 || STM32F058xx || */
AnnaBridge 171:3a7713b1edbc 142 /* STM32F071xB || STM32F072xB || STM32F078xx || */
AnnaBridge 171:3a7713b1edbc 143 /* STM32F091xC || defined (STM32F098xx) */
AnnaBridge 171:3a7713b1edbc 144 /**
AnnaBridge 171:3a7713b1edbc 145 * @}
AnnaBridge 171:3a7713b1edbc 146 */
AnnaBridge 171:3a7713b1edbc 147
AnnaBridge 171:3a7713b1edbc 148 /**
AnnaBridge 171:3a7713b1edbc 149 * @}
AnnaBridge 171:3a7713b1edbc 150 */
AnnaBridge 171:3a7713b1edbc 151
AnnaBridge 171:3a7713b1edbc 152 /* Private Macros -----------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 153 /** @defgroup TIM_Private_Macros TIM Private Macros
AnnaBridge 171:3a7713b1edbc 154 * @{
AnnaBridge 171:3a7713b1edbc 155 */
AnnaBridge 171:3a7713b1edbc 156
AnnaBridge 171:3a7713b1edbc 157 #define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM_TIM14_GPIO) ||\
AnnaBridge 171:3a7713b1edbc 158 ((TIM_REMAP) == TIM_TIM14_RTC) ||\
AnnaBridge 171:3a7713b1edbc 159 ((TIM_REMAP) == TIM_TIM14_HSE) ||\
AnnaBridge 171:3a7713b1edbc 160 ((TIM_REMAP) == TIM_TIM14_MCO))
AnnaBridge 171:3a7713b1edbc 161
AnnaBridge 171:3a7713b1edbc 162 #define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFFU) /*!< BreakDead Time */
AnnaBridge 171:3a7713b1edbc 163
AnnaBridge 171:3a7713b1edbc 164 #if defined(STM32F051x8) || defined(STM32F058xx) || \
AnnaBridge 171:3a7713b1edbc 165 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
AnnaBridge 171:3a7713b1edbc 166 defined(STM32F091xC) || defined (STM32F098xx)
AnnaBridge 171:3a7713b1edbc 167 #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
AnnaBridge 171:3a7713b1edbc 168 ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) || \
AnnaBridge 171:3a7713b1edbc 169 ((SOURCE) == TIM_CLEARINPUTSOURCE_OCREFCLR))
AnnaBridge 171:3a7713b1edbc 170 #else
AnnaBridge 171:3a7713b1edbc 171 #define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \
AnnaBridge 171:3a7713b1edbc 172 ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
AnnaBridge 171:3a7713b1edbc 173 #endif /* STM32F051x8 || STM32F058xx || */
AnnaBridge 171:3a7713b1edbc 174 /* STM32F071xB || STM32F072xB || STM32F078xx || */
AnnaBridge 171:3a7713b1edbc 175 /* STM32F091xC || defined (STM32F098xx) */
AnnaBridge 171:3a7713b1edbc 176 /**
AnnaBridge 171:3a7713b1edbc 177 * @}
AnnaBridge 171:3a7713b1edbc 178 */
AnnaBridge 171:3a7713b1edbc 179
AnnaBridge 171:3a7713b1edbc 180 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 181
AnnaBridge 171:3a7713b1edbc 182 /* Exported functions --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 183 /** @addtogroup TIMEx_Exported_Functions
AnnaBridge 171:3a7713b1edbc 184 * @{
AnnaBridge 171:3a7713b1edbc 185 */
AnnaBridge 171:3a7713b1edbc 186
AnnaBridge 171:3a7713b1edbc 187 /** @addtogroup TIMEx_Exported_Functions_Group1
AnnaBridge 171:3a7713b1edbc 188 * @{
AnnaBridge 171:3a7713b1edbc 189 */
AnnaBridge 171:3a7713b1edbc 190 /* Timer Hall Sensor functions **********************************************/
AnnaBridge 171:3a7713b1edbc 191 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig);
AnnaBridge 171:3a7713b1edbc 192 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 193
AnnaBridge 171:3a7713b1edbc 194 void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 195 void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 196
AnnaBridge 171:3a7713b1edbc 197 /* Blocking mode: Polling */
AnnaBridge 171:3a7713b1edbc 198 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 199 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 200 /* Non-Blocking mode: Interrupt */
AnnaBridge 171:3a7713b1edbc 201 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 202 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 203 /* Non-Blocking mode: DMA */
AnnaBridge 171:3a7713b1edbc 204 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
AnnaBridge 171:3a7713b1edbc 205 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 206 /**
AnnaBridge 171:3a7713b1edbc 207 * @}
AnnaBridge 171:3a7713b1edbc 208 */
AnnaBridge 171:3a7713b1edbc 209
AnnaBridge 171:3a7713b1edbc 210 /** @addtogroup TIMEx_Exported_Functions_Group2
AnnaBridge 171:3a7713b1edbc 211 * @{
AnnaBridge 171:3a7713b1edbc 212 */
AnnaBridge 171:3a7713b1edbc 213 /* Timer Complementary Output Compare functions *****************************/
AnnaBridge 171:3a7713b1edbc 214 /* Blocking mode: Polling */
AnnaBridge 171:3a7713b1edbc 215 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 171:3a7713b1edbc 216 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 171:3a7713b1edbc 217
AnnaBridge 171:3a7713b1edbc 218 /* Non-Blocking mode: Interrupt */
AnnaBridge 171:3a7713b1edbc 219 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 171:3a7713b1edbc 220 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 171:3a7713b1edbc 221
AnnaBridge 171:3a7713b1edbc 222 /* Non-Blocking mode: DMA */
AnnaBridge 171:3a7713b1edbc 223 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
AnnaBridge 171:3a7713b1edbc 224 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 171:3a7713b1edbc 225 /**
AnnaBridge 171:3a7713b1edbc 226 * @}
AnnaBridge 171:3a7713b1edbc 227 */
AnnaBridge 171:3a7713b1edbc 228
AnnaBridge 171:3a7713b1edbc 229 /** @addtogroup TIMEx_Exported_Functions_Group3
AnnaBridge 171:3a7713b1edbc 230 * @{
AnnaBridge 171:3a7713b1edbc 231 */
AnnaBridge 171:3a7713b1edbc 232 /* Timer Complementary PWM functions ****************************************/
AnnaBridge 171:3a7713b1edbc 233 /* Blocking mode: Polling */
AnnaBridge 171:3a7713b1edbc 234 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 171:3a7713b1edbc 235 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 171:3a7713b1edbc 236
AnnaBridge 171:3a7713b1edbc 237 /* Non-Blocking mode: Interrupt */
AnnaBridge 171:3a7713b1edbc 238 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 171:3a7713b1edbc 239 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 171:3a7713b1edbc 240 /* Non-Blocking mode: DMA */
AnnaBridge 171:3a7713b1edbc 241 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
AnnaBridge 171:3a7713b1edbc 242 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
AnnaBridge 171:3a7713b1edbc 243 /**
AnnaBridge 171:3a7713b1edbc 244 * @}
AnnaBridge 171:3a7713b1edbc 245 */
AnnaBridge 171:3a7713b1edbc 246
AnnaBridge 171:3a7713b1edbc 247 /** @addtogroup TIMEx_Exported_Functions_Group4
AnnaBridge 171:3a7713b1edbc 248 * @{
AnnaBridge 171:3a7713b1edbc 249 */
AnnaBridge 171:3a7713b1edbc 250 /* Timer Complementary One Pulse functions **********************************/
AnnaBridge 171:3a7713b1edbc 251 /* Blocking mode: Polling */
AnnaBridge 171:3a7713b1edbc 252 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge 171:3a7713b1edbc 253 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge 171:3a7713b1edbc 254
AnnaBridge 171:3a7713b1edbc 255 /* Non-Blocking mode: Interrupt */
AnnaBridge 171:3a7713b1edbc 256 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge 171:3a7713b1edbc 257 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
AnnaBridge 171:3a7713b1edbc 258 /**
AnnaBridge 171:3a7713b1edbc 259 * @}
AnnaBridge 171:3a7713b1edbc 260 */
AnnaBridge 171:3a7713b1edbc 261
AnnaBridge 171:3a7713b1edbc 262 /** @addtogroup TIMEx_Exported_Functions_Group5
AnnaBridge 171:3a7713b1edbc 263 * @{
AnnaBridge 171:3a7713b1edbc 264 */
AnnaBridge 171:3a7713b1edbc 265 /* Extended Control functions ************************************************/
AnnaBridge 171:3a7713b1edbc 266 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
AnnaBridge 171:3a7713b1edbc 267 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
AnnaBridge 171:3a7713b1edbc 268 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
AnnaBridge 171:3a7713b1edbc 269 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig);
AnnaBridge 171:3a7713b1edbc 270 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
AnnaBridge 171:3a7713b1edbc 271 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
AnnaBridge 171:3a7713b1edbc 272 /**
AnnaBridge 171:3a7713b1edbc 273 * @}
AnnaBridge 171:3a7713b1edbc 274 */
AnnaBridge 171:3a7713b1edbc 275
AnnaBridge 171:3a7713b1edbc 276 /** @addtogroup TIMEx_Exported_Functions_Group6
AnnaBridge 171:3a7713b1edbc 277 * @{
AnnaBridge 171:3a7713b1edbc 278 */
AnnaBridge 171:3a7713b1edbc 279 /* Extension Callback *********************************************************/
AnnaBridge 171:3a7713b1edbc 280 void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 281 void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 282 /**
AnnaBridge 171:3a7713b1edbc 283 * @}
AnnaBridge 171:3a7713b1edbc 284 */
AnnaBridge 171:3a7713b1edbc 285
AnnaBridge 171:3a7713b1edbc 286 /** @addtogroup TIMEx_Exported_Functions_Group7
AnnaBridge 171:3a7713b1edbc 287 * @{
AnnaBridge 171:3a7713b1edbc 288 */
AnnaBridge 171:3a7713b1edbc 289 /* Extension Peripheral State functions **************************************/
AnnaBridge 171:3a7713b1edbc 290 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
AnnaBridge 171:3a7713b1edbc 291 /**
AnnaBridge 171:3a7713b1edbc 292 * @}
AnnaBridge 171:3a7713b1edbc 293 */
AnnaBridge 171:3a7713b1edbc 294
AnnaBridge 171:3a7713b1edbc 295 /**
AnnaBridge 171:3a7713b1edbc 296 * @}
AnnaBridge 171:3a7713b1edbc 297 */
AnnaBridge 171:3a7713b1edbc 298 /* End of exported functions -------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 299
AnnaBridge 171:3a7713b1edbc 300 /* Private functions----------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 301 /** @defgroup TIMEx_Private_Functions TIMEx Private Functions
AnnaBridge 171:3a7713b1edbc 302 * @{
AnnaBridge 171:3a7713b1edbc 303 */
AnnaBridge 171:3a7713b1edbc 304 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
AnnaBridge 171:3a7713b1edbc 305 /**
AnnaBridge 171:3a7713b1edbc 306 * @}
AnnaBridge 171:3a7713b1edbc 307 */
AnnaBridge 171:3a7713b1edbc 308 /* End of private functions --------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 309
AnnaBridge 171:3a7713b1edbc 310 /**
AnnaBridge 171:3a7713b1edbc 311 * @}
AnnaBridge 171:3a7713b1edbc 312 */
AnnaBridge 171:3a7713b1edbc 313
AnnaBridge 171:3a7713b1edbc 314 /**
AnnaBridge 171:3a7713b1edbc 315 * @}
AnnaBridge 171:3a7713b1edbc 316 */
AnnaBridge 171:3a7713b1edbc 317
AnnaBridge 171:3a7713b1edbc 318 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 319 }
AnnaBridge 171:3a7713b1edbc 320 #endif
AnnaBridge 171:3a7713b1edbc 321
AnnaBridge 171:3a7713b1edbc 322
AnnaBridge 171:3a7713b1edbc 323 #endif /* __STM32F0xx_HAL_TIM_EX_H */
AnnaBridge 171:3a7713b1edbc 324
AnnaBridge 171:3a7713b1edbc 325 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/