mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F030R8/TOOLCHAIN_IAR/stm32f0xx_hal_dma.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file stm32f0xx_hal_dma.h
AnnaBridge 171:3a7713b1edbc 4 * @author MCD Application Team
AnnaBridge 171:3a7713b1edbc 5 * @brief Header file of DMA HAL module.
AnnaBridge 171:3a7713b1edbc 6 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 7 * @attention
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 12 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 14 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 17 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 171:3a7713b1edbc 19 * may be used to endorse or promote products derived from this software
AnnaBridge 171:3a7713b1edbc 20 * without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 171:3a7713b1edbc 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 171:3a7713b1edbc 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 171:3a7713b1edbc 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 171:3a7713b1edbc 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 171:3a7713b1edbc 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 171:3a7713b1edbc 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 171:3a7713b1edbc 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 32 *
AnnaBridge 171:3a7713b1edbc 33 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 34 */
AnnaBridge 171:3a7713b1edbc 35
AnnaBridge 171:3a7713b1edbc 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 171:3a7713b1edbc 37 #ifndef __STM32F0xx_HAL_DMA_H
AnnaBridge 171:3a7713b1edbc 38 #define __STM32F0xx_HAL_DMA_H
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 41 extern "C" {
AnnaBridge 171:3a7713b1edbc 42 #endif
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 /* Includes ------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 45 #include "stm32f0xx_hal_def.h"
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /** @addtogroup STM32F0xx_HAL_Driver
AnnaBridge 171:3a7713b1edbc 48 * @{
AnnaBridge 171:3a7713b1edbc 49 */
AnnaBridge 171:3a7713b1edbc 50
AnnaBridge 171:3a7713b1edbc 51 /** @addtogroup DMA
AnnaBridge 171:3a7713b1edbc 52 * @{
AnnaBridge 171:3a7713b1edbc 53 */
AnnaBridge 171:3a7713b1edbc 54
AnnaBridge 171:3a7713b1edbc 55 /* Exported types ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 56
AnnaBridge 171:3a7713b1edbc 57 /** @defgroup DMA_Exported_Types DMA Exported Types
AnnaBridge 171:3a7713b1edbc 58 * @{
AnnaBridge 171:3a7713b1edbc 59 */
AnnaBridge 171:3a7713b1edbc 60
AnnaBridge 171:3a7713b1edbc 61 /**
AnnaBridge 171:3a7713b1edbc 62 * @brief DMA Configuration Structure definition
AnnaBridge 171:3a7713b1edbc 63 */
AnnaBridge 171:3a7713b1edbc 64 typedef struct
AnnaBridge 171:3a7713b1edbc 65 {
AnnaBridge 171:3a7713b1edbc 66 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
AnnaBridge 171:3a7713b1edbc 67 from memory to memory or from peripheral to memory.
AnnaBridge 171:3a7713b1edbc 68 This parameter can be a value of @ref DMA_Data_transfer_direction */
AnnaBridge 171:3a7713b1edbc 69
AnnaBridge 171:3a7713b1edbc 70 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
AnnaBridge 171:3a7713b1edbc 71 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
AnnaBridge 171:3a7713b1edbc 72
AnnaBridge 171:3a7713b1edbc 73 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
AnnaBridge 171:3a7713b1edbc 74 This parameter can be a value of @ref DMA_Memory_incremented_mode */
AnnaBridge 171:3a7713b1edbc 75
AnnaBridge 171:3a7713b1edbc 76 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
AnnaBridge 171:3a7713b1edbc 77 This parameter can be a value of @ref DMA_Peripheral_data_size */
AnnaBridge 171:3a7713b1edbc 78
AnnaBridge 171:3a7713b1edbc 79 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
AnnaBridge 171:3a7713b1edbc 80 This parameter can be a value of @ref DMA_Memory_data_size */
AnnaBridge 171:3a7713b1edbc 81
AnnaBridge 171:3a7713b1edbc 82 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
AnnaBridge 171:3a7713b1edbc 83 This parameter can be a value of @ref DMA_mode
AnnaBridge 171:3a7713b1edbc 84 @note The circular buffer mode cannot be used if the memory-to-memory
AnnaBridge 171:3a7713b1edbc 85 data transfer is configured on the selected Channel */
AnnaBridge 171:3a7713b1edbc 86
AnnaBridge 171:3a7713b1edbc 87 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
AnnaBridge 171:3a7713b1edbc 88 This parameter can be a value of @ref DMA_Priority_level */
AnnaBridge 171:3a7713b1edbc 89 } DMA_InitTypeDef;
AnnaBridge 171:3a7713b1edbc 90
AnnaBridge 171:3a7713b1edbc 91 /**
AnnaBridge 171:3a7713b1edbc 92 * @brief HAL DMA State structures definition
AnnaBridge 171:3a7713b1edbc 93 */
AnnaBridge 171:3a7713b1edbc 94 typedef enum
AnnaBridge 171:3a7713b1edbc 95 {
AnnaBridge 171:3a7713b1edbc 96 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
AnnaBridge 171:3a7713b1edbc 97 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
AnnaBridge 171:3a7713b1edbc 98 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
AnnaBridge 171:3a7713b1edbc 99 HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */
AnnaBridge 171:3a7713b1edbc 100 }HAL_DMA_StateTypeDef;
AnnaBridge 171:3a7713b1edbc 101
AnnaBridge 171:3a7713b1edbc 102 /**
AnnaBridge 171:3a7713b1edbc 103 * @brief HAL DMA Error Code structure definition
AnnaBridge 171:3a7713b1edbc 104 */
AnnaBridge 171:3a7713b1edbc 105 typedef enum
AnnaBridge 171:3a7713b1edbc 106 {
AnnaBridge 171:3a7713b1edbc 107 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
AnnaBridge 171:3a7713b1edbc 108 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
AnnaBridge 171:3a7713b1edbc 109 }HAL_DMA_LevelCompleteTypeDef;
AnnaBridge 171:3a7713b1edbc 110
AnnaBridge 171:3a7713b1edbc 111 /**
AnnaBridge 171:3a7713b1edbc 112 * @brief HAL DMA Callback ID structure definition
AnnaBridge 171:3a7713b1edbc 113 */
AnnaBridge 171:3a7713b1edbc 114 typedef enum
AnnaBridge 171:3a7713b1edbc 115 {
AnnaBridge 171:3a7713b1edbc 116 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
AnnaBridge 171:3a7713b1edbc 117 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
AnnaBridge 171:3a7713b1edbc 118 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
AnnaBridge 171:3a7713b1edbc 119 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
AnnaBridge 171:3a7713b1edbc 120 HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
AnnaBridge 171:3a7713b1edbc 121
AnnaBridge 171:3a7713b1edbc 122 }HAL_DMA_CallbackIDTypeDef;
AnnaBridge 171:3a7713b1edbc 123
AnnaBridge 171:3a7713b1edbc 124 /**
AnnaBridge 171:3a7713b1edbc 125 * @brief DMA handle Structure definition
AnnaBridge 171:3a7713b1edbc 126 */
AnnaBridge 171:3a7713b1edbc 127 typedef struct __DMA_HandleTypeDef
AnnaBridge 171:3a7713b1edbc 128 {
AnnaBridge 171:3a7713b1edbc 129 DMA_Channel_TypeDef *Instance; /*!< Register base address */
AnnaBridge 171:3a7713b1edbc 130
AnnaBridge 171:3a7713b1edbc 131 DMA_InitTypeDef Init; /*!< DMA communication parameters */
AnnaBridge 171:3a7713b1edbc 132
AnnaBridge 171:3a7713b1edbc 133 HAL_LockTypeDef Lock; /*!< DMA locking object */
AnnaBridge 171:3a7713b1edbc 134
AnnaBridge 171:3a7713b1edbc 135 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
AnnaBridge 171:3a7713b1edbc 136
AnnaBridge 171:3a7713b1edbc 137 void *Parent; /*!< Parent object state */
AnnaBridge 171:3a7713b1edbc 138
AnnaBridge 171:3a7713b1edbc 139 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
AnnaBridge 171:3a7713b1edbc 140
AnnaBridge 171:3a7713b1edbc 141 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
AnnaBridge 171:3a7713b1edbc 142
AnnaBridge 171:3a7713b1edbc 143 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
AnnaBridge 171:3a7713b1edbc 144
AnnaBridge 171:3a7713b1edbc 145 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
AnnaBridge 171:3a7713b1edbc 146
AnnaBridge 171:3a7713b1edbc 147 __IO uint32_t ErrorCode; /*!< DMA Error code */
AnnaBridge 171:3a7713b1edbc 148
AnnaBridge 171:3a7713b1edbc 149 DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
AnnaBridge 171:3a7713b1edbc 150
AnnaBridge 171:3a7713b1edbc 151 uint32_t ChannelIndex; /*!< DMA Channel Index */
AnnaBridge 171:3a7713b1edbc 152 } DMA_HandleTypeDef;
AnnaBridge 171:3a7713b1edbc 153
AnnaBridge 171:3a7713b1edbc 154 /**
AnnaBridge 171:3a7713b1edbc 155 * @}
AnnaBridge 171:3a7713b1edbc 156 */
AnnaBridge 171:3a7713b1edbc 157
AnnaBridge 171:3a7713b1edbc 158 /* Exported constants --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 159
AnnaBridge 171:3a7713b1edbc 160 /** @defgroup DMA_Exported_Constants DMA Exported Constants
AnnaBridge 171:3a7713b1edbc 161 * @{
AnnaBridge 171:3a7713b1edbc 162 */
AnnaBridge 171:3a7713b1edbc 163
AnnaBridge 171:3a7713b1edbc 164 /** @defgroup DMA_Error_Code DMA Error Code
AnnaBridge 171:3a7713b1edbc 165 * @{
AnnaBridge 171:3a7713b1edbc 166 */
AnnaBridge 171:3a7713b1edbc 167 #define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */
AnnaBridge 171:3a7713b1edbc 168 #define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */
AnnaBridge 171:3a7713b1edbc 169 #define HAL_DMA_ERROR_NO_XFER (0x00000004U) /*!< no ongoin transfer */
AnnaBridge 171:3a7713b1edbc 170 #define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
AnnaBridge 171:3a7713b1edbc 171 #define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */
AnnaBridge 171:3a7713b1edbc 172 /**
AnnaBridge 171:3a7713b1edbc 173 * @}
AnnaBridge 171:3a7713b1edbc 174 */
AnnaBridge 171:3a7713b1edbc 175
AnnaBridge 171:3a7713b1edbc 176 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
AnnaBridge 171:3a7713b1edbc 177 * @{
AnnaBridge 171:3a7713b1edbc 178 */
AnnaBridge 171:3a7713b1edbc 179 #define DMA_PERIPH_TO_MEMORY (0x00000000U) /*!< Peripheral to memory direction */
AnnaBridge 171:3a7713b1edbc 180 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
AnnaBridge 171:3a7713b1edbc 181 #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */
AnnaBridge 171:3a7713b1edbc 182
AnnaBridge 171:3a7713b1edbc 183 /**
AnnaBridge 171:3a7713b1edbc 184 * @}
AnnaBridge 171:3a7713b1edbc 185 */
AnnaBridge 171:3a7713b1edbc 186
AnnaBridge 171:3a7713b1edbc 187 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
AnnaBridge 171:3a7713b1edbc 188 * @{
AnnaBridge 171:3a7713b1edbc 189 */
AnnaBridge 171:3a7713b1edbc 190 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
AnnaBridge 171:3a7713b1edbc 191 #define DMA_PINC_DISABLE (0x00000000U) /*!< Peripheral increment mode Disable */
AnnaBridge 171:3a7713b1edbc 192 /**
AnnaBridge 171:3a7713b1edbc 193 * @}
AnnaBridge 171:3a7713b1edbc 194 */
AnnaBridge 171:3a7713b1edbc 195
AnnaBridge 171:3a7713b1edbc 196 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
AnnaBridge 171:3a7713b1edbc 197 * @{
AnnaBridge 171:3a7713b1edbc 198 */
AnnaBridge 171:3a7713b1edbc 199 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
AnnaBridge 171:3a7713b1edbc 200 #define DMA_MINC_DISABLE (0x00000000U) /*!< Memory increment mode Disable */
AnnaBridge 171:3a7713b1edbc 201 /**
AnnaBridge 171:3a7713b1edbc 202 * @}
AnnaBridge 171:3a7713b1edbc 203 */
AnnaBridge 171:3a7713b1edbc 204
AnnaBridge 171:3a7713b1edbc 205 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
AnnaBridge 171:3a7713b1edbc 206 * @{
AnnaBridge 171:3a7713b1edbc 207 */
AnnaBridge 171:3a7713b1edbc 208 #define DMA_PDATAALIGN_BYTE (0x00000000U) /*!< Peripheral data alignment : Byte */
AnnaBridge 171:3a7713b1edbc 209 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
AnnaBridge 171:3a7713b1edbc 210 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
AnnaBridge 171:3a7713b1edbc 211 /**
AnnaBridge 171:3a7713b1edbc 212 * @}
AnnaBridge 171:3a7713b1edbc 213 */
AnnaBridge 171:3a7713b1edbc 214
AnnaBridge 171:3a7713b1edbc 215 /** @defgroup DMA_Memory_data_size DMA Memory data size
AnnaBridge 171:3a7713b1edbc 216 * @{
AnnaBridge 171:3a7713b1edbc 217 */
AnnaBridge 171:3a7713b1edbc 218 #define DMA_MDATAALIGN_BYTE (0x00000000U) /*!< Memory data alignment : Byte */
AnnaBridge 171:3a7713b1edbc 219 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
AnnaBridge 171:3a7713b1edbc 220 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
AnnaBridge 171:3a7713b1edbc 221 /**
AnnaBridge 171:3a7713b1edbc 222 * @}
AnnaBridge 171:3a7713b1edbc 223 */
AnnaBridge 171:3a7713b1edbc 224
AnnaBridge 171:3a7713b1edbc 225 /** @defgroup DMA_mode DMA mode
AnnaBridge 171:3a7713b1edbc 226 * @{
AnnaBridge 171:3a7713b1edbc 227 */
AnnaBridge 171:3a7713b1edbc 228 #define DMA_NORMAL (0x00000000U) /*!< Normal Mode */
AnnaBridge 171:3a7713b1edbc 229 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
AnnaBridge 171:3a7713b1edbc 230 /**
AnnaBridge 171:3a7713b1edbc 231 * @}
AnnaBridge 171:3a7713b1edbc 232 */
AnnaBridge 171:3a7713b1edbc 233
AnnaBridge 171:3a7713b1edbc 234 /** @defgroup DMA_Priority_level DMA Priority level
AnnaBridge 171:3a7713b1edbc 235 * @{
AnnaBridge 171:3a7713b1edbc 236 */
AnnaBridge 171:3a7713b1edbc 237 #define DMA_PRIORITY_LOW (0x00000000U) /*!< Priority level : Low */
AnnaBridge 171:3a7713b1edbc 238 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
AnnaBridge 171:3a7713b1edbc 239 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
AnnaBridge 171:3a7713b1edbc 240 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
AnnaBridge 171:3a7713b1edbc 241 /**
AnnaBridge 171:3a7713b1edbc 242 * @}
AnnaBridge 171:3a7713b1edbc 243 */
AnnaBridge 171:3a7713b1edbc 244
AnnaBridge 171:3a7713b1edbc 245
AnnaBridge 171:3a7713b1edbc 246 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
AnnaBridge 171:3a7713b1edbc 247 * @{
AnnaBridge 171:3a7713b1edbc 248 */
AnnaBridge 171:3a7713b1edbc 249 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
AnnaBridge 171:3a7713b1edbc 250 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
AnnaBridge 171:3a7713b1edbc 251 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
AnnaBridge 171:3a7713b1edbc 252 /**
AnnaBridge 171:3a7713b1edbc 253 * @}
AnnaBridge 171:3a7713b1edbc 254 */
AnnaBridge 171:3a7713b1edbc 255
AnnaBridge 171:3a7713b1edbc 256 /** @defgroup DMA_flag_definitions DMA flag definitions
AnnaBridge 171:3a7713b1edbc 257 * @{
AnnaBridge 171:3a7713b1edbc 258 */
AnnaBridge 171:3a7713b1edbc 259
AnnaBridge 171:3a7713b1edbc 260 #define DMA_FLAG_GL1 (0x00000001U) /*!< Channel 1 global interrupt flag */
AnnaBridge 171:3a7713b1edbc 261 #define DMA_FLAG_TC1 (0x00000002U) /*!< Channel 1 transfer complete flag */
AnnaBridge 171:3a7713b1edbc 262 #define DMA_FLAG_HT1 (0x00000004U) /*!< Channel 1 half transfer flag */
AnnaBridge 171:3a7713b1edbc 263 #define DMA_FLAG_TE1 (0x00000008U) /*!< Channel 1 transfer error flag */
AnnaBridge 171:3a7713b1edbc 264 #define DMA_FLAG_GL2 (0x00000010U) /*!< Channel 2 global interrupt flag */
AnnaBridge 171:3a7713b1edbc 265 #define DMA_FLAG_TC2 (0x00000020U) /*!< Channel 2 transfer complete flag */
AnnaBridge 171:3a7713b1edbc 266 #define DMA_FLAG_HT2 (0x00000040U) /*!< Channel 2 half transfer flag */
AnnaBridge 171:3a7713b1edbc 267 #define DMA_FLAG_TE2 (0x00000080U) /*!< Channel 2 transfer error flag */
AnnaBridge 171:3a7713b1edbc 268 #define DMA_FLAG_GL3 (0x00000100U) /*!< Channel 3 global interrupt flag */
AnnaBridge 171:3a7713b1edbc 269 #define DMA_FLAG_TC3 (0x00000200U) /*!< Channel 3 transfer complete flag */
AnnaBridge 171:3a7713b1edbc 270 #define DMA_FLAG_HT3 (0x00000400U) /*!< Channel 3 half transfer flag */
AnnaBridge 171:3a7713b1edbc 271 #define DMA_FLAG_TE3 (0x00000800U) /*!< Channel 3 transfer error flag */
AnnaBridge 171:3a7713b1edbc 272 #define DMA_FLAG_GL4 (0x00001000U) /*!< Channel 4 global interrupt flag */
AnnaBridge 171:3a7713b1edbc 273 #define DMA_FLAG_TC4 (0x00002000U) /*!< Channel 4 transfer complete flag */
AnnaBridge 171:3a7713b1edbc 274 #define DMA_FLAG_HT4 (0x00004000U) /*!< Channel 4 half transfer flag */
AnnaBridge 171:3a7713b1edbc 275 #define DMA_FLAG_TE4 (0x00008000U) /*!< Channel 4 transfer error flag */
AnnaBridge 171:3a7713b1edbc 276 #define DMA_FLAG_GL5 (0x00010000U) /*!< Channel 5 global interrupt flag */
AnnaBridge 171:3a7713b1edbc 277 #define DMA_FLAG_TC5 (0x00020000U) /*!< Channel 5 transfer complete flag */
AnnaBridge 171:3a7713b1edbc 278 #define DMA_FLAG_HT5 (0x00040000U) /*!< Channel 5 half transfer flag */
AnnaBridge 171:3a7713b1edbc 279 #define DMA_FLAG_TE5 (0x00080000U) /*!< Channel 5 transfer error flag */
AnnaBridge 171:3a7713b1edbc 280 #define DMA_FLAG_GL6 (0x00100000U) /*!< Channel 6 global interrupt flag */
AnnaBridge 171:3a7713b1edbc 281 #define DMA_FLAG_TC6 (0x00200000U) /*!< Channel 6 transfer complete flag */
AnnaBridge 171:3a7713b1edbc 282 #define DMA_FLAG_HT6 (0x00400000U) /*!< Channel 6 half transfer flag */
AnnaBridge 171:3a7713b1edbc 283 #define DMA_FLAG_TE6 (0x00800000U) /*!< Channel 6 transfer error flag */
AnnaBridge 171:3a7713b1edbc 284 #define DMA_FLAG_GL7 (0x01000000U) /*!< Channel 7 global interrupt flag */
AnnaBridge 171:3a7713b1edbc 285 #define DMA_FLAG_TC7 (0x02000000U) /*!< Channel 7 transfer complete flag */
AnnaBridge 171:3a7713b1edbc 286 #define DMA_FLAG_HT7 (0x04000000U) /*!< Channel 7 half transfer flag */
AnnaBridge 171:3a7713b1edbc 287 #define DMA_FLAG_TE7 (0x08000000U) /*!< Channel 7 transfer error flag */
AnnaBridge 171:3a7713b1edbc 288
AnnaBridge 171:3a7713b1edbc 289 /**
AnnaBridge 171:3a7713b1edbc 290 * @}
AnnaBridge 171:3a7713b1edbc 291 */
AnnaBridge 171:3a7713b1edbc 292
AnnaBridge 171:3a7713b1edbc 293 #if defined(SYSCFG_CFGR1_DMA_RMP)
AnnaBridge 171:3a7713b1edbc 294 /** @defgroup HAL_DMA_remapping HAL DMA remapping
AnnaBridge 171:3a7713b1edbc 295 * Elements values convention: 0xYYYYYYYY
AnnaBridge 171:3a7713b1edbc 296 * - YYYYYYYY : Position in the SYSCFG register CFGR1
AnnaBridge 171:3a7713b1edbc 297 * @{
AnnaBridge 171:3a7713b1edbc 298 */
AnnaBridge 171:3a7713b1edbc 299 #define DMA_REMAP_ADC_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_ADC_DMA_RMP) /*!< ADC DMA remap
AnnaBridge 171:3a7713b1edbc 300 0: No remap (ADC DMA requests mapped on DMA channel 1
AnnaBridge 171:3a7713b1edbc 301 1: Remap (ADC DMA requests mapped on DMA channel 2 */
AnnaBridge 171:3a7713b1edbc 302 #define DMA_REMAP_USART1_TX_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1 TX DMA remap
AnnaBridge 171:3a7713b1edbc 303 0: No remap (USART1_TX DMA request mapped on DMA channel 2
AnnaBridge 171:3a7713b1edbc 304 1: Remap (USART1_TX DMA request mapped on DMA channel 4 */
AnnaBridge 171:3a7713b1edbc 305 #define DMA_REMAP_USART1_RX_DMA_CH5 ((uint32_t)SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1 RX DMA remap
AnnaBridge 171:3a7713b1edbc 306 0: No remap (USART1_RX DMA request mapped on DMA channel 3
AnnaBridge 171:3a7713b1edbc 307 1: Remap (USART1_RX DMA request mapped on DMA channel 5 */
AnnaBridge 171:3a7713b1edbc 308 #define DMA_REMAP_TIM16_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16 DMA request remap
AnnaBridge 171:3a7713b1edbc 309 0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3)
AnnaBridge 171:3a7713b1edbc 310 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4) */
AnnaBridge 171:3a7713b1edbc 311 #define DMA_REMAP_TIM17_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17 DMA request remap
AnnaBridge 171:3a7713b1edbc 312 0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1
AnnaBridge 171:3a7713b1edbc 313 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2) */
AnnaBridge 171:3a7713b1edbc 314 #if defined (STM32F070xB)
AnnaBridge 171:3a7713b1edbc 315 #define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F070xB devices only.
AnnaBridge 171:3a7713b1edbc 316 0: Disabled, need to remap before use
AnnaBridge 171:3a7713b1edbc 317 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */
AnnaBridge 171:3a7713b1edbc 318
AnnaBridge 171:3a7713b1edbc 319 #endif
AnnaBridge 171:3a7713b1edbc 320
AnnaBridge 171:3a7713b1edbc 321 #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx)
AnnaBridge 171:3a7713b1edbc 322 #define DMA_REMAP_TIM16_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16 alternate DMA request remapping bit. Available on STM32F07x devices only
AnnaBridge 171:3a7713b1edbc 323 0: No alternate remap (TIM16 DMA requestsmapped according to TIM16_DMA_RMP bit)
AnnaBridge 171:3a7713b1edbc 324 1: Alternate remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6) */
AnnaBridge 171:3a7713b1edbc 325 #define DMA_REMAP_TIM17_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17 alternate DMA request remapping bit. Available on STM32F07x devices only
AnnaBridge 171:3a7713b1edbc 326 0: No alternate remap (TIM17 DMA requestsmapped according to TIM17_DMA_RMP bit)
AnnaBridge 171:3a7713b1edbc 327 1: Alternate remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7) */
AnnaBridge 171:3a7713b1edbc 328 #define DMA_REMAP_SPI2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_SPI2_DMA_RMP) /*!< SPI2 DMA request remapping bit. Available on STM32F07x devices only.
AnnaBridge 171:3a7713b1edbc 329 0: No remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively)
AnnaBridge 171:3a7713b1edbc 330 1: Remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */
AnnaBridge 171:3a7713b1edbc 331 #define DMA_REMAP_USART2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2 DMA request remapping bit. Available on STM32F07x devices only.
AnnaBridge 171:3a7713b1edbc 332 0: No remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively)
AnnaBridge 171:3a7713b1edbc 333 1: 1: Remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */
AnnaBridge 171:3a7713b1edbc 334 #define DMA_REMAP_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F07x devices only.
AnnaBridge 171:3a7713b1edbc 335 0: No remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively)
AnnaBridge 171:3a7713b1edbc 336 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */
AnnaBridge 171:3a7713b1edbc 337 #define DMA_REMAP_I2C1_DMA_CH76 ((uint32_t)SYSCFG_CFGR1_I2C1_DMA_RMP) /*!< I2C1 DMA request remapping bit. Available on STM32F07x devices only.
AnnaBridge 171:3a7713b1edbc 338 0: No remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively)
AnnaBridge 171:3a7713b1edbc 339 1: Remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively) */
AnnaBridge 171:3a7713b1edbc 340 #define DMA_REMAP_TIM1_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1 DMA request remapping bit. Available on STM32F07x devices only.
AnnaBridge 171:3a7713b1edbc 341 0: No remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively)
AnnaBridge 171:3a7713b1edbc 342 1: Remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */
AnnaBridge 171:3a7713b1edbc 343 #define DMA_REMAP_TIM2_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2 DMA request remapping bit. Available on STM32F07x devices only.
AnnaBridge 171:3a7713b1edbc 344 0: No remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively)
AnnaBridge 171:3a7713b1edbc 345 1: Remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */
AnnaBridge 171:3a7713b1edbc 346 #define DMA_REMAP_TIM3_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3 DMA request remapping bit. Available on STM32F07x devices only.
AnnaBridge 171:3a7713b1edbc 347 0: No remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4)
AnnaBridge 171:3a7713b1edbc 348 1: Remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6) */
AnnaBridge 171:3a7713b1edbc 349 #endif
AnnaBridge 171:3a7713b1edbc 350
AnnaBridge 171:3a7713b1edbc 351 /**
AnnaBridge 171:3a7713b1edbc 352 * @}
AnnaBridge 171:3a7713b1edbc 353 */
AnnaBridge 171:3a7713b1edbc 354
AnnaBridge 171:3a7713b1edbc 355 #endif /* SYSCFG_CFGR1_DMA_RMP */
AnnaBridge 171:3a7713b1edbc 356 /**
AnnaBridge 171:3a7713b1edbc 357 * @}
AnnaBridge 171:3a7713b1edbc 358 */
AnnaBridge 171:3a7713b1edbc 359
AnnaBridge 171:3a7713b1edbc 360 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 361 /** @defgroup DMA_Exported_Macros DMA Exported Macros
AnnaBridge 171:3a7713b1edbc 362 * @{
AnnaBridge 171:3a7713b1edbc 363 */
AnnaBridge 171:3a7713b1edbc 364
AnnaBridge 171:3a7713b1edbc 365 /** @brief Reset DMA handle state
AnnaBridge 171:3a7713b1edbc 366 * @param __HANDLE__ DMA handle.
AnnaBridge 171:3a7713b1edbc 367 * @retval None
AnnaBridge 171:3a7713b1edbc 368 */
AnnaBridge 171:3a7713b1edbc 369 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
AnnaBridge 171:3a7713b1edbc 370
AnnaBridge 171:3a7713b1edbc 371 /**
AnnaBridge 171:3a7713b1edbc 372 * @brief Enable the specified DMA Channel.
AnnaBridge 171:3a7713b1edbc 373 * @param __HANDLE__ DMA handle
AnnaBridge 171:3a7713b1edbc 374 * @retval None
AnnaBridge 171:3a7713b1edbc 375 */
AnnaBridge 171:3a7713b1edbc 376 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
AnnaBridge 171:3a7713b1edbc 377
AnnaBridge 171:3a7713b1edbc 378 /**
AnnaBridge 171:3a7713b1edbc 379 * @brief Disable the specified DMA Channel.
AnnaBridge 171:3a7713b1edbc 380 * @param __HANDLE__ DMA handle
AnnaBridge 171:3a7713b1edbc 381 * @retval None
AnnaBridge 171:3a7713b1edbc 382 */
AnnaBridge 171:3a7713b1edbc 383 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
AnnaBridge 171:3a7713b1edbc 384
AnnaBridge 171:3a7713b1edbc 385
AnnaBridge 171:3a7713b1edbc 386 /* Interrupt & Flag management */
AnnaBridge 171:3a7713b1edbc 387
AnnaBridge 171:3a7713b1edbc 388 /**
AnnaBridge 171:3a7713b1edbc 389 * @brief Enables the specified DMA Channel interrupts.
AnnaBridge 171:3a7713b1edbc 390 * @param __HANDLE__ DMA handle
AnnaBridge 171:3a7713b1edbc 391 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
AnnaBridge 171:3a7713b1edbc 392 * This parameter can be any combination of the following values:
AnnaBridge 171:3a7713b1edbc 393 * @arg DMA_IT_TC: Transfer complete interrupt mask
AnnaBridge 171:3a7713b1edbc 394 * @arg DMA_IT_HT: Half transfer complete interrupt mask
AnnaBridge 171:3a7713b1edbc 395 * @arg DMA_IT_TE: Transfer error interrupt mask
AnnaBridge 171:3a7713b1edbc 396 * @retval None
AnnaBridge 171:3a7713b1edbc 397 */
AnnaBridge 171:3a7713b1edbc 398 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
AnnaBridge 171:3a7713b1edbc 399
AnnaBridge 171:3a7713b1edbc 400 /**
AnnaBridge 171:3a7713b1edbc 401 * @brief Disables the specified DMA Channel interrupts.
AnnaBridge 171:3a7713b1edbc 402 * @param __HANDLE__ DMA handle
AnnaBridge 171:3a7713b1edbc 403 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
AnnaBridge 171:3a7713b1edbc 404 * This parameter can be any combination of the following values:
AnnaBridge 171:3a7713b1edbc 405 * @arg DMA_IT_TC: Transfer complete interrupt mask
AnnaBridge 171:3a7713b1edbc 406 * @arg DMA_IT_HT: Half transfer complete interrupt mask
AnnaBridge 171:3a7713b1edbc 407 * @arg DMA_IT_TE: Transfer error interrupt mask
AnnaBridge 171:3a7713b1edbc 408 * @retval None
AnnaBridge 171:3a7713b1edbc 409 */
AnnaBridge 171:3a7713b1edbc 410 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
AnnaBridge 171:3a7713b1edbc 411
AnnaBridge 171:3a7713b1edbc 412 /**
AnnaBridge 171:3a7713b1edbc 413 * @brief Checks whether the specified DMA Channel interrupt is enabled or disabled.
AnnaBridge 171:3a7713b1edbc 414 * @param __HANDLE__ DMA handle
AnnaBridge 171:3a7713b1edbc 415 * @param __INTERRUPT__ specifies the DMA interrupt source to check.
AnnaBridge 171:3a7713b1edbc 416 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 417 * @arg DMA_IT_TC: Transfer complete interrupt mask
AnnaBridge 171:3a7713b1edbc 418 * @arg DMA_IT_HT: Half transfer complete interrupt mask
AnnaBridge 171:3a7713b1edbc 419 * @arg DMA_IT_TE: Transfer error interrupt mask
AnnaBridge 171:3a7713b1edbc 420 * @retval The state of DMA_IT (SET or RESET).
AnnaBridge 171:3a7713b1edbc 421 */
AnnaBridge 171:3a7713b1edbc 422 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
AnnaBridge 171:3a7713b1edbc 423
AnnaBridge 171:3a7713b1edbc 424 /**
AnnaBridge 171:3a7713b1edbc 425 * @brief Returns the number of remaining data units in the current DMAy Channelx transfer.
AnnaBridge 171:3a7713b1edbc 426 * @param __HANDLE__ DMA handle
AnnaBridge 171:3a7713b1edbc 427 *
AnnaBridge 171:3a7713b1edbc 428 * @retval The number of remaining data units in the current DMA Channel transfer.
AnnaBridge 171:3a7713b1edbc 429 */
AnnaBridge 171:3a7713b1edbc 430 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
AnnaBridge 171:3a7713b1edbc 431
AnnaBridge 171:3a7713b1edbc 432 #if defined(SYSCFG_CFGR1_DMA_RMP)
AnnaBridge 171:3a7713b1edbc 433 /** @brief DMA remapping enable/disable macros
AnnaBridge 171:3a7713b1edbc 434 * @param __DMA_REMAP__ This parameter can be a value of @ref HAL_DMA_remapping
AnnaBridge 171:3a7713b1edbc 435 */
AnnaBridge 171:3a7713b1edbc 436 #define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
AnnaBridge 171:3a7713b1edbc 437 SYSCFG->CFGR1 |= (__DMA_REMAP__); \
AnnaBridge 171:3a7713b1edbc 438 }while(0)
AnnaBridge 171:3a7713b1edbc 439 #define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
AnnaBridge 171:3a7713b1edbc 440 SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \
AnnaBridge 171:3a7713b1edbc 441 }while(0)
AnnaBridge 171:3a7713b1edbc 442 #endif /* SYSCFG_CFGR1_DMA_RMP */
AnnaBridge 171:3a7713b1edbc 443
AnnaBridge 171:3a7713b1edbc 444 /**
AnnaBridge 171:3a7713b1edbc 445 * @}
AnnaBridge 171:3a7713b1edbc 446 */
AnnaBridge 171:3a7713b1edbc 447
AnnaBridge 171:3a7713b1edbc 448 /* Include DMA HAL Extension module */
AnnaBridge 171:3a7713b1edbc 449 #include "stm32f0xx_hal_dma_ex.h"
AnnaBridge 171:3a7713b1edbc 450
AnnaBridge 171:3a7713b1edbc 451 /* Exported functions --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 452 /** @addtogroup DMA_Exported_Functions
AnnaBridge 171:3a7713b1edbc 453 * @{
AnnaBridge 171:3a7713b1edbc 454 */
AnnaBridge 171:3a7713b1edbc 455
AnnaBridge 171:3a7713b1edbc 456 /** @addtogroup DMA_Exported_Functions_Group1
AnnaBridge 171:3a7713b1edbc 457 * @{
AnnaBridge 171:3a7713b1edbc 458 */
AnnaBridge 171:3a7713b1edbc 459 /* Initialization and de-initialization functions *****************************/
AnnaBridge 171:3a7713b1edbc 460 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
AnnaBridge 171:3a7713b1edbc 461 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
AnnaBridge 171:3a7713b1edbc 462 /**
AnnaBridge 171:3a7713b1edbc 463 * @}
AnnaBridge 171:3a7713b1edbc 464 */
AnnaBridge 171:3a7713b1edbc 465
AnnaBridge 171:3a7713b1edbc 466 /** @addtogroup DMA_Exported_Functions_Group2
AnnaBridge 171:3a7713b1edbc 467 * @{
AnnaBridge 171:3a7713b1edbc 468 */
AnnaBridge 171:3a7713b1edbc 469 /* Input and Output operation functions *****************************************************/
AnnaBridge 171:3a7713b1edbc 470 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
AnnaBridge 171:3a7713b1edbc 471 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
AnnaBridge 171:3a7713b1edbc 472 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
AnnaBridge 171:3a7713b1edbc 473 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
AnnaBridge 171:3a7713b1edbc 474 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
AnnaBridge 171:3a7713b1edbc 475 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
AnnaBridge 171:3a7713b1edbc 476 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
AnnaBridge 171:3a7713b1edbc 477 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
AnnaBridge 171:3a7713b1edbc 478
AnnaBridge 171:3a7713b1edbc 479 /**
AnnaBridge 171:3a7713b1edbc 480 * @}
AnnaBridge 171:3a7713b1edbc 481 */
AnnaBridge 171:3a7713b1edbc 482
AnnaBridge 171:3a7713b1edbc 483 /** @addtogroup DMA_Exported_Functions_Group3
AnnaBridge 171:3a7713b1edbc 484 * @{
AnnaBridge 171:3a7713b1edbc 485 */
AnnaBridge 171:3a7713b1edbc 486 /* Peripheral State and Error functions ***************************************/
AnnaBridge 171:3a7713b1edbc 487 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
AnnaBridge 171:3a7713b1edbc 488 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
AnnaBridge 171:3a7713b1edbc 489 /**
AnnaBridge 171:3a7713b1edbc 490 * @}
AnnaBridge 171:3a7713b1edbc 491 */
AnnaBridge 171:3a7713b1edbc 492
AnnaBridge 171:3a7713b1edbc 493 /**
AnnaBridge 171:3a7713b1edbc 494 * @}
AnnaBridge 171:3a7713b1edbc 495 */
AnnaBridge 171:3a7713b1edbc 496
AnnaBridge 171:3a7713b1edbc 497 /** @addtogroup DMA_Private_Macros
AnnaBridge 171:3a7713b1edbc 498 * @{
AnnaBridge 171:3a7713b1edbc 499 */
AnnaBridge 171:3a7713b1edbc 500 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
AnnaBridge 171:3a7713b1edbc 501 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
AnnaBridge 171:3a7713b1edbc 502 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
AnnaBridge 171:3a7713b1edbc 503 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
AnnaBridge 171:3a7713b1edbc 504 ((STATE) == DMA_PINC_DISABLE))
AnnaBridge 171:3a7713b1edbc 505
AnnaBridge 171:3a7713b1edbc 506 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
AnnaBridge 171:3a7713b1edbc 507 ((STATE) == DMA_MINC_DISABLE))
AnnaBridge 171:3a7713b1edbc 508
AnnaBridge 171:3a7713b1edbc 509 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
AnnaBridge 171:3a7713b1edbc 510 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
AnnaBridge 171:3a7713b1edbc 511 ((SIZE) == DMA_PDATAALIGN_WORD))
AnnaBridge 171:3a7713b1edbc 512
AnnaBridge 171:3a7713b1edbc 513 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
AnnaBridge 171:3a7713b1edbc 514 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
AnnaBridge 171:3a7713b1edbc 515 ((SIZE) == DMA_MDATAALIGN_WORD ))
AnnaBridge 171:3a7713b1edbc 516
AnnaBridge 171:3a7713b1edbc 517 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
AnnaBridge 171:3a7713b1edbc 518 ((MODE) == DMA_CIRCULAR))
AnnaBridge 171:3a7713b1edbc 519 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
AnnaBridge 171:3a7713b1edbc 520 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
AnnaBridge 171:3a7713b1edbc 521 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
AnnaBridge 171:3a7713b1edbc 522 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
AnnaBridge 171:3a7713b1edbc 523 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
AnnaBridge 171:3a7713b1edbc 524
AnnaBridge 171:3a7713b1edbc 525 #if defined(SYSCFG_CFGR1_DMA_RMP)
AnnaBridge 171:3a7713b1edbc 526
AnnaBridge 171:3a7713b1edbc 527 #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx)
AnnaBridge 171:3a7713b1edbc 528 #define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \
AnnaBridge 171:3a7713b1edbc 529 ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \
AnnaBridge 171:3a7713b1edbc 530 ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \
AnnaBridge 171:3a7713b1edbc 531 ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \
AnnaBridge 171:3a7713b1edbc 532 ((RMP) == DMA_REMAP_TIM17_DMA_CH2) || \
AnnaBridge 171:3a7713b1edbc 533 ((RMP) == DMA_REMAP_TIM16_DMA_CH6) || \
AnnaBridge 171:3a7713b1edbc 534 ((RMP) == DMA_REMAP_TIM17_DMA_CH7) || \
AnnaBridge 171:3a7713b1edbc 535 ((RMP) == DMA_REMAP_SPI2_DMA_CH67) || \
AnnaBridge 171:3a7713b1edbc 536 ((RMP) == DMA_REMAP_USART2_DMA_CH67) || \
AnnaBridge 171:3a7713b1edbc 537 ((RMP) == DMA_REMAP_USART3_DMA_CH32) || \
AnnaBridge 171:3a7713b1edbc 538 ((RMP) == DMA_REMAP_I2C1_DMA_CH76) || \
AnnaBridge 171:3a7713b1edbc 539 ((RMP) == DMA_REMAP_TIM1_DMA_CH6) || \
AnnaBridge 171:3a7713b1edbc 540 ((RMP) == DMA_REMAP_TIM2_DMA_CH7) || \
AnnaBridge 171:3a7713b1edbc 541 ((RMP) == DMA_REMAP_TIM3_DMA_CH6))
AnnaBridge 171:3a7713b1edbc 542 #elif defined (STM32F070xB)
AnnaBridge 171:3a7713b1edbc 543 #define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_USART3_DMA_CH32) || \
AnnaBridge 171:3a7713b1edbc 544 ((RMP) == DMA_REMAP_ADC_DMA_CH2) || \
AnnaBridge 171:3a7713b1edbc 545 ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \
AnnaBridge 171:3a7713b1edbc 546 ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \
AnnaBridge 171:3a7713b1edbc 547 ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \
AnnaBridge 171:3a7713b1edbc 548 ((RMP) == DMA_REMAP_TIM17_DMA_CH2))
AnnaBridge 171:3a7713b1edbc 549 #else
AnnaBridge 171:3a7713b1edbc 550 #define IS_DMA_REMAP(RMP) (((RMP) == DMA_REMAP_ADC_DMA_CH2) || \
AnnaBridge 171:3a7713b1edbc 551 ((RMP) == DMA_REMAP_USART1_TX_DMA_CH4) || \
AnnaBridge 171:3a7713b1edbc 552 ((RMP) == DMA_REMAP_USART1_RX_DMA_CH5) || \
AnnaBridge 171:3a7713b1edbc 553 ((RMP) == DMA_REMAP_TIM16_DMA_CH4) || \
AnnaBridge 171:3a7713b1edbc 554 ((RMP) == DMA_REMAP_TIM17_DMA_CH2))
AnnaBridge 171:3a7713b1edbc 555 #endif
AnnaBridge 171:3a7713b1edbc 556
AnnaBridge 171:3a7713b1edbc 557 #endif /* SYSCFG_CFGR1_DMA_RMP */
AnnaBridge 171:3a7713b1edbc 558
AnnaBridge 171:3a7713b1edbc 559
AnnaBridge 171:3a7713b1edbc 560 /**
AnnaBridge 171:3a7713b1edbc 561 * @}
AnnaBridge 171:3a7713b1edbc 562 */
AnnaBridge 171:3a7713b1edbc 563
AnnaBridge 171:3a7713b1edbc 564 /**
AnnaBridge 171:3a7713b1edbc 565 * @}
AnnaBridge 171:3a7713b1edbc 566 */
AnnaBridge 171:3a7713b1edbc 567
AnnaBridge 171:3a7713b1edbc 568 /**
AnnaBridge 171:3a7713b1edbc 569 * @}
AnnaBridge 171:3a7713b1edbc 570 */
AnnaBridge 171:3a7713b1edbc 571
AnnaBridge 171:3a7713b1edbc 572 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 573 }
AnnaBridge 171:3a7713b1edbc 574 #endif
AnnaBridge 171:3a7713b1edbc 575
AnnaBridge 171:3a7713b1edbc 576 #endif /* __STM32F0xx_HAL_DMA_H */
AnnaBridge 171:3a7713b1edbc 577
AnnaBridge 171:3a7713b1edbc 578 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
AnnaBridge 171:3a7713b1edbc 579