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TARGET_NUCLEO_F030R8/TOOLCHAIN_IAR/stm32f0xx_hal.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file stm32f0xx_hal.h
AnnaBridge 171:3a7713b1edbc 4 * @author MCD Application Team
AnnaBridge 171:3a7713b1edbc 5 * @brief This file contains all the functions prototypes for the HAL
AnnaBridge 171:3a7713b1edbc 6 * module driver.
AnnaBridge 171:3a7713b1edbc 7 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 8 * @attention
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 171:3a7713b1edbc 11 *
AnnaBridge 171:3a7713b1edbc 12 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 13 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 14 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 15 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 16 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 17 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 18 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 19 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 171:3a7713b1edbc 20 * may be used to endorse or promote products derived from this software
AnnaBridge 171:3a7713b1edbc 21 * without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 22 *
AnnaBridge 171:3a7713b1edbc 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 171:3a7713b1edbc 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 171:3a7713b1edbc 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 171:3a7713b1edbc 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 171:3a7713b1edbc 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 171:3a7713b1edbc 30 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 171:3a7713b1edbc 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 171:3a7713b1edbc 32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 33 *
AnnaBridge 171:3a7713b1edbc 34 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 35 */
AnnaBridge 171:3a7713b1edbc 36
AnnaBridge 171:3a7713b1edbc 37 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 171:3a7713b1edbc 38 #ifndef __STM32F0xx_HAL_H
AnnaBridge 171:3a7713b1edbc 39 #define __STM32F0xx_HAL_H
AnnaBridge 171:3a7713b1edbc 40
AnnaBridge 171:3a7713b1edbc 41 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 42 extern "C" {
AnnaBridge 171:3a7713b1edbc 43 #endif
AnnaBridge 171:3a7713b1edbc 44
AnnaBridge 171:3a7713b1edbc 45 /* Includes ------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 46 #include "stm32f0xx_hal_conf.h"
AnnaBridge 171:3a7713b1edbc 47
AnnaBridge 171:3a7713b1edbc 48 /** @addtogroup STM32F0xx_HAL_Driver
AnnaBridge 171:3a7713b1edbc 49 * @{
AnnaBridge 171:3a7713b1edbc 50 */
AnnaBridge 171:3a7713b1edbc 51
AnnaBridge 171:3a7713b1edbc 52 /** @addtogroup HAL
AnnaBridge 171:3a7713b1edbc 53 * @{
AnnaBridge 171:3a7713b1edbc 54 */
AnnaBridge 171:3a7713b1edbc 55
AnnaBridge 171:3a7713b1edbc 56 /* Private macros ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 57 /** @addtogroup HAL_Private_Macros
AnnaBridge 171:3a7713b1edbc 58 * @{
AnnaBridge 171:3a7713b1edbc 59 */
AnnaBridge 171:3a7713b1edbc 60 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \
AnnaBridge 171:3a7713b1edbc 61 defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
AnnaBridge 171:3a7713b1edbc 62 defined(STM32F070xB) || defined(STM32F030x6)
AnnaBridge 171:3a7713b1edbc 63 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PA9) == SYSCFG_FASTMODEPLUS_PA9) || \
AnnaBridge 171:3a7713b1edbc 64 (((__PIN__) & SYSCFG_FASTMODEPLUS_PA10) == SYSCFG_FASTMODEPLUS_PA10) || \
AnnaBridge 171:3a7713b1edbc 65 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
AnnaBridge 171:3a7713b1edbc 66 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
AnnaBridge 171:3a7713b1edbc 67 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
AnnaBridge 171:3a7713b1edbc 68 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
AnnaBridge 171:3a7713b1edbc 69 #else
AnnaBridge 171:3a7713b1edbc 70 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
AnnaBridge 171:3a7713b1edbc 71 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
AnnaBridge 171:3a7713b1edbc 72 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
AnnaBridge 171:3a7713b1edbc 73 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
AnnaBridge 171:3a7713b1edbc 74 #endif
AnnaBridge 171:3a7713b1edbc 75 #if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
AnnaBridge 171:3a7713b1edbc 76 #define IS_HAL_REMAP_PIN(RMP) ((RMP) == HAL_REMAP_PA11_PA12)
AnnaBridge 171:3a7713b1edbc 77 #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
AnnaBridge 171:3a7713b1edbc 78 #if defined(STM32F091xC) || defined(STM32F098xx)
AnnaBridge 171:3a7713b1edbc 79 #define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \
AnnaBridge 171:3a7713b1edbc 80 ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \
AnnaBridge 171:3a7713b1edbc 81 ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4))
AnnaBridge 171:3a7713b1edbc 82 #endif /* STM32F091xC || STM32F098xx */
AnnaBridge 171:3a7713b1edbc 83 /**
AnnaBridge 171:3a7713b1edbc 84 * @}
AnnaBridge 171:3a7713b1edbc 85 */
AnnaBridge 171:3a7713b1edbc 86
AnnaBridge 171:3a7713b1edbc 87 /* Exported types ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 88 /* Exported constants --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 89 /** @defgroup HAL_Exported_Constants HAL Exported Constants
AnnaBridge 171:3a7713b1edbc 90 * @{
AnnaBridge 171:3a7713b1edbc 91 */
AnnaBridge 171:3a7713b1edbc 92
AnnaBridge 171:3a7713b1edbc 93 #if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
AnnaBridge 171:3a7713b1edbc 94 /** @defgroup HAL_Pin_remapping HAL Pin remapping
AnnaBridge 171:3a7713b1edbc 95 * @{
AnnaBridge 171:3a7713b1edbc 96 */
AnnaBridge 171:3a7713b1edbc 97 #define HAL_REMAP_PA11_PA12 (SYSCFG_CFGR1_PA11_PA12_RMP) /*!< PA11 and PA12 remapping bit for small packages (28 and 20 pins).
AnnaBridge 171:3a7713b1edbc 98 0: No remap (pin pair PA9/10 mapped on the pins)
AnnaBridge 171:3a7713b1edbc 99 1: Remap (pin pair PA11/12 mapped instead of PA9/10) */
AnnaBridge 171:3a7713b1edbc 100
AnnaBridge 171:3a7713b1edbc 101 /**
AnnaBridge 171:3a7713b1edbc 102 * @}
AnnaBridge 171:3a7713b1edbc 103 */
AnnaBridge 171:3a7713b1edbc 104 #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
AnnaBridge 171:3a7713b1edbc 105
AnnaBridge 171:3a7713b1edbc 106 #if defined(STM32F091xC) || defined(STM32F098xx)
AnnaBridge 171:3a7713b1edbc 107 /** @defgroup HAL_IRDA_ENV_SEL HAL IRDA Enveloppe Selection
AnnaBridge 171:3a7713b1edbc 108 * @note Applicable on STM32F09x
AnnaBridge 171:3a7713b1edbc 109 * @{
AnnaBridge 171:3a7713b1edbc 110 */
AnnaBridge 171:3a7713b1edbc 111 #define HAL_SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IRDA_ENV_SEL_0 & SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 00: Timer16 is selected as IRDA Modulation enveloppe source */
AnnaBridge 171:3a7713b1edbc 112 #define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IRDA_ENV_SEL_0) /* 01: USART1 is selected as IRDA Modulation enveloppe source */
AnnaBridge 171:3a7713b1edbc 113 #define HAL_SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 10: USART4 is selected as IRDA Modulation enveloppe source */
AnnaBridge 171:3a7713b1edbc 114
AnnaBridge 171:3a7713b1edbc 115 /**
AnnaBridge 171:3a7713b1edbc 116 * @}
AnnaBridge 171:3a7713b1edbc 117 */
AnnaBridge 171:3a7713b1edbc 118 #endif /* STM32F091xC || STM32F098xx */
AnnaBridge 171:3a7713b1edbc 119
AnnaBridge 171:3a7713b1edbc 120
AnnaBridge 171:3a7713b1edbc 121 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
AnnaBridge 171:3a7713b1edbc 122 * @{
AnnaBridge 171:3a7713b1edbc 123 */
AnnaBridge 171:3a7713b1edbc 124
AnnaBridge 171:3a7713b1edbc 125 /** @brief Fast-mode Plus driving capability on a specific GPIO
AnnaBridge 171:3a7713b1edbc 126 */
AnnaBridge 171:3a7713b1edbc 127 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \
AnnaBridge 171:3a7713b1edbc 128 defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
AnnaBridge 171:3a7713b1edbc 129 defined(STM32F070xB) || defined(STM32F030x6)
AnnaBridge 171:3a7713b1edbc 130 #define SYSCFG_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast-mode Plus on PA9 */
AnnaBridge 171:3a7713b1edbc 131 #define SYSCFG_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast-mode Plus on PA10 */
AnnaBridge 171:3a7713b1edbc 132 #endif
AnnaBridge 171:3a7713b1edbc 133 #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< Enable Fast-mode Plus on PB6 */
AnnaBridge 171:3a7713b1edbc 134 #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< Enable Fast-mode Plus on PB7 */
AnnaBridge 171:3a7713b1edbc 135 #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< Enable Fast-mode Plus on PB8 */
AnnaBridge 171:3a7713b1edbc 136 #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< Enable Fast-mode Plus on PB9 */
AnnaBridge 171:3a7713b1edbc 137
AnnaBridge 171:3a7713b1edbc 138 /**
AnnaBridge 171:3a7713b1edbc 139 * @}
AnnaBridge 171:3a7713b1edbc 140 */
AnnaBridge 171:3a7713b1edbc 141
AnnaBridge 171:3a7713b1edbc 142
AnnaBridge 171:3a7713b1edbc 143 #if defined(STM32F091xC) || defined (STM32F098xx)
AnnaBridge 171:3a7713b1edbc 144 /** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper
AnnaBridge 171:3a7713b1edbc 145 * @brief ISR Wrapper
AnnaBridge 171:3a7713b1edbc 146 * @note applicable on STM32F09x
AnnaBridge 171:3a7713b1edbc 147 * @{
AnnaBridge 171:3a7713b1edbc 148 */
AnnaBridge 171:3a7713b1edbc 149 #define HAL_SYSCFG_ITLINE0 ( 0x00000000U) /*!< Internal define for macro handling */
AnnaBridge 171:3a7713b1edbc 150 #define HAL_SYSCFG_ITLINE1 ( 0x00000001U) /*!< Internal define for macro handling */
AnnaBridge 171:3a7713b1edbc 151 #define HAL_SYSCFG_ITLINE2 ( 0x00000002U) /*!< Internal define for macro handling */
AnnaBridge 171:3a7713b1edbc 152 #define HAL_SYSCFG_ITLINE3 ( 0x00000003U) /*!< Internal define for macro handling */
AnnaBridge 171:3a7713b1edbc 153 #define HAL_SYSCFG_ITLINE4 ( 0x00000004U) /*!< Internal define for macro handling */
AnnaBridge 171:3a7713b1edbc 154 #define HAL_SYSCFG_ITLINE5 ( 0x00000005U) /*!< Internal define for macro handling */
AnnaBridge 171:3a7713b1edbc 155 #define HAL_SYSCFG_ITLINE6 ( 0x00000006U) /*!< Internal define for macro handling */
AnnaBridge 171:3a7713b1edbc 156 #define HAL_SYSCFG_ITLINE7 ( 0x00000007U) /*!< Internal define for macro handling */
AnnaBridge 171:3a7713b1edbc 157 #define HAL_SYSCFG_ITLINE8 ( 0x00000008U) /*!< Internal define for macro handling */
AnnaBridge 171:3a7713b1edbc 158 #define HAL_SYSCFG_ITLINE9 ( 0x00000009U) /*!< Internal define for macro handling */
AnnaBridge 171:3a7713b1edbc 159 #define HAL_SYSCFG_ITLINE10 ( 0x0000000AU) /*!< Internal define for macro handling */
AnnaBridge 171:3a7713b1edbc 160 #define HAL_SYSCFG_ITLINE11 ( 0x0000000BU) /*!< Internal define for macro handling */
AnnaBridge 171:3a7713b1edbc 161 #define HAL_SYSCFG_ITLINE12 ( 0x0000000CU) /*!< Internal define for macro handling */
AnnaBridge 171:3a7713b1edbc 162 #define HAL_SYSCFG_ITLINE13 ( 0x0000000DU) /*!< Internal define for macro handling */
AnnaBridge 171:3a7713b1edbc 163 #define HAL_SYSCFG_ITLINE14 ( 0x0000000EU) /*!< Internal define for macro handling */
AnnaBridge 171:3a7713b1edbc 164 #define HAL_SYSCFG_ITLINE15 ( 0x0000000FU) /*!< Internal define for macro handling */
AnnaBridge 171:3a7713b1edbc 165 #define HAL_SYSCFG_ITLINE16 ( 0x00000010U) /*!< Internal define for macro handling */
AnnaBridge 171:3a7713b1edbc 166 #define HAL_SYSCFG_ITLINE17 ( 0x00000011U) /*!< Internal define for macro handling */
AnnaBridge 171:3a7713b1edbc 167 #define HAL_SYSCFG_ITLINE18 ( 0x00000012U) /*!< Internal define for macro handling */
AnnaBridge 171:3a7713b1edbc 168 #define HAL_SYSCFG_ITLINE19 ( 0x00000013U) /*!< Internal define for macro handling */
AnnaBridge 171:3a7713b1edbc 169 #define HAL_SYSCFG_ITLINE20 ( 0x00000014U) /*!< Internal define for macro handling */
AnnaBridge 171:3a7713b1edbc 170 #define HAL_SYSCFG_ITLINE21 ( 0x00000015U) /*!< Internal define for macro handling */
AnnaBridge 171:3a7713b1edbc 171 #define HAL_SYSCFG_ITLINE22 ( 0x00000016U) /*!< Internal define for macro handling */
AnnaBridge 171:3a7713b1edbc 172 #define HAL_SYSCFG_ITLINE23 ( 0x00000017U) /*!< Internal define for macro handling */
AnnaBridge 171:3a7713b1edbc 173 #define HAL_SYSCFG_ITLINE24 ( 0x00000018U) /*!< Internal define for macro handling */
AnnaBridge 171:3a7713b1edbc 174 #define HAL_SYSCFG_ITLINE25 ( 0x00000019U) /*!< Internal define for macro handling */
AnnaBridge 171:3a7713b1edbc 175 #define HAL_SYSCFG_ITLINE26 ( 0x0000001AU) /*!< Internal define for macro handling */
AnnaBridge 171:3a7713b1edbc 176 #define HAL_SYSCFG_ITLINE27 ( 0x0000001BU) /*!< Internal define for macro handling */
AnnaBridge 171:3a7713b1edbc 177 #define HAL_SYSCFG_ITLINE28 ( 0x0000001CU) /*!< Internal define for macro handling */
AnnaBridge 171:3a7713b1edbc 178 #define HAL_SYSCFG_ITLINE29 ( 0x0000001DU) /*!< Internal define for macro handling */
AnnaBridge 171:3a7713b1edbc 179 #define HAL_SYSCFG_ITLINE30 ( 0x0000001EU) /*!< Internal define for macro handling */
AnnaBridge 171:3a7713b1edbc 180 #define HAL_SYSCFG_ITLINE31 ( 0x0000001FU) /*!< Internal define for macro handling */
AnnaBridge 171:3a7713b1edbc 181
AnnaBridge 171:3a7713b1edbc 182 #define HAL_ITLINE_EWDG ((uint32_t) ((HAL_SYSCFG_ITLINE0 << 0x18U) | SYSCFG_ITLINE0_SR_EWDG)) /*!< EWDG has expired .... */
AnnaBridge 171:3a7713b1edbc 183 #if defined(STM32F091xC)
AnnaBridge 171:3a7713b1edbc 184 #define HAL_ITLINE_PVDOUT ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_PVDOUT)) /*!< Power voltage detection Interrupt .... */
AnnaBridge 171:3a7713b1edbc 185 #endif
AnnaBridge 171:3a7713b1edbc 186 #define HAL_ITLINE_VDDIO2 ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18U) | SYSCFG_ITLINE1_SR_VDDIO2)) /*!< VDDIO2 Interrupt .... */
AnnaBridge 171:3a7713b1edbc 187 #define HAL_ITLINE_RTC_WAKEUP ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_WAKEUP)) /*!< RTC WAKEUP -> exti[20] Interrupt */
AnnaBridge 171:3a7713b1edbc 188 #define HAL_ITLINE_RTC_TSTAMP ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_TSTAMP)) /*!< RTC Time Stamp -> exti[19] interrupt */
AnnaBridge 171:3a7713b1edbc 189 #define HAL_ITLINE_RTC_ALRA ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18U) | SYSCFG_ITLINE2_SR_RTC_ALRA)) /*!< RTC Alarm -> exti[17] interrupt .... */
AnnaBridge 171:3a7713b1edbc 190 #define HAL_ITLINE_FLASH_ITF ((uint32_t) ((HAL_SYSCFG_ITLINE3 << 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ITF)) /*!< Flash ITF Interrupt */
AnnaBridge 171:3a7713b1edbc 191 #define HAL_ITLINE_CRS ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CRS)) /*!< CRS Interrupt */
AnnaBridge 171:3a7713b1edbc 192 #define HAL_ITLINE_CLK_CTRL ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18U) | SYSCFG_ITLINE4_SR_CLK_CTRL)) /*!< CLK Control Interrupt */
AnnaBridge 171:3a7713b1edbc 193 #define HAL_ITLINE_EXTI0 ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI0)) /*!< External Interrupt 0 */
AnnaBridge 171:3a7713b1edbc 194 #define HAL_ITLINE_EXTI1 ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18U) | SYSCFG_ITLINE5_SR_EXTI1)) /*!< External Interrupt 1 */
AnnaBridge 171:3a7713b1edbc 195 #define HAL_ITLINE_EXTI2 ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI2)) /*!< External Interrupt 2 */
AnnaBridge 171:3a7713b1edbc 196 #define HAL_ITLINE_EXTI3 ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18U) | SYSCFG_ITLINE6_SR_EXTI3)) /*!< External Interrupt 3 */
AnnaBridge 171:3a7713b1edbc 197 #define HAL_ITLINE_EXTI4 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI4)) /*!< EXTI4 Interrupt */
AnnaBridge 171:3a7713b1edbc 198 #define HAL_ITLINE_EXTI5 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI5)) /*!< EXTI5 Interrupt */
AnnaBridge 171:3a7713b1edbc 199 #define HAL_ITLINE_EXTI6 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI6)) /*!< EXTI6 Interrupt */
AnnaBridge 171:3a7713b1edbc 200 #define HAL_ITLINE_EXTI7 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI7)) /*!< EXTI7 Interrupt */
AnnaBridge 171:3a7713b1edbc 201 #define HAL_ITLINE_EXTI8 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI8)) /*!< EXTI8 Interrupt */
AnnaBridge 171:3a7713b1edbc 202 #define HAL_ITLINE_EXTI9 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI9)) /*!< EXTI9 Interrupt */
AnnaBridge 171:3a7713b1edbc 203 #define HAL_ITLINE_EXTI10 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI10)) /*!< EXTI10 Interrupt */
AnnaBridge 171:3a7713b1edbc 204 #define HAL_ITLINE_EXTI11 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI11)) /*!< EXTI11 Interrupt */
AnnaBridge 171:3a7713b1edbc 205 #define HAL_ITLINE_EXTI12 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI12)) /*!< EXTI12 Interrupt */
AnnaBridge 171:3a7713b1edbc 206 #define HAL_ITLINE_EXTI13 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI13)) /*!< EXTI13 Interrupt */
AnnaBridge 171:3a7713b1edbc 207 #define HAL_ITLINE_EXTI14 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI14)) /*!< EXTI14 Interrupt */
AnnaBridge 171:3a7713b1edbc 208 #define HAL_ITLINE_EXTI15 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18U) | SYSCFG_ITLINE7_SR_EXTI15)) /*!< EXTI15 Interrupt */
AnnaBridge 171:3a7713b1edbc 209 #define HAL_ITLINE_TSC_EOA ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_TSC_EOA)) /*!< Touch control EOA Interrupt */
AnnaBridge 171:3a7713b1edbc 210 #define HAL_ITLINE_TSC_MCE ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18U) | SYSCFG_ITLINE8_SR_TSC_MCE)) /*!< Touch control MCE Interrupt */
AnnaBridge 171:3a7713b1edbc 211 #define HAL_ITLINE_DMA1_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE9 << 0x18U) | SYSCFG_ITLINE9_SR_DMA1_CH1)) /*!< DMA1 Channel 1 Interrupt */
AnnaBridge 171:3a7713b1edbc 212 #define HAL_ITLINE_DMA1_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH2)) /*!< DMA1 Channel 2 Interrupt */
AnnaBridge 171:3a7713b1edbc 213 #define HAL_ITLINE_DMA1_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH3)) /*!< DMA1 Channel 3 Interrupt */
AnnaBridge 171:3a7713b1edbc 214 #define HAL_ITLINE_DMA2_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA2_CH1)) /*!< DMA2 Channel 1 Interrupt */
AnnaBridge 171:3a7713b1edbc 215 #define HAL_ITLINE_DMA2_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18U) | SYSCFG_ITLINE10_SR_DMA2_CH2)) /*!< DMA2 Channel 2 Interrupt */
AnnaBridge 171:3a7713b1edbc 216 #define HAL_ITLINE_DMA1_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH4)) /*!< DMA1 Channel 4 Interrupt */
AnnaBridge 171:3a7713b1edbc 217 #define HAL_ITLINE_DMA1_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH5)) /*!< DMA1 Channel 5 Interrupt */
AnnaBridge 171:3a7713b1edbc 218 #define HAL_ITLINE_DMA1_CH6 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH6)) /*!< DMA1 Channel 6 Interrupt */
AnnaBridge 171:3a7713b1edbc 219 #define HAL_ITLINE_DMA1_CH7 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH7)) /*!< DMA1 Channel 7 Interrupt */
AnnaBridge 171:3a7713b1edbc 220 #define HAL_ITLINE_DMA2_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH3)) /*!< DMA2 Channel 3 Interrupt */
AnnaBridge 171:3a7713b1edbc 221 #define HAL_ITLINE_DMA2_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH4)) /*!< DMA2 Channel 4 Interrupt */
AnnaBridge 171:3a7713b1edbc 222 #define HAL_ITLINE_DMA2_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH5)) /*!< DMA2 Channel 5 Interrupt */
AnnaBridge 171:3a7713b1edbc 223 #define HAL_ITLINE_ADC ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_ADC)) /*!< ADC Interrupt */
AnnaBridge 171:3a7713b1edbc 224 #define HAL_ITLINE_COMP1 ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP1)) /*!< COMP1 Interrupt -> exti[21] */
AnnaBridge 171:3a7713b1edbc 225 #define HAL_ITLINE_COMP2 ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18U) | SYSCFG_ITLINE12_SR_COMP2)) /*!< COMP2 Interrupt -> exti[21] */
AnnaBridge 171:3a7713b1edbc 226 #define HAL_ITLINE_TIM1_BRK ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_BRK)) /*!< TIM1 BRK Interrupt */
AnnaBridge 171:3a7713b1edbc 227 #define HAL_ITLINE_TIM1_UPD ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_UPD)) /*!< TIM1 UPD Interrupt */
AnnaBridge 171:3a7713b1edbc 228 #define HAL_ITLINE_TIM1_TRG ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_TRG)) /*!< TIM1 TRG Interrupt */
AnnaBridge 171:3a7713b1edbc 229 #define HAL_ITLINE_TIM1_CCU ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18U) | SYSCFG_ITLINE13_SR_TIM1_CCU)) /*!< TIM1 CCU Interrupt */
AnnaBridge 171:3a7713b1edbc 230 #define HAL_ITLINE_TIM1_CC ((uint32_t) ((HAL_SYSCFG_ITLINE14 << 0x18U) | SYSCFG_ITLINE14_SR_TIM1_CC)) /*!< TIM1 CC Interrupt */
AnnaBridge 171:3a7713b1edbc 231 #define HAL_ITLINE_TIM2 ((uint32_t) ((HAL_SYSCFG_ITLINE15 << 0x18U) | SYSCFG_ITLINE15_SR_TIM2_GLB)) /*!< TIM2 Interrupt */
AnnaBridge 171:3a7713b1edbc 232 #define HAL_ITLINE_TIM3 ((uint32_t) ((HAL_SYSCFG_ITLINE16 << 0x18U) | SYSCFG_ITLINE16_SR_TIM3_GLB)) /*!< TIM3 Interrupt */
AnnaBridge 171:3a7713b1edbc 233 #define HAL_ITLINE_DAC ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_DAC)) /*!< DAC Interrupt */
AnnaBridge 171:3a7713b1edbc 234 #define HAL_ITLINE_TIM6 ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18U) | SYSCFG_ITLINE17_SR_TIM6_GLB)) /*!< TIM6 Interrupt */
AnnaBridge 171:3a7713b1edbc 235 #define HAL_ITLINE_TIM7 ((uint32_t) ((HAL_SYSCFG_ITLINE18 << 0x18U) | SYSCFG_ITLINE18_SR_TIM7_GLB)) /*!< TIM7 Interrupt */
AnnaBridge 171:3a7713b1edbc 236 #define HAL_ITLINE_TIM14 ((uint32_t) ((HAL_SYSCFG_ITLINE19 << 0x18U) | SYSCFG_ITLINE19_SR_TIM14_GLB)) /*!< TIM14 Interrupt */
AnnaBridge 171:3a7713b1edbc 237 #define HAL_ITLINE_TIM15 ((uint32_t) ((HAL_SYSCFG_ITLINE20 << 0x18U) | SYSCFG_ITLINE20_SR_TIM15_GLB)) /*!< TIM15 Interrupt */
AnnaBridge 171:3a7713b1edbc 238 #define HAL_ITLINE_TIM16 ((uint32_t) ((HAL_SYSCFG_ITLINE21 << 0x18U) | SYSCFG_ITLINE21_SR_TIM16_GLB)) /*!< TIM16 Interrupt */
AnnaBridge 171:3a7713b1edbc 239 #define HAL_ITLINE_TIM17 ((uint32_t) ((HAL_SYSCFG_ITLINE22 << 0x18U) | SYSCFG_ITLINE22_SR_TIM17_GLB)) /*!< TIM17 Interrupt */
AnnaBridge 171:3a7713b1edbc 240 #define HAL_ITLINE_I2C1 ((uint32_t) ((HAL_SYSCFG_ITLINE23 << 0x18U) | SYSCFG_ITLINE23_SR_I2C1_GLB)) /*!< I2C1 Interrupt -> exti[23] */
AnnaBridge 171:3a7713b1edbc 241 #define HAL_ITLINE_I2C2 ((uint32_t) ((HAL_SYSCFG_ITLINE24 << 0x18U) | SYSCFG_ITLINE24_SR_I2C2_GLB)) /*!< I2C2 Interrupt */
AnnaBridge 171:3a7713b1edbc 242 #define HAL_ITLINE_SPI1 ((uint32_t) ((HAL_SYSCFG_ITLINE25 << 0x18U) | SYSCFG_ITLINE25_SR_SPI1)) /*!< I2C1 Interrupt -> exti[23] */
AnnaBridge 171:3a7713b1edbc 243 #define HAL_ITLINE_SPI2 ((uint32_t) ((HAL_SYSCFG_ITLINE26 << 0x18U) | SYSCFG_ITLINE26_SR_SPI2)) /*!< SPI1 Interrupt */
AnnaBridge 171:3a7713b1edbc 244 #define HAL_ITLINE_USART1 ((uint32_t) ((HAL_SYSCFG_ITLINE27 << 0x18U) | SYSCFG_ITLINE27_SR_USART1_GLB)) /*!< USART1 GLB Interrupt -> exti[25] */
AnnaBridge 171:3a7713b1edbc 245 #define HAL_ITLINE_USART2 ((uint32_t) ((HAL_SYSCFG_ITLINE28 << 0x18U) | SYSCFG_ITLINE28_SR_USART2_GLB)) /*!< USART2 GLB Interrupt -> exti[26] */
AnnaBridge 171:3a7713b1edbc 246 #define HAL_ITLINE_USART3 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART3_GLB)) /*!< USART3 Interrupt .... */
AnnaBridge 171:3a7713b1edbc 247 #define HAL_ITLINE_USART4 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART4_GLB)) /*!< USART4 Interrupt .... */
AnnaBridge 171:3a7713b1edbc 248 #define HAL_ITLINE_USART5 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART5_GLB)) /*!< USART5 Interrupt .... */
AnnaBridge 171:3a7713b1edbc 249 #define HAL_ITLINE_USART6 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART6_GLB)) /*!< USART6 Interrupt .... */
AnnaBridge 171:3a7713b1edbc 250 #define HAL_ITLINE_USART7 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART7_GLB)) /*!< USART7 Interrupt .... */
AnnaBridge 171:3a7713b1edbc 251 #define HAL_ITLINE_USART8 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18U) | SYSCFG_ITLINE29_SR_USART8_GLB)) /*!< USART8 Interrupt .... */
AnnaBridge 171:3a7713b1edbc 252 #define HAL_ITLINE_CAN ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CAN)) /*!< CAN Interrupt */
AnnaBridge 171:3a7713b1edbc 253 #define HAL_ITLINE_CEC ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18U) | SYSCFG_ITLINE30_SR_CEC)) /*!< CEC Interrupt -> exti[27] */
AnnaBridge 171:3a7713b1edbc 254 /**
AnnaBridge 171:3a7713b1edbc 255 * @}
AnnaBridge 171:3a7713b1edbc 256 */
AnnaBridge 171:3a7713b1edbc 257 #endif /* STM32F091xC || STM32F098xx */
AnnaBridge 171:3a7713b1edbc 258
AnnaBridge 171:3a7713b1edbc 259 /**
AnnaBridge 171:3a7713b1edbc 260 * @}
AnnaBridge 171:3a7713b1edbc 261 */
AnnaBridge 171:3a7713b1edbc 262
AnnaBridge 171:3a7713b1edbc 263 /* Exported macros -----------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 264 /** @defgroup HAL_Exported_Macros HAL Exported Macros
AnnaBridge 171:3a7713b1edbc 265 * @{
AnnaBridge 171:3a7713b1edbc 266 */
AnnaBridge 171:3a7713b1edbc 267
AnnaBridge 171:3a7713b1edbc 268 /** @defgroup HAL_Freeze_Unfreeze_Peripherals HAL Freeze Unfreeze Peripherals
AnnaBridge 171:3a7713b1edbc 269 * @brief Freeze/Unfreeze Peripherals in Debug mode
AnnaBridge 171:3a7713b1edbc 270 * @{
AnnaBridge 171:3a7713b1edbc 271 */
AnnaBridge 171:3a7713b1edbc 272
AnnaBridge 171:3a7713b1edbc 273 #if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
AnnaBridge 171:3a7713b1edbc 274 #define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP))
AnnaBridge 171:3a7713b1edbc 275 #define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP))
AnnaBridge 171:3a7713b1edbc 276 #endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */
AnnaBridge 171:3a7713b1edbc 277
AnnaBridge 171:3a7713b1edbc 278 #if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP)
AnnaBridge 171:3a7713b1edbc 279 #define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
AnnaBridge 171:3a7713b1edbc 280 #define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
AnnaBridge 171:3a7713b1edbc 281 #endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */
AnnaBridge 171:3a7713b1edbc 282
AnnaBridge 171:3a7713b1edbc 283 #if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
AnnaBridge 171:3a7713b1edbc 284 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
AnnaBridge 171:3a7713b1edbc 285 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
AnnaBridge 171:3a7713b1edbc 286 #endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */
AnnaBridge 171:3a7713b1edbc 287
AnnaBridge 171:3a7713b1edbc 288 #if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP)
AnnaBridge 171:3a7713b1edbc 289 #define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
AnnaBridge 171:3a7713b1edbc 290 #define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
AnnaBridge 171:3a7713b1edbc 291 #endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */
AnnaBridge 171:3a7713b1edbc 292
AnnaBridge 171:3a7713b1edbc 293 #if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP)
AnnaBridge 171:3a7713b1edbc 294 #define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
AnnaBridge 171:3a7713b1edbc 295 #define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
AnnaBridge 171:3a7713b1edbc 296 #endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */
AnnaBridge 171:3a7713b1edbc 297
AnnaBridge 171:3a7713b1edbc 298 #if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
AnnaBridge 171:3a7713b1edbc 299 #define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
AnnaBridge 171:3a7713b1edbc 300 #define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
AnnaBridge 171:3a7713b1edbc 301 #endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
AnnaBridge 171:3a7713b1edbc 302
AnnaBridge 171:3a7713b1edbc 303 #if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
AnnaBridge 171:3a7713b1edbc 304 #define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
AnnaBridge 171:3a7713b1edbc 305 #define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
AnnaBridge 171:3a7713b1edbc 306 #endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
AnnaBridge 171:3a7713b1edbc 307
AnnaBridge 171:3a7713b1edbc 308 #if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
AnnaBridge 171:3a7713b1edbc 309 #define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
AnnaBridge 171:3a7713b1edbc 310 #define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
AnnaBridge 171:3a7713b1edbc 311 #endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
AnnaBridge 171:3a7713b1edbc 312
AnnaBridge 171:3a7713b1edbc 313 #if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
AnnaBridge 171:3a7713b1edbc 314 #define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
AnnaBridge 171:3a7713b1edbc 315 #define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
AnnaBridge 171:3a7713b1edbc 316 #endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
AnnaBridge 171:3a7713b1edbc 317
AnnaBridge 171:3a7713b1edbc 318 #if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
AnnaBridge 171:3a7713b1edbc 319 #define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
AnnaBridge 171:3a7713b1edbc 320 #define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
AnnaBridge 171:3a7713b1edbc 321 #endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
AnnaBridge 171:3a7713b1edbc 322
AnnaBridge 171:3a7713b1edbc 323 #if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
AnnaBridge 171:3a7713b1edbc 324 #define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
AnnaBridge 171:3a7713b1edbc 325 #define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
AnnaBridge 171:3a7713b1edbc 326 #endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */
AnnaBridge 171:3a7713b1edbc 327
AnnaBridge 171:3a7713b1edbc 328 #if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
AnnaBridge 171:3a7713b1edbc 329 #define __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP))
AnnaBridge 171:3a7713b1edbc 330 #define __HAL_DBGMCU_UNFREEZE_TIM15() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP))
AnnaBridge 171:3a7713b1edbc 331 #endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */
AnnaBridge 171:3a7713b1edbc 332
AnnaBridge 171:3a7713b1edbc 333 #if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP)
AnnaBridge 171:3a7713b1edbc 334 #define __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP))
AnnaBridge 171:3a7713b1edbc 335 #define __HAL_DBGMCU_UNFREEZE_TIM16() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP))
AnnaBridge 171:3a7713b1edbc 336 #endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */
AnnaBridge 171:3a7713b1edbc 337
AnnaBridge 171:3a7713b1edbc 338 #if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP)
AnnaBridge 171:3a7713b1edbc 339 #define __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP))
AnnaBridge 171:3a7713b1edbc 340 #define __HAL_DBGMCU_UNFREEZE_TIM17() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP))
AnnaBridge 171:3a7713b1edbc 341 #endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */
AnnaBridge 171:3a7713b1edbc 342
AnnaBridge 171:3a7713b1edbc 343 /**
AnnaBridge 171:3a7713b1edbc 344 * @}
AnnaBridge 171:3a7713b1edbc 345 */
AnnaBridge 171:3a7713b1edbc 346
AnnaBridge 171:3a7713b1edbc 347 /** @defgroup Memory_Mapping_Selection Memory Mapping Selection
AnnaBridge 171:3a7713b1edbc 348 * @{
AnnaBridge 171:3a7713b1edbc 349 */
AnnaBridge 171:3a7713b1edbc 350 #if defined(SYSCFG_CFGR1_MEM_MODE)
AnnaBridge 171:3a7713b1edbc 351 /** @brief Main Flash memory mapped at 0x00000000
AnnaBridge 171:3a7713b1edbc 352 */
AnnaBridge 171:3a7713b1edbc 353 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE))
AnnaBridge 171:3a7713b1edbc 354 #endif /* SYSCFG_CFGR1_MEM_MODE */
AnnaBridge 171:3a7713b1edbc 355
AnnaBridge 171:3a7713b1edbc 356 #if defined(SYSCFG_CFGR1_MEM_MODE_0)
AnnaBridge 171:3a7713b1edbc 357 /** @brief System Flash memory mapped at 0x00000000
AnnaBridge 171:3a7713b1edbc 358 */
AnnaBridge 171:3a7713b1edbc 359 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
AnnaBridge 171:3a7713b1edbc 360 SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \
AnnaBridge 171:3a7713b1edbc 361 }while(0)
AnnaBridge 171:3a7713b1edbc 362 #endif /* SYSCFG_CFGR1_MEM_MODE_0 */
AnnaBridge 171:3a7713b1edbc 363
AnnaBridge 171:3a7713b1edbc 364 #if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1)
AnnaBridge 171:3a7713b1edbc 365 /** @brief Embedded SRAM mapped at 0x00000000
AnnaBridge 171:3a7713b1edbc 366 */
AnnaBridge 171:3a7713b1edbc 367 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
AnnaBridge 171:3a7713b1edbc 368 SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \
AnnaBridge 171:3a7713b1edbc 369 }while(0)
AnnaBridge 171:3a7713b1edbc 370 #endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */
AnnaBridge 171:3a7713b1edbc 371 /**
AnnaBridge 171:3a7713b1edbc 372 * @}
AnnaBridge 171:3a7713b1edbc 373 */
AnnaBridge 171:3a7713b1edbc 374
AnnaBridge 171:3a7713b1edbc 375
AnnaBridge 171:3a7713b1edbc 376 #if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
AnnaBridge 171:3a7713b1edbc 377 /** @defgroup HAL_Pin_remap HAL Pin remap
AnnaBridge 171:3a7713b1edbc 378 * @brief Pin remapping enable/disable macros
AnnaBridge 171:3a7713b1edbc 379 * @param __PIN_REMAP__ This parameter can be a value of @ref HAL_Pin_remapping
AnnaBridge 171:3a7713b1edbc 380 * @{
AnnaBridge 171:3a7713b1edbc 381 */
AnnaBridge 171:3a7713b1edbc 382 #define __HAL_REMAP_PIN_ENABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \
AnnaBridge 171:3a7713b1edbc 383 SYSCFG->CFGR1 |= (__PIN_REMAP__); \
AnnaBridge 171:3a7713b1edbc 384 }while(0)
AnnaBridge 171:3a7713b1edbc 385 #define __HAL_REMAP_PIN_DISABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \
AnnaBridge 171:3a7713b1edbc 386 SYSCFG->CFGR1 &= ~(__PIN_REMAP__); \
AnnaBridge 171:3a7713b1edbc 387 }while(0)
AnnaBridge 171:3a7713b1edbc 388 /**
AnnaBridge 171:3a7713b1edbc 389 * @}
AnnaBridge 171:3a7713b1edbc 390 */
AnnaBridge 171:3a7713b1edbc 391 #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
AnnaBridge 171:3a7713b1edbc 392
AnnaBridge 171:3a7713b1edbc 393 /** @brief Fast-mode Plus driving capability enable/disable macros
AnnaBridge 171:3a7713b1edbc 394 * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values.
AnnaBridge 171:3a7713b1edbc 395 * That you can find above these macros.
AnnaBridge 171:3a7713b1edbc 396 */
AnnaBridge 171:3a7713b1edbc 397 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
AnnaBridge 171:3a7713b1edbc 398 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
AnnaBridge 171:3a7713b1edbc 399 }while(0)
AnnaBridge 171:3a7713b1edbc 400
AnnaBridge 171:3a7713b1edbc 401 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
AnnaBridge 171:3a7713b1edbc 402 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
AnnaBridge 171:3a7713b1edbc 403 }while(0)
AnnaBridge 171:3a7713b1edbc 404 #if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
AnnaBridge 171:3a7713b1edbc 405 /** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
AnnaBridge 171:3a7713b1edbc 406 * @{
AnnaBridge 171:3a7713b1edbc 407 */
AnnaBridge 171:3a7713b1edbc 408 /** @brief SYSCFG Break Lockup lock
AnnaBridge 171:3a7713b1edbc 409 * Enables and locks the connection of Cortex-M0 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input
AnnaBridge 171:3a7713b1edbc 410 * @note The selected configuration is locked and can be unlocked by system reset
AnnaBridge 171:3a7713b1edbc 411 */
AnnaBridge 171:3a7713b1edbc 412 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
AnnaBridge 171:3a7713b1edbc 413 SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
AnnaBridge 171:3a7713b1edbc 414 }while(0)
AnnaBridge 171:3a7713b1edbc 415 /**
AnnaBridge 171:3a7713b1edbc 416 * @}
AnnaBridge 171:3a7713b1edbc 417 */
AnnaBridge 171:3a7713b1edbc 418 #endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
AnnaBridge 171:3a7713b1edbc 419
AnnaBridge 171:3a7713b1edbc 420 #if defined(SYSCFG_CFGR2_PVD_LOCK)
AnnaBridge 171:3a7713b1edbc 421 /** @defgroup PVD_Lock_Enable PVD Lock
AnnaBridge 171:3a7713b1edbc 422 * @{
AnnaBridge 171:3a7713b1edbc 423 */
AnnaBridge 171:3a7713b1edbc 424 /** @brief SYSCFG Break PVD lock
AnnaBridge 171:3a7713b1edbc 425 * Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
AnnaBridge 171:3a7713b1edbc 426 * @note The selected configuration is locked and can be unlocked by system reset
AnnaBridge 171:3a7713b1edbc 427 */
AnnaBridge 171:3a7713b1edbc 428 #define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
AnnaBridge 171:3a7713b1edbc 429 SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
AnnaBridge 171:3a7713b1edbc 430 }while(0)
AnnaBridge 171:3a7713b1edbc 431 /**
AnnaBridge 171:3a7713b1edbc 432 * @}
AnnaBridge 171:3a7713b1edbc 433 */
AnnaBridge 171:3a7713b1edbc 434 #endif /* SYSCFG_CFGR2_PVD_LOCK */
AnnaBridge 171:3a7713b1edbc 435
AnnaBridge 171:3a7713b1edbc 436 #if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
AnnaBridge 171:3a7713b1edbc 437 /** @defgroup SRAM_Parity_Lock SRAM Parity Lock
AnnaBridge 171:3a7713b1edbc 438 * @{
AnnaBridge 171:3a7713b1edbc 439 */
AnnaBridge 171:3a7713b1edbc 440 /** @brief SYSCFG Break SRAM PARITY lock
AnnaBridge 171:3a7713b1edbc 441 * Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17
AnnaBridge 171:3a7713b1edbc 442 * @note The selected configuration is locked and can be unlocked by system reset
AnnaBridge 171:3a7713b1edbc 443 */
AnnaBridge 171:3a7713b1edbc 444 #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \
AnnaBridge 171:3a7713b1edbc 445 SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \
AnnaBridge 171:3a7713b1edbc 446 }while(0)
AnnaBridge 171:3a7713b1edbc 447 /**
AnnaBridge 171:3a7713b1edbc 448 * @}
AnnaBridge 171:3a7713b1edbc 449 */
AnnaBridge 171:3a7713b1edbc 450 #endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */
AnnaBridge 171:3a7713b1edbc 451
AnnaBridge 171:3a7713b1edbc 452 #if defined(SYSCFG_CFGR2_SRAM_PEF)
AnnaBridge 171:3a7713b1edbc 453 /** @defgroup HAL_SYSCFG_Parity_check_on_RAM HAL SYSCFG Parity check on RAM
AnnaBridge 171:3a7713b1edbc 454 * @brief Parity check on RAM disable macro
AnnaBridge 171:3a7713b1edbc 455 * @note Disabling the parity check on RAM locks the configuration bit.
AnnaBridge 171:3a7713b1edbc 456 * To re-enable the parity check on RAM perform a system reset.
AnnaBridge 171:3a7713b1edbc 457 * @{
AnnaBridge 171:3a7713b1edbc 458 */
AnnaBridge 171:3a7713b1edbc 459 #define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PEF)
AnnaBridge 171:3a7713b1edbc 460 /**
AnnaBridge 171:3a7713b1edbc 461 * @}
AnnaBridge 171:3a7713b1edbc 462 */
AnnaBridge 171:3a7713b1edbc 463 #endif /* SYSCFG_CFGR2_SRAM_PEF */
AnnaBridge 171:3a7713b1edbc 464
AnnaBridge 171:3a7713b1edbc 465
AnnaBridge 171:3a7713b1edbc 466 #if defined(STM32F091xC) || defined (STM32F098xx)
AnnaBridge 171:3a7713b1edbc 467 /** @defgroup HAL_ISR_wrapper_check HAL ISR wrapper check
AnnaBridge 171:3a7713b1edbc 468 * @brief ISR wrapper check
AnnaBridge 171:3a7713b1edbc 469 * @note This feature is applicable on STM32F09x
AnnaBridge 171:3a7713b1edbc 470 * @note Allow to determine interrupt source per line.
AnnaBridge 171:3a7713b1edbc 471 * @{
AnnaBridge 171:3a7713b1edbc 472 */
AnnaBridge 171:3a7713b1edbc 473 #define __HAL_GET_PENDING_IT(__SOURCE__) (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18U)] & ((__SOURCE__) & 0x00FFFFFF))
AnnaBridge 171:3a7713b1edbc 474 /**
AnnaBridge 171:3a7713b1edbc 475 * @}
AnnaBridge 171:3a7713b1edbc 476 */
AnnaBridge 171:3a7713b1edbc 477 #endif /* (STM32F091xC) || defined (STM32F098xx)*/
AnnaBridge 171:3a7713b1edbc 478
AnnaBridge 171:3a7713b1edbc 479 #if defined(STM32F091xC) || defined (STM32F098xx)
AnnaBridge 171:3a7713b1edbc 480 /** @defgroup HAL_SYSCFG_IRDA_modulation_envelope_selection HAL SYSCFG IRDA modulation envelope selection
AnnaBridge 171:3a7713b1edbc 481 * @brief selection of the modulation envelope signal macro, using bits [7:6] of SYS_CTRL(CFGR1) register
AnnaBridge 171:3a7713b1edbc 482 * @note This feature is applicable on STM32F09x
AnnaBridge 171:3a7713b1edbc 483 * @param __SOURCE__ This parameter can be a value of @ref HAL_IRDA_ENV_SEL
AnnaBridge 171:3a7713b1edbc 484 * @{
AnnaBridge 171:3a7713b1edbc 485 */
AnnaBridge 171:3a7713b1edbc 486 #define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__) do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__))); \
AnnaBridge 171:3a7713b1edbc 487 SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_IRDA_ENV_SEL); \
AnnaBridge 171:3a7713b1edbc 488 SYSCFG->CFGR1 |= (__SOURCE__); \
AnnaBridge 171:3a7713b1edbc 489 }while(0)
AnnaBridge 171:3a7713b1edbc 490
AnnaBridge 171:3a7713b1edbc 491 #define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION() ((SYSCFG->CFGR1) & 0x000000C0)
AnnaBridge 171:3a7713b1edbc 492 /**
AnnaBridge 171:3a7713b1edbc 493 * @}
AnnaBridge 171:3a7713b1edbc 494 */
AnnaBridge 171:3a7713b1edbc 495 #endif /* (STM32F091xC) || defined (STM32F098xx)*/
AnnaBridge 171:3a7713b1edbc 496
AnnaBridge 171:3a7713b1edbc 497 /**
AnnaBridge 171:3a7713b1edbc 498 * @}
AnnaBridge 171:3a7713b1edbc 499 */
AnnaBridge 171:3a7713b1edbc 500
AnnaBridge 171:3a7713b1edbc 501 /* Exported functions --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 502
AnnaBridge 171:3a7713b1edbc 503 /** @addtogroup HAL_Exported_Functions
AnnaBridge 171:3a7713b1edbc 504 * @{
AnnaBridge 171:3a7713b1edbc 505 */
AnnaBridge 171:3a7713b1edbc 506
AnnaBridge 171:3a7713b1edbc 507 /** @addtogroup HAL_Exported_Functions_Group1
AnnaBridge 171:3a7713b1edbc 508 * @{
AnnaBridge 171:3a7713b1edbc 509 */
AnnaBridge 171:3a7713b1edbc 510 /* Initialization and de-initialization functions ******************************/
AnnaBridge 171:3a7713b1edbc 511 HAL_StatusTypeDef HAL_Init(void);
AnnaBridge 171:3a7713b1edbc 512 HAL_StatusTypeDef HAL_DeInit(void);
AnnaBridge 171:3a7713b1edbc 513 void HAL_MspInit(void);
AnnaBridge 171:3a7713b1edbc 514 void HAL_MspDeInit(void);
AnnaBridge 171:3a7713b1edbc 515 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
AnnaBridge 171:3a7713b1edbc 516 /**
AnnaBridge 171:3a7713b1edbc 517 * @}
AnnaBridge 171:3a7713b1edbc 518 */
AnnaBridge 171:3a7713b1edbc 519
AnnaBridge 171:3a7713b1edbc 520 /** @addtogroup HAL_Exported_Functions_Group2
AnnaBridge 171:3a7713b1edbc 521 * @{
AnnaBridge 171:3a7713b1edbc 522 */
AnnaBridge 171:3a7713b1edbc 523
AnnaBridge 171:3a7713b1edbc 524 /* Peripheral Control functions ************************************************/
AnnaBridge 171:3a7713b1edbc 525 void HAL_IncTick(void);
AnnaBridge 171:3a7713b1edbc 526 void HAL_Delay(__IO uint32_t Delay);
AnnaBridge 171:3a7713b1edbc 527 uint32_t HAL_GetTick(void);
AnnaBridge 171:3a7713b1edbc 528 void HAL_SuspendTick(void);
AnnaBridge 171:3a7713b1edbc 529 void HAL_ResumeTick(void);
AnnaBridge 171:3a7713b1edbc 530 uint32_t HAL_GetHalVersion(void);
AnnaBridge 171:3a7713b1edbc 531 uint32_t HAL_GetREVID(void);
AnnaBridge 171:3a7713b1edbc 532 uint32_t HAL_GetDEVID(void);
AnnaBridge 171:3a7713b1edbc 533 uint32_t HAL_GetUIDw0(void);
AnnaBridge 171:3a7713b1edbc 534 uint32_t HAL_GetUIDw1(void);
AnnaBridge 171:3a7713b1edbc 535 uint32_t HAL_GetUIDw2(void);
AnnaBridge 171:3a7713b1edbc 536 void HAL_DBGMCU_EnableDBGStopMode(void);
AnnaBridge 171:3a7713b1edbc 537 void HAL_DBGMCU_DisableDBGStopMode(void);
AnnaBridge 171:3a7713b1edbc 538 void HAL_DBGMCU_EnableDBGStandbyMode(void);
AnnaBridge 171:3a7713b1edbc 539 void HAL_DBGMCU_DisableDBGStandbyMode(void);
AnnaBridge 171:3a7713b1edbc 540 /**
AnnaBridge 171:3a7713b1edbc 541 * @}
AnnaBridge 171:3a7713b1edbc 542 */
AnnaBridge 171:3a7713b1edbc 543
AnnaBridge 171:3a7713b1edbc 544 /**
AnnaBridge 171:3a7713b1edbc 545 * @}
AnnaBridge 171:3a7713b1edbc 546 */
AnnaBridge 171:3a7713b1edbc 547
AnnaBridge 171:3a7713b1edbc 548 /**
AnnaBridge 171:3a7713b1edbc 549 * @}
AnnaBridge 171:3a7713b1edbc 550 */
AnnaBridge 171:3a7713b1edbc 551
AnnaBridge 171:3a7713b1edbc 552 /**
AnnaBridge 171:3a7713b1edbc 553 * @}
AnnaBridge 171:3a7713b1edbc 554 */
AnnaBridge 171:3a7713b1edbc 555
AnnaBridge 171:3a7713b1edbc 556 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 557 }
AnnaBridge 171:3a7713b1edbc 558 #endif
AnnaBridge 171:3a7713b1edbc 559
AnnaBridge 171:3a7713b1edbc 560 #endif /* __STM32F0xx_HAL_H */
AnnaBridge 171:3a7713b1edbc 561
AnnaBridge 171:3a7713b1edbc 562 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/