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TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_STD/stm32f0xx_ll_system.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	171:3a7713b1edbc	1	/**
AnnaBridge	171:3a7713b1edbc	2	******************************************************************************
AnnaBridge	171:3a7713b1edbc	3	* @file stm32f0xx_ll_system.h
AnnaBridge	171:3a7713b1edbc	4	* @author MCD Application Team
AnnaBridge	171:3a7713b1edbc	5	* @brief Header file of SYSTEM LL module.
AnnaBridge	171:3a7713b1edbc	6	@verbatim
AnnaBridge	171:3a7713b1edbc	7	==============================================================================
AnnaBridge	171:3a7713b1edbc	8	##### How to use this driver #####
AnnaBridge	171:3a7713b1edbc	9	==============================================================================
AnnaBridge	171:3a7713b1edbc	10	[..]
AnnaBridge	171:3a7713b1edbc	11	The LL SYSTEM driver contains a set of generic APIs that can be
AnnaBridge	171:3a7713b1edbc	12	used by user:
AnnaBridge	171:3a7713b1edbc	13	(+) Some of the FLASH features need to be handled in the SYSTEM file.
AnnaBridge	171:3a7713b1edbc	14	(+) Access to DBGCMU registers
AnnaBridge	171:3a7713b1edbc	15	(+) Access to SYSCFG registers
AnnaBridge	171:3a7713b1edbc	16
AnnaBridge	171:3a7713b1edbc	17	@endverbatim
AnnaBridge	171:3a7713b1edbc	18	******************************************************************************
AnnaBridge	171:3a7713b1edbc	19	* @attention
AnnaBridge	171:3a7713b1edbc	20	*
AnnaBridge	171:3a7713b1edbc	21	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	171:3a7713b1edbc	22	*
AnnaBridge	171:3a7713b1edbc	23	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	171:3a7713b1edbc	24	* are permitted provided that the following conditions are met:
AnnaBridge	171:3a7713b1edbc	25	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	171:3a7713b1edbc	26	* this list of conditions and the following disclaimer.
AnnaBridge	171:3a7713b1edbc	27	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	171:3a7713b1edbc	28	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	171:3a7713b1edbc	29	* and/or other materials provided with the distribution.
AnnaBridge	171:3a7713b1edbc	30	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	171:3a7713b1edbc	31	* may be used to endorse or promote products derived from this software
AnnaBridge	171:3a7713b1edbc	32	* without specific prior written permission.
AnnaBridge	171:3a7713b1edbc	33	*
AnnaBridge	171:3a7713b1edbc	34	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	171:3a7713b1edbc	35	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	171:3a7713b1edbc	36	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	171:3a7713b1edbc	37	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	171:3a7713b1edbc	38	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	171:3a7713b1edbc	39	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	171:3a7713b1edbc	40	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	171:3a7713b1edbc	41	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	171:3a7713b1edbc	42	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	171:3a7713b1edbc	43	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	171:3a7713b1edbc	44	*
AnnaBridge	171:3a7713b1edbc	45	******************************************************************************
AnnaBridge	171:3a7713b1edbc	46	*/
AnnaBridge	171:3a7713b1edbc	47
AnnaBridge	171:3a7713b1edbc	48	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	171:3a7713b1edbc	49	#ifndef __STM32F0xx_LL_SYSTEM_H
AnnaBridge	171:3a7713b1edbc	50	#define __STM32F0xx_LL_SYSTEM_H
AnnaBridge	171:3a7713b1edbc	51
AnnaBridge	171:3a7713b1edbc	52	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	53	extern "C" {
AnnaBridge	171:3a7713b1edbc	54	#endif
AnnaBridge	171:3a7713b1edbc	55
AnnaBridge	171:3a7713b1edbc	56	/* Includes ------------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	57	#include "stm32f0xx.h"
AnnaBridge	171:3a7713b1edbc	58
AnnaBridge	171:3a7713b1edbc	59	/** @addtogroup STM32F0xx_LL_Driver
AnnaBridge	171:3a7713b1edbc	60	* @{
AnnaBridge	171:3a7713b1edbc	61	*/
AnnaBridge	171:3a7713b1edbc	62
AnnaBridge	171:3a7713b1edbc	63	#if defined (FLASH) \|\| defined (SYSCFG) \|\| defined (DBGMCU)
AnnaBridge	171:3a7713b1edbc	64
AnnaBridge	171:3a7713b1edbc	65	/** @defgroup SYSTEM_LL SYSTEM
AnnaBridge	171:3a7713b1edbc	66	* @{
AnnaBridge	171:3a7713b1edbc	67	*/
AnnaBridge	171:3a7713b1edbc	68
AnnaBridge	171:3a7713b1edbc	69	/* Private types -------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	70	/* Private variables ---------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	71
AnnaBridge	171:3a7713b1edbc	72	/* Private constants ---------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	73	/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
AnnaBridge	171:3a7713b1edbc	74	* @{
AnnaBridge	171:3a7713b1edbc	75	*/
AnnaBridge	171:3a7713b1edbc	76
AnnaBridge	171:3a7713b1edbc	77	/**
AnnaBridge	171:3a7713b1edbc	78	* @}
AnnaBridge	171:3a7713b1edbc	79	*/
AnnaBridge	171:3a7713b1edbc	80
AnnaBridge	171:3a7713b1edbc	81	/* Private macros ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	82
AnnaBridge	171:3a7713b1edbc	83	/* Exported types ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	84	/* Exported constants --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	85	/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
AnnaBridge	171:3a7713b1edbc	86	* @{
AnnaBridge	171:3a7713b1edbc	87	*/
AnnaBridge	171:3a7713b1edbc	88
AnnaBridge	171:3a7713b1edbc	89	/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG Remap
AnnaBridge	171:3a7713b1edbc	90	* @{
AnnaBridge	171:3a7713b1edbc	91	*/
AnnaBridge	171:3a7713b1edbc	92	#define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000U /!< Main Flash memory mapped at 0x00000000 /
AnnaBridge	171:3a7713b1edbc	93	#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /!< System Flash memory mapped at 0x00000000 /
AnnaBridge	171:3a7713b1edbc	94	#define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 \| SYSCFG_CFGR1_MEM_MODE_0) /!< Embedded SRAM mapped at 0x00000000 /
AnnaBridge	171:3a7713b1edbc	95	/**
AnnaBridge	171:3a7713b1edbc	96	* @}
AnnaBridge	171:3a7713b1edbc	97	*/
AnnaBridge	171:3a7713b1edbc	98
AnnaBridge	171:3a7713b1edbc	99	#if defined(SYSCFG_CFGR1_IR_MOD)
AnnaBridge	171:3a7713b1edbc	100	/** @defgroup SYSTEM_LL_EC_IR_MOD SYSCFG IR Modulation
AnnaBridge	171:3a7713b1edbc	101	* @{
AnnaBridge	171:3a7713b1edbc	102	*/
AnnaBridge	171:3a7713b1edbc	103	#define LL_SYSCFG_IR_MOD_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1) /!< Timer16 is selected as IR Modulation enveloppe source /
AnnaBridge	171:3a7713b1edbc	104	#define LL_SYSCFG_IR_MOD_USART1 (SYSCFG_CFGR1_IR_MOD_0) /!< USART1 is selected as IR Modulation enveloppe source /
AnnaBridge	171:3a7713b1edbc	105	#define LL_SYSCFG_IR_MOD_USART4 (SYSCFG_CFGR1_IR_MOD_1) /!< USART4 is selected as IR Modulation enveloppe source /
AnnaBridge	171:3a7713b1edbc	106	/**
AnnaBridge	171:3a7713b1edbc	107	* @}
AnnaBridge	171:3a7713b1edbc	108	*/
AnnaBridge	171:3a7713b1edbc	109
AnnaBridge	171:3a7713b1edbc	110	#endif /* SYSCFG_CFGR1_IR_MOD */
AnnaBridge	171:3a7713b1edbc	111
AnnaBridge	171:3a7713b1edbc	112	#if defined(SYSCFG_CFGR1_USART1TX_DMA_RMP) \|\| defined(SYSCFG_CFGR1_USART1RX_DMA_RMP) \|\| defined(SYSCFG_CFGR1_USART2_DMA_RMP) \|\| defined(SYSCFG_CFGR1_USART3_DMA_RMP)
AnnaBridge	171:3a7713b1edbc	113	/** @defgroup SYSTEM_LL_EC_USART1TX_RMP SYSCFG USART DMA Remap
AnnaBridge	171:3a7713b1edbc	114	* @{
AnnaBridge	171:3a7713b1edbc	115	*/
AnnaBridge	171:3a7713b1edbc	116	#if defined (SYSCFG_CFGR1_USART1TX_DMA_RMP)
AnnaBridge	171:3a7713b1edbc	117	#define LL_SYSCFG_USART1TX_RMP_DMA1CH2 ((SYSCFG_CFGR1_USART1TX_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< USART1_TX DMA request mapped on DMA channel 2U /
AnnaBridge	171:3a7713b1edbc	118	#define LL_SYSCFG_USART1TX_RMP_DMA1CH4 ((SYSCFG_CFGR1_USART1TX_DMA_RMP >> 8U) \| SYSCFG_CFGR1_USART1TX_DMA_RMP) /!< USART1_TX DMA request mapped on DMA channel 4U /
AnnaBridge	171:3a7713b1edbc	119	#endif /SYSCFG_CFGR1_USART1TX_DMA_RMP/
AnnaBridge	171:3a7713b1edbc	120	#if defined (SYSCFG_CFGR1_USART1RX_DMA_RMP)
AnnaBridge	171:3a7713b1edbc	121	#define LL_SYSCFG_USART1RX_RMP_DMA1CH3 ((SYSCFG_CFGR1_USART1RX_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< USART1_RX DMA request mapped on DMA channel 3U /
AnnaBridge	171:3a7713b1edbc	122	#define LL_SYSCFG_USART1RX_RMP_DMA1CH5 ((SYSCFG_CFGR1_USART1RX_DMA_RMP >> 8U) \| SYSCFG_CFGR1_USART1RX_DMA_RMP) /!< USART1_RX DMA request mapped on DMA channel 5 /
AnnaBridge	171:3a7713b1edbc	123	#endif /SYSCFG_CFGR1_USART1RX_DMA_RMP/
AnnaBridge	171:3a7713b1edbc	124	#if defined (SYSCFG_CFGR1_USART2_DMA_RMP)
AnnaBridge	171:3a7713b1edbc	125	#define LL_SYSCFG_USART2_RMP_DMA1CH54 ((SYSCFG_CFGR1_USART2_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4U respectively /
AnnaBridge	171:3a7713b1edbc	126	#define LL_SYSCFG_USART2_RMP_DMA1CH67 ((SYSCFG_CFGR1_USART2_DMA_RMP >> 8U) \| SYSCFG_CFGR1_USART2_DMA_RMP) /!< USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively /
AnnaBridge	171:3a7713b1edbc	127	#endif /SYSCFG_CFGR1_USART2_DMA_RMP/
AnnaBridge	171:3a7713b1edbc	128	#if defined (SYSCFG_CFGR1_USART3_DMA_RMP)
AnnaBridge	171:3a7713b1edbc	129	#define LL_SYSCFG_USART3_RMP_DMA1CH67 ((SYSCFG_CFGR1_USART3_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively /
AnnaBridge	171:3a7713b1edbc	130	#define LL_SYSCFG_USART3_RMP_DMA1CH32 ((SYSCFG_CFGR1_USART3_DMA_RMP >> 8U) \| SYSCFG_CFGR1_USART3_DMA_RMP) /!< USART3_RX and USART3_TX DMA requests mapped on DMA channel 3U and 2U respectively /
AnnaBridge	171:3a7713b1edbc	131	#endif /* SYSCFG_CFGR1_USART3_DMA_RMP */
AnnaBridge	171:3a7713b1edbc	132	/**
AnnaBridge	171:3a7713b1edbc	133	* @}
AnnaBridge	171:3a7713b1edbc	134	*/
AnnaBridge	171:3a7713b1edbc	135	#endif /* SYSCFG_CFGR1_USART1TX_DMA_RMP \|\| SYSCFG_CFGR1_USART1RX_DMA_RMP \|\| SYSCFG_CFGR1_USART2_DMA_RMP \|\| SYSCFG_CFGR1_USART3_DMA_RMP */
AnnaBridge	171:3a7713b1edbc	136
AnnaBridge	171:3a7713b1edbc	137	#if defined (SYSCFG_CFGR1_SPI2_DMA_RMP)
AnnaBridge	171:3a7713b1edbc	138	/** @defgroup SYSTEM_LL_EC_SPI2_RMP_DMA1 SYSCFG SPI2 DMA Remap
AnnaBridge	171:3a7713b1edbc	139	* @{
AnnaBridge	171:3a7713b1edbc	140	*/
AnnaBridge	171:3a7713b1edbc	141	#define LL_SYSCFG_SPI2_RMP_DMA1_CH45 (uint32_t)0x00000000U /!< SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4U and 5 respectively /
AnnaBridge	171:3a7713b1edbc	142	#define LL_SYSCFG_SPI2_RMP_DMA1_CH67 SYSCFG_CFGR1_SPI2_DMA_RMP /!< SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively /
AnnaBridge	171:3a7713b1edbc	143	/**
AnnaBridge	171:3a7713b1edbc	144	* @}
AnnaBridge	171:3a7713b1edbc	145	*/
AnnaBridge	171:3a7713b1edbc	146
AnnaBridge	171:3a7713b1edbc	147	#endif /SYSCFG_CFGR1_SPI2_DMA_RMP/
AnnaBridge	171:3a7713b1edbc	148
AnnaBridge	171:3a7713b1edbc	149	#if defined (SYSCFG_CFGR1_I2C1_DMA_RMP)
AnnaBridge	171:3a7713b1edbc	150	/** @defgroup SYSTEM_LL_EC_I2C1_RMP_DMA1 SYSCFG I2C1 DMA Remap
AnnaBridge	171:3a7713b1edbc	151	* @{
AnnaBridge	171:3a7713b1edbc	152	*/
AnnaBridge	171:3a7713b1edbc	153	#define LL_SYSCFG_I2C1_RMP_DMA1_CH32 (uint32_t)0x00000000U /!< I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3U and 2U respectively /
AnnaBridge	171:3a7713b1edbc	154	#define LL_SYSCFG_I2C1_RMP_DMA1_CH76 SYSCFG_CFGR1_I2C1_DMA_RMP /!< I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively /
AnnaBridge	171:3a7713b1edbc	155	/**
AnnaBridge	171:3a7713b1edbc	156	* @}
AnnaBridge	171:3a7713b1edbc	157	*/
AnnaBridge	171:3a7713b1edbc	158
AnnaBridge	171:3a7713b1edbc	159	#endif /SYSCFG_CFGR1_I2C1_DMA_RMP/
AnnaBridge	171:3a7713b1edbc	160
AnnaBridge	171:3a7713b1edbc	161	#if defined(SYSCFG_CFGR1_ADC_DMA_RMP)
AnnaBridge	171:3a7713b1edbc	162	/** @defgroup SYSTEM_LL_EC_ADC1_RMP_DMA1 SYSCFG ADC1 DMA Remap
AnnaBridge	171:3a7713b1edbc	163	* @{
AnnaBridge	171:3a7713b1edbc	164	*/
AnnaBridge	171:3a7713b1edbc	165	#define LL_SYSCFG_ADC1_RMP_DMA1_CH1 (uint32_t)0x00000000U /!< ADC DMA request mapped on DMA channel 1U /
AnnaBridge	171:3a7713b1edbc	166	#define LL_SYSCFG_ADC1_RMP_DMA1_CH2 SYSCFG_CFGR1_ADC_DMA_RMP /!< ADC DMA request mapped on DMA channel 2U /
AnnaBridge	171:3a7713b1edbc	167	/**
AnnaBridge	171:3a7713b1edbc	168	* @}
AnnaBridge	171:3a7713b1edbc	169	*/
AnnaBridge	171:3a7713b1edbc	170
AnnaBridge	171:3a7713b1edbc	171	#endif /* SYSCFG_CFGR1_ADC_DMA_RMP */
AnnaBridge	171:3a7713b1edbc	172
AnnaBridge	171:3a7713b1edbc	173	#if defined(SYSCFG_CFGR1_TIM16_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM17_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM1_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM2_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM3_DMA_RMP)
AnnaBridge	171:3a7713b1edbc	174	/** @defgroup SYSTEM_LL_EC_TIM16_RMP_DMA1 SYSCFG TIM DMA Remap
AnnaBridge	171:3a7713b1edbc	175	* @{
AnnaBridge	171:3a7713b1edbc	176	*/
AnnaBridge	171:3a7713b1edbc	177	#if defined(SYSCFG_CFGR1_TIM16_DMA_RMP)
AnnaBridge	171:3a7713b1edbc	178	#if defined (SYSCFG_CFGR1_TIM16_DMA_RMP2)
AnnaBridge	171:3a7713b1edbc	179	#define LL_SYSCFG_TIM16_RMP_DMA1_CH3 (((SYSCFG_CFGR1_TIM16_DMA_RMP \| SYSCFG_CFGR1_TIM16_DMA_RMP2) >> 8U) \| (uint32_t)0x00000000U) /!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 /
AnnaBridge	171:3a7713b1edbc	180	#define LL_SYSCFG_TIM16_RMP_DMA1_CH4 (((SYSCFG_CFGR1_TIM16_DMA_RMP \| SYSCFG_CFGR1_TIM16_DMA_RMP2) >> 8U) \| SYSCFG_CFGR1_TIM16_DMA_RMP) /!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4 /
AnnaBridge	171:3a7713b1edbc	181	#define LL_SYSCFG_TIM16_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM16_DMA_RMP2 >> 8U) \| SYSCFG_CFGR1_TIM16_DMA_RMP2) /!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6 /
AnnaBridge	171:3a7713b1edbc	182	#else
AnnaBridge	171:3a7713b1edbc	183	#define LL_SYSCFG_TIM16_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM16_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3 /
AnnaBridge	171:3a7713b1edbc	184	#define LL_SYSCFG_TIM16_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM16_DMA_RMP >> 8U) \| SYSCFG_CFGR1_TIM16_DMA_RMP) /!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4 /
AnnaBridge	171:3a7713b1edbc	185	#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP2 */
AnnaBridge	171:3a7713b1edbc	186	#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP */
AnnaBridge	171:3a7713b1edbc	187	#if defined(SYSCFG_CFGR1_TIM17_DMA_RMP)
AnnaBridge	171:3a7713b1edbc	188	#if defined (SYSCFG_CFGR1_TIM17_DMA_RMP2)
AnnaBridge	171:3a7713b1edbc	189	#define LL_SYSCFG_TIM17_RMP_DMA1_CH1 (((SYSCFG_CFGR1_TIM17_DMA_RMP \| SYSCFG_CFGR1_TIM17_DMA_RMP2) >> 8U) \| (uint32_t)0x00000000U) /!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 /
AnnaBridge	171:3a7713b1edbc	190	#define LL_SYSCFG_TIM17_RMP_DMA1_CH2 (((SYSCFG_CFGR1_TIM17_DMA_RMP \| SYSCFG_CFGR1_TIM17_DMA_RMP2) >> 8U) \| SYSCFG_CFGR1_TIM17_DMA_RMP) /!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2 /
AnnaBridge	171:3a7713b1edbc	191	#define LL_SYSCFG_TIM17_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM17_DMA_RMP2 >> 8U) \| SYSCFG_CFGR1_TIM17_DMA_RMP2) /!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7 /
AnnaBridge	171:3a7713b1edbc	192	#else
AnnaBridge	171:3a7713b1edbc	193	#define LL_SYSCFG_TIM17_RMP_DMA1_CH1 ((SYSCFG_CFGR1_TIM17_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 /
AnnaBridge	171:3a7713b1edbc	194	#define LL_SYSCFG_TIM17_RMP_DMA1_CH2 ((SYSCFG_CFGR1_TIM17_DMA_RMP >> 8U) \| SYSCFG_CFGR1_TIM17_DMA_RMP) /!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2 /
AnnaBridge	171:3a7713b1edbc	195	#endif /* SYSCFG_CFGR1_TIM17_DMA_RMP2 */
AnnaBridge	171:3a7713b1edbc	196	#endif /* SYSCFG_CFGR1_TIM17_DMA_RMP */
AnnaBridge	171:3a7713b1edbc	197	#if defined (SYSCFG_CFGR1_TIM1_DMA_RMP)
AnnaBridge	171:3a7713b1edbc	198	#define LL_SYSCFG_TIM1_RMP_DMA1_CH234 ((SYSCFG_CFGR1_TIM1_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMAchannel 2, 3 and 4 respectively /
AnnaBridge	171:3a7713b1edbc	199	#define LL_SYSCFG_TIM1_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM1_DMA_RMP >> 8U) \| SYSCFG_CFGR1_TIM1_DMA_RMP) /!< TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 /
AnnaBridge	171:3a7713b1edbc	200	#endif /SYSCFG_CFGR1_TIM1_DMA_RMP/
AnnaBridge	171:3a7713b1edbc	201	#if defined (SYSCFG_CFGR1_TIM2_DMA_RMP)
AnnaBridge	171:3a7713b1edbc	202	#define LL_SYSCFG_TIM2_RMP_DMA1_CH34 ((SYSCFG_CFGR1_TIM2_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively /
AnnaBridge	171:3a7713b1edbc	203	#define LL_SYSCFG_TIM2_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM2_DMA_RMP >> 8U) \| SYSCFG_CFGR1_TIM2_DMA_RMP) /!< TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 /
AnnaBridge	171:3a7713b1edbc	204	#endif /SYSCFG_CFGR1_TIM2_DMA_RMP/
AnnaBridge	171:3a7713b1edbc	205	#if defined (SYSCFG_CFGR1_TIM3_DMA_RMP)
AnnaBridge	171:3a7713b1edbc	206	#define LL_SYSCFG_TIM3_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM3_DMA_RMP >> 8U) \| (uint32_t)0x00000000U) /!< TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4 /
AnnaBridge	171:3a7713b1edbc	207	#define LL_SYSCFG_TIM3_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM3_DMA_RMP >> 8U) \| SYSCFG_CFGR1_TIM3_DMA_RMP) /!< TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6 /
AnnaBridge	171:3a7713b1edbc	208	#endif /SYSCFG_CFGR1_TIM3_DMA_RMP/
AnnaBridge	171:3a7713b1edbc	209	/**
AnnaBridge	171:3a7713b1edbc	210	* @}
AnnaBridge	171:3a7713b1edbc	211	*/
AnnaBridge	171:3a7713b1edbc	212
AnnaBridge	171:3a7713b1edbc	213	#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP \|\| SYSCFG_CFGR1_TIM17_DMA_RMP \|\| SYSCFG_CFGR1_TIM1_DMA_RMP \|\| SYSCFG_CFGR1_TIM2_DMA_RMP \|\| SYSCFG_CFGR1_TIM3_DMA_RMP */
AnnaBridge	171:3a7713b1edbc	214
AnnaBridge	171:3a7713b1edbc	215	/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
AnnaBridge	171:3a7713b1edbc	216	* @{
AnnaBridge	171:3a7713b1edbc	217	*/
AnnaBridge	171:3a7713b1edbc	218	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /!< I2C PB6 Fast mode plus /
AnnaBridge	171:3a7713b1edbc	219	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /!< I2C PB7 Fast mode plus /
AnnaBridge	171:3a7713b1edbc	220	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /!< I2C PB8 Fast mode plus /
AnnaBridge	171:3a7713b1edbc	221	#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /!< I2C PB9 Fast mode plus /
AnnaBridge	171:3a7713b1edbc	222	#if defined(SYSCFG_CFGR1_I2C_FMP_I2C1)
AnnaBridge	171:3a7713b1edbc	223	#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 /
AnnaBridge	171:3a7713b1edbc	224	#endif /SYSCFG_CFGR1_I2C_FMP_I2C1/
AnnaBridge	171:3a7713b1edbc	225	#if defined(SYSCFG_CFGR1_I2C_FMP_I2C2)
AnnaBridge	171:3a7713b1edbc	226	#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2 /!< Enable I2C2 Fast mode plus /
AnnaBridge	171:3a7713b1edbc	227	#endif /SYSCFG_CFGR1_I2C_FMP_I2C2/
AnnaBridge	171:3a7713b1edbc	228	#if defined(SYSCFG_CFGR1_I2C_FMP_PA9)
AnnaBridge	171:3a7713b1edbc	229	#define LL_SYSCFG_I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /!< Enable Fast Mode Plus on PA9 /
AnnaBridge	171:3a7713b1edbc	230	#endif /SYSCFG_CFGR1_I2C_FMP_PA9/
AnnaBridge	171:3a7713b1edbc	231	#if defined(SYSCFG_CFGR1_I2C_FMP_PA10)
AnnaBridge	171:3a7713b1edbc	232	#define LL_SYSCFG_I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /!< Enable Fast Mode Plus on PA10 /
AnnaBridge	171:3a7713b1edbc	233	#endif /SYSCFG_CFGR1_I2C_FMP_PA10/
AnnaBridge	171:3a7713b1edbc	234	/**
AnnaBridge	171:3a7713b1edbc	235	* @}
AnnaBridge	171:3a7713b1edbc	236	*/
AnnaBridge	171:3a7713b1edbc	237
AnnaBridge	171:3a7713b1edbc	238	/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
AnnaBridge	171:3a7713b1edbc	239	* @{
AnnaBridge	171:3a7713b1edbc	240	*/
AnnaBridge	171:3a7713b1edbc	241	#define LL_SYSCFG_EXTI_PORTA (uint32_t)0U /!< EXTI PORT A /
AnnaBridge	171:3a7713b1edbc	242	#define LL_SYSCFG_EXTI_PORTB (uint32_t)1U /!< EXTI PORT B /
AnnaBridge	171:3a7713b1edbc	243	#define LL_SYSCFG_EXTI_PORTC (uint32_t)2U /!< EXTI PORT C /
AnnaBridge	171:3a7713b1edbc	244	#if defined(GPIOD_BASE)
AnnaBridge	171:3a7713b1edbc	245	#define LL_SYSCFG_EXTI_PORTD (uint32_t)3U /!< EXTI PORT D /
AnnaBridge	171:3a7713b1edbc	246	#endif /GPIOD_BASE/
AnnaBridge	171:3a7713b1edbc	247	#if defined(GPIOE_BASE)
AnnaBridge	171:3a7713b1edbc	248	#define LL_SYSCFG_EXTI_PORTE (uint32_t)4U /!< EXTI PORT E /
AnnaBridge	171:3a7713b1edbc	249	#endif /GPIOE_BASE/
AnnaBridge	171:3a7713b1edbc	250	#define LL_SYSCFG_EXTI_PORTF (uint32_t)5U /!< EXTI PORT F /
AnnaBridge	171:3a7713b1edbc	251	/**
AnnaBridge	171:3a7713b1edbc	252	* @}
AnnaBridge	171:3a7713b1edbc	253	*/
AnnaBridge	171:3a7713b1edbc	254
AnnaBridge	171:3a7713b1edbc	255	/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
AnnaBridge	171:3a7713b1edbc	256	* @{
AnnaBridge	171:3a7713b1edbc	257	*/
AnnaBridge	171:3a7713b1edbc	258	#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0U << 16U \| 0U) /!< EXTI_POSITION_0 \| EXTICR[0] /
AnnaBridge	171:3a7713b1edbc	259	#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(4U << 16U \| 0U) /!< EXTI_POSITION_4 \| EXTICR[0] /
AnnaBridge	171:3a7713b1edbc	260	#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(8U << 16U \| 0U) /!< EXTI_POSITION_8 \| EXTICR[0] /
AnnaBridge	171:3a7713b1edbc	261	#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(12U << 16U \| 0U) /!< EXTI_POSITION_12 \| EXTICR[0] /
AnnaBridge	171:3a7713b1edbc	262	#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0U << 16U \| 1U) /!< EXTI_POSITION_0 \| EXTICR[1] /
AnnaBridge	171:3a7713b1edbc	263	#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(4U << 16U \| 1U) /!< EXTI_POSITION_4 \| EXTICR[1] /
AnnaBridge	171:3a7713b1edbc	264	#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(8U << 16U \| 1U) /!< EXTI_POSITION_8 \| EXTICR[1] /
AnnaBridge	171:3a7713b1edbc	265	#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(12U << 16U \| 1U) /!< EXTI_POSITION_12 \| EXTICR[1] /
AnnaBridge	171:3a7713b1edbc	266	#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0U << 16U \| 2U) /!< EXTI_POSITION_0 \| EXTICR[2] /
AnnaBridge	171:3a7713b1edbc	267	#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(4U << 16U \| 2U) /!< EXTI_POSITION_4 \| EXTICR[2] /
AnnaBridge	171:3a7713b1edbc	268	#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(8U << 16U \| 2U) /!< EXTI_POSITION_8 \| EXTICR[2] /
AnnaBridge	171:3a7713b1edbc	269	#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(12U << 16U \| 2U) /!< EXTI_POSITION_12 \| EXTICR[2] /
AnnaBridge	171:3a7713b1edbc	270	#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0U << 16U \| 3U) /!< EXTI_POSITION_0 \| EXTICR[3] /
AnnaBridge	171:3a7713b1edbc	271	#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(4U << 16U \| 3U) /!< EXTI_POSITION_4 \| EXTICR[3] /
AnnaBridge	171:3a7713b1edbc	272	#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(8U << 16U \| 3U) /!< EXTI_POSITION_8 \| EXTICR[3] /
AnnaBridge	171:3a7713b1edbc	273	#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(12U << 16U \| 3U) /!< EXTI_POSITION_12 \| EXTICR[3] /
AnnaBridge	171:3a7713b1edbc	274	/**
AnnaBridge	171:3a7713b1edbc	275	* @}
AnnaBridge	171:3a7713b1edbc	276	*/
AnnaBridge	171:3a7713b1edbc	277
AnnaBridge	171:3a7713b1edbc	278	/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
AnnaBridge	171:3a7713b1edbc	279	* @{
AnnaBridge	171:3a7713b1edbc	280	*/
AnnaBridge	171:3a7713b1edbc	281	#if defined(SYSCFG_CFGR2_PVD_LOCK)
AnnaBridge	171:3a7713b1edbc	282	#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection
AnnaBridge	171:3a7713b1edbc	283	with TIM1/15/16U/17 Break Input and also
AnnaBridge	171:3a7713b1edbc	284	the PVDE and PLS bits of the Power Control Interface */
AnnaBridge	171:3a7713b1edbc	285	#endif /SYSCFG_CFGR2_PVD_LOCK/
AnnaBridge	171:3a7713b1edbc	286	#define LL_SYSCFG_TIMBREAK_SRAM_PARITY SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Enables and locks the SRAM_PARITY error signal
AnnaBridge	171:3a7713b1edbc	287	with Break Input of TIM1/15/16/17 */
AnnaBridge	171:3a7713b1edbc	288	#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP (Hardfault) output of
AnnaBridge	171:3a7713b1edbc	289	CortexM0 with Break Input of TIM1/15/16/17 */
AnnaBridge	171:3a7713b1edbc	290	/**
AnnaBridge	171:3a7713b1edbc	291	* @}
AnnaBridge	171:3a7713b1edbc	292	*/
AnnaBridge	171:3a7713b1edbc	293
AnnaBridge	171:3a7713b1edbc	294	/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
AnnaBridge	171:3a7713b1edbc	295	* @{
AnnaBridge	171:3a7713b1edbc	296	*/
AnnaBridge	171:3a7713b1edbc	297	#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
AnnaBridge	171:3a7713b1edbc	298	#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /!< TIM2 counter stopped when core is halted /
AnnaBridge	171:3a7713b1edbc	299	#endif /DBGMCU_APB1_FZ_DBG_TIM2_STOP/
AnnaBridge	171:3a7713b1edbc	300	#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /!< TIM3 counter stopped when core is halted /
AnnaBridge	171:3a7713b1edbc	301	#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
AnnaBridge	171:3a7713b1edbc	302	#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /!< TIM6 counter stopped when core is halted /
AnnaBridge	171:3a7713b1edbc	303	#endif /DBGMCU_APB1_FZ_DBG_TIM6_STOP/
AnnaBridge	171:3a7713b1edbc	304	#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
AnnaBridge	171:3a7713b1edbc	305	#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /!< TIM7 counter stopped when core is halted /
AnnaBridge	171:3a7713b1edbc	306	#endif /DBGMCU_APB1_FZ_DBG_TIM7_STOP/
AnnaBridge	171:3a7713b1edbc	307	#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /!< TIM14 counter stopped when core is halted /
AnnaBridge	171:3a7713b1edbc	308	#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /!< RTC Calendar frozen when core is halted /
AnnaBridge	171:3a7713b1edbc	309	#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /!< Debug Window Watchdog stopped when Core is halted /
AnnaBridge	171:3a7713b1edbc	310	#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /!< Debug Independent Watchdog stopped when Core is halted /
AnnaBridge	171:3a7713b1edbc	311	#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /!< I2C1 SMBUS timeout mode stopped when Core is halted /
AnnaBridge	171:3a7713b1edbc	312	#if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
AnnaBridge	171:3a7713b1edbc	313	#define LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP /!< CAN debug stopped when Core is halted /
AnnaBridge	171:3a7713b1edbc	314	#endif /DBGMCU_APB1_FZ_DBG_CAN_STOP/
AnnaBridge	171:3a7713b1edbc	315	/**
AnnaBridge	171:3a7713b1edbc	316	* @}
AnnaBridge	171:3a7713b1edbc	317	*/
AnnaBridge	171:3a7713b1edbc	318
AnnaBridge	171:3a7713b1edbc	319	/** @defgroup SYSTEM_LL_EC_APB1 GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
AnnaBridge	171:3a7713b1edbc	320	* @{
AnnaBridge	171:3a7713b1edbc	321	*/
AnnaBridge	171:3a7713b1edbc	322	#define LL_DBGMCU_APB1_GRP2_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /!< TIM1 counter stopped when core is halted /
AnnaBridge	171:3a7713b1edbc	323	#if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
AnnaBridge	171:3a7713b1edbc	324	#define LL_DBGMCU_APB1_GRP2_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP /!< TIM15 counter stopped when core is halted /
AnnaBridge	171:3a7713b1edbc	325	#endif /DBGMCU_APB2_FZ_DBG_TIM15_STOP/
AnnaBridge	171:3a7713b1edbc	326	#define LL_DBGMCU_APB1_GRP2_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP /!< TIM16 counter stopped when core is halted /
AnnaBridge	171:3a7713b1edbc	327	#define LL_DBGMCU_APB1_GRP2_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP /!< TIM17 counter stopped when core is halted /
AnnaBridge	171:3a7713b1edbc	328	/**
AnnaBridge	171:3a7713b1edbc	329	* @}
AnnaBridge	171:3a7713b1edbc	330	*/
AnnaBridge	171:3a7713b1edbc	331
AnnaBridge	171:3a7713b1edbc	332	/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
AnnaBridge	171:3a7713b1edbc	333	* @{
AnnaBridge	171:3a7713b1edbc	334	*/
AnnaBridge	171:3a7713b1edbc	335	#define LL_FLASH_LATENCY_0 0x00000000U /!< FLASH Zero Latency cycle /
AnnaBridge	171:3a7713b1edbc	336	#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY /!< FLASH One Latency cycle /
AnnaBridge	171:3a7713b1edbc	337	/**
AnnaBridge	171:3a7713b1edbc	338	* @}
AnnaBridge	171:3a7713b1edbc	339	*/
AnnaBridge	171:3a7713b1edbc	340
AnnaBridge	171:3a7713b1edbc	341	/**
AnnaBridge	171:3a7713b1edbc	342	* @}
AnnaBridge	171:3a7713b1edbc	343	*/
AnnaBridge	171:3a7713b1edbc	344
AnnaBridge	171:3a7713b1edbc	345	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	346
AnnaBridge	171:3a7713b1edbc	347	/* Exported functions --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	348	/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
AnnaBridge	171:3a7713b1edbc	349	* @{
AnnaBridge	171:3a7713b1edbc	350	*/
AnnaBridge	171:3a7713b1edbc	351
AnnaBridge	171:3a7713b1edbc	352	/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
AnnaBridge	171:3a7713b1edbc	353	* @{
AnnaBridge	171:3a7713b1edbc	354	*/
AnnaBridge	171:3a7713b1edbc	355
AnnaBridge	171:3a7713b1edbc	356	/**
AnnaBridge	171:3a7713b1edbc	357	* @brief Set memory mapping at address 0x00000000
AnnaBridge	171:3a7713b1edbc	358	* @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_SetRemapMemory
AnnaBridge	171:3a7713b1edbc	359	* @param Memory This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	360	* @arg @ref LL_SYSCFG_REMAP_FLASH
AnnaBridge	171:3a7713b1edbc	361	* @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
AnnaBridge	171:3a7713b1edbc	362	* @arg @ref LL_SYSCFG_REMAP_SRAM
AnnaBridge	171:3a7713b1edbc	363	* @retval None
AnnaBridge	171:3a7713b1edbc	364	*/
AnnaBridge	171:3a7713b1edbc	365	__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
AnnaBridge	171:3a7713b1edbc	366	{
AnnaBridge	171:3a7713b1edbc	367	MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory);
AnnaBridge	171:3a7713b1edbc	368	}
AnnaBridge	171:3a7713b1edbc	369
AnnaBridge	171:3a7713b1edbc	370	/**
AnnaBridge	171:3a7713b1edbc	371	* @brief Get memory mapping at address 0x00000000
AnnaBridge	171:3a7713b1edbc	372	* @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_GetRemapMemory
AnnaBridge	171:3a7713b1edbc	373	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	374	* @arg @ref LL_SYSCFG_REMAP_FLASH
AnnaBridge	171:3a7713b1edbc	375	* @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
AnnaBridge	171:3a7713b1edbc	376	* @arg @ref LL_SYSCFG_REMAP_SRAM
AnnaBridge	171:3a7713b1edbc	377	*/
AnnaBridge	171:3a7713b1edbc	378	__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
AnnaBridge	171:3a7713b1edbc	379	{
AnnaBridge	171:3a7713b1edbc	380	return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE));
AnnaBridge	171:3a7713b1edbc	381	}
AnnaBridge	171:3a7713b1edbc	382
AnnaBridge	171:3a7713b1edbc	383	#if defined(SYSCFG_CFGR1_IR_MOD)
AnnaBridge	171:3a7713b1edbc	384	/**
AnnaBridge	171:3a7713b1edbc	385	* @brief Set IR Modulation Envelope signal source.
AnnaBridge	171:3a7713b1edbc	386	* @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_SetIRModEnvelopeSignal
AnnaBridge	171:3a7713b1edbc	387	* @param Source This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	388	* @arg @ref LL_SYSCFG_IR_MOD_TIM16
AnnaBridge	171:3a7713b1edbc	389	* @arg @ref LL_SYSCFG_IR_MOD_USART1
AnnaBridge	171:3a7713b1edbc	390	* @arg @ref LL_SYSCFG_IR_MOD_USART4
AnnaBridge	171:3a7713b1edbc	391	* @retval None
AnnaBridge	171:3a7713b1edbc	392	*/
AnnaBridge	171:3a7713b1edbc	393	__STATIC_INLINE void LL_SYSCFG_SetIRModEnvelopeSignal(uint32_t Source)
AnnaBridge	171:3a7713b1edbc	394	{
AnnaBridge	171:3a7713b1edbc	395	MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD, Source);
AnnaBridge	171:3a7713b1edbc	396	}
AnnaBridge	171:3a7713b1edbc	397
AnnaBridge	171:3a7713b1edbc	398	/**
AnnaBridge	171:3a7713b1edbc	399	* @brief Get IR Modulation Envelope signal source.
AnnaBridge	171:3a7713b1edbc	400	* @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_GetIRModEnvelopeSignal
AnnaBridge	171:3a7713b1edbc	401	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	402	* @arg @ref LL_SYSCFG_IR_MOD_TIM16
AnnaBridge	171:3a7713b1edbc	403	* @arg @ref LL_SYSCFG_IR_MOD_USART1
AnnaBridge	171:3a7713b1edbc	404	* @arg @ref LL_SYSCFG_IR_MOD_USART4
AnnaBridge	171:3a7713b1edbc	405	*/
AnnaBridge	171:3a7713b1edbc	406	__STATIC_INLINE uint32_t LL_SYSCFG_GetIRModEnvelopeSignal(void)
AnnaBridge	171:3a7713b1edbc	407	{
AnnaBridge	171:3a7713b1edbc	408	return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD));
AnnaBridge	171:3a7713b1edbc	409	}
AnnaBridge	171:3a7713b1edbc	410	#endif /* SYSCFG_CFGR1_IR_MOD */
AnnaBridge	171:3a7713b1edbc	411
AnnaBridge	171:3a7713b1edbc	412	#if defined(SYSCFG_CFGR1_USART1TX_DMA_RMP) \|\| defined(SYSCFG_CFGR1_USART1RX_DMA_RMP) \|\| defined(SYSCFG_CFGR1_USART2_DMA_RMP) \|\| defined(SYSCFG_CFGR1_USART3_DMA_RMP)
AnnaBridge	171:3a7713b1edbc	413	/**
AnnaBridge	171:3a7713b1edbc	414	* @brief Set DMA request remapping bits for USART
AnnaBridge	171:3a7713b1edbc	415	* @rmtoll SYSCFG_CFGR1 USART1TX_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n
AnnaBridge	171:3a7713b1edbc	416	* SYSCFG_CFGR1 USART1RX_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n
AnnaBridge	171:3a7713b1edbc	417	* SYSCFG_CFGR1 USART2_DMA_RMP LL_SYSCFG_SetRemapDMA_USART\n
AnnaBridge	171:3a7713b1edbc	418	* SYSCFG_CFGR1 USART3_DMA_RMP LL_SYSCFG_SetRemapDMA_USART
AnnaBridge	171:3a7713b1edbc	419	* @param Remap This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	420	* @arg @ref LL_SYSCFG_USART1TX_RMP_DMA1CH2 (*)
AnnaBridge	171:3a7713b1edbc	421	* @arg @ref LL_SYSCFG_USART1TX_RMP_DMA1CH4 (*)
AnnaBridge	171:3a7713b1edbc	422	* @arg @ref LL_SYSCFG_USART1RX_RMP_DMA1CH3 (*)
AnnaBridge	171:3a7713b1edbc	423	* @arg @ref LL_SYSCFG_USART1RX_RMP_DMA1CH5 (*)
AnnaBridge	171:3a7713b1edbc	424	* @arg @ref LL_SYSCFG_USART2_RMP_DMA1CH54 (*)
AnnaBridge	171:3a7713b1edbc	425	* @arg @ref LL_SYSCFG_USART2_RMP_DMA1CH67 (*)
AnnaBridge	171:3a7713b1edbc	426	* @arg @ref LL_SYSCFG_USART3_RMP_DMA1CH67 (*)
AnnaBridge	171:3a7713b1edbc	427	* @arg @ref LL_SYSCFG_USART3_RMP_DMA1CH32 (*)
AnnaBridge	171:3a7713b1edbc	428	*
AnnaBridge	171:3a7713b1edbc	429	* (*) value not defined in all devices.
AnnaBridge	171:3a7713b1edbc	430	* @retval None
AnnaBridge	171:3a7713b1edbc	431	*/
AnnaBridge	171:3a7713b1edbc	432	__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_USART(uint32_t Remap)
AnnaBridge	171:3a7713b1edbc	433	{
AnnaBridge	171:3a7713b1edbc	434	MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF00FFU) << 8U, (Remap & 0xFF00FF00U));
AnnaBridge	171:3a7713b1edbc	435	}
AnnaBridge	171:3a7713b1edbc	436	#endif /* SYSCFG_CFGR1_USART1TX_DMA_RMP \|\| SYSCFG_CFGR1_USART1RX_DMA_RMP \|\| SYSCFG_CFGR1_USART2_DMA_RMP \|\| SYSCFG_CFGR1_USART3_DMA_RMP */
AnnaBridge	171:3a7713b1edbc	437
AnnaBridge	171:3a7713b1edbc	438	#if defined(SYSCFG_CFGR1_SPI2_DMA_RMP)
AnnaBridge	171:3a7713b1edbc	439	/**
AnnaBridge	171:3a7713b1edbc	440	* @brief Set DMA request remapping bits for SPI
AnnaBridge	171:3a7713b1edbc	441	* @rmtoll SYSCFG_CFGR1 SPI2_DMA_RMP LL_SYSCFG_SetRemapDMA_SPI
AnnaBridge	171:3a7713b1edbc	442	* @param Remap This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	443	* @arg @ref LL_SYSCFG_SPI2_RMP_DMA1_CH45
AnnaBridge	171:3a7713b1edbc	444	* @arg @ref LL_SYSCFG_SPI2_RMP_DMA1_CH67
AnnaBridge	171:3a7713b1edbc	445	* @retval None
AnnaBridge	171:3a7713b1edbc	446	*/
AnnaBridge	171:3a7713b1edbc	447	__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_SPI(uint32_t Remap)
AnnaBridge	171:3a7713b1edbc	448	{
AnnaBridge	171:3a7713b1edbc	449	MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_SPI2_DMA_RMP, Remap);
AnnaBridge	171:3a7713b1edbc	450	}
AnnaBridge	171:3a7713b1edbc	451	#endif /* SYSCFG_CFGR1_SPI2_DMA_RMP */
AnnaBridge	171:3a7713b1edbc	452
AnnaBridge	171:3a7713b1edbc	453	#if defined(SYSCFG_CFGR1_I2C1_DMA_RMP)
AnnaBridge	171:3a7713b1edbc	454	/**
AnnaBridge	171:3a7713b1edbc	455	* @brief Set DMA request remapping bits for I2C
AnnaBridge	171:3a7713b1edbc	456	* @rmtoll SYSCFG_CFGR1 I2C1_DMA_RMP LL_SYSCFG_SetRemapDMA_I2C
AnnaBridge	171:3a7713b1edbc	457	* @param Remap This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	458	* @arg @ref LL_SYSCFG_I2C1_RMP_DMA1_CH32
AnnaBridge	171:3a7713b1edbc	459	* @arg @ref LL_SYSCFG_I2C1_RMP_DMA1_CH76
AnnaBridge	171:3a7713b1edbc	460	* @retval None
AnnaBridge	171:3a7713b1edbc	461	*/
AnnaBridge	171:3a7713b1edbc	462	__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_I2C(uint32_t Remap)
AnnaBridge	171:3a7713b1edbc	463	{
AnnaBridge	171:3a7713b1edbc	464	MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_I2C1_DMA_RMP, Remap);
AnnaBridge	171:3a7713b1edbc	465	}
AnnaBridge	171:3a7713b1edbc	466	#endif /* SYSCFG_CFGR1_I2C1_DMA_RMP */
AnnaBridge	171:3a7713b1edbc	467
AnnaBridge	171:3a7713b1edbc	468	#if defined(SYSCFG_CFGR1_ADC_DMA_RMP)
AnnaBridge	171:3a7713b1edbc	469	/**
AnnaBridge	171:3a7713b1edbc	470	* @brief Set DMA request remapping bits for ADC
AnnaBridge	171:3a7713b1edbc	471	* @rmtoll SYSCFG_CFGR1 ADC_DMA_RMP LL_SYSCFG_SetRemapDMA_ADC
AnnaBridge	171:3a7713b1edbc	472	* @param Remap This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	473	* @arg @ref LL_SYSCFG_ADC1_RMP_DMA1_CH1
AnnaBridge	171:3a7713b1edbc	474	* @arg @ref LL_SYSCFG_ADC1_RMP_DMA1_CH2
AnnaBridge	171:3a7713b1edbc	475	* @retval None
AnnaBridge	171:3a7713b1edbc	476	*/
AnnaBridge	171:3a7713b1edbc	477	__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_ADC(uint32_t Remap)
AnnaBridge	171:3a7713b1edbc	478	{
AnnaBridge	171:3a7713b1edbc	479	MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_ADC_DMA_RMP, Remap);
AnnaBridge	171:3a7713b1edbc	480	}
AnnaBridge	171:3a7713b1edbc	481	#endif /* SYSCFG_CFGR1_ADC_DMA_RMP */
AnnaBridge	171:3a7713b1edbc	482
AnnaBridge	171:3a7713b1edbc	483	#if defined(SYSCFG_CFGR1_TIM16_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM17_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM1_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM2_DMA_RMP) \|\| defined(SYSCFG_CFGR1_TIM3_DMA_RMP)
AnnaBridge	171:3a7713b1edbc	484	/**
AnnaBridge	171:3a7713b1edbc	485	* @brief Set DMA request remapping bits for TIM
AnnaBridge	171:3a7713b1edbc	486	* @rmtoll SYSCFG_CFGR1 TIM16_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
AnnaBridge	171:3a7713b1edbc	487	* SYSCFG_CFGR1 TIM17_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
AnnaBridge	171:3a7713b1edbc	488	* SYSCFG_CFGR1 TIM16_DMA_RMP2 LL_SYSCFG_SetRemapDMA_TIM\n
AnnaBridge	171:3a7713b1edbc	489	* SYSCFG_CFGR1 TIM17_DMA_RMP2 LL_SYSCFG_SetRemapDMA_TIM\n
AnnaBridge	171:3a7713b1edbc	490	* SYSCFG_CFGR1 TIM1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
AnnaBridge	171:3a7713b1edbc	491	* SYSCFG_CFGR1 TIM2_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
AnnaBridge	171:3a7713b1edbc	492	* SYSCFG_CFGR1 TIM3_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM
AnnaBridge	171:3a7713b1edbc	493	* @param Remap This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	494	* @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH3 (*)
AnnaBridge	171:3a7713b1edbc	495	* @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH4 (*)
AnnaBridge	171:3a7713b1edbc	496	* @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH6 (*)
AnnaBridge	171:3a7713b1edbc	497	* @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH1 (*)
AnnaBridge	171:3a7713b1edbc	498	* @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH2 (*)
AnnaBridge	171:3a7713b1edbc	499	* @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH7 (*)
AnnaBridge	171:3a7713b1edbc	500	* @arg @ref LL_SYSCFG_TIM1_RMP_DMA1_CH234 (*)
AnnaBridge	171:3a7713b1edbc	501	* @arg @ref LL_SYSCFG_TIM1_RMP_DMA1_CH6 (*)
AnnaBridge	171:3a7713b1edbc	502	* @arg @ref LL_SYSCFG_TIM2_RMP_DMA1_CH34 (*)
AnnaBridge	171:3a7713b1edbc	503	* @arg @ref LL_SYSCFG_TIM2_RMP_DMA1_CH7 (*)
AnnaBridge	171:3a7713b1edbc	504	* @arg @ref LL_SYSCFG_TIM3_RMP_DMA1_CH4 (*)
AnnaBridge	171:3a7713b1edbc	505	* @arg @ref LL_SYSCFG_TIM3_RMP_DMA1_CH6 (*)
AnnaBridge	171:3a7713b1edbc	506	*
AnnaBridge	171:3a7713b1edbc	507	* (*) value not defined in all devices.
AnnaBridge	171:3a7713b1edbc	508	* @retval None
AnnaBridge	171:3a7713b1edbc	509	*/
AnnaBridge	171:3a7713b1edbc	510	__STATIC_INLINE void LL_SYSCFG_SetRemapDMA_TIM(uint32_t Remap)
AnnaBridge	171:3a7713b1edbc	511	{
AnnaBridge	171:3a7713b1edbc	512	MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF00FFU) << 8U, (Remap & 0xFF00FF00U));
AnnaBridge	171:3a7713b1edbc	513	}
AnnaBridge	171:3a7713b1edbc	514	#endif /* SYSCFG_CFGR1_TIM16_DMA_RMP \|\| SYSCFG_CFGR1_TIM17_DMA_RMP \|\| SYSCFG_CFGR1_TIM1_DMA_RMP \|\| SYSCFG_CFGR1_TIM2_DMA_RMP \|\| SYSCFG_CFGR1_TIM3_DMA_RMP */
AnnaBridge	171:3a7713b1edbc	515
AnnaBridge	171:3a7713b1edbc	516	#if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
AnnaBridge	171:3a7713b1edbc	517	/**
AnnaBridge	171:3a7713b1edbc	518	* @brief Enable PIN pair PA11/12 mapped instead of PA9/10 (control the mapping of either
AnnaBridge	171:3a7713b1edbc	519	* PA9/10 or PA11/12 pin pair on small pin-count packages)
AnnaBridge	171:3a7713b1edbc	520	* @rmtoll SYSCFG_CFGR1 PA11_PA12_RMP LL_SYSCFG_EnablePinRemap
AnnaBridge	171:3a7713b1edbc	521	* @retval None
AnnaBridge	171:3a7713b1edbc	522	*/
AnnaBridge	171:3a7713b1edbc	523	__STATIC_INLINE void LL_SYSCFG_EnablePinRemap(void)
AnnaBridge	171:3a7713b1edbc	524	{
AnnaBridge	171:3a7713b1edbc	525	SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_PA11_PA12_RMP);
AnnaBridge	171:3a7713b1edbc	526	}
AnnaBridge	171:3a7713b1edbc	527
AnnaBridge	171:3a7713b1edbc	528	/**
AnnaBridge	171:3a7713b1edbc	529	* @brief Disable PIN pair PA11/12 mapped instead of PA9/10 (control the mapping of either
AnnaBridge	171:3a7713b1edbc	530	* PA9/10 or PA11/12 pin pair on small pin-count packages)
AnnaBridge	171:3a7713b1edbc	531	* @rmtoll SYSCFG_CFGR1 PA11_PA12_RMP LL_SYSCFG_DisablePinRemap
AnnaBridge	171:3a7713b1edbc	532	* @retval None
AnnaBridge	171:3a7713b1edbc	533	*/
AnnaBridge	171:3a7713b1edbc	534	__STATIC_INLINE void LL_SYSCFG_DisablePinRemap(void)
AnnaBridge	171:3a7713b1edbc	535	{
AnnaBridge	171:3a7713b1edbc	536	CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_PA11_PA12_RMP);
AnnaBridge	171:3a7713b1edbc	537	}
AnnaBridge	171:3a7713b1edbc	538	#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
AnnaBridge	171:3a7713b1edbc	539
AnnaBridge	171:3a7713b1edbc	540	/**
AnnaBridge	171:3a7713b1edbc	541	* @brief Enable the I2C fast mode plus driving capability.
AnnaBridge	171:3a7713b1edbc	542	* @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_EnableFastModePlus\n
AnnaBridge	171:3a7713b1edbc	543	* SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_EnableFastModePlus\n
AnnaBridge	171:3a7713b1edbc	544	* SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_EnableFastModePlus\n
AnnaBridge	171:3a7713b1edbc	545	* SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_EnableFastModePlus\n
AnnaBridge	171:3a7713b1edbc	546	* SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_EnableFastModePlus\n
AnnaBridge	171:3a7713b1edbc	547	* SYSCFG_CFGR1 I2C_FMP_I2C2 LL_SYSCFG_EnableFastModePlus\n
AnnaBridge	171:3a7713b1edbc	548	* SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_EnableFastModePlus\n
AnnaBridge	171:3a7713b1edbc	549	* SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_EnableFastModePlus
AnnaBridge	171:3a7713b1edbc	550	* @param ConfigFastModePlus This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	551	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
AnnaBridge	171:3a7713b1edbc	552	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
AnnaBridge	171:3a7713b1edbc	553	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
AnnaBridge	171:3a7713b1edbc	554	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
AnnaBridge	171:3a7713b1edbc	555	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 (*)
AnnaBridge	171:3a7713b1edbc	556	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
AnnaBridge	171:3a7713b1edbc	557	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9 (*)
AnnaBridge	171:3a7713b1edbc	558	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10 (*)
AnnaBridge	171:3a7713b1edbc	559	*
AnnaBridge	171:3a7713b1edbc	560	* (*) value not defined in all devices
AnnaBridge	171:3a7713b1edbc	561	* @retval None
AnnaBridge	171:3a7713b1edbc	562	*/
AnnaBridge	171:3a7713b1edbc	563	__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
AnnaBridge	171:3a7713b1edbc	564	{
AnnaBridge	171:3a7713b1edbc	565	SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
AnnaBridge	171:3a7713b1edbc	566	}
AnnaBridge	171:3a7713b1edbc	567
AnnaBridge	171:3a7713b1edbc	568	/**
AnnaBridge	171:3a7713b1edbc	569	* @brief Disable the I2C fast mode plus driving capability.
AnnaBridge	171:3a7713b1edbc	570	* @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_DisableFastModePlus\n
AnnaBridge	171:3a7713b1edbc	571	* SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_DisableFastModePlus\n
AnnaBridge	171:3a7713b1edbc	572	* SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_DisableFastModePlus\n
AnnaBridge	171:3a7713b1edbc	573	* SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_DisableFastModePlus\n
AnnaBridge	171:3a7713b1edbc	574	* SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_DisableFastModePlus\n
AnnaBridge	171:3a7713b1edbc	575	* SYSCFG_CFGR1 I2C_FMP_I2C2 LL_SYSCFG_DisableFastModePlus\n
AnnaBridge	171:3a7713b1edbc	576	* SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_DisableFastModePlus\n
AnnaBridge	171:3a7713b1edbc	577	* SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_DisableFastModePlus
AnnaBridge	171:3a7713b1edbc	578	* @param ConfigFastModePlus This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	579	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
AnnaBridge	171:3a7713b1edbc	580	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
AnnaBridge	171:3a7713b1edbc	581	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
AnnaBridge	171:3a7713b1edbc	582	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
AnnaBridge	171:3a7713b1edbc	583	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 (*)
AnnaBridge	171:3a7713b1edbc	584	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
AnnaBridge	171:3a7713b1edbc	585	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9 (*)
AnnaBridge	171:3a7713b1edbc	586	* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10 (*)
AnnaBridge	171:3a7713b1edbc	587	*
AnnaBridge	171:3a7713b1edbc	588	* (*) value not defined in all devices
AnnaBridge	171:3a7713b1edbc	589	* @retval None
AnnaBridge	171:3a7713b1edbc	590	*/
AnnaBridge	171:3a7713b1edbc	591	__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
AnnaBridge	171:3a7713b1edbc	592	{
AnnaBridge	171:3a7713b1edbc	593	CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
AnnaBridge	171:3a7713b1edbc	594	}
AnnaBridge	171:3a7713b1edbc	595
AnnaBridge	171:3a7713b1edbc	596	/**
AnnaBridge	171:3a7713b1edbc	597	* @brief Configure source input for the EXTI external interrupt.
AnnaBridge	171:3a7713b1edbc	598	* @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	599	* SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	600	* SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	601	* SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	602	* SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	603	* SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	604	* SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	605	* SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	606	* SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	607	* SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	608	* SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	609	* SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	610	* SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	611	* SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	612	* SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	613	* SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource
AnnaBridge	171:3a7713b1edbc	614	* @param Port This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	615	* @arg @ref LL_SYSCFG_EXTI_PORTA
AnnaBridge	171:3a7713b1edbc	616	* @arg @ref LL_SYSCFG_EXTI_PORTB
AnnaBridge	171:3a7713b1edbc	617	* @arg @ref LL_SYSCFG_EXTI_PORTC
AnnaBridge	171:3a7713b1edbc	618	* @arg @ref LL_SYSCFG_EXTI_PORTD (*)
AnnaBridge	171:3a7713b1edbc	619	* @arg @ref LL_SYSCFG_EXTI_PORTE (*)
AnnaBridge	171:3a7713b1edbc	620	* @arg @ref LL_SYSCFG_EXTI_PORTF
AnnaBridge	171:3a7713b1edbc	621	*
AnnaBridge	171:3a7713b1edbc	622	* (*) value not defined in all devices
AnnaBridge	171:3a7713b1edbc	623	* @param Line This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	624	* @arg @ref LL_SYSCFG_EXTI_LINE0
AnnaBridge	171:3a7713b1edbc	625	* @arg @ref LL_SYSCFG_EXTI_LINE1
AnnaBridge	171:3a7713b1edbc	626	* @arg @ref LL_SYSCFG_EXTI_LINE2
AnnaBridge	171:3a7713b1edbc	627	* @arg @ref LL_SYSCFG_EXTI_LINE3
AnnaBridge	171:3a7713b1edbc	628	* @arg @ref LL_SYSCFG_EXTI_LINE4
AnnaBridge	171:3a7713b1edbc	629	* @arg @ref LL_SYSCFG_EXTI_LINE5
AnnaBridge	171:3a7713b1edbc	630	* @arg @ref LL_SYSCFG_EXTI_LINE6
AnnaBridge	171:3a7713b1edbc	631	* @arg @ref LL_SYSCFG_EXTI_LINE7
AnnaBridge	171:3a7713b1edbc	632	* @arg @ref LL_SYSCFG_EXTI_LINE8
AnnaBridge	171:3a7713b1edbc	633	* @arg @ref LL_SYSCFG_EXTI_LINE9
AnnaBridge	171:3a7713b1edbc	634	* @arg @ref LL_SYSCFG_EXTI_LINE10
AnnaBridge	171:3a7713b1edbc	635	* @arg @ref LL_SYSCFG_EXTI_LINE11
AnnaBridge	171:3a7713b1edbc	636	* @arg @ref LL_SYSCFG_EXTI_LINE12
AnnaBridge	171:3a7713b1edbc	637	* @arg @ref LL_SYSCFG_EXTI_LINE13
AnnaBridge	171:3a7713b1edbc	638	* @arg @ref LL_SYSCFG_EXTI_LINE14
AnnaBridge	171:3a7713b1edbc	639	* @arg @ref LL_SYSCFG_EXTI_LINE15
AnnaBridge	171:3a7713b1edbc	640	* @retval None
AnnaBridge	171:3a7713b1edbc	641	*/
AnnaBridge	171:3a7713b1edbc	642	__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
AnnaBridge	171:3a7713b1edbc	643	{
AnnaBridge	171:3a7713b1edbc	644	MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], SYSCFG_EXTICR1_EXTI0 << (Line >> 16), Port << (Line >> 16));
AnnaBridge	171:3a7713b1edbc	645	}
AnnaBridge	171:3a7713b1edbc	646
AnnaBridge	171:3a7713b1edbc	647	/**
AnnaBridge	171:3a7713b1edbc	648	* @brief Get the configured defined for specific EXTI Line
AnnaBridge	171:3a7713b1edbc	649	* @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	650	* SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	651	* SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	652	* SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	653	* SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	654	* SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	655	* SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	656	* SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	657	* SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	658	* SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	659	* SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	660	* SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	661	* SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	662	* SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	663	* SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n
AnnaBridge	171:3a7713b1edbc	664	* SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource
AnnaBridge	171:3a7713b1edbc	665	* @param Line This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	666	* @arg @ref LL_SYSCFG_EXTI_LINE0
AnnaBridge	171:3a7713b1edbc	667	* @arg @ref LL_SYSCFG_EXTI_LINE1
AnnaBridge	171:3a7713b1edbc	668	* @arg @ref LL_SYSCFG_EXTI_LINE2
AnnaBridge	171:3a7713b1edbc	669	* @arg @ref LL_SYSCFG_EXTI_LINE3
AnnaBridge	171:3a7713b1edbc	670	* @arg @ref LL_SYSCFG_EXTI_LINE4
AnnaBridge	171:3a7713b1edbc	671	* @arg @ref LL_SYSCFG_EXTI_LINE5
AnnaBridge	171:3a7713b1edbc	672	* @arg @ref LL_SYSCFG_EXTI_LINE6
AnnaBridge	171:3a7713b1edbc	673	* @arg @ref LL_SYSCFG_EXTI_LINE7
AnnaBridge	171:3a7713b1edbc	674	* @arg @ref LL_SYSCFG_EXTI_LINE8
AnnaBridge	171:3a7713b1edbc	675	* @arg @ref LL_SYSCFG_EXTI_LINE9
AnnaBridge	171:3a7713b1edbc	676	* @arg @ref LL_SYSCFG_EXTI_LINE10
AnnaBridge	171:3a7713b1edbc	677	* @arg @ref LL_SYSCFG_EXTI_LINE11
AnnaBridge	171:3a7713b1edbc	678	* @arg @ref LL_SYSCFG_EXTI_LINE12
AnnaBridge	171:3a7713b1edbc	679	* @arg @ref LL_SYSCFG_EXTI_LINE13
AnnaBridge	171:3a7713b1edbc	680	* @arg @ref LL_SYSCFG_EXTI_LINE14
AnnaBridge	171:3a7713b1edbc	681	* @arg @ref LL_SYSCFG_EXTI_LINE15
AnnaBridge	171:3a7713b1edbc	682	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	683	* @arg @ref LL_SYSCFG_EXTI_PORTA
AnnaBridge	171:3a7713b1edbc	684	* @arg @ref LL_SYSCFG_EXTI_PORTB
AnnaBridge	171:3a7713b1edbc	685	* @arg @ref LL_SYSCFG_EXTI_PORTC
AnnaBridge	171:3a7713b1edbc	686	* @arg @ref LL_SYSCFG_EXTI_PORTD (*)
AnnaBridge	171:3a7713b1edbc	687	* @arg @ref LL_SYSCFG_EXTI_PORTE (*)
AnnaBridge	171:3a7713b1edbc	688	* @arg @ref LL_SYSCFG_EXTI_PORTF
AnnaBridge	171:3a7713b1edbc	689	*
AnnaBridge	171:3a7713b1edbc	690	* (*) value not defined in all devices
AnnaBridge	171:3a7713b1edbc	691	*/
AnnaBridge	171:3a7713b1edbc	692	__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
AnnaBridge	171:3a7713b1edbc	693	{
AnnaBridge	171:3a7713b1edbc	694	return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (SYSCFG_EXTICR1_EXTI0 << (Line >> 16))) >> (Line >> 16));
AnnaBridge	171:3a7713b1edbc	695	}
AnnaBridge	171:3a7713b1edbc	696
AnnaBridge	171:3a7713b1edbc	697	#if defined(SYSCFG_ITLINE0_SR_EWDG)
AnnaBridge	171:3a7713b1edbc	698	/**
AnnaBridge	171:3a7713b1edbc	699	* @brief Check if Window watchdog interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	700	* @rmtoll SYSCFG_ITLINE0 SR_EWDG LL_SYSCFG_IsActiveFlag_WWDG
AnnaBridge	171:3a7713b1edbc	701	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	702	*/
AnnaBridge	171:3a7713b1edbc	703	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_WWDG(void)
AnnaBridge	171:3a7713b1edbc	704	{
AnnaBridge	171:3a7713b1edbc	705	return (READ_BIT(SYSCFG->IT_LINE_SR[0], SYSCFG_ITLINE0_SR_EWDG) == (SYSCFG_ITLINE0_SR_EWDG));
AnnaBridge	171:3a7713b1edbc	706	}
AnnaBridge	171:3a7713b1edbc	707	#endif /* SYSCFG_ITLINE0_SR_EWDG */
AnnaBridge	171:3a7713b1edbc	708
AnnaBridge	171:3a7713b1edbc	709	#if defined(SYSCFG_ITLINE1_SR_PVDOUT)
AnnaBridge	171:3a7713b1edbc	710	/**
AnnaBridge	171:3a7713b1edbc	711	* @brief Check if PVD supply monitoring interrupt occurred or not (EXTI line 16).
AnnaBridge	171:3a7713b1edbc	712	* @rmtoll SYSCFG_ITLINE1 SR_PVDOUT LL_SYSCFG_IsActiveFlag_PVDOUT
AnnaBridge	171:3a7713b1edbc	713	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	714	*/
AnnaBridge	171:3a7713b1edbc	715	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_PVDOUT(void)
AnnaBridge	171:3a7713b1edbc	716	{
AnnaBridge	171:3a7713b1edbc	717	return (READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_PVDOUT) == (SYSCFG_ITLINE1_SR_PVDOUT));
AnnaBridge	171:3a7713b1edbc	718	}
AnnaBridge	171:3a7713b1edbc	719	#endif /* SYSCFG_ITLINE1_SR_PVDOUT */
AnnaBridge	171:3a7713b1edbc	720
AnnaBridge	171:3a7713b1edbc	721	#if defined(SYSCFG_ITLINE1_SR_VDDIO2)
AnnaBridge	171:3a7713b1edbc	722	/**
AnnaBridge	171:3a7713b1edbc	723	* @brief Check if VDDIO2 supply monitoring interrupt occurred or not (EXTI line 31).
AnnaBridge	171:3a7713b1edbc	724	* @rmtoll SYSCFG_ITLINE1 SR_VDDIO2 LL_SYSCFG_IsActiveFlag_VDDIO2
AnnaBridge	171:3a7713b1edbc	725	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	726	*/
AnnaBridge	171:3a7713b1edbc	727	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VDDIO2(void)
AnnaBridge	171:3a7713b1edbc	728	{
AnnaBridge	171:3a7713b1edbc	729	return (READ_BIT(SYSCFG->IT_LINE_SR[1], SYSCFG_ITLINE1_SR_VDDIO2) == (SYSCFG_ITLINE1_SR_VDDIO2));
AnnaBridge	171:3a7713b1edbc	730	}
AnnaBridge	171:3a7713b1edbc	731	#endif /* SYSCFG_ITLINE1_SR_VDDIO2 */
AnnaBridge	171:3a7713b1edbc	732
AnnaBridge	171:3a7713b1edbc	733	#if defined(SYSCFG_ITLINE2_SR_RTC_WAKEUP)
AnnaBridge	171:3a7713b1edbc	734	/**
AnnaBridge	171:3a7713b1edbc	735	* @brief Check if RTC Wake Up interrupt occurred or not (EXTI line 20).
AnnaBridge	171:3a7713b1edbc	736	* @rmtoll SYSCFG_ITLINE2 SR_RTC_WAKEUP LL_SYSCFG_IsActiveFlag_RTC_WAKEUP
AnnaBridge	171:3a7713b1edbc	737	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	738	*/
AnnaBridge	171:3a7713b1edbc	739	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_WAKEUP(void)
AnnaBridge	171:3a7713b1edbc	740	{
AnnaBridge	171:3a7713b1edbc	741	return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_WAKEUP) == (SYSCFG_ITLINE2_SR_RTC_WAKEUP));
AnnaBridge	171:3a7713b1edbc	742	}
AnnaBridge	171:3a7713b1edbc	743	#endif /* SYSCFG_ITLINE2_SR_RTC_WAKEUP */
AnnaBridge	171:3a7713b1edbc	744
AnnaBridge	171:3a7713b1edbc	745	#if defined(SYSCFG_ITLINE2_SR_RTC_TSTAMP)
AnnaBridge	171:3a7713b1edbc	746	/**
AnnaBridge	171:3a7713b1edbc	747	* @brief Check if RTC Tamper and TimeStamp interrupt occurred or not (EXTI line 19).
AnnaBridge	171:3a7713b1edbc	748	* @rmtoll SYSCFG_ITLINE2 SR_RTC_TSTAMP LL_SYSCFG_IsActiveFlag_RTC_TSTAMP
AnnaBridge	171:3a7713b1edbc	749	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	750	*/
AnnaBridge	171:3a7713b1edbc	751	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_TSTAMP(void)
AnnaBridge	171:3a7713b1edbc	752	{
AnnaBridge	171:3a7713b1edbc	753	return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_TSTAMP) == (SYSCFG_ITLINE2_SR_RTC_TSTAMP));
AnnaBridge	171:3a7713b1edbc	754	}
AnnaBridge	171:3a7713b1edbc	755	#endif /* SYSCFG_ITLINE2_SR_RTC_TSTAMP */
AnnaBridge	171:3a7713b1edbc	756
AnnaBridge	171:3a7713b1edbc	757	#if defined(SYSCFG_ITLINE2_SR_RTC_ALRA)
AnnaBridge	171:3a7713b1edbc	758	/**
AnnaBridge	171:3a7713b1edbc	759	* @brief Check if RTC Alarm interrupt occurred or not (EXTI line 17).
AnnaBridge	171:3a7713b1edbc	760	* @rmtoll SYSCFG_ITLINE2 SR_RTC_ALRA LL_SYSCFG_IsActiveFlag_RTC_ALRA
AnnaBridge	171:3a7713b1edbc	761	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	762	*/
AnnaBridge	171:3a7713b1edbc	763	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC_ALRA(void)
AnnaBridge	171:3a7713b1edbc	764	{
AnnaBridge	171:3a7713b1edbc	765	return (READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC_ALRA) == (SYSCFG_ITLINE2_SR_RTC_ALRA));
AnnaBridge	171:3a7713b1edbc	766	}
AnnaBridge	171:3a7713b1edbc	767	#endif /* SYSCFG_ITLINE2_SR_RTC_ALRA */
AnnaBridge	171:3a7713b1edbc	768
AnnaBridge	171:3a7713b1edbc	769	#if defined(SYSCFG_ITLINE3_SR_FLASH_ITF)
AnnaBridge	171:3a7713b1edbc	770	/**
AnnaBridge	171:3a7713b1edbc	771	* @brief Check if Flash interface interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	772	* @rmtoll SYSCFG_ITLINE3 SR_FLASH_ITF LL_SYSCFG_IsActiveFlag_FLASH_ITF
AnnaBridge	171:3a7713b1edbc	773	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	774	*/
AnnaBridge	171:3a7713b1edbc	775	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FLASH_ITF(void)
AnnaBridge	171:3a7713b1edbc	776	{
AnnaBridge	171:3a7713b1edbc	777	return (READ_BIT(SYSCFG->IT_LINE_SR[3], SYSCFG_ITLINE3_SR_FLASH_ITF) == (SYSCFG_ITLINE3_SR_FLASH_ITF));
AnnaBridge	171:3a7713b1edbc	778	}
AnnaBridge	171:3a7713b1edbc	779	#endif /* SYSCFG_ITLINE3_SR_FLASH_ITF */
AnnaBridge	171:3a7713b1edbc	780
AnnaBridge	171:3a7713b1edbc	781	#if defined(SYSCFG_ITLINE4_SR_CRS)
AnnaBridge	171:3a7713b1edbc	782	/**
AnnaBridge	171:3a7713b1edbc	783	* @brief Check if Clock recovery system interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	784	* @rmtoll SYSCFG_ITLINE4 SR_CRS LL_SYSCFG_IsActiveFlag_CRS
AnnaBridge	171:3a7713b1edbc	785	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	786	*/
AnnaBridge	171:3a7713b1edbc	787	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CRS(void)
AnnaBridge	171:3a7713b1edbc	788	{
AnnaBridge	171:3a7713b1edbc	789	return (READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CRS) == (SYSCFG_ITLINE4_SR_CRS));
AnnaBridge	171:3a7713b1edbc	790	}
AnnaBridge	171:3a7713b1edbc	791	#endif /* SYSCFG_ITLINE4_SR_CRS */
AnnaBridge	171:3a7713b1edbc	792
AnnaBridge	171:3a7713b1edbc	793	#if defined(SYSCFG_ITLINE4_SR_CLK_CTRL)
AnnaBridge	171:3a7713b1edbc	794	/**
AnnaBridge	171:3a7713b1edbc	795	* @brief Check if Reset and clock control interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	796	* @rmtoll SYSCFG_ITLINE4 SR_CLK_CTRL LL_SYSCFG_IsActiveFlag_CLK_CTRL
AnnaBridge	171:3a7713b1edbc	797	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	798	*/
AnnaBridge	171:3a7713b1edbc	799	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CLK_CTRL(void)
AnnaBridge	171:3a7713b1edbc	800	{
AnnaBridge	171:3a7713b1edbc	801	return (READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CLK_CTRL) == (SYSCFG_ITLINE4_SR_CLK_CTRL));
AnnaBridge	171:3a7713b1edbc	802	}
AnnaBridge	171:3a7713b1edbc	803	#endif /* SYSCFG_ITLINE4_SR_CLK_CTRL */
AnnaBridge	171:3a7713b1edbc	804
AnnaBridge	171:3a7713b1edbc	805	#if defined(SYSCFG_ITLINE5_SR_EXTI0)
AnnaBridge	171:3a7713b1edbc	806	/**
AnnaBridge	171:3a7713b1edbc	807	* @brief Check if EXTI line 0 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	808	* @rmtoll SYSCFG_ITLINE5 SR_EXTI0 LL_SYSCFG_IsActiveFlag_EXTI0
AnnaBridge	171:3a7713b1edbc	809	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	810	*/
AnnaBridge	171:3a7713b1edbc	811	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI0(void)
AnnaBridge	171:3a7713b1edbc	812	{
AnnaBridge	171:3a7713b1edbc	813	return (READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI0) == (SYSCFG_ITLINE5_SR_EXTI0));
AnnaBridge	171:3a7713b1edbc	814	}
AnnaBridge	171:3a7713b1edbc	815	#endif /* SYSCFG_ITLINE5_SR_EXTI0 */
AnnaBridge	171:3a7713b1edbc	816
AnnaBridge	171:3a7713b1edbc	817	#if defined(SYSCFG_ITLINE5_SR_EXTI1)
AnnaBridge	171:3a7713b1edbc	818	/**
AnnaBridge	171:3a7713b1edbc	819	* @brief Check if EXTI line 1 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	820	* @rmtoll SYSCFG_ITLINE5 SR_EXTI1 LL_SYSCFG_IsActiveFlag_EXTI1
AnnaBridge	171:3a7713b1edbc	821	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	822	*/
AnnaBridge	171:3a7713b1edbc	823	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI1(void)
AnnaBridge	171:3a7713b1edbc	824	{
AnnaBridge	171:3a7713b1edbc	825	return (READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI1) == (SYSCFG_ITLINE5_SR_EXTI1));
AnnaBridge	171:3a7713b1edbc	826	}
AnnaBridge	171:3a7713b1edbc	827	#endif /* SYSCFG_ITLINE5_SR_EXTI1 */
AnnaBridge	171:3a7713b1edbc	828
AnnaBridge	171:3a7713b1edbc	829	#if defined(SYSCFG_ITLINE6_SR_EXTI2)
AnnaBridge	171:3a7713b1edbc	830	/**
AnnaBridge	171:3a7713b1edbc	831	* @brief Check if EXTI line 2 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	832	* @rmtoll SYSCFG_ITLINE6 SR_EXTI2 LL_SYSCFG_IsActiveFlag_EXTI2
AnnaBridge	171:3a7713b1edbc	833	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	834	*/
AnnaBridge	171:3a7713b1edbc	835	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI2(void)
AnnaBridge	171:3a7713b1edbc	836	{
AnnaBridge	171:3a7713b1edbc	837	return (READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI2) == (SYSCFG_ITLINE6_SR_EXTI2));
AnnaBridge	171:3a7713b1edbc	838	}
AnnaBridge	171:3a7713b1edbc	839	#endif /* SYSCFG_ITLINE6_SR_EXTI2 */
AnnaBridge	171:3a7713b1edbc	840
AnnaBridge	171:3a7713b1edbc	841	#if defined(SYSCFG_ITLINE6_SR_EXTI3)
AnnaBridge	171:3a7713b1edbc	842	/**
AnnaBridge	171:3a7713b1edbc	843	* @brief Check if EXTI line 3 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	844	* @rmtoll SYSCFG_ITLINE6 SR_EXTI3 LL_SYSCFG_IsActiveFlag_EXTI3
AnnaBridge	171:3a7713b1edbc	845	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	846	*/
AnnaBridge	171:3a7713b1edbc	847	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI3(void)
AnnaBridge	171:3a7713b1edbc	848	{
AnnaBridge	171:3a7713b1edbc	849	return (READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI3) == (SYSCFG_ITLINE6_SR_EXTI3));
AnnaBridge	171:3a7713b1edbc	850	}
AnnaBridge	171:3a7713b1edbc	851	#endif /* SYSCFG_ITLINE6_SR_EXTI3 */
AnnaBridge	171:3a7713b1edbc	852
AnnaBridge	171:3a7713b1edbc	853	#if defined(SYSCFG_ITLINE7_SR_EXTI4)
AnnaBridge	171:3a7713b1edbc	854	/**
AnnaBridge	171:3a7713b1edbc	855	* @brief Check if EXTI line 4 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	856	* @rmtoll SYSCFG_ITLINE7 SR_EXTI4 LL_SYSCFG_IsActiveFlag_EXTI4
AnnaBridge	171:3a7713b1edbc	857	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	858	*/
AnnaBridge	171:3a7713b1edbc	859	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI4(void)
AnnaBridge	171:3a7713b1edbc	860	{
AnnaBridge	171:3a7713b1edbc	861	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI4) == (SYSCFG_ITLINE7_SR_EXTI4));
AnnaBridge	171:3a7713b1edbc	862	}
AnnaBridge	171:3a7713b1edbc	863	#endif /* SYSCFG_ITLINE7_SR_EXTI4 */
AnnaBridge	171:3a7713b1edbc	864
AnnaBridge	171:3a7713b1edbc	865	#if defined(SYSCFG_ITLINE7_SR_EXTI5)
AnnaBridge	171:3a7713b1edbc	866	/**
AnnaBridge	171:3a7713b1edbc	867	* @brief Check if EXTI line 5 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	868	* @rmtoll SYSCFG_ITLINE7 SR_EXTI5 LL_SYSCFG_IsActiveFlag_EXTI5
AnnaBridge	171:3a7713b1edbc	869	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	870	*/
AnnaBridge	171:3a7713b1edbc	871	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI5(void)
AnnaBridge	171:3a7713b1edbc	872	{
AnnaBridge	171:3a7713b1edbc	873	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI5) == (SYSCFG_ITLINE7_SR_EXTI5));
AnnaBridge	171:3a7713b1edbc	874	}
AnnaBridge	171:3a7713b1edbc	875	#endif /* SYSCFG_ITLINE7_SR_EXTI5 */
AnnaBridge	171:3a7713b1edbc	876
AnnaBridge	171:3a7713b1edbc	877	#if defined(SYSCFG_ITLINE7_SR_EXTI6)
AnnaBridge	171:3a7713b1edbc	878	/**
AnnaBridge	171:3a7713b1edbc	879	* @brief Check if EXTI line 6 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	880	* @rmtoll SYSCFG_ITLINE7 SR_EXTI6 LL_SYSCFG_IsActiveFlag_EXTI6
AnnaBridge	171:3a7713b1edbc	881	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	882	*/
AnnaBridge	171:3a7713b1edbc	883	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI6(void)
AnnaBridge	171:3a7713b1edbc	884	{
AnnaBridge	171:3a7713b1edbc	885	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI6) == (SYSCFG_ITLINE7_SR_EXTI6));
AnnaBridge	171:3a7713b1edbc	886	}
AnnaBridge	171:3a7713b1edbc	887	#endif /* SYSCFG_ITLINE7_SR_EXTI6 */
AnnaBridge	171:3a7713b1edbc	888
AnnaBridge	171:3a7713b1edbc	889	#if defined(SYSCFG_ITLINE7_SR_EXTI7)
AnnaBridge	171:3a7713b1edbc	890	/**
AnnaBridge	171:3a7713b1edbc	891	* @brief Check if EXTI line 7 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	892	* @rmtoll SYSCFG_ITLINE7 SR_EXTI7 LL_SYSCFG_IsActiveFlag_EXTI7
AnnaBridge	171:3a7713b1edbc	893	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	894	*/
AnnaBridge	171:3a7713b1edbc	895	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI7(void)
AnnaBridge	171:3a7713b1edbc	896	{
AnnaBridge	171:3a7713b1edbc	897	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI7) == (SYSCFG_ITLINE7_SR_EXTI7));
AnnaBridge	171:3a7713b1edbc	898	}
AnnaBridge	171:3a7713b1edbc	899	#endif /* SYSCFG_ITLINE7_SR_EXTI7 */
AnnaBridge	171:3a7713b1edbc	900
AnnaBridge	171:3a7713b1edbc	901	#if defined(SYSCFG_ITLINE7_SR_EXTI8)
AnnaBridge	171:3a7713b1edbc	902	/**
AnnaBridge	171:3a7713b1edbc	903	* @brief Check if EXTI line 8 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	904	* @rmtoll SYSCFG_ITLINE7 SR_EXTI8 LL_SYSCFG_IsActiveFlag_EXTI8
AnnaBridge	171:3a7713b1edbc	905	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	906	*/
AnnaBridge	171:3a7713b1edbc	907	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI8(void)
AnnaBridge	171:3a7713b1edbc	908	{
AnnaBridge	171:3a7713b1edbc	909	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI8) == (SYSCFG_ITLINE7_SR_EXTI8));
AnnaBridge	171:3a7713b1edbc	910	}
AnnaBridge	171:3a7713b1edbc	911	#endif /* SYSCFG_ITLINE7_SR_EXTI8 */
AnnaBridge	171:3a7713b1edbc	912
AnnaBridge	171:3a7713b1edbc	913	#if defined(SYSCFG_ITLINE7_SR_EXTI9)
AnnaBridge	171:3a7713b1edbc	914	/**
AnnaBridge	171:3a7713b1edbc	915	* @brief Check if EXTI line 9 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	916	* @rmtoll SYSCFG_ITLINE7 SR_EXTI9 LL_SYSCFG_IsActiveFlag_EXTI9
AnnaBridge	171:3a7713b1edbc	917	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	918	*/
AnnaBridge	171:3a7713b1edbc	919	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI9(void)
AnnaBridge	171:3a7713b1edbc	920	{
AnnaBridge	171:3a7713b1edbc	921	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI9) == (SYSCFG_ITLINE7_SR_EXTI9));
AnnaBridge	171:3a7713b1edbc	922	}
AnnaBridge	171:3a7713b1edbc	923	#endif /* SYSCFG_ITLINE7_SR_EXTI9 */
AnnaBridge	171:3a7713b1edbc	924
AnnaBridge	171:3a7713b1edbc	925	#if defined(SYSCFG_ITLINE7_SR_EXTI10)
AnnaBridge	171:3a7713b1edbc	926	/**
AnnaBridge	171:3a7713b1edbc	927	* @brief Check if EXTI line 10 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	928	* @rmtoll SYSCFG_ITLINE7 SR_EXTI10 LL_SYSCFG_IsActiveFlag_EXTI10
AnnaBridge	171:3a7713b1edbc	929	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	930	*/
AnnaBridge	171:3a7713b1edbc	931	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI10(void)
AnnaBridge	171:3a7713b1edbc	932	{
AnnaBridge	171:3a7713b1edbc	933	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI10) == (SYSCFG_ITLINE7_SR_EXTI10));
AnnaBridge	171:3a7713b1edbc	934	}
AnnaBridge	171:3a7713b1edbc	935	#endif /* SYSCFG_ITLINE7_SR_EXTI10 */
AnnaBridge	171:3a7713b1edbc	936
AnnaBridge	171:3a7713b1edbc	937	#if defined(SYSCFG_ITLINE7_SR_EXTI11)
AnnaBridge	171:3a7713b1edbc	938	/**
AnnaBridge	171:3a7713b1edbc	939	* @brief Check if EXTI line 11 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	940	* @rmtoll SYSCFG_ITLINE7 SR_EXTI11 LL_SYSCFG_IsActiveFlag_EXTI11
AnnaBridge	171:3a7713b1edbc	941	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	942	*/
AnnaBridge	171:3a7713b1edbc	943	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI11(void)
AnnaBridge	171:3a7713b1edbc	944	{
AnnaBridge	171:3a7713b1edbc	945	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI11) == (SYSCFG_ITLINE7_SR_EXTI11));
AnnaBridge	171:3a7713b1edbc	946	}
AnnaBridge	171:3a7713b1edbc	947	#endif /* SYSCFG_ITLINE7_SR_EXTI11 */
AnnaBridge	171:3a7713b1edbc	948
AnnaBridge	171:3a7713b1edbc	949	#if defined(SYSCFG_ITLINE7_SR_EXTI12)
AnnaBridge	171:3a7713b1edbc	950	/**
AnnaBridge	171:3a7713b1edbc	951	* @brief Check if EXTI line 12 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	952	* @rmtoll SYSCFG_ITLINE7 SR_EXTI12 LL_SYSCFG_IsActiveFlag_EXTI12
AnnaBridge	171:3a7713b1edbc	953	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	954	*/
AnnaBridge	171:3a7713b1edbc	955	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI12(void)
AnnaBridge	171:3a7713b1edbc	956	{
AnnaBridge	171:3a7713b1edbc	957	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI12) == (SYSCFG_ITLINE7_SR_EXTI12));
AnnaBridge	171:3a7713b1edbc	958	}
AnnaBridge	171:3a7713b1edbc	959	#endif /* SYSCFG_ITLINE7_SR_EXTI12 */
AnnaBridge	171:3a7713b1edbc	960
AnnaBridge	171:3a7713b1edbc	961	#if defined(SYSCFG_ITLINE7_SR_EXTI13)
AnnaBridge	171:3a7713b1edbc	962	/**
AnnaBridge	171:3a7713b1edbc	963	* @brief Check if EXTI line 13 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	964	* @rmtoll SYSCFG_ITLINE7 SR_EXTI13 LL_SYSCFG_IsActiveFlag_EXTI13
AnnaBridge	171:3a7713b1edbc	965	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	966	*/
AnnaBridge	171:3a7713b1edbc	967	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI13(void)
AnnaBridge	171:3a7713b1edbc	968	{
AnnaBridge	171:3a7713b1edbc	969	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI13) == (SYSCFG_ITLINE7_SR_EXTI13));
AnnaBridge	171:3a7713b1edbc	970	}
AnnaBridge	171:3a7713b1edbc	971	#endif /* SYSCFG_ITLINE7_SR_EXTI13 */
AnnaBridge	171:3a7713b1edbc	972
AnnaBridge	171:3a7713b1edbc	973	#if defined(SYSCFG_ITLINE7_SR_EXTI14)
AnnaBridge	171:3a7713b1edbc	974	/**
AnnaBridge	171:3a7713b1edbc	975	* @brief Check if EXTI line 14 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	976	* @rmtoll SYSCFG_ITLINE7 SR_EXTI14 LL_SYSCFG_IsActiveFlag_EXTI14
AnnaBridge	171:3a7713b1edbc	977	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	978	*/
AnnaBridge	171:3a7713b1edbc	979	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI14(void)
AnnaBridge	171:3a7713b1edbc	980	{
AnnaBridge	171:3a7713b1edbc	981	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI14) == (SYSCFG_ITLINE7_SR_EXTI14));
AnnaBridge	171:3a7713b1edbc	982	}
AnnaBridge	171:3a7713b1edbc	983	#endif /* SYSCFG_ITLINE7_SR_EXTI14 */
AnnaBridge	171:3a7713b1edbc	984
AnnaBridge	171:3a7713b1edbc	985	#if defined(SYSCFG_ITLINE7_SR_EXTI15)
AnnaBridge	171:3a7713b1edbc	986	/**
AnnaBridge	171:3a7713b1edbc	987	* @brief Check if EXTI line 15 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	988	* @rmtoll SYSCFG_ITLINE7 SR_EXTI15 LL_SYSCFG_IsActiveFlag_EXTI15
AnnaBridge	171:3a7713b1edbc	989	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	990	*/
AnnaBridge	171:3a7713b1edbc	991	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI15(void)
AnnaBridge	171:3a7713b1edbc	992	{
AnnaBridge	171:3a7713b1edbc	993	return (READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI15) == (SYSCFG_ITLINE7_SR_EXTI15));
AnnaBridge	171:3a7713b1edbc	994	}
AnnaBridge	171:3a7713b1edbc	995	#endif /* SYSCFG_ITLINE7_SR_EXTI15 */
AnnaBridge	171:3a7713b1edbc	996
AnnaBridge	171:3a7713b1edbc	997	#if defined(SYSCFG_ITLINE8_SR_TSC_EOA)
AnnaBridge	171:3a7713b1edbc	998	/**
AnnaBridge	171:3a7713b1edbc	999	* @brief Check if Touch sensing controller end of acquisition interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1000	* @rmtoll SYSCFG_ITLINE8 SR_TSC_EOA LL_SYSCFG_IsActiveFlag_TSC_EOA
AnnaBridge	171:3a7713b1edbc	1001	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1002	*/
AnnaBridge	171:3a7713b1edbc	1003	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TSC_EOA(void)
AnnaBridge	171:3a7713b1edbc	1004	{
AnnaBridge	171:3a7713b1edbc	1005	return (READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_TSC_EOA) == (SYSCFG_ITLINE8_SR_TSC_EOA));
AnnaBridge	171:3a7713b1edbc	1006	}
AnnaBridge	171:3a7713b1edbc	1007	#endif /* SYSCFG_ITLINE8_SR_TSC_EOA */
AnnaBridge	171:3a7713b1edbc	1008
AnnaBridge	171:3a7713b1edbc	1009	#if defined(SYSCFG_ITLINE8_SR_TSC_MCE)
AnnaBridge	171:3a7713b1edbc	1010	/**
AnnaBridge	171:3a7713b1edbc	1011	* @brief Check if Touch sensing controller max counterror interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1012	* @rmtoll SYSCFG_ITLINE8 SR_TSC_MCE LL_SYSCFG_IsActiveFlag_TSC_MCE
AnnaBridge	171:3a7713b1edbc	1013	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1014	*/
AnnaBridge	171:3a7713b1edbc	1015	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TSC_MCE(void)
AnnaBridge	171:3a7713b1edbc	1016	{
AnnaBridge	171:3a7713b1edbc	1017	return (READ_BIT(SYSCFG->IT_LINE_SR[8], SYSCFG_ITLINE8_SR_TSC_MCE) == (SYSCFG_ITLINE8_SR_TSC_MCE));
AnnaBridge	171:3a7713b1edbc	1018	}
AnnaBridge	171:3a7713b1edbc	1019	#endif /* SYSCFG_ITLINE8_SR_TSC_MCE */
AnnaBridge	171:3a7713b1edbc	1020
AnnaBridge	171:3a7713b1edbc	1021	#if defined(SYSCFG_ITLINE9_SR_DMA1_CH1)
AnnaBridge	171:3a7713b1edbc	1022	/**
AnnaBridge	171:3a7713b1edbc	1023	* @brief Check if DMA1 channel 1 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1024	* @rmtoll SYSCFG_ITLINE9 SR_DMA1_CH1 LL_SYSCFG_IsActiveFlag_DMA1_CH1
AnnaBridge	171:3a7713b1edbc	1025	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1026	*/
AnnaBridge	171:3a7713b1edbc	1027	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH1(void)
AnnaBridge	171:3a7713b1edbc	1028	{
AnnaBridge	171:3a7713b1edbc	1029	return (READ_BIT(SYSCFG->IT_LINE_SR[9], SYSCFG_ITLINE9_SR_DMA1_CH1) == (SYSCFG_ITLINE9_SR_DMA1_CH1));
AnnaBridge	171:3a7713b1edbc	1030	}
AnnaBridge	171:3a7713b1edbc	1031	#endif /* SYSCFG_ITLINE9_SR_DMA1_CH1 */
AnnaBridge	171:3a7713b1edbc	1032
AnnaBridge	171:3a7713b1edbc	1033	#if defined(SYSCFG_ITLINE10_SR_DMA1_CH2)
AnnaBridge	171:3a7713b1edbc	1034	/**
AnnaBridge	171:3a7713b1edbc	1035	* @brief Check if DMA1 channel 2 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1036	* @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH2 LL_SYSCFG_IsActiveFlag_DMA1_CH2
AnnaBridge	171:3a7713b1edbc	1037	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1038	*/
AnnaBridge	171:3a7713b1edbc	1039	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH2(void)
AnnaBridge	171:3a7713b1edbc	1040	{
AnnaBridge	171:3a7713b1edbc	1041	return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH2) == (SYSCFG_ITLINE10_SR_DMA1_CH2));
AnnaBridge	171:3a7713b1edbc	1042	}
AnnaBridge	171:3a7713b1edbc	1043	#endif /* SYSCFG_ITLINE10_SR_DMA1_CH2 */
AnnaBridge	171:3a7713b1edbc	1044
AnnaBridge	171:3a7713b1edbc	1045	#if defined(SYSCFG_ITLINE10_SR_DMA1_CH3)
AnnaBridge	171:3a7713b1edbc	1046	/**
AnnaBridge	171:3a7713b1edbc	1047	* @brief Check if DMA1 channel 3 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1048	* @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH3 LL_SYSCFG_IsActiveFlag_DMA1_CH3
AnnaBridge	171:3a7713b1edbc	1049	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1050	*/
AnnaBridge	171:3a7713b1edbc	1051	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH3(void)
AnnaBridge	171:3a7713b1edbc	1052	{
AnnaBridge	171:3a7713b1edbc	1053	return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH3) == (SYSCFG_ITLINE10_SR_DMA1_CH3));
AnnaBridge	171:3a7713b1edbc	1054	}
AnnaBridge	171:3a7713b1edbc	1055	#endif /* SYSCFG_ITLINE10_SR_DMA1_CH3 */
AnnaBridge	171:3a7713b1edbc	1056
AnnaBridge	171:3a7713b1edbc	1057	#if defined(SYSCFG_ITLINE10_SR_DMA2_CH1)
AnnaBridge	171:3a7713b1edbc	1058	/**
AnnaBridge	171:3a7713b1edbc	1059	* @brief Check if DMA2 channel 1 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1060	* @rmtoll SYSCFG_ITLINE10 SR_DMA2_CH1 LL_SYSCFG_IsActiveFlag_DMA2_CH1
AnnaBridge	171:3a7713b1edbc	1061	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1062	*/
AnnaBridge	171:3a7713b1edbc	1063	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH1(void)
AnnaBridge	171:3a7713b1edbc	1064	{
AnnaBridge	171:3a7713b1edbc	1065	return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA2_CH1) == (SYSCFG_ITLINE10_SR_DMA2_CH1));
AnnaBridge	171:3a7713b1edbc	1066	}
AnnaBridge	171:3a7713b1edbc	1067	#endif /* SYSCFG_ITLINE10_SR_DMA2_CH1 */
AnnaBridge	171:3a7713b1edbc	1068
AnnaBridge	171:3a7713b1edbc	1069	#if defined(SYSCFG_ITLINE10_SR_DMA2_CH2)
AnnaBridge	171:3a7713b1edbc	1070	/**
AnnaBridge	171:3a7713b1edbc	1071	* @brief Check if DMA2 channel 2 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1072	* @rmtoll SYSCFG_ITLINE10 SR_DMA2_CH2 LL_SYSCFG_IsActiveFlag_DMA2_CH2
AnnaBridge	171:3a7713b1edbc	1073	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1074	*/
AnnaBridge	171:3a7713b1edbc	1075	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH2(void)
AnnaBridge	171:3a7713b1edbc	1076	{
AnnaBridge	171:3a7713b1edbc	1077	return (READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA2_CH2) == (SYSCFG_ITLINE10_SR_DMA2_CH2));
AnnaBridge	171:3a7713b1edbc	1078	}
AnnaBridge	171:3a7713b1edbc	1079	#endif /* SYSCFG_ITLINE10_SR_DMA2_CH2 */
AnnaBridge	171:3a7713b1edbc	1080
AnnaBridge	171:3a7713b1edbc	1081	#if defined(SYSCFG_ITLINE11_SR_DMA1_CH4)
AnnaBridge	171:3a7713b1edbc	1082	/**
AnnaBridge	171:3a7713b1edbc	1083	* @brief Check if DMA1 channel 4 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1084	* @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH4 LL_SYSCFG_IsActiveFlag_DMA1_CH4
AnnaBridge	171:3a7713b1edbc	1085	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1086	*/
AnnaBridge	171:3a7713b1edbc	1087	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH4(void)
AnnaBridge	171:3a7713b1edbc	1088	{
AnnaBridge	171:3a7713b1edbc	1089	return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH4) == (SYSCFG_ITLINE11_SR_DMA1_CH4));
AnnaBridge	171:3a7713b1edbc	1090	}
AnnaBridge	171:3a7713b1edbc	1091	#endif /* SYSCFG_ITLINE11_SR_DMA1_CH4 */
AnnaBridge	171:3a7713b1edbc	1092
AnnaBridge	171:3a7713b1edbc	1093	#if defined(SYSCFG_ITLINE11_SR_DMA1_CH5)
AnnaBridge	171:3a7713b1edbc	1094	/**
AnnaBridge	171:3a7713b1edbc	1095	* @brief Check if DMA1 channel 5 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1096	* @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH5 LL_SYSCFG_IsActiveFlag_DMA1_CH5
AnnaBridge	171:3a7713b1edbc	1097	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1098	*/
AnnaBridge	171:3a7713b1edbc	1099	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH5(void)
AnnaBridge	171:3a7713b1edbc	1100	{
AnnaBridge	171:3a7713b1edbc	1101	return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH5) == (SYSCFG_ITLINE11_SR_DMA1_CH5));
AnnaBridge	171:3a7713b1edbc	1102	}
AnnaBridge	171:3a7713b1edbc	1103	#endif /* SYSCFG_ITLINE11_SR_DMA1_CH5 */
AnnaBridge	171:3a7713b1edbc	1104
AnnaBridge	171:3a7713b1edbc	1105	#if defined(SYSCFG_ITLINE11_SR_DMA1_CH6)
AnnaBridge	171:3a7713b1edbc	1106	/**
AnnaBridge	171:3a7713b1edbc	1107	* @brief Check if DMA1 channel 6 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1108	* @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH6 LL_SYSCFG_IsActiveFlag_DMA1_CH6
AnnaBridge	171:3a7713b1edbc	1109	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1110	*/
AnnaBridge	171:3a7713b1edbc	1111	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH6(void)
AnnaBridge	171:3a7713b1edbc	1112	{
AnnaBridge	171:3a7713b1edbc	1113	return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH6) == (SYSCFG_ITLINE11_SR_DMA1_CH6));
AnnaBridge	171:3a7713b1edbc	1114	}
AnnaBridge	171:3a7713b1edbc	1115	#endif /* SYSCFG_ITLINE11_SR_DMA1_CH6 */
AnnaBridge	171:3a7713b1edbc	1116
AnnaBridge	171:3a7713b1edbc	1117	#if defined(SYSCFG_ITLINE11_SR_DMA1_CH7)
AnnaBridge	171:3a7713b1edbc	1118	/**
AnnaBridge	171:3a7713b1edbc	1119	* @brief Check if DMA1 channel 7 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1120	* @rmtoll SYSCFG_ITLINE11 SR_DMA1_CH7 LL_SYSCFG_IsActiveFlag_DMA1_CH7
AnnaBridge	171:3a7713b1edbc	1121	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1122	*/
AnnaBridge	171:3a7713b1edbc	1123	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH7(void)
AnnaBridge	171:3a7713b1edbc	1124	{
AnnaBridge	171:3a7713b1edbc	1125	return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA1_CH7) == (SYSCFG_ITLINE11_SR_DMA1_CH7));
AnnaBridge	171:3a7713b1edbc	1126	}
AnnaBridge	171:3a7713b1edbc	1127	#endif /* SYSCFG_ITLINE11_SR_DMA1_CH7 */
AnnaBridge	171:3a7713b1edbc	1128
AnnaBridge	171:3a7713b1edbc	1129	#if defined(SYSCFG_ITLINE11_SR_DMA2_CH3)
AnnaBridge	171:3a7713b1edbc	1130	/**
AnnaBridge	171:3a7713b1edbc	1131	* @brief Check if DMA2 channel 3 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1132	* @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH3 LL_SYSCFG_IsActiveFlag_DMA2_CH3
AnnaBridge	171:3a7713b1edbc	1133	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1134	*/
AnnaBridge	171:3a7713b1edbc	1135	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH3(void)
AnnaBridge	171:3a7713b1edbc	1136	{
AnnaBridge	171:3a7713b1edbc	1137	return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH3) == (SYSCFG_ITLINE11_SR_DMA2_CH3));
AnnaBridge	171:3a7713b1edbc	1138	}
AnnaBridge	171:3a7713b1edbc	1139	#endif /* SYSCFG_ITLINE11_SR_DMA2_CH3 */
AnnaBridge	171:3a7713b1edbc	1140
AnnaBridge	171:3a7713b1edbc	1141	#if defined(SYSCFG_ITLINE11_SR_DMA2_CH4)
AnnaBridge	171:3a7713b1edbc	1142	/**
AnnaBridge	171:3a7713b1edbc	1143	* @brief Check if DMA2 channel 4 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1144	* @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH4 LL_SYSCFG_IsActiveFlag_DMA2_CH4
AnnaBridge	171:3a7713b1edbc	1145	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1146	*/
AnnaBridge	171:3a7713b1edbc	1147	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH4(void)
AnnaBridge	171:3a7713b1edbc	1148	{
AnnaBridge	171:3a7713b1edbc	1149	return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH4) == (SYSCFG_ITLINE11_SR_DMA2_CH4));
AnnaBridge	171:3a7713b1edbc	1150	}
AnnaBridge	171:3a7713b1edbc	1151	#endif /* SYSCFG_ITLINE11_SR_DMA2_CH4 */
AnnaBridge	171:3a7713b1edbc	1152
AnnaBridge	171:3a7713b1edbc	1153	#if defined(SYSCFG_ITLINE11_SR_DMA2_CH5)
AnnaBridge	171:3a7713b1edbc	1154	/**
AnnaBridge	171:3a7713b1edbc	1155	* @brief Check if DMA2 channel 5 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1156	* @rmtoll SYSCFG_ITLINE11 SR_DMA2_CH5 LL_SYSCFG_IsActiveFlag_DMA2_CH5
AnnaBridge	171:3a7713b1edbc	1157	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1158	*/
AnnaBridge	171:3a7713b1edbc	1159	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA2_CH5(void)
AnnaBridge	171:3a7713b1edbc	1160	{
AnnaBridge	171:3a7713b1edbc	1161	return (READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMA2_CH5) == (SYSCFG_ITLINE11_SR_DMA2_CH5));
AnnaBridge	171:3a7713b1edbc	1162	}
AnnaBridge	171:3a7713b1edbc	1163	#endif /* SYSCFG_ITLINE11_SR_DMA2_CH5 */
AnnaBridge	171:3a7713b1edbc	1164
AnnaBridge	171:3a7713b1edbc	1165	#if defined(SYSCFG_ITLINE12_SR_ADC)
AnnaBridge	171:3a7713b1edbc	1166	/**
AnnaBridge	171:3a7713b1edbc	1167	* @brief Check if ADC interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1168	* @rmtoll SYSCFG_ITLINE12 SR_ADC LL_SYSCFG_IsActiveFlag_ADC
AnnaBridge	171:3a7713b1edbc	1169	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1170	*/
AnnaBridge	171:3a7713b1edbc	1171	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_ADC(void)
AnnaBridge	171:3a7713b1edbc	1172	{
AnnaBridge	171:3a7713b1edbc	1173	return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_ADC) == (SYSCFG_ITLINE12_SR_ADC));
AnnaBridge	171:3a7713b1edbc	1174	}
AnnaBridge	171:3a7713b1edbc	1175	#endif /* SYSCFG_ITLINE12_SR_ADC */
AnnaBridge	171:3a7713b1edbc	1176
AnnaBridge	171:3a7713b1edbc	1177	#if defined(SYSCFG_ITLINE12_SR_COMP1)
AnnaBridge	171:3a7713b1edbc	1178	/**
AnnaBridge	171:3a7713b1edbc	1179	* @brief Check if Comparator 1 interrupt occurred or not (EXTI line 21).
AnnaBridge	171:3a7713b1edbc	1180	* @rmtoll SYSCFG_ITLINE12 SR_COMP1 LL_SYSCFG_IsActiveFlag_COMP1
AnnaBridge	171:3a7713b1edbc	1181	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1182	*/
AnnaBridge	171:3a7713b1edbc	1183	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP1(void)
AnnaBridge	171:3a7713b1edbc	1184	{
AnnaBridge	171:3a7713b1edbc	1185	return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP1) == (SYSCFG_ITLINE12_SR_COMP1));
AnnaBridge	171:3a7713b1edbc	1186	}
AnnaBridge	171:3a7713b1edbc	1187	#endif /* SYSCFG_ITLINE12_SR_COMP1 */
AnnaBridge	171:3a7713b1edbc	1188
AnnaBridge	171:3a7713b1edbc	1189	#if defined(SYSCFG_ITLINE12_SR_COMP2)
AnnaBridge	171:3a7713b1edbc	1190	/**
AnnaBridge	171:3a7713b1edbc	1191	* @brief Check if Comparator 2 interrupt occurred or not (EXTI line 22).
AnnaBridge	171:3a7713b1edbc	1192	* @rmtoll SYSCFG_ITLINE12 SR_COMP2 LL_SYSCFG_IsActiveFlag_COMP2
AnnaBridge	171:3a7713b1edbc	1193	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1194	*/
AnnaBridge	171:3a7713b1edbc	1195	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_COMP2(void)
AnnaBridge	171:3a7713b1edbc	1196	{
AnnaBridge	171:3a7713b1edbc	1197	return (READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_COMP2) == (SYSCFG_ITLINE12_SR_COMP2));
AnnaBridge	171:3a7713b1edbc	1198	}
AnnaBridge	171:3a7713b1edbc	1199	#endif /* SYSCFG_ITLINE12_SR_COMP2 */
AnnaBridge	171:3a7713b1edbc	1200
AnnaBridge	171:3a7713b1edbc	1201	#if defined(SYSCFG_ITLINE13_SR_TIM1_BRK)
AnnaBridge	171:3a7713b1edbc	1202	/**
AnnaBridge	171:3a7713b1edbc	1203	* @brief Check if Timer 1 break interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1204	* @rmtoll SYSCFG_ITLINE13 SR_TIM1_BRK LL_SYSCFG_IsActiveFlag_TIM1_BRK
AnnaBridge	171:3a7713b1edbc	1205	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1206	*/
AnnaBridge	171:3a7713b1edbc	1207	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_BRK(void)
AnnaBridge	171:3a7713b1edbc	1208	{
AnnaBridge	171:3a7713b1edbc	1209	return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_BRK) == (SYSCFG_ITLINE13_SR_TIM1_BRK));
AnnaBridge	171:3a7713b1edbc	1210	}
AnnaBridge	171:3a7713b1edbc	1211	#endif /* SYSCFG_ITLINE13_SR_TIM1_BRK */
AnnaBridge	171:3a7713b1edbc	1212
AnnaBridge	171:3a7713b1edbc	1213	#if defined(SYSCFG_ITLINE13_SR_TIM1_UPD)
AnnaBridge	171:3a7713b1edbc	1214	/**
AnnaBridge	171:3a7713b1edbc	1215	* @brief Check if Timer 1 update interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1216	* @rmtoll SYSCFG_ITLINE13 SR_TIM1_UPD LL_SYSCFG_IsActiveFlag_TIM1_UPD
AnnaBridge	171:3a7713b1edbc	1217	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1218	*/
AnnaBridge	171:3a7713b1edbc	1219	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_UPD(void)
AnnaBridge	171:3a7713b1edbc	1220	{
AnnaBridge	171:3a7713b1edbc	1221	return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_UPD) == (SYSCFG_ITLINE13_SR_TIM1_UPD));
AnnaBridge	171:3a7713b1edbc	1222	}
AnnaBridge	171:3a7713b1edbc	1223	#endif /* SYSCFG_ITLINE13_SR_TIM1_UPD */
AnnaBridge	171:3a7713b1edbc	1224
AnnaBridge	171:3a7713b1edbc	1225	#if defined(SYSCFG_ITLINE13_SR_TIM1_TRG)
AnnaBridge	171:3a7713b1edbc	1226	/**
AnnaBridge	171:3a7713b1edbc	1227	* @brief Check if Timer 1 trigger interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1228	* @rmtoll SYSCFG_ITLINE13 SR_TIM1_TRG LL_SYSCFG_IsActiveFlag_TIM1_TRG
AnnaBridge	171:3a7713b1edbc	1229	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1230	*/
AnnaBridge	171:3a7713b1edbc	1231	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_TRG(void)
AnnaBridge	171:3a7713b1edbc	1232	{
AnnaBridge	171:3a7713b1edbc	1233	return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_TRG) == (SYSCFG_ITLINE13_SR_TIM1_TRG));
AnnaBridge	171:3a7713b1edbc	1234	}
AnnaBridge	171:3a7713b1edbc	1235	#endif /* SYSCFG_ITLINE13_SR_TIM1_TRG */
AnnaBridge	171:3a7713b1edbc	1236
AnnaBridge	171:3a7713b1edbc	1237	#if defined(SYSCFG_ITLINE13_SR_TIM1_CCU)
AnnaBridge	171:3a7713b1edbc	1238	/**
AnnaBridge	171:3a7713b1edbc	1239	* @brief Check if Timer 1 commutation interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1240	* @rmtoll SYSCFG_ITLINE13 SR_TIM1_CCU LL_SYSCFG_IsActiveFlag_TIM1_CCU
AnnaBridge	171:3a7713b1edbc	1241	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1242	*/
AnnaBridge	171:3a7713b1edbc	1243	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CCU(void)
AnnaBridge	171:3a7713b1edbc	1244	{
AnnaBridge	171:3a7713b1edbc	1245	return (READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_CCU) == (SYSCFG_ITLINE13_SR_TIM1_CCU));
AnnaBridge	171:3a7713b1edbc	1246	}
AnnaBridge	171:3a7713b1edbc	1247	#endif /* SYSCFG_ITLINE13_SR_TIM1_CCU */
AnnaBridge	171:3a7713b1edbc	1248
AnnaBridge	171:3a7713b1edbc	1249	#if defined(SYSCFG_ITLINE14_SR_TIM1_CC)
AnnaBridge	171:3a7713b1edbc	1250	/**
AnnaBridge	171:3a7713b1edbc	1251	* @brief Check if Timer 1 capture compare interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1252	* @rmtoll SYSCFG_ITLINE14 SR_TIM1_CC LL_SYSCFG_IsActiveFlag_TIM1_CC
AnnaBridge	171:3a7713b1edbc	1253	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1254	*/
AnnaBridge	171:3a7713b1edbc	1255	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CC(void)
AnnaBridge	171:3a7713b1edbc	1256	{
AnnaBridge	171:3a7713b1edbc	1257	return (READ_BIT(SYSCFG->IT_LINE_SR[14], SYSCFG_ITLINE14_SR_TIM1_CC) == (SYSCFG_ITLINE14_SR_TIM1_CC));
AnnaBridge	171:3a7713b1edbc	1258	}
AnnaBridge	171:3a7713b1edbc	1259	#endif /* SYSCFG_ITLINE14_SR_TIM1_CC */
AnnaBridge	171:3a7713b1edbc	1260
AnnaBridge	171:3a7713b1edbc	1261	#if defined(SYSCFG_ITLINE15_SR_TIM2_GLB)
AnnaBridge	171:3a7713b1edbc	1262	/**
AnnaBridge	171:3a7713b1edbc	1263	* @brief Check if Timer 2 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1264	* @rmtoll SYSCFG_ITLINE15 SR_TIM2_GLB LL_SYSCFG_IsActiveFlag_TIM2
AnnaBridge	171:3a7713b1edbc	1265	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1266	*/
AnnaBridge	171:3a7713b1edbc	1267	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM2(void)
AnnaBridge	171:3a7713b1edbc	1268	{
AnnaBridge	171:3a7713b1edbc	1269	return (READ_BIT(SYSCFG->IT_LINE_SR[15], SYSCFG_ITLINE15_SR_TIM2_GLB) == (SYSCFG_ITLINE15_SR_TIM2_GLB));
AnnaBridge	171:3a7713b1edbc	1270	}
AnnaBridge	171:3a7713b1edbc	1271	#endif /* SYSCFG_ITLINE15_SR_TIM2_GLB */
AnnaBridge	171:3a7713b1edbc	1272
AnnaBridge	171:3a7713b1edbc	1273	#if defined(SYSCFG_ITLINE16_SR_TIM3_GLB)
AnnaBridge	171:3a7713b1edbc	1274	/**
AnnaBridge	171:3a7713b1edbc	1275	* @brief Check if Timer 3 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1276	* @rmtoll SYSCFG_ITLINE16 SR_TIM3_GLB LL_SYSCFG_IsActiveFlag_TIM3
AnnaBridge	171:3a7713b1edbc	1277	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1278	*/
AnnaBridge	171:3a7713b1edbc	1279	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM3(void)
AnnaBridge	171:3a7713b1edbc	1280	{
AnnaBridge	171:3a7713b1edbc	1281	return (READ_BIT(SYSCFG->IT_LINE_SR[16], SYSCFG_ITLINE16_SR_TIM3_GLB) == (SYSCFG_ITLINE16_SR_TIM3_GLB));
AnnaBridge	171:3a7713b1edbc	1282	}
AnnaBridge	171:3a7713b1edbc	1283	#endif /* SYSCFG_ITLINE16_SR_TIM3_GLB */
AnnaBridge	171:3a7713b1edbc	1284
AnnaBridge	171:3a7713b1edbc	1285	#if defined(SYSCFG_ITLINE17_SR_DAC)
AnnaBridge	171:3a7713b1edbc	1286	/**
AnnaBridge	171:3a7713b1edbc	1287	* @brief Check if DAC underrun interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1288	* @rmtoll SYSCFG_ITLINE17 SR_DAC LL_SYSCFG_IsActiveFlag_DAC
AnnaBridge	171:3a7713b1edbc	1289	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1290	*/
AnnaBridge	171:3a7713b1edbc	1291	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DAC(void)
AnnaBridge	171:3a7713b1edbc	1292	{
AnnaBridge	171:3a7713b1edbc	1293	return (READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_DAC) == (SYSCFG_ITLINE17_SR_DAC));
AnnaBridge	171:3a7713b1edbc	1294	}
AnnaBridge	171:3a7713b1edbc	1295	#endif /* SYSCFG_ITLINE17_SR_DAC */
AnnaBridge	171:3a7713b1edbc	1296
AnnaBridge	171:3a7713b1edbc	1297	#if defined(SYSCFG_ITLINE17_SR_TIM6_GLB)
AnnaBridge	171:3a7713b1edbc	1298	/**
AnnaBridge	171:3a7713b1edbc	1299	* @brief Check if Timer 6 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1300	* @rmtoll SYSCFG_ITLINE17 SR_TIM6_GLB LL_SYSCFG_IsActiveFlag_TIM6
AnnaBridge	171:3a7713b1edbc	1301	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1302	*/
AnnaBridge	171:3a7713b1edbc	1303	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM6(void)
AnnaBridge	171:3a7713b1edbc	1304	{
AnnaBridge	171:3a7713b1edbc	1305	return (READ_BIT(SYSCFG->IT_LINE_SR[17], SYSCFG_ITLINE17_SR_TIM6_GLB) == (SYSCFG_ITLINE17_SR_TIM6_GLB));
AnnaBridge	171:3a7713b1edbc	1306	}
AnnaBridge	171:3a7713b1edbc	1307	#endif /* SYSCFG_ITLINE17_SR_TIM6_GLB */
AnnaBridge	171:3a7713b1edbc	1308
AnnaBridge	171:3a7713b1edbc	1309	#if defined(SYSCFG_ITLINE18_SR_TIM7_GLB)
AnnaBridge	171:3a7713b1edbc	1310	/**
AnnaBridge	171:3a7713b1edbc	1311	* @brief Check if Timer 7 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1312	* @rmtoll SYSCFG_ITLINE18 SR_TIM7_GLB LL_SYSCFG_IsActiveFlag_TIM7
AnnaBridge	171:3a7713b1edbc	1313	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1314	*/
AnnaBridge	171:3a7713b1edbc	1315	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM7(void)
AnnaBridge	171:3a7713b1edbc	1316	{
AnnaBridge	171:3a7713b1edbc	1317	return (READ_BIT(SYSCFG->IT_LINE_SR[18], SYSCFG_ITLINE18_SR_TIM7_GLB) == (SYSCFG_ITLINE18_SR_TIM7_GLB));
AnnaBridge	171:3a7713b1edbc	1318	}
AnnaBridge	171:3a7713b1edbc	1319	#endif /* SYSCFG_ITLINE18_SR_TIM7_GLB */
AnnaBridge	171:3a7713b1edbc	1320
AnnaBridge	171:3a7713b1edbc	1321	#if defined(SYSCFG_ITLINE19_SR_TIM14_GLB)
AnnaBridge	171:3a7713b1edbc	1322	/**
AnnaBridge	171:3a7713b1edbc	1323	* @brief Check if Timer 14 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1324	* @rmtoll SYSCFG_ITLINE19 SR_TIM14_GLB LL_SYSCFG_IsActiveFlag_TIM14
AnnaBridge	171:3a7713b1edbc	1325	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1326	*/
AnnaBridge	171:3a7713b1edbc	1327	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM14(void)
AnnaBridge	171:3a7713b1edbc	1328	{
AnnaBridge	171:3a7713b1edbc	1329	return (READ_BIT(SYSCFG->IT_LINE_SR[19], SYSCFG_ITLINE19_SR_TIM14_GLB) == (SYSCFG_ITLINE19_SR_TIM14_GLB));
AnnaBridge	171:3a7713b1edbc	1330	}
AnnaBridge	171:3a7713b1edbc	1331	#endif /* SYSCFG_ITLINE19_SR_TIM14_GLB */
AnnaBridge	171:3a7713b1edbc	1332
AnnaBridge	171:3a7713b1edbc	1333	#if defined(SYSCFG_ITLINE20_SR_TIM15_GLB)
AnnaBridge	171:3a7713b1edbc	1334	/**
AnnaBridge	171:3a7713b1edbc	1335	* @brief Check if Timer 15 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1336	* @rmtoll SYSCFG_ITLINE20 SR_TIM15_GLB LL_SYSCFG_IsActiveFlag_TIM15
AnnaBridge	171:3a7713b1edbc	1337	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1338	*/
AnnaBridge	171:3a7713b1edbc	1339	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM15(void)
AnnaBridge	171:3a7713b1edbc	1340	{
AnnaBridge	171:3a7713b1edbc	1341	return (READ_BIT(SYSCFG->IT_LINE_SR[20], SYSCFG_ITLINE20_SR_TIM15_GLB) == (SYSCFG_ITLINE20_SR_TIM15_GLB));
AnnaBridge	171:3a7713b1edbc	1342	}
AnnaBridge	171:3a7713b1edbc	1343	#endif /* SYSCFG_ITLINE20_SR_TIM15_GLB */
AnnaBridge	171:3a7713b1edbc	1344
AnnaBridge	171:3a7713b1edbc	1345	#if defined(SYSCFG_ITLINE21_SR_TIM16_GLB)
AnnaBridge	171:3a7713b1edbc	1346	/**
AnnaBridge	171:3a7713b1edbc	1347	* @brief Check if Timer 16 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1348	* @rmtoll SYSCFG_ITLINE21 SR_TIM16_GLB LL_SYSCFG_IsActiveFlag_TIM16
AnnaBridge	171:3a7713b1edbc	1349	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1350	*/
AnnaBridge	171:3a7713b1edbc	1351	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM16(void)
AnnaBridge	171:3a7713b1edbc	1352	{
AnnaBridge	171:3a7713b1edbc	1353	return (READ_BIT(SYSCFG->IT_LINE_SR[21], SYSCFG_ITLINE21_SR_TIM16_GLB) == (SYSCFG_ITLINE21_SR_TIM16_GLB));
AnnaBridge	171:3a7713b1edbc	1354	}
AnnaBridge	171:3a7713b1edbc	1355	#endif /* SYSCFG_ITLINE21_SR_TIM16_GLB */
AnnaBridge	171:3a7713b1edbc	1356
AnnaBridge	171:3a7713b1edbc	1357	#if defined(SYSCFG_ITLINE22_SR_TIM17_GLB)
AnnaBridge	171:3a7713b1edbc	1358	/**
AnnaBridge	171:3a7713b1edbc	1359	* @brief Check if Timer 17 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1360	* @rmtoll SYSCFG_ITLINE22 SR_TIM17_GLB LL_SYSCFG_IsActiveFlag_TIM17
AnnaBridge	171:3a7713b1edbc	1361	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1362	*/
AnnaBridge	171:3a7713b1edbc	1363	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM17(void)
AnnaBridge	171:3a7713b1edbc	1364	{
AnnaBridge	171:3a7713b1edbc	1365	return (READ_BIT(SYSCFG->IT_LINE_SR[22], SYSCFG_ITLINE22_SR_TIM17_GLB) == (SYSCFG_ITLINE22_SR_TIM17_GLB));
AnnaBridge	171:3a7713b1edbc	1366	}
AnnaBridge	171:3a7713b1edbc	1367	#endif /* SYSCFG_ITLINE22_SR_TIM17_GLB */
AnnaBridge	171:3a7713b1edbc	1368
AnnaBridge	171:3a7713b1edbc	1369	#if defined(SYSCFG_ITLINE23_SR_I2C1_GLB)
AnnaBridge	171:3a7713b1edbc	1370	/**
AnnaBridge	171:3a7713b1edbc	1371	* @brief Check if I2C1 interrupt occurred or not, combined with EXTI line 23.
AnnaBridge	171:3a7713b1edbc	1372	* @rmtoll SYSCFG_ITLINE23 SR_I2C1_GLB LL_SYSCFG_IsActiveFlag_I2C1
AnnaBridge	171:3a7713b1edbc	1373	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1374	*/
AnnaBridge	171:3a7713b1edbc	1375	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C1(void)
AnnaBridge	171:3a7713b1edbc	1376	{
AnnaBridge	171:3a7713b1edbc	1377	return (READ_BIT(SYSCFG->IT_LINE_SR[23], SYSCFG_ITLINE23_SR_I2C1_GLB) == (SYSCFG_ITLINE23_SR_I2C1_GLB));
AnnaBridge	171:3a7713b1edbc	1378	}
AnnaBridge	171:3a7713b1edbc	1379	#endif /* SYSCFG_ITLINE23_SR_I2C1_GLB */
AnnaBridge	171:3a7713b1edbc	1380
AnnaBridge	171:3a7713b1edbc	1381	#if defined(SYSCFG_ITLINE24_SR_I2C2_GLB)
AnnaBridge	171:3a7713b1edbc	1382	/**
AnnaBridge	171:3a7713b1edbc	1383	* @brief Check if I2C2 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1384	* @rmtoll SYSCFG_ITLINE24 SR_I2C2_GLB LL_SYSCFG_IsActiveFlag_I2C2
AnnaBridge	171:3a7713b1edbc	1385	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1386	*/
AnnaBridge	171:3a7713b1edbc	1387	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C2(void)
AnnaBridge	171:3a7713b1edbc	1388	{
AnnaBridge	171:3a7713b1edbc	1389	return (READ_BIT(SYSCFG->IT_LINE_SR[24], SYSCFG_ITLINE24_SR_I2C2_GLB) == (SYSCFG_ITLINE24_SR_I2C2_GLB));
AnnaBridge	171:3a7713b1edbc	1390	}
AnnaBridge	171:3a7713b1edbc	1391	#endif /* SYSCFG_ITLINE24_SR_I2C2_GLB */
AnnaBridge	171:3a7713b1edbc	1392
AnnaBridge	171:3a7713b1edbc	1393	#if defined(SYSCFG_ITLINE25_SR_SPI1)
AnnaBridge	171:3a7713b1edbc	1394	/**
AnnaBridge	171:3a7713b1edbc	1395	* @brief Check if SPI1 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1396	* @rmtoll SYSCFG_ITLINE25 SR_SPI1 LL_SYSCFG_IsActiveFlag_SPI1
AnnaBridge	171:3a7713b1edbc	1397	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1398	*/
AnnaBridge	171:3a7713b1edbc	1399	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI1(void)
AnnaBridge	171:3a7713b1edbc	1400	{
AnnaBridge	171:3a7713b1edbc	1401	return (READ_BIT(SYSCFG->IT_LINE_SR[25], SYSCFG_ITLINE25_SR_SPI1) == (SYSCFG_ITLINE25_SR_SPI1));
AnnaBridge	171:3a7713b1edbc	1402	}
AnnaBridge	171:3a7713b1edbc	1403	#endif /* SYSCFG_ITLINE25_SR_SPI1 */
AnnaBridge	171:3a7713b1edbc	1404
AnnaBridge	171:3a7713b1edbc	1405	#if defined(SYSCFG_ITLINE26_SR_SPI2)
AnnaBridge	171:3a7713b1edbc	1406	/**
AnnaBridge	171:3a7713b1edbc	1407	* @brief Check if SPI2 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1408	* @rmtoll SYSCFG_ITLINE26 SR_SPI2 LL_SYSCFG_IsActiveFlag_SPI2
AnnaBridge	171:3a7713b1edbc	1409	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1410	*/
AnnaBridge	171:3a7713b1edbc	1411	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI2(void)
AnnaBridge	171:3a7713b1edbc	1412	{
AnnaBridge	171:3a7713b1edbc	1413	return (READ_BIT(SYSCFG->IT_LINE_SR[26], SYSCFG_ITLINE26_SR_SPI2) == (SYSCFG_ITLINE26_SR_SPI2));
AnnaBridge	171:3a7713b1edbc	1414	}
AnnaBridge	171:3a7713b1edbc	1415	#endif /* SYSCFG_ITLINE26_SR_SPI2 */
AnnaBridge	171:3a7713b1edbc	1416
AnnaBridge	171:3a7713b1edbc	1417	#if defined(SYSCFG_ITLINE27_SR_USART1_GLB)
AnnaBridge	171:3a7713b1edbc	1418	/**
AnnaBridge	171:3a7713b1edbc	1419	* @brief Check if USART1 interrupt occurred or not, combined with EXTI line 25.
AnnaBridge	171:3a7713b1edbc	1420	* @rmtoll SYSCFG_ITLINE27 SR_USART1_GLB LL_SYSCFG_IsActiveFlag_USART1
AnnaBridge	171:3a7713b1edbc	1421	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1422	*/
AnnaBridge	171:3a7713b1edbc	1423	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART1(void)
AnnaBridge	171:3a7713b1edbc	1424	{
AnnaBridge	171:3a7713b1edbc	1425	return (READ_BIT(SYSCFG->IT_LINE_SR[27], SYSCFG_ITLINE27_SR_USART1_GLB) == (SYSCFG_ITLINE27_SR_USART1_GLB));
AnnaBridge	171:3a7713b1edbc	1426	}
AnnaBridge	171:3a7713b1edbc	1427	#endif /* SYSCFG_ITLINE27_SR_USART1_GLB */
AnnaBridge	171:3a7713b1edbc	1428
AnnaBridge	171:3a7713b1edbc	1429	#if defined(SYSCFG_ITLINE28_SR_USART2_GLB)
AnnaBridge	171:3a7713b1edbc	1430	/**
AnnaBridge	171:3a7713b1edbc	1431	* @brief Check if USART2 interrupt occurred or not, combined with EXTI line 26.
AnnaBridge	171:3a7713b1edbc	1432	* @rmtoll SYSCFG_ITLINE28 SR_USART2_GLB LL_SYSCFG_IsActiveFlag_USART2
AnnaBridge	171:3a7713b1edbc	1433	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1434	*/
AnnaBridge	171:3a7713b1edbc	1435	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART2(void)
AnnaBridge	171:3a7713b1edbc	1436	{
AnnaBridge	171:3a7713b1edbc	1437	return (READ_BIT(SYSCFG->IT_LINE_SR[28], SYSCFG_ITLINE28_SR_USART2_GLB) == (SYSCFG_ITLINE28_SR_USART2_GLB));
AnnaBridge	171:3a7713b1edbc	1438	}
AnnaBridge	171:3a7713b1edbc	1439	#endif /* SYSCFG_ITLINE28_SR_USART2_GLB */
AnnaBridge	171:3a7713b1edbc	1440
AnnaBridge	171:3a7713b1edbc	1441	#if defined(SYSCFG_ITLINE29_SR_USART3_GLB)
AnnaBridge	171:3a7713b1edbc	1442	/**
AnnaBridge	171:3a7713b1edbc	1443	* @brief Check if USART3 interrupt occurred or not, combined with EXTI line 28.
AnnaBridge	171:3a7713b1edbc	1444	* @rmtoll SYSCFG_ITLINE29 SR_USART3_GLB LL_SYSCFG_IsActiveFlag_USART3
AnnaBridge	171:3a7713b1edbc	1445	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1446	*/
AnnaBridge	171:3a7713b1edbc	1447	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART3(void)
AnnaBridge	171:3a7713b1edbc	1448	{
AnnaBridge	171:3a7713b1edbc	1449	return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART3_GLB) == (SYSCFG_ITLINE29_SR_USART3_GLB));
AnnaBridge	171:3a7713b1edbc	1450	}
AnnaBridge	171:3a7713b1edbc	1451	#endif /* SYSCFG_ITLINE29_SR_USART3_GLB */
AnnaBridge	171:3a7713b1edbc	1452
AnnaBridge	171:3a7713b1edbc	1453	#if defined(SYSCFG_ITLINE29_SR_USART4_GLB)
AnnaBridge	171:3a7713b1edbc	1454	/**
AnnaBridge	171:3a7713b1edbc	1455	* @brief Check if USART4 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1456	* @rmtoll SYSCFG_ITLINE29 SR_USART4_GLB LL_SYSCFG_IsActiveFlag_USART4
AnnaBridge	171:3a7713b1edbc	1457	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1458	*/
AnnaBridge	171:3a7713b1edbc	1459	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART4(void)
AnnaBridge	171:3a7713b1edbc	1460	{
AnnaBridge	171:3a7713b1edbc	1461	return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART4_GLB) == (SYSCFG_ITLINE29_SR_USART4_GLB));
AnnaBridge	171:3a7713b1edbc	1462	}
AnnaBridge	171:3a7713b1edbc	1463	#endif /* SYSCFG_ITLINE29_SR_USART4_GLB */
AnnaBridge	171:3a7713b1edbc	1464
AnnaBridge	171:3a7713b1edbc	1465	#if defined(SYSCFG_ITLINE29_SR_USART5_GLB)
AnnaBridge	171:3a7713b1edbc	1466	/**
AnnaBridge	171:3a7713b1edbc	1467	* @brief Check if USART5 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1468	* @rmtoll SYSCFG_ITLINE29 SR_USART5_GLB LL_SYSCFG_IsActiveFlag_USART5
AnnaBridge	171:3a7713b1edbc	1469	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1470	*/
AnnaBridge	171:3a7713b1edbc	1471	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART5(void)
AnnaBridge	171:3a7713b1edbc	1472	{
AnnaBridge	171:3a7713b1edbc	1473	return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART5_GLB) == (SYSCFG_ITLINE29_SR_USART5_GLB));
AnnaBridge	171:3a7713b1edbc	1474	}
AnnaBridge	171:3a7713b1edbc	1475	#endif /* SYSCFG_ITLINE29_SR_USART5_GLB */
AnnaBridge	171:3a7713b1edbc	1476
AnnaBridge	171:3a7713b1edbc	1477	#if defined(SYSCFG_ITLINE29_SR_USART6_GLB)
AnnaBridge	171:3a7713b1edbc	1478	/**
AnnaBridge	171:3a7713b1edbc	1479	* @brief Check if USART6 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1480	* @rmtoll SYSCFG_ITLINE29 SR_USART6_GLB LL_SYSCFG_IsActiveFlag_USART6
AnnaBridge	171:3a7713b1edbc	1481	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1482	*/
AnnaBridge	171:3a7713b1edbc	1483	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART6(void)
AnnaBridge	171:3a7713b1edbc	1484	{
AnnaBridge	171:3a7713b1edbc	1485	return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART6_GLB) == (SYSCFG_ITLINE29_SR_USART6_GLB));
AnnaBridge	171:3a7713b1edbc	1486	}
AnnaBridge	171:3a7713b1edbc	1487	#endif /* SYSCFG_ITLINE29_SR_USART6_GLB */
AnnaBridge	171:3a7713b1edbc	1488
AnnaBridge	171:3a7713b1edbc	1489	#if defined(SYSCFG_ITLINE29_SR_USART7_GLB)
AnnaBridge	171:3a7713b1edbc	1490	/**
AnnaBridge	171:3a7713b1edbc	1491	* @brief Check if USART7 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1492	* @rmtoll SYSCFG_ITLINE29 SR_USART7_GLB LL_SYSCFG_IsActiveFlag_USART7
AnnaBridge	171:3a7713b1edbc	1493	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1494	*/
AnnaBridge	171:3a7713b1edbc	1495	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART7(void)
AnnaBridge	171:3a7713b1edbc	1496	{
AnnaBridge	171:3a7713b1edbc	1497	return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART7_GLB) == (SYSCFG_ITLINE29_SR_USART7_GLB));
AnnaBridge	171:3a7713b1edbc	1498	}
AnnaBridge	171:3a7713b1edbc	1499	#endif /* SYSCFG_ITLINE29_SR_USART7_GLB */
AnnaBridge	171:3a7713b1edbc	1500
AnnaBridge	171:3a7713b1edbc	1501	#if defined(SYSCFG_ITLINE29_SR_USART8_GLB)
AnnaBridge	171:3a7713b1edbc	1502	/**
AnnaBridge	171:3a7713b1edbc	1503	* @brief Check if USART8 interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1504	* @rmtoll SYSCFG_ITLINE29 SR_USART8_GLB LL_SYSCFG_IsActiveFlag_USART8
AnnaBridge	171:3a7713b1edbc	1505	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1506	*/
AnnaBridge	171:3a7713b1edbc	1507	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART8(void)
AnnaBridge	171:3a7713b1edbc	1508	{
AnnaBridge	171:3a7713b1edbc	1509	return (READ_BIT(SYSCFG->IT_LINE_SR[29], SYSCFG_ITLINE29_SR_USART8_GLB) == (SYSCFG_ITLINE29_SR_USART8_GLB));
AnnaBridge	171:3a7713b1edbc	1510	}
AnnaBridge	171:3a7713b1edbc	1511	#endif /* SYSCFG_ITLINE29_SR_USART8_GLB */
AnnaBridge	171:3a7713b1edbc	1512
AnnaBridge	171:3a7713b1edbc	1513	#if defined(SYSCFG_ITLINE30_SR_CAN)
AnnaBridge	171:3a7713b1edbc	1514	/**
AnnaBridge	171:3a7713b1edbc	1515	* @brief Check if CAN interrupt occurred or not.
AnnaBridge	171:3a7713b1edbc	1516	* @rmtoll SYSCFG_ITLINE30 SR_CAN LL_SYSCFG_IsActiveFlag_CAN
AnnaBridge	171:3a7713b1edbc	1517	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1518	*/
AnnaBridge	171:3a7713b1edbc	1519	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CAN(void)
AnnaBridge	171:3a7713b1edbc	1520	{
AnnaBridge	171:3a7713b1edbc	1521	return (READ_BIT(SYSCFG->IT_LINE_SR[30], SYSCFG_ITLINE30_SR_CAN) == (SYSCFG_ITLINE30_SR_CAN));
AnnaBridge	171:3a7713b1edbc	1522	}
AnnaBridge	171:3a7713b1edbc	1523	#endif /* SYSCFG_ITLINE30_SR_CAN */
AnnaBridge	171:3a7713b1edbc	1524
AnnaBridge	171:3a7713b1edbc	1525	#if defined(SYSCFG_ITLINE30_SR_CEC)
AnnaBridge	171:3a7713b1edbc	1526	/**
AnnaBridge	171:3a7713b1edbc	1527	* @brief Check if CEC interrupt occurred or not, combined with EXTI line 27.
AnnaBridge	171:3a7713b1edbc	1528	* @rmtoll SYSCFG_ITLINE30 SR_CEC LL_SYSCFG_IsActiveFlag_CEC
AnnaBridge	171:3a7713b1edbc	1529	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1530	*/
AnnaBridge	171:3a7713b1edbc	1531	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CEC(void)
AnnaBridge	171:3a7713b1edbc	1532	{
AnnaBridge	171:3a7713b1edbc	1533	return (READ_BIT(SYSCFG->IT_LINE_SR[30], SYSCFG_ITLINE30_SR_CEC) == (SYSCFG_ITLINE30_SR_CEC));
AnnaBridge	171:3a7713b1edbc	1534	}
AnnaBridge	171:3a7713b1edbc	1535	#endif /* SYSCFG_ITLINE30_SR_CEC */
AnnaBridge	171:3a7713b1edbc	1536
AnnaBridge	171:3a7713b1edbc	1537	/**
AnnaBridge	171:3a7713b1edbc	1538	* @brief Set connections to TIMx Break inputs
AnnaBridge	171:3a7713b1edbc	1539	* @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_SetTIMBreakInputs\n
AnnaBridge	171:3a7713b1edbc	1540	* SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_SetTIMBreakInputs\n
AnnaBridge	171:3a7713b1edbc	1541	* SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_SetTIMBreakInputs
AnnaBridge	171:3a7713b1edbc	1542	* @param Break This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	1543	* @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
AnnaBridge	171:3a7713b1edbc	1544	* @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY
AnnaBridge	171:3a7713b1edbc	1545	* @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
AnnaBridge	171:3a7713b1edbc	1546	*
AnnaBridge	171:3a7713b1edbc	1547	* (*) value not defined in all devices
AnnaBridge	171:3a7713b1edbc	1548	* @retval None
AnnaBridge	171:3a7713b1edbc	1549	*/
AnnaBridge	171:3a7713b1edbc	1550	__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
AnnaBridge	171:3a7713b1edbc	1551	{
AnnaBridge	171:3a7713b1edbc	1552	#if defined(SYSCFG_CFGR2_PVD_LOCK)
AnnaBridge	171:3a7713b1edbc	1553	MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK \| SYSCFG_CFGR2_SRAM_PARITY_LOCK \| SYSCFG_CFGR2_PVD_LOCK, Break);
AnnaBridge	171:3a7713b1edbc	1554	#else
AnnaBridge	171:3a7713b1edbc	1555	MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK \| SYSCFG_CFGR2_SRAM_PARITY_LOCK, Break);
AnnaBridge	171:3a7713b1edbc	1556	#endif /SYSCFG_CFGR2_PVD_LOCK/
AnnaBridge	171:3a7713b1edbc	1557	}
AnnaBridge	171:3a7713b1edbc	1558
AnnaBridge	171:3a7713b1edbc	1559	/**
AnnaBridge	171:3a7713b1edbc	1560	* @brief Get connections to TIMx Break inputs
AnnaBridge	171:3a7713b1edbc	1561	* @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_GetTIMBreakInputs\n
AnnaBridge	171:3a7713b1edbc	1562	* SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_GetTIMBreakInputs\n
AnnaBridge	171:3a7713b1edbc	1563	* SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_GetTIMBreakInputs
AnnaBridge	171:3a7713b1edbc	1564	* @retval Returned value can be can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	1565	* @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
AnnaBridge	171:3a7713b1edbc	1566	* @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY
AnnaBridge	171:3a7713b1edbc	1567	* @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
AnnaBridge	171:3a7713b1edbc	1568	*
AnnaBridge	171:3a7713b1edbc	1569	* (*) value not defined in all devices
AnnaBridge	171:3a7713b1edbc	1570	*/
AnnaBridge	171:3a7713b1edbc	1571	__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
AnnaBridge	171:3a7713b1edbc	1572	{
AnnaBridge	171:3a7713b1edbc	1573	#if defined(SYSCFG_CFGR2_PVD_LOCK)
AnnaBridge	171:3a7713b1edbc	1574	return (uint32_t)(READ_BIT(SYSCFG->CFGR2,
AnnaBridge	171:3a7713b1edbc	1575	SYSCFG_CFGR2_LOCKUP_LOCK \| SYSCFG_CFGR2_SRAM_PARITY_LOCK \| SYSCFG_CFGR2_PVD_LOCK));
AnnaBridge	171:3a7713b1edbc	1576	#else
AnnaBridge	171:3a7713b1edbc	1577	return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK \| SYSCFG_CFGR2_SRAM_PARITY_LOCK));
AnnaBridge	171:3a7713b1edbc	1578	#endif /SYSCFG_CFGR2_PVD_LOCK/
AnnaBridge	171:3a7713b1edbc	1579	}
AnnaBridge	171:3a7713b1edbc	1580
AnnaBridge	171:3a7713b1edbc	1581	/**
AnnaBridge	171:3a7713b1edbc	1582	* @brief Check if SRAM parity error detected
AnnaBridge	171:3a7713b1edbc	1583	* @rmtoll SYSCFG_CFGR2 SRAM_PEF LL_SYSCFG_IsActiveFlag_SP
AnnaBridge	171:3a7713b1edbc	1584	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1585	*/
AnnaBridge	171:3a7713b1edbc	1586	__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
AnnaBridge	171:3a7713b1edbc	1587	{
AnnaBridge	171:3a7713b1edbc	1588	return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PEF) == (SYSCFG_CFGR2_SRAM_PEF));
AnnaBridge	171:3a7713b1edbc	1589	}
AnnaBridge	171:3a7713b1edbc	1590
AnnaBridge	171:3a7713b1edbc	1591	/**
AnnaBridge	171:3a7713b1edbc	1592	* @brief Clear SRAM parity error flag
AnnaBridge	171:3a7713b1edbc	1593	* @rmtoll SYSCFG_CFGR2 SRAM_PEF LL_SYSCFG_ClearFlag_SP
AnnaBridge	171:3a7713b1edbc	1594	* @retval None
AnnaBridge	171:3a7713b1edbc	1595	*/
AnnaBridge	171:3a7713b1edbc	1596	__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
AnnaBridge	171:3a7713b1edbc	1597	{
AnnaBridge	171:3a7713b1edbc	1598	SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PEF);
AnnaBridge	171:3a7713b1edbc	1599	}
AnnaBridge	171:3a7713b1edbc	1600
AnnaBridge	171:3a7713b1edbc	1601	/**
AnnaBridge	171:3a7713b1edbc	1602	* @}
AnnaBridge	171:3a7713b1edbc	1603	*/
AnnaBridge	171:3a7713b1edbc	1604
AnnaBridge	171:3a7713b1edbc	1605	/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
AnnaBridge	171:3a7713b1edbc	1606	* @{
AnnaBridge	171:3a7713b1edbc	1607	*/
AnnaBridge	171:3a7713b1edbc	1608
AnnaBridge	171:3a7713b1edbc	1609	/**
AnnaBridge	171:3a7713b1edbc	1610	* @brief Return the device identifier
AnnaBridge	171:3a7713b1edbc	1611	* @note For STM32F03x devices, the device ID is 0x444
AnnaBridge	171:3a7713b1edbc	1612	* @note For STM32F04x devices, the device ID is 0x445.
AnnaBridge	171:3a7713b1edbc	1613	* @note For STM32F05x devices, the device ID is 0x440
AnnaBridge	171:3a7713b1edbc	1614	* @note For STM32F07x devices, the device ID is 0x448
AnnaBridge	171:3a7713b1edbc	1615	* @note For STM32F09x devices, the device ID is 0x442
AnnaBridge	171:3a7713b1edbc	1616	* @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
AnnaBridge	171:3a7713b1edbc	1617	* @retval Values between Min_Data=0x00 and Max_Data=0xFFF
AnnaBridge	171:3a7713b1edbc	1618	*/
AnnaBridge	171:3a7713b1edbc	1619	__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
AnnaBridge	171:3a7713b1edbc	1620	{
AnnaBridge	171:3a7713b1edbc	1621	return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
AnnaBridge	171:3a7713b1edbc	1622	}
AnnaBridge	171:3a7713b1edbc	1623
AnnaBridge	171:3a7713b1edbc	1624	/**
AnnaBridge	171:3a7713b1edbc	1625	* @brief Return the device revision identifier
AnnaBridge	171:3a7713b1edbc	1626	* @note This field indicates the revision of the device.
AnnaBridge	171:3a7713b1edbc	1627	For example, it is read as 0x1000 for Revision 1.0.
AnnaBridge	171:3a7713b1edbc	1628	* @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
AnnaBridge	171:3a7713b1edbc	1629	* @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
AnnaBridge	171:3a7713b1edbc	1630	*/
AnnaBridge	171:3a7713b1edbc	1631	__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
AnnaBridge	171:3a7713b1edbc	1632	{
AnnaBridge	171:3a7713b1edbc	1633	return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
AnnaBridge	171:3a7713b1edbc	1634	}
AnnaBridge	171:3a7713b1edbc	1635
AnnaBridge	171:3a7713b1edbc	1636	/**
AnnaBridge	171:3a7713b1edbc	1637	* @brief Enable the Debug Module during STOP mode
AnnaBridge	171:3a7713b1edbc	1638	* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
AnnaBridge	171:3a7713b1edbc	1639	* @retval None
AnnaBridge	171:3a7713b1edbc	1640	*/
AnnaBridge	171:3a7713b1edbc	1641	__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
AnnaBridge	171:3a7713b1edbc	1642	{
AnnaBridge	171:3a7713b1edbc	1643	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
AnnaBridge	171:3a7713b1edbc	1644	}
AnnaBridge	171:3a7713b1edbc	1645
AnnaBridge	171:3a7713b1edbc	1646	/**
AnnaBridge	171:3a7713b1edbc	1647	* @brief Disable the Debug Module during STOP mode
AnnaBridge	171:3a7713b1edbc	1648	* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
AnnaBridge	171:3a7713b1edbc	1649	* @retval None
AnnaBridge	171:3a7713b1edbc	1650	*/
AnnaBridge	171:3a7713b1edbc	1651	__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
AnnaBridge	171:3a7713b1edbc	1652	{
AnnaBridge	171:3a7713b1edbc	1653	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
AnnaBridge	171:3a7713b1edbc	1654	}
AnnaBridge	171:3a7713b1edbc	1655
AnnaBridge	171:3a7713b1edbc	1656	/**
AnnaBridge	171:3a7713b1edbc	1657	* @brief Enable the Debug Module during STANDBY mode
AnnaBridge	171:3a7713b1edbc	1658	* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
AnnaBridge	171:3a7713b1edbc	1659	* @retval None
AnnaBridge	171:3a7713b1edbc	1660	*/
AnnaBridge	171:3a7713b1edbc	1661	__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
AnnaBridge	171:3a7713b1edbc	1662	{
AnnaBridge	171:3a7713b1edbc	1663	SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
AnnaBridge	171:3a7713b1edbc	1664	}
AnnaBridge	171:3a7713b1edbc	1665
AnnaBridge	171:3a7713b1edbc	1666	/**
AnnaBridge	171:3a7713b1edbc	1667	* @brief Disable the Debug Module during STANDBY mode
AnnaBridge	171:3a7713b1edbc	1668	* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
AnnaBridge	171:3a7713b1edbc	1669	* @retval None
AnnaBridge	171:3a7713b1edbc	1670	*/
AnnaBridge	171:3a7713b1edbc	1671	__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
AnnaBridge	171:3a7713b1edbc	1672	{
AnnaBridge	171:3a7713b1edbc	1673	CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
AnnaBridge	171:3a7713b1edbc	1674	}
AnnaBridge	171:3a7713b1edbc	1675
AnnaBridge	171:3a7713b1edbc	1676	/**
AnnaBridge	171:3a7713b1edbc	1677	* @brief Freeze APB1 peripherals (group1 peripherals)
AnnaBridge	171:3a7713b1edbc	1678	* @rmtoll DBGMCU_APB1FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	171:3a7713b1edbc	1679	* DBGMCU_APB1FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	171:3a7713b1edbc	1680	* DBGMCU_APB1FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	171:3a7713b1edbc	1681	* DBGMCU_APB1FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	171:3a7713b1edbc	1682	* DBGMCU_APB1FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	171:3a7713b1edbc	1683	* DBGMCU_APB1FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	171:3a7713b1edbc	1684	* DBGMCU_APB1FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	171:3a7713b1edbc	1685	* DBGMCU_APB1FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	171:3a7713b1edbc	1686	* DBGMCU_APB1FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
AnnaBridge	171:3a7713b1edbc	1687	* DBGMCU_APB1FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
AnnaBridge	171:3a7713b1edbc	1688	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	1689	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
AnnaBridge	171:3a7713b1edbc	1690	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
AnnaBridge	171:3a7713b1edbc	1691	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
AnnaBridge	171:3a7713b1edbc	1692	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
AnnaBridge	171:3a7713b1edbc	1693	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
AnnaBridge	171:3a7713b1edbc	1694	* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
AnnaBridge	171:3a7713b1edbc	1695	* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
AnnaBridge	171:3a7713b1edbc	1696	* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
AnnaBridge	171:3a7713b1edbc	1697	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
AnnaBridge	171:3a7713b1edbc	1698	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*)
AnnaBridge	171:3a7713b1edbc	1699	*
AnnaBridge	171:3a7713b1edbc	1700	* (*) value not defined in all devices
AnnaBridge	171:3a7713b1edbc	1701	* @retval None
AnnaBridge	171:3a7713b1edbc	1702	*/
AnnaBridge	171:3a7713b1edbc	1703	__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
AnnaBridge	171:3a7713b1edbc	1704	{
AnnaBridge	171:3a7713b1edbc	1705	SET_BIT(DBGMCU->APB1FZ, Periphs);
AnnaBridge	171:3a7713b1edbc	1706	}
AnnaBridge	171:3a7713b1edbc	1707
AnnaBridge	171:3a7713b1edbc	1708	/**
AnnaBridge	171:3a7713b1edbc	1709	* @brief Unfreeze APB1 peripherals (group1 peripherals)
AnnaBridge	171:3a7713b1edbc	1710	* @rmtoll DBGMCU_APB1FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	171:3a7713b1edbc	1711	* DBGMCU_APB1FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	171:3a7713b1edbc	1712	* DBGMCU_APB1FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	171:3a7713b1edbc	1713	* DBGMCU_APB1FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	171:3a7713b1edbc	1714	* DBGMCU_APB1FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	171:3a7713b1edbc	1715	* DBGMCU_APB1FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	171:3a7713b1edbc	1716	* DBGMCU_APB1FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	171:3a7713b1edbc	1717	* DBGMCU_APB1FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	171:3a7713b1edbc	1718	* DBGMCU_APB1FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
AnnaBridge	171:3a7713b1edbc	1719	* DBGMCU_APB1FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
AnnaBridge	171:3a7713b1edbc	1720	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	1721	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
AnnaBridge	171:3a7713b1edbc	1722	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
AnnaBridge	171:3a7713b1edbc	1723	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
AnnaBridge	171:3a7713b1edbc	1724	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
AnnaBridge	171:3a7713b1edbc	1725	* @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
AnnaBridge	171:3a7713b1edbc	1726	* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
AnnaBridge	171:3a7713b1edbc	1727	* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
AnnaBridge	171:3a7713b1edbc	1728	* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
AnnaBridge	171:3a7713b1edbc	1729	* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
AnnaBridge	171:3a7713b1edbc	1730	* @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*)
AnnaBridge	171:3a7713b1edbc	1731	*
AnnaBridge	171:3a7713b1edbc	1732	* (*) value not defined in all devices
AnnaBridge	171:3a7713b1edbc	1733	* @retval None
AnnaBridge	171:3a7713b1edbc	1734	*/
AnnaBridge	171:3a7713b1edbc	1735	__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
AnnaBridge	171:3a7713b1edbc	1736	{
AnnaBridge	171:3a7713b1edbc	1737	CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
AnnaBridge	171:3a7713b1edbc	1738	}
AnnaBridge	171:3a7713b1edbc	1739
AnnaBridge	171:3a7713b1edbc	1740	/**
AnnaBridge	171:3a7713b1edbc	1741	* @brief Freeze APB1 peripherals (group2 peripherals)
AnnaBridge	171:3a7713b1edbc	1742	* @rmtoll DBGMCU_APB2FZ DBG_TIM1_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n
AnnaBridge	171:3a7713b1edbc	1743	* DBGMCU_APB2FZ DBG_TIM15_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n
AnnaBridge	171:3a7713b1edbc	1744	* DBGMCU_APB2FZ DBG_TIM16_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph\n
AnnaBridge	171:3a7713b1edbc	1745	* DBGMCU_APB2FZ DBG_TIM17_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
AnnaBridge	171:3a7713b1edbc	1746	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	1747	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP
AnnaBridge	171:3a7713b1edbc	1748	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM15_STOP (*)
AnnaBridge	171:3a7713b1edbc	1749	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP
AnnaBridge	171:3a7713b1edbc	1750	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP
AnnaBridge	171:3a7713b1edbc	1751	*
AnnaBridge	171:3a7713b1edbc	1752	* (*) value not defined in all devices
AnnaBridge	171:3a7713b1edbc	1753	* @retval None
AnnaBridge	171:3a7713b1edbc	1754	*/
AnnaBridge	171:3a7713b1edbc	1755	__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
AnnaBridge	171:3a7713b1edbc	1756	{
AnnaBridge	171:3a7713b1edbc	1757	SET_BIT(DBGMCU->APB2FZ, Periphs);
AnnaBridge	171:3a7713b1edbc	1758	}
AnnaBridge	171:3a7713b1edbc	1759
AnnaBridge	171:3a7713b1edbc	1760	/**
AnnaBridge	171:3a7713b1edbc	1761	* @brief Unfreeze APB1 peripherals (group2 peripherals)
AnnaBridge	171:3a7713b1edbc	1762	* @rmtoll DBGMCU_APB2FZ DBG_TIM1_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
AnnaBridge	171:3a7713b1edbc	1763	* DBGMCU_APB2FZ DBG_TIM15_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
AnnaBridge	171:3a7713b1edbc	1764	* DBGMCU_APB2FZ DBG_TIM16_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n
AnnaBridge	171:3a7713b1edbc	1765	* DBGMCU_APB2FZ DBG_TIM17_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph
AnnaBridge	171:3a7713b1edbc	1766	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	171:3a7713b1edbc	1767	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP
AnnaBridge	171:3a7713b1edbc	1768	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM15_STOP (*)
AnnaBridge	171:3a7713b1edbc	1769	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP
AnnaBridge	171:3a7713b1edbc	1770	* @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP
AnnaBridge	171:3a7713b1edbc	1771	*
AnnaBridge	171:3a7713b1edbc	1772	* (*) value not defined in all devices
AnnaBridge	171:3a7713b1edbc	1773	* @retval None
AnnaBridge	171:3a7713b1edbc	1774	*/
AnnaBridge	171:3a7713b1edbc	1775	__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
AnnaBridge	171:3a7713b1edbc	1776	{
AnnaBridge	171:3a7713b1edbc	1777	CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
AnnaBridge	171:3a7713b1edbc	1778	}
AnnaBridge	171:3a7713b1edbc	1779	/**
AnnaBridge	171:3a7713b1edbc	1780	* @}
AnnaBridge	171:3a7713b1edbc	1781	*/
AnnaBridge	171:3a7713b1edbc	1782
AnnaBridge	171:3a7713b1edbc	1783	/** @defgroup SYSTEM_LL_EF_FLASH FLASH
AnnaBridge	171:3a7713b1edbc	1784	* @{
AnnaBridge	171:3a7713b1edbc	1785	*/
AnnaBridge	171:3a7713b1edbc	1786
AnnaBridge	171:3a7713b1edbc	1787	/**
AnnaBridge	171:3a7713b1edbc	1788	* @brief Set FLASH Latency
AnnaBridge	171:3a7713b1edbc	1789	* @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
AnnaBridge	171:3a7713b1edbc	1790	* @param Latency This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1791	* @arg @ref LL_FLASH_LATENCY_0
AnnaBridge	171:3a7713b1edbc	1792	* @arg @ref LL_FLASH_LATENCY_1
AnnaBridge	171:3a7713b1edbc	1793	* @retval None
AnnaBridge	171:3a7713b1edbc	1794	*/
AnnaBridge	171:3a7713b1edbc	1795	__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
AnnaBridge	171:3a7713b1edbc	1796	{
AnnaBridge	171:3a7713b1edbc	1797	MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
AnnaBridge	171:3a7713b1edbc	1798	}
AnnaBridge	171:3a7713b1edbc	1799
AnnaBridge	171:3a7713b1edbc	1800	/**
AnnaBridge	171:3a7713b1edbc	1801	* @brief Get FLASH Latency
AnnaBridge	171:3a7713b1edbc	1802	* @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
AnnaBridge	171:3a7713b1edbc	1803	* @retval Returned value can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1804	* @arg @ref LL_FLASH_LATENCY_0
AnnaBridge	171:3a7713b1edbc	1805	* @arg @ref LL_FLASH_LATENCY_1
AnnaBridge	171:3a7713b1edbc	1806	*/
AnnaBridge	171:3a7713b1edbc	1807	__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
AnnaBridge	171:3a7713b1edbc	1808	{
AnnaBridge	171:3a7713b1edbc	1809	return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
AnnaBridge	171:3a7713b1edbc	1810	}
AnnaBridge	171:3a7713b1edbc	1811
AnnaBridge	171:3a7713b1edbc	1812	/**
AnnaBridge	171:3a7713b1edbc	1813	* @brief Enable Prefetch
AnnaBridge	171:3a7713b1edbc	1814	* @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch
AnnaBridge	171:3a7713b1edbc	1815	* @retval None
AnnaBridge	171:3a7713b1edbc	1816	*/
AnnaBridge	171:3a7713b1edbc	1817	__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
AnnaBridge	171:3a7713b1edbc	1818	{
AnnaBridge	171:3a7713b1edbc	1819	SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
AnnaBridge	171:3a7713b1edbc	1820	}
AnnaBridge	171:3a7713b1edbc	1821
AnnaBridge	171:3a7713b1edbc	1822	/**
AnnaBridge	171:3a7713b1edbc	1823	* @brief Disable Prefetch
AnnaBridge	171:3a7713b1edbc	1824	* @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch
AnnaBridge	171:3a7713b1edbc	1825	* @retval None
AnnaBridge	171:3a7713b1edbc	1826	*/
AnnaBridge	171:3a7713b1edbc	1827	__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
AnnaBridge	171:3a7713b1edbc	1828	{
AnnaBridge	171:3a7713b1edbc	1829	CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE);
AnnaBridge	171:3a7713b1edbc	1830	}
AnnaBridge	171:3a7713b1edbc	1831
AnnaBridge	171:3a7713b1edbc	1832	/**
AnnaBridge	171:3a7713b1edbc	1833	* @brief Check if Prefetch buffer is enabled
AnnaBridge	171:3a7713b1edbc	1834	* @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled
AnnaBridge	171:3a7713b1edbc	1835	* @retval State of bit (1 or 0).
AnnaBridge	171:3a7713b1edbc	1836	*/
AnnaBridge	171:3a7713b1edbc	1837	__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
AnnaBridge	171:3a7713b1edbc	1838	{
AnnaBridge	171:3a7713b1edbc	1839	return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS));
AnnaBridge	171:3a7713b1edbc	1840	}
AnnaBridge	171:3a7713b1edbc	1841
AnnaBridge	171:3a7713b1edbc	1842
AnnaBridge	171:3a7713b1edbc	1843
AnnaBridge	171:3a7713b1edbc	1844	/**
AnnaBridge	171:3a7713b1edbc	1845	* @}
AnnaBridge	171:3a7713b1edbc	1846	*/
AnnaBridge	171:3a7713b1edbc	1847
AnnaBridge	171:3a7713b1edbc	1848	/**
AnnaBridge	171:3a7713b1edbc	1849	* @}
AnnaBridge	171:3a7713b1edbc	1850	*/
AnnaBridge	171:3a7713b1edbc	1851
AnnaBridge	171:3a7713b1edbc	1852	/**
AnnaBridge	171:3a7713b1edbc	1853	* @}
AnnaBridge	171:3a7713b1edbc	1854	*/
AnnaBridge	171:3a7713b1edbc	1855
AnnaBridge	171:3a7713b1edbc	1856	#endif /* defined (FLASH) \|\| defined (SYSCFG) \|\| defined (DBGMCU) */
AnnaBridge	171:3a7713b1edbc	1857
AnnaBridge	171:3a7713b1edbc	1858	/**
AnnaBridge	171:3a7713b1edbc	1859	* @}
AnnaBridge	171:3a7713b1edbc	1860	*/
AnnaBridge	171:3a7713b1edbc	1861
AnnaBridge	171:3a7713b1edbc	1862	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	1863	}
AnnaBridge	171:3a7713b1edbc	1864	#endif
AnnaBridge	171:3a7713b1edbc	1865
AnnaBridge	171:3a7713b1edbc	1866	#endif /* __STM32F0xx_LL_SYSTEM_H */
AnnaBridge	171:3a7713b1edbc	1867
AnnaBridge	171:3a7713b1edbc	1868	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/