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TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/stm32f0xx_hal_usart.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file stm32f0xx_hal_usart.h
AnnaBridge 171:3a7713b1edbc 4 * @author MCD Application Team
AnnaBridge 171:3a7713b1edbc 5 * @brief Header file of USART HAL module.
AnnaBridge 171:3a7713b1edbc 6 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 7 * @attention
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 12 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 14 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 17 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 171:3a7713b1edbc 19 * may be used to endorse or promote products derived from this software
AnnaBridge 171:3a7713b1edbc 20 * without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 171:3a7713b1edbc 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 171:3a7713b1edbc 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 171:3a7713b1edbc 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 171:3a7713b1edbc 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 171:3a7713b1edbc 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 171:3a7713b1edbc 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 171:3a7713b1edbc 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 32 *
AnnaBridge 171:3a7713b1edbc 33 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 34 */
AnnaBridge 171:3a7713b1edbc 35
AnnaBridge 171:3a7713b1edbc 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 171:3a7713b1edbc 37 #ifndef __STM32F0xx_HAL_USART_H
AnnaBridge 171:3a7713b1edbc 38 #define __STM32F0xx_HAL_USART_H
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 41 extern "C" {
AnnaBridge 171:3a7713b1edbc 42 #endif
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 /* Includes ------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 45 #include "stm32f0xx_hal_def.h"
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /** @addtogroup STM32F0xx_HAL_Driver
AnnaBridge 171:3a7713b1edbc 48 * @{
AnnaBridge 171:3a7713b1edbc 49 */
AnnaBridge 171:3a7713b1edbc 50
AnnaBridge 171:3a7713b1edbc 51 /** @addtogroup USART
AnnaBridge 171:3a7713b1edbc 52 * @{
AnnaBridge 171:3a7713b1edbc 53 */
AnnaBridge 171:3a7713b1edbc 54
AnnaBridge 171:3a7713b1edbc 55 /* Exported types ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 56 /** @defgroup USART_Exported_Types USART Exported Types
AnnaBridge 171:3a7713b1edbc 57 * @{
AnnaBridge 171:3a7713b1edbc 58 */
AnnaBridge 171:3a7713b1edbc 59
AnnaBridge 171:3a7713b1edbc 60 /**
AnnaBridge 171:3a7713b1edbc 61 * @brief USART Init Structure definition
AnnaBridge 171:3a7713b1edbc 62 */
AnnaBridge 171:3a7713b1edbc 63 typedef struct
AnnaBridge 171:3a7713b1edbc 64 {
AnnaBridge 171:3a7713b1edbc 65 uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
AnnaBridge 171:3a7713b1edbc 66 The baud rate is computed using the following formula:
AnnaBridge 171:3a7713b1edbc 67 Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate))). */
AnnaBridge 171:3a7713b1edbc 68
AnnaBridge 171:3a7713b1edbc 69 uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
AnnaBridge 171:3a7713b1edbc 70 This parameter can be a value of @ref USARTEx_Word_Length. */
AnnaBridge 171:3a7713b1edbc 71
AnnaBridge 171:3a7713b1edbc 72 uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
AnnaBridge 171:3a7713b1edbc 73 This parameter can be a value of @ref USART_Stop_Bits. */
AnnaBridge 171:3a7713b1edbc 74
AnnaBridge 171:3a7713b1edbc 75 uint32_t Parity; /*!< Specifies the parity mode.
AnnaBridge 171:3a7713b1edbc 76 This parameter can be a value of @ref USART_Parity
AnnaBridge 171:3a7713b1edbc 77 @note When parity is enabled, the computed parity is inserted
AnnaBridge 171:3a7713b1edbc 78 at the MSB position of the transmitted data (9th bit when
AnnaBridge 171:3a7713b1edbc 79 the word length is set to 9 data bits; 8th bit when the
AnnaBridge 171:3a7713b1edbc 80 word length is set to 8 data bits). */
AnnaBridge 171:3a7713b1edbc 81
AnnaBridge 171:3a7713b1edbc 82 uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
AnnaBridge 171:3a7713b1edbc 83 This parameter can be a value of @ref USART_Mode. */
AnnaBridge 171:3a7713b1edbc 84
AnnaBridge 171:3a7713b1edbc 85 uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
AnnaBridge 171:3a7713b1edbc 86 This parameter can be a value of @ref USART_Clock_Polarity. */
AnnaBridge 171:3a7713b1edbc 87
AnnaBridge 171:3a7713b1edbc 88 uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
AnnaBridge 171:3a7713b1edbc 89 This parameter can be a value of @ref USART_Clock_Phase. */
AnnaBridge 171:3a7713b1edbc 90
AnnaBridge 171:3a7713b1edbc 91 uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
AnnaBridge 171:3a7713b1edbc 92 data bit (MSB) has to be output on the SCLK pin in synchronous mode.
AnnaBridge 171:3a7713b1edbc 93 This parameter can be a value of @ref USART_Last_Bit. */
AnnaBridge 171:3a7713b1edbc 94 }USART_InitTypeDef;
AnnaBridge 171:3a7713b1edbc 95
AnnaBridge 171:3a7713b1edbc 96 /**
AnnaBridge 171:3a7713b1edbc 97 * @brief HAL USART State structures definition
AnnaBridge 171:3a7713b1edbc 98 */
AnnaBridge 171:3a7713b1edbc 99 typedef enum
AnnaBridge 171:3a7713b1edbc 100 {
AnnaBridge 171:3a7713b1edbc 101 HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */
AnnaBridge 171:3a7713b1edbc 102 HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
AnnaBridge 171:3a7713b1edbc 103 HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
AnnaBridge 171:3a7713b1edbc 104 HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
AnnaBridge 171:3a7713b1edbc 105 HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
AnnaBridge 171:3a7713b1edbc 106 HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */
AnnaBridge 171:3a7713b1edbc 107 HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
AnnaBridge 171:3a7713b1edbc 108 HAL_USART_STATE_ERROR = 0x04U /*!< Error */
AnnaBridge 171:3a7713b1edbc 109 }HAL_USART_StateTypeDef;
AnnaBridge 171:3a7713b1edbc 110
AnnaBridge 171:3a7713b1edbc 111 /**
AnnaBridge 171:3a7713b1edbc 112 * @brief USART clock sources definitions
AnnaBridge 171:3a7713b1edbc 113 */
AnnaBridge 171:3a7713b1edbc 114 typedef enum
AnnaBridge 171:3a7713b1edbc 115 {
AnnaBridge 171:3a7713b1edbc 116 USART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
AnnaBridge 171:3a7713b1edbc 117 USART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
AnnaBridge 171:3a7713b1edbc 118 USART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
AnnaBridge 171:3a7713b1edbc 119 USART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
AnnaBridge 171:3a7713b1edbc 120 USART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */
AnnaBridge 171:3a7713b1edbc 121 }USART_ClockSourceTypeDef;
AnnaBridge 171:3a7713b1edbc 122
AnnaBridge 171:3a7713b1edbc 123
AnnaBridge 171:3a7713b1edbc 124 /**
AnnaBridge 171:3a7713b1edbc 125 * @brief USART handle Structure definition
AnnaBridge 171:3a7713b1edbc 126 */
AnnaBridge 171:3a7713b1edbc 127 typedef struct
AnnaBridge 171:3a7713b1edbc 128 {
AnnaBridge 171:3a7713b1edbc 129 USART_TypeDef *Instance; /*!< USART registers base address */
AnnaBridge 171:3a7713b1edbc 130
AnnaBridge 171:3a7713b1edbc 131 USART_InitTypeDef Init; /*!< USART communication parameters */
AnnaBridge 171:3a7713b1edbc 132
AnnaBridge 171:3a7713b1edbc 133 uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */
AnnaBridge 171:3a7713b1edbc 134
AnnaBridge 171:3a7713b1edbc 135 uint16_t TxXferSize; /*!< USART Tx Transfer size */
AnnaBridge 171:3a7713b1edbc 136
AnnaBridge 171:3a7713b1edbc 137 __IO uint16_t TxXferCount; /*!< USART Tx Transfer Counter */
AnnaBridge 171:3a7713b1edbc 138
AnnaBridge 171:3a7713b1edbc 139 uint8_t *pRxBuffPtr; /*!< Pointer to USART Rx transfer Buffer */
AnnaBridge 171:3a7713b1edbc 140
AnnaBridge 171:3a7713b1edbc 141 uint16_t RxXferSize; /*!< USART Rx Transfer size */
AnnaBridge 171:3a7713b1edbc 142
AnnaBridge 171:3a7713b1edbc 143 __IO uint16_t RxXferCount; /*!< USART Rx Transfer Counter */
AnnaBridge 171:3a7713b1edbc 144
AnnaBridge 171:3a7713b1edbc 145 uint16_t Mask; /*!< USART Rx RDR register mask */
AnnaBridge 171:3a7713b1edbc 146
AnnaBridge 171:3a7713b1edbc 147 DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */
AnnaBridge 171:3a7713b1edbc 148
AnnaBridge 171:3a7713b1edbc 149 DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */
AnnaBridge 171:3a7713b1edbc 150
AnnaBridge 171:3a7713b1edbc 151 HAL_LockTypeDef Lock; /*!< Locking object */
AnnaBridge 171:3a7713b1edbc 152
AnnaBridge 171:3a7713b1edbc 153 __IO HAL_USART_StateTypeDef State; /*!< USART communication state */
AnnaBridge 171:3a7713b1edbc 154
AnnaBridge 171:3a7713b1edbc 155 __IO uint32_t ErrorCode; /*!< USART Error code */
AnnaBridge 171:3a7713b1edbc 156
AnnaBridge 171:3a7713b1edbc 157 }USART_HandleTypeDef;
AnnaBridge 171:3a7713b1edbc 158
AnnaBridge 171:3a7713b1edbc 159 /**
AnnaBridge 171:3a7713b1edbc 160 * @}
AnnaBridge 171:3a7713b1edbc 161 */
AnnaBridge 171:3a7713b1edbc 162
AnnaBridge 171:3a7713b1edbc 163 /* Exported constants --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 164 /** @defgroup USART_Exported_Constants USART Exported Constants
AnnaBridge 171:3a7713b1edbc 165 * @{
AnnaBridge 171:3a7713b1edbc 166 */
AnnaBridge 171:3a7713b1edbc 167
AnnaBridge 171:3a7713b1edbc 168 /** @defgroup USART_Error USART Error
AnnaBridge 171:3a7713b1edbc 169 * @{
AnnaBridge 171:3a7713b1edbc 170 */
AnnaBridge 171:3a7713b1edbc 171 #define HAL_USART_ERROR_NONE (0x00000000U) /*!< No error */
AnnaBridge 171:3a7713b1edbc 172 #define HAL_USART_ERROR_PE (0x00000001U) /*!< Parity error */
AnnaBridge 171:3a7713b1edbc 173 #define HAL_USART_ERROR_NE (0x00000002U) /*!< Noise error */
AnnaBridge 171:3a7713b1edbc 174 #define HAL_USART_ERROR_FE (0x00000004U) /*!< frame error */
AnnaBridge 171:3a7713b1edbc 175 #define HAL_USART_ERROR_ORE (0x00000008U) /*!< Overrun error */
AnnaBridge 171:3a7713b1edbc 176 #define HAL_USART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
AnnaBridge 171:3a7713b1edbc 177 /**
AnnaBridge 171:3a7713b1edbc 178 * @}
AnnaBridge 171:3a7713b1edbc 179 */
AnnaBridge 171:3a7713b1edbc 180
AnnaBridge 171:3a7713b1edbc 181 /** @defgroup USART_Stop_Bits USART Number of Stop Bits
AnnaBridge 171:3a7713b1edbc 182 * @{
AnnaBridge 171:3a7713b1edbc 183 */
AnnaBridge 171:3a7713b1edbc 184 #ifdef USART_SMARTCARD_SUPPORT
AnnaBridge 171:3a7713b1edbc 185 #define USART_STOPBITS_0_5 ((uint32_t)USART_CR2_STOP_0) /*!< USART frame with 0.5 stop bit */
AnnaBridge 171:3a7713b1edbc 186 #define USART_STOPBITS_1 (0x00000000U) /*!< USART frame with 1 stop bit */
AnnaBridge 171:3a7713b1edbc 187 #define USART_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< USART frame with 1.5 stop bits */
AnnaBridge 171:3a7713b1edbc 188 #define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) /*!< USART frame with 2 stop bits */
AnnaBridge 171:3a7713b1edbc 189 #else
AnnaBridge 171:3a7713b1edbc 190 #define USART_STOPBITS_1 (0x00000000U) /*!< USART frame with 1 stop bit */
AnnaBridge 171:3a7713b1edbc 191 #define USART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) /*!< USART frame with 2 stop bits */
AnnaBridge 171:3a7713b1edbc 192 #endif
AnnaBridge 171:3a7713b1edbc 193 /**
AnnaBridge 171:3a7713b1edbc 194 * @}
AnnaBridge 171:3a7713b1edbc 195 */
AnnaBridge 171:3a7713b1edbc 196
AnnaBridge 171:3a7713b1edbc 197 /** @defgroup USART_Parity USART Parity
AnnaBridge 171:3a7713b1edbc 198 * @{
AnnaBridge 171:3a7713b1edbc 199 */
AnnaBridge 171:3a7713b1edbc 200 #define USART_PARITY_NONE (0x00000000U) /*!< No parity */
AnnaBridge 171:3a7713b1edbc 201 #define USART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */
AnnaBridge 171:3a7713b1edbc 202 #define USART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */
AnnaBridge 171:3a7713b1edbc 203 /**
AnnaBridge 171:3a7713b1edbc 204 * @}
AnnaBridge 171:3a7713b1edbc 205 */
AnnaBridge 171:3a7713b1edbc 206
AnnaBridge 171:3a7713b1edbc 207 /** @defgroup USART_Mode USART Mode
AnnaBridge 171:3a7713b1edbc 208 * @{
AnnaBridge 171:3a7713b1edbc 209 */
AnnaBridge 171:3a7713b1edbc 210 #define USART_MODE_RX ((uint32_t)USART_CR1_RE) /*!< RX mode */
AnnaBridge 171:3a7713b1edbc 211 #define USART_MODE_TX ((uint32_t)USART_CR1_TE) /*!< TX mode */
AnnaBridge 171:3a7713b1edbc 212 #define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< RX and TX mode */
AnnaBridge 171:3a7713b1edbc 213 /**
AnnaBridge 171:3a7713b1edbc 214 * @}
AnnaBridge 171:3a7713b1edbc 215 */
AnnaBridge 171:3a7713b1edbc 216
AnnaBridge 171:3a7713b1edbc 217 /** @defgroup USART_Clock USART Clock
AnnaBridge 171:3a7713b1edbc 218 * @{
AnnaBridge 171:3a7713b1edbc 219 */
AnnaBridge 171:3a7713b1edbc 220 #define USART_CLOCK_DISABLE (0x00000000U) /*!< USART clock disable */
AnnaBridge 171:3a7713b1edbc 221 #define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN) /*!< USART clock enable */
AnnaBridge 171:3a7713b1edbc 222 /**
AnnaBridge 171:3a7713b1edbc 223 * @}
AnnaBridge 171:3a7713b1edbc 224 */
AnnaBridge 171:3a7713b1edbc 225
AnnaBridge 171:3a7713b1edbc 226 /** @defgroup USART_Clock_Polarity USART Clock Polarity
AnnaBridge 171:3a7713b1edbc 227 * @{
AnnaBridge 171:3a7713b1edbc 228 */
AnnaBridge 171:3a7713b1edbc 229 #define USART_POLARITY_LOW (0x00000000U) /*!< USART Clock signal is steady Low */
AnnaBridge 171:3a7713b1edbc 230 #define USART_POLARITY_HIGH ((uint32_t)USART_CR2_CPOL) /*!< USART Clock signal is steady High */
AnnaBridge 171:3a7713b1edbc 231 /**
AnnaBridge 171:3a7713b1edbc 232 * @}
AnnaBridge 171:3a7713b1edbc 233 */
AnnaBridge 171:3a7713b1edbc 234
AnnaBridge 171:3a7713b1edbc 235 /** @defgroup USART_Clock_Phase USART Clock Phase
AnnaBridge 171:3a7713b1edbc 236 * @{
AnnaBridge 171:3a7713b1edbc 237 */
AnnaBridge 171:3a7713b1edbc 238 #define USART_PHASE_1EDGE (0x00000000U) /*!< USART frame phase on first clock transition */
AnnaBridge 171:3a7713b1edbc 239 #define USART_PHASE_2EDGE ((uint32_t)USART_CR2_CPHA) /*!< USART frame phase on second clock transition */
AnnaBridge 171:3a7713b1edbc 240 /**
AnnaBridge 171:3a7713b1edbc 241 * @}
AnnaBridge 171:3a7713b1edbc 242 */
AnnaBridge 171:3a7713b1edbc 243
AnnaBridge 171:3a7713b1edbc 244 /** @defgroup USART_Last_Bit USART Last Bit
AnnaBridge 171:3a7713b1edbc 245 * @{
AnnaBridge 171:3a7713b1edbc 246 */
AnnaBridge 171:3a7713b1edbc 247 #define USART_LASTBIT_DISABLE (0x00000000U) /*!< USART frame last data bit clock pulse not output to SCLK pin */
AnnaBridge 171:3a7713b1edbc 248 #define USART_LASTBIT_ENABLE ((uint32_t)USART_CR2_LBCL) /*!< USART frame last data bit clock pulse output to SCLK pin */
AnnaBridge 171:3a7713b1edbc 249 /**
AnnaBridge 171:3a7713b1edbc 250 * @}
AnnaBridge 171:3a7713b1edbc 251 */
AnnaBridge 171:3a7713b1edbc 252
AnnaBridge 171:3a7713b1edbc 253 /** @defgroup USART_Interrupt_definition USART Interrupts Definition
AnnaBridge 171:3a7713b1edbc 254 * Elements values convention: 0000ZZZZ0XXYYYYYb
AnnaBridge 171:3a7713b1edbc 255 * - YYYYY : Interrupt source position in the XX register (5bits)
AnnaBridge 171:3a7713b1edbc 256 * - XX : Interrupt source register (2bits)
AnnaBridge 171:3a7713b1edbc 257 * - 01: CR1 register
AnnaBridge 171:3a7713b1edbc 258 * - 10: CR2 register
AnnaBridge 171:3a7713b1edbc 259 * - 11: CR3 register
AnnaBridge 171:3a7713b1edbc 260 * - ZZZZ : Flag position in the ISR register(4bits)
AnnaBridge 171:3a7713b1edbc 261 * @{
AnnaBridge 171:3a7713b1edbc 262 */
AnnaBridge 171:3a7713b1edbc 263
AnnaBridge 171:3a7713b1edbc 264 #define USART_IT_PE ((uint16_t)0x0028U) /*!< USART parity error interruption */
AnnaBridge 171:3a7713b1edbc 265 #define USART_IT_TXE ((uint16_t)0x0727U) /*!< USART transmit data register empty interruption */
AnnaBridge 171:3a7713b1edbc 266 #define USART_IT_TC ((uint16_t)0x0626U) /*!< USART transmission complete interruption */
AnnaBridge 171:3a7713b1edbc 267 #define USART_IT_RXNE ((uint16_t)0x0525U) /*!< USART read data register not empty interruption */
AnnaBridge 171:3a7713b1edbc 268 #define USART_IT_IDLE ((uint16_t)0x0424U) /*!< USART idle interruption */
AnnaBridge 171:3a7713b1edbc 269 #define USART_IT_ERR ((uint16_t)0x0060U) /*!< USART error interruption */
AnnaBridge 171:3a7713b1edbc 270 #define USART_IT_ORE ((uint16_t)0x0300U) /*!< USART overrun error interruption */
AnnaBridge 171:3a7713b1edbc 271 #define USART_IT_NE ((uint16_t)0x0200U) /*!< USART noise error interruption */
AnnaBridge 171:3a7713b1edbc 272 #define USART_IT_FE ((uint16_t)0x0100U) /*!< USART frame error interruption */
AnnaBridge 171:3a7713b1edbc 273 /**
AnnaBridge 171:3a7713b1edbc 274 * @}
AnnaBridge 171:3a7713b1edbc 275 */
AnnaBridge 171:3a7713b1edbc 276
AnnaBridge 171:3a7713b1edbc 277 /** @defgroup USART_IT_CLEAR_Flags USART Interruption Clear Flags
AnnaBridge 171:3a7713b1edbc 278 * @{
AnnaBridge 171:3a7713b1edbc 279 */
AnnaBridge 171:3a7713b1edbc 280 #define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
AnnaBridge 171:3a7713b1edbc 281 #define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
AnnaBridge 171:3a7713b1edbc 282 #define USART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
AnnaBridge 171:3a7713b1edbc 283 #define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
AnnaBridge 171:3a7713b1edbc 284 #define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
AnnaBridge 171:3a7713b1edbc 285 #define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
AnnaBridge 171:3a7713b1edbc 286 #define USART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
AnnaBridge 171:3a7713b1edbc 287 /**
AnnaBridge 171:3a7713b1edbc 288 * @}
AnnaBridge 171:3a7713b1edbc 289 */
AnnaBridge 171:3a7713b1edbc 290
AnnaBridge 171:3a7713b1edbc 291 /** @defgroup USART_Interruption_Mask USART Interruption Flags Mask
AnnaBridge 171:3a7713b1edbc 292 * @{
AnnaBridge 171:3a7713b1edbc 293 */
AnnaBridge 171:3a7713b1edbc 294 #define USART_IT_MASK ((uint16_t)0x001FU) /*!< USART interruptions flags mask */
AnnaBridge 171:3a7713b1edbc 295 /**
AnnaBridge 171:3a7713b1edbc 296 * @}
AnnaBridge 171:3a7713b1edbc 297 */
AnnaBridge 171:3a7713b1edbc 298
AnnaBridge 171:3a7713b1edbc 299 /**
AnnaBridge 171:3a7713b1edbc 300 * @}
AnnaBridge 171:3a7713b1edbc 301 */
AnnaBridge 171:3a7713b1edbc 302
AnnaBridge 171:3a7713b1edbc 303 /* Exported macros -----------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 304 /** @defgroup USART_Exported_Macros USART Exported Macros
AnnaBridge 171:3a7713b1edbc 305 * @{
AnnaBridge 171:3a7713b1edbc 306 */
AnnaBridge 171:3a7713b1edbc 307
AnnaBridge 171:3a7713b1edbc 308 /** @brief Reset USART handle state.
AnnaBridge 171:3a7713b1edbc 309 * @param __HANDLE__ USART handle.
AnnaBridge 171:3a7713b1edbc 310 * @retval None
AnnaBridge 171:3a7713b1edbc 311 */
AnnaBridge 171:3a7713b1edbc 312 #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
AnnaBridge 171:3a7713b1edbc 313
AnnaBridge 171:3a7713b1edbc 314 /** @brief Check whether the specified USART flag is set or not.
AnnaBridge 171:3a7713b1edbc 315 * @param __HANDLE__ specifies the USART Handle
AnnaBridge 171:3a7713b1edbc 316 * @param __FLAG__ specifies the flag to check.
AnnaBridge 171:3a7713b1edbc 317 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 318 @if STM32F030x6
AnnaBridge 171:3a7713b1edbc 319 @elseif STM32F030x8
AnnaBridge 171:3a7713b1edbc 320 @elseif STM32F030xC
AnnaBridge 171:3a7713b1edbc 321 @elseif STM32F070x6
AnnaBridge 171:3a7713b1edbc 322 @elseif STM32F070xB
AnnaBridge 171:3a7713b1edbc 323 @else
AnnaBridge 171:3a7713b1edbc 324 * @arg @ref USART_FLAG_REACK Receive enable acknowledge flag
AnnaBridge 171:3a7713b1edbc 325 @endif
AnnaBridge 171:3a7713b1edbc 326 * @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag
AnnaBridge 171:3a7713b1edbc 327 * @arg @ref USART_FLAG_BUSY Busy flag
AnnaBridge 171:3a7713b1edbc 328 * @arg @ref USART_FLAG_CTS CTS Change flag
AnnaBridge 171:3a7713b1edbc 329 * @arg @ref USART_FLAG_TXE Transmit data register empty flag
AnnaBridge 171:3a7713b1edbc 330 * @arg @ref USART_FLAG_TC Transmission Complete flag
AnnaBridge 171:3a7713b1edbc 331 * @arg @ref USART_FLAG_RXNE Receive data register not empty flag
AnnaBridge 171:3a7713b1edbc 332 * @arg @ref USART_FLAG_IDLE Idle Line detection flag
AnnaBridge 171:3a7713b1edbc 333 * @arg @ref USART_FLAG_ORE OverRun Error flag
AnnaBridge 171:3a7713b1edbc 334 * @arg @ref USART_FLAG_NE Noise Error flag
AnnaBridge 171:3a7713b1edbc 335 * @arg @ref USART_FLAG_FE Framing Error flag
AnnaBridge 171:3a7713b1edbc 336 * @arg @ref USART_FLAG_PE Parity Error flag
AnnaBridge 171:3a7713b1edbc 337 * @retval The new state of __FLAG__ (TRUE or FALSE).
AnnaBridge 171:3a7713b1edbc 338 */
AnnaBridge 171:3a7713b1edbc 339 #define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
AnnaBridge 171:3a7713b1edbc 340
AnnaBridge 171:3a7713b1edbc 341 /** @brief Clear the specified USART pending flag.
AnnaBridge 171:3a7713b1edbc 342 * @param __HANDLE__ specifies the USART Handle.
AnnaBridge 171:3a7713b1edbc 343 * @param __FLAG__ specifies the flag to check.
AnnaBridge 171:3a7713b1edbc 344 * This parameter can be any combination of the following values:
AnnaBridge 171:3a7713b1edbc 345 * @arg @ref USART_CLEAR_PEF
AnnaBridge 171:3a7713b1edbc 346 * @arg @ref USART_CLEAR_FEF
AnnaBridge 171:3a7713b1edbc 347 * @arg @ref USART_CLEAR_NEF
AnnaBridge 171:3a7713b1edbc 348 * @arg @ref USART_CLEAR_OREF
AnnaBridge 171:3a7713b1edbc 349 * @arg @ref USART_CLEAR_IDLEF
AnnaBridge 171:3a7713b1edbc 350 * @arg @ref USART_CLEAR_TCF
AnnaBridge 171:3a7713b1edbc 351 * @arg @ref USART_CLEAR_CTSF
AnnaBridge 171:3a7713b1edbc 352 * @retval None
AnnaBridge 171:3a7713b1edbc 353 */
AnnaBridge 171:3a7713b1edbc 354 #define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
AnnaBridge 171:3a7713b1edbc 355
AnnaBridge 171:3a7713b1edbc 356 /** @brief Clear the USART PE pending flag.
AnnaBridge 171:3a7713b1edbc 357 * @param __HANDLE__ specifies the USART Handle.
AnnaBridge 171:3a7713b1edbc 358 * @retval None
AnnaBridge 171:3a7713b1edbc 359 */
AnnaBridge 171:3a7713b1edbc 360 #define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
AnnaBridge 171:3a7713b1edbc 361
AnnaBridge 171:3a7713b1edbc 362 /** @brief Clear the USART FE pending flag.
AnnaBridge 171:3a7713b1edbc 363 * @param __HANDLE__ specifies the USART Handle.
AnnaBridge 171:3a7713b1edbc 364 * @retval None
AnnaBridge 171:3a7713b1edbc 365 */
AnnaBridge 171:3a7713b1edbc 366 #define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
AnnaBridge 171:3a7713b1edbc 367
AnnaBridge 171:3a7713b1edbc 368 /** @brief Clear the USART NE pending flag.
AnnaBridge 171:3a7713b1edbc 369 * @param __HANDLE__ specifies the USART Handle.
AnnaBridge 171:3a7713b1edbc 370 * @retval None
AnnaBridge 171:3a7713b1edbc 371 */
AnnaBridge 171:3a7713b1edbc 372 #define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
AnnaBridge 171:3a7713b1edbc 373
AnnaBridge 171:3a7713b1edbc 374 /** @brief Clear the USART ORE pending flag.
AnnaBridge 171:3a7713b1edbc 375 * @param __HANDLE__ specifies the USART Handle.
AnnaBridge 171:3a7713b1edbc 376 * @retval None
AnnaBridge 171:3a7713b1edbc 377 */
AnnaBridge 171:3a7713b1edbc 378 #define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
AnnaBridge 171:3a7713b1edbc 379
AnnaBridge 171:3a7713b1edbc 380 /** @brief Clear the USART IDLE pending flag.
AnnaBridge 171:3a7713b1edbc 381 * @param __HANDLE__ specifies the USART Handle.
AnnaBridge 171:3a7713b1edbc 382 * @retval None
AnnaBridge 171:3a7713b1edbc 383 */
AnnaBridge 171:3a7713b1edbc 384 #define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
AnnaBridge 171:3a7713b1edbc 385
AnnaBridge 171:3a7713b1edbc 386 /** @brief Enable the specified USART interrupt.
AnnaBridge 171:3a7713b1edbc 387 * @param __HANDLE__ specifies the USART Handle.
AnnaBridge 171:3a7713b1edbc 388 * @param __INTERRUPT__ specifies the USART interrupt source to enable.
AnnaBridge 171:3a7713b1edbc 389 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 390 * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
AnnaBridge 171:3a7713b1edbc 391 * @arg @ref USART_IT_TC Transmission complete interrupt
AnnaBridge 171:3a7713b1edbc 392 * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
AnnaBridge 171:3a7713b1edbc 393 * @arg @ref USART_IT_IDLE Idle line detection interrupt
AnnaBridge 171:3a7713b1edbc 394 * @arg @ref USART_IT_PE Parity Error interrupt
AnnaBridge 171:3a7713b1edbc 395 * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
AnnaBridge 171:3a7713b1edbc 396 * @retval None
AnnaBridge 171:3a7713b1edbc 397 */
AnnaBridge 171:3a7713b1edbc 398 #define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & 0xFF) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
AnnaBridge 171:3a7713b1edbc 399 ((((__INTERRUPT__) & 0xFF) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
AnnaBridge 171:3a7713b1edbc 400 ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
AnnaBridge 171:3a7713b1edbc 401
AnnaBridge 171:3a7713b1edbc 402 /** @brief Disable the specified USART interrupt.
AnnaBridge 171:3a7713b1edbc 403 * @param __HANDLE__ specifies the USART Handle.
AnnaBridge 171:3a7713b1edbc 404 * @param __INTERRUPT__ specifies the USART interrupt source to disable.
AnnaBridge 171:3a7713b1edbc 405 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 406 * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
AnnaBridge 171:3a7713b1edbc 407 * @arg @ref USART_IT_TC Transmission complete interrupt
AnnaBridge 171:3a7713b1edbc 408 * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
AnnaBridge 171:3a7713b1edbc 409 * @arg @ref USART_IT_IDLE Idle line detection interrupt
AnnaBridge 171:3a7713b1edbc 410 * @arg @ref USART_IT_PE Parity Error interrupt
AnnaBridge 171:3a7713b1edbc 411 * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
AnnaBridge 171:3a7713b1edbc 412 * @retval None
AnnaBridge 171:3a7713b1edbc 413 */
AnnaBridge 171:3a7713b1edbc 414 #define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & 0xFF) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
AnnaBridge 171:3a7713b1edbc 415 ((((__INTERRUPT__) & 0xFF) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
AnnaBridge 171:3a7713b1edbc 416 ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
AnnaBridge 171:3a7713b1edbc 417
AnnaBridge 171:3a7713b1edbc 418
AnnaBridge 171:3a7713b1edbc 419 /** @brief Check whether the specified USART interrupt has occurred or not.
AnnaBridge 171:3a7713b1edbc 420 * @param __HANDLE__ specifies the USART Handle.
AnnaBridge 171:3a7713b1edbc 421 * @param __IT__ specifies the USART interrupt source to check.
AnnaBridge 171:3a7713b1edbc 422 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 423 * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
AnnaBridge 171:3a7713b1edbc 424 * @arg @ref USART_IT_TC Transmission complete interrupt
AnnaBridge 171:3a7713b1edbc 425 * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
AnnaBridge 171:3a7713b1edbc 426 * @arg @ref USART_IT_IDLE Idle line detection interrupt
AnnaBridge 171:3a7713b1edbc 427 * @arg @ref USART_IT_ORE OverRun Error interrupt
AnnaBridge 171:3a7713b1edbc 428 * @arg @ref USART_IT_NE Noise Error interrupt
AnnaBridge 171:3a7713b1edbc 429 * @arg @ref USART_IT_FE Framing Error interrupt
AnnaBridge 171:3a7713b1edbc 430 * @arg @ref USART_IT_PE Parity Error interrupt
AnnaBridge 171:3a7713b1edbc 431 * @retval The new state of __IT__ (TRUE or FALSE).
AnnaBridge 171:3a7713b1edbc 432 */
AnnaBridge 171:3a7713b1edbc 433 #define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
AnnaBridge 171:3a7713b1edbc 434
AnnaBridge 171:3a7713b1edbc 435 /** @brief Check whether the specified USART interrupt source is enabled or not.
AnnaBridge 171:3a7713b1edbc 436 * @param __HANDLE__ specifies the USART Handle.
AnnaBridge 171:3a7713b1edbc 437 * @param __IT__ specifies the USART interrupt source to check.
AnnaBridge 171:3a7713b1edbc 438 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 439 * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
AnnaBridge 171:3a7713b1edbc 440 * @arg @ref USART_IT_TC Transmission complete interrupt
AnnaBridge 171:3a7713b1edbc 441 * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
AnnaBridge 171:3a7713b1edbc 442 * @arg @ref USART_IT_IDLE Idle line detection interrupt
AnnaBridge 171:3a7713b1edbc 443 * @arg @ref USART_IT_ORE OverRun Error interrupt
AnnaBridge 171:3a7713b1edbc 444 * @arg @ref USART_IT_NE Noise Error interrupt
AnnaBridge 171:3a7713b1edbc 445 * @arg @ref USART_IT_FE Framing Error interrupt
AnnaBridge 171:3a7713b1edbc 446 * @arg @ref USART_IT_PE Parity Error interrupt
AnnaBridge 171:3a7713b1edbc 447 * @retval The new state of __IT__ (TRUE or FALSE).
AnnaBridge 171:3a7713b1edbc 448 */
AnnaBridge 171:3a7713b1edbc 449 #define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1U)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2U)? \
AnnaBridge 171:3a7713b1edbc 450 (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (1U << \
AnnaBridge 171:3a7713b1edbc 451 (((uint16_t)(__IT__)) & USART_IT_MASK)))
AnnaBridge 171:3a7713b1edbc 452
AnnaBridge 171:3a7713b1edbc 453
AnnaBridge 171:3a7713b1edbc 454 /** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag.
AnnaBridge 171:3a7713b1edbc 455 * @param __HANDLE__ specifies the USART Handle.
AnnaBridge 171:3a7713b1edbc 456 * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
AnnaBridge 171:3a7713b1edbc 457 * to clear the corresponding interrupt.
AnnaBridge 171:3a7713b1edbc 458 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 459 * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag
AnnaBridge 171:3a7713b1edbc 460 * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag
AnnaBridge 171:3a7713b1edbc 461 * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag
AnnaBridge 171:3a7713b1edbc 462 * @arg @ref USART_CLEAR_OREF OverRun Error Clear Flag
AnnaBridge 171:3a7713b1edbc 463 * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
AnnaBridge 171:3a7713b1edbc 464 * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
AnnaBridge 171:3a7713b1edbc 465 * @arg @ref USART_CLEAR_CTSF CTS Interrupt Clear Flag
AnnaBridge 171:3a7713b1edbc 466 * @retval None
AnnaBridge 171:3a7713b1edbc 467 */
AnnaBridge 171:3a7713b1edbc 468 #define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
AnnaBridge 171:3a7713b1edbc 469
AnnaBridge 171:3a7713b1edbc 470 /** @brief Set a specific USART request flag.
AnnaBridge 171:3a7713b1edbc 471 * @param __HANDLE__ specifies the USART Handle.
AnnaBridge 171:3a7713b1edbc 472 * @param __REQ__ specifies the request flag to set.
AnnaBridge 171:3a7713b1edbc 473 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 474 * @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request
AnnaBridge 171:3a7713b1edbc 475 @if STM32F030x6
AnnaBridge 171:3a7713b1edbc 476 @elseif STM32F030x8
AnnaBridge 171:3a7713b1edbc 477 @elseif STM32F030xC
AnnaBridge 171:3a7713b1edbc 478 @elseif STM32F070x6
AnnaBridge 171:3a7713b1edbc 479 @elseif STM32F070xB
AnnaBridge 171:3a7713b1edbc 480 @else
AnnaBridge 171:3a7713b1edbc 481 * @arg @ref USART_TXDATA_FLUSH_REQUEST Transmit data flush Request
AnnaBridge 171:3a7713b1edbc 482 @endif
AnnaBridge 171:3a7713b1edbc 483 *
AnnaBridge 171:3a7713b1edbc 484 * @retval None
AnnaBridge 171:3a7713b1edbc 485 */
AnnaBridge 171:3a7713b1edbc 486 #define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (__REQ__))
AnnaBridge 171:3a7713b1edbc 487
AnnaBridge 171:3a7713b1edbc 488 /** @brief Enable the USART one bit sample method.
AnnaBridge 171:3a7713b1edbc 489 * @param __HANDLE__ specifies the USART Handle.
AnnaBridge 171:3a7713b1edbc 490 * @retval None
AnnaBridge 171:3a7713b1edbc 491 */
AnnaBridge 171:3a7713b1edbc 492 #define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
AnnaBridge 171:3a7713b1edbc 493
AnnaBridge 171:3a7713b1edbc 494 /** @brief Disable the USART one bit sample method.
AnnaBridge 171:3a7713b1edbc 495 * @param __HANDLE__ specifies the USART Handle.
AnnaBridge 171:3a7713b1edbc 496 * @retval None
AnnaBridge 171:3a7713b1edbc 497 */
AnnaBridge 171:3a7713b1edbc 498 #define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
AnnaBridge 171:3a7713b1edbc 499
AnnaBridge 171:3a7713b1edbc 500 /** @brief Enable USART.
AnnaBridge 171:3a7713b1edbc 501 * @param __HANDLE__ specifies the USART Handle.
AnnaBridge 171:3a7713b1edbc 502 * @retval None
AnnaBridge 171:3a7713b1edbc 503 */
AnnaBridge 171:3a7713b1edbc 504 #define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
AnnaBridge 171:3a7713b1edbc 505
AnnaBridge 171:3a7713b1edbc 506 /** @brief Disable USART.
AnnaBridge 171:3a7713b1edbc 507 * @param __HANDLE__ specifies the USART Handle.
AnnaBridge 171:3a7713b1edbc 508 * @retval None
AnnaBridge 171:3a7713b1edbc 509 */
AnnaBridge 171:3a7713b1edbc 510 #define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
AnnaBridge 171:3a7713b1edbc 511
AnnaBridge 171:3a7713b1edbc 512 /**
AnnaBridge 171:3a7713b1edbc 513 * @}
AnnaBridge 171:3a7713b1edbc 514 */
AnnaBridge 171:3a7713b1edbc 515
AnnaBridge 171:3a7713b1edbc 516 /* Private macros --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 517 /** @defgroup USART_Private_Macros USART Private Macros
AnnaBridge 171:3a7713b1edbc 518 * @{
AnnaBridge 171:3a7713b1edbc 519 */
AnnaBridge 171:3a7713b1edbc 520
AnnaBridge 171:3a7713b1edbc 521 /** @brief Check USART Baud rate.
AnnaBridge 171:3a7713b1edbc 522 * @param __BAUDRATE__ Baudrate specified by the user.
AnnaBridge 171:3a7713b1edbc 523 * The maximum Baud Rate is derived from the maximum clock on F0 (i.e. 48 MHz)
AnnaBridge 171:3a7713b1edbc 524 * divided by the smallest oversampling used on the USART (i.e. 8)
AnnaBridge 171:3a7713b1edbc 525 * @retval Test result (TRUE or FALSE).
AnnaBridge 171:3a7713b1edbc 526 */
AnnaBridge 171:3a7713b1edbc 527 #define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 6000001U)
AnnaBridge 171:3a7713b1edbc 528
AnnaBridge 171:3a7713b1edbc 529 /**
AnnaBridge 171:3a7713b1edbc 530 * @brief Ensure that USART frame number of stop bits is valid.
AnnaBridge 171:3a7713b1edbc 531 * @param __STOPBITS__ USART frame number of stop bits.
AnnaBridge 171:3a7713b1edbc 532 * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
AnnaBridge 171:3a7713b1edbc 533 */
AnnaBridge 171:3a7713b1edbc 534 #ifdef USART_SMARTCARD_SUPPORT
AnnaBridge 171:3a7713b1edbc 535 #define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \
AnnaBridge 171:3a7713b1edbc 536 ((__STOPBITS__) == USART_STOPBITS_1) || \
AnnaBridge 171:3a7713b1edbc 537 ((__STOPBITS__) == USART_STOPBITS_1_5) || \
AnnaBridge 171:3a7713b1edbc 538 ((__STOPBITS__) == USART_STOPBITS_2))
AnnaBridge 171:3a7713b1edbc 539 #else
AnnaBridge 171:3a7713b1edbc 540 #define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_1) || \
AnnaBridge 171:3a7713b1edbc 541 ((__STOPBITS__) == USART_STOPBITS_2))
AnnaBridge 171:3a7713b1edbc 542 #endif
AnnaBridge 171:3a7713b1edbc 543
AnnaBridge 171:3a7713b1edbc 544 /**
AnnaBridge 171:3a7713b1edbc 545 * @brief Ensure that USART frame parity is valid.
AnnaBridge 171:3a7713b1edbc 546 * @param __PARITY__ USART frame parity.
AnnaBridge 171:3a7713b1edbc 547 * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
AnnaBridge 171:3a7713b1edbc 548 */
AnnaBridge 171:3a7713b1edbc 549 #define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \
AnnaBridge 171:3a7713b1edbc 550 ((__PARITY__) == USART_PARITY_EVEN) || \
AnnaBridge 171:3a7713b1edbc 551 ((__PARITY__) == USART_PARITY_ODD))
AnnaBridge 171:3a7713b1edbc 552
AnnaBridge 171:3a7713b1edbc 553 /**
AnnaBridge 171:3a7713b1edbc 554 * @brief Ensure that USART communication mode is valid.
AnnaBridge 171:3a7713b1edbc 555 * @param __MODE__ USART communication mode.
AnnaBridge 171:3a7713b1edbc 556 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
AnnaBridge 171:3a7713b1edbc 557 */
AnnaBridge 171:3a7713b1edbc 558 #define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
AnnaBridge 171:3a7713b1edbc 559
AnnaBridge 171:3a7713b1edbc 560 /**
AnnaBridge 171:3a7713b1edbc 561 * @brief Ensure that USART clock state is valid.
AnnaBridge 171:3a7713b1edbc 562 * @param __CLOCK__ USART clock state.
AnnaBridge 171:3a7713b1edbc 563 * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)
AnnaBridge 171:3a7713b1edbc 564 */
AnnaBridge 171:3a7713b1edbc 565 #define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \
AnnaBridge 171:3a7713b1edbc 566 ((__CLOCK__) == USART_CLOCK_ENABLE))
AnnaBridge 171:3a7713b1edbc 567
AnnaBridge 171:3a7713b1edbc 568 /**
AnnaBridge 171:3a7713b1edbc 569 * @brief Ensure that USART frame polarity is valid.
AnnaBridge 171:3a7713b1edbc 570 * @param __CPOL__ USART frame polarity.
AnnaBridge 171:3a7713b1edbc 571 * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
AnnaBridge 171:3a7713b1edbc 572 */
AnnaBridge 171:3a7713b1edbc 573 #define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
AnnaBridge 171:3a7713b1edbc 574
AnnaBridge 171:3a7713b1edbc 575 /**
AnnaBridge 171:3a7713b1edbc 576 * @brief Ensure that USART frame phase is valid.
AnnaBridge 171:3a7713b1edbc 577 * @param __CPHA__ USART frame phase.
AnnaBridge 171:3a7713b1edbc 578 * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
AnnaBridge 171:3a7713b1edbc 579 */
AnnaBridge 171:3a7713b1edbc 580 #define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
AnnaBridge 171:3a7713b1edbc 581
AnnaBridge 171:3a7713b1edbc 582 /**
AnnaBridge 171:3a7713b1edbc 583 * @brief Ensure that USART frame last bit clock pulse setting is valid.
AnnaBridge 171:3a7713b1edbc 584 * @param __LASTBIT__ USART frame last bit clock pulse setting.
AnnaBridge 171:3a7713b1edbc 585 * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
AnnaBridge 171:3a7713b1edbc 586 */
AnnaBridge 171:3a7713b1edbc 587 #define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
AnnaBridge 171:3a7713b1edbc 588 ((__LASTBIT__) == USART_LASTBIT_ENABLE))
AnnaBridge 171:3a7713b1edbc 589
AnnaBridge 171:3a7713b1edbc 590 /**
AnnaBridge 171:3a7713b1edbc 591 * @}
AnnaBridge 171:3a7713b1edbc 592 */
AnnaBridge 171:3a7713b1edbc 593
AnnaBridge 171:3a7713b1edbc 594 /* Include USART HAL Extended module */
AnnaBridge 171:3a7713b1edbc 595 #include "stm32f0xx_hal_usart_ex.h"
AnnaBridge 171:3a7713b1edbc 596
AnnaBridge 171:3a7713b1edbc 597 /* Exported functions --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 598 /** @addtogroup USART_Exported_Functions USART Exported Functions
AnnaBridge 171:3a7713b1edbc 599 * @{
AnnaBridge 171:3a7713b1edbc 600 */
AnnaBridge 171:3a7713b1edbc 601
AnnaBridge 171:3a7713b1edbc 602 /** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
AnnaBridge 171:3a7713b1edbc 603 * @{
AnnaBridge 171:3a7713b1edbc 604 */
AnnaBridge 171:3a7713b1edbc 605
AnnaBridge 171:3a7713b1edbc 606 /* Initialization and de-initialization functions ****************************/
AnnaBridge 171:3a7713b1edbc 607 HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
AnnaBridge 171:3a7713b1edbc 608 HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
AnnaBridge 171:3a7713b1edbc 609 void HAL_USART_MspInit(USART_HandleTypeDef *husart);
AnnaBridge 171:3a7713b1edbc 610 void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
AnnaBridge 171:3a7713b1edbc 611
AnnaBridge 171:3a7713b1edbc 612 /**
AnnaBridge 171:3a7713b1edbc 613 * @}
AnnaBridge 171:3a7713b1edbc 614 */
AnnaBridge 171:3a7713b1edbc 615
AnnaBridge 171:3a7713b1edbc 616 /** @addtogroup USART_Exported_Functions_Group2 IO operation functions
AnnaBridge 171:3a7713b1edbc 617 * @{
AnnaBridge 171:3a7713b1edbc 618 */
AnnaBridge 171:3a7713b1edbc 619
AnnaBridge 171:3a7713b1edbc 620 /* IO operation functions *****************************************************/
AnnaBridge 171:3a7713b1edbc 621 HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
AnnaBridge 171:3a7713b1edbc 622 HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
AnnaBridge 171:3a7713b1edbc 623 HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
AnnaBridge 171:3a7713b1edbc 624 HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
AnnaBridge 171:3a7713b1edbc 625 HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
AnnaBridge 171:3a7713b1edbc 626 HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
AnnaBridge 171:3a7713b1edbc 627 HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
AnnaBridge 171:3a7713b1edbc 628 HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
AnnaBridge 171:3a7713b1edbc 629 HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
AnnaBridge 171:3a7713b1edbc 630 HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
AnnaBridge 171:3a7713b1edbc 631 HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
AnnaBridge 171:3a7713b1edbc 632 HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
AnnaBridge 171:3a7713b1edbc 633 /* Transfer Abort functions */
AnnaBridge 171:3a7713b1edbc 634 HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);
AnnaBridge 171:3a7713b1edbc 635 HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
AnnaBridge 171:3a7713b1edbc 636
AnnaBridge 171:3a7713b1edbc 637 void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
AnnaBridge 171:3a7713b1edbc 638 void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
AnnaBridge 171:3a7713b1edbc 639 void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
AnnaBridge 171:3a7713b1edbc 640 void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
AnnaBridge 171:3a7713b1edbc 641 void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
AnnaBridge 171:3a7713b1edbc 642 void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
AnnaBridge 171:3a7713b1edbc 643 void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
AnnaBridge 171:3a7713b1edbc 644 void HAL_USART_AbortCpltCallback (USART_HandleTypeDef *husart);
AnnaBridge 171:3a7713b1edbc 645
AnnaBridge 171:3a7713b1edbc 646 /**
AnnaBridge 171:3a7713b1edbc 647 * @}
AnnaBridge 171:3a7713b1edbc 648 */
AnnaBridge 171:3a7713b1edbc 649
AnnaBridge 171:3a7713b1edbc 650 /* Peripheral Control functions ***********************************************/
AnnaBridge 171:3a7713b1edbc 651
AnnaBridge 171:3a7713b1edbc 652 /** @addtogroup USART_Exported_Functions_Group3 Peripheral State and Error functions
AnnaBridge 171:3a7713b1edbc 653 * @{
AnnaBridge 171:3a7713b1edbc 654 */
AnnaBridge 171:3a7713b1edbc 655
AnnaBridge 171:3a7713b1edbc 656 /* Peripheral State and Error functions ***************************************/
AnnaBridge 171:3a7713b1edbc 657 HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
AnnaBridge 171:3a7713b1edbc 658 uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
AnnaBridge 171:3a7713b1edbc 659
AnnaBridge 171:3a7713b1edbc 660 /**
AnnaBridge 171:3a7713b1edbc 661 * @}
AnnaBridge 171:3a7713b1edbc 662 */
AnnaBridge 171:3a7713b1edbc 663
AnnaBridge 171:3a7713b1edbc 664 /**
AnnaBridge 171:3a7713b1edbc 665 * @}
AnnaBridge 171:3a7713b1edbc 666 */
AnnaBridge 171:3a7713b1edbc 667
AnnaBridge 171:3a7713b1edbc 668 /**
AnnaBridge 171:3a7713b1edbc 669 * @}
AnnaBridge 171:3a7713b1edbc 670 */
AnnaBridge 171:3a7713b1edbc 671
AnnaBridge 171:3a7713b1edbc 672 /**
AnnaBridge 171:3a7713b1edbc 673 * @}
AnnaBridge 171:3a7713b1edbc 674 */
AnnaBridge 171:3a7713b1edbc 675
AnnaBridge 171:3a7713b1edbc 676 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 677 }
AnnaBridge 171:3a7713b1edbc 678 #endif
AnnaBridge 171:3a7713b1edbc 679
AnnaBridge 171:3a7713b1edbc 680 #endif /* __STM32F0xx_HAL_USART_H */
AnnaBridge 171:3a7713b1edbc 681
AnnaBridge 171:3a7713b1edbc 682 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
AnnaBridge 171:3a7713b1edbc 683