mbed - The official Mbed 2 C/C++ SDK provides the softwa…

Users » mbed_official » Code » mbed

mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/stm32f0xx_hal_rcc.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	171:3a7713b1edbc	1	/**
AnnaBridge	171:3a7713b1edbc	2	******************************************************************************
AnnaBridge	171:3a7713b1edbc	3	* @file stm32f0xx_hal_rcc.h
AnnaBridge	171:3a7713b1edbc	4	* @author MCD Application Team
AnnaBridge	171:3a7713b1edbc	5	* @brief Header file of RCC HAL module.
AnnaBridge	171:3a7713b1edbc	6	******************************************************************************
AnnaBridge	171:3a7713b1edbc	7	* @attention
AnnaBridge	171:3a7713b1edbc	8	*
AnnaBridge	171:3a7713b1edbc	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	171:3a7713b1edbc	10	*
AnnaBridge	171:3a7713b1edbc	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	171:3a7713b1edbc	12	* are permitted provided that the following conditions are met:
AnnaBridge	171:3a7713b1edbc	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	171:3a7713b1edbc	14	* this list of conditions and the following disclaimer.
AnnaBridge	171:3a7713b1edbc	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	171:3a7713b1edbc	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	171:3a7713b1edbc	17	* and/or other materials provided with the distribution.
AnnaBridge	171:3a7713b1edbc	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	171:3a7713b1edbc	19	* may be used to endorse or promote products derived from this software
AnnaBridge	171:3a7713b1edbc	20	* without specific prior written permission.
AnnaBridge	171:3a7713b1edbc	21	*
AnnaBridge	171:3a7713b1edbc	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	171:3a7713b1edbc	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	171:3a7713b1edbc	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	171:3a7713b1edbc	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	171:3a7713b1edbc	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	171:3a7713b1edbc	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	171:3a7713b1edbc	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	171:3a7713b1edbc	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	171:3a7713b1edbc	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	171:3a7713b1edbc	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	171:3a7713b1edbc	32	*
AnnaBridge	171:3a7713b1edbc	33	******************************************************************************
AnnaBridge	171:3a7713b1edbc	34	*/
AnnaBridge	171:3a7713b1edbc	35
AnnaBridge	171:3a7713b1edbc	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	171:3a7713b1edbc	37	#ifndef __STM32F0xx_HAL_RCC_H
AnnaBridge	171:3a7713b1edbc	38	#define __STM32F0xx_HAL_RCC_H
AnnaBridge	171:3a7713b1edbc	39
AnnaBridge	171:3a7713b1edbc	40	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	41	extern "C" {
AnnaBridge	171:3a7713b1edbc	42	#endif
AnnaBridge	171:3a7713b1edbc	43
AnnaBridge	171:3a7713b1edbc	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	45	#include "stm32f0xx_hal_def.h"
AnnaBridge	171:3a7713b1edbc	46
AnnaBridge	171:3a7713b1edbc	47	/** @addtogroup STM32F0xx_HAL_Driver
AnnaBridge	171:3a7713b1edbc	48	* @{
AnnaBridge	171:3a7713b1edbc	49	*/
AnnaBridge	171:3a7713b1edbc	50
AnnaBridge	171:3a7713b1edbc	51	/** @addtogroup RCC
AnnaBridge	171:3a7713b1edbc	52	* @{
AnnaBridge	171:3a7713b1edbc	53	*/
AnnaBridge	171:3a7713b1edbc	54
AnnaBridge	171:3a7713b1edbc	55	/** @addtogroup RCC_Private_Constants
AnnaBridge	171:3a7713b1edbc	56	* @{
AnnaBridge	171:3a7713b1edbc	57	*/
AnnaBridge	171:3a7713b1edbc	58
AnnaBridge	171:3a7713b1edbc	59	/** @defgroup RCC_Timeout RCC Timeout
AnnaBridge	171:3a7713b1edbc	60	* @{
AnnaBridge	171:3a7713b1edbc	61	*/
AnnaBridge	171:3a7713b1edbc	62
AnnaBridge	171:3a7713b1edbc	63	/* Disable Backup domain write protection state change timeout */
AnnaBridge	171:3a7713b1edbc	64	#define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */
AnnaBridge	171:3a7713b1edbc	65	/* LSE state change timeout */
AnnaBridge	171:3a7713b1edbc	66	#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
AnnaBridge	171:3a7713b1edbc	67	#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */
AnnaBridge	171:3a7713b1edbc	68	#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
AnnaBridge	171:3a7713b1edbc	69	#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
AnnaBridge	171:3a7713b1edbc	70	#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
AnnaBridge	171:3a7713b1edbc	71	#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
AnnaBridge	171:3a7713b1edbc	72	#define HSI14_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
AnnaBridge	171:3a7713b1edbc	73	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	171:3a7713b1edbc	74	#define HSI48_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
AnnaBridge	171:3a7713b1edbc	75	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	171:3a7713b1edbc	76	/**
AnnaBridge	171:3a7713b1edbc	77	* @}
AnnaBridge	171:3a7713b1edbc	78	*/
AnnaBridge	171:3a7713b1edbc	79
AnnaBridge	171:3a7713b1edbc	80	/** @defgroup RCC_Register_Offset Register offsets
AnnaBridge	171:3a7713b1edbc	81	* @{
AnnaBridge	171:3a7713b1edbc	82	*/
AnnaBridge	171:3a7713b1edbc	83	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
AnnaBridge	171:3a7713b1edbc	84	#define RCC_CR_OFFSET 0x00
AnnaBridge	171:3a7713b1edbc	85	#define RCC_CFGR_OFFSET 0x04
AnnaBridge	171:3a7713b1edbc	86	#define RCC_CIR_OFFSET 0x08
AnnaBridge	171:3a7713b1edbc	87	#define RCC_BDCR_OFFSET 0x20
AnnaBridge	171:3a7713b1edbc	88	#define RCC_CSR_OFFSET 0x24
AnnaBridge	171:3a7713b1edbc	89
AnnaBridge	171:3a7713b1edbc	90	/**
AnnaBridge	171:3a7713b1edbc	91	* @}
AnnaBridge	171:3a7713b1edbc	92	*/
AnnaBridge	171:3a7713b1edbc	93
AnnaBridge	171:3a7713b1edbc	94
AnnaBridge	171:3a7713b1edbc	95	/* CR register byte 2 (Bits[23:16]) base address */
AnnaBridge	171:3a7713b1edbc	96	#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
AnnaBridge	171:3a7713b1edbc	97
AnnaBridge	171:3a7713b1edbc	98	/* CIR register byte 1 (Bits[15:8]) base address */
AnnaBridge	171:3a7713b1edbc	99	#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
AnnaBridge	171:3a7713b1edbc	100
AnnaBridge	171:3a7713b1edbc	101	/* CIR register byte 2 (Bits[23:16]) base address */
AnnaBridge	171:3a7713b1edbc	102	#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
AnnaBridge	171:3a7713b1edbc	103
AnnaBridge	171:3a7713b1edbc	104	/* Defines used for Flags */
AnnaBridge	171:3a7713b1edbc	105	#define CR_REG_INDEX ((uint8_t)1U)
AnnaBridge	171:3a7713b1edbc	106	#define CR2_REG_INDEX ((uint8_t)2U)
AnnaBridge	171:3a7713b1edbc	107	#define BDCR_REG_INDEX ((uint8_t)3U)
AnnaBridge	171:3a7713b1edbc	108	#define CSR_REG_INDEX ((uint8_t)4U)
AnnaBridge	171:3a7713b1edbc	109
AnnaBridge	171:3a7713b1edbc	110	/* Bits position in in the CFGR register */
AnnaBridge	171:3a7713b1edbc	111	#define RCC_CFGR_PLLMUL_BITNUMBER 18U
AnnaBridge	171:3a7713b1edbc	112	#define RCC_CFGR_HPRE_BITNUMBER 4U
AnnaBridge	171:3a7713b1edbc	113	#define RCC_CFGR_PPRE_BITNUMBER 8U
AnnaBridge	171:3a7713b1edbc	114	/* Flags in the CFGR2 register */
AnnaBridge	171:3a7713b1edbc	115	#define RCC_CFGR2_PREDIV_BITNUMBER 0
AnnaBridge	171:3a7713b1edbc	116	/* Flags in the CR register */
AnnaBridge	171:3a7713b1edbc	117	#define RCC_CR_HSIRDY_BitNumber 1
AnnaBridge	171:3a7713b1edbc	118	#define RCC_CR_HSERDY_BitNumber 17
AnnaBridge	171:3a7713b1edbc	119	#define RCC_CR_PLLRDY_BitNumber 25
AnnaBridge	171:3a7713b1edbc	120	/* Flags in the CR2 register */
AnnaBridge	171:3a7713b1edbc	121	#define RCC_CR2_HSI14RDY_BitNumber 1
AnnaBridge	171:3a7713b1edbc	122	#define RCC_CR2_HSI48RDY_BitNumber 16
AnnaBridge	171:3a7713b1edbc	123	/* Flags in the BDCR register */
AnnaBridge	171:3a7713b1edbc	124	#define RCC_BDCR_LSERDY_BitNumber 1
AnnaBridge	171:3a7713b1edbc	125	/* Flags in the CSR register */
AnnaBridge	171:3a7713b1edbc	126	#define RCC_CSR_LSIRDY_BitNumber 1
AnnaBridge	171:3a7713b1edbc	127	#define RCC_CSR_V18PWRRSTF_BitNumber 23
AnnaBridge	171:3a7713b1edbc	128	#define RCC_CSR_RMVF_BitNumber 24
AnnaBridge	171:3a7713b1edbc	129	#define RCC_CSR_OBLRSTF_BitNumber 25
AnnaBridge	171:3a7713b1edbc	130	#define RCC_CSR_PINRSTF_BitNumber 26
AnnaBridge	171:3a7713b1edbc	131	#define RCC_CSR_PORRSTF_BitNumber 27
AnnaBridge	171:3a7713b1edbc	132	#define RCC_CSR_SFTRSTF_BitNumber 28
AnnaBridge	171:3a7713b1edbc	133	#define RCC_CSR_IWDGRSTF_BitNumber 29
AnnaBridge	171:3a7713b1edbc	134	#define RCC_CSR_WWDGRSTF_BitNumber 30
AnnaBridge	171:3a7713b1edbc	135	#define RCC_CSR_LPWRRSTF_BitNumber 31
AnnaBridge	171:3a7713b1edbc	136	/* Flags in the HSITRIM register */
AnnaBridge	171:3a7713b1edbc	137	#define RCC_CR_HSITRIM_BitNumber 3
AnnaBridge	171:3a7713b1edbc	138	#define RCC_HSI14TRIM_BIT_NUMBER 3
AnnaBridge	171:3a7713b1edbc	139	#define RCC_FLAG_MASK ((uint8_t)0x1FU)
AnnaBridge	171:3a7713b1edbc	140
AnnaBridge	171:3a7713b1edbc	141	/**
AnnaBridge	171:3a7713b1edbc	142	* @}
AnnaBridge	171:3a7713b1edbc	143	*/
AnnaBridge	171:3a7713b1edbc	144
AnnaBridge	171:3a7713b1edbc	145	/** @addtogroup RCC_Private_Macros
AnnaBridge	171:3a7713b1edbc	146	* @{
AnnaBridge	171:3a7713b1edbc	147	*/
AnnaBridge	171:3a7713b1edbc	148	#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) \|\| ((__HSE__) == RCC_HSE_ON) \|\| \
AnnaBridge	171:3a7713b1edbc	149	((__HSE__) == RCC_HSE_BYPASS))
AnnaBridge	171:3a7713b1edbc	150	#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) \|\| ((__LSE__) == RCC_LSE_ON) \|\| \
AnnaBridge	171:3a7713b1edbc	151	((__LSE__) == RCC_LSE_BYPASS))
AnnaBridge	171:3a7713b1edbc	152	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON))
AnnaBridge	171:3a7713b1edbc	153	#define IS_RCC_HSI14(__HSI14__) (((__HSI14__) == RCC_HSI14_OFF) \|\| ((__HSI14__) == RCC_HSI14_ON) \|\| ((__HSI14__) == RCC_HSI14_ADC_CONTROL))
AnnaBridge	171:3a7713b1edbc	154	#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
AnnaBridge	171:3a7713b1edbc	155	#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) \|\| ((__LSI__) == RCC_LSI_ON))
AnnaBridge	171:3a7713b1edbc	156	#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) \|\| ((__PLL__) == RCC_PLL_OFF) \|\| \
AnnaBridge	171:3a7713b1edbc	157	((__PLL__) == RCC_PLL_ON))
AnnaBridge	171:3a7713b1edbc	158	#define IS_RCC_PREDIV(__PREDIV__) (((__PREDIV__) == RCC_PREDIV_DIV1) \|\| ((__PREDIV__) == RCC_PREDIV_DIV2) \|\| \
AnnaBridge	171:3a7713b1edbc	159	((__PREDIV__) == RCC_PREDIV_DIV3) \|\| ((__PREDIV__) == RCC_PREDIV_DIV4) \|\| \
AnnaBridge	171:3a7713b1edbc	160	((__PREDIV__) == RCC_PREDIV_DIV5) \|\| ((__PREDIV__) == RCC_PREDIV_DIV6) \|\| \
AnnaBridge	171:3a7713b1edbc	161	((__PREDIV__) == RCC_PREDIV_DIV7) \|\| ((__PREDIV__) == RCC_PREDIV_DIV8) \|\| \
AnnaBridge	171:3a7713b1edbc	162	((__PREDIV__) == RCC_PREDIV_DIV9) \|\| ((__PREDIV__) == RCC_PREDIV_DIV10) \|\| \
AnnaBridge	171:3a7713b1edbc	163	((__PREDIV__) == RCC_PREDIV_DIV11) \|\| ((__PREDIV__) == RCC_PREDIV_DIV12) \|\| \
AnnaBridge	171:3a7713b1edbc	164	((__PREDIV__) == RCC_PREDIV_DIV13) \|\| ((__PREDIV__) == RCC_PREDIV_DIV14) \|\| \
AnnaBridge	171:3a7713b1edbc	165	((__PREDIV__) == RCC_PREDIV_DIV15) \|\| ((__PREDIV__) == RCC_PREDIV_DIV16))
AnnaBridge	171:3a7713b1edbc	166
AnnaBridge	171:3a7713b1edbc	167	#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) \|\| ((__MUL__) == RCC_PLL_MUL3) \|\| \
AnnaBridge	171:3a7713b1edbc	168	((__MUL__) == RCC_PLL_MUL4) \|\| ((__MUL__) == RCC_PLL_MUL5) \|\| \
AnnaBridge	171:3a7713b1edbc	169	((__MUL__) == RCC_PLL_MUL6) \|\| ((__MUL__) == RCC_PLL_MUL7) \|\| \
AnnaBridge	171:3a7713b1edbc	170	((__MUL__) == RCC_PLL_MUL8) \|\| ((__MUL__) == RCC_PLL_MUL9) \|\| \
AnnaBridge	171:3a7713b1edbc	171	((__MUL__) == RCC_PLL_MUL10) \|\| ((__MUL__) == RCC_PLL_MUL11) \|\| \
AnnaBridge	171:3a7713b1edbc	172	((__MUL__) == RCC_PLL_MUL12) \|\| ((__MUL__) == RCC_PLL_MUL13) \|\| \
AnnaBridge	171:3a7713b1edbc	173	((__MUL__) == RCC_PLL_MUL14) \|\| ((__MUL__) == RCC_PLL_MUL15) \|\| \
AnnaBridge	171:3a7713b1edbc	174	((__MUL__) == RCC_PLL_MUL16))
AnnaBridge	171:3a7713b1edbc	175	#define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) \|\| \
AnnaBridge	171:3a7713b1edbc	176	(((__CLK__) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) \|\| \
AnnaBridge	171:3a7713b1edbc	177	(((__CLK__) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1))
AnnaBridge	171:3a7713b1edbc	178	#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|\| \
AnnaBridge	171:3a7713b1edbc	179	((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \
AnnaBridge	171:3a7713b1edbc	180	((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \
AnnaBridge	171:3a7713b1edbc	181	((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \
AnnaBridge	171:3a7713b1edbc	182	((__HCLK__) == RCC_SYSCLK_DIV512))
AnnaBridge	171:3a7713b1edbc	183	#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \
AnnaBridge	171:3a7713b1edbc	184	((__PCLK__) == RCC_HCLK_DIV4) \|\| ((__PCLK__) == RCC_HCLK_DIV8) \|\| \
AnnaBridge	171:3a7713b1edbc	185	((__PCLK__) == RCC_HCLK_DIV16))
AnnaBridge	171:3a7713b1edbc	186	#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
AnnaBridge	171:3a7713b1edbc	187	#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) \|\| \
AnnaBridge	171:3a7713b1edbc	188	((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) \|\| \
AnnaBridge	171:3a7713b1edbc	189	((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) \|\| \
AnnaBridge	171:3a7713b1edbc	190	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
AnnaBridge	171:3a7713b1edbc	191	#define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK1) \|\| \
AnnaBridge	171:3a7713b1edbc	192	((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
AnnaBridge	171:3a7713b1edbc	193	((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) \|\| \
AnnaBridge	171:3a7713b1edbc	194	((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
AnnaBridge	171:3a7713b1edbc	195	#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) \|\| \
AnnaBridge	171:3a7713b1edbc	196	((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK))
AnnaBridge	171:3a7713b1edbc	197
AnnaBridge	171:3a7713b1edbc	198	/**
AnnaBridge	171:3a7713b1edbc	199	* @}
AnnaBridge	171:3a7713b1edbc	200	*/
AnnaBridge	171:3a7713b1edbc	201
AnnaBridge	171:3a7713b1edbc	202	/* Exported types ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	203
AnnaBridge	171:3a7713b1edbc	204	/** @defgroup RCC_Exported_Types RCC Exported Types
AnnaBridge	171:3a7713b1edbc	205	* @{
AnnaBridge	171:3a7713b1edbc	206	*/
AnnaBridge	171:3a7713b1edbc	207
AnnaBridge	171:3a7713b1edbc	208	/**
AnnaBridge	171:3a7713b1edbc	209	* @brief RCC PLL configuration structure definition
AnnaBridge	171:3a7713b1edbc	210	*/
AnnaBridge	171:3a7713b1edbc	211	typedef struct
AnnaBridge	171:3a7713b1edbc	212	{
AnnaBridge	171:3a7713b1edbc	213	uint32_t PLLState; /*!< PLLState: The new state of the PLL.
AnnaBridge	171:3a7713b1edbc	214	This parameter can be a value of @ref RCC_PLL_Config */
AnnaBridge	171:3a7713b1edbc	215
AnnaBridge	171:3a7713b1edbc	216	uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
AnnaBridge	171:3a7713b1edbc	217	This parameter must be a value of @ref RCC_PLL_Clock_Source */
AnnaBridge	171:3a7713b1edbc	218
AnnaBridge	171:3a7713b1edbc	219	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
AnnaBridge	171:3a7713b1edbc	220	This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
AnnaBridge	171:3a7713b1edbc	221
AnnaBridge	171:3a7713b1edbc	222	uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock
AnnaBridge	171:3a7713b1edbc	223	This parameter must be a value of @ref RCC_PLL_Prediv_Factor */
AnnaBridge	171:3a7713b1edbc	224
AnnaBridge	171:3a7713b1edbc	225	} RCC_PLLInitTypeDef;
AnnaBridge	171:3a7713b1edbc	226
AnnaBridge	171:3a7713b1edbc	227	/**
AnnaBridge	171:3a7713b1edbc	228	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
AnnaBridge	171:3a7713b1edbc	229	*/
AnnaBridge	171:3a7713b1edbc	230	typedef struct
AnnaBridge	171:3a7713b1edbc	231	{
AnnaBridge	171:3a7713b1edbc	232	uint32_t OscillatorType; /*!< The oscillators to be configured.
AnnaBridge	171:3a7713b1edbc	233	This parameter can be a value of @ref RCC_Oscillator_Type */
AnnaBridge	171:3a7713b1edbc	234
AnnaBridge	171:3a7713b1edbc	235	uint32_t HSEState; /*!< The new state of the HSE.
AnnaBridge	171:3a7713b1edbc	236	This parameter can be a value of @ref RCC_HSE_Config */
AnnaBridge	171:3a7713b1edbc	237
AnnaBridge	171:3a7713b1edbc	238	uint32_t LSEState; /*!< The new state of the LSE.
AnnaBridge	171:3a7713b1edbc	239	This parameter can be a value of @ref RCC_LSE_Config */
AnnaBridge	171:3a7713b1edbc	240
AnnaBridge	171:3a7713b1edbc	241	uint32_t HSIState; /*!< The new state of the HSI.
AnnaBridge	171:3a7713b1edbc	242	This parameter can be a value of @ref RCC_HSI_Config */
AnnaBridge	171:3a7713b1edbc	243
AnnaBridge	171:3a7713b1edbc	244	uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
AnnaBridge	171:3a7713b1edbc	245	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */
AnnaBridge	171:3a7713b1edbc	246
AnnaBridge	171:3a7713b1edbc	247	uint32_t HSI14State; /*!< The new state of the HSI14.
AnnaBridge	171:3a7713b1edbc	248	This parameter can be a value of @ref RCC_HSI14_Config */
AnnaBridge	171:3a7713b1edbc	249
AnnaBridge	171:3a7713b1edbc	250	uint32_t HSI14CalibrationValue; /*!< The HSI14 calibration trimming value (default is RCC_HSI14CALIBRATION_DEFAULT).
AnnaBridge	171:3a7713b1edbc	251	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */
AnnaBridge	171:3a7713b1edbc	252
AnnaBridge	171:3a7713b1edbc	253	uint32_t LSIState; /*!< The new state of the LSI.
AnnaBridge	171:3a7713b1edbc	254	This parameter can be a value of @ref RCC_LSI_Config */
AnnaBridge	171:3a7713b1edbc	255
AnnaBridge	171:3a7713b1edbc	256	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	171:3a7713b1edbc	257	uint32_t HSI48State; /*!< The new state of the HSI48.
AnnaBridge	171:3a7713b1edbc	258	This parameter can be a value of @ref RCC_HSI48_Config */
AnnaBridge	171:3a7713b1edbc	259
AnnaBridge	171:3a7713b1edbc	260	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	171:3a7713b1edbc	261	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
AnnaBridge	171:3a7713b1edbc	262
AnnaBridge	171:3a7713b1edbc	263	} RCC_OscInitTypeDef;
AnnaBridge	171:3a7713b1edbc	264
AnnaBridge	171:3a7713b1edbc	265	/**
AnnaBridge	171:3a7713b1edbc	266	* @brief RCC System, AHB and APB busses clock configuration structure definition
AnnaBridge	171:3a7713b1edbc	267	*/
AnnaBridge	171:3a7713b1edbc	268	typedef struct
AnnaBridge	171:3a7713b1edbc	269	{
AnnaBridge	171:3a7713b1edbc	270	uint32_t ClockType; /*!< The clock to be configured.
AnnaBridge	171:3a7713b1edbc	271	This parameter can be a value of @ref RCC_System_Clock_Type */
AnnaBridge	171:3a7713b1edbc	272
AnnaBridge	171:3a7713b1edbc	273	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
AnnaBridge	171:3a7713b1edbc	274	This parameter can be a value of @ref RCC_System_Clock_Source */
AnnaBridge	171:3a7713b1edbc	275
AnnaBridge	171:3a7713b1edbc	276	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
AnnaBridge	171:3a7713b1edbc	277	This parameter can be a value of @ref RCC_AHB_Clock_Source */
AnnaBridge	171:3a7713b1edbc	278
AnnaBridge	171:3a7713b1edbc	279	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
AnnaBridge	171:3a7713b1edbc	280	This parameter can be a value of @ref RCC_APB1_Clock_Source */
AnnaBridge	171:3a7713b1edbc	281
AnnaBridge	171:3a7713b1edbc	282	} RCC_ClkInitTypeDef;
AnnaBridge	171:3a7713b1edbc	283
AnnaBridge	171:3a7713b1edbc	284	/**
AnnaBridge	171:3a7713b1edbc	285	* @}
AnnaBridge	171:3a7713b1edbc	286	*/
AnnaBridge	171:3a7713b1edbc	287
AnnaBridge	171:3a7713b1edbc	288	/* Exported constants --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	289	/** @defgroup RCC_Exported_Constants RCC Exported Constants
AnnaBridge	171:3a7713b1edbc	290	* @{
AnnaBridge	171:3a7713b1edbc	291	*/
AnnaBridge	171:3a7713b1edbc	292
AnnaBridge	171:3a7713b1edbc	293	/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
AnnaBridge	171:3a7713b1edbc	294	* @{
AnnaBridge	171:3a7713b1edbc	295	*/
AnnaBridge	171:3a7713b1edbc	296
AnnaBridge	171:3a7713b1edbc	297	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /!< HSE clock selected as PLL entry clock source /
AnnaBridge	171:3a7713b1edbc	298
AnnaBridge	171:3a7713b1edbc	299	/**
AnnaBridge	171:3a7713b1edbc	300	* @}
AnnaBridge	171:3a7713b1edbc	301	*/
AnnaBridge	171:3a7713b1edbc	302
AnnaBridge	171:3a7713b1edbc	303	/** @defgroup RCC_Oscillator_Type Oscillator Type
AnnaBridge	171:3a7713b1edbc	304	* @{
AnnaBridge	171:3a7713b1edbc	305	*/
AnnaBridge	171:3a7713b1edbc	306	#define RCC_OSCILLATORTYPE_NONE (0x00000000U)
AnnaBridge	171:3a7713b1edbc	307	#define RCC_OSCILLATORTYPE_HSE (0x00000001U)
AnnaBridge	171:3a7713b1edbc	308	#define RCC_OSCILLATORTYPE_HSI (0x00000002U)
AnnaBridge	171:3a7713b1edbc	309	#define RCC_OSCILLATORTYPE_LSE (0x00000004U)
AnnaBridge	171:3a7713b1edbc	310	#define RCC_OSCILLATORTYPE_LSI (0x00000008U)
AnnaBridge	171:3a7713b1edbc	311	#define RCC_OSCILLATORTYPE_HSI14 (0x00000010U)
AnnaBridge	171:3a7713b1edbc	312	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	171:3a7713b1edbc	313	#define RCC_OSCILLATORTYPE_HSI48 (0x00000020U)
AnnaBridge	171:3a7713b1edbc	314	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	171:3a7713b1edbc	315	/**
AnnaBridge	171:3a7713b1edbc	316	* @}
AnnaBridge	171:3a7713b1edbc	317	*/
AnnaBridge	171:3a7713b1edbc	318
AnnaBridge	171:3a7713b1edbc	319	/** @defgroup RCC_HSE_Config HSE Config
AnnaBridge	171:3a7713b1edbc	320	* @{
AnnaBridge	171:3a7713b1edbc	321	*/
AnnaBridge	171:3a7713b1edbc	322	#define RCC_HSE_OFF (0x00000000U) /!< HSE clock deactivation /
AnnaBridge	171:3a7713b1edbc	323	#define RCC_HSE_ON (0x00000001U) /!< HSE clock activation /
AnnaBridge	171:3a7713b1edbc	324	#define RCC_HSE_BYPASS (0x00000005U) /!< External clock source for HSE clock /
AnnaBridge	171:3a7713b1edbc	325	/**
AnnaBridge	171:3a7713b1edbc	326	* @}
AnnaBridge	171:3a7713b1edbc	327	*/
AnnaBridge	171:3a7713b1edbc	328
AnnaBridge	171:3a7713b1edbc	329	/** @defgroup RCC_LSE_Config LSE Config
AnnaBridge	171:3a7713b1edbc	330	* @{
AnnaBridge	171:3a7713b1edbc	331	*/
AnnaBridge	171:3a7713b1edbc	332	#define RCC_LSE_OFF (0x00000000U) /!< LSE clock deactivation /
AnnaBridge	171:3a7713b1edbc	333	#define RCC_LSE_ON (0x00000001U) /!< LSE clock activation /
AnnaBridge	171:3a7713b1edbc	334	#define RCC_LSE_BYPASS (0x00000005U) /!< External clock source for LSE clock /
AnnaBridge	171:3a7713b1edbc	335
AnnaBridge	171:3a7713b1edbc	336	/**
AnnaBridge	171:3a7713b1edbc	337	* @}
AnnaBridge	171:3a7713b1edbc	338	*/
AnnaBridge	171:3a7713b1edbc	339
AnnaBridge	171:3a7713b1edbc	340	/** @defgroup RCC_HSI_Config HSI Config
AnnaBridge	171:3a7713b1edbc	341	* @{
AnnaBridge	171:3a7713b1edbc	342	*/
AnnaBridge	171:3a7713b1edbc	343	#define RCC_HSI_OFF (0x00000000U) /!< HSI clock deactivation /
AnnaBridge	171:3a7713b1edbc	344	#define RCC_HSI_ON RCC_CR_HSION /!< HSI clock activation /
AnnaBridge	171:3a7713b1edbc	345
AnnaBridge	171:3a7713b1edbc	346	#define RCC_HSICALIBRATION_DEFAULT (0x10U) /* Default HSI calibration trimming value */
AnnaBridge	171:3a7713b1edbc	347
AnnaBridge	171:3a7713b1edbc	348	/**
AnnaBridge	171:3a7713b1edbc	349	* @}
AnnaBridge	171:3a7713b1edbc	350	*/
AnnaBridge	171:3a7713b1edbc	351
AnnaBridge	171:3a7713b1edbc	352	/** @defgroup RCC_HSI14_Config RCC HSI14 Config
AnnaBridge	171:3a7713b1edbc	353	* @{
AnnaBridge	171:3a7713b1edbc	354	*/
AnnaBridge	171:3a7713b1edbc	355	#define RCC_HSI14_OFF (0x00000000U)
AnnaBridge	171:3a7713b1edbc	356	#define RCC_HSI14_ON RCC_CR2_HSI14ON
AnnaBridge	171:3a7713b1edbc	357	#define RCC_HSI14_ADC_CONTROL (~RCC_CR2_HSI14DIS)
AnnaBridge	171:3a7713b1edbc	358
AnnaBridge	171:3a7713b1edbc	359	#define RCC_HSI14CALIBRATION_DEFAULT (0x10U) /* Default HSI14 calibration trimming value */
AnnaBridge	171:3a7713b1edbc	360	/**
AnnaBridge	171:3a7713b1edbc	361	* @}
AnnaBridge	171:3a7713b1edbc	362	*/
AnnaBridge	171:3a7713b1edbc	363
AnnaBridge	171:3a7713b1edbc	364	/** @defgroup RCC_LSI_Config LSI Config
AnnaBridge	171:3a7713b1edbc	365	* @{
AnnaBridge	171:3a7713b1edbc	366	*/
AnnaBridge	171:3a7713b1edbc	367	#define RCC_LSI_OFF (0x00000000U) /!< LSI clock deactivation /
AnnaBridge	171:3a7713b1edbc	368	#define RCC_LSI_ON RCC_CSR_LSION /!< LSI clock activation /
AnnaBridge	171:3a7713b1edbc	369
AnnaBridge	171:3a7713b1edbc	370	/**
AnnaBridge	171:3a7713b1edbc	371	* @}
AnnaBridge	171:3a7713b1edbc	372	*/
AnnaBridge	171:3a7713b1edbc	373
AnnaBridge	171:3a7713b1edbc	374	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	171:3a7713b1edbc	375	/** @defgroup RCC_HSI48_Config HSI48 Config
AnnaBridge	171:3a7713b1edbc	376	* @{
AnnaBridge	171:3a7713b1edbc	377	*/
AnnaBridge	171:3a7713b1edbc	378	#define RCC_HSI48_OFF ((uint8_t)0x00U)
AnnaBridge	171:3a7713b1edbc	379	#define RCC_HSI48_ON ((uint8_t)0x01U)
AnnaBridge	171:3a7713b1edbc	380
AnnaBridge	171:3a7713b1edbc	381	/**
AnnaBridge	171:3a7713b1edbc	382	* @}
AnnaBridge	171:3a7713b1edbc	383	*/
AnnaBridge	171:3a7713b1edbc	384	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	171:3a7713b1edbc	385
AnnaBridge	171:3a7713b1edbc	386	/** @defgroup RCC_PLL_Config PLL Config
AnnaBridge	171:3a7713b1edbc	387	* @{
AnnaBridge	171:3a7713b1edbc	388	*/
AnnaBridge	171:3a7713b1edbc	389	#define RCC_PLL_NONE (0x00000000U) /!< PLL is not configured /
AnnaBridge	171:3a7713b1edbc	390	#define RCC_PLL_OFF (0x00000001U) /!< PLL deactivation /
AnnaBridge	171:3a7713b1edbc	391	#define RCC_PLL_ON (0x00000002U) /!< PLL activation /
AnnaBridge	171:3a7713b1edbc	392
AnnaBridge	171:3a7713b1edbc	393	/**
AnnaBridge	171:3a7713b1edbc	394	* @}
AnnaBridge	171:3a7713b1edbc	395	*/
AnnaBridge	171:3a7713b1edbc	396
AnnaBridge	171:3a7713b1edbc	397	/** @defgroup RCC_System_Clock_Type System Clock Type
AnnaBridge	171:3a7713b1edbc	398	* @{
AnnaBridge	171:3a7713b1edbc	399	*/
AnnaBridge	171:3a7713b1edbc	400	#define RCC_CLOCKTYPE_SYSCLK (0x00000001U) /!< SYSCLK to configure /
AnnaBridge	171:3a7713b1edbc	401	#define RCC_CLOCKTYPE_HCLK (0x00000002U) /!< HCLK to configure /
AnnaBridge	171:3a7713b1edbc	402	#define RCC_CLOCKTYPE_PCLK1 (0x00000004U) /!< PCLK1 to configure /
AnnaBridge	171:3a7713b1edbc	403
AnnaBridge	171:3a7713b1edbc	404	/**
AnnaBridge	171:3a7713b1edbc	405	* @}
AnnaBridge	171:3a7713b1edbc	406	*/
AnnaBridge	171:3a7713b1edbc	407
AnnaBridge	171:3a7713b1edbc	408	/** @defgroup RCC_System_Clock_Source System Clock Source
AnnaBridge	171:3a7713b1edbc	409	* @{
AnnaBridge	171:3a7713b1edbc	410	*/
AnnaBridge	171:3a7713b1edbc	411	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selected as system clock /
AnnaBridge	171:3a7713b1edbc	412	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selected as system clock /
AnnaBridge	171:3a7713b1edbc	413	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /!< PLL selected as system clock /
AnnaBridge	171:3a7713b1edbc	414
AnnaBridge	171:3a7713b1edbc	415	/**
AnnaBridge	171:3a7713b1edbc	416	* @}
AnnaBridge	171:3a7713b1edbc	417	*/
AnnaBridge	171:3a7713b1edbc	418
AnnaBridge	171:3a7713b1edbc	419	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
AnnaBridge	171:3a7713b1edbc	420	* @{
AnnaBridge	171:3a7713b1edbc	421	*/
AnnaBridge	171:3a7713b1edbc	422	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
AnnaBridge	171:3a7713b1edbc	423	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
AnnaBridge	171:3a7713b1edbc	424	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /!< PLL used as system clock /
AnnaBridge	171:3a7713b1edbc	425
AnnaBridge	171:3a7713b1edbc	426	/**
AnnaBridge	171:3a7713b1edbc	427	* @}
AnnaBridge	171:3a7713b1edbc	428	*/
AnnaBridge	171:3a7713b1edbc	429
AnnaBridge	171:3a7713b1edbc	430	/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
AnnaBridge	171:3a7713b1edbc	431	* @{
AnnaBridge	171:3a7713b1edbc	432	*/
AnnaBridge	171:3a7713b1edbc	433	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
AnnaBridge	171:3a7713b1edbc	434	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
AnnaBridge	171:3a7713b1edbc	435	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
AnnaBridge	171:3a7713b1edbc	436	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
AnnaBridge	171:3a7713b1edbc	437	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
AnnaBridge	171:3a7713b1edbc	438	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
AnnaBridge	171:3a7713b1edbc	439	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
AnnaBridge	171:3a7713b1edbc	440	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
AnnaBridge	171:3a7713b1edbc	441	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
AnnaBridge	171:3a7713b1edbc	442
AnnaBridge	171:3a7713b1edbc	443	/**
AnnaBridge	171:3a7713b1edbc	444	* @}
AnnaBridge	171:3a7713b1edbc	445	*/
AnnaBridge	171:3a7713b1edbc	446
AnnaBridge	171:3a7713b1edbc	447	/** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source
AnnaBridge	171:3a7713b1edbc	448	* @{
AnnaBridge	171:3a7713b1edbc	449	*/
AnnaBridge	171:3a7713b1edbc	450	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE_DIV1 /!< HCLK not divided /
AnnaBridge	171:3a7713b1edbc	451	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE_DIV2 /!< HCLK divided by 2 /
AnnaBridge	171:3a7713b1edbc	452	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE_DIV4 /!< HCLK divided by 4 /
AnnaBridge	171:3a7713b1edbc	453	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE_DIV8 /!< HCLK divided by 8 /
AnnaBridge	171:3a7713b1edbc	454	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE_DIV16 /!< HCLK divided by 16 /
AnnaBridge	171:3a7713b1edbc	455
AnnaBridge	171:3a7713b1edbc	456	/**
AnnaBridge	171:3a7713b1edbc	457	* @}
AnnaBridge	171:3a7713b1edbc	458	*/
AnnaBridge	171:3a7713b1edbc	459
AnnaBridge	171:3a7713b1edbc	460	/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
AnnaBridge	171:3a7713b1edbc	461	* @{
AnnaBridge	171:3a7713b1edbc	462	*/
AnnaBridge	171:3a7713b1edbc	463	#define RCC_RTCCLKSOURCE_NO_CLK (0x00000000U) /!< No clock /
AnnaBridge	171:3a7713b1edbc	464	#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /!< LSE oscillator clock used as RTC clock /
AnnaBridge	171:3a7713b1edbc	465	#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /!< LSI oscillator clock used as RTC clock /
AnnaBridge	171:3a7713b1edbc	466	#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE /!< HSE oscillator clock divided by 32 used as RTC clock /
AnnaBridge	171:3a7713b1edbc	467	/**
AnnaBridge	171:3a7713b1edbc	468	* @}
AnnaBridge	171:3a7713b1edbc	469	*/
AnnaBridge	171:3a7713b1edbc	470
AnnaBridge	171:3a7713b1edbc	471	/** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
AnnaBridge	171:3a7713b1edbc	472	* @{
AnnaBridge	171:3a7713b1edbc	473	*/
AnnaBridge	171:3a7713b1edbc	474	#define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2
AnnaBridge	171:3a7713b1edbc	475	#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
AnnaBridge	171:3a7713b1edbc	476	#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
AnnaBridge	171:3a7713b1edbc	477	#define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5
AnnaBridge	171:3a7713b1edbc	478	#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
AnnaBridge	171:3a7713b1edbc	479	#define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7
AnnaBridge	171:3a7713b1edbc	480	#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
AnnaBridge	171:3a7713b1edbc	481	#define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9
AnnaBridge	171:3a7713b1edbc	482	#define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10
AnnaBridge	171:3a7713b1edbc	483	#define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11
AnnaBridge	171:3a7713b1edbc	484	#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
AnnaBridge	171:3a7713b1edbc	485	#define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13
AnnaBridge	171:3a7713b1edbc	486	#define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14
AnnaBridge	171:3a7713b1edbc	487	#define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15
AnnaBridge	171:3a7713b1edbc	488	#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
AnnaBridge	171:3a7713b1edbc	489
AnnaBridge	171:3a7713b1edbc	490	/**
AnnaBridge	171:3a7713b1edbc	491	* @}
AnnaBridge	171:3a7713b1edbc	492	*/
AnnaBridge	171:3a7713b1edbc	493
AnnaBridge	171:3a7713b1edbc	494	/** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor
AnnaBridge	171:3a7713b1edbc	495	* @{
AnnaBridge	171:3a7713b1edbc	496	*/
AnnaBridge	171:3a7713b1edbc	497
AnnaBridge	171:3a7713b1edbc	498	#define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
AnnaBridge	171:3a7713b1edbc	499	#define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
AnnaBridge	171:3a7713b1edbc	500	#define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
AnnaBridge	171:3a7713b1edbc	501	#define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
AnnaBridge	171:3a7713b1edbc	502	#define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
AnnaBridge	171:3a7713b1edbc	503	#define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
AnnaBridge	171:3a7713b1edbc	504	#define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
AnnaBridge	171:3a7713b1edbc	505	#define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
AnnaBridge	171:3a7713b1edbc	506	#define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
AnnaBridge	171:3a7713b1edbc	507	#define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
AnnaBridge	171:3a7713b1edbc	508	#define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
AnnaBridge	171:3a7713b1edbc	509	#define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
AnnaBridge	171:3a7713b1edbc	510	#define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
AnnaBridge	171:3a7713b1edbc	511	#define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
AnnaBridge	171:3a7713b1edbc	512	#define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
AnnaBridge	171:3a7713b1edbc	513	#define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
AnnaBridge	171:3a7713b1edbc	514
AnnaBridge	171:3a7713b1edbc	515	/**
AnnaBridge	171:3a7713b1edbc	516	* @}
AnnaBridge	171:3a7713b1edbc	517	*/
AnnaBridge	171:3a7713b1edbc	518
AnnaBridge	171:3a7713b1edbc	519
AnnaBridge	171:3a7713b1edbc	520	/** @defgroup RCC_USART1_Clock_Source RCC USART1 Clock Source
AnnaBridge	171:3a7713b1edbc	521	* @{
AnnaBridge	171:3a7713b1edbc	522	*/
AnnaBridge	171:3a7713b1edbc	523	#define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK
AnnaBridge	171:3a7713b1edbc	524	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
AnnaBridge	171:3a7713b1edbc	525	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
AnnaBridge	171:3a7713b1edbc	526	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
AnnaBridge	171:3a7713b1edbc	527
AnnaBridge	171:3a7713b1edbc	528	/**
AnnaBridge	171:3a7713b1edbc	529	* @}
AnnaBridge	171:3a7713b1edbc	530	*/
AnnaBridge	171:3a7713b1edbc	531
AnnaBridge	171:3a7713b1edbc	532	/** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source
AnnaBridge	171:3a7713b1edbc	533	* @{
AnnaBridge	171:3a7713b1edbc	534	*/
AnnaBridge	171:3a7713b1edbc	535	#define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI
AnnaBridge	171:3a7713b1edbc	536	#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK
AnnaBridge	171:3a7713b1edbc	537
AnnaBridge	171:3a7713b1edbc	538	/**
AnnaBridge	171:3a7713b1edbc	539	* @}
AnnaBridge	171:3a7713b1edbc	540	*/
AnnaBridge	171:3a7713b1edbc	541	/** @defgroup RCC_MCO_Index MCO Index
AnnaBridge	171:3a7713b1edbc	542	* @{
AnnaBridge	171:3a7713b1edbc	543	*/
AnnaBridge	171:3a7713b1edbc	544	#define RCC_MCO1 (0x00000000U)
AnnaBridge	171:3a7713b1edbc	545	#define RCC_MCO RCC_MCO1 /!< MCO1 to be compliant with other families with 2 MCOs/
AnnaBridge	171:3a7713b1edbc	546
AnnaBridge	171:3a7713b1edbc	547	/**
AnnaBridge	171:3a7713b1edbc	548	* @}
AnnaBridge	171:3a7713b1edbc	549	*/
AnnaBridge	171:3a7713b1edbc	550
AnnaBridge	171:3a7713b1edbc	551	/** @defgroup RCC_MCO_Clock_Source RCC MCO Clock Source
AnnaBridge	171:3a7713b1edbc	552	* @{
AnnaBridge	171:3a7713b1edbc	553	*/
AnnaBridge	171:3a7713b1edbc	554	#define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK
AnnaBridge	171:3a7713b1edbc	555	#define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI
AnnaBridge	171:3a7713b1edbc	556	#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE
AnnaBridge	171:3a7713b1edbc	557	#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
AnnaBridge	171:3a7713b1edbc	558	#define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI
AnnaBridge	171:3a7713b1edbc	559	#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE
AnnaBridge	171:3a7713b1edbc	560	#define RCC_MCO1SOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
AnnaBridge	171:3a7713b1edbc	561	#define RCC_MCO1SOURCE_HSI14 RCC_CFGR_MCO_HSI14
AnnaBridge	171:3a7713b1edbc	562
AnnaBridge	171:3a7713b1edbc	563	/**
AnnaBridge	171:3a7713b1edbc	564	* @}
AnnaBridge	171:3a7713b1edbc	565	*/
AnnaBridge	171:3a7713b1edbc	566
AnnaBridge	171:3a7713b1edbc	567	/** @defgroup RCC_Interrupt Interrupts
AnnaBridge	171:3a7713b1edbc	568	* @{
AnnaBridge	171:3a7713b1edbc	569	*/
AnnaBridge	171:3a7713b1edbc	570	#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /!< LSI Ready Interrupt flag /
AnnaBridge	171:3a7713b1edbc	571	#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /!< LSE Ready Interrupt flag /
AnnaBridge	171:3a7713b1edbc	572	#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /!< HSI Ready Interrupt flag /
AnnaBridge	171:3a7713b1edbc	573	#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /!< HSE Ready Interrupt flag /
AnnaBridge	171:3a7713b1edbc	574	#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /!< PLL Ready Interrupt flag /
AnnaBridge	171:3a7713b1edbc	575	#define RCC_IT_HSI14RDY ((uint8_t)RCC_CIR_HSI14RDYF) /!< HSI14 Ready Interrupt flag /
AnnaBridge	171:3a7713b1edbc	576	#if defined(RCC_CIR_HSI48RDYF)
AnnaBridge	171:3a7713b1edbc	577	#define RCC_IT_HSI48RDY ((uint8_t)RCC_CIR_HSI48RDYF) /!< HSI48 Ready Interrupt flag /
AnnaBridge	171:3a7713b1edbc	578	#endif
AnnaBridge	171:3a7713b1edbc	579	#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /!< Clock Security System Interrupt flag /
AnnaBridge	171:3a7713b1edbc	580	/**
AnnaBridge	171:3a7713b1edbc	581	* @}
AnnaBridge	171:3a7713b1edbc	582	*/
AnnaBridge	171:3a7713b1edbc	583
AnnaBridge	171:3a7713b1edbc	584	/** @defgroup RCC_Flag Flags
AnnaBridge	171:3a7713b1edbc	585	* Elements values convention: XXXYYYYYb
AnnaBridge	171:3a7713b1edbc	586	* - YYYYY : Flag position in the register
AnnaBridge	171:3a7713b1edbc	587	* - XXX : Register index
AnnaBridge	171:3a7713b1edbc	588	* - 001: CR register
AnnaBridge	171:3a7713b1edbc	589	* - 010: CR2 register
AnnaBridge	171:3a7713b1edbc	590	* - 011: BDCR register
AnnaBridge	171:3a7713b1edbc	591	* - 0100: CSR register
AnnaBridge	171:3a7713b1edbc	592	* @{
AnnaBridge	171:3a7713b1edbc	593	*/
AnnaBridge	171:3a7713b1edbc	594	/* Flags in the CR register */
AnnaBridge	171:3a7713b1edbc	595	#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) \| RCC_CR_HSIRDY_BitNumber))
AnnaBridge	171:3a7713b1edbc	596	#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) \| RCC_CR_HSERDY_BitNumber))
AnnaBridge	171:3a7713b1edbc	597	#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) \| RCC_CR_PLLRDY_BitNumber))
AnnaBridge	171:3a7713b1edbc	598	/* Flags in the CR2 register */
AnnaBridge	171:3a7713b1edbc	599	#define RCC_FLAG_HSI14RDY ((uint8_t)((CR2_REG_INDEX << 5U) \| RCC_CR2_HSI14RDY_BitNumber))
AnnaBridge	171:3a7713b1edbc	600
AnnaBridge	171:3a7713b1edbc	601	/* Flags in the CSR register */
AnnaBridge	171:3a7713b1edbc	602	#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) \| RCC_CSR_LSIRDY_BitNumber))
AnnaBridge	171:3a7713b1edbc	603	#if defined(RCC_CSR_V18PWRRSTF)
AnnaBridge	171:3a7713b1edbc	604	#define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5U) \| RCC_CSR_V18PWRRSTF_BitNumber))
AnnaBridge	171:3a7713b1edbc	605	#endif
AnnaBridge	171:3a7713b1edbc	606	#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5U) \| RCC_CSR_OBLRSTF_BitNumber))
AnnaBridge	171:3a7713b1edbc	607	#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) \| RCC_CSR_PINRSTF_BitNumber)) /!< PIN reset flag /
AnnaBridge	171:3a7713b1edbc	608	#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) \| RCC_CSR_PORRSTF_BitNumber)) /!< POR/PDR reset flag /
AnnaBridge	171:3a7713b1edbc	609	#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) \| RCC_CSR_SFTRSTF_BitNumber)) /!< Software Reset flag /
AnnaBridge	171:3a7713b1edbc	610	#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) \| RCC_CSR_IWDGRSTF_BitNumber)) /!< Independent Watchdog reset flag /
AnnaBridge	171:3a7713b1edbc	611	#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) \| RCC_CSR_WWDGRSTF_BitNumber)) /!< Window watchdog reset flag /
AnnaBridge	171:3a7713b1edbc	612	#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) \| RCC_CSR_LPWRRSTF_BitNumber)) /!< Low-Power reset flag /
AnnaBridge	171:3a7713b1edbc	613
AnnaBridge	171:3a7713b1edbc	614	/* Flags in the BDCR register */
AnnaBridge	171:3a7713b1edbc	615	#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) \| RCC_BDCR_LSERDY_BitNumber)) /!< External Low Speed oscillator Ready /
AnnaBridge	171:3a7713b1edbc	616
AnnaBridge	171:3a7713b1edbc	617	/**
AnnaBridge	171:3a7713b1edbc	618	* @}
AnnaBridge	171:3a7713b1edbc	619	*/
AnnaBridge	171:3a7713b1edbc	620
AnnaBridge	171:3a7713b1edbc	621	/**
AnnaBridge	171:3a7713b1edbc	622	* @}
AnnaBridge	171:3a7713b1edbc	623	*/
AnnaBridge	171:3a7713b1edbc	624
AnnaBridge	171:3a7713b1edbc	625	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	626
AnnaBridge	171:3a7713b1edbc	627	/** @defgroup RCC_Exported_Macros RCC Exported Macros
AnnaBridge	171:3a7713b1edbc	628	* @{
AnnaBridge	171:3a7713b1edbc	629	*/
AnnaBridge	171:3a7713b1edbc	630
AnnaBridge	171:3a7713b1edbc	631	/** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable
AnnaBridge	171:3a7713b1edbc	632	* @brief Enable or disable the AHB peripheral clock.
AnnaBridge	171:3a7713b1edbc	633	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	171:3a7713b1edbc	634	* is disabled and the application software has to enable this clock before
AnnaBridge	171:3a7713b1edbc	635	* using it.
AnnaBridge	171:3a7713b1edbc	636	* @{
AnnaBridge	171:3a7713b1edbc	637	*/
AnnaBridge	171:3a7713b1edbc	638	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	639	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	640	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
AnnaBridge	171:3a7713b1edbc	641	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	642	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
AnnaBridge	171:3a7713b1edbc	643	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	644	} while(0U)
AnnaBridge	171:3a7713b1edbc	645	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	646	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	647	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
AnnaBridge	171:3a7713b1edbc	648	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	649	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
AnnaBridge	171:3a7713b1edbc	650	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	651	} while(0U)
AnnaBridge	171:3a7713b1edbc	652	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	653	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	654	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
AnnaBridge	171:3a7713b1edbc	655	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	656	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
AnnaBridge	171:3a7713b1edbc	657	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	658	} while(0U)
AnnaBridge	171:3a7713b1edbc	659	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	660	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	661	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
AnnaBridge	171:3a7713b1edbc	662	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	663	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
AnnaBridge	171:3a7713b1edbc	664	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	665	} while(0U)
AnnaBridge	171:3a7713b1edbc	666	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	667	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	668	SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
AnnaBridge	171:3a7713b1edbc	669	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	670	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
AnnaBridge	171:3a7713b1edbc	671	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	672	} while(0U)
AnnaBridge	171:3a7713b1edbc	673	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	674	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	675	SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
AnnaBridge	171:3a7713b1edbc	676	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	677	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
AnnaBridge	171:3a7713b1edbc	678	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	679	} while(0U)
AnnaBridge	171:3a7713b1edbc	680	#define __HAL_RCC_SRAM_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	681	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	682	SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
AnnaBridge	171:3a7713b1edbc	683	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	684	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
AnnaBridge	171:3a7713b1edbc	685	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	686	} while(0U)
AnnaBridge	171:3a7713b1edbc	687	#define __HAL_RCC_FLITF_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	688	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	689	SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
AnnaBridge	171:3a7713b1edbc	690	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	691	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
AnnaBridge	171:3a7713b1edbc	692	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	693	} while(0U)
AnnaBridge	171:3a7713b1edbc	694
AnnaBridge	171:3a7713b1edbc	695	#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
AnnaBridge	171:3a7713b1edbc	696	#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
AnnaBridge	171:3a7713b1edbc	697	#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
AnnaBridge	171:3a7713b1edbc	698	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
AnnaBridge	171:3a7713b1edbc	699	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
AnnaBridge	171:3a7713b1edbc	700	#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
AnnaBridge	171:3a7713b1edbc	701	#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
AnnaBridge	171:3a7713b1edbc	702	#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
AnnaBridge	171:3a7713b1edbc	703	/**
AnnaBridge	171:3a7713b1edbc	704	* @}
AnnaBridge	171:3a7713b1edbc	705	*/
AnnaBridge	171:3a7713b1edbc	706
AnnaBridge	171:3a7713b1edbc	707	/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
AnnaBridge	171:3a7713b1edbc	708	* @brief Get the enable or disable status of the AHB peripheral clock.
AnnaBridge	171:3a7713b1edbc	709	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	171:3a7713b1edbc	710	* is disabled and the application software has to enable this clock before
AnnaBridge	171:3a7713b1edbc	711	* using it.
AnnaBridge	171:3a7713b1edbc	712	* @{
AnnaBridge	171:3a7713b1edbc	713	*/
AnnaBridge	171:3a7713b1edbc	714	#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	715	#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	716	#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	717	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	718	#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	719	#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	720	#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	721	#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	722	#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	723	#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	724	#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	725	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	726	#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	727	#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	728	#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	729	#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	730	/**
AnnaBridge	171:3a7713b1edbc	731	* @}
AnnaBridge	171:3a7713b1edbc	732	*/
AnnaBridge	171:3a7713b1edbc	733
AnnaBridge	171:3a7713b1edbc	734	/** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable
AnnaBridge	171:3a7713b1edbc	735	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
AnnaBridge	171:3a7713b1edbc	736	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	171:3a7713b1edbc	737	* is disabled and the application software has to enable this clock before
AnnaBridge	171:3a7713b1edbc	738	* using it.
AnnaBridge	171:3a7713b1edbc	739	* @{
AnnaBridge	171:3a7713b1edbc	740	*/
AnnaBridge	171:3a7713b1edbc	741	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	742	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	743	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	171:3a7713b1edbc	744	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	745	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
AnnaBridge	171:3a7713b1edbc	746	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	747	} while(0U)
AnnaBridge	171:3a7713b1edbc	748	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	749	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	750	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge	171:3a7713b1edbc	751	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	752	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
AnnaBridge	171:3a7713b1edbc	753	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	754	} while(0U)
AnnaBridge	171:3a7713b1edbc	755	#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	756	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	757	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
AnnaBridge	171:3a7713b1edbc	758	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	759	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
AnnaBridge	171:3a7713b1edbc	760	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	761	} while(0U)
AnnaBridge	171:3a7713b1edbc	762	#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	763	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	764	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
AnnaBridge	171:3a7713b1edbc	765	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	766	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
AnnaBridge	171:3a7713b1edbc	767	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	768	} while(0U)
AnnaBridge	171:3a7713b1edbc	769	#define __HAL_RCC_PWR_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	770	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	771	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
AnnaBridge	171:3a7713b1edbc	772	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	773	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
AnnaBridge	171:3a7713b1edbc	774	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	775	} while(0U)
AnnaBridge	171:3a7713b1edbc	776
AnnaBridge	171:3a7713b1edbc	777	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
AnnaBridge	171:3a7713b1edbc	778	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
AnnaBridge	171:3a7713b1edbc	779	#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
AnnaBridge	171:3a7713b1edbc	780	#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
AnnaBridge	171:3a7713b1edbc	781	#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
AnnaBridge	171:3a7713b1edbc	782	/**
AnnaBridge	171:3a7713b1edbc	783	* @}
AnnaBridge	171:3a7713b1edbc	784	*/
AnnaBridge	171:3a7713b1edbc	785
AnnaBridge	171:3a7713b1edbc	786	/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
AnnaBridge	171:3a7713b1edbc	787	* @brief Get the enable or disable status of the APB1 peripheral clock.
AnnaBridge	171:3a7713b1edbc	788	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	171:3a7713b1edbc	789	* is disabled and the application software has to enable this clock before
AnnaBridge	171:3a7713b1edbc	790	* using it.
AnnaBridge	171:3a7713b1edbc	791	* @{
AnnaBridge	171:3a7713b1edbc	792	*/
AnnaBridge	171:3a7713b1edbc	793	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	794	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	795	#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	796	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	797	#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
AnnaBridge	171:3a7713b1edbc	798	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	799	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	800	#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	801	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	802	#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
AnnaBridge	171:3a7713b1edbc	803	/**
AnnaBridge	171:3a7713b1edbc	804	* @}
AnnaBridge	171:3a7713b1edbc	805	*/
AnnaBridge	171:3a7713b1edbc	806
AnnaBridge	171:3a7713b1edbc	807
AnnaBridge	171:3a7713b1edbc	808	/** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable
AnnaBridge	171:3a7713b1edbc	809	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
AnnaBridge	171:3a7713b1edbc	810	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	171:3a7713b1edbc	811	* is disabled and the application software has to enable this clock before
AnnaBridge	171:3a7713b1edbc	812	* using it.
AnnaBridge	171:3a7713b1edbc	813	* @{
AnnaBridge	171:3a7713b1edbc	814	*/
AnnaBridge	171:3a7713b1edbc	815	#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	816	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	817	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
AnnaBridge	171:3a7713b1edbc	818	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	819	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
AnnaBridge	171:3a7713b1edbc	820	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	821	} while(0U)
AnnaBridge	171:3a7713b1edbc	822	#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	823	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	824	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
AnnaBridge	171:3a7713b1edbc	825	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	826	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
AnnaBridge	171:3a7713b1edbc	827	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	828	} while(0U)
AnnaBridge	171:3a7713b1edbc	829	#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	830	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	831	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
AnnaBridge	171:3a7713b1edbc	832	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	833	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
AnnaBridge	171:3a7713b1edbc	834	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	835	} while(0U)
AnnaBridge	171:3a7713b1edbc	836	#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	837	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	838	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
AnnaBridge	171:3a7713b1edbc	839	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	840	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
AnnaBridge	171:3a7713b1edbc	841	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	842	} while(0U)
AnnaBridge	171:3a7713b1edbc	843	#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	844	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	845	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
AnnaBridge	171:3a7713b1edbc	846	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	847	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
AnnaBridge	171:3a7713b1edbc	848	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	849	} while(0U)
AnnaBridge	171:3a7713b1edbc	850	#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	851	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	852	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
AnnaBridge	171:3a7713b1edbc	853	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	854	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
AnnaBridge	171:3a7713b1edbc	855	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	856	} while(0U)
AnnaBridge	171:3a7713b1edbc	857	#define __HAL_RCC_USART1_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	858	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	859	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
AnnaBridge	171:3a7713b1edbc	860	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	861	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
AnnaBridge	171:3a7713b1edbc	862	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	863	} while(0U)
AnnaBridge	171:3a7713b1edbc	864	#define __HAL_RCC_DBGMCU_CLK_ENABLE() do { \
AnnaBridge	171:3a7713b1edbc	865	__IO uint32_t tmpreg; \
AnnaBridge	171:3a7713b1edbc	866	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\
AnnaBridge	171:3a7713b1edbc	867	/* Delay after an RCC peripheral clock enabling */\
AnnaBridge	171:3a7713b1edbc	868	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN);\
AnnaBridge	171:3a7713b1edbc	869	UNUSED(tmpreg); \
AnnaBridge	171:3a7713b1edbc	870	} while(0U)
AnnaBridge	171:3a7713b1edbc	871
AnnaBridge	171:3a7713b1edbc	872	#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
AnnaBridge	171:3a7713b1edbc	873	#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
AnnaBridge	171:3a7713b1edbc	874	#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
AnnaBridge	171:3a7713b1edbc	875	#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
AnnaBridge	171:3a7713b1edbc	876	#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
AnnaBridge	171:3a7713b1edbc	877	#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
AnnaBridge	171:3a7713b1edbc	878	#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
AnnaBridge	171:3a7713b1edbc	879	#define __HAL_RCC_DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DBGMCUEN))
AnnaBridge	171:3a7713b1edbc	880	/**
AnnaBridge	171:3a7713b1edbc	881	* @}
AnnaBridge	171:3a7713b1edbc	882	*/
AnnaBridge	171:3a7713b1edbc	883
AnnaBridge	171:3a7713b1edbc	884	/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
AnnaBridge	171:3a7713b1edbc	885	* @brief Get the enable or disable status of the APB2 peripheral clock.
AnnaBridge	171:3a7713b1edbc	886	* @note After reset, the peripheral clock (used for registers read/write access)
AnnaBridge	171:3a7713b1edbc	887	* is disabled and the application software has to enable this clock before
AnnaBridge	171:3a7713b1edbc	888	* using it.
AnnaBridge	171:3a7713b1edbc	889	* @{
AnnaBridge	171:3a7713b1edbc	890	*/
AnnaBridge	171:3a7713b1edbc	891	#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	892	#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	893	#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	894	#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	895	#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	896	#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	897	#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
AnnaBridge	171:3a7713b1edbc	898	#define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DBGMCUEN)) != RESET)
AnnaBridge	171:3a7713b1edbc	899	#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	900	#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	901	#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	902	#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	903	#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	904	#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	905	#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
AnnaBridge	171:3a7713b1edbc	906	#define __HAL_RCC_DBGMCU_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DBGMCUEN)) == RESET)
AnnaBridge	171:3a7713b1edbc	907	/**
AnnaBridge	171:3a7713b1edbc	908	* @}
AnnaBridge	171:3a7713b1edbc	909	*/
AnnaBridge	171:3a7713b1edbc	910
AnnaBridge	171:3a7713b1edbc	911	/** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset
AnnaBridge	171:3a7713b1edbc	912	* @brief Force or release AHB peripheral reset.
AnnaBridge	171:3a7713b1edbc	913	* @{
AnnaBridge	171:3a7713b1edbc	914	*/
AnnaBridge	171:3a7713b1edbc	915	#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU)
AnnaBridge	171:3a7713b1edbc	916	#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOARST))
AnnaBridge	171:3a7713b1edbc	917	#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOBRST))
AnnaBridge	171:3a7713b1edbc	918	#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOCRST))
AnnaBridge	171:3a7713b1edbc	919	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOFRST))
AnnaBridge	171:3a7713b1edbc	920
AnnaBridge	171:3a7713b1edbc	921	#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U)
AnnaBridge	171:3a7713b1edbc	922	#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
AnnaBridge	171:3a7713b1edbc	923	#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
AnnaBridge	171:3a7713b1edbc	924	#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
AnnaBridge	171:3a7713b1edbc	925	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
AnnaBridge	171:3a7713b1edbc	926	/**
AnnaBridge	171:3a7713b1edbc	927	* @}
AnnaBridge	171:3a7713b1edbc	928	*/
AnnaBridge	171:3a7713b1edbc	929
AnnaBridge	171:3a7713b1edbc	930	/** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset
AnnaBridge	171:3a7713b1edbc	931	* @brief Force or release APB1 peripheral reset.
AnnaBridge	171:3a7713b1edbc	932	* @{
AnnaBridge	171:3a7713b1edbc	933	*/
AnnaBridge	171:3a7713b1edbc	934	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
AnnaBridge	171:3a7713b1edbc	935	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
AnnaBridge	171:3a7713b1edbc	936	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
AnnaBridge	171:3a7713b1edbc	937	#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
AnnaBridge	171:3a7713b1edbc	938	#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
AnnaBridge	171:3a7713b1edbc	939	#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
AnnaBridge	171:3a7713b1edbc	940
AnnaBridge	171:3a7713b1edbc	941	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U)
AnnaBridge	171:3a7713b1edbc	942	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
AnnaBridge	171:3a7713b1edbc	943	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
AnnaBridge	171:3a7713b1edbc	944	#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
AnnaBridge	171:3a7713b1edbc	945	#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
AnnaBridge	171:3a7713b1edbc	946	#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
AnnaBridge	171:3a7713b1edbc	947	/**
AnnaBridge	171:3a7713b1edbc	948	* @}
AnnaBridge	171:3a7713b1edbc	949	*/
AnnaBridge	171:3a7713b1edbc	950
AnnaBridge	171:3a7713b1edbc	951	/** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset
AnnaBridge	171:3a7713b1edbc	952	* @brief Force or release APB2 peripheral reset.
AnnaBridge	171:3a7713b1edbc	953	* @{
AnnaBridge	171:3a7713b1edbc	954	*/
AnnaBridge	171:3a7713b1edbc	955	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
AnnaBridge	171:3a7713b1edbc	956	#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
AnnaBridge	171:3a7713b1edbc	957	#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADC1RST))
AnnaBridge	171:3a7713b1edbc	958	#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
AnnaBridge	171:3a7713b1edbc	959	#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
AnnaBridge	171:3a7713b1edbc	960	#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
AnnaBridge	171:3a7713b1edbc	961	#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM16RST))
AnnaBridge	171:3a7713b1edbc	962	#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM17RST))
AnnaBridge	171:3a7713b1edbc	963	#define __HAL_RCC_DBGMCU_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DBGMCURST))
AnnaBridge	171:3a7713b1edbc	964
AnnaBridge	171:3a7713b1edbc	965	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U)
AnnaBridge	171:3a7713b1edbc	966	#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
AnnaBridge	171:3a7713b1edbc	967	#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
AnnaBridge	171:3a7713b1edbc	968	#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
AnnaBridge	171:3a7713b1edbc	969	#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
AnnaBridge	171:3a7713b1edbc	970	#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
AnnaBridge	171:3a7713b1edbc	971	#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
AnnaBridge	171:3a7713b1edbc	972	#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
AnnaBridge	171:3a7713b1edbc	973	#define __HAL_RCC_DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DBGMCURST))
AnnaBridge	171:3a7713b1edbc	974	/**
AnnaBridge	171:3a7713b1edbc	975	* @}
AnnaBridge	171:3a7713b1edbc	976	*/
AnnaBridge	171:3a7713b1edbc	977	/** @defgroup RCC_HSI_Configuration HSI Configuration
AnnaBridge	171:3a7713b1edbc	978	* @{
AnnaBridge	171:3a7713b1edbc	979	*/
AnnaBridge	171:3a7713b1edbc	980
AnnaBridge	171:3a7713b1edbc	981	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
AnnaBridge	171:3a7713b1edbc	982	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge	171:3a7713b1edbc	983	* @note HSI can not be stopped if it is used as system clock source. In this case,
AnnaBridge	171:3a7713b1edbc	984	* you have to select another source of the system clock then stop the HSI.
AnnaBridge	171:3a7713b1edbc	985	* @note After enabling the HSI, the application software should wait on HSIRDY
AnnaBridge	171:3a7713b1edbc	986	* flag to be set indicating that HSI clock is stable and can be used as
AnnaBridge	171:3a7713b1edbc	987	* system clock source.
AnnaBridge	171:3a7713b1edbc	988	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
AnnaBridge	171:3a7713b1edbc	989	* clock cycles.
AnnaBridge	171:3a7713b1edbc	990	*/
AnnaBridge	171:3a7713b1edbc	991	#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
AnnaBridge	171:3a7713b1edbc	992	#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
AnnaBridge	171:3a7713b1edbc	993
AnnaBridge	171:3a7713b1edbc	994	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
AnnaBridge	171:3a7713b1edbc	995	* @note The calibration is used to compensate for the variations in voltage
AnnaBridge	171:3a7713b1edbc	996	* and temperature that influence the frequency of the internal HSI RC.
AnnaBridge	171:3a7713b1edbc	997	* @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
AnnaBridge	171:3a7713b1edbc	998	* (default is RCC_HSICALIBRATION_DEFAULT).
AnnaBridge	171:3a7713b1edbc	999	* This parameter must be a number between 0 and 0x1F.
AnnaBridge	171:3a7713b1edbc	1000	*/
AnnaBridge	171:3a7713b1edbc	1001	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
AnnaBridge	171:3a7713b1edbc	1002	MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_BitNumber)
AnnaBridge	171:3a7713b1edbc	1003
AnnaBridge	171:3a7713b1edbc	1004	/**
AnnaBridge	171:3a7713b1edbc	1005	* @}
AnnaBridge	171:3a7713b1edbc	1006	*/
AnnaBridge	171:3a7713b1edbc	1007
AnnaBridge	171:3a7713b1edbc	1008	/** @defgroup RCC_LSI_Configuration LSI Configuration
AnnaBridge	171:3a7713b1edbc	1009	* @{
AnnaBridge	171:3a7713b1edbc	1010	*/
AnnaBridge	171:3a7713b1edbc	1011
AnnaBridge	171:3a7713b1edbc	1012	/** @brief Macro to enable the Internal Low Speed oscillator (LSI).
AnnaBridge	171:3a7713b1edbc	1013	* @note After enabling the LSI, the application software should wait on
AnnaBridge	171:3a7713b1edbc	1014	* LSIRDY flag to be set indicating that LSI clock is stable and can
AnnaBridge	171:3a7713b1edbc	1015	* be used to clock the IWDG and/or the RTC.
AnnaBridge	171:3a7713b1edbc	1016	*/
AnnaBridge	171:3a7713b1edbc	1017	#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
AnnaBridge	171:3a7713b1edbc	1018
AnnaBridge	171:3a7713b1edbc	1019	/** @brief Macro to disable the Internal Low Speed oscillator (LSI).
AnnaBridge	171:3a7713b1edbc	1020	* @note LSI can not be disabled if the IWDG is running.
AnnaBridge	171:3a7713b1edbc	1021	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
AnnaBridge	171:3a7713b1edbc	1022	* clock cycles.
AnnaBridge	171:3a7713b1edbc	1023	*/
AnnaBridge	171:3a7713b1edbc	1024	#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
AnnaBridge	171:3a7713b1edbc	1025
AnnaBridge	171:3a7713b1edbc	1026	/**
AnnaBridge	171:3a7713b1edbc	1027	* @}
AnnaBridge	171:3a7713b1edbc	1028	*/
AnnaBridge	171:3a7713b1edbc	1029
AnnaBridge	171:3a7713b1edbc	1030	/** @defgroup RCC_HSE_Configuration HSE Configuration
AnnaBridge	171:3a7713b1edbc	1031	* @{
AnnaBridge	171:3a7713b1edbc	1032	*/
AnnaBridge	171:3a7713b1edbc	1033
AnnaBridge	171:3a7713b1edbc	1034	/**
AnnaBridge	171:3a7713b1edbc	1035	* @brief Macro to configure the External High Speed oscillator (HSE).
AnnaBridge	171:3a7713b1edbc	1036	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
AnnaBridge	171:3a7713b1edbc	1037	* supported by this macro. User should request a transition to HSE Off
AnnaBridge	171:3a7713b1edbc	1038	* first and then HSE On or HSE Bypass.
AnnaBridge	171:3a7713b1edbc	1039	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
AnnaBridge	171:3a7713b1edbc	1040	* software should wait on HSERDY flag to be set indicating that HSE clock
AnnaBridge	171:3a7713b1edbc	1041	* is stable and can be used to clock the PLL and/or system clock.
AnnaBridge	171:3a7713b1edbc	1042	* @note HSE state can not be changed if it is used directly or through the
AnnaBridge	171:3a7713b1edbc	1043	* PLL as system clock. In this case, you have to select another source
AnnaBridge	171:3a7713b1edbc	1044	* of the system clock then change the HSE state (ex. disable it).
AnnaBridge	171:3a7713b1edbc	1045	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge	171:3a7713b1edbc	1046	* @note This function reset the CSSON bit, so if the clock security system(CSS)
AnnaBridge	171:3a7713b1edbc	1047	* was previously enabled you have to enable it again after calling this
AnnaBridge	171:3a7713b1edbc	1048	* function.
AnnaBridge	171:3a7713b1edbc	1049	* @param __STATE__ specifies the new state of the HSE.
AnnaBridge	171:3a7713b1edbc	1050	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1051	* @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
AnnaBridge	171:3a7713b1edbc	1052	* 6 HSE oscillator clock cycles.
AnnaBridge	171:3a7713b1edbc	1053	* @arg @ref RCC_HSE_ON turn ON the HSE oscillator
AnnaBridge	171:3a7713b1edbc	1054	* @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
AnnaBridge	171:3a7713b1edbc	1055	*/
AnnaBridge	171:3a7713b1edbc	1056	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
AnnaBridge	171:3a7713b1edbc	1057	do{ \
AnnaBridge	171:3a7713b1edbc	1058	if ((__STATE__) == RCC_HSE_ON) \
AnnaBridge	171:3a7713b1edbc	1059	{ \
AnnaBridge	171:3a7713b1edbc	1060	SET_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge	171:3a7713b1edbc	1061	} \
AnnaBridge	171:3a7713b1edbc	1062	else if ((__STATE__) == RCC_HSE_OFF) \
AnnaBridge	171:3a7713b1edbc	1063	{ \
AnnaBridge	171:3a7713b1edbc	1064	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge	171:3a7713b1edbc	1065	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
AnnaBridge	171:3a7713b1edbc	1066	} \
AnnaBridge	171:3a7713b1edbc	1067	else if ((__STATE__) == RCC_HSE_BYPASS) \
AnnaBridge	171:3a7713b1edbc	1068	{ \
AnnaBridge	171:3a7713b1edbc	1069	SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
AnnaBridge	171:3a7713b1edbc	1070	SET_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge	171:3a7713b1edbc	1071	} \
AnnaBridge	171:3a7713b1edbc	1072	else \
AnnaBridge	171:3a7713b1edbc	1073	{ \
AnnaBridge	171:3a7713b1edbc	1074	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
AnnaBridge	171:3a7713b1edbc	1075	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
AnnaBridge	171:3a7713b1edbc	1076	} \
AnnaBridge	171:3a7713b1edbc	1077	}while(0U)
AnnaBridge	171:3a7713b1edbc	1078
AnnaBridge	171:3a7713b1edbc	1079	/**
AnnaBridge	171:3a7713b1edbc	1080	* @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
AnnaBridge	171:3a7713b1edbc	1081	* @note Predivision factor can not be changed if PLL is used as system clock
AnnaBridge	171:3a7713b1edbc	1082	* In this case, you have to select another source of the system clock, disable the PLL and
AnnaBridge	171:3a7713b1edbc	1083	* then change the HSE predivision factor.
AnnaBridge	171:3a7713b1edbc	1084	* @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.
AnnaBridge	171:3a7713b1edbc	1085	* This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
AnnaBridge	171:3a7713b1edbc	1086	*/
AnnaBridge	171:3a7713b1edbc	1087	#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \
AnnaBridge	171:3a7713b1edbc	1088	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSE_PREDIV_VALUE__))
AnnaBridge	171:3a7713b1edbc	1089
AnnaBridge	171:3a7713b1edbc	1090	/**
AnnaBridge	171:3a7713b1edbc	1091	* @}
AnnaBridge	171:3a7713b1edbc	1092	*/
AnnaBridge	171:3a7713b1edbc	1093
AnnaBridge	171:3a7713b1edbc	1094	/** @defgroup RCC_LSE_Configuration LSE Configuration
AnnaBridge	171:3a7713b1edbc	1095	* @{
AnnaBridge	171:3a7713b1edbc	1096	*/
AnnaBridge	171:3a7713b1edbc	1097
AnnaBridge	171:3a7713b1edbc	1098	/**
AnnaBridge	171:3a7713b1edbc	1099	* @brief Macro to configure the External Low Speed oscillator (LSE).
AnnaBridge	171:3a7713b1edbc	1100	* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
AnnaBridge	171:3a7713b1edbc	1101	* @note As the LSE is in the Backup domain and write access is denied to
AnnaBridge	171:3a7713b1edbc	1102	* this domain after reset, you have to enable write access using
AnnaBridge	171:3a7713b1edbc	1103	* @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
AnnaBridge	171:3a7713b1edbc	1104	* (to be done once after reset).
AnnaBridge	171:3a7713b1edbc	1105	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
AnnaBridge	171:3a7713b1edbc	1106	* software should wait on LSERDY flag to be set indicating that LSE clock
AnnaBridge	171:3a7713b1edbc	1107	* is stable and can be used to clock the RTC.
AnnaBridge	171:3a7713b1edbc	1108	* @param __STATE__ specifies the new state of the LSE.
AnnaBridge	171:3a7713b1edbc	1109	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1110	* @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
AnnaBridge	171:3a7713b1edbc	1111	* 6 LSE oscillator clock cycles.
AnnaBridge	171:3a7713b1edbc	1112	* @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
AnnaBridge	171:3a7713b1edbc	1113	* @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
AnnaBridge	171:3a7713b1edbc	1114	*/
AnnaBridge	171:3a7713b1edbc	1115	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
AnnaBridge	171:3a7713b1edbc	1116	do{ \
AnnaBridge	171:3a7713b1edbc	1117	if ((__STATE__) == RCC_LSE_ON) \
AnnaBridge	171:3a7713b1edbc	1118	{ \
AnnaBridge	171:3a7713b1edbc	1119	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
AnnaBridge	171:3a7713b1edbc	1120	} \
AnnaBridge	171:3a7713b1edbc	1121	else if ((__STATE__) == RCC_LSE_OFF) \
AnnaBridge	171:3a7713b1edbc	1122	{ \
AnnaBridge	171:3a7713b1edbc	1123	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
AnnaBridge	171:3a7713b1edbc	1124	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
AnnaBridge	171:3a7713b1edbc	1125	} \
AnnaBridge	171:3a7713b1edbc	1126	else if ((__STATE__) == RCC_LSE_BYPASS) \
AnnaBridge	171:3a7713b1edbc	1127	{ \
AnnaBridge	171:3a7713b1edbc	1128	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
AnnaBridge	171:3a7713b1edbc	1129	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
AnnaBridge	171:3a7713b1edbc	1130	} \
AnnaBridge	171:3a7713b1edbc	1131	else \
AnnaBridge	171:3a7713b1edbc	1132	{ \
AnnaBridge	171:3a7713b1edbc	1133	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
AnnaBridge	171:3a7713b1edbc	1134	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
AnnaBridge	171:3a7713b1edbc	1135	} \
AnnaBridge	171:3a7713b1edbc	1136	}while(0U)
AnnaBridge	171:3a7713b1edbc	1137
AnnaBridge	171:3a7713b1edbc	1138	/**
AnnaBridge	171:3a7713b1edbc	1139	* @}
AnnaBridge	171:3a7713b1edbc	1140	*/
AnnaBridge	171:3a7713b1edbc	1141
AnnaBridge	171:3a7713b1edbc	1142	/** @defgroup RCC_HSI14_Configuration RCC_HSI14_Configuration
AnnaBridge	171:3a7713b1edbc	1143	* @{
AnnaBridge	171:3a7713b1edbc	1144	*/
AnnaBridge	171:3a7713b1edbc	1145
AnnaBridge	171:3a7713b1edbc	1146	/** @brief Macro to enable the Internal 14Mhz High Speed oscillator (HSI14).
AnnaBridge	171:3a7713b1edbc	1147	* @note After enabling the HSI14 with @ref __HAL_RCC_HSI14_ENABLE(), the application software
AnnaBridge	171:3a7713b1edbc	1148	* should wait on HSI14RDY flag to be set indicating that HSI clock is stable and can be
AnnaBridge	171:3a7713b1edbc	1149	* used as system clock source. This is not necessary if @ref HAL_RCC_OscConfig() is used.
AnnaBridge	171:3a7713b1edbc	1150	* clock cycles.
AnnaBridge	171:3a7713b1edbc	1151	*/
AnnaBridge	171:3a7713b1edbc	1152	#define __HAL_RCC_HSI14_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14ON)
AnnaBridge	171:3a7713b1edbc	1153
AnnaBridge	171:3a7713b1edbc	1154	/** @brief Macro to disable the Internal 14Mhz High Speed oscillator (HSI14).
AnnaBridge	171:3a7713b1edbc	1155	* @note The HSI14 is stopped by hardware when entering STOP and STANDBY modes.
AnnaBridge	171:3a7713b1edbc	1156	* @note HSI14 can not be stopped if it is used as system clock source. In this case,
AnnaBridge	171:3a7713b1edbc	1157	* you have to select another source of the system clock then stop the HSI14.
AnnaBridge	171:3a7713b1edbc	1158	* @note When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator
AnnaBridge	171:3a7713b1edbc	1159	* clock cycles.
AnnaBridge	171:3a7713b1edbc	1160	*/
AnnaBridge	171:3a7713b1edbc	1161	#define __HAL_RCC_HSI14_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON)
AnnaBridge	171:3a7713b1edbc	1162
AnnaBridge	171:3a7713b1edbc	1163	/** @brief Macro to enable the Internal 14Mhz High Speed oscillator (HSI14) used by ADC.
AnnaBridge	171:3a7713b1edbc	1164	*/
AnnaBridge	171:3a7713b1edbc	1165	#define __HAL_RCC_HSI14ADC_ENABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS)
AnnaBridge	171:3a7713b1edbc	1166
AnnaBridge	171:3a7713b1edbc	1167	/** @brief Macro to disable the Internal 14Mhz High Speed oscillator (HSI14) used by ADC.
AnnaBridge	171:3a7713b1edbc	1168	*/
AnnaBridge	171:3a7713b1edbc	1169	#define __HAL_RCC_HSI14ADC_DISABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS)
AnnaBridge	171:3a7713b1edbc	1170
AnnaBridge	171:3a7713b1edbc	1171	/** @brief Macro to adjust the Internal 14Mhz High Speed oscillator (HSI) calibration value.
AnnaBridge	171:3a7713b1edbc	1172	* @note The calibration is used to compensate for the variations in voltage
AnnaBridge	171:3a7713b1edbc	1173	* and temperature that influence the frequency of the internal HSI14 RC.
AnnaBridge	171:3a7713b1edbc	1174	* @param __HSI14CALIBRATIONVALUE__ specifies the calibration trimming value
AnnaBridge	171:3a7713b1edbc	1175	* (default is RCC_HSI14CALIBRATION_DEFAULT).
AnnaBridge	171:3a7713b1edbc	1176	* This parameter must be a number between 0 and 0x1F.
AnnaBridge	171:3a7713b1edbc	1177	*/
AnnaBridge	171:3a7713b1edbc	1178	#define __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(__HSI14CALIBRATIONVALUE__) \
AnnaBridge	171:3a7713b1edbc	1179	MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, (uint32_t)(__HSI14CALIBRATIONVALUE__) << RCC_HSI14TRIM_BIT_NUMBER)
AnnaBridge	171:3a7713b1edbc	1180	/**
AnnaBridge	171:3a7713b1edbc	1181	* @}
AnnaBridge	171:3a7713b1edbc	1182	*/
AnnaBridge	171:3a7713b1edbc	1183
AnnaBridge	171:3a7713b1edbc	1184	/** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config
AnnaBridge	171:3a7713b1edbc	1185	* @{
AnnaBridge	171:3a7713b1edbc	1186	*/
AnnaBridge	171:3a7713b1edbc	1187
AnnaBridge	171:3a7713b1edbc	1188	/** @brief Macro to configure the USART1 clock (USART1CLK).
AnnaBridge	171:3a7713b1edbc	1189	* @param __USART1CLKSOURCE__ specifies the USART1 clock source.
AnnaBridge	171:3a7713b1edbc	1190	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1191	* @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
AnnaBridge	171:3a7713b1edbc	1192	* @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
AnnaBridge	171:3a7713b1edbc	1193	* @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
AnnaBridge	171:3a7713b1edbc	1194	* @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
AnnaBridge	171:3a7713b1edbc	1195	*/
AnnaBridge	171:3a7713b1edbc	1196	#define __HAL_RCC_USART1_CONFIG(__USART1CLKSOURCE__) \
AnnaBridge	171:3a7713b1edbc	1197	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSOURCE__))
AnnaBridge	171:3a7713b1edbc	1198
AnnaBridge	171:3a7713b1edbc	1199	/** @brief Macro to get the USART1 clock source.
AnnaBridge	171:3a7713b1edbc	1200	* @retval The clock source can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1201	* @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
AnnaBridge	171:3a7713b1edbc	1202	* @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
AnnaBridge	171:3a7713b1edbc	1203	* @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
AnnaBridge	171:3a7713b1edbc	1204	* @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
AnnaBridge	171:3a7713b1edbc	1205	*/
AnnaBridge	171:3a7713b1edbc	1206	#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW)))
AnnaBridge	171:3a7713b1edbc	1207
AnnaBridge	171:3a7713b1edbc	1208	/**
AnnaBridge	171:3a7713b1edbc	1209	* @}
AnnaBridge	171:3a7713b1edbc	1210	*/
AnnaBridge	171:3a7713b1edbc	1211
AnnaBridge	171:3a7713b1edbc	1212	/** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config
AnnaBridge	171:3a7713b1edbc	1213	* @{
AnnaBridge	171:3a7713b1edbc	1214	*/
AnnaBridge	171:3a7713b1edbc	1215
AnnaBridge	171:3a7713b1edbc	1216	/** @brief Macro to configure the I2C1 clock (I2C1CLK).
AnnaBridge	171:3a7713b1edbc	1217	* @param __I2C1CLKSOURCE__ specifies the I2C1 clock source.
AnnaBridge	171:3a7713b1edbc	1218	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1219	* @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
AnnaBridge	171:3a7713b1edbc	1220	* @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
AnnaBridge	171:3a7713b1edbc	1221	*/
AnnaBridge	171:3a7713b1edbc	1222	#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSOURCE__) \
AnnaBridge	171:3a7713b1edbc	1223	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSOURCE__))
AnnaBridge	171:3a7713b1edbc	1224
AnnaBridge	171:3a7713b1edbc	1225	/** @brief Macro to get the I2C1 clock source.
AnnaBridge	171:3a7713b1edbc	1226	* @retval The clock source can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1227	* @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
AnnaBridge	171:3a7713b1edbc	1228	* @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
AnnaBridge	171:3a7713b1edbc	1229	*/
AnnaBridge	171:3a7713b1edbc	1230	#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW)))
AnnaBridge	171:3a7713b1edbc	1231	/**
AnnaBridge	171:3a7713b1edbc	1232	* @}
AnnaBridge	171:3a7713b1edbc	1233	*/
AnnaBridge	171:3a7713b1edbc	1234
AnnaBridge	171:3a7713b1edbc	1235	/** @defgroup RCC_PLL_Configuration PLL Configuration
AnnaBridge	171:3a7713b1edbc	1236	* @{
AnnaBridge	171:3a7713b1edbc	1237	*/
AnnaBridge	171:3a7713b1edbc	1238
AnnaBridge	171:3a7713b1edbc	1239	/** @brief Macro to enable the main PLL.
AnnaBridge	171:3a7713b1edbc	1240	* @note After enabling the main PLL, the application software should wait on
AnnaBridge	171:3a7713b1edbc	1241	* PLLRDY flag to be set indicating that PLL clock is stable and can
AnnaBridge	171:3a7713b1edbc	1242	* be used as system clock source.
AnnaBridge	171:3a7713b1edbc	1243	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
AnnaBridge	171:3a7713b1edbc	1244	*/
AnnaBridge	171:3a7713b1edbc	1245	#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
AnnaBridge	171:3a7713b1edbc	1246
AnnaBridge	171:3a7713b1edbc	1247	/** @brief Macro to disable the main PLL.
AnnaBridge	171:3a7713b1edbc	1248	* @note The main PLL can not be disabled if it is used as system clock source
AnnaBridge	171:3a7713b1edbc	1249	*/
AnnaBridge	171:3a7713b1edbc	1250	#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
AnnaBridge	171:3a7713b1edbc	1251
AnnaBridge	171:3a7713b1edbc	1252	/** @brief Macro to configure the PLL clock source, multiplication and division factors.
AnnaBridge	171:3a7713b1edbc	1253	* @note This function must be used only when the main PLL is disabled.
AnnaBridge	171:3a7713b1edbc	1254	*
AnnaBridge	171:3a7713b1edbc	1255	* @param __RCC_PLLSOURCE__ specifies the PLL entry clock source.
AnnaBridge	171:3a7713b1edbc	1256	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1257	* @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
AnnaBridge	171:3a7713b1edbc	1258	* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
AnnaBridge	171:3a7713b1edbc	1259	* @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock
AnnaBridge	171:3a7713b1edbc	1260	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1261	* This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
AnnaBridge	171:3a7713b1edbc	1262	* @param __PREDIV__ specifies the predivider factor for PLL VCO input clock
AnnaBridge	171:3a7713b1edbc	1263	* This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16.
AnnaBridge	171:3a7713b1edbc	1264	*
AnnaBridge	171:3a7713b1edbc	1265	*/
AnnaBridge	171:3a7713b1edbc	1266	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__ , __PREDIV__, __PLLMUL__) \
AnnaBridge	171:3a7713b1edbc	1267	do { \
AnnaBridge	171:3a7713b1edbc	1268	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
AnnaBridge	171:3a7713b1edbc	1269	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL \| RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)\|(__RCC_PLLSOURCE__))); \
AnnaBridge	171:3a7713b1edbc	1270	} while(0U)
AnnaBridge	171:3a7713b1edbc	1271
AnnaBridge	171:3a7713b1edbc	1272
AnnaBridge	171:3a7713b1edbc	1273	/** @brief Get oscillator clock selected as PLL input clock
AnnaBridge	171:3a7713b1edbc	1274	* @retval The clock source used for PLL entry. The returned value can be one
AnnaBridge	171:3a7713b1edbc	1275	* of the following:
AnnaBridge	171:3a7713b1edbc	1276	* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
AnnaBridge	171:3a7713b1edbc	1277	*/
AnnaBridge	171:3a7713b1edbc	1278	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
AnnaBridge	171:3a7713b1edbc	1279
AnnaBridge	171:3a7713b1edbc	1280	/**
AnnaBridge	171:3a7713b1edbc	1281	* @}
AnnaBridge	171:3a7713b1edbc	1282	*/
AnnaBridge	171:3a7713b1edbc	1283
AnnaBridge	171:3a7713b1edbc	1284	/** @defgroup RCC_Get_Clock_source Get Clock source
AnnaBridge	171:3a7713b1edbc	1285	* @{
AnnaBridge	171:3a7713b1edbc	1286	*/
AnnaBridge	171:3a7713b1edbc	1287
AnnaBridge	171:3a7713b1edbc	1288	/**
AnnaBridge	171:3a7713b1edbc	1289	* @brief Macro to configure the system clock source.
AnnaBridge	171:3a7713b1edbc	1290	* @param __SYSCLKSOURCE__ specifies the system clock source.
AnnaBridge	171:3a7713b1edbc	1291	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1292	* @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
AnnaBridge	171:3a7713b1edbc	1293	* @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
AnnaBridge	171:3a7713b1edbc	1294	* @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
AnnaBridge	171:3a7713b1edbc	1295	*/
AnnaBridge	171:3a7713b1edbc	1296	#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
AnnaBridge	171:3a7713b1edbc	1297	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
AnnaBridge	171:3a7713b1edbc	1298
AnnaBridge	171:3a7713b1edbc	1299	/** @brief Macro to get the clock source used as system clock.
AnnaBridge	171:3a7713b1edbc	1300	* @retval The clock source used as system clock. The returned value can be one
AnnaBridge	171:3a7713b1edbc	1301	* of the following:
AnnaBridge	171:3a7713b1edbc	1302	* @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
AnnaBridge	171:3a7713b1edbc	1303	* @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
AnnaBridge	171:3a7713b1edbc	1304	* @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
AnnaBridge	171:3a7713b1edbc	1305	*/
AnnaBridge	171:3a7713b1edbc	1306	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
AnnaBridge	171:3a7713b1edbc	1307
AnnaBridge	171:3a7713b1edbc	1308	/**
AnnaBridge	171:3a7713b1edbc	1309	* @}
AnnaBridge	171:3a7713b1edbc	1310	*/
AnnaBridge	171:3a7713b1edbc	1311
AnnaBridge	171:3a7713b1edbc	1312	/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
AnnaBridge	171:3a7713b1edbc	1313	* @{
AnnaBridge	171:3a7713b1edbc	1314	*/
AnnaBridge	171:3a7713b1edbc	1315
AnnaBridge	171:3a7713b1edbc	1316	#if defined(RCC_CFGR_MCOPRE)
AnnaBridge	171:3a7713b1edbc	1317	/** @brief Macro to configure the MCO clock.
AnnaBridge	171:3a7713b1edbc	1318	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
AnnaBridge	171:3a7713b1edbc	1319	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1320	* @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1321	* @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1322	* @arg @ref RCC_MCO1SOURCE_HSI HSI oscillator clock selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1323	* @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1324	* @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1325	* @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1326	* @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1327	@if STM32F042x6
AnnaBridge	171:3a7713b1edbc	1328	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1329	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1330	@elseif STM32F048xx
AnnaBridge	171:3a7713b1edbc	1331	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1332	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1333	@elseif STM32F071xB
AnnaBridge	171:3a7713b1edbc	1334	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1335	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1336	@elseif STM32F072xB
AnnaBridge	171:3a7713b1edbc	1337	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1338	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1339	@elseif STM32F078xx
AnnaBridge	171:3a7713b1edbc	1340	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1341	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1342	@elseif STM32F091xC
AnnaBridge	171:3a7713b1edbc	1343	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1344	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1345	@elseif STM32F098xx
AnnaBridge	171:3a7713b1edbc	1346	* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1347	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1348	@elseif STM32F030x6
AnnaBridge	171:3a7713b1edbc	1349	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1350	@elseif STM32F030xC
AnnaBridge	171:3a7713b1edbc	1351	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1352	@elseif STM32F031x6
AnnaBridge	171:3a7713b1edbc	1353	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1354	@elseif STM32F038xx
AnnaBridge	171:3a7713b1edbc	1355	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1356	@elseif STM32F070x6
AnnaBridge	171:3a7713b1edbc	1357	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1358	@elseif STM32F070xB
AnnaBridge	171:3a7713b1edbc	1359	* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1360	@endif
AnnaBridge	171:3a7713b1edbc	1361	* @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1362	* @param __MCODIV__ specifies the MCO clock prescaler.
AnnaBridge	171:3a7713b1edbc	1363	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1364	* @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1
AnnaBridge	171:3a7713b1edbc	1365	* @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2
AnnaBridge	171:3a7713b1edbc	1366	* @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4
AnnaBridge	171:3a7713b1edbc	1367	* @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
AnnaBridge	171:3a7713b1edbc	1368	* @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
AnnaBridge	171:3a7713b1edbc	1369	* @arg @ref RCC_MCODIV_32 MCO clock source is divided by 32
AnnaBridge	171:3a7713b1edbc	1370	* @arg @ref RCC_MCODIV_64 MCO clock source is divided by 64
AnnaBridge	171:3a7713b1edbc	1371	* @arg @ref RCC_MCODIV_128 MCO clock source is divided by 128
AnnaBridge	171:3a7713b1edbc	1372	*/
AnnaBridge	171:3a7713b1edbc	1373	#else
AnnaBridge	171:3a7713b1edbc	1374	/** @brief Macro to configure the MCO clock.
AnnaBridge	171:3a7713b1edbc	1375	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
AnnaBridge	171:3a7713b1edbc	1376	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1377	* @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1378	* @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1379	* @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1380	* @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1381	* @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1382	* @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1383	* @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1384	* @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
AnnaBridge	171:3a7713b1edbc	1385	* @param __MCODIV__ specifies the MCO clock prescaler.
AnnaBridge	171:3a7713b1edbc	1386	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1387	* @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
AnnaBridge	171:3a7713b1edbc	1388	*/
AnnaBridge	171:3a7713b1edbc	1389	#endif
AnnaBridge	171:3a7713b1edbc	1390	#if defined(RCC_CFGR_MCOPRE)
AnnaBridge	171:3a7713b1edbc	1391	#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
AnnaBridge	171:3a7713b1edbc	1392	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO \| RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) \| (__MCODIV__)))
AnnaBridge	171:3a7713b1edbc	1393	#else
AnnaBridge	171:3a7713b1edbc	1394
AnnaBridge	171:3a7713b1edbc	1395	#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
AnnaBridge	171:3a7713b1edbc	1396	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
AnnaBridge	171:3a7713b1edbc	1397
AnnaBridge	171:3a7713b1edbc	1398	#endif
AnnaBridge	171:3a7713b1edbc	1399
AnnaBridge	171:3a7713b1edbc	1400	/**
AnnaBridge	171:3a7713b1edbc	1401	* @}
AnnaBridge	171:3a7713b1edbc	1402	*/
AnnaBridge	171:3a7713b1edbc	1403
AnnaBridge	171:3a7713b1edbc	1404	/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
AnnaBridge	171:3a7713b1edbc	1405	* @{
AnnaBridge	171:3a7713b1edbc	1406	*/
AnnaBridge	171:3a7713b1edbc	1407
AnnaBridge	171:3a7713b1edbc	1408	/** @brief Macro to configure the RTC clock (RTCCLK).
AnnaBridge	171:3a7713b1edbc	1409	* @note As the RTC clock configuration bits are in the Backup domain and write
AnnaBridge	171:3a7713b1edbc	1410	* access is denied to this domain after reset, you have to enable write
AnnaBridge	171:3a7713b1edbc	1411	* access using the Power Backup Access macro before to configure
AnnaBridge	171:3a7713b1edbc	1412	* the RTC clock source (to be done once after reset).
AnnaBridge	171:3a7713b1edbc	1413	* @note Once the RTC clock is configured it cannot be changed unless the
AnnaBridge	171:3a7713b1edbc	1414	* Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
AnnaBridge	171:3a7713b1edbc	1415	* a Power On Reset (POR).
AnnaBridge	171:3a7713b1edbc	1416	*
AnnaBridge	171:3a7713b1edbc	1417	* @param __RTC_CLKSOURCE__ specifies the RTC clock source.
AnnaBridge	171:3a7713b1edbc	1418	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1419	* @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
AnnaBridge	171:3a7713b1edbc	1420	* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
AnnaBridge	171:3a7713b1edbc	1421	* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
AnnaBridge	171:3a7713b1edbc	1422	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32
AnnaBridge	171:3a7713b1edbc	1423	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
AnnaBridge	171:3a7713b1edbc	1424	* work in STOP and STANDBY modes, and can be used as wakeup source.
AnnaBridge	171:3a7713b1edbc	1425	* However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source,
AnnaBridge	171:3a7713b1edbc	1426	* the RTC cannot be used in STOP and STANDBY modes.
AnnaBridge	171:3a7713b1edbc	1427	* @note The system must always be configured so as to get a PCLK frequency greater than or
AnnaBridge	171:3a7713b1edbc	1428	* equal to the RTCCLK frequency for a proper operation of the RTC.
AnnaBridge	171:3a7713b1edbc	1429	*/
AnnaBridge	171:3a7713b1edbc	1430	#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
AnnaBridge	171:3a7713b1edbc	1431
AnnaBridge	171:3a7713b1edbc	1432	/** @brief Macro to get the RTC clock source.
AnnaBridge	171:3a7713b1edbc	1433	* @retval The clock source can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1434	* @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
AnnaBridge	171:3a7713b1edbc	1435	* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
AnnaBridge	171:3a7713b1edbc	1436	* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
AnnaBridge	171:3a7713b1edbc	1437	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32
AnnaBridge	171:3a7713b1edbc	1438	*/
AnnaBridge	171:3a7713b1edbc	1439	#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
AnnaBridge	171:3a7713b1edbc	1440
AnnaBridge	171:3a7713b1edbc	1441	/** @brief Macro to enable the the RTC clock.
AnnaBridge	171:3a7713b1edbc	1442	* @note These macros must be used only after the RTC clock source was selected.
AnnaBridge	171:3a7713b1edbc	1443	*/
AnnaBridge	171:3a7713b1edbc	1444	#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
AnnaBridge	171:3a7713b1edbc	1445
AnnaBridge	171:3a7713b1edbc	1446	/** @brief Macro to disable the the RTC clock.
AnnaBridge	171:3a7713b1edbc	1447	* @note These macros must be used only after the RTC clock source was selected.
AnnaBridge	171:3a7713b1edbc	1448	*/
AnnaBridge	171:3a7713b1edbc	1449	#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
AnnaBridge	171:3a7713b1edbc	1450
AnnaBridge	171:3a7713b1edbc	1451	/** @brief Macro to force the Backup domain reset.
AnnaBridge	171:3a7713b1edbc	1452	* @note This function resets the RTC peripheral (including the backup registers)
AnnaBridge	171:3a7713b1edbc	1453	* and the RTC clock source selection in RCC_BDCR register.
AnnaBridge	171:3a7713b1edbc	1454	*/
AnnaBridge	171:3a7713b1edbc	1455	#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
AnnaBridge	171:3a7713b1edbc	1456
AnnaBridge	171:3a7713b1edbc	1457	/** @brief Macros to release the Backup domain reset.
AnnaBridge	171:3a7713b1edbc	1458	*/
AnnaBridge	171:3a7713b1edbc	1459	#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
AnnaBridge	171:3a7713b1edbc	1460
AnnaBridge	171:3a7713b1edbc	1461	/**
AnnaBridge	171:3a7713b1edbc	1462	* @}
AnnaBridge	171:3a7713b1edbc	1463	*/
AnnaBridge	171:3a7713b1edbc	1464
AnnaBridge	171:3a7713b1edbc	1465	/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
AnnaBridge	171:3a7713b1edbc	1466	* @brief macros to manage the specified RCC Flags and interrupts.
AnnaBridge	171:3a7713b1edbc	1467	* @{
AnnaBridge	171:3a7713b1edbc	1468	*/
AnnaBridge	171:3a7713b1edbc	1469
AnnaBridge	171:3a7713b1edbc	1470	/** @brief Enable RCC interrupt.
AnnaBridge	171:3a7713b1edbc	1471	* @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
AnnaBridge	171:3a7713b1edbc	1472	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	1473	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
AnnaBridge	171:3a7713b1edbc	1474	* @arg @ref RCC_IT_LSERDY LSE ready interrupt
AnnaBridge	171:3a7713b1edbc	1475	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
AnnaBridge	171:3a7713b1edbc	1476	* @arg @ref RCC_IT_HSERDY HSE ready interrupt
AnnaBridge	171:3a7713b1edbc	1477	* @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
AnnaBridge	171:3a7713b1edbc	1478	* @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt
AnnaBridge	171:3a7713b1edbc	1479	@if STM32F042x6
AnnaBridge	171:3a7713b1edbc	1480	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
AnnaBridge	171:3a7713b1edbc	1481	@elseif STM32F048xx
AnnaBridge	171:3a7713b1edbc	1482	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
AnnaBridge	171:3a7713b1edbc	1483	@elseif STM32F071xB
AnnaBridge	171:3a7713b1edbc	1484	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
AnnaBridge	171:3a7713b1edbc	1485	@elseif STM32F072xB
AnnaBridge	171:3a7713b1edbc	1486	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
AnnaBridge	171:3a7713b1edbc	1487	@elseif STM32F078xx
AnnaBridge	171:3a7713b1edbc	1488	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
AnnaBridge	171:3a7713b1edbc	1489	@elseif STM32F091xC
AnnaBridge	171:3a7713b1edbc	1490	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
AnnaBridge	171:3a7713b1edbc	1491	@elseif STM32F098xx
AnnaBridge	171:3a7713b1edbc	1492	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
AnnaBridge	171:3a7713b1edbc	1493	@endif
AnnaBridge	171:3a7713b1edbc	1494	*/
AnnaBridge	171:3a7713b1edbc	1495	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	1496
AnnaBridge	171:3a7713b1edbc	1497	/** @brief Disable RCC interrupt.
AnnaBridge	171:3a7713b1edbc	1498	* @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
AnnaBridge	171:3a7713b1edbc	1499	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	1500	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
AnnaBridge	171:3a7713b1edbc	1501	* @arg @ref RCC_IT_LSERDY LSE ready interrupt
AnnaBridge	171:3a7713b1edbc	1502	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
AnnaBridge	171:3a7713b1edbc	1503	* @arg @ref RCC_IT_HSERDY HSE ready interrupt
AnnaBridge	171:3a7713b1edbc	1504	* @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
AnnaBridge	171:3a7713b1edbc	1505	* @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt
AnnaBridge	171:3a7713b1edbc	1506	@if STM32F042x6
AnnaBridge	171:3a7713b1edbc	1507	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
AnnaBridge	171:3a7713b1edbc	1508	@elseif STM32F048xx
AnnaBridge	171:3a7713b1edbc	1509	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
AnnaBridge	171:3a7713b1edbc	1510	@elseif STM32F071xB
AnnaBridge	171:3a7713b1edbc	1511	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
AnnaBridge	171:3a7713b1edbc	1512	@elseif STM32F072xB
AnnaBridge	171:3a7713b1edbc	1513	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
AnnaBridge	171:3a7713b1edbc	1514	@elseif STM32F078xx
AnnaBridge	171:3a7713b1edbc	1515	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
AnnaBridge	171:3a7713b1edbc	1516	@elseif STM32F091xC
AnnaBridge	171:3a7713b1edbc	1517	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
AnnaBridge	171:3a7713b1edbc	1518	@elseif STM32F098xx
AnnaBridge	171:3a7713b1edbc	1519	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
AnnaBridge	171:3a7713b1edbc	1520	@endif
AnnaBridge	171:3a7713b1edbc	1521	*/
AnnaBridge	171:3a7713b1edbc	1522	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
AnnaBridge	171:3a7713b1edbc	1523
AnnaBridge	171:3a7713b1edbc	1524	/** @brief Clear the RCC's interrupt pending bits.
AnnaBridge	171:3a7713b1edbc	1525	* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
AnnaBridge	171:3a7713b1edbc	1526	* This parameter can be any combination of the following values:
AnnaBridge	171:3a7713b1edbc	1527	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
AnnaBridge	171:3a7713b1edbc	1528	* @arg @ref RCC_IT_LSERDY LSE ready interrupt.
AnnaBridge	171:3a7713b1edbc	1529	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
AnnaBridge	171:3a7713b1edbc	1530	* @arg @ref RCC_IT_HSERDY HSE ready interrupt.
AnnaBridge	171:3a7713b1edbc	1531	* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
AnnaBridge	171:3a7713b1edbc	1532	* @arg @ref RCC_IT_CSS Clock Security System interrupt
AnnaBridge	171:3a7713b1edbc	1533	* @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt
AnnaBridge	171:3a7713b1edbc	1534	@if STM32F042x6
AnnaBridge	171:3a7713b1edbc	1535	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
AnnaBridge	171:3a7713b1edbc	1536	@elseif STM32F048xx
AnnaBridge	171:3a7713b1edbc	1537	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
AnnaBridge	171:3a7713b1edbc	1538	@elseif STM32F071xB
AnnaBridge	171:3a7713b1edbc	1539	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
AnnaBridge	171:3a7713b1edbc	1540	@elseif STM32F072xB
AnnaBridge	171:3a7713b1edbc	1541	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
AnnaBridge	171:3a7713b1edbc	1542	@elseif STM32F078xx
AnnaBridge	171:3a7713b1edbc	1543	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
AnnaBridge	171:3a7713b1edbc	1544	@elseif STM32F091xC
AnnaBridge	171:3a7713b1edbc	1545	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
AnnaBridge	171:3a7713b1edbc	1546	@elseif STM32F098xx
AnnaBridge	171:3a7713b1edbc	1547	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
AnnaBridge	171:3a7713b1edbc	1548	@endif
AnnaBridge	171:3a7713b1edbc	1549	*/
AnnaBridge	171:3a7713b1edbc	1550	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	1551
AnnaBridge	171:3a7713b1edbc	1552	/** @brief Check the RCC's interrupt has occurred or not.
AnnaBridge	171:3a7713b1edbc	1553	* @param __INTERRUPT__ specifies the RCC interrupt source to check.
AnnaBridge	171:3a7713b1edbc	1554	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1555	* @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
AnnaBridge	171:3a7713b1edbc	1556	* @arg @ref RCC_IT_LSERDY LSE ready interrupt.
AnnaBridge	171:3a7713b1edbc	1557	* @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
AnnaBridge	171:3a7713b1edbc	1558	* @arg @ref RCC_IT_HSERDY HSE ready interrupt.
AnnaBridge	171:3a7713b1edbc	1559	* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
AnnaBridge	171:3a7713b1edbc	1560	* @arg @ref RCC_IT_CSS Clock Security System interrupt
AnnaBridge	171:3a7713b1edbc	1561	* @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt enable
AnnaBridge	171:3a7713b1edbc	1562	@if STM32F042x6
AnnaBridge	171:3a7713b1edbc	1563	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
AnnaBridge	171:3a7713b1edbc	1564	@elseif STM32F048xx
AnnaBridge	171:3a7713b1edbc	1565	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
AnnaBridge	171:3a7713b1edbc	1566	@elseif STM32F071xB
AnnaBridge	171:3a7713b1edbc	1567	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
AnnaBridge	171:3a7713b1edbc	1568	@elseif STM32F072xB
AnnaBridge	171:3a7713b1edbc	1569	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
AnnaBridge	171:3a7713b1edbc	1570	@elseif STM32F078xx
AnnaBridge	171:3a7713b1edbc	1571	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
AnnaBridge	171:3a7713b1edbc	1572	@elseif STM32F091xC
AnnaBridge	171:3a7713b1edbc	1573	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
AnnaBridge	171:3a7713b1edbc	1574	@elseif STM32F098xx
AnnaBridge	171:3a7713b1edbc	1575	* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
AnnaBridge	171:3a7713b1edbc	1576	@endif
AnnaBridge	171:3a7713b1edbc	1577	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
AnnaBridge	171:3a7713b1edbc	1578	*/
AnnaBridge	171:3a7713b1edbc	1579	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
AnnaBridge	171:3a7713b1edbc	1580
AnnaBridge	171:3a7713b1edbc	1581	/** @brief Set RMVF bit to clear the reset flags.
AnnaBridge	171:3a7713b1edbc	1582	* The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
AnnaBridge	171:3a7713b1edbc	1583	* RCC_FLAG_OBLRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
AnnaBridge	171:3a7713b1edbc	1584	*/
AnnaBridge	171:3a7713b1edbc	1585	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
AnnaBridge	171:3a7713b1edbc	1586
AnnaBridge	171:3a7713b1edbc	1587	/** @brief Check RCC flag is set or not.
AnnaBridge	171:3a7713b1edbc	1588	* @param __FLAG__ specifies the flag to check.
AnnaBridge	171:3a7713b1edbc	1589	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	1590	* @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.
AnnaBridge	171:3a7713b1edbc	1591	* @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.
AnnaBridge	171:3a7713b1edbc	1592	* @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.
AnnaBridge	171:3a7713b1edbc	1593	* @arg @ref RCC_FLAG_HSI14RDY HSI14 oscillator clock ready
AnnaBridge	171:3a7713b1edbc	1594	@if STM32F038xx
AnnaBridge	171:3a7713b1edbc	1595	* @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
AnnaBridge	171:3a7713b1edbc	1596	@elseif STM32F042x6
AnnaBridge	171:3a7713b1edbc	1597	* @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready
AnnaBridge	171:3a7713b1edbc	1598	@elseif STM32F048xx
AnnaBridge	171:3a7713b1edbc	1599	* @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready
AnnaBridge	171:3a7713b1edbc	1600	* @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
AnnaBridge	171:3a7713b1edbc	1601	@elseif STM32F058xx
AnnaBridge	171:3a7713b1edbc	1602	* @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
AnnaBridge	171:3a7713b1edbc	1603	@elseif STM32F071xB
AnnaBridge	171:3a7713b1edbc	1604	* @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready
AnnaBridge	171:3a7713b1edbc	1605	@elseif STM32F072xB
AnnaBridge	171:3a7713b1edbc	1606	* @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready
AnnaBridge	171:3a7713b1edbc	1607	@elseif STM32F078xx
AnnaBridge	171:3a7713b1edbc	1608	* @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready
AnnaBridge	171:3a7713b1edbc	1609	* @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
AnnaBridge	171:3a7713b1edbc	1610	@elseif STM32F091xC
AnnaBridge	171:3a7713b1edbc	1611	* @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready
AnnaBridge	171:3a7713b1edbc	1612	@elseif STM32F098xx
AnnaBridge	171:3a7713b1edbc	1613	* @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready
AnnaBridge	171:3a7713b1edbc	1614	* @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
AnnaBridge	171:3a7713b1edbc	1615	@endif
AnnaBridge	171:3a7713b1edbc	1616	* @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
AnnaBridge	171:3a7713b1edbc	1617	* @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
AnnaBridge	171:3a7713b1edbc	1618	* @arg @ref RCC_FLAG_OBLRST Option Byte Load reset
AnnaBridge	171:3a7713b1edbc	1619	* @arg @ref RCC_FLAG_PINRST Pin reset.
AnnaBridge	171:3a7713b1edbc	1620	* @arg @ref RCC_FLAG_PORRST POR/PDR reset.
AnnaBridge	171:3a7713b1edbc	1621	* @arg @ref RCC_FLAG_SFTRST Software reset.
AnnaBridge	171:3a7713b1edbc	1622	* @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
AnnaBridge	171:3a7713b1edbc	1623	* @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
AnnaBridge	171:3a7713b1edbc	1624	* @arg @ref RCC_FLAG_LPWRRST Low Power reset.
AnnaBridge	171:3a7713b1edbc	1625	* @retval The new state of __FLAG__ (TRUE or FALSE).
AnnaBridge	171:3a7713b1edbc	1626	*/
AnnaBridge	171:3a7713b1edbc	1627	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \
AnnaBridge	171:3a7713b1edbc	1628	(((__FLAG__) >> 5U) == CR2_REG_INDEX)? RCC->CR2 : \
AnnaBridge	171:3a7713b1edbc	1629	(((__FLAG__) >> 5U) == BDCR_REG_INDEX) ? RCC->BDCR : \
AnnaBridge	171:3a7713b1edbc	1630	RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
AnnaBridge	171:3a7713b1edbc	1631
AnnaBridge	171:3a7713b1edbc	1632	/**
AnnaBridge	171:3a7713b1edbc	1633	* @}
AnnaBridge	171:3a7713b1edbc	1634	*/
AnnaBridge	171:3a7713b1edbc	1635
AnnaBridge	171:3a7713b1edbc	1636	/**
AnnaBridge	171:3a7713b1edbc	1637	* @}
AnnaBridge	171:3a7713b1edbc	1638	*/
AnnaBridge	171:3a7713b1edbc	1639
AnnaBridge	171:3a7713b1edbc	1640	/* Include RCC HAL Extension module */
AnnaBridge	171:3a7713b1edbc	1641	#include "stm32f0xx_hal_rcc_ex.h"
AnnaBridge	171:3a7713b1edbc	1642
AnnaBridge	171:3a7713b1edbc	1643	/* Exported functions --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	1644	/** @addtogroup RCC_Exported_Functions
AnnaBridge	171:3a7713b1edbc	1645	* @{
AnnaBridge	171:3a7713b1edbc	1646	*/
AnnaBridge	171:3a7713b1edbc	1647
AnnaBridge	171:3a7713b1edbc	1648	/** @addtogroup RCC_Exported_Functions_Group1
AnnaBridge	171:3a7713b1edbc	1649	* @{
AnnaBridge	171:3a7713b1edbc	1650	*/
AnnaBridge	171:3a7713b1edbc	1651
AnnaBridge	171:3a7713b1edbc	1652	/* Initialization and de-initialization functions ******************************/
AnnaBridge	171:3a7713b1edbc	1653	void HAL_RCC_DeInit(void);
AnnaBridge	171:3a7713b1edbc	1654	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
AnnaBridge	171:3a7713b1edbc	1655	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
AnnaBridge	171:3a7713b1edbc	1656
AnnaBridge	171:3a7713b1edbc	1657	/**
AnnaBridge	171:3a7713b1edbc	1658	* @}
AnnaBridge	171:3a7713b1edbc	1659	*/
AnnaBridge	171:3a7713b1edbc	1660
AnnaBridge	171:3a7713b1edbc	1661	/** @addtogroup RCC_Exported_Functions_Group2
AnnaBridge	171:3a7713b1edbc	1662	* @{
AnnaBridge	171:3a7713b1edbc	1663	*/
AnnaBridge	171:3a7713b1edbc	1664
AnnaBridge	171:3a7713b1edbc	1665	/* Peripheral Control functions ************************************************/
AnnaBridge	171:3a7713b1edbc	1666	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
AnnaBridge	171:3a7713b1edbc	1667	void HAL_RCC_EnableCSS(void);
AnnaBridge	171:3a7713b1edbc	1668	/* CSS NMI IRQ handler */
AnnaBridge	171:3a7713b1edbc	1669	void HAL_RCC_NMI_IRQHandler(void);
AnnaBridge	171:3a7713b1edbc	1670	/* User Callbacks in non blocking mode (IT mode) */
AnnaBridge	171:3a7713b1edbc	1671	void HAL_RCC_CSSCallback(void);
AnnaBridge	171:3a7713b1edbc	1672	void HAL_RCC_DisableCSS(void);
AnnaBridge	171:3a7713b1edbc	1673	uint32_t HAL_RCC_GetSysClockFreq(void);
AnnaBridge	171:3a7713b1edbc	1674	uint32_t HAL_RCC_GetHCLKFreq(void);
AnnaBridge	171:3a7713b1edbc	1675	uint32_t HAL_RCC_GetPCLK1Freq(void);
AnnaBridge	171:3a7713b1edbc	1676	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
AnnaBridge	171:3a7713b1edbc	1677	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
AnnaBridge	171:3a7713b1edbc	1678
AnnaBridge	171:3a7713b1edbc	1679	/**
AnnaBridge	171:3a7713b1edbc	1680	* @}
AnnaBridge	171:3a7713b1edbc	1681	*/
AnnaBridge	171:3a7713b1edbc	1682
AnnaBridge	171:3a7713b1edbc	1683	/**
AnnaBridge	171:3a7713b1edbc	1684	* @}
AnnaBridge	171:3a7713b1edbc	1685	*/
AnnaBridge	171:3a7713b1edbc	1686
AnnaBridge	171:3a7713b1edbc	1687	/**
AnnaBridge	171:3a7713b1edbc	1688	* @}
AnnaBridge	171:3a7713b1edbc	1689	*/
AnnaBridge	171:3a7713b1edbc	1690
AnnaBridge	171:3a7713b1edbc	1691	/**
AnnaBridge	171:3a7713b1edbc	1692	* @}
AnnaBridge	171:3a7713b1edbc	1693	*/
AnnaBridge	171:3a7713b1edbc	1694
AnnaBridge	171:3a7713b1edbc	1695	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	1696	}
AnnaBridge	171:3a7713b1edbc	1697	#endif
AnnaBridge	171:3a7713b1edbc	1698
AnnaBridge	171:3a7713b1edbc	1699	#endif /* __STM32F0xx_HAL_RCC_H */
AnnaBridge	171:3a7713b1edbc	1700
AnnaBridge	171:3a7713b1edbc	1701	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
AnnaBridge	171:3a7713b1edbc	1702