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TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/stm32f0xx_hal_pwr_ex.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /** |
| AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32f0xx_hal_pwr_ex.h |
| AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
| AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of PWR HAL Extension module. |
| AnnaBridge | 171:3a7713b1edbc | 6 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 7 | * @attention |
| AnnaBridge | 171:3a7713b1edbc | 8 | * |
| AnnaBridge | 171:3a7713b1edbc | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| AnnaBridge | 171:3a7713b1edbc | 10 | * |
| AnnaBridge | 171:3a7713b1edbc | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 171:3a7713b1edbc | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 171:3a7713b1edbc | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 171:3a7713b1edbc | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 171:3a7713b1edbc | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 171:3a7713b1edbc | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 171:3a7713b1edbc | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 171:3a7713b1edbc | 20 | * without specific prior written permission. |
| AnnaBridge | 171:3a7713b1edbc | 21 | * |
| AnnaBridge | 171:3a7713b1edbc | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 171:3a7713b1edbc | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 171:3a7713b1edbc | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 171:3a7713b1edbc | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 171:3a7713b1edbc | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 171:3a7713b1edbc | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 171:3a7713b1edbc | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 171:3a7713b1edbc | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 171:3a7713b1edbc | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 171:3a7713b1edbc | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 171:3a7713b1edbc | 32 | * |
| AnnaBridge | 171:3a7713b1edbc | 33 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 34 | */ |
| AnnaBridge | 171:3a7713b1edbc | 35 | |
| AnnaBridge | 171:3a7713b1edbc | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 37 | #ifndef __STM32F0xx_HAL_PWR_EX_H |
| AnnaBridge | 171:3a7713b1edbc | 38 | #define __STM32F0xx_HAL_PWR_EX_H |
| AnnaBridge | 171:3a7713b1edbc | 39 | |
| AnnaBridge | 171:3a7713b1edbc | 40 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 41 | extern "C" { |
| AnnaBridge | 171:3a7713b1edbc | 42 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 43 | |
| AnnaBridge | 171:3a7713b1edbc | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 45 | #include "stm32f0xx_hal_def.h" |
| AnnaBridge | 171:3a7713b1edbc | 46 | |
| AnnaBridge | 171:3a7713b1edbc | 47 | /** @addtogroup STM32F0xx_HAL_Driver |
| AnnaBridge | 171:3a7713b1edbc | 48 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 49 | */ |
| AnnaBridge | 171:3a7713b1edbc | 50 | |
| AnnaBridge | 171:3a7713b1edbc | 51 | /** @addtogroup PWREx |
| AnnaBridge | 171:3a7713b1edbc | 52 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 53 | */ |
| AnnaBridge | 171:3a7713b1edbc | 54 | |
| AnnaBridge | 171:3a7713b1edbc | 55 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 56 | |
| AnnaBridge | 171:3a7713b1edbc | 57 | /** @defgroup PWREx_Exported_Types PWREx Exported Types |
| AnnaBridge | 171:3a7713b1edbc | 58 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 59 | */ |
| AnnaBridge | 171:3a7713b1edbc | 60 | |
| AnnaBridge | 171:3a7713b1edbc | 61 | #if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ |
| AnnaBridge | 171:3a7713b1edbc | 62 | defined (STM32F071xB) || defined (STM32F072xB) || \ |
| AnnaBridge | 171:3a7713b1edbc | 63 | defined (STM32F091xC) |
| AnnaBridge | 171:3a7713b1edbc | 64 | |
| AnnaBridge | 171:3a7713b1edbc | 65 | /** |
| AnnaBridge | 171:3a7713b1edbc | 66 | * @brief PWR PVD configuration structure definition |
| AnnaBridge | 171:3a7713b1edbc | 67 | */ |
| AnnaBridge | 171:3a7713b1edbc | 68 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 69 | { |
| AnnaBridge | 171:3a7713b1edbc | 70 | uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level |
| AnnaBridge | 171:3a7713b1edbc | 71 | This parameter can be a value of @ref PWREx_PVD_detection_level */ |
| AnnaBridge | 171:3a7713b1edbc | 72 | |
| AnnaBridge | 171:3a7713b1edbc | 73 | uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. |
| AnnaBridge | 171:3a7713b1edbc | 74 | This parameter can be a value of @ref PWREx_PVD_Mode */ |
| AnnaBridge | 171:3a7713b1edbc | 75 | }PWR_PVDTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 76 | |
| AnnaBridge | 171:3a7713b1edbc | 77 | #endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ |
| AnnaBridge | 171:3a7713b1edbc | 78 | /* defined (STM32F071xB) || defined (STM32F072xB) || */ |
| AnnaBridge | 171:3a7713b1edbc | 79 | /* defined (STM32F091xC) */ |
| AnnaBridge | 171:3a7713b1edbc | 80 | /** |
| AnnaBridge | 171:3a7713b1edbc | 81 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 82 | */ |
| AnnaBridge | 171:3a7713b1edbc | 83 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 84 | |
| AnnaBridge | 171:3a7713b1edbc | 85 | /** @defgroup PWREx_Exported_Constants PWREx Exported Constants |
| AnnaBridge | 171:3a7713b1edbc | 86 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 87 | */ |
| AnnaBridge | 171:3a7713b1edbc | 88 | |
| AnnaBridge | 171:3a7713b1edbc | 89 | |
| AnnaBridge | 171:3a7713b1edbc | 90 | /** @defgroup PWREx_WakeUp_Pins PWREx Wakeup Pins |
| AnnaBridge | 171:3a7713b1edbc | 91 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 92 | */ |
| AnnaBridge | 171:3a7713b1edbc | 93 | #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ |
| AnnaBridge | 171:3a7713b1edbc | 94 | defined (STM32F091xC) || defined (STM32F098xx) |
| AnnaBridge | 171:3a7713b1edbc | 95 | #define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) |
| AnnaBridge | 171:3a7713b1edbc | 96 | #define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) |
| AnnaBridge | 171:3a7713b1edbc | 97 | #define PWR_WAKEUP_PIN3 ((uint32_t)PWR_CSR_EWUP3) |
| AnnaBridge | 171:3a7713b1edbc | 98 | #define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4) |
| AnnaBridge | 171:3a7713b1edbc | 99 | #define PWR_WAKEUP_PIN5 ((uint32_t)PWR_CSR_EWUP5) |
| AnnaBridge | 171:3a7713b1edbc | 100 | #define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6) |
| AnnaBridge | 171:3a7713b1edbc | 101 | #define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7) |
| AnnaBridge | 171:3a7713b1edbc | 102 | #define PWR_WAKEUP_PIN8 ((uint32_t)PWR_CSR_EWUP8) |
| AnnaBridge | 171:3a7713b1edbc | 103 | |
| AnnaBridge | 171:3a7713b1edbc | 104 | #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ |
| AnnaBridge | 171:3a7713b1edbc | 105 | ((PIN) == PWR_WAKEUP_PIN2) || \ |
| AnnaBridge | 171:3a7713b1edbc | 106 | ((PIN) == PWR_WAKEUP_PIN3) || \ |
| AnnaBridge | 171:3a7713b1edbc | 107 | ((PIN) == PWR_WAKEUP_PIN4) || \ |
| AnnaBridge | 171:3a7713b1edbc | 108 | ((PIN) == PWR_WAKEUP_PIN5) || \ |
| AnnaBridge | 171:3a7713b1edbc | 109 | ((PIN) == PWR_WAKEUP_PIN6) || \ |
| AnnaBridge | 171:3a7713b1edbc | 110 | ((PIN) == PWR_WAKEUP_PIN7) || \ |
| AnnaBridge | 171:3a7713b1edbc | 111 | ((PIN) == PWR_WAKEUP_PIN8)) |
| AnnaBridge | 171:3a7713b1edbc | 112 | |
| AnnaBridge | 171:3a7713b1edbc | 113 | #elif defined(STM32F030xC) || defined (STM32F070xB) |
| AnnaBridge | 171:3a7713b1edbc | 114 | #define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) |
| AnnaBridge | 171:3a7713b1edbc | 115 | #define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) |
| AnnaBridge | 171:3a7713b1edbc | 116 | #define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4) |
| AnnaBridge | 171:3a7713b1edbc | 117 | #define PWR_WAKEUP_PIN5 ((uint32_t)PWR_CSR_EWUP5) |
| AnnaBridge | 171:3a7713b1edbc | 118 | #define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6) |
| AnnaBridge | 171:3a7713b1edbc | 119 | #define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7) |
| AnnaBridge | 171:3a7713b1edbc | 120 | |
| AnnaBridge | 171:3a7713b1edbc | 121 | #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ |
| AnnaBridge | 171:3a7713b1edbc | 122 | ((PIN) == PWR_WAKEUP_PIN2) || \ |
| AnnaBridge | 171:3a7713b1edbc | 123 | ((PIN) == PWR_WAKEUP_PIN4) || \ |
| AnnaBridge | 171:3a7713b1edbc | 124 | ((PIN) == PWR_WAKEUP_PIN5) || \ |
| AnnaBridge | 171:3a7713b1edbc | 125 | ((PIN) == PWR_WAKEUP_PIN6) || \ |
| AnnaBridge | 171:3a7713b1edbc | 126 | ((PIN) == PWR_WAKEUP_PIN7)) |
| AnnaBridge | 171:3a7713b1edbc | 127 | |
| AnnaBridge | 171:3a7713b1edbc | 128 | #elif defined(STM32F042x6) || defined (STM32F048xx) |
| AnnaBridge | 171:3a7713b1edbc | 129 | #define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) |
| AnnaBridge | 171:3a7713b1edbc | 130 | #define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) |
| AnnaBridge | 171:3a7713b1edbc | 131 | #define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4) |
| AnnaBridge | 171:3a7713b1edbc | 132 | #define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6) |
| AnnaBridge | 171:3a7713b1edbc | 133 | #define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7) |
| AnnaBridge | 171:3a7713b1edbc | 134 | |
| AnnaBridge | 171:3a7713b1edbc | 135 | #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ |
| AnnaBridge | 171:3a7713b1edbc | 136 | ((PIN) == PWR_WAKEUP_PIN2) || \ |
| AnnaBridge | 171:3a7713b1edbc | 137 | ((PIN) == PWR_WAKEUP_PIN4) || \ |
| AnnaBridge | 171:3a7713b1edbc | 138 | ((PIN) == PWR_WAKEUP_PIN6) || \ |
| AnnaBridge | 171:3a7713b1edbc | 139 | ((PIN) == PWR_WAKEUP_PIN7)) |
| AnnaBridge | 171:3a7713b1edbc | 140 | |
| AnnaBridge | 171:3a7713b1edbc | 141 | #else |
| AnnaBridge | 171:3a7713b1edbc | 142 | #define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) |
| AnnaBridge | 171:3a7713b1edbc | 143 | #define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) |
| AnnaBridge | 171:3a7713b1edbc | 144 | |
| AnnaBridge | 171:3a7713b1edbc | 145 | |
| AnnaBridge | 171:3a7713b1edbc | 146 | #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ |
| AnnaBridge | 171:3a7713b1edbc | 147 | ((PIN) == PWR_WAKEUP_PIN2)) |
| AnnaBridge | 171:3a7713b1edbc | 148 | |
| AnnaBridge | 171:3a7713b1edbc | 149 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 150 | |
| AnnaBridge | 171:3a7713b1edbc | 151 | /** |
| AnnaBridge | 171:3a7713b1edbc | 152 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 153 | */ |
| AnnaBridge | 171:3a7713b1edbc | 154 | |
| AnnaBridge | 171:3a7713b1edbc | 155 | /** @defgroup PWREx_EXTI_Line PWREx EXTI Line |
| AnnaBridge | 171:3a7713b1edbc | 156 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 157 | */ |
| AnnaBridge | 171:3a7713b1edbc | 158 | #if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ |
| AnnaBridge | 171:3a7713b1edbc | 159 | defined (STM32F071xB) || defined (STM32F072xB) || \ |
| AnnaBridge | 171:3a7713b1edbc | 160 | defined (STM32F091xC) |
| AnnaBridge | 171:3a7713b1edbc | 161 | |
| AnnaBridge | 171:3a7713b1edbc | 162 | #define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ |
| AnnaBridge | 171:3a7713b1edbc | 163 | |
| AnnaBridge | 171:3a7713b1edbc | 164 | #endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ |
| AnnaBridge | 171:3a7713b1edbc | 165 | /* defined (STM32F071xB) || defined (STM32F072xB) || */ |
| AnnaBridge | 171:3a7713b1edbc | 166 | /* defined (STM32F091xC) */ |
| AnnaBridge | 171:3a7713b1edbc | 167 | |
| AnnaBridge | 171:3a7713b1edbc | 168 | #if defined (STM32F042x6) || defined (STM32F048xx) || \ |
| AnnaBridge | 171:3a7713b1edbc | 169 | defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ |
| AnnaBridge | 171:3a7713b1edbc | 170 | defined (STM32F091xC) || defined (STM32F098xx) |
| AnnaBridge | 171:3a7713b1edbc | 171 | |
| AnnaBridge | 171:3a7713b1edbc | 172 | #define PWR_EXTI_LINE_VDDIO2 ((uint32_t)EXTI_IMR_MR31) /*!< External interrupt line 31 Connected to the Vddio2 Monitor EXTI Line */ |
| AnnaBridge | 171:3a7713b1edbc | 173 | |
| AnnaBridge | 171:3a7713b1edbc | 174 | #endif /* defined (STM32F042x6) || defined (STM32F048xx) ||\ |
| AnnaBridge | 171:3a7713b1edbc | 175 | defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ |
| AnnaBridge | 171:3a7713b1edbc | 176 | defined (STM32F091xC) || defined (STM32F098xx) ||*/ |
| AnnaBridge | 171:3a7713b1edbc | 177 | /** |
| AnnaBridge | 171:3a7713b1edbc | 178 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 179 | */ |
| AnnaBridge | 171:3a7713b1edbc | 180 | |
| AnnaBridge | 171:3a7713b1edbc | 181 | #if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ |
| AnnaBridge | 171:3a7713b1edbc | 182 | defined (STM32F071xB) || defined (STM32F072xB) || \ |
| AnnaBridge | 171:3a7713b1edbc | 183 | defined (STM32F091xC) |
| AnnaBridge | 171:3a7713b1edbc | 184 | /** @defgroup PWREx_PVD_detection_level PWREx PVD detection level |
| AnnaBridge | 171:3a7713b1edbc | 185 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 186 | */ |
| AnnaBridge | 171:3a7713b1edbc | 187 | #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 |
| AnnaBridge | 171:3a7713b1edbc | 188 | #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 |
| AnnaBridge | 171:3a7713b1edbc | 189 | #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 |
| AnnaBridge | 171:3a7713b1edbc | 190 | #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 |
| AnnaBridge | 171:3a7713b1edbc | 191 | #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 |
| AnnaBridge | 171:3a7713b1edbc | 192 | #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 |
| AnnaBridge | 171:3a7713b1edbc | 193 | #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 |
| AnnaBridge | 171:3a7713b1edbc | 194 | #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 |
| AnnaBridge | 171:3a7713b1edbc | 195 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ |
| AnnaBridge | 171:3a7713b1edbc | 196 | ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ |
| AnnaBridge | 171:3a7713b1edbc | 197 | ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ |
| AnnaBridge | 171:3a7713b1edbc | 198 | ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) |
| AnnaBridge | 171:3a7713b1edbc | 199 | /** |
| AnnaBridge | 171:3a7713b1edbc | 200 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 201 | */ |
| AnnaBridge | 171:3a7713b1edbc | 202 | |
| AnnaBridge | 171:3a7713b1edbc | 203 | /** @defgroup PWREx_PVD_Mode PWREx PVD Mode |
| AnnaBridge | 171:3a7713b1edbc | 204 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 205 | */ |
| AnnaBridge | 171:3a7713b1edbc | 206 | #define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< basic mode is used */ |
| AnnaBridge | 171:3a7713b1edbc | 207 | #define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ |
| AnnaBridge | 171:3a7713b1edbc | 208 | #define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ |
| AnnaBridge | 171:3a7713b1edbc | 209 | #define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ |
| AnnaBridge | 171:3a7713b1edbc | 210 | #define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */ |
| AnnaBridge | 171:3a7713b1edbc | 211 | #define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */ |
| AnnaBridge | 171:3a7713b1edbc | 212 | #define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ |
| AnnaBridge | 171:3a7713b1edbc | 213 | |
| AnnaBridge | 171:3a7713b1edbc | 214 | #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ |
| AnnaBridge | 171:3a7713b1edbc | 215 | ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ |
| AnnaBridge | 171:3a7713b1edbc | 216 | ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ |
| AnnaBridge | 171:3a7713b1edbc | 217 | ((MODE) == PWR_PVD_MODE_NORMAL)) |
| AnnaBridge | 171:3a7713b1edbc | 218 | /** |
| AnnaBridge | 171:3a7713b1edbc | 219 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 220 | */ |
| AnnaBridge | 171:3a7713b1edbc | 221 | #endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ |
| AnnaBridge | 171:3a7713b1edbc | 222 | /* defined (STM32F071xB) || defined (STM32F072xB) || */ |
| AnnaBridge | 171:3a7713b1edbc | 223 | /* defined (STM32F091xC) */ |
| AnnaBridge | 171:3a7713b1edbc | 224 | |
| AnnaBridge | 171:3a7713b1edbc | 225 | /** @defgroup PWREx_Flag PWREx Flag |
| AnnaBridge | 171:3a7713b1edbc | 226 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 227 | */ |
| AnnaBridge | 171:3a7713b1edbc | 228 | #if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ |
| AnnaBridge | 171:3a7713b1edbc | 229 | defined (STM32F071xB) || defined (STM32F072xB) || \ |
| AnnaBridge | 171:3a7713b1edbc | 230 | defined (STM32F091xC) |
| AnnaBridge | 171:3a7713b1edbc | 231 | |
| AnnaBridge | 171:3a7713b1edbc | 232 | #define PWR_FLAG_WU PWR_CSR_WUF |
| AnnaBridge | 171:3a7713b1edbc | 233 | #define PWR_FLAG_SB PWR_CSR_SBF |
| AnnaBridge | 171:3a7713b1edbc | 234 | #define PWR_FLAG_PVDO PWR_CSR_PVDO |
| AnnaBridge | 171:3a7713b1edbc | 235 | #define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF |
| AnnaBridge | 171:3a7713b1edbc | 236 | #elif defined (STM32F070x6) || defined (STM32F070xB) || defined (STM32F030xC) |
| AnnaBridge | 171:3a7713b1edbc | 237 | #define PWR_FLAG_WU PWR_CSR_WUF |
| AnnaBridge | 171:3a7713b1edbc | 238 | #define PWR_FLAG_SB PWR_CSR_SBF |
| AnnaBridge | 171:3a7713b1edbc | 239 | #define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF |
| AnnaBridge | 171:3a7713b1edbc | 240 | #else |
| AnnaBridge | 171:3a7713b1edbc | 241 | #define PWR_FLAG_WU PWR_CSR_WUF |
| AnnaBridge | 171:3a7713b1edbc | 242 | #define PWR_FLAG_SB PWR_CSR_SBF |
| AnnaBridge | 171:3a7713b1edbc | 243 | |
| AnnaBridge | 171:3a7713b1edbc | 244 | #endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ |
| AnnaBridge | 171:3a7713b1edbc | 245 | /* defined (STM32F071xB) || defined (STM32F072xB) || */ |
| AnnaBridge | 171:3a7713b1edbc | 246 | /* defined (STM32F091xC) */ |
| AnnaBridge | 171:3a7713b1edbc | 247 | /** |
| AnnaBridge | 171:3a7713b1edbc | 248 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 249 | */ |
| AnnaBridge | 171:3a7713b1edbc | 250 | |
| AnnaBridge | 171:3a7713b1edbc | 251 | /** |
| AnnaBridge | 171:3a7713b1edbc | 252 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 253 | */ |
| AnnaBridge | 171:3a7713b1edbc | 254 | |
| AnnaBridge | 171:3a7713b1edbc | 255 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 256 | /** @defgroup PWREx_Exported_Macros PWREx Exported Macros |
| AnnaBridge | 171:3a7713b1edbc | 257 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 258 | */ |
| AnnaBridge | 171:3a7713b1edbc | 259 | #if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ |
| AnnaBridge | 171:3a7713b1edbc | 260 | defined (STM32F071xB) || defined (STM32F072xB) || \ |
| AnnaBridge | 171:3a7713b1edbc | 261 | defined (STM32F091xC) |
| AnnaBridge | 171:3a7713b1edbc | 262 | /** |
| AnnaBridge | 171:3a7713b1edbc | 263 | * @brief Enable interrupt on PVD Exti Line 16. |
| AnnaBridge | 171:3a7713b1edbc | 264 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 265 | */ |
| AnnaBridge | 171:3a7713b1edbc | 266 | #define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD)) |
| AnnaBridge | 171:3a7713b1edbc | 267 | |
| AnnaBridge | 171:3a7713b1edbc | 268 | /** |
| AnnaBridge | 171:3a7713b1edbc | 269 | * @brief Disable interrupt on PVD Exti Line 16. |
| AnnaBridge | 171:3a7713b1edbc | 270 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 271 | */ |
| AnnaBridge | 171:3a7713b1edbc | 272 | #define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD)) |
| AnnaBridge | 171:3a7713b1edbc | 273 | |
| AnnaBridge | 171:3a7713b1edbc | 274 | /** |
| AnnaBridge | 171:3a7713b1edbc | 275 | * @brief Enable event on PVD Exti Line 16. |
| AnnaBridge | 171:3a7713b1edbc | 276 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 277 | */ |
| AnnaBridge | 171:3a7713b1edbc | 278 | #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD)) |
| AnnaBridge | 171:3a7713b1edbc | 279 | |
| AnnaBridge | 171:3a7713b1edbc | 280 | /** |
| AnnaBridge | 171:3a7713b1edbc | 281 | * @brief Disable event on PVD Exti Line 16. |
| AnnaBridge | 171:3a7713b1edbc | 282 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 283 | */ |
| AnnaBridge | 171:3a7713b1edbc | 284 | #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD)) |
| AnnaBridge | 171:3a7713b1edbc | 285 | |
| AnnaBridge | 171:3a7713b1edbc | 286 | /** |
| AnnaBridge | 171:3a7713b1edbc | 287 | * @brief Disable the PVD Extended Interrupt Rising Trigger. |
| AnnaBridge | 171:3a7713b1edbc | 288 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 289 | */ |
| AnnaBridge | 171:3a7713b1edbc | 290 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 171:3a7713b1edbc | 291 | |
| AnnaBridge | 171:3a7713b1edbc | 292 | /** |
| AnnaBridge | 171:3a7713b1edbc | 293 | * @brief Disable the PVD Extended Interrupt Falling Trigger. |
| AnnaBridge | 171:3a7713b1edbc | 294 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 295 | */ |
| AnnaBridge | 171:3a7713b1edbc | 296 | #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) |
| AnnaBridge | 171:3a7713b1edbc | 297 | |
| AnnaBridge | 171:3a7713b1edbc | 298 | /** |
| AnnaBridge | 171:3a7713b1edbc | 299 | * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. |
| AnnaBridge | 171:3a7713b1edbc | 300 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 301 | */ |
| AnnaBridge | 171:3a7713b1edbc | 302 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); |
| AnnaBridge | 171:3a7713b1edbc | 303 | |
| AnnaBridge | 171:3a7713b1edbc | 304 | |
| AnnaBridge | 171:3a7713b1edbc | 305 | /** |
| AnnaBridge | 171:3a7713b1edbc | 306 | * @brief PVD EXTI line configuration: set falling edge trigger. |
| AnnaBridge | 171:3a7713b1edbc | 307 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 308 | */ |
| AnnaBridge | 171:3a7713b1edbc | 309 | #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_PVD) |
| AnnaBridge | 171:3a7713b1edbc | 310 | |
| AnnaBridge | 171:3a7713b1edbc | 311 | /** |
| AnnaBridge | 171:3a7713b1edbc | 312 | * @brief PVD EXTI line configuration: set rising edge trigger. |
| AnnaBridge | 171:3a7713b1edbc | 313 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 314 | */ |
| AnnaBridge | 171:3a7713b1edbc | 315 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() EXTI->RTSR |= (PWR_EXTI_LINE_PVD) |
| AnnaBridge | 171:3a7713b1edbc | 316 | |
| AnnaBridge | 171:3a7713b1edbc | 317 | /** |
| AnnaBridge | 171:3a7713b1edbc | 318 | * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger. |
| AnnaBridge | 171:3a7713b1edbc | 319 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 320 | */ |
| AnnaBridge | 171:3a7713b1edbc | 321 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); |
| AnnaBridge | 171:3a7713b1edbc | 322 | |
| AnnaBridge | 171:3a7713b1edbc | 323 | /** |
| AnnaBridge | 171:3a7713b1edbc | 324 | * @brief Check whether the specified PVD EXTI interrupt flag is set or not. |
| AnnaBridge | 171:3a7713b1edbc | 325 | * @retval EXTI PVD Line Status. |
| AnnaBridge | 171:3a7713b1edbc | 326 | */ |
| AnnaBridge | 171:3a7713b1edbc | 327 | #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) |
| AnnaBridge | 171:3a7713b1edbc | 328 | |
| AnnaBridge | 171:3a7713b1edbc | 329 | /** |
| AnnaBridge | 171:3a7713b1edbc | 330 | * @brief Clear the PVD EXTI flag. |
| AnnaBridge | 171:3a7713b1edbc | 331 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 332 | */ |
| AnnaBridge | 171:3a7713b1edbc | 333 | #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) |
| AnnaBridge | 171:3a7713b1edbc | 334 | |
| AnnaBridge | 171:3a7713b1edbc | 335 | /** |
| AnnaBridge | 171:3a7713b1edbc | 336 | * @brief Generate a Software interrupt on selected EXTI line. |
| AnnaBridge | 171:3a7713b1edbc | 337 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 338 | */ |
| AnnaBridge | 171:3a7713b1edbc | 339 | #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD)) |
| AnnaBridge | 171:3a7713b1edbc | 340 | |
| AnnaBridge | 171:3a7713b1edbc | 341 | #endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ |
| AnnaBridge | 171:3a7713b1edbc | 342 | /* defined (STM32F071xB) || defined (STM32F072xB) || */ |
| AnnaBridge | 171:3a7713b1edbc | 343 | /* defined (STM32F091xC) */ |
| AnnaBridge | 171:3a7713b1edbc | 344 | |
| AnnaBridge | 171:3a7713b1edbc | 345 | |
| AnnaBridge | 171:3a7713b1edbc | 346 | #if defined (STM32F042x6) || defined (STM32F048xx) || \ |
| AnnaBridge | 171:3a7713b1edbc | 347 | defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ |
| AnnaBridge | 171:3a7713b1edbc | 348 | defined (STM32F091xC) || defined (STM32F098xx) |
| AnnaBridge | 171:3a7713b1edbc | 349 | /** |
| AnnaBridge | 171:3a7713b1edbc | 350 | * @brief Enable interrupt on Vddio2 Monitor Exti Line 31. |
| AnnaBridge | 171:3a7713b1edbc | 351 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 352 | */ |
| AnnaBridge | 171:3a7713b1edbc | 353 | #define __HAL_PWR_VDDIO2_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_VDDIO2)) |
| AnnaBridge | 171:3a7713b1edbc | 354 | |
| AnnaBridge | 171:3a7713b1edbc | 355 | /** |
| AnnaBridge | 171:3a7713b1edbc | 356 | * @brief Disable interrupt on Vddio2 Monitor Exti Line 31. |
| AnnaBridge | 171:3a7713b1edbc | 357 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 358 | */ |
| AnnaBridge | 171:3a7713b1edbc | 359 | #define __HAL_PWR_VDDIO2_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_VDDIO2)) |
| AnnaBridge | 171:3a7713b1edbc | 360 | |
| AnnaBridge | 171:3a7713b1edbc | 361 | /** |
| AnnaBridge | 171:3a7713b1edbc | 362 | * @brief Vddio2 Monitor EXTI line configuration: clear falling edge and rising edge trigger. |
| AnnaBridge | 171:3a7713b1edbc | 363 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 364 | */ |
| AnnaBridge | 171:3a7713b1edbc | 365 | #define __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE() \ |
| AnnaBridge | 171:3a7713b1edbc | 366 | do{ \ |
| AnnaBridge | 171:3a7713b1edbc | 367 | EXTI->FTSR &= ~(PWR_EXTI_LINE_VDDIO2); \ |
| AnnaBridge | 171:3a7713b1edbc | 368 | EXTI->RTSR &= ~(PWR_EXTI_LINE_VDDIO2); \ |
| AnnaBridge | 171:3a7713b1edbc | 369 | } while(0) |
| AnnaBridge | 171:3a7713b1edbc | 370 | |
| AnnaBridge | 171:3a7713b1edbc | 371 | /** |
| AnnaBridge | 171:3a7713b1edbc | 372 | * @brief Vddio2 Monitor EXTI line configuration: set falling edge trigger. |
| AnnaBridge | 171:3a7713b1edbc | 373 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 374 | */ |
| AnnaBridge | 171:3a7713b1edbc | 375 | #define __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_VDDIO2) |
| AnnaBridge | 171:3a7713b1edbc | 376 | |
| AnnaBridge | 171:3a7713b1edbc | 377 | /** |
| AnnaBridge | 171:3a7713b1edbc | 378 | * @brief Check whether the specified VDDIO2 monitor EXTI interrupt flag is set or not. |
| AnnaBridge | 171:3a7713b1edbc | 379 | * @retval EXTI VDDIO2 Monitor Line Status. |
| AnnaBridge | 171:3a7713b1edbc | 380 | */ |
| AnnaBridge | 171:3a7713b1edbc | 381 | #define __HAL_PWR_VDDIO2_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_VDDIO2)) |
| AnnaBridge | 171:3a7713b1edbc | 382 | |
| AnnaBridge | 171:3a7713b1edbc | 383 | /** |
| AnnaBridge | 171:3a7713b1edbc | 384 | * @brief Clear the VDDIO2 Monitor EXTI flag. |
| AnnaBridge | 171:3a7713b1edbc | 385 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 386 | */ |
| AnnaBridge | 171:3a7713b1edbc | 387 | #define __HAL_PWR_VDDIO2_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_VDDIO2)) |
| AnnaBridge | 171:3a7713b1edbc | 388 | |
| AnnaBridge | 171:3a7713b1edbc | 389 | /** |
| AnnaBridge | 171:3a7713b1edbc | 390 | * @brief Generate a Software interrupt on selected EXTI line. |
| AnnaBridge | 171:3a7713b1edbc | 391 | * @retval None. |
| AnnaBridge | 171:3a7713b1edbc | 392 | */ |
| AnnaBridge | 171:3a7713b1edbc | 393 | #define __HAL_PWR_VDDIO2_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_VDDIO2)) |
| AnnaBridge | 171:3a7713b1edbc | 394 | |
| AnnaBridge | 171:3a7713b1edbc | 395 | |
| AnnaBridge | 171:3a7713b1edbc | 396 | #endif /* defined (STM32F042x6) || defined (STM32F048xx) ||\ |
| AnnaBridge | 171:3a7713b1edbc | 397 | defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ |
| AnnaBridge | 171:3a7713b1edbc | 398 | defined (STM32F091xC) || defined (STM32F098xx) */ |
| AnnaBridge | 171:3a7713b1edbc | 399 | |
| AnnaBridge | 171:3a7713b1edbc | 400 | /** |
| AnnaBridge | 171:3a7713b1edbc | 401 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 402 | */ |
| AnnaBridge | 171:3a7713b1edbc | 403 | |
| AnnaBridge | 171:3a7713b1edbc | 404 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 405 | |
| AnnaBridge | 171:3a7713b1edbc | 406 | /** @addtogroup PWREx_Exported_Functions PWREx Exported Functions |
| AnnaBridge | 171:3a7713b1edbc | 407 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 408 | */ |
| AnnaBridge | 171:3a7713b1edbc | 409 | |
| AnnaBridge | 171:3a7713b1edbc | 410 | /** @addtogroup PWREx_Exported_Functions_Group1 |
| AnnaBridge | 171:3a7713b1edbc | 411 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 412 | */ |
| AnnaBridge | 171:3a7713b1edbc | 413 | /* I/O operation functions ***************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 414 | #if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ |
| AnnaBridge | 171:3a7713b1edbc | 415 | defined (STM32F071xB) || defined (STM32F072xB) || \ |
| AnnaBridge | 171:3a7713b1edbc | 416 | defined (STM32F091xC) |
| AnnaBridge | 171:3a7713b1edbc | 417 | void HAL_PWR_PVD_IRQHandler(void); |
| AnnaBridge | 171:3a7713b1edbc | 418 | void HAL_PWR_PVDCallback(void); |
| AnnaBridge | 171:3a7713b1edbc | 419 | #endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ |
| AnnaBridge | 171:3a7713b1edbc | 420 | /* defined (STM32F071xB) || defined (STM32F072xB) || */ |
| AnnaBridge | 171:3a7713b1edbc | 421 | /* defined (STM32F091xC) */ |
| AnnaBridge | 171:3a7713b1edbc | 422 | |
| AnnaBridge | 171:3a7713b1edbc | 423 | #if defined (STM32F042x6) || defined (STM32F048xx) || \ |
| AnnaBridge | 171:3a7713b1edbc | 424 | defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ |
| AnnaBridge | 171:3a7713b1edbc | 425 | defined (STM32F091xC) || defined (STM32F098xx) |
| AnnaBridge | 171:3a7713b1edbc | 426 | void HAL_PWREx_Vddio2Monitor_IRQHandler(void); |
| AnnaBridge | 171:3a7713b1edbc | 427 | void HAL_PWREx_Vddio2MonitorCallback(void); |
| AnnaBridge | 171:3a7713b1edbc | 428 | #endif /* defined (STM32F042x6) || defined (STM32F048xx) || \ |
| AnnaBridge | 171:3a7713b1edbc | 429 | defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ |
| AnnaBridge | 171:3a7713b1edbc | 430 | defined (STM32F091xC) || defined (STM32F098xx) */ |
| AnnaBridge | 171:3a7713b1edbc | 431 | |
| AnnaBridge | 171:3a7713b1edbc | 432 | /* Peripheral Control functions **********************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 433 | #if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \ |
| AnnaBridge | 171:3a7713b1edbc | 434 | defined (STM32F071xB) || defined (STM32F072xB) || \ |
| AnnaBridge | 171:3a7713b1edbc | 435 | defined (STM32F091xC) |
| AnnaBridge | 171:3a7713b1edbc | 436 | void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); |
| AnnaBridge | 171:3a7713b1edbc | 437 | void HAL_PWR_EnablePVD(void); |
| AnnaBridge | 171:3a7713b1edbc | 438 | void HAL_PWR_DisablePVD(void); |
| AnnaBridge | 171:3a7713b1edbc | 439 | #endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */ |
| AnnaBridge | 171:3a7713b1edbc | 440 | /* defined (STM32F071xB) || defined (STM32F072xB) || */ |
| AnnaBridge | 171:3a7713b1edbc | 441 | /* defined (STM32F091xC) */ |
| AnnaBridge | 171:3a7713b1edbc | 442 | |
| AnnaBridge | 171:3a7713b1edbc | 443 | #if defined (STM32F042x6) || defined (STM32F048xx) || \ |
| AnnaBridge | 171:3a7713b1edbc | 444 | defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ |
| AnnaBridge | 171:3a7713b1edbc | 445 | defined (STM32F091xC) || defined (STM32F098xx) |
| AnnaBridge | 171:3a7713b1edbc | 446 | void HAL_PWREx_EnableVddio2Monitor(void); |
| AnnaBridge | 171:3a7713b1edbc | 447 | void HAL_PWREx_DisableVddio2Monitor(void); |
| AnnaBridge | 171:3a7713b1edbc | 448 | #endif /* defined (STM32F042x6) || defined (STM32F048xx) || \ |
| AnnaBridge | 171:3a7713b1edbc | 449 | defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ |
| AnnaBridge | 171:3a7713b1edbc | 450 | defined (STM32F091xC) || defined (STM32F098xx) */ |
| AnnaBridge | 171:3a7713b1edbc | 451 | |
| AnnaBridge | 171:3a7713b1edbc | 452 | /** |
| AnnaBridge | 171:3a7713b1edbc | 453 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 454 | */ |
| AnnaBridge | 171:3a7713b1edbc | 455 | |
| AnnaBridge | 171:3a7713b1edbc | 456 | /** |
| AnnaBridge | 171:3a7713b1edbc | 457 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 458 | */ |
| AnnaBridge | 171:3a7713b1edbc | 459 | |
| AnnaBridge | 171:3a7713b1edbc | 460 | /** |
| AnnaBridge | 171:3a7713b1edbc | 461 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 462 | */ |
| AnnaBridge | 171:3a7713b1edbc | 463 | |
| AnnaBridge | 171:3a7713b1edbc | 464 | /** |
| AnnaBridge | 171:3a7713b1edbc | 465 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 466 | */ |
| AnnaBridge | 171:3a7713b1edbc | 467 | |
| AnnaBridge | 171:3a7713b1edbc | 468 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 469 | } |
| AnnaBridge | 171:3a7713b1edbc | 470 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 471 | |
| AnnaBridge | 171:3a7713b1edbc | 472 | #endif /* __STM32F0xx_HAL_PWR_EX_H */ |
| AnnaBridge | 171:3a7713b1edbc | 473 | |
| AnnaBridge | 171:3a7713b1edbc | 474 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
| AnnaBridge | 171:3a7713b1edbc | 475 |
