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TARGET_NUCLEO_F030R8/TOOLCHAIN_ARM_MICRO/stm32f0xx_hal_adc.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /** |
| AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32f0xx_hal_adc.h |
| AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
| AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file containing functions prototypes of ADC HAL library. |
| AnnaBridge | 171:3a7713b1edbc | 6 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 7 | * @attention |
| AnnaBridge | 171:3a7713b1edbc | 8 | * |
| AnnaBridge | 171:3a7713b1edbc | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| AnnaBridge | 171:3a7713b1edbc | 10 | * |
| AnnaBridge | 171:3a7713b1edbc | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 171:3a7713b1edbc | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 171:3a7713b1edbc | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 171:3a7713b1edbc | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 171:3a7713b1edbc | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 171:3a7713b1edbc | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 171:3a7713b1edbc | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 171:3a7713b1edbc | 20 | * without specific prior written permission. |
| AnnaBridge | 171:3a7713b1edbc | 21 | * |
| AnnaBridge | 171:3a7713b1edbc | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 171:3a7713b1edbc | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 171:3a7713b1edbc | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 171:3a7713b1edbc | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 171:3a7713b1edbc | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 171:3a7713b1edbc | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 171:3a7713b1edbc | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 171:3a7713b1edbc | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 171:3a7713b1edbc | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 171:3a7713b1edbc | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 171:3a7713b1edbc | 32 | * |
| AnnaBridge | 171:3a7713b1edbc | 33 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 34 | */ |
| AnnaBridge | 171:3a7713b1edbc | 35 | |
| AnnaBridge | 171:3a7713b1edbc | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 37 | #ifndef __STM32F0xx_HAL_ADC_H |
| AnnaBridge | 171:3a7713b1edbc | 38 | #define __STM32F0xx_HAL_ADC_H |
| AnnaBridge | 171:3a7713b1edbc | 39 | |
| AnnaBridge | 171:3a7713b1edbc | 40 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 41 | extern "C" { |
| AnnaBridge | 171:3a7713b1edbc | 42 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 43 | |
| AnnaBridge | 171:3a7713b1edbc | 44 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 45 | #include "stm32f0xx_hal_def.h" |
| AnnaBridge | 171:3a7713b1edbc | 46 | |
| AnnaBridge | 171:3a7713b1edbc | 47 | /* Include low level driver */ |
| AnnaBridge | 171:3a7713b1edbc | 48 | #include "stm32f0xx_ll_adc.h" |
| AnnaBridge | 171:3a7713b1edbc | 49 | |
| AnnaBridge | 171:3a7713b1edbc | 50 | /** @addtogroup STM32F0xx_HAL_Driver |
| AnnaBridge | 171:3a7713b1edbc | 51 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 52 | */ |
| AnnaBridge | 171:3a7713b1edbc | 53 | |
| AnnaBridge | 171:3a7713b1edbc | 54 | /** @addtogroup ADC |
| AnnaBridge | 171:3a7713b1edbc | 55 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 56 | */ |
| AnnaBridge | 171:3a7713b1edbc | 57 | |
| AnnaBridge | 171:3a7713b1edbc | 58 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 59 | /** @defgroup ADC_Exported_Types ADC Exported Types |
| AnnaBridge | 171:3a7713b1edbc | 60 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 61 | */ |
| AnnaBridge | 171:3a7713b1edbc | 62 | |
| AnnaBridge | 171:3a7713b1edbc | 63 | /** |
| AnnaBridge | 171:3a7713b1edbc | 64 | * @brief Structure definition of ADC initialization and regular group |
| AnnaBridge | 171:3a7713b1edbc | 65 | * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. |
| AnnaBridge | 171:3a7713b1edbc | 66 | * ADC state can be either: |
| AnnaBridge | 171:3a7713b1edbc | 67 | * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ClockPrescaler') |
| AnnaBridge | 171:3a7713b1edbc | 68 | * - For all parameters except 'ClockPrescaler' and 'resolution': ADC enabled without conversion on going on regular group. |
| AnnaBridge | 171:3a7713b1edbc | 69 | * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed |
| AnnaBridge | 171:3a7713b1edbc | 70 | * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). |
| AnnaBridge | 171:3a7713b1edbc | 71 | */ |
| AnnaBridge | 171:3a7713b1edbc | 72 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 73 | { |
| AnnaBridge | 171:3a7713b1edbc | 74 | uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from ADC dedicated HSI RC oscillator 14MHz) and clock prescaler. |
| AnnaBridge | 171:3a7713b1edbc | 75 | This parameter can be a value of @ref ADC_ClockPrescaler |
| AnnaBridge | 171:3a7713b1edbc | 76 | Note: In case of usage of the ADC dedicated HSI RC oscillator, it must be preliminarily enabled at RCC top level. |
| AnnaBridge | 171:3a7713b1edbc | 77 | Note: This parameter can be modified only if the ADC is disabled */ |
| AnnaBridge | 171:3a7713b1edbc | 78 | uint32_t Resolution; /*!< Configures the ADC resolution. |
| AnnaBridge | 171:3a7713b1edbc | 79 | This parameter can be a value of @ref ADC_Resolution */ |
| AnnaBridge | 171:3a7713b1edbc | 80 | uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right. |
| AnnaBridge | 171:3a7713b1edbc | 81 | This parameter can be a value of @ref ADC_Data_align */ |
| AnnaBridge | 171:3a7713b1edbc | 82 | uint32_t ScanConvMode; /*!< Configures the sequencer of regular group. |
| AnnaBridge | 171:3a7713b1edbc | 83 | This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. |
| AnnaBridge | 171:3a7713b1edbc | 84 | Sequencer is automatically enabled if several channels are set (sequencer cannot be disabled, as it can be the case on other STM32 devices): |
| AnnaBridge | 171:3a7713b1edbc | 85 | If only 1 channel is set: Conversion is performed in single mode. |
| AnnaBridge | 171:3a7713b1edbc | 86 | If several channels are set: Conversions are performed in sequence mode (ranks defined by each channel number: channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). |
| AnnaBridge | 171:3a7713b1edbc | 87 | Scan direction can be set to forward (from channel 0 to channel 18) or backward (from channel 18 to channel 0). |
| AnnaBridge | 171:3a7713b1edbc | 88 | This parameter can be a value of @ref ADC_Scan_mode */ |
| AnnaBridge | 171:3a7713b1edbc | 89 | uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence. |
| AnnaBridge | 171:3a7713b1edbc | 90 | This parameter can be a value of @ref ADC_EOCSelection. */ |
| AnnaBridge | 171:3a7713b1edbc | 91 | uint32_t LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous |
| AnnaBridge | 171:3a7713b1edbc | 92 | conversion (for regular group) has been treated by user software, using function HAL_ADC_GetValue(). |
| AnnaBridge | 171:3a7713b1edbc | 93 | This feature automatically adapts the ADC conversions trigs to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. |
| AnnaBridge | 171:3a7713b1edbc | 94 | This parameter can be set to ENABLE or DISABLE. |
| AnnaBridge | 171:3a7713b1edbc | 95 | Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer. |
| AnnaBridge | 171:3a7713b1edbc | 96 | Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed |
| AnnaBridge | 171:3a7713b1edbc | 97 | and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion. */ |
| AnnaBridge | 171:3a7713b1edbc | 98 | uint32_t LowPowerAutoPowerOff; /*!< Selects the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling). |
| AnnaBridge | 171:3a7713b1edbc | 99 | This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait'). |
| AnnaBridge | 171:3a7713b1edbc | 100 | This parameter can be set to ENABLE or DISABLE. |
| AnnaBridge | 171:3a7713b1edbc | 101 | Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */ |
| AnnaBridge | 171:3a7713b1edbc | 102 | uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, |
| AnnaBridge | 171:3a7713b1edbc | 103 | after the selected trigger occurred (software start or external trigger). |
| AnnaBridge | 171:3a7713b1edbc | 104 | This parameter can be set to ENABLE or DISABLE. */ |
| AnnaBridge | 171:3a7713b1edbc | 105 | uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). |
| AnnaBridge | 171:3a7713b1edbc | 106 | Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. |
| AnnaBridge | 171:3a7713b1edbc | 107 | Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. |
| AnnaBridge | 171:3a7713b1edbc | 108 | This parameter can be set to ENABLE or DISABLE |
| AnnaBridge | 171:3a7713b1edbc | 109 | Note: Number of discontinuous ranks increment is fixed to one-by-one. */ |
| AnnaBridge | 171:3a7713b1edbc | 110 | uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. |
| AnnaBridge | 171:3a7713b1edbc | 111 | If set to ADC_SOFTWARE_START, external triggers are disabled. |
| AnnaBridge | 171:3a7713b1edbc | 112 | This parameter can be a value of @ref ADC_External_trigger_source_Regular */ |
| AnnaBridge | 171:3a7713b1edbc | 113 | uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group. |
| AnnaBridge | 171:3a7713b1edbc | 114 | If trigger is set to ADC_SOFTWARE_START, this parameter is discarded. |
| AnnaBridge | 171:3a7713b1edbc | 115 | This parameter can be a value of @ref ADC_External_trigger_edge_Regular */ |
| AnnaBridge | 171:3a7713b1edbc | 116 | uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached) |
| AnnaBridge | 171:3a7713b1edbc | 117 | or in Continuous mode (DMA transfer unlimited, whatever number of conversions). |
| AnnaBridge | 171:3a7713b1edbc | 118 | Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. |
| AnnaBridge | 171:3a7713b1edbc | 119 | This parameter can be set to ENABLE or DISABLE. */ |
| AnnaBridge | 171:3a7713b1edbc | 120 | uint32_t Overrun; /*!< Select the behaviour in case of overrun: data preserved or overwritten |
| AnnaBridge | 171:3a7713b1edbc | 121 | This parameter has an effect on regular group only, including in DMA mode. |
| AnnaBridge | 171:3a7713b1edbc | 122 | This parameter can be a value of @ref ADC_Overrun */ |
| AnnaBridge | 171:3a7713b1edbc | 123 | uint32_t SamplingTimeCommon; /*!< Sampling time value to be set for the selected channel. |
| AnnaBridge | 171:3a7713b1edbc | 124 | Unit: ADC clock cycles |
| AnnaBridge | 171:3a7713b1edbc | 125 | Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). |
| AnnaBridge | 171:3a7713b1edbc | 126 | Note: On STM32F0 devices, the sampling time setting is common to all channels. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure. |
| AnnaBridge | 171:3a7713b1edbc | 127 | This parameter can be a value of @ref ADC_sampling_times |
| AnnaBridge | 171:3a7713b1edbc | 128 | Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), |
| AnnaBridge | 171:3a7713b1edbc | 129 | sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) |
| AnnaBridge | 171:3a7713b1edbc | 130 | Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17us). */ |
| AnnaBridge | 171:3a7713b1edbc | 131 | }ADC_InitTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 132 | |
| AnnaBridge | 171:3a7713b1edbc | 133 | /** |
| AnnaBridge | 171:3a7713b1edbc | 134 | * @brief Structure definition of ADC channel for regular group |
| AnnaBridge | 171:3a7713b1edbc | 135 | * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. |
| AnnaBridge | 171:3a7713b1edbc | 136 | * ADC state can be either: |
| AnnaBridge | 171:3a7713b1edbc | 137 | * - For all parameters: ADC disabled or enabled without conversion on going on regular group. |
| AnnaBridge | 171:3a7713b1edbc | 138 | * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed |
| AnnaBridge | 171:3a7713b1edbc | 139 | * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). |
| AnnaBridge | 171:3a7713b1edbc | 140 | */ |
| AnnaBridge | 171:3a7713b1edbc | 141 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 142 | { |
| AnnaBridge | 171:3a7713b1edbc | 143 | uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. |
| AnnaBridge | 171:3a7713b1edbc | 144 | This parameter can be a value of @ref ADC_channels |
| AnnaBridge | 171:3a7713b1edbc | 145 | Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */ |
| AnnaBridge | 171:3a7713b1edbc | 146 | uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer. |
| AnnaBridge | 171:3a7713b1edbc | 147 | On STM32F0 devices, number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).. |
| AnnaBridge | 171:3a7713b1edbc | 148 | Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer. |
| AnnaBridge | 171:3a7713b1edbc | 149 | This parameter can be a value of @ref ADC_rank */ |
| AnnaBridge | 171:3a7713b1edbc | 150 | uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. |
| AnnaBridge | 171:3a7713b1edbc | 151 | Unit: ADC clock cycles |
| AnnaBridge | 171:3a7713b1edbc | 152 | Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). |
| AnnaBridge | 171:3a7713b1edbc | 153 | This parameter can be a value of @ref ADC_sampling_times |
| AnnaBridge | 171:3a7713b1edbc | 154 | Caution: this setting impacts the entire regular group. Therefore, call of HAL_ADC_ConfigChannel() to configure a channel can impact the configuration of other channels previously set. |
| AnnaBridge | 171:3a7713b1edbc | 155 | Caution: Obsolete parameter. Use parameter "SamplingTimeCommon" in ADC initialization structure. |
| AnnaBridge | 171:3a7713b1edbc | 156 | If parameter "SamplingTimeCommon" is set to a valid sampling time, parameter "SamplingTime" is discarded. |
| AnnaBridge | 171:3a7713b1edbc | 157 | Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), |
| AnnaBridge | 171:3a7713b1edbc | 158 | sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) |
| AnnaBridge | 171:3a7713b1edbc | 159 | Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17us). */ |
| AnnaBridge | 171:3a7713b1edbc | 160 | }ADC_ChannelConfTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 161 | |
| AnnaBridge | 171:3a7713b1edbc | 162 | /** |
| AnnaBridge | 171:3a7713b1edbc | 163 | * @brief Structure definition of ADC analog watchdog |
| AnnaBridge | 171:3a7713b1edbc | 164 | * @note The setting of these parameters with function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. |
| AnnaBridge | 171:3a7713b1edbc | 165 | * ADC state can be either: ADC disabled or ADC enabled without conversion on going on regular group. |
| AnnaBridge | 171:3a7713b1edbc | 166 | */ |
| AnnaBridge | 171:3a7713b1edbc | 167 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 168 | { |
| AnnaBridge | 171:3a7713b1edbc | 169 | uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all/none channels. |
| AnnaBridge | 171:3a7713b1edbc | 170 | This parameter can be a value of @ref ADC_analog_watchdog_mode. */ |
| AnnaBridge | 171:3a7713b1edbc | 171 | uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog. |
| AnnaBridge | 171:3a7713b1edbc | 172 | This parameter has an effect only if parameter 'WatchdogMode' is configured on single channel. Only 1 channel can be monitored. |
| AnnaBridge | 171:3a7713b1edbc | 173 | This parameter can be a value of @ref ADC_channels. */ |
| AnnaBridge | 171:3a7713b1edbc | 174 | uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode. |
| AnnaBridge | 171:3a7713b1edbc | 175 | This parameter can be set to ENABLE or DISABLE */ |
| AnnaBridge | 171:3a7713b1edbc | 176 | uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. |
| AnnaBridge | 171:3a7713b1edbc | 177 | Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ |
| AnnaBridge | 171:3a7713b1edbc | 178 | uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. |
| AnnaBridge | 171:3a7713b1edbc | 179 | Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ |
| AnnaBridge | 171:3a7713b1edbc | 180 | }ADC_AnalogWDGConfTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 181 | |
| AnnaBridge | 171:3a7713b1edbc | 182 | /** |
| AnnaBridge | 171:3a7713b1edbc | 183 | * @brief HAL ADC state machine: ADC states definition (bitfields) |
| AnnaBridge | 171:3a7713b1edbc | 184 | * @note ADC state machine is managed by bitfields, state must be compared |
| AnnaBridge | 171:3a7713b1edbc | 185 | * with bit by bit. |
| AnnaBridge | 171:3a7713b1edbc | 186 | * For example: |
| AnnaBridge | 171:3a7713b1edbc | 187 | * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) " |
| AnnaBridge | 171:3a7713b1edbc | 188 | * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) " |
| AnnaBridge | 171:3a7713b1edbc | 189 | */ |
| AnnaBridge | 171:3a7713b1edbc | 190 | /* States of ADC global scope */ |
| AnnaBridge | 171:3a7713b1edbc | 191 | #define HAL_ADC_STATE_RESET (0x00000000U) /*!< ADC not yet initialized or disabled */ |
| AnnaBridge | 171:3a7713b1edbc | 192 | #define HAL_ADC_STATE_READY (0x00000001U) /*!< ADC peripheral ready for use */ |
| AnnaBridge | 171:3a7713b1edbc | 193 | #define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */ |
| AnnaBridge | 171:3a7713b1edbc | 194 | #define HAL_ADC_STATE_TIMEOUT (0x00000004U) /*!< TimeOut occurrence */ |
| AnnaBridge | 171:3a7713b1edbc | 195 | |
| AnnaBridge | 171:3a7713b1edbc | 196 | /* States of ADC errors */ |
| AnnaBridge | 171:3a7713b1edbc | 197 | #define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010U) /*!< Internal error occurrence */ |
| AnnaBridge | 171:3a7713b1edbc | 198 | #define HAL_ADC_STATE_ERROR_CONFIG (0x00000020U) /*!< Configuration error occurrence */ |
| AnnaBridge | 171:3a7713b1edbc | 199 | #define HAL_ADC_STATE_ERROR_DMA (0x00000040U) /*!< DMA error occurrence */ |
| AnnaBridge | 171:3a7713b1edbc | 200 | |
| AnnaBridge | 171:3a7713b1edbc | 201 | /* States of ADC group regular */ |
| AnnaBridge | 171:3a7713b1edbc | 202 | #define HAL_ADC_STATE_REG_BUSY (0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, |
| AnnaBridge | 171:3a7713b1edbc | 203 | external trigger, low power auto power-on, multimode ADC master control) */ |
| AnnaBridge | 171:3a7713b1edbc | 204 | #define HAL_ADC_STATE_REG_EOC (0x00000200U) /*!< Conversion data available on group regular */ |
| AnnaBridge | 171:3a7713b1edbc | 205 | #define HAL_ADC_STATE_REG_OVR (0x00000400U) /*!< Overrun occurrence */ |
| AnnaBridge | 171:3a7713b1edbc | 206 | #define HAL_ADC_STATE_REG_EOSMP (0x00000800U) /*!< Not available on STM32F0 device: End Of Sampling flag raised */ |
| AnnaBridge | 171:3a7713b1edbc | 207 | |
| AnnaBridge | 171:3a7713b1edbc | 208 | /* States of ADC group injected */ |
| AnnaBridge | 171:3a7713b1edbc | 209 | #define HAL_ADC_STATE_INJ_BUSY (0x00001000U) /*!< Not available on STM32F0 device: A conversion on group injected is ongoing or can occur (either by auto-injection mode, |
| AnnaBridge | 171:3a7713b1edbc | 210 | external trigger, low power auto power-on, multimode ADC master control) */ |
| AnnaBridge | 171:3a7713b1edbc | 211 | #define HAL_ADC_STATE_INJ_EOC (0x00002000U) /*!< Not available on STM32F0 device: Conversion data available on group injected */ |
| AnnaBridge | 171:3a7713b1edbc | 212 | #define HAL_ADC_STATE_INJ_JQOVF (0x00004000U) /*!< Not available on STM32F0 device: Not available on STM32F0 device: Injected queue overflow occurrence */ |
| AnnaBridge | 171:3a7713b1edbc | 213 | |
| AnnaBridge | 171:3a7713b1edbc | 214 | /* States of ADC analog watchdogs */ |
| AnnaBridge | 171:3a7713b1edbc | 215 | #define HAL_ADC_STATE_AWD1 (0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */ |
| AnnaBridge | 171:3a7713b1edbc | 216 | #define HAL_ADC_STATE_AWD2 (0x00020000U) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 2 */ |
| AnnaBridge | 171:3a7713b1edbc | 217 | #define HAL_ADC_STATE_AWD3 (0x00040000U) /*!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 3 */ |
| AnnaBridge | 171:3a7713b1edbc | 218 | |
| AnnaBridge | 171:3a7713b1edbc | 219 | /* States of ADC multi-mode */ |
| AnnaBridge | 171:3a7713b1edbc | 220 | #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000U) /*!< Not available on STM32F0 device: ADC in multimode slave state, controlled by another ADC master ( */ |
| AnnaBridge | 171:3a7713b1edbc | 221 | |
| AnnaBridge | 171:3a7713b1edbc | 222 | |
| AnnaBridge | 171:3a7713b1edbc | 223 | /** |
| AnnaBridge | 171:3a7713b1edbc | 224 | * @brief ADC handle Structure definition |
| AnnaBridge | 171:3a7713b1edbc | 225 | */ |
| AnnaBridge | 171:3a7713b1edbc | 226 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 227 | { |
| AnnaBridge | 171:3a7713b1edbc | 228 | ADC_TypeDef *Instance; /*!< Register base address */ |
| AnnaBridge | 171:3a7713b1edbc | 229 | |
| AnnaBridge | 171:3a7713b1edbc | 230 | ADC_InitTypeDef Init; /*!< ADC required parameters */ |
| AnnaBridge | 171:3a7713b1edbc | 231 | |
| AnnaBridge | 171:3a7713b1edbc | 232 | DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ |
| AnnaBridge | 171:3a7713b1edbc | 233 | |
| AnnaBridge | 171:3a7713b1edbc | 234 | HAL_LockTypeDef Lock; /*!< ADC locking object */ |
| AnnaBridge | 171:3a7713b1edbc | 235 | |
| AnnaBridge | 171:3a7713b1edbc | 236 | __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ |
| AnnaBridge | 171:3a7713b1edbc | 237 | |
| AnnaBridge | 171:3a7713b1edbc | 238 | __IO uint32_t ErrorCode; /*!< ADC Error code */ |
| AnnaBridge | 171:3a7713b1edbc | 239 | }ADC_HandleTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 240 | /** |
| AnnaBridge | 171:3a7713b1edbc | 241 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 242 | */ |
| AnnaBridge | 171:3a7713b1edbc | 243 | |
| AnnaBridge | 171:3a7713b1edbc | 244 | |
| AnnaBridge | 171:3a7713b1edbc | 245 | |
| AnnaBridge | 171:3a7713b1edbc | 246 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 247 | |
| AnnaBridge | 171:3a7713b1edbc | 248 | /** @defgroup ADC_Exported_Constants ADC Exported Constants |
| AnnaBridge | 171:3a7713b1edbc | 249 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 250 | */ |
| AnnaBridge | 171:3a7713b1edbc | 251 | |
| AnnaBridge | 171:3a7713b1edbc | 252 | /** @defgroup ADC_Error_Code ADC Error Code |
| AnnaBridge | 171:3a7713b1edbc | 253 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 254 | */ |
| AnnaBridge | 171:3a7713b1edbc | 255 | #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ |
| AnnaBridge | 171:3a7713b1edbc | 256 | #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC IP internal error: if problem of clocking, |
| AnnaBridge | 171:3a7713b1edbc | 257 | enable/disable, erroneous state */ |
| AnnaBridge | 171:3a7713b1edbc | 258 | #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ |
| AnnaBridge | 171:3a7713b1edbc | 259 | #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ |
| AnnaBridge | 171:3a7713b1edbc | 260 | |
| AnnaBridge | 171:3a7713b1edbc | 261 | /** |
| AnnaBridge | 171:3a7713b1edbc | 262 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 263 | */ |
| AnnaBridge | 171:3a7713b1edbc | 264 | |
| AnnaBridge | 171:3a7713b1edbc | 265 | /** @defgroup ADC_ClockPrescaler ADC ClockPrescaler |
| AnnaBridge | 171:3a7713b1edbc | 266 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 267 | */ |
| AnnaBridge | 171:3a7713b1edbc | 268 | #define ADC_CLOCK_ASYNC_DIV1 (0x00000000U) /*!< ADC asynchronous clock derived from ADC dedicated HSI */ |
| AnnaBridge | 171:3a7713b1edbc | 269 | |
| AnnaBridge | 171:3a7713b1edbc | 270 | #define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2 */ |
| AnnaBridge | 171:3a7713b1edbc | 271 | #define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4 */ |
| AnnaBridge | 171:3a7713b1edbc | 272 | |
| AnnaBridge | 171:3a7713b1edbc | 273 | /** |
| AnnaBridge | 171:3a7713b1edbc | 274 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 275 | */ |
| AnnaBridge | 171:3a7713b1edbc | 276 | |
| AnnaBridge | 171:3a7713b1edbc | 277 | /** @defgroup ADC_Resolution ADC Resolution |
| AnnaBridge | 171:3a7713b1edbc | 278 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 279 | */ |
| AnnaBridge | 171:3a7713b1edbc | 280 | #define ADC_RESOLUTION_12B (0x00000000U) /*!< ADC 12-bit resolution */ |
| AnnaBridge | 171:3a7713b1edbc | 281 | #define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR1_RES_0) /*!< ADC 10-bit resolution */ |
| AnnaBridge | 171:3a7713b1edbc | 282 | #define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR1_RES_1) /*!< ADC 8-bit resolution */ |
| AnnaBridge | 171:3a7713b1edbc | 283 | #define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR1_RES) /*!< ADC 6-bit resolution */ |
| AnnaBridge | 171:3a7713b1edbc | 284 | /** |
| AnnaBridge | 171:3a7713b1edbc | 285 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 286 | */ |
| AnnaBridge | 171:3a7713b1edbc | 287 | |
| AnnaBridge | 171:3a7713b1edbc | 288 | /** @defgroup ADC_Data_align ADC Data_align |
| AnnaBridge | 171:3a7713b1edbc | 289 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 290 | */ |
| AnnaBridge | 171:3a7713b1edbc | 291 | #define ADC_DATAALIGN_RIGHT (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 292 | #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR1_ALIGN) |
| AnnaBridge | 171:3a7713b1edbc | 293 | /** |
| AnnaBridge | 171:3a7713b1edbc | 294 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 295 | */ |
| AnnaBridge | 171:3a7713b1edbc | 296 | |
| AnnaBridge | 171:3a7713b1edbc | 297 | /** @defgroup ADC_Scan_mode ADC Scan mode |
| AnnaBridge | 171:3a7713b1edbc | 298 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 299 | */ |
| AnnaBridge | 171:3a7713b1edbc | 300 | /* Note: Scan mode values must be compatible with other STM32 devices having */ |
| AnnaBridge | 171:3a7713b1edbc | 301 | /* a configurable sequencer. */ |
| AnnaBridge | 171:3a7713b1edbc | 302 | /* Scan direction setting values are defined by taking in account */ |
| AnnaBridge | 171:3a7713b1edbc | 303 | /* already defined values for other STM32 devices: */ |
| AnnaBridge | 171:3a7713b1edbc | 304 | /* ADC_SCAN_DISABLE (0x00000000U) */ |
| AnnaBridge | 171:3a7713b1edbc | 305 | /* ADC_SCAN_ENABLE (0x00000001U) */ |
| AnnaBridge | 171:3a7713b1edbc | 306 | /* Scan direction forward is considered as default setting equivalent */ |
| AnnaBridge | 171:3a7713b1edbc | 307 | /* to scan enable. */ |
| AnnaBridge | 171:3a7713b1edbc | 308 | /* Scan direction backward is considered as additional setting. */ |
| AnnaBridge | 171:3a7713b1edbc | 309 | /* In case of migration from another STM32 device, the user will be */ |
| AnnaBridge | 171:3a7713b1edbc | 310 | /* warned of change of setting choices with assert check. */ |
| AnnaBridge | 171:3a7713b1edbc | 311 | #define ADC_SCAN_DIRECTION_FORWARD (0x00000001U) /*!< Scan direction forward: from channel 0 to channel 18 */ |
| AnnaBridge | 171:3a7713b1edbc | 312 | #define ADC_SCAN_DIRECTION_BACKWARD (0x00000002U) /*!< Scan direction backward: from channel 18 to channel 0 */ |
| AnnaBridge | 171:3a7713b1edbc | 313 | |
| AnnaBridge | 171:3a7713b1edbc | 314 | #define ADC_SCAN_ENABLE ADC_SCAN_DIRECTION_FORWARD /* For compatibility with other STM32 devices */ |
| AnnaBridge | 171:3a7713b1edbc | 315 | |
| AnnaBridge | 171:3a7713b1edbc | 316 | /** |
| AnnaBridge | 171:3a7713b1edbc | 317 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 318 | */ |
| AnnaBridge | 171:3a7713b1edbc | 319 | |
| AnnaBridge | 171:3a7713b1edbc | 320 | /** @defgroup ADC_External_trigger_edge_Regular ADC External trigger edge Regular |
| AnnaBridge | 171:3a7713b1edbc | 321 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 322 | */ |
| AnnaBridge | 171:3a7713b1edbc | 323 | #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 324 | #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR1_EXTEN_0) |
| AnnaBridge | 171:3a7713b1edbc | 325 | #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR1_EXTEN_1) |
| AnnaBridge | 171:3a7713b1edbc | 326 | #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR1_EXTEN) |
| AnnaBridge | 171:3a7713b1edbc | 327 | /** |
| AnnaBridge | 171:3a7713b1edbc | 328 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 329 | */ |
| AnnaBridge | 171:3a7713b1edbc | 330 | |
| AnnaBridge | 171:3a7713b1edbc | 331 | /** @defgroup ADC_EOCSelection ADC EOCSelection |
| AnnaBridge | 171:3a7713b1edbc | 332 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 333 | */ |
| AnnaBridge | 171:3a7713b1edbc | 334 | #define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC) |
| AnnaBridge | 171:3a7713b1edbc | 335 | #define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS) |
| AnnaBridge | 171:3a7713b1edbc | 336 | /** |
| AnnaBridge | 171:3a7713b1edbc | 337 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 338 | */ |
| AnnaBridge | 171:3a7713b1edbc | 339 | |
| AnnaBridge | 171:3a7713b1edbc | 340 | /** @defgroup ADC_Overrun ADC Overrun |
| AnnaBridge | 171:3a7713b1edbc | 341 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 342 | */ |
| AnnaBridge | 171:3a7713b1edbc | 343 | #define ADC_OVR_DATA_OVERWRITTEN (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 344 | #define ADC_OVR_DATA_PRESERVED (0x00000001U) |
| AnnaBridge | 171:3a7713b1edbc | 345 | /** |
| AnnaBridge | 171:3a7713b1edbc | 346 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 347 | */ |
| AnnaBridge | 171:3a7713b1edbc | 348 | |
| AnnaBridge | 171:3a7713b1edbc | 349 | /** @defgroup ADC_rank ADC rank |
| AnnaBridge | 171:3a7713b1edbc | 350 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 351 | */ |
| AnnaBridge | 171:3a7713b1edbc | 352 | #define ADC_RANK_CHANNEL_NUMBER (0x00001000U) /*!< Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */ |
| AnnaBridge | 171:3a7713b1edbc | 353 | #define ADC_RANK_NONE (0x00001001U) /*!< Disable the selected rank (selected channel) from sequencer */ |
| AnnaBridge | 171:3a7713b1edbc | 354 | /** |
| AnnaBridge | 171:3a7713b1edbc | 355 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 356 | */ |
| AnnaBridge | 171:3a7713b1edbc | 357 | |
| AnnaBridge | 171:3a7713b1edbc | 358 | /** @defgroup ADC_sampling_times ADC sampling times |
| AnnaBridge | 171:3a7713b1edbc | 359 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 360 | */ |
| AnnaBridge | 171:3a7713b1edbc | 361 | /* Note: Parameter "ADC_SAMPLETIME_1CYCLE_5" defined with a dummy bit */ |
| AnnaBridge | 171:3a7713b1edbc | 362 | /* to distinguish this parameter versus reset value 0x00000000, */ |
| AnnaBridge | 171:3a7713b1edbc | 363 | /* in the context of management of parameters "SamplingTimeCommon" */ |
| AnnaBridge | 171:3a7713b1edbc | 364 | /* and "SamplingTime" (obsolete)). */ |
| AnnaBridge | 171:3a7713b1edbc | 365 | #define ADC_SAMPLETIME_1CYCLE_5 (0x10000000U) /*!< Sampling time 1.5 ADC clock cycle */ |
| AnnaBridge | 171:3a7713b1edbc | 366 | #define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t) ADC_SMPR_SMP_0) /*!< Sampling time 7.5 ADC clock cycles */ |
| AnnaBridge | 171:3a7713b1edbc | 367 | #define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t) ADC_SMPR_SMP_1) /*!< Sampling time 13.5 ADC clock cycles */ |
| AnnaBridge | 171:3a7713b1edbc | 368 | #define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0)) /*!< Sampling time 28.5 ADC clock cycles */ |
| AnnaBridge | 171:3a7713b1edbc | 369 | #define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t) ADC_SMPR_SMP_2) /*!< Sampling time 41.5 ADC clock cycles */ |
| AnnaBridge | 171:3a7713b1edbc | 370 | #define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_2 | ADC_SMPR_SMP_0)) /*!< Sampling time 55.5 ADC clock cycles */ |
| AnnaBridge | 171:3a7713b1edbc | 371 | #define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1)) /*!< Sampling time 71.5 ADC clock cycles */ |
| AnnaBridge | 171:3a7713b1edbc | 372 | #define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t) ADC_SMPR_SMP) /*!< Sampling time 239.5 ADC clock cycles */ |
| AnnaBridge | 171:3a7713b1edbc | 373 | /** |
| AnnaBridge | 171:3a7713b1edbc | 374 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 375 | */ |
| AnnaBridge | 171:3a7713b1edbc | 376 | |
| AnnaBridge | 171:3a7713b1edbc | 377 | /** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode |
| AnnaBridge | 171:3a7713b1edbc | 378 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 379 | */ |
| AnnaBridge | 171:3a7713b1edbc | 380 | #define ADC_ANALOGWATCHDOG_NONE ( 0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 381 | #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN)) |
| AnnaBridge | 171:3a7713b1edbc | 382 | #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR1_AWDEN) |
| AnnaBridge | 171:3a7713b1edbc | 383 | /** |
| AnnaBridge | 171:3a7713b1edbc | 384 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 385 | */ |
| AnnaBridge | 171:3a7713b1edbc | 386 | |
| AnnaBridge | 171:3a7713b1edbc | 387 | /** @defgroup ADC_Event_type ADC Event type |
| AnnaBridge | 171:3a7713b1edbc | 388 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 389 | */ |
| AnnaBridge | 171:3a7713b1edbc | 390 | #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog 1 event */ |
| AnnaBridge | 171:3a7713b1edbc | 391 | #define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */ |
| AnnaBridge | 171:3a7713b1edbc | 392 | /** |
| AnnaBridge | 171:3a7713b1edbc | 393 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 394 | */ |
| AnnaBridge | 171:3a7713b1edbc | 395 | |
| AnnaBridge | 171:3a7713b1edbc | 396 | /** @defgroup ADC_interrupts_definition ADC interrupts definition |
| AnnaBridge | 171:3a7713b1edbc | 397 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 398 | */ |
| AnnaBridge | 171:3a7713b1edbc | 399 | #define ADC_IT_AWD ADC_IER_AWDIE /*!< ADC Analog watchdog interrupt source */ |
| AnnaBridge | 171:3a7713b1edbc | 400 | #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ |
| AnnaBridge | 171:3a7713b1edbc | 401 | #define ADC_IT_EOS ADC_IER_EOSEQIE /*!< ADC End of Regular sequence of Conversions interrupt source */ |
| AnnaBridge | 171:3a7713b1edbc | 402 | #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of Regular Conversion interrupt source */ |
| AnnaBridge | 171:3a7713b1edbc | 403 | #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of Sampling interrupt source */ |
| AnnaBridge | 171:3a7713b1edbc | 404 | #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ |
| AnnaBridge | 171:3a7713b1edbc | 405 | /** |
| AnnaBridge | 171:3a7713b1edbc | 406 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 407 | */ |
| AnnaBridge | 171:3a7713b1edbc | 408 | |
| AnnaBridge | 171:3a7713b1edbc | 409 | /** @defgroup ADC_flags_definition ADC flags definition |
| AnnaBridge | 171:3a7713b1edbc | 410 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 411 | */ |
| AnnaBridge | 171:3a7713b1edbc | 412 | #define ADC_FLAG_AWD ADC_ISR_AWD /*!< ADC Analog watchdog flag */ |
| AnnaBridge | 171:3a7713b1edbc | 413 | #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ |
| AnnaBridge | 171:3a7713b1edbc | 414 | #define ADC_FLAG_EOS ADC_ISR_EOSEQ /*!< ADC End of Regular sequence of Conversions flag */ |
| AnnaBridge | 171:3a7713b1edbc | 415 | #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ |
| AnnaBridge | 171:3a7713b1edbc | 416 | #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ |
| AnnaBridge | 171:3a7713b1edbc | 417 | #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ |
| AnnaBridge | 171:3a7713b1edbc | 418 | /** |
| AnnaBridge | 171:3a7713b1edbc | 419 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 420 | */ |
| AnnaBridge | 171:3a7713b1edbc | 421 | |
| AnnaBridge | 171:3a7713b1edbc | 422 | /** |
| AnnaBridge | 171:3a7713b1edbc | 423 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 424 | */ |
| AnnaBridge | 171:3a7713b1edbc | 425 | |
| AnnaBridge | 171:3a7713b1edbc | 426 | |
| AnnaBridge | 171:3a7713b1edbc | 427 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 428 | |
| AnnaBridge | 171:3a7713b1edbc | 429 | /** @addtogroup ADC_Private_Constants ADC Private Constants |
| AnnaBridge | 171:3a7713b1edbc | 430 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 431 | */ |
| AnnaBridge | 171:3a7713b1edbc | 432 | |
| AnnaBridge | 171:3a7713b1edbc | 433 | /** @defgroup ADC_Internal_HAL_driver_Ext_trig_src_Regular ADC Internal HAL driver Ext trig src Regular |
| AnnaBridge | 171:3a7713b1edbc | 434 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 435 | */ |
| AnnaBridge | 171:3a7713b1edbc | 436 | |
| AnnaBridge | 171:3a7713b1edbc | 437 | /* List of external triggers of regular group for ADC1: */ |
| AnnaBridge | 171:3a7713b1edbc | 438 | /* (used internally by HAL driver. To not use into HAL structure parameters) */ |
| AnnaBridge | 171:3a7713b1edbc | 439 | #define ADC1_2_EXTERNALTRIG_T1_TRGO (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 440 | #define ADC1_2_EXTERNALTRIG_T1_CC4 ((uint32_t)ADC_CFGR1_EXTSEL_0) |
| AnnaBridge | 171:3a7713b1edbc | 441 | #define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)ADC_CFGR1_EXTSEL_1) |
| AnnaBridge | 171:3a7713b1edbc | 442 | #define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0)) |
| AnnaBridge | 171:3a7713b1edbc | 443 | #define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)ADC_CFGR1_EXTSEL_2) |
| AnnaBridge | 171:3a7713b1edbc | 444 | /** |
| AnnaBridge | 171:3a7713b1edbc | 445 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 446 | */ |
| AnnaBridge | 171:3a7713b1edbc | 447 | |
| AnnaBridge | 171:3a7713b1edbc | 448 | /* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */ |
| AnnaBridge | 171:3a7713b1edbc | 449 | #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC) |
| AnnaBridge | 171:3a7713b1edbc | 450 | |
| AnnaBridge | 171:3a7713b1edbc | 451 | /** |
| AnnaBridge | 171:3a7713b1edbc | 452 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 453 | */ |
| AnnaBridge | 171:3a7713b1edbc | 454 | |
| AnnaBridge | 171:3a7713b1edbc | 455 | |
| AnnaBridge | 171:3a7713b1edbc | 456 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 457 | |
| AnnaBridge | 171:3a7713b1edbc | 458 | /** @defgroup ADC_Exported_Macros ADC Exported Macros |
| AnnaBridge | 171:3a7713b1edbc | 459 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 460 | */ |
| AnnaBridge | 171:3a7713b1edbc | 461 | /* Macro for internal HAL driver usage, and possibly can be used into code of */ |
| AnnaBridge | 171:3a7713b1edbc | 462 | /* final user. */ |
| AnnaBridge | 171:3a7713b1edbc | 463 | |
| AnnaBridge | 171:3a7713b1edbc | 464 | /** |
| AnnaBridge | 171:3a7713b1edbc | 465 | * @brief Enable the ADC peripheral |
| AnnaBridge | 171:3a7713b1edbc | 466 | * @param __HANDLE__ ADC handle |
| AnnaBridge | 171:3a7713b1edbc | 467 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 468 | */ |
| AnnaBridge | 171:3a7713b1edbc | 469 | #define __HAL_ADC_ENABLE(__HANDLE__) \ |
| AnnaBridge | 171:3a7713b1edbc | 470 | ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN) |
| AnnaBridge | 171:3a7713b1edbc | 471 | |
| AnnaBridge | 171:3a7713b1edbc | 472 | /** |
| AnnaBridge | 171:3a7713b1edbc | 473 | * @brief Disable the ADC peripheral |
| AnnaBridge | 171:3a7713b1edbc | 474 | * @param __HANDLE__ ADC handle |
| AnnaBridge | 171:3a7713b1edbc | 475 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 476 | */ |
| AnnaBridge | 171:3a7713b1edbc | 477 | #define __HAL_ADC_DISABLE(__HANDLE__) \ |
| AnnaBridge | 171:3a7713b1edbc | 478 | do{ \ |
| AnnaBridge | 171:3a7713b1edbc | 479 | (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS; \ |
| AnnaBridge | 171:3a7713b1edbc | 480 | __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \ |
| AnnaBridge | 171:3a7713b1edbc | 481 | } while(0) |
| AnnaBridge | 171:3a7713b1edbc | 482 | |
| AnnaBridge | 171:3a7713b1edbc | 483 | /** |
| AnnaBridge | 171:3a7713b1edbc | 484 | * @brief Enable the ADC end of conversion interrupt. |
| AnnaBridge | 171:3a7713b1edbc | 485 | * @param __HANDLE__ ADC handle |
| AnnaBridge | 171:3a7713b1edbc | 486 | * @param __INTERRUPT__ ADC Interrupt |
| AnnaBridge | 171:3a7713b1edbc | 487 | * This parameter can be any combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 488 | * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source |
| AnnaBridge | 171:3a7713b1edbc | 489 | * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source |
| AnnaBridge | 171:3a7713b1edbc | 490 | * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source |
| AnnaBridge | 171:3a7713b1edbc | 491 | * @arg ADC_IT_OVR: ADC overrun interrupt source |
| AnnaBridge | 171:3a7713b1edbc | 492 | * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source |
| AnnaBridge | 171:3a7713b1edbc | 493 | * @arg ADC_IT_RDY: ADC Ready interrupt source |
| AnnaBridge | 171:3a7713b1edbc | 494 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 495 | */ |
| AnnaBridge | 171:3a7713b1edbc | 496 | #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ |
| AnnaBridge | 171:3a7713b1edbc | 497 | (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) |
| AnnaBridge | 171:3a7713b1edbc | 498 | |
| AnnaBridge | 171:3a7713b1edbc | 499 | /** |
| AnnaBridge | 171:3a7713b1edbc | 500 | * @brief Disable the ADC end of conversion interrupt. |
| AnnaBridge | 171:3a7713b1edbc | 501 | * @param __HANDLE__ ADC handle |
| AnnaBridge | 171:3a7713b1edbc | 502 | * @param __INTERRUPT__ ADC Interrupt |
| AnnaBridge | 171:3a7713b1edbc | 503 | * This parameter can be any combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 504 | * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source |
| AnnaBridge | 171:3a7713b1edbc | 505 | * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source |
| AnnaBridge | 171:3a7713b1edbc | 506 | * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source |
| AnnaBridge | 171:3a7713b1edbc | 507 | * @arg ADC_IT_OVR: ADC overrun interrupt source |
| AnnaBridge | 171:3a7713b1edbc | 508 | * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source |
| AnnaBridge | 171:3a7713b1edbc | 509 | * @arg ADC_IT_RDY: ADC Ready interrupt source |
| AnnaBridge | 171:3a7713b1edbc | 510 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 511 | */ |
| AnnaBridge | 171:3a7713b1edbc | 512 | #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ |
| AnnaBridge | 171:3a7713b1edbc | 513 | (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) |
| AnnaBridge | 171:3a7713b1edbc | 514 | |
| AnnaBridge | 171:3a7713b1edbc | 515 | /** @brief Checks if the specified ADC interrupt source is enabled or disabled. |
| AnnaBridge | 171:3a7713b1edbc | 516 | * @param __HANDLE__ ADC handle |
| AnnaBridge | 171:3a7713b1edbc | 517 | * @param __INTERRUPT__ ADC interrupt source to check |
| AnnaBridge | 171:3a7713b1edbc | 518 | * This parameter can be any combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 519 | * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source |
| AnnaBridge | 171:3a7713b1edbc | 520 | * @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source |
| AnnaBridge | 171:3a7713b1edbc | 521 | * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source |
| AnnaBridge | 171:3a7713b1edbc | 522 | * @arg ADC_IT_OVR: ADC overrun interrupt source |
| AnnaBridge | 171:3a7713b1edbc | 523 | * @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source |
| AnnaBridge | 171:3a7713b1edbc | 524 | * @arg ADC_IT_RDY: ADC Ready interrupt source |
| AnnaBridge | 171:3a7713b1edbc | 525 | * @retval State ofinterruption (SET or RESET) |
| AnnaBridge | 171:3a7713b1edbc | 526 | */ |
| AnnaBridge | 171:3a7713b1edbc | 527 | #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ |
| AnnaBridge | 171:3a7713b1edbc | 528 | (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) |
| AnnaBridge | 171:3a7713b1edbc | 529 | |
| AnnaBridge | 171:3a7713b1edbc | 530 | /** |
| AnnaBridge | 171:3a7713b1edbc | 531 | * @brief Get the selected ADC's flag status. |
| AnnaBridge | 171:3a7713b1edbc | 532 | * @param __HANDLE__ ADC handle |
| AnnaBridge | 171:3a7713b1edbc | 533 | * @param __FLAG__ ADC flag |
| AnnaBridge | 171:3a7713b1edbc | 534 | * This parameter can be any combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 535 | * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag |
| AnnaBridge | 171:3a7713b1edbc | 536 | * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag |
| AnnaBridge | 171:3a7713b1edbc | 537 | * @arg ADC_FLAG_AWD: ADC Analog watchdog flag |
| AnnaBridge | 171:3a7713b1edbc | 538 | * @arg ADC_FLAG_OVR: ADC overrun flag |
| AnnaBridge | 171:3a7713b1edbc | 539 | * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag |
| AnnaBridge | 171:3a7713b1edbc | 540 | * @arg ADC_FLAG_RDY: ADC Ready flag |
| AnnaBridge | 171:3a7713b1edbc | 541 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 542 | */ |
| AnnaBridge | 171:3a7713b1edbc | 543 | #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ |
| AnnaBridge | 171:3a7713b1edbc | 544 | ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) |
| AnnaBridge | 171:3a7713b1edbc | 545 | |
| AnnaBridge | 171:3a7713b1edbc | 546 | /** |
| AnnaBridge | 171:3a7713b1edbc | 547 | * @brief Clear the ADC's pending flags |
| AnnaBridge | 171:3a7713b1edbc | 548 | * @param __HANDLE__ ADC handle |
| AnnaBridge | 171:3a7713b1edbc | 549 | * @param __FLAG__ ADC flag |
| AnnaBridge | 171:3a7713b1edbc | 550 | * This parameter can be any combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 551 | * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag |
| AnnaBridge | 171:3a7713b1edbc | 552 | * @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag |
| AnnaBridge | 171:3a7713b1edbc | 553 | * @arg ADC_FLAG_AWD: ADC Analog watchdog flag |
| AnnaBridge | 171:3a7713b1edbc | 554 | * @arg ADC_FLAG_OVR: ADC overrun flag |
| AnnaBridge | 171:3a7713b1edbc | 555 | * @arg ADC_FLAG_EOSMP: ADC End of Sampling flag |
| AnnaBridge | 171:3a7713b1edbc | 556 | * @arg ADC_FLAG_RDY: ADC Ready flag |
| AnnaBridge | 171:3a7713b1edbc | 557 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 558 | */ |
| AnnaBridge | 171:3a7713b1edbc | 559 | /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ |
| AnnaBridge | 171:3a7713b1edbc | 560 | #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ |
| AnnaBridge | 171:3a7713b1edbc | 561 | (((__HANDLE__)->Instance->ISR) = (__FLAG__)) |
| AnnaBridge | 171:3a7713b1edbc | 562 | |
| AnnaBridge | 171:3a7713b1edbc | 563 | /** @brief Reset ADC handle state |
| AnnaBridge | 171:3a7713b1edbc | 564 | * @param __HANDLE__ ADC handle |
| AnnaBridge | 171:3a7713b1edbc | 565 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 566 | */ |
| AnnaBridge | 171:3a7713b1edbc | 567 | #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ |
| AnnaBridge | 171:3a7713b1edbc | 568 | ((__HANDLE__)->State = HAL_ADC_STATE_RESET) |
| AnnaBridge | 171:3a7713b1edbc | 569 | |
| AnnaBridge | 171:3a7713b1edbc | 570 | /** |
| AnnaBridge | 171:3a7713b1edbc | 571 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 572 | */ |
| AnnaBridge | 171:3a7713b1edbc | 573 | |
| AnnaBridge | 171:3a7713b1edbc | 574 | |
| AnnaBridge | 171:3a7713b1edbc | 575 | /* Private macro -------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 576 | |
| AnnaBridge | 171:3a7713b1edbc | 577 | /** @defgroup ADC_Private_Macros ADC Private Macros |
| AnnaBridge | 171:3a7713b1edbc | 578 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 579 | */ |
| AnnaBridge | 171:3a7713b1edbc | 580 | /* Macro reserved for internal HAL driver usage, not intended to be used in */ |
| AnnaBridge | 171:3a7713b1edbc | 581 | /* code of final user. */ |
| AnnaBridge | 171:3a7713b1edbc | 582 | |
| AnnaBridge | 171:3a7713b1edbc | 583 | |
| AnnaBridge | 171:3a7713b1edbc | 584 | /** |
| AnnaBridge | 171:3a7713b1edbc | 585 | * @brief Verification of hardware constraints before ADC can be enabled |
| AnnaBridge | 171:3a7713b1edbc | 586 | * @param __HANDLE__ ADC handle |
| AnnaBridge | 171:3a7713b1edbc | 587 | * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled) |
| AnnaBridge | 171:3a7713b1edbc | 588 | */ |
| AnnaBridge | 171:3a7713b1edbc | 589 | #define ADC_ENABLING_CONDITIONS(__HANDLE__) \ |
| AnnaBridge | 171:3a7713b1edbc | 590 | (( ( ((__HANDLE__)->Instance->CR) & \ |
| AnnaBridge | 171:3a7713b1edbc | 591 | (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) \ |
| AnnaBridge | 171:3a7713b1edbc | 592 | ) == RESET \ |
| AnnaBridge | 171:3a7713b1edbc | 593 | ) ? SET : RESET) |
| AnnaBridge | 171:3a7713b1edbc | 594 | |
| AnnaBridge | 171:3a7713b1edbc | 595 | /** |
| AnnaBridge | 171:3a7713b1edbc | 596 | * @brief Verification of hardware constraints before ADC can be disabled |
| AnnaBridge | 171:3a7713b1edbc | 597 | * @param __HANDLE__ ADC handle |
| AnnaBridge | 171:3a7713b1edbc | 598 | * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled) |
| AnnaBridge | 171:3a7713b1edbc | 599 | */ |
| AnnaBridge | 171:3a7713b1edbc | 600 | #define ADC_DISABLING_CONDITIONS(__HANDLE__) \ |
| AnnaBridge | 171:3a7713b1edbc | 601 | (( ( ((__HANDLE__)->Instance->CR) & \ |
| AnnaBridge | 171:3a7713b1edbc | 602 | (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \ |
| AnnaBridge | 171:3a7713b1edbc | 603 | ) ? SET : RESET) |
| AnnaBridge | 171:3a7713b1edbc | 604 | |
| AnnaBridge | 171:3a7713b1edbc | 605 | /** |
| AnnaBridge | 171:3a7713b1edbc | 606 | * @brief Verification of ADC state: enabled or disabled |
| AnnaBridge | 171:3a7713b1edbc | 607 | * @param __HANDLE__ ADC handle |
| AnnaBridge | 171:3a7713b1edbc | 608 | * @retval SET (ADC enabled) or RESET (ADC disabled) |
| AnnaBridge | 171:3a7713b1edbc | 609 | */ |
| AnnaBridge | 171:3a7713b1edbc | 610 | /* Note: If low power mode AutoPowerOff is enabled, power-on/off phases are */ |
| AnnaBridge | 171:3a7713b1edbc | 611 | /* performed automatically by hardware and flag ADC_FLAG_RDY is not */ |
| AnnaBridge | 171:3a7713b1edbc | 612 | /* set. */ |
| AnnaBridge | 171:3a7713b1edbc | 613 | #define ADC_IS_ENABLE(__HANDLE__) \ |
| AnnaBridge | 171:3a7713b1edbc | 614 | (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ |
| AnnaBridge | 171:3a7713b1edbc | 615 | (((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) || \ |
| AnnaBridge | 171:3a7713b1edbc | 616 | ((((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_AUTOFF) == ADC_CFGR1_AUTOFF) ) \ |
| AnnaBridge | 171:3a7713b1edbc | 617 | ) ? SET : RESET) |
| AnnaBridge | 171:3a7713b1edbc | 618 | |
| AnnaBridge | 171:3a7713b1edbc | 619 | /** |
| AnnaBridge | 171:3a7713b1edbc | 620 | * @brief Test if conversion trigger of regular group is software start |
| AnnaBridge | 171:3a7713b1edbc | 621 | * or external trigger. |
| AnnaBridge | 171:3a7713b1edbc | 622 | * @param __HANDLE__ ADC handle |
| AnnaBridge | 171:3a7713b1edbc | 623 | * @retval SET (software start) or RESET (external trigger) |
| AnnaBridge | 171:3a7713b1edbc | 624 | */ |
| AnnaBridge | 171:3a7713b1edbc | 625 | #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ |
| AnnaBridge | 171:3a7713b1edbc | 626 | (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == RESET) |
| AnnaBridge | 171:3a7713b1edbc | 627 | |
| AnnaBridge | 171:3a7713b1edbc | 628 | /** |
| AnnaBridge | 171:3a7713b1edbc | 629 | * @brief Check if no conversion on going on regular group |
| AnnaBridge | 171:3a7713b1edbc | 630 | * @param __HANDLE__ ADC handle |
| AnnaBridge | 171:3a7713b1edbc | 631 | * @retval SET (conversion is on going) or RESET (no conversion is on going) |
| AnnaBridge | 171:3a7713b1edbc | 632 | */ |
| AnnaBridge | 171:3a7713b1edbc | 633 | #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \ |
| AnnaBridge | 171:3a7713b1edbc | 634 | (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \ |
| AnnaBridge | 171:3a7713b1edbc | 635 | ) ? RESET : SET) |
| AnnaBridge | 171:3a7713b1edbc | 636 | |
| AnnaBridge | 171:3a7713b1edbc | 637 | /** |
| AnnaBridge | 171:3a7713b1edbc | 638 | * @brief Returns resolution bits in CFGR1 register: RES[1:0]. |
| AnnaBridge | 171:3a7713b1edbc | 639 | * Returned value is among parameters to @ref ADC_Resolution. |
| AnnaBridge | 171:3a7713b1edbc | 640 | * @param __HANDLE__ ADC handle |
| AnnaBridge | 171:3a7713b1edbc | 641 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 642 | */ |
| AnnaBridge | 171:3a7713b1edbc | 643 | #define ADC_GET_RESOLUTION(__HANDLE__) \ |
| AnnaBridge | 171:3a7713b1edbc | 644 | (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES) |
| AnnaBridge | 171:3a7713b1edbc | 645 | |
| AnnaBridge | 171:3a7713b1edbc | 646 | /** |
| AnnaBridge | 171:3a7713b1edbc | 647 | * @brief Returns ADC sample time bits in SMPR register: SMP[2:0]. |
| AnnaBridge | 171:3a7713b1edbc | 648 | * Returned value is among parameters to @ref ADC_Resolution. |
| AnnaBridge | 171:3a7713b1edbc | 649 | * @param __HANDLE__ ADC handle |
| AnnaBridge | 171:3a7713b1edbc | 650 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 651 | */ |
| AnnaBridge | 171:3a7713b1edbc | 652 | #define ADC_GET_SAMPLINGTIME(__HANDLE__) \ |
| AnnaBridge | 171:3a7713b1edbc | 653 | (((__HANDLE__)->Instance->SMPR) & ADC_SMPR_SMP) |
| AnnaBridge | 171:3a7713b1edbc | 654 | |
| AnnaBridge | 171:3a7713b1edbc | 655 | /** |
| AnnaBridge | 171:3a7713b1edbc | 656 | * @brief Simultaneously clears and sets specific bits of the handle State |
| AnnaBridge | 171:3a7713b1edbc | 657 | * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), |
| AnnaBridge | 171:3a7713b1edbc | 658 | * the first parameter is the ADC handle State, the second parameter is the |
| AnnaBridge | 171:3a7713b1edbc | 659 | * bit field to clear, the third and last parameter is the bit field to set. |
| AnnaBridge | 171:3a7713b1edbc | 660 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 661 | */ |
| AnnaBridge | 171:3a7713b1edbc | 662 | #define ADC_STATE_CLR_SET MODIFY_REG |
| AnnaBridge | 171:3a7713b1edbc | 663 | |
| AnnaBridge | 171:3a7713b1edbc | 664 | /** |
| AnnaBridge | 171:3a7713b1edbc | 665 | * @brief Clear ADC error code (set it to error code: "no error") |
| AnnaBridge | 171:3a7713b1edbc | 666 | * @param __HANDLE__ ADC handle |
| AnnaBridge | 171:3a7713b1edbc | 667 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 668 | */ |
| AnnaBridge | 171:3a7713b1edbc | 669 | #define ADC_CLEAR_ERRORCODE(__HANDLE__) \ |
| AnnaBridge | 171:3a7713b1edbc | 670 | ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) |
| AnnaBridge | 171:3a7713b1edbc | 671 | |
| AnnaBridge | 171:3a7713b1edbc | 672 | |
| AnnaBridge | 171:3a7713b1edbc | 673 | /** |
| AnnaBridge | 171:3a7713b1edbc | 674 | * @brief Configure the channel number into channel selection register |
| AnnaBridge | 171:3a7713b1edbc | 675 | * @param _CHANNEL_ ADC Channel |
| AnnaBridge | 171:3a7713b1edbc | 676 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 677 | */ |
| AnnaBridge | 171:3a7713b1edbc | 678 | /* This function converts ADC channels from numbers (see defgroup ADC_channels) |
| AnnaBridge | 171:3a7713b1edbc | 679 | to bitfields, to get the equivalence of CMSIS channels: |
| AnnaBridge | 171:3a7713b1edbc | 680 | ADC_CHANNEL_0 ((uint32_t) ADC_CHSELR_CHSEL0) |
| AnnaBridge | 171:3a7713b1edbc | 681 | ADC_CHANNEL_1 ((uint32_t) ADC_CHSELR_CHSEL1) |
| AnnaBridge | 171:3a7713b1edbc | 682 | ADC_CHANNEL_2 ((uint32_t) ADC_CHSELR_CHSEL2) |
| AnnaBridge | 171:3a7713b1edbc | 683 | ADC_CHANNEL_3 ((uint32_t) ADC_CHSELR_CHSEL3) |
| AnnaBridge | 171:3a7713b1edbc | 684 | ADC_CHANNEL_4 ((uint32_t) ADC_CHSELR_CHSEL4) |
| AnnaBridge | 171:3a7713b1edbc | 685 | ADC_CHANNEL_5 ((uint32_t) ADC_CHSELR_CHSEL5) |
| AnnaBridge | 171:3a7713b1edbc | 686 | ADC_CHANNEL_6 ((uint32_t) ADC_CHSELR_CHSEL6) |
| AnnaBridge | 171:3a7713b1edbc | 687 | ADC_CHANNEL_7 ((uint32_t) ADC_CHSELR_CHSEL7) |
| AnnaBridge | 171:3a7713b1edbc | 688 | ADC_CHANNEL_8 ((uint32_t) ADC_CHSELR_CHSEL8) |
| AnnaBridge | 171:3a7713b1edbc | 689 | ADC_CHANNEL_9 ((uint32_t) ADC_CHSELR_CHSEL9) |
| AnnaBridge | 171:3a7713b1edbc | 690 | ADC_CHANNEL_10 ((uint32_t) ADC_CHSELR_CHSEL10) |
| AnnaBridge | 171:3a7713b1edbc | 691 | ADC_CHANNEL_11 ((uint32_t) ADC_CHSELR_CHSEL11) |
| AnnaBridge | 171:3a7713b1edbc | 692 | ADC_CHANNEL_12 ((uint32_t) ADC_CHSELR_CHSEL12) |
| AnnaBridge | 171:3a7713b1edbc | 693 | ADC_CHANNEL_13 ((uint32_t) ADC_CHSELR_CHSEL13) |
| AnnaBridge | 171:3a7713b1edbc | 694 | ADC_CHANNEL_14 ((uint32_t) ADC_CHSELR_CHSEL14) |
| AnnaBridge | 171:3a7713b1edbc | 695 | ADC_CHANNEL_15 ((uint32_t) ADC_CHSELR_CHSEL15) |
| AnnaBridge | 171:3a7713b1edbc | 696 | ADC_CHANNEL_16 ((uint32_t) ADC_CHSELR_CHSEL16) |
| AnnaBridge | 171:3a7713b1edbc | 697 | ADC_CHANNEL_17 ((uint32_t) ADC_CHSELR_CHSEL17) |
| AnnaBridge | 171:3a7713b1edbc | 698 | ADC_CHANNEL_18 ((uint32_t) ADC_CHSELR_CHSEL18) |
| AnnaBridge | 171:3a7713b1edbc | 699 | */ |
| AnnaBridge | 171:3a7713b1edbc | 700 | #define ADC_CHSELR_CHANNEL(_CHANNEL_) \ |
| AnnaBridge | 171:3a7713b1edbc | 701 | ( 1U << (_CHANNEL_)) |
| AnnaBridge | 171:3a7713b1edbc | 702 | |
| AnnaBridge | 171:3a7713b1edbc | 703 | /** |
| AnnaBridge | 171:3a7713b1edbc | 704 | * @brief Set the ADC's sample time |
| AnnaBridge | 171:3a7713b1edbc | 705 | * @param _SAMPLETIME_ Sample time parameter. |
| AnnaBridge | 171:3a7713b1edbc | 706 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 707 | */ |
| AnnaBridge | 171:3a7713b1edbc | 708 | /* Note: ADC sampling time set using mask ADC_SMPR_SMP due to parameter */ |
| AnnaBridge | 171:3a7713b1edbc | 709 | /* "ADC_SAMPLETIME_1CYCLE_5" defined with a dummy bit (bit used to */ |
| AnnaBridge | 171:3a7713b1edbc | 710 | /* distinguish this parameter versus reset value 0x00000000, */ |
| AnnaBridge | 171:3a7713b1edbc | 711 | /* in the context of management of parameters "SamplingTimeCommon" */ |
| AnnaBridge | 171:3a7713b1edbc | 712 | /* and "SamplingTime" (obsolete)). */ |
| AnnaBridge | 171:3a7713b1edbc | 713 | #define ADC_SMPR_SET(_SAMPLETIME_) \ |
| AnnaBridge | 171:3a7713b1edbc | 714 | ((_SAMPLETIME_) & (ADC_SMPR_SMP)) |
| AnnaBridge | 171:3a7713b1edbc | 715 | |
| AnnaBridge | 171:3a7713b1edbc | 716 | /** |
| AnnaBridge | 171:3a7713b1edbc | 717 | * @brief Set the Analog Watchdog 1 channel. |
| AnnaBridge | 171:3a7713b1edbc | 718 | * @param _CHANNEL_ channel to be monitored by Analog Watchdog 1. |
| AnnaBridge | 171:3a7713b1edbc | 719 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 720 | */ |
| AnnaBridge | 171:3a7713b1edbc | 721 | #define ADC_CFGR_AWDCH(_CHANNEL_) \ |
| AnnaBridge | 171:3a7713b1edbc | 722 | ((_CHANNEL_) << 26U) |
| AnnaBridge | 171:3a7713b1edbc | 723 | |
| AnnaBridge | 171:3a7713b1edbc | 724 | /** |
| AnnaBridge | 171:3a7713b1edbc | 725 | * @brief Enable ADC discontinuous conversion mode for regular group |
| AnnaBridge | 171:3a7713b1edbc | 726 | * @param _REG_DISCONTINUOUS_MODE_ Regular discontinuous mode. |
| AnnaBridge | 171:3a7713b1edbc | 727 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 728 | */ |
| AnnaBridge | 171:3a7713b1edbc | 729 | #define ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) \ |
| AnnaBridge | 171:3a7713b1edbc | 730 | ((_REG_DISCONTINUOUS_MODE_) << 16U) |
| AnnaBridge | 171:3a7713b1edbc | 731 | |
| AnnaBridge | 171:3a7713b1edbc | 732 | /** |
| AnnaBridge | 171:3a7713b1edbc | 733 | * @brief Enable the ADC auto off mode. |
| AnnaBridge | 171:3a7713b1edbc | 734 | * @param _AUTOOFF_ Auto off bit enable or disable. |
| AnnaBridge | 171:3a7713b1edbc | 735 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 736 | */ |
| AnnaBridge | 171:3a7713b1edbc | 737 | #define ADC_CFGR1_AUTOOFF(_AUTOOFF_) \ |
| AnnaBridge | 171:3a7713b1edbc | 738 | ((_AUTOOFF_) << 15U) |
| AnnaBridge | 171:3a7713b1edbc | 739 | |
| AnnaBridge | 171:3a7713b1edbc | 740 | /** |
| AnnaBridge | 171:3a7713b1edbc | 741 | * @brief Enable the ADC auto delay mode. |
| AnnaBridge | 171:3a7713b1edbc | 742 | * @param _AUTOWAIT_ Auto delay bit enable or disable. |
| AnnaBridge | 171:3a7713b1edbc | 743 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 744 | */ |
| AnnaBridge | 171:3a7713b1edbc | 745 | #define ADC_CFGR1_AUTOWAIT(_AUTOWAIT_) \ |
| AnnaBridge | 171:3a7713b1edbc | 746 | ((_AUTOWAIT_) << 14U) |
| AnnaBridge | 171:3a7713b1edbc | 747 | |
| AnnaBridge | 171:3a7713b1edbc | 748 | /** |
| AnnaBridge | 171:3a7713b1edbc | 749 | * @brief Enable ADC continuous conversion mode. |
| AnnaBridge | 171:3a7713b1edbc | 750 | * @param _CONTINUOUS_MODE_ Continuous mode. |
| AnnaBridge | 171:3a7713b1edbc | 751 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 752 | */ |
| AnnaBridge | 171:3a7713b1edbc | 753 | #define ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_) \ |
| AnnaBridge | 171:3a7713b1edbc | 754 | ((_CONTINUOUS_MODE_) << 13U) |
| AnnaBridge | 171:3a7713b1edbc | 755 | |
| AnnaBridge | 171:3a7713b1edbc | 756 | /** |
| AnnaBridge | 171:3a7713b1edbc | 757 | * @brief Enable ADC overrun mode. |
| AnnaBridge | 171:3a7713b1edbc | 758 | * @param _OVERRUN_MODE_ Overrun mode. |
| AnnaBridge | 171:3a7713b1edbc | 759 | * @retval Overun bit setting to be programmed into CFGR register |
| AnnaBridge | 171:3a7713b1edbc | 760 | */ |
| AnnaBridge | 171:3a7713b1edbc | 761 | /* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant */ |
| AnnaBridge | 171:3a7713b1edbc | 762 | /* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it */ |
| AnnaBridge | 171:3a7713b1edbc | 763 | /* as the default case to be compliant with other STM32 devices. */ |
| AnnaBridge | 171:3a7713b1edbc | 764 | #define ADC_CFGR1_OVERRUN(_OVERRUN_MODE_) \ |
| AnnaBridge | 171:3a7713b1edbc | 765 | ( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED) \ |
| AnnaBridge | 171:3a7713b1edbc | 766 | )? (ADC_CFGR1_OVRMOD) : (0x00000000) \ |
| AnnaBridge | 171:3a7713b1edbc | 767 | ) |
| AnnaBridge | 171:3a7713b1edbc | 768 | |
| AnnaBridge | 171:3a7713b1edbc | 769 | /** |
| AnnaBridge | 171:3a7713b1edbc | 770 | * @brief Enable ADC scan mode to convert multiple ranks with sequencer. |
| AnnaBridge | 171:3a7713b1edbc | 771 | * @param _SCAN_MODE_ Scan conversion mode. |
| AnnaBridge | 171:3a7713b1edbc | 772 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 773 | */ |
| AnnaBridge | 171:3a7713b1edbc | 774 | /* Note: Scan mode set using this macro (instead of parameter direct set) */ |
| AnnaBridge | 171:3a7713b1edbc | 775 | /* due to different modes on other STM32 devices: to avoid any */ |
| AnnaBridge | 171:3a7713b1edbc | 776 | /* unwanted setting, the exact parameter corresponding to the device */ |
| AnnaBridge | 171:3a7713b1edbc | 777 | /* must be passed to this macro. */ |
| AnnaBridge | 171:3a7713b1edbc | 778 | #define ADC_SCANDIR(_SCAN_MODE_) \ |
| AnnaBridge | 171:3a7713b1edbc | 779 | ( ( (_SCAN_MODE_) == (ADC_SCAN_DIRECTION_BACKWARD) \ |
| AnnaBridge | 171:3a7713b1edbc | 780 | )? (ADC_CFGR1_SCANDIR) : (0x00000000) \ |
| AnnaBridge | 171:3a7713b1edbc | 781 | ) |
| AnnaBridge | 171:3a7713b1edbc | 782 | |
| AnnaBridge | 171:3a7713b1edbc | 783 | /** |
| AnnaBridge | 171:3a7713b1edbc | 784 | * @brief Enable the ADC DMA continuous request. |
| AnnaBridge | 171:3a7713b1edbc | 785 | * @param _DMACONTREQ_MODE_ DMA continuous request mode. |
| AnnaBridge | 171:3a7713b1edbc | 786 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 787 | */ |
| AnnaBridge | 171:3a7713b1edbc | 788 | #define ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_) \ |
| AnnaBridge | 171:3a7713b1edbc | 789 | ((_DMACONTREQ_MODE_) << 1U) |
| AnnaBridge | 171:3a7713b1edbc | 790 | |
| AnnaBridge | 171:3a7713b1edbc | 791 | /** |
| AnnaBridge | 171:3a7713b1edbc | 792 | * @brief Configure the analog watchdog high threshold into register TR. |
| AnnaBridge | 171:3a7713b1edbc | 793 | * @param _Threshold_ Threshold value |
| AnnaBridge | 171:3a7713b1edbc | 794 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 795 | */ |
| AnnaBridge | 171:3a7713b1edbc | 796 | #define ADC_TRX_HIGHTHRESHOLD(_Threshold_) \ |
| AnnaBridge | 171:3a7713b1edbc | 797 | ((_Threshold_) << 16U) |
| AnnaBridge | 171:3a7713b1edbc | 798 | |
| AnnaBridge | 171:3a7713b1edbc | 799 | /** |
| AnnaBridge | 171:3a7713b1edbc | 800 | * @brief Shift the AWD threshold in function of the selected ADC resolution. |
| AnnaBridge | 171:3a7713b1edbc | 801 | * Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. |
| AnnaBridge | 171:3a7713b1edbc | 802 | * If resolution 12 bits, no shift. |
| AnnaBridge | 171:3a7713b1edbc | 803 | * If resolution 10 bits, shift of 2 ranks on the left. |
| AnnaBridge | 171:3a7713b1edbc | 804 | * If resolution 8 bits, shift of 4 ranks on the left. |
| AnnaBridge | 171:3a7713b1edbc | 805 | * If resolution 6 bits, shift of 6 ranks on the left. |
| AnnaBridge | 171:3a7713b1edbc | 806 | * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)) |
| AnnaBridge | 171:3a7713b1edbc | 807 | * @param __HANDLE__ ADC handle |
| AnnaBridge | 171:3a7713b1edbc | 808 | * @param _Threshold_ Value to be shifted |
| AnnaBridge | 171:3a7713b1edbc | 809 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 810 | */ |
| AnnaBridge | 171:3a7713b1edbc | 811 | #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \ |
| AnnaBridge | 171:3a7713b1edbc | 812 | ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2)) |
| AnnaBridge | 171:3a7713b1edbc | 813 | |
| AnnaBridge | 171:3a7713b1edbc | 814 | |
| AnnaBridge | 171:3a7713b1edbc | 815 | #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) || \ |
| AnnaBridge | 171:3a7713b1edbc | 816 | ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ |
| AnnaBridge | 171:3a7713b1edbc | 817 | ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) ) |
| AnnaBridge | 171:3a7713b1edbc | 818 | |
| AnnaBridge | 171:3a7713b1edbc | 819 | #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \ |
| AnnaBridge | 171:3a7713b1edbc | 820 | ((RESOLUTION) == ADC_RESOLUTION_10B) || \ |
| AnnaBridge | 171:3a7713b1edbc | 821 | ((RESOLUTION) == ADC_RESOLUTION_8B) || \ |
| AnnaBridge | 171:3a7713b1edbc | 822 | ((RESOLUTION) == ADC_RESOLUTION_6B) ) |
| AnnaBridge | 171:3a7713b1edbc | 823 | |
| AnnaBridge | 171:3a7713b1edbc | 824 | #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ |
| AnnaBridge | 171:3a7713b1edbc | 825 | ((ALIGN) == ADC_DATAALIGN_LEFT) ) |
| AnnaBridge | 171:3a7713b1edbc | 826 | |
| AnnaBridge | 171:3a7713b1edbc | 827 | #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) || \ |
| AnnaBridge | 171:3a7713b1edbc | 828 | ((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD) ) |
| AnnaBridge | 171:3a7713b1edbc | 829 | |
| AnnaBridge | 171:3a7713b1edbc | 830 | #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 831 | ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ |
| AnnaBridge | 171:3a7713b1edbc | 832 | ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ |
| AnnaBridge | 171:3a7713b1edbc | 833 | ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) |
| AnnaBridge | 171:3a7713b1edbc | 834 | |
| AnnaBridge | 171:3a7713b1edbc | 835 | #define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \ |
| AnnaBridge | 171:3a7713b1edbc | 836 | ((EOC_SELECTION) == ADC_EOC_SEQ_CONV) ) |
| AnnaBridge | 171:3a7713b1edbc | 837 | |
| AnnaBridge | 171:3a7713b1edbc | 838 | #define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \ |
| AnnaBridge | 171:3a7713b1edbc | 839 | ((OVR) == ADC_OVR_DATA_OVERWRITTEN) ) |
| AnnaBridge | 171:3a7713b1edbc | 840 | |
| AnnaBridge | 171:3a7713b1edbc | 841 | #define IS_ADC_RANK(WATCHDOG) (((WATCHDOG) == ADC_RANK_CHANNEL_NUMBER) || \ |
| AnnaBridge | 171:3a7713b1edbc | 842 | ((WATCHDOG) == ADC_RANK_NONE) ) |
| AnnaBridge | 171:3a7713b1edbc | 843 | |
| AnnaBridge | 171:3a7713b1edbc | 844 | #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \ |
| AnnaBridge | 171:3a7713b1edbc | 845 | ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \ |
| AnnaBridge | 171:3a7713b1edbc | 846 | ((TIME) == ADC_SAMPLETIME_13CYCLES_5) || \ |
| AnnaBridge | 171:3a7713b1edbc | 847 | ((TIME) == ADC_SAMPLETIME_28CYCLES_5) || \ |
| AnnaBridge | 171:3a7713b1edbc | 848 | ((TIME) == ADC_SAMPLETIME_41CYCLES_5) || \ |
| AnnaBridge | 171:3a7713b1edbc | 849 | ((TIME) == ADC_SAMPLETIME_55CYCLES_5) || \ |
| AnnaBridge | 171:3a7713b1edbc | 850 | ((TIME) == ADC_SAMPLETIME_71CYCLES_5) || \ |
| AnnaBridge | 171:3a7713b1edbc | 851 | ((TIME) == ADC_SAMPLETIME_239CYCLES_5) ) |
| AnnaBridge | 171:3a7713b1edbc | 852 | |
| AnnaBridge | 171:3a7713b1edbc | 853 | #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 854 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ |
| AnnaBridge | 171:3a7713b1edbc | 855 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) ) |
| AnnaBridge | 171:3a7713b1edbc | 856 | |
| AnnaBridge | 171:3a7713b1edbc | 857 | #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \ |
| AnnaBridge | 171:3a7713b1edbc | 858 | ((EVENT) == ADC_OVR_EVENT) ) |
| AnnaBridge | 171:3a7713b1edbc | 859 | |
| AnnaBridge | 171:3a7713b1edbc | 860 | /** @defgroup ADC_range_verification ADC range verification |
| AnnaBridge | 171:3a7713b1edbc | 861 | * in function of ADC resolution selected (12, 10, 8 or 6 bits) |
| AnnaBridge | 171:3a7713b1edbc | 862 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 863 | */ |
| AnnaBridge | 171:3a7713b1edbc | 864 | #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \ |
| AnnaBridge | 171:3a7713b1edbc | 865 | ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= (0x0FFFU))) || \ |
| AnnaBridge | 171:3a7713b1edbc | 866 | (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= (0x03FFU))) || \ |
| AnnaBridge | 171:3a7713b1edbc | 867 | (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= (0x00FFU))) || \ |
| AnnaBridge | 171:3a7713b1edbc | 868 | (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= (0x003FU))) ) |
| AnnaBridge | 171:3a7713b1edbc | 869 | /** |
| AnnaBridge | 171:3a7713b1edbc | 870 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 871 | */ |
| AnnaBridge | 171:3a7713b1edbc | 872 | |
| AnnaBridge | 171:3a7713b1edbc | 873 | /** @defgroup ADC_regular_rank_verification ADC regular rank verification |
| AnnaBridge | 171:3a7713b1edbc | 874 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 875 | */ |
| AnnaBridge | 171:3a7713b1edbc | 876 | #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= (1U)) && ((RANK) <= (16U))) |
| AnnaBridge | 171:3a7713b1edbc | 877 | /** |
| AnnaBridge | 171:3a7713b1edbc | 878 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 879 | */ |
| AnnaBridge | 171:3a7713b1edbc | 880 | |
| AnnaBridge | 171:3a7713b1edbc | 881 | /** |
| AnnaBridge | 171:3a7713b1edbc | 882 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 883 | */ |
| AnnaBridge | 171:3a7713b1edbc | 884 | |
| AnnaBridge | 171:3a7713b1edbc | 885 | /* Include ADC HAL Extension module */ |
| AnnaBridge | 171:3a7713b1edbc | 886 | #include "stm32f0xx_hal_adc_ex.h" |
| AnnaBridge | 171:3a7713b1edbc | 887 | |
| AnnaBridge | 171:3a7713b1edbc | 888 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 889 | /** @addtogroup ADC_Exported_Functions |
| AnnaBridge | 171:3a7713b1edbc | 890 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 891 | */ |
| AnnaBridge | 171:3a7713b1edbc | 892 | |
| AnnaBridge | 171:3a7713b1edbc | 893 | /** @addtogroup ADC_Exported_Functions_Group1 |
| AnnaBridge | 171:3a7713b1edbc | 894 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 895 | */ |
| AnnaBridge | 171:3a7713b1edbc | 896 | |
| AnnaBridge | 171:3a7713b1edbc | 897 | |
| AnnaBridge | 171:3a7713b1edbc | 898 | /* Initialization and de-initialization functions **********************************/ |
| AnnaBridge | 171:3a7713b1edbc | 899 | HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); |
| AnnaBridge | 171:3a7713b1edbc | 900 | HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); |
| AnnaBridge | 171:3a7713b1edbc | 901 | void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); |
| AnnaBridge | 171:3a7713b1edbc | 902 | void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); |
| AnnaBridge | 171:3a7713b1edbc | 903 | /** |
| AnnaBridge | 171:3a7713b1edbc | 904 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 905 | */ |
| AnnaBridge | 171:3a7713b1edbc | 906 | |
| AnnaBridge | 171:3a7713b1edbc | 907 | /* IO operation functions *****************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 908 | |
| AnnaBridge | 171:3a7713b1edbc | 909 | /** @addtogroup ADC_Exported_Functions_Group2 |
| AnnaBridge | 171:3a7713b1edbc | 910 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 911 | */ |
| AnnaBridge | 171:3a7713b1edbc | 912 | |
| AnnaBridge | 171:3a7713b1edbc | 913 | |
| AnnaBridge | 171:3a7713b1edbc | 914 | /* Blocking mode: Polling */ |
| AnnaBridge | 171:3a7713b1edbc | 915 | HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); |
| AnnaBridge | 171:3a7713b1edbc | 916 | HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); |
| AnnaBridge | 171:3a7713b1edbc | 917 | HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); |
| AnnaBridge | 171:3a7713b1edbc | 918 | HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); |
| AnnaBridge | 171:3a7713b1edbc | 919 | |
| AnnaBridge | 171:3a7713b1edbc | 920 | /* Non-blocking mode: Interruption */ |
| AnnaBridge | 171:3a7713b1edbc | 921 | HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); |
| AnnaBridge | 171:3a7713b1edbc | 922 | HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); |
| AnnaBridge | 171:3a7713b1edbc | 923 | |
| AnnaBridge | 171:3a7713b1edbc | 924 | /* Non-blocking mode: DMA */ |
| AnnaBridge | 171:3a7713b1edbc | 925 | HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); |
| AnnaBridge | 171:3a7713b1edbc | 926 | HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); |
| AnnaBridge | 171:3a7713b1edbc | 927 | |
| AnnaBridge | 171:3a7713b1edbc | 928 | /* ADC retrieve conversion value intended to be used with polling or interruption */ |
| AnnaBridge | 171:3a7713b1edbc | 929 | uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); |
| AnnaBridge | 171:3a7713b1edbc | 930 | |
| AnnaBridge | 171:3a7713b1edbc | 931 | /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ |
| AnnaBridge | 171:3a7713b1edbc | 932 | void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); |
| AnnaBridge | 171:3a7713b1edbc | 933 | void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); |
| AnnaBridge | 171:3a7713b1edbc | 934 | void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); |
| AnnaBridge | 171:3a7713b1edbc | 935 | void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); |
| AnnaBridge | 171:3a7713b1edbc | 936 | void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); |
| AnnaBridge | 171:3a7713b1edbc | 937 | /** |
| AnnaBridge | 171:3a7713b1edbc | 938 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 939 | */ |
| AnnaBridge | 171:3a7713b1edbc | 940 | |
| AnnaBridge | 171:3a7713b1edbc | 941 | |
| AnnaBridge | 171:3a7713b1edbc | 942 | /* Peripheral Control functions ***********************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 943 | /** @addtogroup ADC_Exported_Functions_Group3 |
| AnnaBridge | 171:3a7713b1edbc | 944 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 945 | */ |
| AnnaBridge | 171:3a7713b1edbc | 946 | HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); |
| AnnaBridge | 171:3a7713b1edbc | 947 | HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); |
| AnnaBridge | 171:3a7713b1edbc | 948 | /** |
| AnnaBridge | 171:3a7713b1edbc | 949 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 950 | */ |
| AnnaBridge | 171:3a7713b1edbc | 951 | |
| AnnaBridge | 171:3a7713b1edbc | 952 | |
| AnnaBridge | 171:3a7713b1edbc | 953 | /* Peripheral State functions *************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 954 | /** @addtogroup ADC_Exported_Functions_Group4 |
| AnnaBridge | 171:3a7713b1edbc | 955 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 956 | */ |
| AnnaBridge | 171:3a7713b1edbc | 957 | uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); |
| AnnaBridge | 171:3a7713b1edbc | 958 | uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); |
| AnnaBridge | 171:3a7713b1edbc | 959 | /** |
| AnnaBridge | 171:3a7713b1edbc | 960 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 961 | */ |
| AnnaBridge | 171:3a7713b1edbc | 962 | |
| AnnaBridge | 171:3a7713b1edbc | 963 | |
| AnnaBridge | 171:3a7713b1edbc | 964 | /** |
| AnnaBridge | 171:3a7713b1edbc | 965 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 966 | */ |
| AnnaBridge | 171:3a7713b1edbc | 967 | |
| AnnaBridge | 171:3a7713b1edbc | 968 | |
| AnnaBridge | 171:3a7713b1edbc | 969 | /** |
| AnnaBridge | 171:3a7713b1edbc | 970 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 971 | */ |
| AnnaBridge | 171:3a7713b1edbc | 972 | |
| AnnaBridge | 171:3a7713b1edbc | 973 | /** |
| AnnaBridge | 171:3a7713b1edbc | 974 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 975 | */ |
| AnnaBridge | 171:3a7713b1edbc | 976 | |
| AnnaBridge | 171:3a7713b1edbc | 977 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 978 | } |
| AnnaBridge | 171:3a7713b1edbc | 979 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 980 | |
| AnnaBridge | 171:3a7713b1edbc | 981 | |
| AnnaBridge | 171:3a7713b1edbc | 982 | #endif /* __STM32F0xx_HAL_ADC_H */ |
| AnnaBridge | 171:3a7713b1edbc | 983 | |
| AnnaBridge | 171:3a7713b1edbc | 984 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
| AnnaBridge | 171:3a7713b1edbc | 985 |
