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TARGET_MOTE_L152RC/TOOLCHAIN_IAR/stm32l1xx_ll_sdmmc.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /** |
| AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32l1xx_ll_sdmmc.h |
| AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
| AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of SDMMC HAL module. |
| AnnaBridge | 171:3a7713b1edbc | 6 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 7 | * @attention |
| AnnaBridge | 171:3a7713b1edbc | 8 | * |
| AnnaBridge | 171:3a7713b1edbc | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 171:3a7713b1edbc | 10 | * |
| AnnaBridge | 171:3a7713b1edbc | 11 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 171:3a7713b1edbc | 12 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 171:3a7713b1edbc | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 14 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 171:3a7713b1edbc | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 171:3a7713b1edbc | 17 | * and/or other materials provided with the distribution. |
| AnnaBridge | 171:3a7713b1edbc | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 171:3a7713b1edbc | 19 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 171:3a7713b1edbc | 20 | * without specific prior written permission. |
| AnnaBridge | 171:3a7713b1edbc | 21 | * |
| AnnaBridge | 171:3a7713b1edbc | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 171:3a7713b1edbc | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 171:3a7713b1edbc | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 171:3a7713b1edbc | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 171:3a7713b1edbc | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 171:3a7713b1edbc | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 171:3a7713b1edbc | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 171:3a7713b1edbc | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 171:3a7713b1edbc | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 171:3a7713b1edbc | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 171:3a7713b1edbc | 32 | * |
| AnnaBridge | 171:3a7713b1edbc | 33 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 34 | */ |
| AnnaBridge | 171:3a7713b1edbc | 35 | |
| AnnaBridge | 171:3a7713b1edbc | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 37 | #ifndef __STM32L1xx_LL_SD_H |
| AnnaBridge | 171:3a7713b1edbc | 38 | #define __STM32L1xx_LL_SD_H |
| AnnaBridge | 171:3a7713b1edbc | 39 | |
| AnnaBridge | 171:3a7713b1edbc | 40 | #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) |
| AnnaBridge | 171:3a7713b1edbc | 41 | |
| AnnaBridge | 171:3a7713b1edbc | 42 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 43 | extern "C" { |
| AnnaBridge | 171:3a7713b1edbc | 44 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 45 | |
| AnnaBridge | 171:3a7713b1edbc | 46 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 47 | #include "stm32l1xx_hal_def.h" |
| AnnaBridge | 171:3a7713b1edbc | 48 | |
| AnnaBridge | 171:3a7713b1edbc | 49 | /** @addtogroup STM32L1xx_HAL_Driver |
| AnnaBridge | 171:3a7713b1edbc | 50 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 51 | */ |
| AnnaBridge | 171:3a7713b1edbc | 52 | |
| AnnaBridge | 171:3a7713b1edbc | 53 | /** @addtogroup SDMMC_LL |
| AnnaBridge | 171:3a7713b1edbc | 54 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 55 | */ |
| AnnaBridge | 171:3a7713b1edbc | 56 | |
| AnnaBridge | 171:3a7713b1edbc | 57 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 58 | /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types |
| AnnaBridge | 171:3a7713b1edbc | 59 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 60 | */ |
| AnnaBridge | 171:3a7713b1edbc | 61 | |
| AnnaBridge | 171:3a7713b1edbc | 62 | /** |
| AnnaBridge | 171:3a7713b1edbc | 63 | * @brief SDMMC Configuration Structure definition |
| AnnaBridge | 171:3a7713b1edbc | 64 | */ |
| AnnaBridge | 171:3a7713b1edbc | 65 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 66 | { |
| AnnaBridge | 171:3a7713b1edbc | 67 | uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. |
| AnnaBridge | 171:3a7713b1edbc | 68 | This parameter can be a value of @ref SDIO_Clock_Edge */ |
| AnnaBridge | 171:3a7713b1edbc | 69 | |
| AnnaBridge | 171:3a7713b1edbc | 70 | uint32_t ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is |
| AnnaBridge | 171:3a7713b1edbc | 71 | enabled or disabled. |
| AnnaBridge | 171:3a7713b1edbc | 72 | This parameter can be a value of @ref SDIO_Clock_Bypass */ |
| AnnaBridge | 171:3a7713b1edbc | 73 | |
| AnnaBridge | 171:3a7713b1edbc | 74 | uint32_t ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or |
| AnnaBridge | 171:3a7713b1edbc | 75 | disabled when the bus is idle. |
| AnnaBridge | 171:3a7713b1edbc | 76 | This parameter can be a value of @ref SDIO_Clock_Power_Save */ |
| AnnaBridge | 171:3a7713b1edbc | 77 | |
| AnnaBridge | 171:3a7713b1edbc | 78 | uint32_t BusWide; /*!< Specifies the SDIO bus width. |
| AnnaBridge | 171:3a7713b1edbc | 79 | This parameter can be a value of @ref SDIO_Bus_Wide */ |
| AnnaBridge | 171:3a7713b1edbc | 80 | |
| AnnaBridge | 171:3a7713b1edbc | 81 | uint32_t HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. |
| AnnaBridge | 171:3a7713b1edbc | 82 | This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ |
| AnnaBridge | 171:3a7713b1edbc | 83 | |
| AnnaBridge | 171:3a7713b1edbc | 84 | uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. |
| AnnaBridge | 171:3a7713b1edbc | 85 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
| AnnaBridge | 171:3a7713b1edbc | 86 | |
| AnnaBridge | 171:3a7713b1edbc | 87 | }SDIO_InitTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 88 | |
| AnnaBridge | 171:3a7713b1edbc | 89 | |
| AnnaBridge | 171:3a7713b1edbc | 90 | /** |
| AnnaBridge | 171:3a7713b1edbc | 91 | * @brief SDIO Command Control structure |
| AnnaBridge | 171:3a7713b1edbc | 92 | */ |
| AnnaBridge | 171:3a7713b1edbc | 93 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 94 | { |
| AnnaBridge | 171:3a7713b1edbc | 95 | uint32_t Argument; /*!< Specifies the SDIO command argument which is sent |
| AnnaBridge | 171:3a7713b1edbc | 96 | to a card as part of a command message. If a command |
| AnnaBridge | 171:3a7713b1edbc | 97 | contains an argument, it must be loaded into this register |
| AnnaBridge | 171:3a7713b1edbc | 98 | before writing the command to the command register. */ |
| AnnaBridge | 171:3a7713b1edbc | 99 | |
| AnnaBridge | 171:3a7713b1edbc | 100 | uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be Min_Data = 0 and |
| AnnaBridge | 171:3a7713b1edbc | 101 | Max_Data = 64 */ |
| AnnaBridge | 171:3a7713b1edbc | 102 | |
| AnnaBridge | 171:3a7713b1edbc | 103 | uint32_t Response; /*!< Specifies the SDIO response type. |
| AnnaBridge | 171:3a7713b1edbc | 104 | This parameter can be a value of @ref SDIO_Response_Type */ |
| AnnaBridge | 171:3a7713b1edbc | 105 | |
| AnnaBridge | 171:3a7713b1edbc | 106 | uint32_t WaitForInterrupt; /*!< Specifies whether SDIO wait for interrupt request is |
| AnnaBridge | 171:3a7713b1edbc | 107 | enabled or disabled. |
| AnnaBridge | 171:3a7713b1edbc | 108 | This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ |
| AnnaBridge | 171:3a7713b1edbc | 109 | |
| AnnaBridge | 171:3a7713b1edbc | 110 | uint32_t CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) |
| AnnaBridge | 171:3a7713b1edbc | 111 | is enabled or disabled. |
| AnnaBridge | 171:3a7713b1edbc | 112 | This parameter can be a value of @ref SDIO_CPSM_State */ |
| AnnaBridge | 171:3a7713b1edbc | 113 | }SDIO_CmdInitTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 114 | |
| AnnaBridge | 171:3a7713b1edbc | 115 | |
| AnnaBridge | 171:3a7713b1edbc | 116 | /** |
| AnnaBridge | 171:3a7713b1edbc | 117 | * @brief SDIO Data Control structure |
| AnnaBridge | 171:3a7713b1edbc | 118 | */ |
| AnnaBridge | 171:3a7713b1edbc | 119 | typedef struct |
| AnnaBridge | 171:3a7713b1edbc | 120 | { |
| AnnaBridge | 171:3a7713b1edbc | 121 | uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ |
| AnnaBridge | 171:3a7713b1edbc | 122 | |
| AnnaBridge | 171:3a7713b1edbc | 123 | uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */ |
| AnnaBridge | 171:3a7713b1edbc | 124 | |
| AnnaBridge | 171:3a7713b1edbc | 125 | uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer. |
| AnnaBridge | 171:3a7713b1edbc | 126 | This parameter can be a value of @ref SDIO_Data_Block_Size */ |
| AnnaBridge | 171:3a7713b1edbc | 127 | |
| AnnaBridge | 171:3a7713b1edbc | 128 | uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer |
| AnnaBridge | 171:3a7713b1edbc | 129 | is a read or write. |
| AnnaBridge | 171:3a7713b1edbc | 130 | This parameter can be a value of @ref SDIO_Transfer_Direction */ |
| AnnaBridge | 171:3a7713b1edbc | 131 | |
| AnnaBridge | 171:3a7713b1edbc | 132 | uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. |
| AnnaBridge | 171:3a7713b1edbc | 133 | This parameter can be a value of @ref SDIO_Transfer_Type */ |
| AnnaBridge | 171:3a7713b1edbc | 134 | |
| AnnaBridge | 171:3a7713b1edbc | 135 | uint32_t DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) |
| AnnaBridge | 171:3a7713b1edbc | 136 | is enabled or disabled. |
| AnnaBridge | 171:3a7713b1edbc | 137 | This parameter can be a value of @ref SDIO_DPSM_State */ |
| AnnaBridge | 171:3a7713b1edbc | 138 | }SDIO_DataInitTypeDef; |
| AnnaBridge | 171:3a7713b1edbc | 139 | |
| AnnaBridge | 171:3a7713b1edbc | 140 | /** |
| AnnaBridge | 171:3a7713b1edbc | 141 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 142 | */ |
| AnnaBridge | 171:3a7713b1edbc | 143 | |
| AnnaBridge | 171:3a7713b1edbc | 144 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 145 | /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants |
| AnnaBridge | 171:3a7713b1edbc | 146 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 147 | */ |
| AnnaBridge | 171:3a7713b1edbc | 148 | |
| AnnaBridge | 171:3a7713b1edbc | 149 | /** @defgroup SDIO_Clock_Edge Clock Edge |
| AnnaBridge | 171:3a7713b1edbc | 150 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 151 | */ |
| AnnaBridge | 171:3a7713b1edbc | 152 | #define SDIO_CLOCK_EDGE_RISING (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 153 | #define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE |
| AnnaBridge | 171:3a7713b1edbc | 154 | |
| AnnaBridge | 171:3a7713b1edbc | 155 | #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \ |
| AnnaBridge | 171:3a7713b1edbc | 156 | ((EDGE) == SDIO_CLOCK_EDGE_FALLING)) |
| AnnaBridge | 171:3a7713b1edbc | 157 | /** |
| AnnaBridge | 171:3a7713b1edbc | 158 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 159 | */ |
| AnnaBridge | 171:3a7713b1edbc | 160 | |
| AnnaBridge | 171:3a7713b1edbc | 161 | /** @defgroup SDIO_Clock_Bypass Clock Bypass |
| AnnaBridge | 171:3a7713b1edbc | 162 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 163 | */ |
| AnnaBridge | 171:3a7713b1edbc | 164 | #define SDIO_CLOCK_BYPASS_DISABLE (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 165 | #define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS |
| AnnaBridge | 171:3a7713b1edbc | 166 | |
| AnnaBridge | 171:3a7713b1edbc | 167 | #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 168 | ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE)) |
| AnnaBridge | 171:3a7713b1edbc | 169 | /** |
| AnnaBridge | 171:3a7713b1edbc | 170 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 171 | */ |
| AnnaBridge | 171:3a7713b1edbc | 172 | |
| AnnaBridge | 171:3a7713b1edbc | 173 | /** @defgroup SDIO_Clock_Power_Save Clock Power Saving |
| AnnaBridge | 171:3a7713b1edbc | 174 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 175 | */ |
| AnnaBridge | 171:3a7713b1edbc | 176 | #define SDIO_CLOCK_POWER_SAVE_DISABLE (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 177 | #define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV |
| AnnaBridge | 171:3a7713b1edbc | 178 | |
| AnnaBridge | 171:3a7713b1edbc | 179 | #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 180 | ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE)) |
| AnnaBridge | 171:3a7713b1edbc | 181 | /** |
| AnnaBridge | 171:3a7713b1edbc | 182 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 183 | */ |
| AnnaBridge | 171:3a7713b1edbc | 184 | |
| AnnaBridge | 171:3a7713b1edbc | 185 | /** @defgroup SDIO_Bus_Wide Bus Width |
| AnnaBridge | 171:3a7713b1edbc | 186 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 187 | */ |
| AnnaBridge | 171:3a7713b1edbc | 188 | #define SDIO_BUS_WIDE_1B (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 189 | #define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0 |
| AnnaBridge | 171:3a7713b1edbc | 190 | #define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1 |
| AnnaBridge | 171:3a7713b1edbc | 191 | |
| AnnaBridge | 171:3a7713b1edbc | 192 | #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \ |
| AnnaBridge | 171:3a7713b1edbc | 193 | ((WIDE) == SDIO_BUS_WIDE_4B) || \ |
| AnnaBridge | 171:3a7713b1edbc | 194 | ((WIDE) == SDIO_BUS_WIDE_8B)) |
| AnnaBridge | 171:3a7713b1edbc | 195 | /** |
| AnnaBridge | 171:3a7713b1edbc | 196 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 197 | */ |
| AnnaBridge | 171:3a7713b1edbc | 198 | |
| AnnaBridge | 171:3a7713b1edbc | 199 | /** @defgroup SDIO_Hardware_Flow_Control Hardware Flow Control |
| AnnaBridge | 171:3a7713b1edbc | 200 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 201 | */ |
| AnnaBridge | 171:3a7713b1edbc | 202 | #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 203 | #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN |
| AnnaBridge | 171:3a7713b1edbc | 204 | |
| AnnaBridge | 171:3a7713b1edbc | 205 | #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 206 | ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE)) |
| AnnaBridge | 171:3a7713b1edbc | 207 | /** |
| AnnaBridge | 171:3a7713b1edbc | 208 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 209 | */ |
| AnnaBridge | 171:3a7713b1edbc | 210 | |
| AnnaBridge | 171:3a7713b1edbc | 211 | /** @defgroup SDIO_Clock_Division Clock Division |
| AnnaBridge | 171:3a7713b1edbc | 212 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 213 | */ |
| AnnaBridge | 171:3a7713b1edbc | 214 | #define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFF) |
| AnnaBridge | 171:3a7713b1edbc | 215 | /** |
| AnnaBridge | 171:3a7713b1edbc | 216 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 217 | */ |
| AnnaBridge | 171:3a7713b1edbc | 218 | |
| AnnaBridge | 171:3a7713b1edbc | 219 | /** @defgroup SDIO_Command_Index Command Index |
| AnnaBridge | 171:3a7713b1edbc | 220 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 221 | */ |
| AnnaBridge | 171:3a7713b1edbc | 222 | #define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) |
| AnnaBridge | 171:3a7713b1edbc | 223 | /** |
| AnnaBridge | 171:3a7713b1edbc | 224 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 225 | */ |
| AnnaBridge | 171:3a7713b1edbc | 226 | |
| AnnaBridge | 171:3a7713b1edbc | 227 | /** @defgroup SDIO_Response_Type Response Type |
| AnnaBridge | 171:3a7713b1edbc | 228 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 229 | */ |
| AnnaBridge | 171:3a7713b1edbc | 230 | #define SDIO_RESPONSE_NO (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 231 | #define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0 |
| AnnaBridge | 171:3a7713b1edbc | 232 | #define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP |
| AnnaBridge | 171:3a7713b1edbc | 233 | |
| AnnaBridge | 171:3a7713b1edbc | 234 | #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \ |
| AnnaBridge | 171:3a7713b1edbc | 235 | ((RESPONSE) == SDIO_RESPONSE_SHORT) || \ |
| AnnaBridge | 171:3a7713b1edbc | 236 | ((RESPONSE) == SDIO_RESPONSE_LONG)) |
| AnnaBridge | 171:3a7713b1edbc | 237 | /** |
| AnnaBridge | 171:3a7713b1edbc | 238 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 239 | */ |
| AnnaBridge | 171:3a7713b1edbc | 240 | |
| AnnaBridge | 171:3a7713b1edbc | 241 | /** @defgroup SDIO_Wait_Interrupt_State Wait Interrupt |
| AnnaBridge | 171:3a7713b1edbc | 242 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 243 | */ |
| AnnaBridge | 171:3a7713b1edbc | 244 | #define SDIO_WAIT_NO (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 245 | #define SDIO_WAIT_IT SDIO_CMD_WAITINT |
| AnnaBridge | 171:3a7713b1edbc | 246 | #define SDIO_WAIT_PEND SDIO_CMD_WAITPEND |
| AnnaBridge | 171:3a7713b1edbc | 247 | |
| AnnaBridge | 171:3a7713b1edbc | 248 | #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \ |
| AnnaBridge | 171:3a7713b1edbc | 249 | ((WAIT) == SDIO_WAIT_IT) || \ |
| AnnaBridge | 171:3a7713b1edbc | 250 | ((WAIT) == SDIO_WAIT_PEND)) |
| AnnaBridge | 171:3a7713b1edbc | 251 | /** |
| AnnaBridge | 171:3a7713b1edbc | 252 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 253 | */ |
| AnnaBridge | 171:3a7713b1edbc | 254 | |
| AnnaBridge | 171:3a7713b1edbc | 255 | /** @defgroup SDIO_CPSM_State CPSM State |
| AnnaBridge | 171:3a7713b1edbc | 256 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 257 | */ |
| AnnaBridge | 171:3a7713b1edbc | 258 | #define SDIO_CPSM_DISABLE (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 259 | #define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN |
| AnnaBridge | 171:3a7713b1edbc | 260 | |
| AnnaBridge | 171:3a7713b1edbc | 261 | #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \ |
| AnnaBridge | 171:3a7713b1edbc | 262 | ((CPSM) == SDIO_CPSM_ENABLE)) |
| AnnaBridge | 171:3a7713b1edbc | 263 | /** |
| AnnaBridge | 171:3a7713b1edbc | 264 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 265 | */ |
| AnnaBridge | 171:3a7713b1edbc | 266 | |
| AnnaBridge | 171:3a7713b1edbc | 267 | /** @defgroup SDIO_Response_Registers Response Register |
| AnnaBridge | 171:3a7713b1edbc | 268 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 269 | */ |
| AnnaBridge | 171:3a7713b1edbc | 270 | #define SDIO_RESP1 (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 271 | #define SDIO_RESP2 (0x00000004U) |
| AnnaBridge | 171:3a7713b1edbc | 272 | #define SDIO_RESP3 (0x00000008U) |
| AnnaBridge | 171:3a7713b1edbc | 273 | #define SDIO_RESP4 (0x0000000CU) |
| AnnaBridge | 171:3a7713b1edbc | 274 | |
| AnnaBridge | 171:3a7713b1edbc | 275 | #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \ |
| AnnaBridge | 171:3a7713b1edbc | 276 | ((RESP) == SDIO_RESP2) || \ |
| AnnaBridge | 171:3a7713b1edbc | 277 | ((RESP) == SDIO_RESP3) || \ |
| AnnaBridge | 171:3a7713b1edbc | 278 | ((RESP) == SDIO_RESP4)) |
| AnnaBridge | 171:3a7713b1edbc | 279 | /** |
| AnnaBridge | 171:3a7713b1edbc | 280 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 281 | */ |
| AnnaBridge | 171:3a7713b1edbc | 282 | |
| AnnaBridge | 171:3a7713b1edbc | 283 | /** @defgroup SDIO_Data_Length Data Lenght |
| AnnaBridge | 171:3a7713b1edbc | 284 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 285 | */ |
| AnnaBridge | 171:3a7713b1edbc | 286 | #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) |
| AnnaBridge | 171:3a7713b1edbc | 287 | /** |
| AnnaBridge | 171:3a7713b1edbc | 288 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 289 | */ |
| AnnaBridge | 171:3a7713b1edbc | 290 | |
| AnnaBridge | 171:3a7713b1edbc | 291 | /** @defgroup SDIO_Data_Block_Size Data Block Size |
| AnnaBridge | 171:3a7713b1edbc | 292 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 293 | */ |
| AnnaBridge | 171:3a7713b1edbc | 294 | #define SDIO_DATABLOCK_SIZE_1B (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 295 | #define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0 |
| AnnaBridge | 171:3a7713b1edbc | 296 | #define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1 |
| AnnaBridge | 171:3a7713b1edbc | 297 | #define SDIO_DATABLOCK_SIZE_8B (0x00000030U) |
| AnnaBridge | 171:3a7713b1edbc | 298 | #define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2 |
| AnnaBridge | 171:3a7713b1edbc | 299 | #define SDIO_DATABLOCK_SIZE_32B (0x00000050U) |
| AnnaBridge | 171:3a7713b1edbc | 300 | #define SDIO_DATABLOCK_SIZE_64B (0x00000060U) |
| AnnaBridge | 171:3a7713b1edbc | 301 | #define SDIO_DATABLOCK_SIZE_128B (0x00000070U) |
| AnnaBridge | 171:3a7713b1edbc | 302 | #define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3 |
| AnnaBridge | 171:3a7713b1edbc | 303 | #define SDIO_DATABLOCK_SIZE_512B (0x00000090U) |
| AnnaBridge | 171:3a7713b1edbc | 304 | #define SDIO_DATABLOCK_SIZE_1024B (0x000000A0U) |
| AnnaBridge | 171:3a7713b1edbc | 305 | #define SDIO_DATABLOCK_SIZE_2048B (0x000000B0U) |
| AnnaBridge | 171:3a7713b1edbc | 306 | #define SDIO_DATABLOCK_SIZE_4096B (0x000000C0U) |
| AnnaBridge | 171:3a7713b1edbc | 307 | #define SDIO_DATABLOCK_SIZE_8192B (0x000000D0U) |
| AnnaBridge | 171:3a7713b1edbc | 308 | #define SDIO_DATABLOCK_SIZE_16384B (0x000000E0U) |
| AnnaBridge | 171:3a7713b1edbc | 309 | |
| AnnaBridge | 171:3a7713b1edbc | 310 | #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \ |
| AnnaBridge | 171:3a7713b1edbc | 311 | ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \ |
| AnnaBridge | 171:3a7713b1edbc | 312 | ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \ |
| AnnaBridge | 171:3a7713b1edbc | 313 | ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \ |
| AnnaBridge | 171:3a7713b1edbc | 314 | ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \ |
| AnnaBridge | 171:3a7713b1edbc | 315 | ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \ |
| AnnaBridge | 171:3a7713b1edbc | 316 | ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \ |
| AnnaBridge | 171:3a7713b1edbc | 317 | ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \ |
| AnnaBridge | 171:3a7713b1edbc | 318 | ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \ |
| AnnaBridge | 171:3a7713b1edbc | 319 | ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \ |
| AnnaBridge | 171:3a7713b1edbc | 320 | ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \ |
| AnnaBridge | 171:3a7713b1edbc | 321 | ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \ |
| AnnaBridge | 171:3a7713b1edbc | 322 | ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \ |
| AnnaBridge | 171:3a7713b1edbc | 323 | ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \ |
| AnnaBridge | 171:3a7713b1edbc | 324 | ((SIZE) == SDIO_DATABLOCK_SIZE_16384B)) |
| AnnaBridge | 171:3a7713b1edbc | 325 | /** |
| AnnaBridge | 171:3a7713b1edbc | 326 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 327 | */ |
| AnnaBridge | 171:3a7713b1edbc | 328 | |
| AnnaBridge | 171:3a7713b1edbc | 329 | /** @defgroup SDIO_Transfer_Direction Transfer Direction |
| AnnaBridge | 171:3a7713b1edbc | 330 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 331 | */ |
| AnnaBridge | 171:3a7713b1edbc | 332 | #define SDIO_TRANSFER_DIR_TO_CARD (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 333 | #define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR |
| AnnaBridge | 171:3a7713b1edbc | 334 | |
| AnnaBridge | 171:3a7713b1edbc | 335 | #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \ |
| AnnaBridge | 171:3a7713b1edbc | 336 | ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO)) |
| AnnaBridge | 171:3a7713b1edbc | 337 | /** |
| AnnaBridge | 171:3a7713b1edbc | 338 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 339 | */ |
| AnnaBridge | 171:3a7713b1edbc | 340 | |
| AnnaBridge | 171:3a7713b1edbc | 341 | /** @defgroup SDIO_Transfer_Type Transfer Type |
| AnnaBridge | 171:3a7713b1edbc | 342 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 343 | */ |
| AnnaBridge | 171:3a7713b1edbc | 344 | #define SDIO_TRANSFER_MODE_BLOCK (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 345 | #define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE |
| AnnaBridge | 171:3a7713b1edbc | 346 | |
| AnnaBridge | 171:3a7713b1edbc | 347 | #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \ |
| AnnaBridge | 171:3a7713b1edbc | 348 | ((MODE) == SDIO_TRANSFER_MODE_STREAM)) |
| AnnaBridge | 171:3a7713b1edbc | 349 | /** |
| AnnaBridge | 171:3a7713b1edbc | 350 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 351 | */ |
| AnnaBridge | 171:3a7713b1edbc | 352 | |
| AnnaBridge | 171:3a7713b1edbc | 353 | /** @defgroup SDIO_DPSM_State DPSM State |
| AnnaBridge | 171:3a7713b1edbc | 354 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 355 | */ |
| AnnaBridge | 171:3a7713b1edbc | 356 | #define SDIO_DPSM_DISABLE (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 357 | #define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN |
| AnnaBridge | 171:3a7713b1edbc | 358 | |
| AnnaBridge | 171:3a7713b1edbc | 359 | #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\ |
| AnnaBridge | 171:3a7713b1edbc | 360 | ((DPSM) == SDIO_DPSM_ENABLE)) |
| AnnaBridge | 171:3a7713b1edbc | 361 | /** |
| AnnaBridge | 171:3a7713b1edbc | 362 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 363 | */ |
| AnnaBridge | 171:3a7713b1edbc | 364 | |
| AnnaBridge | 171:3a7713b1edbc | 365 | /** @defgroup SDIO_Read_Wait_Mode Read Wait Mode |
| AnnaBridge | 171:3a7713b1edbc | 366 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 367 | */ |
| AnnaBridge | 171:3a7713b1edbc | 368 | #define SDIO_READ_WAIT_MODE_DATA2 (0x00000000U) |
| AnnaBridge | 171:3a7713b1edbc | 369 | #define SDIO_READ_WAIT_MODE_CLK (0x00000001U) |
| AnnaBridge | 171:3a7713b1edbc | 370 | |
| AnnaBridge | 171:3a7713b1edbc | 371 | #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \ |
| AnnaBridge | 171:3a7713b1edbc | 372 | ((MODE) == SDIO_READ_WAIT_MODE_DATA2)) |
| AnnaBridge | 171:3a7713b1edbc | 373 | /** |
| AnnaBridge | 171:3a7713b1edbc | 374 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 375 | */ |
| AnnaBridge | 171:3a7713b1edbc | 376 | |
| AnnaBridge | 171:3a7713b1edbc | 377 | /** @defgroup SDIO_Interrupt_sources Interrupt Sources |
| AnnaBridge | 171:3a7713b1edbc | 378 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 379 | */ |
| AnnaBridge | 171:3a7713b1edbc | 380 | #define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL |
| AnnaBridge | 171:3a7713b1edbc | 381 | #define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL |
| AnnaBridge | 171:3a7713b1edbc | 382 | #define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT |
| AnnaBridge | 171:3a7713b1edbc | 383 | #define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT |
| AnnaBridge | 171:3a7713b1edbc | 384 | #define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR |
| AnnaBridge | 171:3a7713b1edbc | 385 | #define SDIO_IT_RXOVERR SDIO_STA_RXOVERR |
| AnnaBridge | 171:3a7713b1edbc | 386 | #define SDIO_IT_CMDREND SDIO_STA_CMDREND |
| AnnaBridge | 171:3a7713b1edbc | 387 | #define SDIO_IT_CMDSENT SDIO_STA_CMDSENT |
| AnnaBridge | 171:3a7713b1edbc | 388 | #define SDIO_IT_DATAEND SDIO_STA_DATAEND |
| AnnaBridge | 171:3a7713b1edbc | 389 | #define SDIO_IT_STBITERR SDIO_STA_STBITERR |
| AnnaBridge | 171:3a7713b1edbc | 390 | #define SDIO_IT_DBCKEND SDIO_STA_DBCKEND |
| AnnaBridge | 171:3a7713b1edbc | 391 | #define SDIO_IT_CMDACT SDIO_STA_CMDACT |
| AnnaBridge | 171:3a7713b1edbc | 392 | #define SDIO_IT_TXACT SDIO_STA_TXACT |
| AnnaBridge | 171:3a7713b1edbc | 393 | #define SDIO_IT_RXACT SDIO_STA_RXACT |
| AnnaBridge | 171:3a7713b1edbc | 394 | #define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE |
| AnnaBridge | 171:3a7713b1edbc | 395 | #define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF |
| AnnaBridge | 171:3a7713b1edbc | 396 | #define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF |
| AnnaBridge | 171:3a7713b1edbc | 397 | #define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF |
| AnnaBridge | 171:3a7713b1edbc | 398 | #define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE |
| AnnaBridge | 171:3a7713b1edbc | 399 | #define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE |
| AnnaBridge | 171:3a7713b1edbc | 400 | #define SDIO_IT_TXDAVL SDIO_STA_TXDAVL |
| AnnaBridge | 171:3a7713b1edbc | 401 | #define SDIO_IT_RXDAVL SDIO_STA_RXDAVL |
| AnnaBridge | 171:3a7713b1edbc | 402 | #define SDIO_IT_SDIOIT SDIO_STA_SDIOIT |
| AnnaBridge | 171:3a7713b1edbc | 403 | #define SDIO_IT_CEATAEND SDIO_STA_CEATAEND |
| AnnaBridge | 171:3a7713b1edbc | 404 | /** |
| AnnaBridge | 171:3a7713b1edbc | 405 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 406 | */ |
| AnnaBridge | 171:3a7713b1edbc | 407 | |
| AnnaBridge | 171:3a7713b1edbc | 408 | /** @defgroup SDIO_Flags Flags |
| AnnaBridge | 171:3a7713b1edbc | 409 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 410 | */ |
| AnnaBridge | 171:3a7713b1edbc | 411 | #define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL |
| AnnaBridge | 171:3a7713b1edbc | 412 | #define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL |
| AnnaBridge | 171:3a7713b1edbc | 413 | #define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT |
| AnnaBridge | 171:3a7713b1edbc | 414 | #define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT |
| AnnaBridge | 171:3a7713b1edbc | 415 | #define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR |
| AnnaBridge | 171:3a7713b1edbc | 416 | #define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR |
| AnnaBridge | 171:3a7713b1edbc | 417 | #define SDIO_FLAG_CMDREND SDIO_STA_CMDREND |
| AnnaBridge | 171:3a7713b1edbc | 418 | #define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT |
| AnnaBridge | 171:3a7713b1edbc | 419 | #define SDIO_FLAG_DATAEND SDIO_STA_DATAEND |
| AnnaBridge | 171:3a7713b1edbc | 420 | #define SDIO_FLAG_STBITERR SDIO_STA_STBITERR |
| AnnaBridge | 171:3a7713b1edbc | 421 | #define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND |
| AnnaBridge | 171:3a7713b1edbc | 422 | #define SDIO_FLAG_CMDACT SDIO_STA_CMDACT |
| AnnaBridge | 171:3a7713b1edbc | 423 | #define SDIO_FLAG_TXACT SDIO_STA_TXACT |
| AnnaBridge | 171:3a7713b1edbc | 424 | #define SDIO_FLAG_RXACT SDIO_STA_RXACT |
| AnnaBridge | 171:3a7713b1edbc | 425 | #define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE |
| AnnaBridge | 171:3a7713b1edbc | 426 | #define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF |
| AnnaBridge | 171:3a7713b1edbc | 427 | #define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF |
| AnnaBridge | 171:3a7713b1edbc | 428 | #define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF |
| AnnaBridge | 171:3a7713b1edbc | 429 | #define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE |
| AnnaBridge | 171:3a7713b1edbc | 430 | #define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE |
| AnnaBridge | 171:3a7713b1edbc | 431 | #define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL |
| AnnaBridge | 171:3a7713b1edbc | 432 | #define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL |
| AnnaBridge | 171:3a7713b1edbc | 433 | #define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT |
| AnnaBridge | 171:3a7713b1edbc | 434 | #define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND |
| AnnaBridge | 171:3a7713b1edbc | 435 | /** |
| AnnaBridge | 171:3a7713b1edbc | 436 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 437 | */ |
| AnnaBridge | 171:3a7713b1edbc | 438 | |
| AnnaBridge | 171:3a7713b1edbc | 439 | /** |
| AnnaBridge | 171:3a7713b1edbc | 440 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 441 | */ |
| AnnaBridge | 171:3a7713b1edbc | 442 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 443 | /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros |
| AnnaBridge | 171:3a7713b1edbc | 444 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 445 | */ |
| AnnaBridge | 171:3a7713b1edbc | 446 | |
| AnnaBridge | 171:3a7713b1edbc | 447 | /** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region |
| AnnaBridge | 171:3a7713b1edbc | 448 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 449 | */ |
| AnnaBridge | 171:3a7713b1edbc | 450 | /* ------------ SDIO registers bit address in the alias region -------------- */ |
| AnnaBridge | 171:3a7713b1edbc | 451 | #define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) |
| AnnaBridge | 171:3a7713b1edbc | 452 | |
| AnnaBridge | 171:3a7713b1edbc | 453 | /* --- CLKCR Register ---*/ |
| AnnaBridge | 171:3a7713b1edbc | 454 | /* Alias word address of CLKEN bit */ |
| AnnaBridge | 171:3a7713b1edbc | 455 | #define CLKCR_OFFSET (SDIO_OFFSET + 0x04) |
| AnnaBridge | 171:3a7713b1edbc | 456 | #define CLKEN_BITNUMBER 0x08 |
| AnnaBridge | 171:3a7713b1edbc | 457 | #define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BITNUMBER * 4)) |
| AnnaBridge | 171:3a7713b1edbc | 458 | |
| AnnaBridge | 171:3a7713b1edbc | 459 | /* --- CMD Register ---*/ |
| AnnaBridge | 171:3a7713b1edbc | 460 | /* Alias word address of SDIOSUSPEND bit */ |
| AnnaBridge | 171:3a7713b1edbc | 461 | #define CMD_OFFSET (SDIO_OFFSET + 0x0C) |
| AnnaBridge | 171:3a7713b1edbc | 462 | #define SDIOSUSPEND_BITNUMBER 0x0B |
| AnnaBridge | 171:3a7713b1edbc | 463 | #define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BITNUMBER * 4)) |
| AnnaBridge | 171:3a7713b1edbc | 464 | |
| AnnaBridge | 171:3a7713b1edbc | 465 | /* Alias word address of ENCMDCOMPL bit */ |
| AnnaBridge | 171:3a7713b1edbc | 466 | #define ENCMDCOMPL_BITNUMBER 0x0C |
| AnnaBridge | 171:3a7713b1edbc | 467 | #define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BITNUMBER * 4)) |
| AnnaBridge | 171:3a7713b1edbc | 468 | |
| AnnaBridge | 171:3a7713b1edbc | 469 | /* Alias word address of NIEN bit */ |
| AnnaBridge | 171:3a7713b1edbc | 470 | #define NIEN_BITNUMBER 0x0D |
| AnnaBridge | 171:3a7713b1edbc | 471 | #define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BITNUMBER * 4)) |
| AnnaBridge | 171:3a7713b1edbc | 472 | |
| AnnaBridge | 171:3a7713b1edbc | 473 | /* Alias word address of ATACMD bit */ |
| AnnaBridge | 171:3a7713b1edbc | 474 | #define ATACMD_BITNUMBER 0x0E |
| AnnaBridge | 171:3a7713b1edbc | 475 | #define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BITNUMBER * 4)) |
| AnnaBridge | 171:3a7713b1edbc | 476 | |
| AnnaBridge | 171:3a7713b1edbc | 477 | /* --- DCTRL Register ---*/ |
| AnnaBridge | 171:3a7713b1edbc | 478 | /* Alias word address of DMAEN bit */ |
| AnnaBridge | 171:3a7713b1edbc | 479 | #define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) |
| AnnaBridge | 171:3a7713b1edbc | 480 | #define DMAEN_BITNUMBER 0x03 |
| AnnaBridge | 171:3a7713b1edbc | 481 | #define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BITNUMBER * 4)) |
| AnnaBridge | 171:3a7713b1edbc | 482 | |
| AnnaBridge | 171:3a7713b1edbc | 483 | /* Alias word address of RWSTART bit */ |
| AnnaBridge | 171:3a7713b1edbc | 484 | #define RWSTART_BITNUMBER 0x08 |
| AnnaBridge | 171:3a7713b1edbc | 485 | #define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BITNUMBER * 4)) |
| AnnaBridge | 171:3a7713b1edbc | 486 | |
| AnnaBridge | 171:3a7713b1edbc | 487 | /* Alias word address of RWSTOP bit */ |
| AnnaBridge | 171:3a7713b1edbc | 488 | #define RWSTOP_BITNUMBER 0x09 |
| AnnaBridge | 171:3a7713b1edbc | 489 | #define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BITNUMBER * 4)) |
| AnnaBridge | 171:3a7713b1edbc | 490 | |
| AnnaBridge | 171:3a7713b1edbc | 491 | /* Alias word address of RWMOD bit */ |
| AnnaBridge | 171:3a7713b1edbc | 492 | #define RWMOD_BITNUMBER 0x0A |
| AnnaBridge | 171:3a7713b1edbc | 493 | #define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BITNUMBER * 4)) |
| AnnaBridge | 171:3a7713b1edbc | 494 | |
| AnnaBridge | 171:3a7713b1edbc | 495 | /* Alias word address of SDIOEN bit */ |
| AnnaBridge | 171:3a7713b1edbc | 496 | #define SDIOEN_BITNUMBER 0x0B |
| AnnaBridge | 171:3a7713b1edbc | 497 | #define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BITNUMBER * 4)) |
| AnnaBridge | 171:3a7713b1edbc | 498 | /** |
| AnnaBridge | 171:3a7713b1edbc | 499 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 500 | */ |
| AnnaBridge | 171:3a7713b1edbc | 501 | |
| AnnaBridge | 171:3a7713b1edbc | 502 | /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions |
| AnnaBridge | 171:3a7713b1edbc | 503 | * @brief SDMMC_LL registers bit address in the alias region |
| AnnaBridge | 171:3a7713b1edbc | 504 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 505 | */ |
| AnnaBridge | 171:3a7713b1edbc | 506 | |
| AnnaBridge | 171:3a7713b1edbc | 507 | /* ---------------------- SDIO registers bit mask --------------------------- */ |
| AnnaBridge | 171:3a7713b1edbc | 508 | /* --- CLKCR Register ---*/ |
| AnnaBridge | 171:3a7713b1edbc | 509 | /* CLKCR register clear mask */ |
| AnnaBridge | 171:3a7713b1edbc | 510 | #define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV | SDIO_CLKCR_PWRSAV |\ |
| AnnaBridge | 171:3a7713b1edbc | 511 | SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS |\ |
| AnnaBridge | 171:3a7713b1edbc | 512 | SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN)) |
| AnnaBridge | 171:3a7713b1edbc | 513 | |
| AnnaBridge | 171:3a7713b1edbc | 514 | /* --- PWRCTRL Register ---*/ |
| AnnaBridge | 171:3a7713b1edbc | 515 | /* --- DCTRL Register ---*/ |
| AnnaBridge | 171:3a7713b1edbc | 516 | /* SDIO DCTRL Clear Mask */ |
| AnnaBridge | 171:3a7713b1edbc | 517 | #define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR |\ |
| AnnaBridge | 171:3a7713b1edbc | 518 | SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE)) |
| AnnaBridge | 171:3a7713b1edbc | 519 | |
| AnnaBridge | 171:3a7713b1edbc | 520 | /* --- CMD Register ---*/ |
| AnnaBridge | 171:3a7713b1edbc | 521 | /* CMD Register clear mask */ |
| AnnaBridge | 171:3a7713b1edbc | 522 | #define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\ |
| AnnaBridge | 171:3a7713b1edbc | 523 | SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND |\ |
| AnnaBridge | 171:3a7713b1edbc | 524 | SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND)) |
| AnnaBridge | 171:3a7713b1edbc | 525 | |
| AnnaBridge | 171:3a7713b1edbc | 526 | /* SDIO RESP Registers Address */ |
| AnnaBridge | 171:3a7713b1edbc | 527 | #define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) |
| AnnaBridge | 171:3a7713b1edbc | 528 | |
| AnnaBridge | 171:3a7713b1edbc | 529 | /* SDIO Initialization Frequency (400KHz max) */ |
| AnnaBridge | 171:3a7713b1edbc | 530 | #define SDIO_INIT_CLK_DIV ((uint8_t)0x76) |
| AnnaBridge | 171:3a7713b1edbc | 531 | |
| AnnaBridge | 171:3a7713b1edbc | 532 | /* SDIO Data Transfer Frequency */ |
| AnnaBridge | 171:3a7713b1edbc | 533 | #define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x4) |
| AnnaBridge | 171:3a7713b1edbc | 534 | |
| AnnaBridge | 171:3a7713b1edbc | 535 | /** |
| AnnaBridge | 171:3a7713b1edbc | 536 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 537 | */ |
| AnnaBridge | 171:3a7713b1edbc | 538 | |
| AnnaBridge | 171:3a7713b1edbc | 539 | /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration |
| AnnaBridge | 171:3a7713b1edbc | 540 | * @brief macros to handle interrupts and specific clock configurations |
| AnnaBridge | 171:3a7713b1edbc | 541 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 542 | */ |
| AnnaBridge | 171:3a7713b1edbc | 543 | |
| AnnaBridge | 171:3a7713b1edbc | 544 | /** |
| AnnaBridge | 171:3a7713b1edbc | 545 | * @brief Enable the SDIO device. |
| AnnaBridge | 171:3a7713b1edbc | 546 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 547 | */ |
| AnnaBridge | 171:3a7713b1edbc | 548 | #define __SDIO_ENABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE) |
| AnnaBridge | 171:3a7713b1edbc | 549 | |
| AnnaBridge | 171:3a7713b1edbc | 550 | /** |
| AnnaBridge | 171:3a7713b1edbc | 551 | * @brief Disable the SDIO device. |
| AnnaBridge | 171:3a7713b1edbc | 552 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 553 | */ |
| AnnaBridge | 171:3a7713b1edbc | 554 | #define __SDIO_DISABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE) |
| AnnaBridge | 171:3a7713b1edbc | 555 | |
| AnnaBridge | 171:3a7713b1edbc | 556 | /** |
| AnnaBridge | 171:3a7713b1edbc | 557 | * @brief Enable the SDIO DMA transfer. |
| AnnaBridge | 171:3a7713b1edbc | 558 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 559 | */ |
| AnnaBridge | 171:3a7713b1edbc | 560 | #define __SDIO_DMA_ENABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE) |
| AnnaBridge | 171:3a7713b1edbc | 561 | |
| AnnaBridge | 171:3a7713b1edbc | 562 | /** |
| AnnaBridge | 171:3a7713b1edbc | 563 | * @brief Disable the SDIO DMA transfer. |
| AnnaBridge | 171:3a7713b1edbc | 564 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 565 | */ |
| AnnaBridge | 171:3a7713b1edbc | 566 | #define __SDIO_DMA_DISABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE) |
| AnnaBridge | 171:3a7713b1edbc | 567 | |
| AnnaBridge | 171:3a7713b1edbc | 568 | /** |
| AnnaBridge | 171:3a7713b1edbc | 569 | * @brief Enable the SDIO device interrupt. |
| AnnaBridge | 171:3a7713b1edbc | 570 | * @param __INSTANCE__ : Pointer to SDIO register base |
| AnnaBridge | 171:3a7713b1edbc | 571 | * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled. |
| AnnaBridge | 171:3a7713b1edbc | 572 | * This parameter can be one or a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 573 | * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
| AnnaBridge | 171:3a7713b1edbc | 574 | * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
| AnnaBridge | 171:3a7713b1edbc | 575 | * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt |
| AnnaBridge | 171:3a7713b1edbc | 576 | * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
| AnnaBridge | 171:3a7713b1edbc | 577 | * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
| AnnaBridge | 171:3a7713b1edbc | 578 | * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
| AnnaBridge | 171:3a7713b1edbc | 579 | * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
| AnnaBridge | 171:3a7713b1edbc | 580 | * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
| AnnaBridge | 171:3a7713b1edbc | 581 | * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt |
| AnnaBridge | 171:3a7713b1edbc | 582 | * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide |
| AnnaBridge | 171:3a7713b1edbc | 583 | * bus mode interrupt |
| AnnaBridge | 171:3a7713b1edbc | 584 | * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
| AnnaBridge | 171:3a7713b1edbc | 585 | * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt |
| AnnaBridge | 171:3a7713b1edbc | 586 | * @arg SDIO_IT_TXACT: Data transmit in progress interrupt |
| AnnaBridge | 171:3a7713b1edbc | 587 | * @arg SDIO_IT_RXACT: Data receive in progress interrupt |
| AnnaBridge | 171:3a7713b1edbc | 588 | * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
| AnnaBridge | 171:3a7713b1edbc | 589 | * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
| AnnaBridge | 171:3a7713b1edbc | 590 | * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt |
| AnnaBridge | 171:3a7713b1edbc | 591 | * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt |
| AnnaBridge | 171:3a7713b1edbc | 592 | * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt |
| AnnaBridge | 171:3a7713b1edbc | 593 | * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt |
| AnnaBridge | 171:3a7713b1edbc | 594 | * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt |
| AnnaBridge | 171:3a7713b1edbc | 595 | * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt |
| AnnaBridge | 171:3a7713b1edbc | 596 | * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt |
| AnnaBridge | 171:3a7713b1edbc | 597 | * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt |
| AnnaBridge | 171:3a7713b1edbc | 598 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 599 | */ |
| AnnaBridge | 171:3a7713b1edbc | 600 | #define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) |
| AnnaBridge | 171:3a7713b1edbc | 601 | |
| AnnaBridge | 171:3a7713b1edbc | 602 | /** |
| AnnaBridge | 171:3a7713b1edbc | 603 | * @brief Disable the SDIO device interrupt. |
| AnnaBridge | 171:3a7713b1edbc | 604 | * @param __INSTANCE__ : Pointer to SDIO register base |
| AnnaBridge | 171:3a7713b1edbc | 605 | * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled. |
| AnnaBridge | 171:3a7713b1edbc | 606 | * This parameter can be one or a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 607 | * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
| AnnaBridge | 171:3a7713b1edbc | 608 | * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
| AnnaBridge | 171:3a7713b1edbc | 609 | * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt |
| AnnaBridge | 171:3a7713b1edbc | 610 | * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
| AnnaBridge | 171:3a7713b1edbc | 611 | * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
| AnnaBridge | 171:3a7713b1edbc | 612 | * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
| AnnaBridge | 171:3a7713b1edbc | 613 | * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
| AnnaBridge | 171:3a7713b1edbc | 614 | * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
| AnnaBridge | 171:3a7713b1edbc | 615 | * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt |
| AnnaBridge | 171:3a7713b1edbc | 616 | * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide |
| AnnaBridge | 171:3a7713b1edbc | 617 | * bus mode interrupt |
| AnnaBridge | 171:3a7713b1edbc | 618 | * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
| AnnaBridge | 171:3a7713b1edbc | 619 | * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt |
| AnnaBridge | 171:3a7713b1edbc | 620 | * @arg SDIO_IT_TXACT: Data transmit in progress interrupt |
| AnnaBridge | 171:3a7713b1edbc | 621 | * @arg SDIO_IT_RXACT: Data receive in progress interrupt |
| AnnaBridge | 171:3a7713b1edbc | 622 | * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
| AnnaBridge | 171:3a7713b1edbc | 623 | * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
| AnnaBridge | 171:3a7713b1edbc | 624 | * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt |
| AnnaBridge | 171:3a7713b1edbc | 625 | * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt |
| AnnaBridge | 171:3a7713b1edbc | 626 | * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt |
| AnnaBridge | 171:3a7713b1edbc | 627 | * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt |
| AnnaBridge | 171:3a7713b1edbc | 628 | * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt |
| AnnaBridge | 171:3a7713b1edbc | 629 | * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt |
| AnnaBridge | 171:3a7713b1edbc | 630 | * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt |
| AnnaBridge | 171:3a7713b1edbc | 631 | * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt |
| AnnaBridge | 171:3a7713b1edbc | 632 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 633 | */ |
| AnnaBridge | 171:3a7713b1edbc | 634 | #define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) |
| AnnaBridge | 171:3a7713b1edbc | 635 | |
| AnnaBridge | 171:3a7713b1edbc | 636 | /** |
| AnnaBridge | 171:3a7713b1edbc | 637 | * @brief Checks whether the specified SDIO flag is set or not. |
| AnnaBridge | 171:3a7713b1edbc | 638 | * @param __INSTANCE__ : Pointer to SDIO register base |
| AnnaBridge | 171:3a7713b1edbc | 639 | * @param __FLAG__: specifies the flag to check. |
| AnnaBridge | 171:3a7713b1edbc | 640 | * This parameter can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 641 | * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) |
| AnnaBridge | 171:3a7713b1edbc | 642 | * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) |
| AnnaBridge | 171:3a7713b1edbc | 643 | * @arg SDIO_FLAG_CTIMEOUT: Command response timeout |
| AnnaBridge | 171:3a7713b1edbc | 644 | * @arg SDIO_FLAG_DTIMEOUT: Data timeout |
| AnnaBridge | 171:3a7713b1edbc | 645 | * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error |
| AnnaBridge | 171:3a7713b1edbc | 646 | * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error |
| AnnaBridge | 171:3a7713b1edbc | 647 | * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) |
| AnnaBridge | 171:3a7713b1edbc | 648 | * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) |
| AnnaBridge | 171:3a7713b1edbc | 649 | * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) |
| AnnaBridge | 171:3a7713b1edbc | 650 | * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode. |
| AnnaBridge | 171:3a7713b1edbc | 651 | * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) |
| AnnaBridge | 171:3a7713b1edbc | 652 | * @arg SDIO_FLAG_CMDACT: Command transfer in progress |
| AnnaBridge | 171:3a7713b1edbc | 653 | * @arg SDIO_FLAG_TXACT: Data transmit in progress |
| AnnaBridge | 171:3a7713b1edbc | 654 | * @arg SDIO_FLAG_RXACT: Data receive in progress |
| AnnaBridge | 171:3a7713b1edbc | 655 | * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty |
| AnnaBridge | 171:3a7713b1edbc | 656 | * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full |
| AnnaBridge | 171:3a7713b1edbc | 657 | * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full |
| AnnaBridge | 171:3a7713b1edbc | 658 | * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full |
| AnnaBridge | 171:3a7713b1edbc | 659 | * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty |
| AnnaBridge | 171:3a7713b1edbc | 660 | * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty |
| AnnaBridge | 171:3a7713b1edbc | 661 | * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO |
| AnnaBridge | 171:3a7713b1edbc | 662 | * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO |
| AnnaBridge | 171:3a7713b1edbc | 663 | * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received |
| AnnaBridge | 171:3a7713b1edbc | 664 | * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 |
| AnnaBridge | 171:3a7713b1edbc | 665 | * @retval The new state of SDIO_FLAG (SET or RESET). |
| AnnaBridge | 171:3a7713b1edbc | 666 | */ |
| AnnaBridge | 171:3a7713b1edbc | 667 | #define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET) |
| AnnaBridge | 171:3a7713b1edbc | 668 | |
| AnnaBridge | 171:3a7713b1edbc | 669 | |
| AnnaBridge | 171:3a7713b1edbc | 670 | /** |
| AnnaBridge | 171:3a7713b1edbc | 671 | * @brief Clears the SDIO pending flags. |
| AnnaBridge | 171:3a7713b1edbc | 672 | * @param __INSTANCE__ : Pointer to SDIO register base |
| AnnaBridge | 171:3a7713b1edbc | 673 | * @param __FLAG__: specifies the flag to clear. |
| AnnaBridge | 171:3a7713b1edbc | 674 | * This parameter can be one or a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 675 | * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) |
| AnnaBridge | 171:3a7713b1edbc | 676 | * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) |
| AnnaBridge | 171:3a7713b1edbc | 677 | * @arg SDIO_FLAG_CTIMEOUT: Command response timeout |
| AnnaBridge | 171:3a7713b1edbc | 678 | * @arg SDIO_FLAG_DTIMEOUT: Data timeout |
| AnnaBridge | 171:3a7713b1edbc | 679 | * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error |
| AnnaBridge | 171:3a7713b1edbc | 680 | * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error |
| AnnaBridge | 171:3a7713b1edbc | 681 | * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) |
| AnnaBridge | 171:3a7713b1edbc | 682 | * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) |
| AnnaBridge | 171:3a7713b1edbc | 683 | * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) |
| AnnaBridge | 171:3a7713b1edbc | 684 | * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode |
| AnnaBridge | 171:3a7713b1edbc | 685 | * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) |
| AnnaBridge | 171:3a7713b1edbc | 686 | * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received |
| AnnaBridge | 171:3a7713b1edbc | 687 | * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 |
| AnnaBridge | 171:3a7713b1edbc | 688 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 689 | */ |
| AnnaBridge | 171:3a7713b1edbc | 690 | #define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) |
| AnnaBridge | 171:3a7713b1edbc | 691 | |
| AnnaBridge | 171:3a7713b1edbc | 692 | /** |
| AnnaBridge | 171:3a7713b1edbc | 693 | * @brief Checks whether the specified SDIO interrupt has occurred or not. |
| AnnaBridge | 171:3a7713b1edbc | 694 | * @param __INSTANCE__ : Pointer to SDIO register base |
| AnnaBridge | 171:3a7713b1edbc | 695 | * @param __INTERRUPT__: specifies the SDIO interrupt source to check. |
| AnnaBridge | 171:3a7713b1edbc | 696 | * This parameter can be one of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 697 | * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
| AnnaBridge | 171:3a7713b1edbc | 698 | * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
| AnnaBridge | 171:3a7713b1edbc | 699 | * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt |
| AnnaBridge | 171:3a7713b1edbc | 700 | * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
| AnnaBridge | 171:3a7713b1edbc | 701 | * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
| AnnaBridge | 171:3a7713b1edbc | 702 | * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
| AnnaBridge | 171:3a7713b1edbc | 703 | * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
| AnnaBridge | 171:3a7713b1edbc | 704 | * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
| AnnaBridge | 171:3a7713b1edbc | 705 | * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt |
| AnnaBridge | 171:3a7713b1edbc | 706 | * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide |
| AnnaBridge | 171:3a7713b1edbc | 707 | * bus mode interrupt |
| AnnaBridge | 171:3a7713b1edbc | 708 | * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
| AnnaBridge | 171:3a7713b1edbc | 709 | * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt |
| AnnaBridge | 171:3a7713b1edbc | 710 | * @arg SDIO_IT_TXACT: Data transmit in progress interrupt |
| AnnaBridge | 171:3a7713b1edbc | 711 | * @arg SDIO_IT_RXACT: Data receive in progress interrupt |
| AnnaBridge | 171:3a7713b1edbc | 712 | * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
| AnnaBridge | 171:3a7713b1edbc | 713 | * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt |
| AnnaBridge | 171:3a7713b1edbc | 714 | * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt |
| AnnaBridge | 171:3a7713b1edbc | 715 | * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt |
| AnnaBridge | 171:3a7713b1edbc | 716 | * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt |
| AnnaBridge | 171:3a7713b1edbc | 717 | * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt |
| AnnaBridge | 171:3a7713b1edbc | 718 | * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt |
| AnnaBridge | 171:3a7713b1edbc | 719 | * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt |
| AnnaBridge | 171:3a7713b1edbc | 720 | * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt |
| AnnaBridge | 171:3a7713b1edbc | 721 | * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt |
| AnnaBridge | 171:3a7713b1edbc | 722 | * @retval The new state of SDIO_IT (SET or RESET). |
| AnnaBridge | 171:3a7713b1edbc | 723 | */ |
| AnnaBridge | 171:3a7713b1edbc | 724 | #define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) |
| AnnaBridge | 171:3a7713b1edbc | 725 | |
| AnnaBridge | 171:3a7713b1edbc | 726 | /** |
| AnnaBridge | 171:3a7713b1edbc | 727 | * @brief Clears the SDIO's interrupt pending bits. |
| AnnaBridge | 171:3a7713b1edbc | 728 | * @param __INSTANCE__ : Pointer to SDIO register base |
| AnnaBridge | 171:3a7713b1edbc | 729 | * @param __INTERRUPT__: specifies the interrupt pending bit to clear. |
| AnnaBridge | 171:3a7713b1edbc | 730 | * This parameter can be one or a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 731 | * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt |
| AnnaBridge | 171:3a7713b1edbc | 732 | * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt |
| AnnaBridge | 171:3a7713b1edbc | 733 | * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt |
| AnnaBridge | 171:3a7713b1edbc | 734 | * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
| AnnaBridge | 171:3a7713b1edbc | 735 | * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
| AnnaBridge | 171:3a7713b1edbc | 736 | * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
| AnnaBridge | 171:3a7713b1edbc | 737 | * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
| AnnaBridge | 171:3a7713b1edbc | 738 | * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
| AnnaBridge | 171:3a7713b1edbc | 739 | * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt |
| AnnaBridge | 171:3a7713b1edbc | 740 | * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide |
| AnnaBridge | 171:3a7713b1edbc | 741 | * bus mode interrupt |
| AnnaBridge | 171:3a7713b1edbc | 742 | * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt |
| AnnaBridge | 171:3a7713b1edbc | 743 | * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 |
| AnnaBridge | 171:3a7713b1edbc | 744 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 745 | */ |
| AnnaBridge | 171:3a7713b1edbc | 746 | #define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) |
| AnnaBridge | 171:3a7713b1edbc | 747 | |
| AnnaBridge | 171:3a7713b1edbc | 748 | /** |
| AnnaBridge | 171:3a7713b1edbc | 749 | * @brief Enable Start the SD I/O Read Wait operation. |
| AnnaBridge | 171:3a7713b1edbc | 750 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 751 | */ |
| AnnaBridge | 171:3a7713b1edbc | 752 | #define __SDIO_START_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE) |
| AnnaBridge | 171:3a7713b1edbc | 753 | |
| AnnaBridge | 171:3a7713b1edbc | 754 | /** |
| AnnaBridge | 171:3a7713b1edbc | 755 | * @brief Disable Start the SD I/O Read Wait operations. |
| AnnaBridge | 171:3a7713b1edbc | 756 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 757 | */ |
| AnnaBridge | 171:3a7713b1edbc | 758 | #define __SDIO_START_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE) |
| AnnaBridge | 171:3a7713b1edbc | 759 | |
| AnnaBridge | 171:3a7713b1edbc | 760 | /** |
| AnnaBridge | 171:3a7713b1edbc | 761 | * @brief Enable Start the SD I/O Read Wait operation. |
| AnnaBridge | 171:3a7713b1edbc | 762 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 763 | */ |
| AnnaBridge | 171:3a7713b1edbc | 764 | #define __SDIO_STOP_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE) |
| AnnaBridge | 171:3a7713b1edbc | 765 | |
| AnnaBridge | 171:3a7713b1edbc | 766 | /** |
| AnnaBridge | 171:3a7713b1edbc | 767 | * @brief Disable Stop the SD I/O Read Wait operations. |
| AnnaBridge | 171:3a7713b1edbc | 768 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 769 | */ |
| AnnaBridge | 171:3a7713b1edbc | 770 | #define __SDIO_STOP_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE) |
| AnnaBridge | 171:3a7713b1edbc | 771 | |
| AnnaBridge | 171:3a7713b1edbc | 772 | /** |
| AnnaBridge | 171:3a7713b1edbc | 773 | * @brief Enable the SD I/O Mode Operation. |
| AnnaBridge | 171:3a7713b1edbc | 774 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 775 | */ |
| AnnaBridge | 171:3a7713b1edbc | 776 | #define __SDIO_OPERATION_ENABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE) |
| AnnaBridge | 171:3a7713b1edbc | 777 | |
| AnnaBridge | 171:3a7713b1edbc | 778 | /** |
| AnnaBridge | 171:3a7713b1edbc | 779 | * @brief Disable the SD I/O Mode Operation. |
| AnnaBridge | 171:3a7713b1edbc | 780 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 781 | */ |
| AnnaBridge | 171:3a7713b1edbc | 782 | #define __SDIO_OPERATION_DISABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE) |
| AnnaBridge | 171:3a7713b1edbc | 783 | |
| AnnaBridge | 171:3a7713b1edbc | 784 | /** |
| AnnaBridge | 171:3a7713b1edbc | 785 | * @brief Enable the SD I/O Suspend command sending. |
| AnnaBridge | 171:3a7713b1edbc | 786 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 787 | */ |
| AnnaBridge | 171:3a7713b1edbc | 788 | #define __SDIO_SUSPEND_CMD_ENABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE) |
| AnnaBridge | 171:3a7713b1edbc | 789 | |
| AnnaBridge | 171:3a7713b1edbc | 790 | /** |
| AnnaBridge | 171:3a7713b1edbc | 791 | * @brief Disable the SD I/O Suspend command sending. |
| AnnaBridge | 171:3a7713b1edbc | 792 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 793 | */ |
| AnnaBridge | 171:3a7713b1edbc | 794 | #define __SDIO_SUSPEND_CMD_DISABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE) |
| AnnaBridge | 171:3a7713b1edbc | 795 | |
| AnnaBridge | 171:3a7713b1edbc | 796 | /** |
| AnnaBridge | 171:3a7713b1edbc | 797 | * @brief Enable the command completion signal. |
| AnnaBridge | 171:3a7713b1edbc | 798 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 799 | */ |
| AnnaBridge | 171:3a7713b1edbc | 800 | #define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE) |
| AnnaBridge | 171:3a7713b1edbc | 801 | |
| AnnaBridge | 171:3a7713b1edbc | 802 | /** |
| AnnaBridge | 171:3a7713b1edbc | 803 | * @brief Disable the command completion signal. |
| AnnaBridge | 171:3a7713b1edbc | 804 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 805 | */ |
| AnnaBridge | 171:3a7713b1edbc | 806 | #define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE) |
| AnnaBridge | 171:3a7713b1edbc | 807 | |
| AnnaBridge | 171:3a7713b1edbc | 808 | /** |
| AnnaBridge | 171:3a7713b1edbc | 809 | * @brief Enable the CE-ATA interrupt. |
| AnnaBridge | 171:3a7713b1edbc | 810 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 811 | */ |
| AnnaBridge | 171:3a7713b1edbc | 812 | #define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = 0U) |
| AnnaBridge | 171:3a7713b1edbc | 813 | |
| AnnaBridge | 171:3a7713b1edbc | 814 | /** |
| AnnaBridge | 171:3a7713b1edbc | 815 | * @brief Disable the CE-ATA interrupt. |
| AnnaBridge | 171:3a7713b1edbc | 816 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 817 | */ |
| AnnaBridge | 171:3a7713b1edbc | 818 | #define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = 1U) |
| AnnaBridge | 171:3a7713b1edbc | 819 | |
| AnnaBridge | 171:3a7713b1edbc | 820 | /** |
| AnnaBridge | 171:3a7713b1edbc | 821 | * @brief Enable send CE-ATA command (CMD61). |
| AnnaBridge | 171:3a7713b1edbc | 822 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 823 | */ |
| AnnaBridge | 171:3a7713b1edbc | 824 | #define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE) |
| AnnaBridge | 171:3a7713b1edbc | 825 | |
| AnnaBridge | 171:3a7713b1edbc | 826 | /** |
| AnnaBridge | 171:3a7713b1edbc | 827 | * @brief Disable send CE-ATA command (CMD61). |
| AnnaBridge | 171:3a7713b1edbc | 828 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 829 | */ |
| AnnaBridge | 171:3a7713b1edbc | 830 | #define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE) |
| AnnaBridge | 171:3a7713b1edbc | 831 | |
| AnnaBridge | 171:3a7713b1edbc | 832 | /** |
| AnnaBridge | 171:3a7713b1edbc | 833 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 834 | */ |
| AnnaBridge | 171:3a7713b1edbc | 835 | |
| AnnaBridge | 171:3a7713b1edbc | 836 | /** |
| AnnaBridge | 171:3a7713b1edbc | 837 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 838 | */ |
| AnnaBridge | 171:3a7713b1edbc | 839 | |
| AnnaBridge | 171:3a7713b1edbc | 840 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 841 | /** @addtogroup SDMMC_LL_Exported_Functions |
| AnnaBridge | 171:3a7713b1edbc | 842 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 843 | */ |
| AnnaBridge | 171:3a7713b1edbc | 844 | |
| AnnaBridge | 171:3a7713b1edbc | 845 | /* Initialization/de-initialization functions **********************************/ |
| AnnaBridge | 171:3a7713b1edbc | 846 | /** @addtogroup HAL_SDMMC_LL_Group1 |
| AnnaBridge | 171:3a7713b1edbc | 847 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 848 | */ |
| AnnaBridge | 171:3a7713b1edbc | 849 | HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init); |
| AnnaBridge | 171:3a7713b1edbc | 850 | /** |
| AnnaBridge | 171:3a7713b1edbc | 851 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 852 | */ |
| AnnaBridge | 171:3a7713b1edbc | 853 | |
| AnnaBridge | 171:3a7713b1edbc | 854 | /* I/O operation functions *****************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 855 | /** @addtogroup HAL_SDMMC_LL_Group2 |
| AnnaBridge | 171:3a7713b1edbc | 856 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 857 | */ |
| AnnaBridge | 171:3a7713b1edbc | 858 | /* Blocking mode: Polling */ |
| AnnaBridge | 171:3a7713b1edbc | 859 | uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx); |
| AnnaBridge | 171:3a7713b1edbc | 860 | HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData); |
| AnnaBridge | 171:3a7713b1edbc | 861 | /** |
| AnnaBridge | 171:3a7713b1edbc | 862 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 863 | */ |
| AnnaBridge | 171:3a7713b1edbc | 864 | |
| AnnaBridge | 171:3a7713b1edbc | 865 | /* Peripheral Control functions ************************************************/ |
| AnnaBridge | 171:3a7713b1edbc | 866 | /** @addtogroup HAL_SDMMC_LL_Group3 |
| AnnaBridge | 171:3a7713b1edbc | 867 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 868 | */ |
| AnnaBridge | 171:3a7713b1edbc | 869 | HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx); |
| AnnaBridge | 171:3a7713b1edbc | 870 | HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx); |
| AnnaBridge | 171:3a7713b1edbc | 871 | uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx); |
| AnnaBridge | 171:3a7713b1edbc | 872 | |
| AnnaBridge | 171:3a7713b1edbc | 873 | /* Command path state machine (CPSM) management functions */ |
| AnnaBridge | 171:3a7713b1edbc | 874 | HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); |
| AnnaBridge | 171:3a7713b1edbc | 875 | uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx); |
| AnnaBridge | 171:3a7713b1edbc | 876 | uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); |
| AnnaBridge | 171:3a7713b1edbc | 877 | |
| AnnaBridge | 171:3a7713b1edbc | 878 | /* Data path state machine (DPSM) management functions */ |
| AnnaBridge | 171:3a7713b1edbc | 879 | HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct); |
| AnnaBridge | 171:3a7713b1edbc | 880 | uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx); |
| AnnaBridge | 171:3a7713b1edbc | 881 | uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx); |
| AnnaBridge | 171:3a7713b1edbc | 882 | |
| AnnaBridge | 171:3a7713b1edbc | 883 | /* SDIO IO Cards mode management functions */ |
| AnnaBridge | 171:3a7713b1edbc | 884 | HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); |
| AnnaBridge | 171:3a7713b1edbc | 885 | |
| AnnaBridge | 171:3a7713b1edbc | 886 | /** |
| AnnaBridge | 171:3a7713b1edbc | 887 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 888 | */ |
| AnnaBridge | 171:3a7713b1edbc | 889 | |
| AnnaBridge | 171:3a7713b1edbc | 890 | /** |
| AnnaBridge | 171:3a7713b1edbc | 891 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 892 | */ |
| AnnaBridge | 171:3a7713b1edbc | 893 | |
| AnnaBridge | 171:3a7713b1edbc | 894 | /** |
| AnnaBridge | 171:3a7713b1edbc | 895 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 896 | */ |
| AnnaBridge | 171:3a7713b1edbc | 897 | |
| AnnaBridge | 171:3a7713b1edbc | 898 | /** |
| AnnaBridge | 171:3a7713b1edbc | 899 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 900 | */ |
| AnnaBridge | 171:3a7713b1edbc | 901 | |
| AnnaBridge | 171:3a7713b1edbc | 902 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 903 | } |
| AnnaBridge | 171:3a7713b1edbc | 904 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 905 | |
| AnnaBridge | 171:3a7713b1edbc | 906 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
| AnnaBridge | 171:3a7713b1edbc | 907 | |
| AnnaBridge | 171:3a7713b1edbc | 908 | #endif /* __STM32L1xx_LL_SD_H */ |
| AnnaBridge | 171:3a7713b1edbc | 909 | |
| AnnaBridge | 171:3a7713b1edbc | 910 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
