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TARGET_MOTE_L152RC/TOOLCHAIN_IAR/stm32l1xx_ll_bus.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 171:3a7713b1edbc | 1 | /** |
| AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32l1xx_ll_bus.h |
| AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
| AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of BUS LL module. |
| AnnaBridge | 171:3a7713b1edbc | 6 | |
| AnnaBridge | 171:3a7713b1edbc | 7 | @verbatim |
| AnnaBridge | 171:3a7713b1edbc | 8 | ##### RCC Limitations ##### |
| AnnaBridge | 171:3a7713b1edbc | 9 | ============================================================================== |
| AnnaBridge | 171:3a7713b1edbc | 10 | [..] |
| AnnaBridge | 171:3a7713b1edbc | 11 | A delay between an RCC peripheral clock enable and the effective peripheral |
| AnnaBridge | 171:3a7713b1edbc | 12 | enabling should be taken into account in order to manage the peripheral read/write |
| AnnaBridge | 171:3a7713b1edbc | 13 | from/to registers. |
| AnnaBridge | 171:3a7713b1edbc | 14 | (+) This delay depends on the peripheral mapping. |
| AnnaBridge | 171:3a7713b1edbc | 15 | (++) AHB & APB peripherals, 1 dummy read is necessary |
| AnnaBridge | 171:3a7713b1edbc | 16 | |
| AnnaBridge | 171:3a7713b1edbc | 17 | [..] |
| AnnaBridge | 171:3a7713b1edbc | 18 | Workarounds: |
| AnnaBridge | 171:3a7713b1edbc | 19 | (#) For AHB & APB peripherals, a dummy read to the peripheral register has been |
| AnnaBridge | 171:3a7713b1edbc | 20 | inserted in each LL_{BUS}_GRP{x}_EnableClock() function. |
| AnnaBridge | 171:3a7713b1edbc | 21 | |
| AnnaBridge | 171:3a7713b1edbc | 22 | @endverbatim |
| AnnaBridge | 171:3a7713b1edbc | 23 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 24 | * @attention |
| AnnaBridge | 171:3a7713b1edbc | 25 | * |
| AnnaBridge | 171:3a7713b1edbc | 26 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 171:3a7713b1edbc | 27 | * |
| AnnaBridge | 171:3a7713b1edbc | 28 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 171:3a7713b1edbc | 29 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 171:3a7713b1edbc | 30 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 31 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 171:3a7713b1edbc | 32 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 171:3a7713b1edbc | 33 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 171:3a7713b1edbc | 34 | * and/or other materials provided with the distribution. |
| AnnaBridge | 171:3a7713b1edbc | 35 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 171:3a7713b1edbc | 36 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 171:3a7713b1edbc | 37 | * without specific prior written permission. |
| AnnaBridge | 171:3a7713b1edbc | 38 | * |
| AnnaBridge | 171:3a7713b1edbc | 39 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 171:3a7713b1edbc | 40 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 171:3a7713b1edbc | 41 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 171:3a7713b1edbc | 42 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 171:3a7713b1edbc | 43 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 171:3a7713b1edbc | 44 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 171:3a7713b1edbc | 45 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 171:3a7713b1edbc | 46 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 171:3a7713b1edbc | 47 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 171:3a7713b1edbc | 48 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 171:3a7713b1edbc | 49 | * |
| AnnaBridge | 171:3a7713b1edbc | 50 | ****************************************************************************** |
| AnnaBridge | 171:3a7713b1edbc | 51 | */ |
| AnnaBridge | 171:3a7713b1edbc | 52 | |
| AnnaBridge | 171:3a7713b1edbc | 53 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 54 | #ifndef __STM32L1xx_LL_BUS_H |
| AnnaBridge | 171:3a7713b1edbc | 55 | #define __STM32L1xx_LL_BUS_H |
| AnnaBridge | 171:3a7713b1edbc | 56 | |
| AnnaBridge | 171:3a7713b1edbc | 57 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 58 | extern "C" { |
| AnnaBridge | 171:3a7713b1edbc | 59 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 60 | |
| AnnaBridge | 171:3a7713b1edbc | 61 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 62 | #include "stm32l1xx.h" |
| AnnaBridge | 171:3a7713b1edbc | 63 | |
| AnnaBridge | 171:3a7713b1edbc | 64 | /** @addtogroup STM32L1xx_LL_Driver |
| AnnaBridge | 171:3a7713b1edbc | 65 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 66 | */ |
| AnnaBridge | 171:3a7713b1edbc | 67 | |
| AnnaBridge | 171:3a7713b1edbc | 68 | #if defined(RCC) |
| AnnaBridge | 171:3a7713b1edbc | 69 | |
| AnnaBridge | 171:3a7713b1edbc | 70 | /** @defgroup BUS_LL BUS |
| AnnaBridge | 171:3a7713b1edbc | 71 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 72 | */ |
| AnnaBridge | 171:3a7713b1edbc | 73 | |
| AnnaBridge | 171:3a7713b1edbc | 74 | /* Private types -------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 75 | /* Private variables ---------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 76 | |
| AnnaBridge | 171:3a7713b1edbc | 77 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 78 | |
| AnnaBridge | 171:3a7713b1edbc | 79 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 80 | |
| AnnaBridge | 171:3a7713b1edbc | 81 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 82 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 83 | /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants |
| AnnaBridge | 171:3a7713b1edbc | 84 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 85 | */ |
| AnnaBridge | 171:3a7713b1edbc | 86 | |
| AnnaBridge | 171:3a7713b1edbc | 87 | /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH |
| AnnaBridge | 171:3a7713b1edbc | 88 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 89 | */ |
| AnnaBridge | 171:3a7713b1edbc | 90 | #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU |
| AnnaBridge | 171:3a7713b1edbc | 91 | #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN |
| AnnaBridge | 171:3a7713b1edbc | 92 | #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN |
| AnnaBridge | 171:3a7713b1edbc | 93 | #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN |
| AnnaBridge | 171:3a7713b1edbc | 94 | #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN |
| AnnaBridge | 171:3a7713b1edbc | 95 | #if defined(GPIOE) |
| AnnaBridge | 171:3a7713b1edbc | 96 | #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN |
| AnnaBridge | 171:3a7713b1edbc | 97 | #endif/*GPIOE*/ |
| AnnaBridge | 171:3a7713b1edbc | 98 | #define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHBENR_GPIOHEN |
| AnnaBridge | 171:3a7713b1edbc | 99 | #if defined(GPIOF) |
| AnnaBridge | 171:3a7713b1edbc | 100 | #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN |
| AnnaBridge | 171:3a7713b1edbc | 101 | #endif/*GPIOF*/ |
| AnnaBridge | 171:3a7713b1edbc | 102 | #if defined(GPIOG) |
| AnnaBridge | 171:3a7713b1edbc | 103 | #define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHBENR_GPIOGEN |
| AnnaBridge | 171:3a7713b1edbc | 104 | #endif/*GPIOG*/ |
| AnnaBridge | 171:3a7713b1edbc | 105 | #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBLPENR_SRAMLPEN |
| AnnaBridge | 171:3a7713b1edbc | 106 | #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN |
| AnnaBridge | 171:3a7713b1edbc | 107 | #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN |
| AnnaBridge | 171:3a7713b1edbc | 108 | #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN |
| AnnaBridge | 171:3a7713b1edbc | 109 | #if defined(DMA2) |
| AnnaBridge | 171:3a7713b1edbc | 110 | #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN |
| AnnaBridge | 171:3a7713b1edbc | 111 | #endif/*DMA2*/ |
| AnnaBridge | 171:3a7713b1edbc | 112 | #if defined(AES) |
| AnnaBridge | 171:3a7713b1edbc | 113 | #define LL_AHB1_GRP1_PERIPH_CRYP RCC_AHBENR_AESEN |
| AnnaBridge | 171:3a7713b1edbc | 114 | #endif/*AES*/ |
| AnnaBridge | 171:3a7713b1edbc | 115 | #if defined(FSMC_Bank1) |
| AnnaBridge | 171:3a7713b1edbc | 116 | #define LL_AHB1_GRP1_PERIPH_FSMC RCC_AHBENR_FSMCEN |
| AnnaBridge | 171:3a7713b1edbc | 117 | #endif/*FSMC_Bank1*/ |
| AnnaBridge | 171:3a7713b1edbc | 118 | /** |
| AnnaBridge | 171:3a7713b1edbc | 119 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 120 | */ |
| AnnaBridge | 171:3a7713b1edbc | 121 | |
| AnnaBridge | 171:3a7713b1edbc | 122 | /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH |
| AnnaBridge | 171:3a7713b1edbc | 123 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 124 | */ |
| AnnaBridge | 171:3a7713b1edbc | 125 | #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU |
| AnnaBridge | 171:3a7713b1edbc | 126 | #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN |
| AnnaBridge | 171:3a7713b1edbc | 127 | #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN |
| AnnaBridge | 171:3a7713b1edbc | 128 | #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN |
| AnnaBridge | 171:3a7713b1edbc | 129 | #if defined(TIM5) |
| AnnaBridge | 171:3a7713b1edbc | 130 | #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN |
| AnnaBridge | 171:3a7713b1edbc | 131 | #endif /*TIM5*/ |
| AnnaBridge | 171:3a7713b1edbc | 132 | #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN |
| AnnaBridge | 171:3a7713b1edbc | 133 | #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN |
| AnnaBridge | 171:3a7713b1edbc | 134 | #if defined(LCD) |
| AnnaBridge | 171:3a7713b1edbc | 135 | #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR_LCDEN |
| AnnaBridge | 171:3a7713b1edbc | 136 | #endif /*LCD*/ |
| AnnaBridge | 171:3a7713b1edbc | 137 | #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN |
| AnnaBridge | 171:3a7713b1edbc | 138 | #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN |
| AnnaBridge | 171:3a7713b1edbc | 139 | #if defined(SPI3) |
| AnnaBridge | 171:3a7713b1edbc | 140 | #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN |
| AnnaBridge | 171:3a7713b1edbc | 141 | #endif /*SPI3*/ |
| AnnaBridge | 171:3a7713b1edbc | 142 | #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN |
| AnnaBridge | 171:3a7713b1edbc | 143 | #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN |
| AnnaBridge | 171:3a7713b1edbc | 144 | #if defined(UART4) |
| AnnaBridge | 171:3a7713b1edbc | 145 | #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN |
| AnnaBridge | 171:3a7713b1edbc | 146 | #endif /*UART4*/ |
| AnnaBridge | 171:3a7713b1edbc | 147 | #if defined(UART5) |
| AnnaBridge | 171:3a7713b1edbc | 148 | #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN |
| AnnaBridge | 171:3a7713b1edbc | 149 | #endif /*UART5*/ |
| AnnaBridge | 171:3a7713b1edbc | 150 | #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN |
| AnnaBridge | 171:3a7713b1edbc | 151 | #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN |
| AnnaBridge | 171:3a7713b1edbc | 152 | #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN |
| AnnaBridge | 171:3a7713b1edbc | 153 | #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN |
| AnnaBridge | 171:3a7713b1edbc | 154 | #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN |
| AnnaBridge | 171:3a7713b1edbc | 155 | #define LL_APB1_GRP1_PERIPH_COMP RCC_APB1ENR_COMPEN |
| AnnaBridge | 171:3a7713b1edbc | 156 | #if defined(OPAMP) |
| AnnaBridge | 171:3a7713b1edbc | 157 | /* Note: Peripherals COMP and OPAMP share the same clock domain */ |
| AnnaBridge | 171:3a7713b1edbc | 158 | #define LL_APB1_GRP1_PERIPH_OPAMP LL_APB1_GRP1_PERIPH_COMP |
| AnnaBridge | 171:3a7713b1edbc | 159 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 160 | /** |
| AnnaBridge | 171:3a7713b1edbc | 161 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 162 | */ |
| AnnaBridge | 171:3a7713b1edbc | 163 | |
| AnnaBridge | 171:3a7713b1edbc | 164 | /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH |
| AnnaBridge | 171:3a7713b1edbc | 165 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 166 | */ |
| AnnaBridge | 171:3a7713b1edbc | 167 | #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU |
| AnnaBridge | 171:3a7713b1edbc | 168 | #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN |
| AnnaBridge | 171:3a7713b1edbc | 169 | #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN |
| AnnaBridge | 171:3a7713b1edbc | 170 | #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN |
| AnnaBridge | 171:3a7713b1edbc | 171 | #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN |
| AnnaBridge | 171:3a7713b1edbc | 172 | #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN |
| AnnaBridge | 171:3a7713b1edbc | 173 | #if defined(SDIO) |
| AnnaBridge | 171:3a7713b1edbc | 174 | #define LL_APB2_GRP1_PERIPH_SDIO RCC_APB2ENR_SDIOEN |
| AnnaBridge | 171:3a7713b1edbc | 175 | #endif /*SDIO*/ |
| AnnaBridge | 171:3a7713b1edbc | 176 | #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN |
| AnnaBridge | 171:3a7713b1edbc | 177 | #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN |
| AnnaBridge | 171:3a7713b1edbc | 178 | /** |
| AnnaBridge | 171:3a7713b1edbc | 179 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 180 | */ |
| AnnaBridge | 171:3a7713b1edbc | 181 | |
| AnnaBridge | 171:3a7713b1edbc | 182 | /** |
| AnnaBridge | 171:3a7713b1edbc | 183 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 184 | */ |
| AnnaBridge | 171:3a7713b1edbc | 185 | |
| AnnaBridge | 171:3a7713b1edbc | 186 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 187 | |
| AnnaBridge | 171:3a7713b1edbc | 188 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 171:3a7713b1edbc | 189 | /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions |
| AnnaBridge | 171:3a7713b1edbc | 190 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 191 | */ |
| AnnaBridge | 171:3a7713b1edbc | 192 | |
| AnnaBridge | 171:3a7713b1edbc | 193 | /** @defgroup BUS_LL_EF_AHB1 AHB1 |
| AnnaBridge | 171:3a7713b1edbc | 194 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 195 | */ |
| AnnaBridge | 171:3a7713b1edbc | 196 | |
| AnnaBridge | 171:3a7713b1edbc | 197 | /** |
| AnnaBridge | 171:3a7713b1edbc | 198 | * @brief Enable AHB1 peripherals clock. |
| AnnaBridge | 171:3a7713b1edbc | 199 | * @rmtoll AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 200 | * AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 201 | * AHBENR GPIOCEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 202 | * AHBENR GPIODEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 203 | * AHBENR GPIOEEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 204 | * AHBENR GPIOHEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 205 | * AHBENR GPIOFEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 206 | * AHBENR GPIOGEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 207 | * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 208 | * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 209 | * AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 210 | * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 211 | * AHBENR AESEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 212 | * AHBENR FSMCEN LL_AHB1_GRP1_EnableClock |
| AnnaBridge | 171:3a7713b1edbc | 213 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 214 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| AnnaBridge | 171:3a7713b1edbc | 215 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| AnnaBridge | 171:3a7713b1edbc | 216 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| AnnaBridge | 171:3a7713b1edbc | 217 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD |
| AnnaBridge | 171:3a7713b1edbc | 218 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) |
| AnnaBridge | 171:3a7713b1edbc | 219 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH |
| AnnaBridge | 171:3a7713b1edbc | 220 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) |
| AnnaBridge | 171:3a7713b1edbc | 221 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) |
| AnnaBridge | 171:3a7713b1edbc | 222 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 171:3a7713b1edbc | 223 | * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH |
| AnnaBridge | 171:3a7713b1edbc | 224 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 171:3a7713b1edbc | 225 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 226 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) |
| AnnaBridge | 171:3a7713b1edbc | 227 | * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*) |
| AnnaBridge | 171:3a7713b1edbc | 228 | * |
| AnnaBridge | 171:3a7713b1edbc | 229 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 230 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 231 | */ |
| AnnaBridge | 171:3a7713b1edbc | 232 | __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 233 | { |
| AnnaBridge | 171:3a7713b1edbc | 234 | __IO uint32_t tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 235 | SET_BIT(RCC->AHBENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 236 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 171:3a7713b1edbc | 237 | tmpreg = READ_BIT(RCC->AHBENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 238 | (void)tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 239 | } |
| AnnaBridge | 171:3a7713b1edbc | 240 | |
| AnnaBridge | 171:3a7713b1edbc | 241 | /** |
| AnnaBridge | 171:3a7713b1edbc | 242 | * @brief Check if AHB1 peripheral clock is enabled or not |
| AnnaBridge | 171:3a7713b1edbc | 243 | * @rmtoll AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 244 | * AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 245 | * AHBENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 246 | * AHBENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 247 | * AHBENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 248 | * AHBENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 249 | * AHBENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 250 | * AHBENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 251 | * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 252 | * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 253 | * AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 254 | * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 255 | * AHBENR AESEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 256 | * AHBENR FSMCEN LL_AHB1_GRP1_IsEnabledClock |
| AnnaBridge | 171:3a7713b1edbc | 257 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 258 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| AnnaBridge | 171:3a7713b1edbc | 259 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| AnnaBridge | 171:3a7713b1edbc | 260 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| AnnaBridge | 171:3a7713b1edbc | 261 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD |
| AnnaBridge | 171:3a7713b1edbc | 262 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) |
| AnnaBridge | 171:3a7713b1edbc | 263 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH |
| AnnaBridge | 171:3a7713b1edbc | 264 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) |
| AnnaBridge | 171:3a7713b1edbc | 265 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) |
| AnnaBridge | 171:3a7713b1edbc | 266 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 171:3a7713b1edbc | 267 | * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH |
| AnnaBridge | 171:3a7713b1edbc | 268 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 171:3a7713b1edbc | 269 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 270 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) |
| AnnaBridge | 171:3a7713b1edbc | 271 | * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*) |
| AnnaBridge | 171:3a7713b1edbc | 272 | * |
| AnnaBridge | 171:3a7713b1edbc | 273 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 274 | * @retval State of Periphs (1 or 0). |
| AnnaBridge | 171:3a7713b1edbc | 275 | */ |
| AnnaBridge | 171:3a7713b1edbc | 276 | __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 277 | { |
| AnnaBridge | 171:3a7713b1edbc | 278 | return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 279 | } |
| AnnaBridge | 171:3a7713b1edbc | 280 | |
| AnnaBridge | 171:3a7713b1edbc | 281 | /** |
| AnnaBridge | 171:3a7713b1edbc | 282 | * @brief Disable AHB1 peripherals clock. |
| AnnaBridge | 171:3a7713b1edbc | 283 | * @rmtoll AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 284 | * AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 285 | * AHBENR GPIOCEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 286 | * AHBENR GPIODEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 287 | * AHBENR GPIOEEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 288 | * AHBENR GPIOHEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 289 | * AHBENR GPIOFEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 290 | * AHBENR GPIOGEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 291 | * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 292 | * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 293 | * AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 294 | * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 295 | * AHBENR AESEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 296 | * AHBENR FSMCEN LL_AHB1_GRP1_DisableClock |
| AnnaBridge | 171:3a7713b1edbc | 297 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 298 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| AnnaBridge | 171:3a7713b1edbc | 299 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| AnnaBridge | 171:3a7713b1edbc | 300 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| AnnaBridge | 171:3a7713b1edbc | 301 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD |
| AnnaBridge | 171:3a7713b1edbc | 302 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) |
| AnnaBridge | 171:3a7713b1edbc | 303 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH |
| AnnaBridge | 171:3a7713b1edbc | 304 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) |
| AnnaBridge | 171:3a7713b1edbc | 305 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) |
| AnnaBridge | 171:3a7713b1edbc | 306 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 171:3a7713b1edbc | 307 | * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH |
| AnnaBridge | 171:3a7713b1edbc | 308 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 171:3a7713b1edbc | 309 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 310 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) |
| AnnaBridge | 171:3a7713b1edbc | 311 | * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*) |
| AnnaBridge | 171:3a7713b1edbc | 312 | * |
| AnnaBridge | 171:3a7713b1edbc | 313 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 314 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 315 | */ |
| AnnaBridge | 171:3a7713b1edbc | 316 | __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 317 | { |
| AnnaBridge | 171:3a7713b1edbc | 318 | CLEAR_BIT(RCC->AHBENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 319 | } |
| AnnaBridge | 171:3a7713b1edbc | 320 | |
| AnnaBridge | 171:3a7713b1edbc | 321 | /** |
| AnnaBridge | 171:3a7713b1edbc | 322 | * @brief Force AHB1 peripherals reset. |
| AnnaBridge | 171:3a7713b1edbc | 323 | * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 324 | * AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 325 | * AHBRSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 326 | * AHBRSTR GPIODRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 327 | * AHBRSTR GPIOERST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 328 | * AHBRSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 329 | * AHBRSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 330 | * AHBRSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 331 | * AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 332 | * AHBRSTR FLITFRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 333 | * AHBRSTR DMA1RST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 334 | * AHBRSTR DMA2RST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 335 | * AHBRSTR AESRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 336 | * AHBRSTR FSMCRST LL_AHB1_GRP1_ForceReset |
| AnnaBridge | 171:3a7713b1edbc | 337 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 338 | * @arg @ref LL_AHB1_GRP1_PERIPH_ALL |
| AnnaBridge | 171:3a7713b1edbc | 339 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| AnnaBridge | 171:3a7713b1edbc | 340 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| AnnaBridge | 171:3a7713b1edbc | 341 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| AnnaBridge | 171:3a7713b1edbc | 342 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD |
| AnnaBridge | 171:3a7713b1edbc | 343 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) |
| AnnaBridge | 171:3a7713b1edbc | 344 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH |
| AnnaBridge | 171:3a7713b1edbc | 345 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) |
| AnnaBridge | 171:3a7713b1edbc | 346 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) |
| AnnaBridge | 171:3a7713b1edbc | 347 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 171:3a7713b1edbc | 348 | * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH |
| AnnaBridge | 171:3a7713b1edbc | 349 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 171:3a7713b1edbc | 350 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 351 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) |
| AnnaBridge | 171:3a7713b1edbc | 352 | * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*) |
| AnnaBridge | 171:3a7713b1edbc | 353 | * |
| AnnaBridge | 171:3a7713b1edbc | 354 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 355 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 356 | */ |
| AnnaBridge | 171:3a7713b1edbc | 357 | __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 358 | { |
| AnnaBridge | 171:3a7713b1edbc | 359 | SET_BIT(RCC->AHBRSTR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 360 | } |
| AnnaBridge | 171:3a7713b1edbc | 361 | |
| AnnaBridge | 171:3a7713b1edbc | 362 | /** |
| AnnaBridge | 171:3a7713b1edbc | 363 | * @brief Release AHB1 peripherals reset. |
| AnnaBridge | 171:3a7713b1edbc | 364 | * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 365 | * AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 366 | * AHBRSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 367 | * AHBRSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 368 | * AHBRSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 369 | * AHBRSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 370 | * AHBRSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 371 | * AHBRSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 372 | * AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 373 | * AHBRSTR FLITFRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 374 | * AHBRSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 375 | * AHBRSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 376 | * AHBRSTR AESRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 377 | * AHBRSTR FSMCRST LL_AHB1_GRP1_ReleaseReset |
| AnnaBridge | 171:3a7713b1edbc | 378 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 379 | * @arg @ref LL_AHB1_GRP1_PERIPH_ALL |
| AnnaBridge | 171:3a7713b1edbc | 380 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| AnnaBridge | 171:3a7713b1edbc | 381 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| AnnaBridge | 171:3a7713b1edbc | 382 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| AnnaBridge | 171:3a7713b1edbc | 383 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD |
| AnnaBridge | 171:3a7713b1edbc | 384 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) |
| AnnaBridge | 171:3a7713b1edbc | 385 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH |
| AnnaBridge | 171:3a7713b1edbc | 386 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) |
| AnnaBridge | 171:3a7713b1edbc | 387 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) |
| AnnaBridge | 171:3a7713b1edbc | 388 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 171:3a7713b1edbc | 389 | * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH |
| AnnaBridge | 171:3a7713b1edbc | 390 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 171:3a7713b1edbc | 391 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 392 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) |
| AnnaBridge | 171:3a7713b1edbc | 393 | * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*) |
| AnnaBridge | 171:3a7713b1edbc | 394 | * |
| AnnaBridge | 171:3a7713b1edbc | 395 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 396 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 397 | */ |
| AnnaBridge | 171:3a7713b1edbc | 398 | __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 399 | { |
| AnnaBridge | 171:3a7713b1edbc | 400 | CLEAR_BIT(RCC->AHBRSTR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 401 | } |
| AnnaBridge | 171:3a7713b1edbc | 402 | |
| AnnaBridge | 171:3a7713b1edbc | 403 | /** |
| AnnaBridge | 171:3a7713b1edbc | 404 | * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode. |
| AnnaBridge | 171:3a7713b1edbc | 405 | * @rmtoll AHBLPENR GPIOALPEN LL_AHB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 406 | * AHBLPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 407 | * AHBLPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 408 | * AHBLPENR GPIODLPEN LL_AHB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 409 | * AHBLPENR GPIOELPEN LL_AHB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 410 | * AHBLPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 411 | * AHBLPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 412 | * AHBLPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 413 | * AHBLPENR CRCLPEN LL_AHB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 414 | * AHBLPENR FLITFLPEN LL_AHB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 415 | * AHBLPENR SRAMLPEN LL_AHB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 416 | * AHBLPENR DMA1LPEN LL_AHB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 417 | * AHBLPENR DMA2LPEN LL_AHB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 418 | * AHBLPENR AESLPEN LL_AHB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 419 | * AHBLPENR FSMCLPEN LL_AHB1_GRP1_EnableClockSleep |
| AnnaBridge | 171:3a7713b1edbc | 420 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 421 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| AnnaBridge | 171:3a7713b1edbc | 422 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| AnnaBridge | 171:3a7713b1edbc | 423 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| AnnaBridge | 171:3a7713b1edbc | 424 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD |
| AnnaBridge | 171:3a7713b1edbc | 425 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) |
| AnnaBridge | 171:3a7713b1edbc | 426 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH |
| AnnaBridge | 171:3a7713b1edbc | 427 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) |
| AnnaBridge | 171:3a7713b1edbc | 428 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) |
| AnnaBridge | 171:3a7713b1edbc | 429 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 171:3a7713b1edbc | 430 | * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH |
| AnnaBridge | 171:3a7713b1edbc | 431 | * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM |
| AnnaBridge | 171:3a7713b1edbc | 432 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 171:3a7713b1edbc | 433 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 434 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) |
| AnnaBridge | 171:3a7713b1edbc | 435 | * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*) |
| AnnaBridge | 171:3a7713b1edbc | 436 | * |
| AnnaBridge | 171:3a7713b1edbc | 437 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 438 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 439 | */ |
| AnnaBridge | 171:3a7713b1edbc | 440 | __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 441 | { |
| AnnaBridge | 171:3a7713b1edbc | 442 | __IO uint32_t tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 443 | SET_BIT(RCC->AHBLPENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 444 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 171:3a7713b1edbc | 445 | tmpreg = READ_BIT(RCC->AHBLPENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 446 | (void)tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 447 | } |
| AnnaBridge | 171:3a7713b1edbc | 448 | |
| AnnaBridge | 171:3a7713b1edbc | 449 | /** |
| AnnaBridge | 171:3a7713b1edbc | 450 | * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode. |
| AnnaBridge | 171:3a7713b1edbc | 451 | * @rmtoll AHBLPENR GPIOALPEN LL_AHB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 452 | * AHBLPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 453 | * AHBLPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 454 | * AHBLPENR GPIODLPEN LL_AHB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 455 | * AHBLPENR GPIOELPEN LL_AHB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 456 | * AHBLPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 457 | * AHBLPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 458 | * AHBLPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 459 | * AHBLPENR CRCLPEN LL_AHB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 460 | * AHBLPENR FLITFLPEN LL_AHB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 461 | * AHBLPENR SRAMLPEN LL_AHB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 462 | * AHBLPENR DMA1LPEN LL_AHB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 463 | * AHBLPENR DMA2LPEN LL_AHB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 464 | * AHBLPENR AESLPEN LL_AHB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 465 | * AHBLPENR FSMCLPEN LL_AHB1_GRP1_DisableClockSleep |
| AnnaBridge | 171:3a7713b1edbc | 466 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 467 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA |
| AnnaBridge | 171:3a7713b1edbc | 468 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB |
| AnnaBridge | 171:3a7713b1edbc | 469 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC |
| AnnaBridge | 171:3a7713b1edbc | 470 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD |
| AnnaBridge | 171:3a7713b1edbc | 471 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*) |
| AnnaBridge | 171:3a7713b1edbc | 472 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH |
| AnnaBridge | 171:3a7713b1edbc | 473 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*) |
| AnnaBridge | 171:3a7713b1edbc | 474 | * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*) |
| AnnaBridge | 171:3a7713b1edbc | 475 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 171:3a7713b1edbc | 476 | * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH |
| AnnaBridge | 171:3a7713b1edbc | 477 | * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM |
| AnnaBridge | 171:3a7713b1edbc | 478 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 171:3a7713b1edbc | 479 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) |
| AnnaBridge | 171:3a7713b1edbc | 480 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*) |
| AnnaBridge | 171:3a7713b1edbc | 481 | * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*) |
| AnnaBridge | 171:3a7713b1edbc | 482 | * |
| AnnaBridge | 171:3a7713b1edbc | 483 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 484 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 485 | */ |
| AnnaBridge | 171:3a7713b1edbc | 486 | __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 487 | { |
| AnnaBridge | 171:3a7713b1edbc | 488 | CLEAR_BIT(RCC->AHBLPENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 489 | } |
| AnnaBridge | 171:3a7713b1edbc | 490 | |
| AnnaBridge | 171:3a7713b1edbc | 491 | /** |
| AnnaBridge | 171:3a7713b1edbc | 492 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 493 | */ |
| AnnaBridge | 171:3a7713b1edbc | 494 | |
| AnnaBridge | 171:3a7713b1edbc | 495 | /** @defgroup BUS_LL_EF_APB1 APB1 |
| AnnaBridge | 171:3a7713b1edbc | 496 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 497 | */ |
| AnnaBridge | 171:3a7713b1edbc | 498 | |
| AnnaBridge | 171:3a7713b1edbc | 499 | /** |
| AnnaBridge | 171:3a7713b1edbc | 500 | * @brief Enable APB1 peripherals clock. |
| AnnaBridge | 171:3a7713b1edbc | 501 | * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 502 | * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 503 | * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 504 | * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 505 | * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 506 | * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 507 | * APB1ENR LCDEN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 508 | * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 509 | * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 510 | * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 511 | * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 512 | * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 513 | * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 514 | * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 515 | * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 516 | * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 517 | * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 518 | * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 519 | * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 520 | * APB1ENR COMPEN LL_APB1_GRP1_EnableClock |
| AnnaBridge | 171:3a7713b1edbc | 521 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 522 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 171:3a7713b1edbc | 523 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 |
| AnnaBridge | 171:3a7713b1edbc | 524 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 |
| AnnaBridge | 171:3a7713b1edbc | 525 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) |
| AnnaBridge | 171:3a7713b1edbc | 526 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
| AnnaBridge | 171:3a7713b1edbc | 527 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 |
| AnnaBridge | 171:3a7713b1edbc | 528 | * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) |
| AnnaBridge | 171:3a7713b1edbc | 529 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 171:3a7713b1edbc | 530 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 |
| AnnaBridge | 171:3a7713b1edbc | 531 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) |
| AnnaBridge | 171:3a7713b1edbc | 532 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 171:3a7713b1edbc | 533 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 |
| AnnaBridge | 171:3a7713b1edbc | 534 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
| AnnaBridge | 171:3a7713b1edbc | 535 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
| AnnaBridge | 171:3a7713b1edbc | 536 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 171:3a7713b1edbc | 537 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 |
| AnnaBridge | 171:3a7713b1edbc | 538 | * @arg @ref LL_APB1_GRP1_PERIPH_USB |
| AnnaBridge | 171:3a7713b1edbc | 539 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 171:3a7713b1edbc | 540 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
| AnnaBridge | 171:3a7713b1edbc | 541 | * @arg @ref LL_APB1_GRP1_PERIPH_COMP |
| AnnaBridge | 171:3a7713b1edbc | 542 | * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*) |
| AnnaBridge | 171:3a7713b1edbc | 543 | * |
| AnnaBridge | 171:3a7713b1edbc | 544 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 545 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 546 | */ |
| AnnaBridge | 171:3a7713b1edbc | 547 | __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 548 | { |
| AnnaBridge | 171:3a7713b1edbc | 549 | __IO uint32_t tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 550 | SET_BIT(RCC->APB1ENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 551 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 171:3a7713b1edbc | 552 | tmpreg = READ_BIT(RCC->APB1ENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 553 | (void)tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 554 | } |
| AnnaBridge | 171:3a7713b1edbc | 555 | |
| AnnaBridge | 171:3a7713b1edbc | 556 | /** |
| AnnaBridge | 171:3a7713b1edbc | 557 | * @brief Check if APB1 peripheral clock is enabled or not |
| AnnaBridge | 171:3a7713b1edbc | 558 | * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 559 | * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 560 | * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 561 | * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 562 | * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 563 | * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 564 | * APB1ENR LCDEN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 565 | * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 566 | * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 567 | * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 568 | * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 569 | * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 570 | * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 571 | * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 572 | * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 573 | * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 574 | * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 575 | * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 576 | * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 577 | * APB1ENR COMPEN LL_APB1_GRP1_IsEnabledClock |
| AnnaBridge | 171:3a7713b1edbc | 578 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 579 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 171:3a7713b1edbc | 580 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 |
| AnnaBridge | 171:3a7713b1edbc | 581 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 |
| AnnaBridge | 171:3a7713b1edbc | 582 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) |
| AnnaBridge | 171:3a7713b1edbc | 583 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
| AnnaBridge | 171:3a7713b1edbc | 584 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 |
| AnnaBridge | 171:3a7713b1edbc | 585 | * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) |
| AnnaBridge | 171:3a7713b1edbc | 586 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 171:3a7713b1edbc | 587 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 |
| AnnaBridge | 171:3a7713b1edbc | 588 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) |
| AnnaBridge | 171:3a7713b1edbc | 589 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 171:3a7713b1edbc | 590 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 |
| AnnaBridge | 171:3a7713b1edbc | 591 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
| AnnaBridge | 171:3a7713b1edbc | 592 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
| AnnaBridge | 171:3a7713b1edbc | 593 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 171:3a7713b1edbc | 594 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 |
| AnnaBridge | 171:3a7713b1edbc | 595 | * @arg @ref LL_APB1_GRP1_PERIPH_USB |
| AnnaBridge | 171:3a7713b1edbc | 596 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 171:3a7713b1edbc | 597 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
| AnnaBridge | 171:3a7713b1edbc | 598 | * @arg @ref LL_APB1_GRP1_PERIPH_COMP |
| AnnaBridge | 171:3a7713b1edbc | 599 | * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*) |
| AnnaBridge | 171:3a7713b1edbc | 600 | * |
| AnnaBridge | 171:3a7713b1edbc | 601 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 602 | * @retval State of Periphs (1 or 0). |
| AnnaBridge | 171:3a7713b1edbc | 603 | */ |
| AnnaBridge | 171:3a7713b1edbc | 604 | __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 605 | { |
| AnnaBridge | 171:3a7713b1edbc | 606 | return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 607 | } |
| AnnaBridge | 171:3a7713b1edbc | 608 | |
| AnnaBridge | 171:3a7713b1edbc | 609 | /** |
| AnnaBridge | 171:3a7713b1edbc | 610 | * @brief Disable APB1 peripherals clock. |
| AnnaBridge | 171:3a7713b1edbc | 611 | * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 612 | * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 613 | * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 614 | * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 615 | * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 616 | * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 617 | * APB1ENR LCDEN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 618 | * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 619 | * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 620 | * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 621 | * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 622 | * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 623 | * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 624 | * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 625 | * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 626 | * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 627 | * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 628 | * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 629 | * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 630 | * APB1ENR COMPEN LL_APB1_GRP1_DisableClock |
| AnnaBridge | 171:3a7713b1edbc | 631 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 632 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 171:3a7713b1edbc | 633 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 |
| AnnaBridge | 171:3a7713b1edbc | 634 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 |
| AnnaBridge | 171:3a7713b1edbc | 635 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) |
| AnnaBridge | 171:3a7713b1edbc | 636 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
| AnnaBridge | 171:3a7713b1edbc | 637 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 |
| AnnaBridge | 171:3a7713b1edbc | 638 | * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) |
| AnnaBridge | 171:3a7713b1edbc | 639 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 171:3a7713b1edbc | 640 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 |
| AnnaBridge | 171:3a7713b1edbc | 641 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) |
| AnnaBridge | 171:3a7713b1edbc | 642 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 171:3a7713b1edbc | 643 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 |
| AnnaBridge | 171:3a7713b1edbc | 644 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
| AnnaBridge | 171:3a7713b1edbc | 645 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
| AnnaBridge | 171:3a7713b1edbc | 646 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 171:3a7713b1edbc | 647 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 |
| AnnaBridge | 171:3a7713b1edbc | 648 | * @arg @ref LL_APB1_GRP1_PERIPH_USB |
| AnnaBridge | 171:3a7713b1edbc | 649 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 171:3a7713b1edbc | 650 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
| AnnaBridge | 171:3a7713b1edbc | 651 | * @arg @ref LL_APB1_GRP1_PERIPH_COMP |
| AnnaBridge | 171:3a7713b1edbc | 652 | * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*) |
| AnnaBridge | 171:3a7713b1edbc | 653 | * |
| AnnaBridge | 171:3a7713b1edbc | 654 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 655 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 656 | */ |
| AnnaBridge | 171:3a7713b1edbc | 657 | __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 658 | { |
| AnnaBridge | 171:3a7713b1edbc | 659 | CLEAR_BIT(RCC->APB1ENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 660 | } |
| AnnaBridge | 171:3a7713b1edbc | 661 | |
| AnnaBridge | 171:3a7713b1edbc | 662 | /** |
| AnnaBridge | 171:3a7713b1edbc | 663 | * @brief Force APB1 peripherals reset. |
| AnnaBridge | 171:3a7713b1edbc | 664 | * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 665 | * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 666 | * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 667 | * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 668 | * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 669 | * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 670 | * APB1RSTR LCDRST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 671 | * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 672 | * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 673 | * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 674 | * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 675 | * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 676 | * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 677 | * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 678 | * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 679 | * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 680 | * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 681 | * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 682 | * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 683 | * APB1RSTR COMPRST LL_APB1_GRP1_ForceReset |
| AnnaBridge | 171:3a7713b1edbc | 684 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 685 | * @arg @ref LL_APB1_GRP1_PERIPH_ALL |
| AnnaBridge | 171:3a7713b1edbc | 686 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 171:3a7713b1edbc | 687 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 |
| AnnaBridge | 171:3a7713b1edbc | 688 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 |
| AnnaBridge | 171:3a7713b1edbc | 689 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) |
| AnnaBridge | 171:3a7713b1edbc | 690 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
| AnnaBridge | 171:3a7713b1edbc | 691 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 |
| AnnaBridge | 171:3a7713b1edbc | 692 | * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) |
| AnnaBridge | 171:3a7713b1edbc | 693 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 171:3a7713b1edbc | 694 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 |
| AnnaBridge | 171:3a7713b1edbc | 695 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) |
| AnnaBridge | 171:3a7713b1edbc | 696 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 171:3a7713b1edbc | 697 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 |
| AnnaBridge | 171:3a7713b1edbc | 698 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
| AnnaBridge | 171:3a7713b1edbc | 699 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
| AnnaBridge | 171:3a7713b1edbc | 700 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 171:3a7713b1edbc | 701 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 |
| AnnaBridge | 171:3a7713b1edbc | 702 | * @arg @ref LL_APB1_GRP1_PERIPH_USB |
| AnnaBridge | 171:3a7713b1edbc | 703 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 171:3a7713b1edbc | 704 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
| AnnaBridge | 171:3a7713b1edbc | 705 | * @arg @ref LL_APB1_GRP1_PERIPH_COMP |
| AnnaBridge | 171:3a7713b1edbc | 706 | * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*) |
| AnnaBridge | 171:3a7713b1edbc | 707 | * |
| AnnaBridge | 171:3a7713b1edbc | 708 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 709 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 710 | */ |
| AnnaBridge | 171:3a7713b1edbc | 711 | __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 712 | { |
| AnnaBridge | 171:3a7713b1edbc | 713 | SET_BIT(RCC->APB1RSTR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 714 | } |
| AnnaBridge | 171:3a7713b1edbc | 715 | |
| AnnaBridge | 171:3a7713b1edbc | 716 | /** |
| AnnaBridge | 171:3a7713b1edbc | 717 | * @brief Release APB1 peripherals reset. |
| AnnaBridge | 171:3a7713b1edbc | 718 | * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 719 | * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 720 | * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 721 | * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 722 | * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 723 | * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 724 | * APB1RSTR LCDRST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 725 | * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 726 | * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 727 | * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 728 | * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 729 | * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 730 | * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 731 | * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 732 | * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 733 | * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 734 | * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 735 | * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 736 | * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 737 | * APB1RSTR COMPRST LL_APB1_GRP1_ReleaseReset |
| AnnaBridge | 171:3a7713b1edbc | 738 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 739 | * @arg @ref LL_APB1_GRP1_PERIPH_ALL |
| AnnaBridge | 171:3a7713b1edbc | 740 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 171:3a7713b1edbc | 741 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 |
| AnnaBridge | 171:3a7713b1edbc | 742 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 |
| AnnaBridge | 171:3a7713b1edbc | 743 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) |
| AnnaBridge | 171:3a7713b1edbc | 744 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
| AnnaBridge | 171:3a7713b1edbc | 745 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 |
| AnnaBridge | 171:3a7713b1edbc | 746 | * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) |
| AnnaBridge | 171:3a7713b1edbc | 747 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 171:3a7713b1edbc | 748 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 |
| AnnaBridge | 171:3a7713b1edbc | 749 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) |
| AnnaBridge | 171:3a7713b1edbc | 750 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 171:3a7713b1edbc | 751 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 |
| AnnaBridge | 171:3a7713b1edbc | 752 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
| AnnaBridge | 171:3a7713b1edbc | 753 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
| AnnaBridge | 171:3a7713b1edbc | 754 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 171:3a7713b1edbc | 755 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 |
| AnnaBridge | 171:3a7713b1edbc | 756 | * @arg @ref LL_APB1_GRP1_PERIPH_USB |
| AnnaBridge | 171:3a7713b1edbc | 757 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 171:3a7713b1edbc | 758 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
| AnnaBridge | 171:3a7713b1edbc | 759 | * @arg @ref LL_APB1_GRP1_PERIPH_COMP |
| AnnaBridge | 171:3a7713b1edbc | 760 | * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*) |
| AnnaBridge | 171:3a7713b1edbc | 761 | * |
| AnnaBridge | 171:3a7713b1edbc | 762 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 763 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 764 | */ |
| AnnaBridge | 171:3a7713b1edbc | 765 | __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 766 | { |
| AnnaBridge | 171:3a7713b1edbc | 767 | CLEAR_BIT(RCC->APB1RSTR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 768 | } |
| AnnaBridge | 171:3a7713b1edbc | 769 | |
| AnnaBridge | 171:3a7713b1edbc | 770 | /** |
| AnnaBridge | 171:3a7713b1edbc | 771 | * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode. |
| AnnaBridge | 171:3a7713b1edbc | 772 | * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 773 | * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 774 | * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 775 | * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 776 | * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 777 | * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 778 | * APB1LPENR LCDLPEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 779 | * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 780 | * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 781 | * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 782 | * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 783 | * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 784 | * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 785 | * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 786 | * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 787 | * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 788 | * APB1LPENR USBLPEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 789 | * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 790 | * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 791 | * APB1LPENR COMPLPEN LL_APB1_GRP1_EnableClockSleep |
| AnnaBridge | 171:3a7713b1edbc | 792 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 793 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 171:3a7713b1edbc | 794 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 |
| AnnaBridge | 171:3a7713b1edbc | 795 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 |
| AnnaBridge | 171:3a7713b1edbc | 796 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) |
| AnnaBridge | 171:3a7713b1edbc | 797 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
| AnnaBridge | 171:3a7713b1edbc | 798 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 |
| AnnaBridge | 171:3a7713b1edbc | 799 | * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) |
| AnnaBridge | 171:3a7713b1edbc | 800 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 171:3a7713b1edbc | 801 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 |
| AnnaBridge | 171:3a7713b1edbc | 802 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) |
| AnnaBridge | 171:3a7713b1edbc | 803 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 171:3a7713b1edbc | 804 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 |
| AnnaBridge | 171:3a7713b1edbc | 805 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
| AnnaBridge | 171:3a7713b1edbc | 806 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
| AnnaBridge | 171:3a7713b1edbc | 807 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 171:3a7713b1edbc | 808 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 |
| AnnaBridge | 171:3a7713b1edbc | 809 | * @arg @ref LL_APB1_GRP1_PERIPH_USB |
| AnnaBridge | 171:3a7713b1edbc | 810 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 171:3a7713b1edbc | 811 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
| AnnaBridge | 171:3a7713b1edbc | 812 | * @arg @ref LL_APB1_GRP1_PERIPH_COMP |
| AnnaBridge | 171:3a7713b1edbc | 813 | * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*) |
| AnnaBridge | 171:3a7713b1edbc | 814 | * |
| AnnaBridge | 171:3a7713b1edbc | 815 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 816 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 817 | */ |
| AnnaBridge | 171:3a7713b1edbc | 818 | __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 819 | { |
| AnnaBridge | 171:3a7713b1edbc | 820 | __IO uint32_t tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 821 | SET_BIT(RCC->APB1LPENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 822 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 171:3a7713b1edbc | 823 | tmpreg = READ_BIT(RCC->APB1LPENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 824 | (void)tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 825 | } |
| AnnaBridge | 171:3a7713b1edbc | 826 | |
| AnnaBridge | 171:3a7713b1edbc | 827 | /** |
| AnnaBridge | 171:3a7713b1edbc | 828 | * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode. |
| AnnaBridge | 171:3a7713b1edbc | 829 | * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 830 | * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 831 | * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 832 | * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 833 | * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 834 | * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 835 | * APB1LPENR LCDLPEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 836 | * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 837 | * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 838 | * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 839 | * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 840 | * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 841 | * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 842 | * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 843 | * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 844 | * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 845 | * APB1LPENR USBLPEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 846 | * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 847 | * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 848 | * APB1LPENR COMPLPEN LL_APB1_GRP1_DisableClockSleep |
| AnnaBridge | 171:3a7713b1edbc | 849 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 850 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 171:3a7713b1edbc | 851 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 |
| AnnaBridge | 171:3a7713b1edbc | 852 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 |
| AnnaBridge | 171:3a7713b1edbc | 853 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) |
| AnnaBridge | 171:3a7713b1edbc | 854 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
| AnnaBridge | 171:3a7713b1edbc | 855 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 |
| AnnaBridge | 171:3a7713b1edbc | 856 | * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) |
| AnnaBridge | 171:3a7713b1edbc | 857 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 171:3a7713b1edbc | 858 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 |
| AnnaBridge | 171:3a7713b1edbc | 859 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) |
| AnnaBridge | 171:3a7713b1edbc | 860 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 171:3a7713b1edbc | 861 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 |
| AnnaBridge | 171:3a7713b1edbc | 862 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
| AnnaBridge | 171:3a7713b1edbc | 863 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
| AnnaBridge | 171:3a7713b1edbc | 864 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 171:3a7713b1edbc | 865 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 |
| AnnaBridge | 171:3a7713b1edbc | 866 | * @arg @ref LL_APB1_GRP1_PERIPH_USB |
| AnnaBridge | 171:3a7713b1edbc | 867 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 171:3a7713b1edbc | 868 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
| AnnaBridge | 171:3a7713b1edbc | 869 | * @arg @ref LL_APB1_GRP1_PERIPH_COMP |
| AnnaBridge | 171:3a7713b1edbc | 870 | * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*) |
| AnnaBridge | 171:3a7713b1edbc | 871 | * |
| AnnaBridge | 171:3a7713b1edbc | 872 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 873 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 874 | */ |
| AnnaBridge | 171:3a7713b1edbc | 875 | __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 876 | { |
| AnnaBridge | 171:3a7713b1edbc | 877 | CLEAR_BIT(RCC->APB1LPENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 878 | } |
| AnnaBridge | 171:3a7713b1edbc | 879 | |
| AnnaBridge | 171:3a7713b1edbc | 880 | /** |
| AnnaBridge | 171:3a7713b1edbc | 881 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 882 | */ |
| AnnaBridge | 171:3a7713b1edbc | 883 | |
| AnnaBridge | 171:3a7713b1edbc | 884 | /** @defgroup BUS_LL_EF_APB2 APB2 |
| AnnaBridge | 171:3a7713b1edbc | 885 | * @{ |
| AnnaBridge | 171:3a7713b1edbc | 886 | */ |
| AnnaBridge | 171:3a7713b1edbc | 887 | |
| AnnaBridge | 171:3a7713b1edbc | 888 | /** |
| AnnaBridge | 171:3a7713b1edbc | 889 | * @brief Enable APB2 peripherals clock. |
| AnnaBridge | 171:3a7713b1edbc | 890 | * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 891 | * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 892 | * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 893 | * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 894 | * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 895 | * APB2ENR SDIOEN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 896 | * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 897 | * APB2ENR USART1EN LL_APB2_GRP1_EnableClock |
| AnnaBridge | 171:3a7713b1edbc | 898 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 899 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 171:3a7713b1edbc | 900 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 |
| AnnaBridge | 171:3a7713b1edbc | 901 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 |
| AnnaBridge | 171:3a7713b1edbc | 902 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 |
| AnnaBridge | 171:3a7713b1edbc | 903 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| AnnaBridge | 171:3a7713b1edbc | 904 | * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) |
| AnnaBridge | 171:3a7713b1edbc | 905 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| AnnaBridge | 171:3a7713b1edbc | 906 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| AnnaBridge | 171:3a7713b1edbc | 907 | * |
| AnnaBridge | 171:3a7713b1edbc | 908 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 909 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 910 | */ |
| AnnaBridge | 171:3a7713b1edbc | 911 | __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 912 | { |
| AnnaBridge | 171:3a7713b1edbc | 913 | __IO uint32_t tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 914 | SET_BIT(RCC->APB2ENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 915 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 171:3a7713b1edbc | 916 | tmpreg = READ_BIT(RCC->APB2ENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 917 | (void)tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 918 | } |
| AnnaBridge | 171:3a7713b1edbc | 919 | |
| AnnaBridge | 171:3a7713b1edbc | 920 | /** |
| AnnaBridge | 171:3a7713b1edbc | 921 | * @brief Check if APB2 peripheral clock is enabled or not |
| AnnaBridge | 171:3a7713b1edbc | 922 | * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 923 | * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 924 | * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 925 | * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 926 | * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 927 | * APB2ENR SDIOEN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 928 | * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 171:3a7713b1edbc | 929 | * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock |
| AnnaBridge | 171:3a7713b1edbc | 930 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 931 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 171:3a7713b1edbc | 932 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 |
| AnnaBridge | 171:3a7713b1edbc | 933 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 |
| AnnaBridge | 171:3a7713b1edbc | 934 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 |
| AnnaBridge | 171:3a7713b1edbc | 935 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| AnnaBridge | 171:3a7713b1edbc | 936 | * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) |
| AnnaBridge | 171:3a7713b1edbc | 937 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| AnnaBridge | 171:3a7713b1edbc | 938 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| AnnaBridge | 171:3a7713b1edbc | 939 | * |
| AnnaBridge | 171:3a7713b1edbc | 940 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 941 | * @retval State of Periphs (1 or 0). |
| AnnaBridge | 171:3a7713b1edbc | 942 | */ |
| AnnaBridge | 171:3a7713b1edbc | 943 | __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 944 | { |
| AnnaBridge | 171:3a7713b1edbc | 945 | return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 946 | } |
| AnnaBridge | 171:3a7713b1edbc | 947 | |
| AnnaBridge | 171:3a7713b1edbc | 948 | /** |
| AnnaBridge | 171:3a7713b1edbc | 949 | * @brief Disable APB2 peripherals clock. |
| AnnaBridge | 171:3a7713b1edbc | 950 | * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 951 | * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 952 | * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 953 | * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 954 | * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 955 | * APB2ENR SDIOEN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 956 | * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 171:3a7713b1edbc | 957 | * APB2ENR USART1EN LL_APB2_GRP1_DisableClock |
| AnnaBridge | 171:3a7713b1edbc | 958 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 959 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 171:3a7713b1edbc | 960 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 |
| AnnaBridge | 171:3a7713b1edbc | 961 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 |
| AnnaBridge | 171:3a7713b1edbc | 962 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 |
| AnnaBridge | 171:3a7713b1edbc | 963 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| AnnaBridge | 171:3a7713b1edbc | 964 | * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) |
| AnnaBridge | 171:3a7713b1edbc | 965 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| AnnaBridge | 171:3a7713b1edbc | 966 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| AnnaBridge | 171:3a7713b1edbc | 967 | * |
| AnnaBridge | 171:3a7713b1edbc | 968 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 969 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 970 | */ |
| AnnaBridge | 171:3a7713b1edbc | 971 | __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 972 | { |
| AnnaBridge | 171:3a7713b1edbc | 973 | CLEAR_BIT(RCC->APB2ENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 974 | } |
| AnnaBridge | 171:3a7713b1edbc | 975 | |
| AnnaBridge | 171:3a7713b1edbc | 976 | /** |
| AnnaBridge | 171:3a7713b1edbc | 977 | * @brief Force APB2 peripherals reset. |
| AnnaBridge | 171:3a7713b1edbc | 978 | * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 979 | * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 980 | * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 981 | * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 982 | * APB2RSTR ADC1RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 983 | * APB2RSTR SDIORST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 984 | * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 171:3a7713b1edbc | 985 | * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset |
| AnnaBridge | 171:3a7713b1edbc | 986 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 987 | * @arg @ref LL_APB2_GRP1_PERIPH_ALL |
| AnnaBridge | 171:3a7713b1edbc | 988 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 171:3a7713b1edbc | 989 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 |
| AnnaBridge | 171:3a7713b1edbc | 990 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 |
| AnnaBridge | 171:3a7713b1edbc | 991 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 |
| AnnaBridge | 171:3a7713b1edbc | 992 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| AnnaBridge | 171:3a7713b1edbc | 993 | * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) |
| AnnaBridge | 171:3a7713b1edbc | 994 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| AnnaBridge | 171:3a7713b1edbc | 995 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| AnnaBridge | 171:3a7713b1edbc | 996 | * |
| AnnaBridge | 171:3a7713b1edbc | 997 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 998 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 999 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1000 | __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 1001 | { |
| AnnaBridge | 171:3a7713b1edbc | 1002 | SET_BIT(RCC->APB2RSTR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 1003 | } |
| AnnaBridge | 171:3a7713b1edbc | 1004 | |
| AnnaBridge | 171:3a7713b1edbc | 1005 | /** |
| AnnaBridge | 171:3a7713b1edbc | 1006 | * @brief Release APB2 peripherals reset. |
| AnnaBridge | 171:3a7713b1edbc | 1007 | * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1008 | * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1009 | * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1010 | * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1011 | * APB2RSTR ADC1RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1012 | * APB2RSTR SDIORST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1013 | * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 171:3a7713b1edbc | 1014 | * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset |
| AnnaBridge | 171:3a7713b1edbc | 1015 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 1016 | * @arg @ref LL_APB2_GRP1_PERIPH_ALL |
| AnnaBridge | 171:3a7713b1edbc | 1017 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 171:3a7713b1edbc | 1018 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 |
| AnnaBridge | 171:3a7713b1edbc | 1019 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 |
| AnnaBridge | 171:3a7713b1edbc | 1020 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 |
| AnnaBridge | 171:3a7713b1edbc | 1021 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| AnnaBridge | 171:3a7713b1edbc | 1022 | * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) |
| AnnaBridge | 171:3a7713b1edbc | 1023 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| AnnaBridge | 171:3a7713b1edbc | 1024 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| AnnaBridge | 171:3a7713b1edbc | 1025 | * |
| AnnaBridge | 171:3a7713b1edbc | 1026 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 1027 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 1028 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1029 | __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 1030 | { |
| AnnaBridge | 171:3a7713b1edbc | 1031 | CLEAR_BIT(RCC->APB2RSTR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 1032 | } |
| AnnaBridge | 171:3a7713b1edbc | 1033 | |
| AnnaBridge | 171:3a7713b1edbc | 1034 | /** |
| AnnaBridge | 171:3a7713b1edbc | 1035 | * @brief Enable APB2 peripherals clock during Low Power (Sleep) mode. |
| AnnaBridge | 171:3a7713b1edbc | 1036 | * @rmtoll APB2LPENR SYSCFGLPEN LL_APB2_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 1037 | * APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 1038 | * APB2LPENR TIM10LPEN LL_APB2_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 1039 | * APB2LPENR TIM11LPEN LL_APB2_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 1040 | * APB2LPENR ADC1LPEN LL_APB2_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 1041 | * APB2LPENR SDIOLPEN LL_APB2_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 1042 | * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 1043 | * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockSleep |
| AnnaBridge | 171:3a7713b1edbc | 1044 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 1045 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 171:3a7713b1edbc | 1046 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 |
| AnnaBridge | 171:3a7713b1edbc | 1047 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 |
| AnnaBridge | 171:3a7713b1edbc | 1048 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 |
| AnnaBridge | 171:3a7713b1edbc | 1049 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| AnnaBridge | 171:3a7713b1edbc | 1050 | * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) |
| AnnaBridge | 171:3a7713b1edbc | 1051 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| AnnaBridge | 171:3a7713b1edbc | 1052 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| AnnaBridge | 171:3a7713b1edbc | 1053 | * |
| AnnaBridge | 171:3a7713b1edbc | 1054 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 1055 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 1056 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1057 | __STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 1058 | { |
| AnnaBridge | 171:3a7713b1edbc | 1059 | __IO uint32_t tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 1060 | SET_BIT(RCC->APB2LPENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 1061 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 171:3a7713b1edbc | 1062 | tmpreg = READ_BIT(RCC->APB2LPENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 1063 | (void)tmpreg; |
| AnnaBridge | 171:3a7713b1edbc | 1064 | } |
| AnnaBridge | 171:3a7713b1edbc | 1065 | |
| AnnaBridge | 171:3a7713b1edbc | 1066 | /** |
| AnnaBridge | 171:3a7713b1edbc | 1067 | * @brief Disable APB2 peripherals clock during Low Power (Sleep) mode. |
| AnnaBridge | 171:3a7713b1edbc | 1068 | * @rmtoll APB2LPENR SYSCFGLPEN LL_APB2_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 1069 | * APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 1070 | * APB2LPENR TIM10LPEN LL_APB2_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 1071 | * APB2LPENR TIM11LPEN LL_APB2_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 1072 | * APB2LPENR ADC1LPEN LL_APB2_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 1073 | * APB2LPENR SDIOLPEN LL_APB2_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 1074 | * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockSleep\n |
| AnnaBridge | 171:3a7713b1edbc | 1075 | * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockSleep |
| AnnaBridge | 171:3a7713b1edbc | 1076 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 171:3a7713b1edbc | 1077 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 171:3a7713b1edbc | 1078 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 |
| AnnaBridge | 171:3a7713b1edbc | 1079 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 |
| AnnaBridge | 171:3a7713b1edbc | 1080 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 |
| AnnaBridge | 171:3a7713b1edbc | 1081 | * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 |
| AnnaBridge | 171:3a7713b1edbc | 1082 | * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*) |
| AnnaBridge | 171:3a7713b1edbc | 1083 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| AnnaBridge | 171:3a7713b1edbc | 1084 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| AnnaBridge | 171:3a7713b1edbc | 1085 | * |
| AnnaBridge | 171:3a7713b1edbc | 1086 | * (*) value not defined in all devices. |
| AnnaBridge | 171:3a7713b1edbc | 1087 | * @retval None |
| AnnaBridge | 171:3a7713b1edbc | 1088 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1089 | __STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs) |
| AnnaBridge | 171:3a7713b1edbc | 1090 | { |
| AnnaBridge | 171:3a7713b1edbc | 1091 | CLEAR_BIT(RCC->APB2LPENR, Periphs); |
| AnnaBridge | 171:3a7713b1edbc | 1092 | } |
| AnnaBridge | 171:3a7713b1edbc | 1093 | |
| AnnaBridge | 171:3a7713b1edbc | 1094 | /** |
| AnnaBridge | 171:3a7713b1edbc | 1095 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 1096 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1097 | |
| AnnaBridge | 171:3a7713b1edbc | 1098 | |
| AnnaBridge | 171:3a7713b1edbc | 1099 | /** |
| AnnaBridge | 171:3a7713b1edbc | 1100 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 1101 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1102 | |
| AnnaBridge | 171:3a7713b1edbc | 1103 | /** |
| AnnaBridge | 171:3a7713b1edbc | 1104 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 1105 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1106 | |
| AnnaBridge | 171:3a7713b1edbc | 1107 | #endif /* defined(RCC) */ |
| AnnaBridge | 171:3a7713b1edbc | 1108 | |
| AnnaBridge | 171:3a7713b1edbc | 1109 | /** |
| AnnaBridge | 171:3a7713b1edbc | 1110 | * @} |
| AnnaBridge | 171:3a7713b1edbc | 1111 | */ |
| AnnaBridge | 171:3a7713b1edbc | 1112 | |
| AnnaBridge | 171:3a7713b1edbc | 1113 | #ifdef __cplusplus |
| AnnaBridge | 171:3a7713b1edbc | 1114 | } |
| AnnaBridge | 171:3a7713b1edbc | 1115 | #endif |
| AnnaBridge | 171:3a7713b1edbc | 1116 | |
| AnnaBridge | 171:3a7713b1edbc | 1117 | #endif /* __STM32L1xx_LL_BUS_H */ |
| AnnaBridge | 171:3a7713b1edbc | 1118 | |
| AnnaBridge | 171:3a7713b1edbc | 1119 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
