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TARGET_MOTE_L152RC/TOOLCHAIN_IAR/stm32l1xx_hal_flash_ex.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file stm32l1xx_hal_flash_ex.h
AnnaBridge 171:3a7713b1edbc 4 * @author MCD Application Team
AnnaBridge 171:3a7713b1edbc 5 * @brief Header file of Flash HAL Extended module.
AnnaBridge 171:3a7713b1edbc 6 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 7 * @attention
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 12 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 14 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 17 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 171:3a7713b1edbc 19 * may be used to endorse or promote products derived from this software
AnnaBridge 171:3a7713b1edbc 20 * without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 171:3a7713b1edbc 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 171:3a7713b1edbc 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 171:3a7713b1edbc 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 171:3a7713b1edbc 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 171:3a7713b1edbc 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 171:3a7713b1edbc 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 171:3a7713b1edbc 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 32 *
AnnaBridge 171:3a7713b1edbc 33 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 34 */
AnnaBridge 171:3a7713b1edbc 35
AnnaBridge 171:3a7713b1edbc 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 171:3a7713b1edbc 37 #ifndef __STM32L1xx_HAL_FLASH_EX_H
AnnaBridge 171:3a7713b1edbc 38 #define __STM32L1xx_HAL_FLASH_EX_H
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 41 extern "C" {
AnnaBridge 171:3a7713b1edbc 42 #endif
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 /* Includes ------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 45 #include "stm32l1xx_hal_def.h"
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /** @addtogroup STM32L1xx_HAL_Driver
AnnaBridge 171:3a7713b1edbc 48 * @{
AnnaBridge 171:3a7713b1edbc 49 */
AnnaBridge 171:3a7713b1edbc 50
AnnaBridge 171:3a7713b1edbc 51 /** @addtogroup FLASHEx
AnnaBridge 171:3a7713b1edbc 52 * @{
AnnaBridge 171:3a7713b1edbc 53 */
AnnaBridge 171:3a7713b1edbc 54
AnnaBridge 171:3a7713b1edbc 55 /** @addtogroup FLASHEx_Private_Constants
AnnaBridge 171:3a7713b1edbc 56 * @{
AnnaBridge 171:3a7713b1edbc 57 */
AnnaBridge 171:3a7713b1edbc 58 #if defined(FLASH_SR_RDERR) && defined(FLASH_SR_OPTVERRUSR)
AnnaBridge 171:3a7713b1edbc 59
AnnaBridge 171:3a7713b1edbc 60 #define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \
AnnaBridge 171:3a7713b1edbc 61 FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \
AnnaBridge 171:3a7713b1edbc 62 FLASH_FLAG_OPTVERRUSR | FLASH_FLAG_RDERR)
AnnaBridge 171:3a7713b1edbc 63
AnnaBridge 171:3a7713b1edbc 64 #elif defined(FLASH_SR_RDERR)
AnnaBridge 171:3a7713b1edbc 65
AnnaBridge 171:3a7713b1edbc 66 #define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \
AnnaBridge 171:3a7713b1edbc 67 FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \
AnnaBridge 171:3a7713b1edbc 68 FLASH_FLAG_RDERR)
AnnaBridge 171:3a7713b1edbc 69
AnnaBridge 171:3a7713b1edbc 70 #elif defined(FLASH_SR_OPTVERRUSR)
AnnaBridge 171:3a7713b1edbc 71
AnnaBridge 171:3a7713b1edbc 72 #define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \
AnnaBridge 171:3a7713b1edbc 73 FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \
AnnaBridge 171:3a7713b1edbc 74 FLASH_FLAG_OPTVERRUSR)
AnnaBridge 171:3a7713b1edbc 75
AnnaBridge 171:3a7713b1edbc 76 #else
AnnaBridge 171:3a7713b1edbc 77
AnnaBridge 171:3a7713b1edbc 78 #define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \
AnnaBridge 171:3a7713b1edbc 79 FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR)
AnnaBridge 171:3a7713b1edbc 80
AnnaBridge 171:3a7713b1edbc 81 #endif /* FLASH_SR_RDERR & FLASH_SR_OPTVERRUSR */
AnnaBridge 171:3a7713b1edbc 82
AnnaBridge 171:3a7713b1edbc 83 #if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L100xBA) \
AnnaBridge 171:3a7713b1edbc 84 || defined(STM32L151xBA) || defined(STM32L152xBA)
AnnaBridge 171:3a7713b1edbc 85
AnnaBridge 171:3a7713b1edbc 86 /******* Devices with FLASH 128K *******/
AnnaBridge 171:3a7713b1edbc 87 #define FLASH_NBPAGES_MAX 512U /* 512 pages from page 0 to page 511U */
AnnaBridge 171:3a7713b1edbc 88
AnnaBridge 171:3a7713b1edbc 89 #elif defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \
AnnaBridge 171:3a7713b1edbc 90 || defined(STM32L151xCA) || defined(STM32L152xCA) || defined(STM32L162xCA)
AnnaBridge 171:3a7713b1edbc 91
AnnaBridge 171:3a7713b1edbc 92 /******* Devices with FLASH 256K *******/
AnnaBridge 171:3a7713b1edbc 93 #define FLASH_NBPAGES_MAX 1025U /* 1025 pages from page 0 to page 1024U */
AnnaBridge 171:3a7713b1edbc 94
AnnaBridge 171:3a7713b1edbc 95 #elif defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
AnnaBridge 171:3a7713b1edbc 96 || defined(STM32L162xD) || defined(STM32L162xDX)
AnnaBridge 171:3a7713b1edbc 97
AnnaBridge 171:3a7713b1edbc 98 /******* Devices with FLASH 384K *******/
AnnaBridge 171:3a7713b1edbc 99 #define FLASH_NBPAGES_MAX 1536U /* 1536 pages from page 0 to page 1535U */
AnnaBridge 171:3a7713b1edbc 100
AnnaBridge 171:3a7713b1edbc 101 #elif defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)
AnnaBridge 171:3a7713b1edbc 102
AnnaBridge 171:3a7713b1edbc 103 /******* Devices with FLASH 512K *******/
AnnaBridge 171:3a7713b1edbc 104 #define FLASH_NBPAGES_MAX 2048U /* 2048 pages from page 0 to page 2047U */
AnnaBridge 171:3a7713b1edbc 105
AnnaBridge 171:3a7713b1edbc 106 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA */
AnnaBridge 171:3a7713b1edbc 107
AnnaBridge 171:3a7713b1edbc 108 #define WRP_MASK_LOW (0x0000FFFFU)
AnnaBridge 171:3a7713b1edbc 109 #define WRP_MASK_HIGH (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 110
AnnaBridge 171:3a7713b1edbc 111 /**
AnnaBridge 171:3a7713b1edbc 112 * @}
AnnaBridge 171:3a7713b1edbc 113 */
AnnaBridge 171:3a7713b1edbc 114
AnnaBridge 171:3a7713b1edbc 115 /** @addtogroup FLASHEx_Private_Macros
AnnaBridge 171:3a7713b1edbc 116 * @{
AnnaBridge 171:3a7713b1edbc 117 */
AnnaBridge 171:3a7713b1edbc 118
AnnaBridge 171:3a7713b1edbc 119 #define IS_FLASH_TYPEERASE(__VALUE__) (((__VALUE__) == FLASH_TYPEERASE_PAGES))
AnnaBridge 171:3a7713b1edbc 120
AnnaBridge 171:3a7713b1edbc 121 #define IS_OPTIONBYTE(__VALUE__) (((__VALUE__) <= (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR)))
AnnaBridge 171:3a7713b1edbc 122
AnnaBridge 171:3a7713b1edbc 123 #define IS_WRPSTATE(__VALUE__) (((__VALUE__) == OB_WRPSTATE_DISABLE) || \
AnnaBridge 171:3a7713b1edbc 124 ((__VALUE__) == OB_WRPSTATE_ENABLE))
AnnaBridge 171:3a7713b1edbc 125
AnnaBridge 171:3a7713b1edbc 126 #define IS_OB_WRP(__PAGE__) (((__PAGE__) != 0x0000000U))
AnnaBridge 171:3a7713b1edbc 127
AnnaBridge 171:3a7713b1edbc 128 #define IS_OB_RDP(__LEVEL__) (((__LEVEL__) == OB_RDP_LEVEL_0) ||\
AnnaBridge 171:3a7713b1edbc 129 ((__LEVEL__) == OB_RDP_LEVEL_1) ||\
AnnaBridge 171:3a7713b1edbc 130 ((__LEVEL__) == OB_RDP_LEVEL_2))
AnnaBridge 171:3a7713b1edbc 131
AnnaBridge 171:3a7713b1edbc 132 #define IS_OB_BOR_LEVEL(__LEVEL__) (((__LEVEL__) == OB_BOR_OFF) || \
AnnaBridge 171:3a7713b1edbc 133 ((__LEVEL__) == OB_BOR_LEVEL1) || \
AnnaBridge 171:3a7713b1edbc 134 ((__LEVEL__) == OB_BOR_LEVEL2) || \
AnnaBridge 171:3a7713b1edbc 135 ((__LEVEL__) == OB_BOR_LEVEL3) || \
AnnaBridge 171:3a7713b1edbc 136 ((__LEVEL__) == OB_BOR_LEVEL4) || \
AnnaBridge 171:3a7713b1edbc 137 ((__LEVEL__) == OB_BOR_LEVEL5))
AnnaBridge 171:3a7713b1edbc 138
AnnaBridge 171:3a7713b1edbc 139 #define IS_OB_IWDG_SOURCE(__SOURCE__) (((__SOURCE__) == OB_IWDG_SW) || ((__SOURCE__) == OB_IWDG_HW))
AnnaBridge 171:3a7713b1edbc 140
AnnaBridge 171:3a7713b1edbc 141 #define IS_OB_STOP_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STOP_NORST) || ((__SOURCE__) == OB_STOP_RST))
AnnaBridge 171:3a7713b1edbc 142
AnnaBridge 171:3a7713b1edbc 143 #define IS_OB_STDBY_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STDBY_NORST) || ((__SOURCE__) == OB_STDBY_RST))
AnnaBridge 171:3a7713b1edbc 144
AnnaBridge 171:3a7713b1edbc 145 #if defined(FLASH_OBR_SPRMOD) && defined(FLASH_OBR_nRST_BFB2)
AnnaBridge 171:3a7713b1edbc 146
AnnaBridge 171:3a7713b1edbc 147 #define IS_OBEX(__VALUE__) (((__VALUE__) == OPTIONBYTE_PCROP) || ((__VALUE__) == OPTIONBYTE_BOOTCONFIG))
AnnaBridge 171:3a7713b1edbc 148
AnnaBridge 171:3a7713b1edbc 149 #elif defined(FLASH_OBR_SPRMOD) && !defined(FLASH_OBR_nRST_BFB2)
AnnaBridge 171:3a7713b1edbc 150
AnnaBridge 171:3a7713b1edbc 151 #define IS_OBEX(__VALUE__) ((__VALUE__) == OPTIONBYTE_PCROP)
AnnaBridge 171:3a7713b1edbc 152
AnnaBridge 171:3a7713b1edbc 153 #elif !defined(FLASH_OBR_SPRMOD) && defined(FLASH_OBR_nRST_BFB2)
AnnaBridge 171:3a7713b1edbc 154
AnnaBridge 171:3a7713b1edbc 155 #define IS_OBEX(__VALUE__) ((__VALUE__) == OPTIONBYTE_BOOTCONFIG)
AnnaBridge 171:3a7713b1edbc 156
AnnaBridge 171:3a7713b1edbc 157 #endif /* FLASH_OBR_SPRMOD && FLASH_OBR_nRST_BFB2 */
AnnaBridge 171:3a7713b1edbc 158
AnnaBridge 171:3a7713b1edbc 159 #if defined(FLASH_OBR_SPRMOD)
AnnaBridge 171:3a7713b1edbc 160
AnnaBridge 171:3a7713b1edbc 161 #define IS_PCROPSTATE(__VALUE__) (((__VALUE__) == OB_PCROP_STATE_DISABLE) || \
AnnaBridge 171:3a7713b1edbc 162 ((__VALUE__) == OB_PCROP_STATE_ENABLE))
AnnaBridge 171:3a7713b1edbc 163
AnnaBridge 171:3a7713b1edbc 164 #define IS_OB_PCROP(__PAGE__) (((__PAGE__) != 0x0000000U))
AnnaBridge 171:3a7713b1edbc 165 #endif /* FLASH_OBR_SPRMOD */
AnnaBridge 171:3a7713b1edbc 166
AnnaBridge 171:3a7713b1edbc 167 #if defined(FLASH_OBR_nRST_BFB2)
AnnaBridge 171:3a7713b1edbc 168
AnnaBridge 171:3a7713b1edbc 169 #define IS_OB_BOOT_BANK(__BANK__) (((__BANK__) == OB_BOOT_BANK2) || ((__BANK__) == OB_BOOT_BANK1))
AnnaBridge 171:3a7713b1edbc 170
AnnaBridge 171:3a7713b1edbc 171 #endif /* FLASH_OBR_nRST_BFB2 */
AnnaBridge 171:3a7713b1edbc 172
AnnaBridge 171:3a7713b1edbc 173 #define IS_TYPEERASEDATA(__VALUE__) (((__VALUE__) == FLASH_TYPEERASEDATA_BYTE) || \
AnnaBridge 171:3a7713b1edbc 174 ((__VALUE__) == FLASH_TYPEERASEDATA_HALFWORD) || \
AnnaBridge 171:3a7713b1edbc 175 ((__VALUE__) == FLASH_TYPEERASEDATA_WORD))
AnnaBridge 171:3a7713b1edbc 176 #define IS_TYPEPROGRAMDATA(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAMDATA_BYTE) || \
AnnaBridge 171:3a7713b1edbc 177 ((__VALUE__) == FLASH_TYPEPROGRAMDATA_HALFWORD) || \
AnnaBridge 171:3a7713b1edbc 178 ((__VALUE__) == FLASH_TYPEPROGRAMDATA_WORD) || \
AnnaBridge 171:3a7713b1edbc 179 ((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTBYTE) || \
AnnaBridge 171:3a7713b1edbc 180 ((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTHALFWORD) || \
AnnaBridge 171:3a7713b1edbc 181 ((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTWORD))
AnnaBridge 171:3a7713b1edbc 182
AnnaBridge 171:3a7713b1edbc 183
AnnaBridge 171:3a7713b1edbc 184 /** @defgroup FLASHEx_Address FLASHEx Address
AnnaBridge 171:3a7713b1edbc 185 * @{
AnnaBridge 171:3a7713b1edbc 186 */
AnnaBridge 171:3a7713b1edbc 187
AnnaBridge 171:3a7713b1edbc 188 #define IS_FLASH_DATA_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_EEPROM_BASE) && ((__ADDRESS__) <= FLASH_EEPROM_END))
AnnaBridge 171:3a7713b1edbc 189
AnnaBridge 171:3a7713b1edbc 190 #if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L100xBA) \
AnnaBridge 171:3a7713b1edbc 191 || defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L100xC) || defined(STM32L151xC) \
AnnaBridge 171:3a7713b1edbc 192 || defined(STM32L152xC) || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L152xCA) \
AnnaBridge 171:3a7713b1edbc 193 || defined(STM32L162xCA)
AnnaBridge 171:3a7713b1edbc 194
AnnaBridge 171:3a7713b1edbc 195 #define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_END))
AnnaBridge 171:3a7713b1edbc 196
AnnaBridge 171:3a7713b1edbc 197 #else /*STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
AnnaBridge 171:3a7713b1edbc 198
AnnaBridge 171:3a7713b1edbc 199 #define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_BANK2_END))
AnnaBridge 171:3a7713b1edbc 200 #define IS_FLASH_PROGRAM_BANK1_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_BANK1_END))
AnnaBridge 171:3a7713b1edbc 201 #define IS_FLASH_PROGRAM_BANK2_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BANK2_BASE) && ((__ADDRESS__) <= FLASH_BANK2_END))
AnnaBridge 171:3a7713b1edbc 202
AnnaBridge 171:3a7713b1edbc 203 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || (...) || STM32L151xCA || STM32L152xCA || STM32L162xCA */
AnnaBridge 171:3a7713b1edbc 204
AnnaBridge 171:3a7713b1edbc 205 #define IS_NBPAGES(__PAGES__) (((__PAGES__) >= 1U) && ((__PAGES__) <= FLASH_NBPAGES_MAX))
AnnaBridge 171:3a7713b1edbc 206
AnnaBridge 171:3a7713b1edbc 207 /**
AnnaBridge 171:3a7713b1edbc 208 * @}
AnnaBridge 171:3a7713b1edbc 209 */
AnnaBridge 171:3a7713b1edbc 210
AnnaBridge 171:3a7713b1edbc 211 /**
AnnaBridge 171:3a7713b1edbc 212 * @}
AnnaBridge 171:3a7713b1edbc 213 */
AnnaBridge 171:3a7713b1edbc 214 /* Exported types ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 215
AnnaBridge 171:3a7713b1edbc 216 /** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
AnnaBridge 171:3a7713b1edbc 217 * @{
AnnaBridge 171:3a7713b1edbc 218 */
AnnaBridge 171:3a7713b1edbc 219
AnnaBridge 171:3a7713b1edbc 220 /**
AnnaBridge 171:3a7713b1edbc 221 * @brief FLASH Erase structure definition
AnnaBridge 171:3a7713b1edbc 222 */
AnnaBridge 171:3a7713b1edbc 223 typedef struct
AnnaBridge 171:3a7713b1edbc 224 {
AnnaBridge 171:3a7713b1edbc 225 uint32_t TypeErase; /*!< TypeErase: Page Erase only.
AnnaBridge 171:3a7713b1edbc 226 This parameter can be a value of @ref FLASHEx_Type_Erase */
AnnaBridge 171:3a7713b1edbc 227
AnnaBridge 171:3a7713b1edbc 228 uint32_t PageAddress; /*!< PageAddress: Initial FLASH address to be erased
AnnaBridge 171:3a7713b1edbc 229 This parameter must be a value belonging to FLASH Programm address (depending on the devices) */
AnnaBridge 171:3a7713b1edbc 230
AnnaBridge 171:3a7713b1edbc 231 uint32_t NbPages; /*!< NbPages: Number of pages to be erased.
AnnaBridge 171:3a7713b1edbc 232 This parameter must be a value between 1 and (max number of pages - value of Initial page)*/
AnnaBridge 171:3a7713b1edbc 233
AnnaBridge 171:3a7713b1edbc 234 } FLASH_EraseInitTypeDef;
AnnaBridge 171:3a7713b1edbc 235
AnnaBridge 171:3a7713b1edbc 236 /**
AnnaBridge 171:3a7713b1edbc 237 * @brief FLASH Option Bytes PROGRAM structure definition
AnnaBridge 171:3a7713b1edbc 238 */
AnnaBridge 171:3a7713b1edbc 239 typedef struct
AnnaBridge 171:3a7713b1edbc 240 {
AnnaBridge 171:3a7713b1edbc 241 uint32_t OptionType; /*!< OptionType: Option byte to be configured.
AnnaBridge 171:3a7713b1edbc 242 This parameter can be a value of @ref FLASHEx_Option_Type */
AnnaBridge 171:3a7713b1edbc 243
AnnaBridge 171:3a7713b1edbc 244 uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
AnnaBridge 171:3a7713b1edbc 245 This parameter can be a value of @ref FLASHEx_WRP_State */
AnnaBridge 171:3a7713b1edbc 246
AnnaBridge 171:3a7713b1edbc 247 uint32_t WRPSector0To31; /*!< WRPSector0To31: specifies the sector(s) which are write protected between Sector 0 to 31
AnnaBridge 171:3a7713b1edbc 248 This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection1 */
AnnaBridge 171:3a7713b1edbc 249
AnnaBridge 171:3a7713b1edbc 250 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \
AnnaBridge 171:3a7713b1edbc 251 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \
AnnaBridge 171:3a7713b1edbc 252 || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \
AnnaBridge 171:3a7713b1edbc 253 || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)
AnnaBridge 171:3a7713b1edbc 254 uint32_t WRPSector32To63; /*!< WRPSector32To63: specifies the sector(s) which are write protected between Sector 32 to 63
AnnaBridge 171:3a7713b1edbc 255 This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection2 */
AnnaBridge 171:3a7713b1edbc 256 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */
AnnaBridge 171:3a7713b1edbc 257
AnnaBridge 171:3a7713b1edbc 258 #if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
AnnaBridge 171:3a7713b1edbc 259 || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \
AnnaBridge 171:3a7713b1edbc 260 || defined(STM32L162xE)
AnnaBridge 171:3a7713b1edbc 261 uint32_t WRPSector64To95; /*!< WRPSector64to95: specifies the sector(s) which are write protected between Sector 64 to 95
AnnaBridge 171:3a7713b1edbc 262 This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection3 */
AnnaBridge 171:3a7713b1edbc 263 #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
AnnaBridge 171:3a7713b1edbc 264
AnnaBridge 171:3a7713b1edbc 265 #if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \
AnnaBridge 171:3a7713b1edbc 266 || defined(STM32L152xDX) || defined(STM32L162xDX)
AnnaBridge 171:3a7713b1edbc 267 uint32_t WRPSector96To127; /*!< WRPSector96To127: specifies the sector(s) which are write protected between Sector 96 to 127 or
AnnaBridge 171:3a7713b1edbc 268 Sectors 96 to 111 for STM32L1xxxDX devices.
AnnaBridge 171:3a7713b1edbc 269 This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection4 */
AnnaBridge 171:3a7713b1edbc 270 #endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */
AnnaBridge 171:3a7713b1edbc 271
AnnaBridge 171:3a7713b1edbc 272 uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level.
AnnaBridge 171:3a7713b1edbc 273 This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
AnnaBridge 171:3a7713b1edbc 274
AnnaBridge 171:3a7713b1edbc 275 uint8_t BORLevel; /*!< BORLevel: Set the BOR Level.
AnnaBridge 171:3a7713b1edbc 276 This parameter can be a value of @ref FLASHEx_Option_Bytes_BOR_Level */
AnnaBridge 171:3a7713b1edbc 277
AnnaBridge 171:3a7713b1edbc 278 uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
AnnaBridge 171:3a7713b1edbc 279 This parameter can be a combination of @ref FLASHEx_Option_Bytes_IWatchdog,
AnnaBridge 171:3a7713b1edbc 280 @ref FLASHEx_Option_Bytes_nRST_STOP and @ref FLASHEx_Option_Bytes_nRST_STDBY*/
AnnaBridge 171:3a7713b1edbc 281 } FLASH_OBProgramInitTypeDef;
AnnaBridge 171:3a7713b1edbc 282
AnnaBridge 171:3a7713b1edbc 283 #if defined(FLASH_OBR_SPRMOD) || defined(FLASH_OBR_nRST_BFB2)
AnnaBridge 171:3a7713b1edbc 284 /**
AnnaBridge 171:3a7713b1edbc 285 * @brief FLASH Advanced Option Bytes Program structure definition
AnnaBridge 171:3a7713b1edbc 286 */
AnnaBridge 171:3a7713b1edbc 287 typedef struct
AnnaBridge 171:3a7713b1edbc 288 {
AnnaBridge 171:3a7713b1edbc 289 uint32_t OptionType; /*!< OptionType: Option byte to be configured for extension .
AnnaBridge 171:3a7713b1edbc 290 This parameter can be a value of @ref FLASHEx_OptionAdv_Type */
AnnaBridge 171:3a7713b1edbc 291
AnnaBridge 171:3a7713b1edbc 292 #if defined(FLASH_OBR_SPRMOD)
AnnaBridge 171:3a7713b1edbc 293 uint32_t PCROPState; /*!< PCROPState: PCROP activation or deactivation.
AnnaBridge 171:3a7713b1edbc 294 This parameter can be a value of @ref FLASHEx_PCROP_State */
AnnaBridge 171:3a7713b1edbc 295
AnnaBridge 171:3a7713b1edbc 296 uint32_t PCROPSector0To31; /*!< PCROPSector0To31: specifies the sector(s) set for PCROP
AnnaBridge 171:3a7713b1edbc 297 This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection1 */
AnnaBridge 171:3a7713b1edbc 298
AnnaBridge 171:3a7713b1edbc 299 #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)
AnnaBridge 171:3a7713b1edbc 300 uint32_t PCROPSector32To63; /*!< PCROPSector32To63: specifies the sector(s) set for PCROP
AnnaBridge 171:3a7713b1edbc 301 This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 */
AnnaBridge 171:3a7713b1edbc 302 #endif /* STM32L151xC || STM32L152xC || STM32L162xC */
AnnaBridge 171:3a7713b1edbc 303 #endif /* FLASH_OBR_SPRMOD */
AnnaBridge 171:3a7713b1edbc 304
AnnaBridge 171:3a7713b1edbc 305 #if defined(FLASH_OBR_nRST_BFB2)
AnnaBridge 171:3a7713b1edbc 306 uint16_t BootConfig; /*!< BootConfig: specifies Option bytes for boot config
AnnaBridge 171:3a7713b1edbc 307 This parameter can be a value of @ref FLASHEx_Option_Bytes_BOOT */
AnnaBridge 171:3a7713b1edbc 308 #endif /* FLASH_OBR_nRST_BFB2*/
AnnaBridge 171:3a7713b1edbc 309 } FLASH_AdvOBProgramInitTypeDef;
AnnaBridge 171:3a7713b1edbc 310
AnnaBridge 171:3a7713b1edbc 311 /**
AnnaBridge 171:3a7713b1edbc 312 * @}
AnnaBridge 171:3a7713b1edbc 313 */
AnnaBridge 171:3a7713b1edbc 314 #endif /* FLASH_OBR_SPRMOD || FLASH_OBR_nRST_BFB2 */
AnnaBridge 171:3a7713b1edbc 315
AnnaBridge 171:3a7713b1edbc 316 /* Exported constants --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 317
AnnaBridge 171:3a7713b1edbc 318
AnnaBridge 171:3a7713b1edbc 319 /** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
AnnaBridge 171:3a7713b1edbc 320 * @{
AnnaBridge 171:3a7713b1edbc 321 */
AnnaBridge 171:3a7713b1edbc 322
AnnaBridge 171:3a7713b1edbc 323 /** @defgroup FLASHEx_Type_Erase FLASHEx_Type_Erase
AnnaBridge 171:3a7713b1edbc 324 * @{
AnnaBridge 171:3a7713b1edbc 325 */
AnnaBridge 171:3a7713b1edbc 326 #define FLASH_TYPEERASE_PAGES (0x00U) /*!<Page erase only*/
AnnaBridge 171:3a7713b1edbc 327
AnnaBridge 171:3a7713b1edbc 328 /**
AnnaBridge 171:3a7713b1edbc 329 * @}
AnnaBridge 171:3a7713b1edbc 330 */
AnnaBridge 171:3a7713b1edbc 331
AnnaBridge 171:3a7713b1edbc 332 /** @defgroup FLASHEx_Option_Type FLASHEx Option Type
AnnaBridge 171:3a7713b1edbc 333 * @{
AnnaBridge 171:3a7713b1edbc 334 */
AnnaBridge 171:3a7713b1edbc 335 #define OPTIONBYTE_WRP (0x01U) /*!<WRP option byte configuration*/
AnnaBridge 171:3a7713b1edbc 336 #define OPTIONBYTE_RDP (0x02U) /*!<RDP option byte configuration*/
AnnaBridge 171:3a7713b1edbc 337 #define OPTIONBYTE_USER (0x04U) /*!<USER option byte configuration*/
AnnaBridge 171:3a7713b1edbc 338 #define OPTIONBYTE_BOR (0x08U) /*!<BOR option byte configuration*/
AnnaBridge 171:3a7713b1edbc 339
AnnaBridge 171:3a7713b1edbc 340 /**
AnnaBridge 171:3a7713b1edbc 341 * @}
AnnaBridge 171:3a7713b1edbc 342 */
AnnaBridge 171:3a7713b1edbc 343
AnnaBridge 171:3a7713b1edbc 344 /** @defgroup FLASHEx_WRP_State FLASHEx WRP State
AnnaBridge 171:3a7713b1edbc 345 * @{
AnnaBridge 171:3a7713b1edbc 346 */
AnnaBridge 171:3a7713b1edbc 347 #define OB_WRPSTATE_DISABLE (0x00U) /*!<Disable the write protection of the desired sectors*/
AnnaBridge 171:3a7713b1edbc 348 #define OB_WRPSTATE_ENABLE (0x01U) /*!<Enable the write protection of the desired sectors*/
AnnaBridge 171:3a7713b1edbc 349
AnnaBridge 171:3a7713b1edbc 350 /**
AnnaBridge 171:3a7713b1edbc 351 * @}
AnnaBridge 171:3a7713b1edbc 352 */
AnnaBridge 171:3a7713b1edbc 353
AnnaBridge 171:3a7713b1edbc 354 /** @defgroup FLASHEx_Option_Bytes_Write_Protection1 FLASHEx Option Bytes Write Protection1
AnnaBridge 171:3a7713b1edbc 355 * @{
AnnaBridge 171:3a7713b1edbc 356 */
AnnaBridge 171:3a7713b1edbc 357
AnnaBridge 171:3a7713b1edbc 358 /* Common pages for Cat1, Cat2, Cat3, Cat4 & Cat5 devices */
AnnaBridge 171:3a7713b1edbc 359 #define OB_WRP1_PAGES0TO15 (0x00000001U) /* Write protection of Sector0 */
AnnaBridge 171:3a7713b1edbc 360 #define OB_WRP1_PAGES16TO31 (0x00000002U) /* Write protection of Sector1 */
AnnaBridge 171:3a7713b1edbc 361 #define OB_WRP1_PAGES32TO47 (0x00000004U) /* Write protection of Sector2 */
AnnaBridge 171:3a7713b1edbc 362 #define OB_WRP1_PAGES48TO63 (0x00000008U) /* Write protection of Sector3 */
AnnaBridge 171:3a7713b1edbc 363 #define OB_WRP1_PAGES64TO79 (0x00000010U) /* Write protection of Sector4 */
AnnaBridge 171:3a7713b1edbc 364 #define OB_WRP1_PAGES80TO95 (0x00000020U) /* Write protection of Sector5 */
AnnaBridge 171:3a7713b1edbc 365 #define OB_WRP1_PAGES96TO111 (0x00000040U) /* Write protection of Sector6 */
AnnaBridge 171:3a7713b1edbc 366 #define OB_WRP1_PAGES112TO127 (0x00000080U) /* Write protection of Sector7 */
AnnaBridge 171:3a7713b1edbc 367 #define OB_WRP1_PAGES128TO143 (0x00000100U) /* Write protection of Sector8 */
AnnaBridge 171:3a7713b1edbc 368 #define OB_WRP1_PAGES144TO159 (0x00000200U) /* Write protection of Sector9 */
AnnaBridge 171:3a7713b1edbc 369 #define OB_WRP1_PAGES160TO175 (0x00000400U) /* Write protection of Sector10 */
AnnaBridge 171:3a7713b1edbc 370 #define OB_WRP1_PAGES176TO191 (0x00000800U) /* Write protection of Sector11 */
AnnaBridge 171:3a7713b1edbc 371 #define OB_WRP1_PAGES192TO207 (0x00001000U) /* Write protection of Sector12 */
AnnaBridge 171:3a7713b1edbc 372 #define OB_WRP1_PAGES208TO223 (0x00002000U) /* Write protection of Sector13 */
AnnaBridge 171:3a7713b1edbc 373 #define OB_WRP1_PAGES224TO239 (0x00004000U) /* Write protection of Sector14 */
AnnaBridge 171:3a7713b1edbc 374 #define OB_WRP1_PAGES240TO255 (0x00008000U) /* Write protection of Sector15 */
AnnaBridge 171:3a7713b1edbc 375 #define OB_WRP1_PAGES256TO271 (0x00010000U) /* Write protection of Sector16 */
AnnaBridge 171:3a7713b1edbc 376 #define OB_WRP1_PAGES272TO287 (0x00020000U) /* Write protection of Sector17 */
AnnaBridge 171:3a7713b1edbc 377 #define OB_WRP1_PAGES288TO303 (0x00040000U) /* Write protection of Sector18 */
AnnaBridge 171:3a7713b1edbc 378 #define OB_WRP1_PAGES304TO319 (0x00080000U) /* Write protection of Sector19 */
AnnaBridge 171:3a7713b1edbc 379 #define OB_WRP1_PAGES320TO335 (0x00100000U) /* Write protection of Sector20 */
AnnaBridge 171:3a7713b1edbc 380 #define OB_WRP1_PAGES336TO351 (0x00200000U) /* Write protection of Sector21 */
AnnaBridge 171:3a7713b1edbc 381 #define OB_WRP1_PAGES352TO367 (0x00400000U) /* Write protection of Sector22 */
AnnaBridge 171:3a7713b1edbc 382 #define OB_WRP1_PAGES368TO383 (0x00800000U) /* Write protection of Sector23 */
AnnaBridge 171:3a7713b1edbc 383 #define OB_WRP1_PAGES384TO399 (0x01000000U) /* Write protection of Sector24 */
AnnaBridge 171:3a7713b1edbc 384 #define OB_WRP1_PAGES400TO415 (0x02000000U) /* Write protection of Sector25 */
AnnaBridge 171:3a7713b1edbc 385 #define OB_WRP1_PAGES416TO431 (0x04000000U) /* Write protection of Sector26 */
AnnaBridge 171:3a7713b1edbc 386 #define OB_WRP1_PAGES432TO447 (0x08000000U) /* Write protection of Sector27 */
AnnaBridge 171:3a7713b1edbc 387 #define OB_WRP1_PAGES448TO463 (0x10000000U) /* Write protection of Sector28 */
AnnaBridge 171:3a7713b1edbc 388 #define OB_WRP1_PAGES464TO479 (0x20000000U) /* Write protection of Sector29 */
AnnaBridge 171:3a7713b1edbc 389 #define OB_WRP1_PAGES480TO495 (0x40000000U) /* Write protection of Sector30 */
AnnaBridge 171:3a7713b1edbc 390 #define OB_WRP1_PAGES496TO511 (0x80000000U) /* Write protection of Sector31 */
AnnaBridge 171:3a7713b1edbc 391
AnnaBridge 171:3a7713b1edbc 392 #define OB_WRP1_ALLPAGES ((uint32_t)FLASH_WRPR1_WRP) /*!< Write protection of all Sectors */
AnnaBridge 171:3a7713b1edbc 393
AnnaBridge 171:3a7713b1edbc 394 /**
AnnaBridge 171:3a7713b1edbc 395 * @}
AnnaBridge 171:3a7713b1edbc 396 */
AnnaBridge 171:3a7713b1edbc 397
AnnaBridge 171:3a7713b1edbc 398 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \
AnnaBridge 171:3a7713b1edbc 399 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \
AnnaBridge 171:3a7713b1edbc 400 || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \
AnnaBridge 171:3a7713b1edbc 401 || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)
AnnaBridge 171:3a7713b1edbc 402
AnnaBridge 171:3a7713b1edbc 403 /** @defgroup FLASHEx_Option_Bytes_Write_Protection2 FLASHEx Option Bytes Write Protection2
AnnaBridge 171:3a7713b1edbc 404 * @{
AnnaBridge 171:3a7713b1edbc 405 */
AnnaBridge 171:3a7713b1edbc 406
AnnaBridge 171:3a7713b1edbc 407 /* Pages for Cat3, Cat4 & Cat5 devices*/
AnnaBridge 171:3a7713b1edbc 408 #define OB_WRP2_PAGES512TO527 (0x00000001U) /* Write protection of Sector32 */
AnnaBridge 171:3a7713b1edbc 409 #define OB_WRP2_PAGES528TO543 (0x00000002U) /* Write protection of Sector33 */
AnnaBridge 171:3a7713b1edbc 410 #define OB_WRP2_PAGES544TO559 (0x00000004U) /* Write protection of Sector34 */
AnnaBridge 171:3a7713b1edbc 411 #define OB_WRP2_PAGES560TO575 (0x00000008U) /* Write protection of Sector35 */
AnnaBridge 171:3a7713b1edbc 412 #define OB_WRP2_PAGES576TO591 (0x00000010U) /* Write protection of Sector36 */
AnnaBridge 171:3a7713b1edbc 413 #define OB_WRP2_PAGES592TO607 (0x00000020U) /* Write protection of Sector37 */
AnnaBridge 171:3a7713b1edbc 414 #define OB_WRP2_PAGES608TO623 (0x00000040U) /* Write protection of Sector38 */
AnnaBridge 171:3a7713b1edbc 415 #define OB_WRP2_PAGES624TO639 (0x00000080U) /* Write protection of Sector39 */
AnnaBridge 171:3a7713b1edbc 416 #define OB_WRP2_PAGES640TO655 (0x00000100U) /* Write protection of Sector40 */
AnnaBridge 171:3a7713b1edbc 417 #define OB_WRP2_PAGES656TO671 (0x00000200U) /* Write protection of Sector41 */
AnnaBridge 171:3a7713b1edbc 418 #define OB_WRP2_PAGES672TO687 (0x00000400U) /* Write protection of Sector42 */
AnnaBridge 171:3a7713b1edbc 419 #define OB_WRP2_PAGES688TO703 (0x00000800U) /* Write protection of Sector43 */
AnnaBridge 171:3a7713b1edbc 420 #define OB_WRP2_PAGES704TO719 (0x00001000U) /* Write protection of Sector44 */
AnnaBridge 171:3a7713b1edbc 421 #define OB_WRP2_PAGES720TO735 (0x00002000U) /* Write protection of Sector45 */
AnnaBridge 171:3a7713b1edbc 422 #define OB_WRP2_PAGES736TO751 (0x00004000U) /* Write protection of Sector46 */
AnnaBridge 171:3a7713b1edbc 423 #define OB_WRP2_PAGES752TO767 (0x00008000U) /* Write protection of Sector47 */
AnnaBridge 171:3a7713b1edbc 424
AnnaBridge 171:3a7713b1edbc 425 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \
AnnaBridge 171:3a7713b1edbc 426 || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA) || defined(STM32L152xD) \
AnnaBridge 171:3a7713b1edbc 427 || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L152xE) \
AnnaBridge 171:3a7713b1edbc 428 || defined(STM32L162xE)
AnnaBridge 171:3a7713b1edbc 429
AnnaBridge 171:3a7713b1edbc 430 #define OB_WRP2_PAGES768TO783 (0x00010000U) /* Write protection of Sector48 */
AnnaBridge 171:3a7713b1edbc 431 #define OB_WRP2_PAGES784TO799 (0x00020000U) /* Write protection of Sector49 */
AnnaBridge 171:3a7713b1edbc 432 #define OB_WRP2_PAGES800TO815 (0x00040000U) /* Write protection of Sector50 */
AnnaBridge 171:3a7713b1edbc 433 #define OB_WRP2_PAGES816TO831 (0x00080000U) /* Write protection of Sector51 */
AnnaBridge 171:3a7713b1edbc 434 #define OB_WRP2_PAGES832TO847 (0x00100000U) /* Write protection of Sector52 */
AnnaBridge 171:3a7713b1edbc 435 #define OB_WRP2_PAGES848TO863 (0x00200000U) /* Write protection of Sector53 */
AnnaBridge 171:3a7713b1edbc 436 #define OB_WRP2_PAGES864TO879 (0x00400000U) /* Write protection of Sector54 */
AnnaBridge 171:3a7713b1edbc 437 #define OB_WRP2_PAGES880TO895 (0x00800000U) /* Write protection of Sector55 */
AnnaBridge 171:3a7713b1edbc 438 #define OB_WRP2_PAGES896TO911 (0x01000000U) /* Write protection of Sector56 */
AnnaBridge 171:3a7713b1edbc 439 #define OB_WRP2_PAGES912TO927 (0x02000000U) /* Write protection of Sector57 */
AnnaBridge 171:3a7713b1edbc 440 #define OB_WRP2_PAGES928TO943 (0x04000000U) /* Write protection of Sector58 */
AnnaBridge 171:3a7713b1edbc 441 #define OB_WRP2_PAGES944TO959 (0x08000000U) /* Write protection of Sector59 */
AnnaBridge 171:3a7713b1edbc 442 #define OB_WRP2_PAGES960TO975 (0x10000000U) /* Write protection of Sector60 */
AnnaBridge 171:3a7713b1edbc 443 #define OB_WRP2_PAGES976TO991 (0x20000000U) /* Write protection of Sector61 */
AnnaBridge 171:3a7713b1edbc 444 #define OB_WRP2_PAGES992TO1007 (0x40000000U) /* Write protection of Sector62 */
AnnaBridge 171:3a7713b1edbc 445 #define OB_WRP2_PAGES1008TO1023 (0x80000000U) /* Write protection of Sector63 */
AnnaBridge 171:3a7713b1edbc 446
AnnaBridge 171:3a7713b1edbc 447 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
AnnaBridge 171:3a7713b1edbc 448
AnnaBridge 171:3a7713b1edbc 449 #define OB_WRP2_ALLPAGES ((uint32_t)FLASH_WRPR2_WRP) /*!< Write protection of all Sectors */
AnnaBridge 171:3a7713b1edbc 450
AnnaBridge 171:3a7713b1edbc 451 /**
AnnaBridge 171:3a7713b1edbc 452 * @}
AnnaBridge 171:3a7713b1edbc 453 */
AnnaBridge 171:3a7713b1edbc 454
AnnaBridge 171:3a7713b1edbc 455 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L162xD || STM32L151xDX || STM32L152xE || STM32L162xE */
AnnaBridge 171:3a7713b1edbc 456
AnnaBridge 171:3a7713b1edbc 457 #if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
AnnaBridge 171:3a7713b1edbc 458 || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \
AnnaBridge 171:3a7713b1edbc 459 || defined(STM32L162xE)
AnnaBridge 171:3a7713b1edbc 460
AnnaBridge 171:3a7713b1edbc 461 /** @defgroup FLASHEx_Option_Bytes_Write_Protection3 FLASHEx Option Bytes Write Protection3
AnnaBridge 171:3a7713b1edbc 462 * @{
AnnaBridge 171:3a7713b1edbc 463 */
AnnaBridge 171:3a7713b1edbc 464
AnnaBridge 171:3a7713b1edbc 465 /* Pages for devices with FLASH >= 256KB*/
AnnaBridge 171:3a7713b1edbc 466 #define OB_WRP3_PAGES1024TO1039 (0x00000001U) /* Write protection of Sector64 */
AnnaBridge 171:3a7713b1edbc 467 #define OB_WRP3_PAGES1040TO1055 (0x00000002U) /* Write protection of Sector65 */
AnnaBridge 171:3a7713b1edbc 468 #define OB_WRP3_PAGES1056TO1071 (0x00000004U) /* Write protection of Sector66 */
AnnaBridge 171:3a7713b1edbc 469 #define OB_WRP3_PAGES1072TO1087 (0x00000008U) /* Write protection of Sector67 */
AnnaBridge 171:3a7713b1edbc 470 #define OB_WRP3_PAGES1088TO1103 (0x00000010U) /* Write protection of Sector68 */
AnnaBridge 171:3a7713b1edbc 471 #define OB_WRP3_PAGES1104TO1119 (0x00000020U) /* Write protection of Sector69 */
AnnaBridge 171:3a7713b1edbc 472 #define OB_WRP3_PAGES1120TO1135 (0x00000040U) /* Write protection of Sector70 */
AnnaBridge 171:3a7713b1edbc 473 #define OB_WRP3_PAGES1136TO1151 (0x00000080U) /* Write protection of Sector71 */
AnnaBridge 171:3a7713b1edbc 474 #define OB_WRP3_PAGES1152TO1167 (0x00000100U) /* Write protection of Sector72 */
AnnaBridge 171:3a7713b1edbc 475 #define OB_WRP3_PAGES1168TO1183 (0x00000200U) /* Write protection of Sector73 */
AnnaBridge 171:3a7713b1edbc 476 #define OB_WRP3_PAGES1184TO1199 (0x00000400U) /* Write protection of Sector74 */
AnnaBridge 171:3a7713b1edbc 477 #define OB_WRP3_PAGES1200TO1215 (0x00000800U) /* Write protection of Sector75 */
AnnaBridge 171:3a7713b1edbc 478 #define OB_WRP3_PAGES1216TO1231 (0x00001000U) /* Write protection of Sector76 */
AnnaBridge 171:3a7713b1edbc 479 #define OB_WRP3_PAGES1232TO1247 (0x00002000U) /* Write protection of Sector77 */
AnnaBridge 171:3a7713b1edbc 480 #define OB_WRP3_PAGES1248TO1263 (0x00004000U) /* Write protection of Sector78 */
AnnaBridge 171:3a7713b1edbc 481 #define OB_WRP3_PAGES1264TO1279 (0x00008000U) /* Write protection of Sector79 */
AnnaBridge 171:3a7713b1edbc 482 #define OB_WRP3_PAGES1280TO1295 (0x00010000U) /* Write protection of Sector80 */
AnnaBridge 171:3a7713b1edbc 483 #define OB_WRP3_PAGES1296TO1311 (0x00020000U) /* Write protection of Sector81 */
AnnaBridge 171:3a7713b1edbc 484 #define OB_WRP3_PAGES1312TO1327 (0x00040000U) /* Write protection of Sector82 */
AnnaBridge 171:3a7713b1edbc 485 #define OB_WRP3_PAGES1328TO1343 (0x00080000U) /* Write protection of Sector83 */
AnnaBridge 171:3a7713b1edbc 486 #define OB_WRP3_PAGES1344TO1359 (0x00100000U) /* Write protection of Sector84 */
AnnaBridge 171:3a7713b1edbc 487 #define OB_WRP3_PAGES1360TO1375 (0x00200000U) /* Write protection of Sector85 */
AnnaBridge 171:3a7713b1edbc 488 #define OB_WRP3_PAGES1376TO1391 (0x00400000U) /* Write protection of Sector86 */
AnnaBridge 171:3a7713b1edbc 489 #define OB_WRP3_PAGES1392TO1407 (0x00800000U) /* Write protection of Sector87 */
AnnaBridge 171:3a7713b1edbc 490 #define OB_WRP3_PAGES1408TO1423 (0x01000000U) /* Write protection of Sector88 */
AnnaBridge 171:3a7713b1edbc 491 #define OB_WRP3_PAGES1424TO1439 (0x02000000U) /* Write protection of Sector89 */
AnnaBridge 171:3a7713b1edbc 492 #define OB_WRP3_PAGES1440TO1455 (0x04000000U) /* Write protection of Sector90 */
AnnaBridge 171:3a7713b1edbc 493 #define OB_WRP3_PAGES1456TO1471 (0x08000000U) /* Write protection of Sector91 */
AnnaBridge 171:3a7713b1edbc 494 #define OB_WRP3_PAGES1472TO1487 (0x10000000U) /* Write protection of Sector92 */
AnnaBridge 171:3a7713b1edbc 495 #define OB_WRP3_PAGES1488TO1503 (0x20000000U) /* Write protection of Sector93 */
AnnaBridge 171:3a7713b1edbc 496 #define OB_WRP3_PAGES1504TO1519 (0x40000000U) /* Write protection of Sector94 */
AnnaBridge 171:3a7713b1edbc 497 #define OB_WRP3_PAGES1520TO1535 (0x80000000U) /* Write protection of Sector95 */
AnnaBridge 171:3a7713b1edbc 498
AnnaBridge 171:3a7713b1edbc 499 #define OB_WRP3_ALLPAGES ((uint32_t)FLASH_WRPR3_WRP) /*!< Write protection of all Sectors */
AnnaBridge 171:3a7713b1edbc 500
AnnaBridge 171:3a7713b1edbc 501 /**
AnnaBridge 171:3a7713b1edbc 502 * @}
AnnaBridge 171:3a7713b1edbc 503 */
AnnaBridge 171:3a7713b1edbc 504
AnnaBridge 171:3a7713b1edbc 505 #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE*/
AnnaBridge 171:3a7713b1edbc 506
AnnaBridge 171:3a7713b1edbc 507 #if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \
AnnaBridge 171:3a7713b1edbc 508 || defined(STM32L152xDX) || defined(STM32L162xDX)
AnnaBridge 171:3a7713b1edbc 509
AnnaBridge 171:3a7713b1edbc 510 /** @defgroup FLASHEx_Option_Bytes_Write_Protection4 FLASHEx Option Bytes Write Protection4
AnnaBridge 171:3a7713b1edbc 511 * @{
AnnaBridge 171:3a7713b1edbc 512 */
AnnaBridge 171:3a7713b1edbc 513
AnnaBridge 171:3a7713b1edbc 514 /* Pages for Cat5 devices*/
AnnaBridge 171:3a7713b1edbc 515 #define OB_WRP4_PAGES1536TO1551 (0x00000001U)/* Write protection of Sector96*/
AnnaBridge 171:3a7713b1edbc 516 #define OB_WRP4_PAGES1552TO1567 (0x00000002U)/* Write protection of Sector97*/
AnnaBridge 171:3a7713b1edbc 517 #define OB_WRP4_PAGES1568TO1583 (0x00000004U)/* Write protection of Sector98*/
AnnaBridge 171:3a7713b1edbc 518 #define OB_WRP4_PAGES1584TO1599 (0x00000008U)/* Write protection of Sector99*/
AnnaBridge 171:3a7713b1edbc 519 #define OB_WRP4_PAGES1600TO1615 (0x00000010U) /* Write protection of Sector100*/
AnnaBridge 171:3a7713b1edbc 520 #define OB_WRP4_PAGES1616TO1631 (0x00000020U) /* Write protection of Sector101*/
AnnaBridge 171:3a7713b1edbc 521 #define OB_WRP4_PAGES1632TO1647 (0x00000040U) /* Write protection of Sector102*/
AnnaBridge 171:3a7713b1edbc 522 #define OB_WRP4_PAGES1648TO1663 (0x00000080U) /* Write protection of Sector103*/
AnnaBridge 171:3a7713b1edbc 523 #define OB_WRP4_PAGES1664TO1679 (0x00000100U) /* Write protection of Sector104*/
AnnaBridge 171:3a7713b1edbc 524 #define OB_WRP4_PAGES1680TO1695 (0x00000200U) /* Write protection of Sector105*/
AnnaBridge 171:3a7713b1edbc 525 #define OB_WRP4_PAGES1696TO1711 (0x00000400U) /* Write protection of Sector106*/
AnnaBridge 171:3a7713b1edbc 526 #define OB_WRP4_PAGES1712TO1727 (0x00000800U) /* Write protection of Sector107*/
AnnaBridge 171:3a7713b1edbc 527 #define OB_WRP4_PAGES1728TO1743 (0x00001000U) /* Write protection of Sector108*/
AnnaBridge 171:3a7713b1edbc 528 #define OB_WRP4_PAGES1744TO1759 (0x00002000U) /* Write protection of Sector109*/
AnnaBridge 171:3a7713b1edbc 529 #define OB_WRP4_PAGES1760TO1775 (0x00004000U) /* Write protection of Sector110*/
AnnaBridge 171:3a7713b1edbc 530 #define OB_WRP4_PAGES1776TO1791 (0x00008000U) /* Write protection of Sector111*/
AnnaBridge 171:3a7713b1edbc 531
AnnaBridge 171:3a7713b1edbc 532 #if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)
AnnaBridge 171:3a7713b1edbc 533
AnnaBridge 171:3a7713b1edbc 534 #define OB_WRP4_PAGES1792TO1807 (0x00010000U) /* Write protection of Sector112*/
AnnaBridge 171:3a7713b1edbc 535 #define OB_WRP4_PAGES1808TO1823 (0x00020000U) /* Write protection of Sector113*/
AnnaBridge 171:3a7713b1edbc 536 #define OB_WRP4_PAGES1824TO1839 (0x00040000U) /* Write protection of Sector114*/
AnnaBridge 171:3a7713b1edbc 537 #define OB_WRP4_PAGES1840TO1855 (0x00080000U) /* Write protection of Sector115*/
AnnaBridge 171:3a7713b1edbc 538 #define OB_WRP4_PAGES1856TO1871 (0x00100000U) /* Write protection of Sector116*/
AnnaBridge 171:3a7713b1edbc 539 #define OB_WRP4_PAGES1872TO1887 (0x00200000U) /* Write protection of Sector117*/
AnnaBridge 171:3a7713b1edbc 540 #define OB_WRP4_PAGES1888TO1903 (0x00400000U) /* Write protection of Sector118*/
AnnaBridge 171:3a7713b1edbc 541 #define OB_WRP4_PAGES1904TO1919 (0x00800000U) /* Write protection of Sector119*/
AnnaBridge 171:3a7713b1edbc 542 #define OB_WRP4_PAGES1920TO1935 (0x01000000U) /* Write protection of Sector120*/
AnnaBridge 171:3a7713b1edbc 543 #define OB_WRP4_PAGES1936TO1951 (0x02000000U) /* Write protection of Sector121*/
AnnaBridge 171:3a7713b1edbc 544 #define OB_WRP4_PAGES1952TO1967 (0x04000000U) /* Write protection of Sector122*/
AnnaBridge 171:3a7713b1edbc 545 #define OB_WRP4_PAGES1968TO1983 (0x08000000U) /* Write protection of Sector123*/
AnnaBridge 171:3a7713b1edbc 546 #define OB_WRP4_PAGES1984TO1999 (0x10000000U) /* Write protection of Sector124*/
AnnaBridge 171:3a7713b1edbc 547 #define OB_WRP4_PAGES2000TO2015 (0x20000000U) /* Write protection of Sector125*/
AnnaBridge 171:3a7713b1edbc 548 #define OB_WRP4_PAGES2016TO2031 (0x40000000U) /* Write protection of Sector126*/
AnnaBridge 171:3a7713b1edbc 549 #define OB_WRP4_PAGES2032TO2047 (0x80000000U) /* Write protection of Sector127*/
AnnaBridge 171:3a7713b1edbc 550
AnnaBridge 171:3a7713b1edbc 551 #endif /* STM32L151xE || STM32L152xE || STM32L162xE */
AnnaBridge 171:3a7713b1edbc 552
AnnaBridge 171:3a7713b1edbc 553 #define OB_WRP4_ALLPAGES ((uint32_t)FLASH_WRPR4_WRP) /*!< Write protection of all Sectors */
AnnaBridge 171:3a7713b1edbc 554
AnnaBridge 171:3a7713b1edbc 555 /**
AnnaBridge 171:3a7713b1edbc 556 * @}
AnnaBridge 171:3a7713b1edbc 557 */
AnnaBridge 171:3a7713b1edbc 558
AnnaBridge 171:3a7713b1edbc 559 #endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */
AnnaBridge 171:3a7713b1edbc 560
AnnaBridge 171:3a7713b1edbc 561 /** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASHEx Option Bytes Read Protection
AnnaBridge 171:3a7713b1edbc 562 * @{
AnnaBridge 171:3a7713b1edbc 563 */
AnnaBridge 171:3a7713b1edbc 564 #define OB_RDP_LEVEL_0 ((uint8_t)0xAAU)
AnnaBridge 171:3a7713b1edbc 565 #define OB_RDP_LEVEL_1 ((uint8_t)0xBBU)
AnnaBridge 171:3a7713b1edbc 566 #define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /* Warning: When enabling read protection level 2
AnnaBridge 171:3a7713b1edbc 567 it is no more possible to go back to level 1 or 0 */
AnnaBridge 171:3a7713b1edbc 568
AnnaBridge 171:3a7713b1edbc 569 /**
AnnaBridge 171:3a7713b1edbc 570 * @}
AnnaBridge 171:3a7713b1edbc 571 */
AnnaBridge 171:3a7713b1edbc 572
AnnaBridge 171:3a7713b1edbc 573 /** @defgroup FLASHEx_Option_Bytes_BOR_Level FLASHEx Option Bytes BOR Level
AnnaBridge 171:3a7713b1edbc 574 * @{
AnnaBridge 171:3a7713b1edbc 575 */
AnnaBridge 171:3a7713b1edbc 576
AnnaBridge 171:3a7713b1edbc 577 #define OB_BOR_OFF ((uint8_t)0x00U) /*!< BOR is disabled at power down, the reset is asserted when the VDD
AnnaBridge 171:3a7713b1edbc 578 power supply reaches the PDR(Power Down Reset) threshold (1.5V) */
AnnaBridge 171:3a7713b1edbc 579 #define OB_BOR_LEVEL1 ((uint8_t)0x08U) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply */
AnnaBridge 171:3a7713b1edbc 580 #define OB_BOR_LEVEL2 ((uint8_t)0x09U) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply */
AnnaBridge 171:3a7713b1edbc 581 #define OB_BOR_LEVEL3 ((uint8_t)0x0AU) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply */
AnnaBridge 171:3a7713b1edbc 582 #define OB_BOR_LEVEL4 ((uint8_t)0x0BU) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply */
AnnaBridge 171:3a7713b1edbc 583 #define OB_BOR_LEVEL5 ((uint8_t)0x0CU) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply */
AnnaBridge 171:3a7713b1edbc 584
AnnaBridge 171:3a7713b1edbc 585 /**
AnnaBridge 171:3a7713b1edbc 586 * @}
AnnaBridge 171:3a7713b1edbc 587 */
AnnaBridge 171:3a7713b1edbc 588
AnnaBridge 171:3a7713b1edbc 589 /** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASHEx Option Bytes IWatchdog
AnnaBridge 171:3a7713b1edbc 590 * @{
AnnaBridge 171:3a7713b1edbc 591 */
AnnaBridge 171:3a7713b1edbc 592
AnnaBridge 171:3a7713b1edbc 593 #define OB_IWDG_SW ((uint8_t)0x10U) /*!< Software WDG selected */
AnnaBridge 171:3a7713b1edbc 594 #define OB_IWDG_HW ((uint8_t)0x00U) /*!< Hardware WDG selected */
AnnaBridge 171:3a7713b1edbc 595
AnnaBridge 171:3a7713b1edbc 596 /**
AnnaBridge 171:3a7713b1edbc 597 * @}
AnnaBridge 171:3a7713b1edbc 598 */
AnnaBridge 171:3a7713b1edbc 599
AnnaBridge 171:3a7713b1edbc 600 /** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASHEx Option Bytes nRST_STOP
AnnaBridge 171:3a7713b1edbc 601 * @{
AnnaBridge 171:3a7713b1edbc 602 */
AnnaBridge 171:3a7713b1edbc 603
AnnaBridge 171:3a7713b1edbc 604 #define OB_STOP_NORST ((uint8_t)0x20U) /*!< No reset generated when entering in STOP */
AnnaBridge 171:3a7713b1edbc 605 #define OB_STOP_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STOP */
AnnaBridge 171:3a7713b1edbc 606 /**
AnnaBridge 171:3a7713b1edbc 607 * @}
AnnaBridge 171:3a7713b1edbc 608 */
AnnaBridge 171:3a7713b1edbc 609
AnnaBridge 171:3a7713b1edbc 610 /** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASHEx Option Bytes nRST_STDBY
AnnaBridge 171:3a7713b1edbc 611 * @{
AnnaBridge 171:3a7713b1edbc 612 */
AnnaBridge 171:3a7713b1edbc 613
AnnaBridge 171:3a7713b1edbc 614 #define OB_STDBY_NORST ((uint8_t)0x40U) /*!< No reset generated when entering in STANDBY */
AnnaBridge 171:3a7713b1edbc 615 #define OB_STDBY_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STANDBY */
AnnaBridge 171:3a7713b1edbc 616
AnnaBridge 171:3a7713b1edbc 617 /**
AnnaBridge 171:3a7713b1edbc 618 * @}
AnnaBridge 171:3a7713b1edbc 619 */
AnnaBridge 171:3a7713b1edbc 620
AnnaBridge 171:3a7713b1edbc 621 #if defined(FLASH_OBR_SPRMOD)
AnnaBridge 171:3a7713b1edbc 622
AnnaBridge 171:3a7713b1edbc 623 /** @defgroup FLASHEx_OptionAdv_Type FLASHEx Option Advanced Type
AnnaBridge 171:3a7713b1edbc 624 * @{
AnnaBridge 171:3a7713b1edbc 625 */
AnnaBridge 171:3a7713b1edbc 626
AnnaBridge 171:3a7713b1edbc 627 #define OPTIONBYTE_PCROP (0x01U) /*!<PCROP option byte configuration*/
AnnaBridge 171:3a7713b1edbc 628
AnnaBridge 171:3a7713b1edbc 629 /**
AnnaBridge 171:3a7713b1edbc 630 * @}
AnnaBridge 171:3a7713b1edbc 631 */
AnnaBridge 171:3a7713b1edbc 632
AnnaBridge 171:3a7713b1edbc 633 #endif /* FLASH_OBR_SPRMOD */
AnnaBridge 171:3a7713b1edbc 634
AnnaBridge 171:3a7713b1edbc 635 #if defined(FLASH_OBR_nRST_BFB2)
AnnaBridge 171:3a7713b1edbc 636
AnnaBridge 171:3a7713b1edbc 637 /** @defgroup FLASHEx_OptionAdv_Type FLASHEx Option Advanced Type
AnnaBridge 171:3a7713b1edbc 638 * @{
AnnaBridge 171:3a7713b1edbc 639 */
AnnaBridge 171:3a7713b1edbc 640
AnnaBridge 171:3a7713b1edbc 641 #define OPTIONBYTE_BOOTCONFIG (0x02U) /*!<BOOTConfig option byte configuration*/
AnnaBridge 171:3a7713b1edbc 642
AnnaBridge 171:3a7713b1edbc 643 /**
AnnaBridge 171:3a7713b1edbc 644 * @}
AnnaBridge 171:3a7713b1edbc 645 */
AnnaBridge 171:3a7713b1edbc 646
AnnaBridge 171:3a7713b1edbc 647 #endif /* FLASH_OBR_nRST_BFB2 */
AnnaBridge 171:3a7713b1edbc 648
AnnaBridge 171:3a7713b1edbc 649 #if defined(FLASH_OBR_SPRMOD)
AnnaBridge 171:3a7713b1edbc 650
AnnaBridge 171:3a7713b1edbc 651 /** @defgroup FLASHEx_PCROP_State FLASHEx PCROP State
AnnaBridge 171:3a7713b1edbc 652 * @{
AnnaBridge 171:3a7713b1edbc 653 */
AnnaBridge 171:3a7713b1edbc 654 #define OB_PCROP_STATE_DISABLE (0x00U) /*!<Disable PCROP for selected sectors */
AnnaBridge 171:3a7713b1edbc 655 #define OB_PCROP_STATE_ENABLE (0x01U) /*!<Enable PCROP for selected sectors */
AnnaBridge 171:3a7713b1edbc 656
AnnaBridge 171:3a7713b1edbc 657 /**
AnnaBridge 171:3a7713b1edbc 658 * @}
AnnaBridge 171:3a7713b1edbc 659 */
AnnaBridge 171:3a7713b1edbc 660
AnnaBridge 171:3a7713b1edbc 661 /** @defgroup FLASHEx_Selection_Protection_Mode FLASHEx Selection Protection Mode
AnnaBridge 171:3a7713b1edbc 662 * @{
AnnaBridge 171:3a7713b1edbc 663 */
AnnaBridge 171:3a7713b1edbc 664 #define OB_PCROP_DESELECTED ((uint16_t)0x0000U) /*!< Disabled PCROP, nWPRi bits used for Write Protection on sector i */
AnnaBridge 171:3a7713b1edbc 665 #define OB_PCROP_SELECTED ((uint16_t)FLASH_OBR_SPRMOD) /*!< Enable PCROP, nWPRi bits used for PCRoP Protection on sector i */
AnnaBridge 171:3a7713b1edbc 666
AnnaBridge 171:3a7713b1edbc 667 /**
AnnaBridge 171:3a7713b1edbc 668 * @}
AnnaBridge 171:3a7713b1edbc 669 */
AnnaBridge 171:3a7713b1edbc 670 #endif /* FLASH_OBR_SPRMOD */
AnnaBridge 171:3a7713b1edbc 671
AnnaBridge 171:3a7713b1edbc 672 #if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \
AnnaBridge 171:3a7713b1edbc 673 || defined(STM32L162xC)
AnnaBridge 171:3a7713b1edbc 674 /** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection1 FLASHEx Option Bytes PC ReadWrite Protection 1
AnnaBridge 171:3a7713b1edbc 675 * @{
AnnaBridge 171:3a7713b1edbc 676 */
AnnaBridge 171:3a7713b1edbc 677
AnnaBridge 171:3a7713b1edbc 678 /* Common pages for Cat1, Cat2, Cat3, Cat4 & Cat5 devices */
AnnaBridge 171:3a7713b1edbc 679 #define OB_PCROP1_PAGES0TO15 (0x00000001U) /* PC Read/Write protection of Sector0 */
AnnaBridge 171:3a7713b1edbc 680 #define OB_PCROP1_PAGES16TO31 (0x00000002U) /* PC Read/Write protection of Sector1 */
AnnaBridge 171:3a7713b1edbc 681 #define OB_PCROP1_PAGES32TO47 (0x00000004U) /* PC Read/Write protection of Sector2 */
AnnaBridge 171:3a7713b1edbc 682 #define OB_PCROP1_PAGES48TO63 (0x00000008U) /* PC Read/Write protection of Sector3 */
AnnaBridge 171:3a7713b1edbc 683 #define OB_PCROP1_PAGES64TO79 (0x00000010U) /* PC Read/Write protection of Sector4 */
AnnaBridge 171:3a7713b1edbc 684 #define OB_PCROP1_PAGES80TO95 (0x00000020U) /* PC Read/Write protection of Sector5 */
AnnaBridge 171:3a7713b1edbc 685 #define OB_PCROP1_PAGES96TO111 (0x00000040U) /* PC Read/Write protection of Sector6 */
AnnaBridge 171:3a7713b1edbc 686 #define OB_PCROP1_PAGES112TO127 (0x00000080U) /* PC Read/Write protection of Sector7 */
AnnaBridge 171:3a7713b1edbc 687 #define OB_PCROP1_PAGES128TO143 (0x00000100U) /* PC Read/Write protection of Sector8 */
AnnaBridge 171:3a7713b1edbc 688 #define OB_PCROP1_PAGES144TO159 (0x00000200U) /* PC Read/Write protection of Sector9 */
AnnaBridge 171:3a7713b1edbc 689 #define OB_PCROP1_PAGES160TO175 (0x00000400U) /* PC Read/Write protection of Sector10 */
AnnaBridge 171:3a7713b1edbc 690 #define OB_PCROP1_PAGES176TO191 (0x00000800U) /* PC Read/Write protection of Sector11 */
AnnaBridge 171:3a7713b1edbc 691 #define OB_PCROP1_PAGES192TO207 (0x00001000U) /* PC Read/Write protection of Sector12 */
AnnaBridge 171:3a7713b1edbc 692 #define OB_PCROP1_PAGES208TO223 (0x00002000U) /* PC Read/Write protection of Sector13 */
AnnaBridge 171:3a7713b1edbc 693 #define OB_PCROP1_PAGES224TO239 (0x00004000U) /* PC Read/Write protection of Sector14 */
AnnaBridge 171:3a7713b1edbc 694 #define OB_PCROP1_PAGES240TO255 (0x00008000U) /* PC Read/Write protection of Sector15 */
AnnaBridge 171:3a7713b1edbc 695 #define OB_PCROP1_PAGES256TO271 (0x00010000U) /* PC Read/Write protection of Sector16 */
AnnaBridge 171:3a7713b1edbc 696 #define OB_PCROP1_PAGES272TO287 (0x00020000U) /* PC Read/Write protection of Sector17 */
AnnaBridge 171:3a7713b1edbc 697 #define OB_PCROP1_PAGES288TO303 (0x00040000U) /* PC Read/Write protection of Sector18 */
AnnaBridge 171:3a7713b1edbc 698 #define OB_PCROP1_PAGES304TO319 (0x00080000U) /* PC Read/Write protection of Sector19 */
AnnaBridge 171:3a7713b1edbc 699 #define OB_PCROP1_PAGES320TO335 (0x00100000U) /* PC Read/Write protection of Sector20 */
AnnaBridge 171:3a7713b1edbc 700 #define OB_PCROP1_PAGES336TO351 (0x00200000U) /* PC Read/Write protection of Sector21 */
AnnaBridge 171:3a7713b1edbc 701 #define OB_PCROP1_PAGES352TO367 (0x00400000U) /* PC Read/Write protection of Sector22 */
AnnaBridge 171:3a7713b1edbc 702 #define OB_PCROP1_PAGES368TO383 (0x00800000U) /* PC Read/Write protection of Sector23 */
AnnaBridge 171:3a7713b1edbc 703 #define OB_PCROP1_PAGES384TO399 (0x01000000U) /* PC Read/Write protection of Sector24 */
AnnaBridge 171:3a7713b1edbc 704 #define OB_PCROP1_PAGES400TO415 (0x02000000U) /* PC Read/Write protection of Sector25 */
AnnaBridge 171:3a7713b1edbc 705 #define OB_PCROP1_PAGES416TO431 (0x04000000U) /* PC Read/Write protection of Sector26 */
AnnaBridge 171:3a7713b1edbc 706 #define OB_PCROP1_PAGES432TO447 (0x08000000U) /* PC Read/Write protection of Sector27 */
AnnaBridge 171:3a7713b1edbc 707 #define OB_PCROP1_PAGES448TO463 (0x10000000U) /* PC Read/Write protection of Sector28 */
AnnaBridge 171:3a7713b1edbc 708 #define OB_PCROP1_PAGES464TO479 (0x20000000U) /* PC Read/Write protection of Sector29 */
AnnaBridge 171:3a7713b1edbc 709 #define OB_PCROP1_PAGES480TO495 (0x40000000U) /* PC Read/Write protection of Sector30 */
AnnaBridge 171:3a7713b1edbc 710 #define OB_PCROP1_PAGES496TO511 (0x80000000U) /* PC Read/Write protection of Sector31 */
AnnaBridge 171:3a7713b1edbc 711
AnnaBridge 171:3a7713b1edbc 712 #define OB_PCROP1_ALLPAGES (0xFFFFFFFFU) /*!< PC Read/Write protection of all Sectors */
AnnaBridge 171:3a7713b1edbc 713
AnnaBridge 171:3a7713b1edbc 714 /**
AnnaBridge 171:3a7713b1edbc 715 * @}
AnnaBridge 171:3a7713b1edbc 716 */
AnnaBridge 171:3a7713b1edbc 717 #endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
AnnaBridge 171:3a7713b1edbc 718
AnnaBridge 171:3a7713b1edbc 719 #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)
AnnaBridge 171:3a7713b1edbc 720
AnnaBridge 171:3a7713b1edbc 721 /** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 FLASHEx Option Bytes PC ReadWrite Protection 2
AnnaBridge 171:3a7713b1edbc 722 * @{
AnnaBridge 171:3a7713b1edbc 723 */
AnnaBridge 171:3a7713b1edbc 724
AnnaBridge 171:3a7713b1edbc 725 /* Pages for Cat3, Cat4 & Cat5 devices*/
AnnaBridge 171:3a7713b1edbc 726 #define OB_PCROP2_PAGES512TO527 (0x00000001U) /* PC Read/Write protection of Sector32 */
AnnaBridge 171:3a7713b1edbc 727 #define OB_PCROP2_PAGES528TO543 (0x00000002U) /* PC Read/Write protection of Sector33 */
AnnaBridge 171:3a7713b1edbc 728 #define OB_PCROP2_PAGES544TO559 (0x00000004U) /* PC Read/Write protection of Sector34 */
AnnaBridge 171:3a7713b1edbc 729 #define OB_PCROP2_PAGES560TO575 (0x00000008U) /* PC Read/Write protection of Sector35 */
AnnaBridge 171:3a7713b1edbc 730 #define OB_PCROP2_PAGES576TO591 (0x00000010U) /* PC Read/Write protection of Sector36 */
AnnaBridge 171:3a7713b1edbc 731 #define OB_PCROP2_PAGES592TO607 (0x00000020U) /* PC Read/Write protection of Sector37 */
AnnaBridge 171:3a7713b1edbc 732 #define OB_PCROP2_PAGES608TO623 (0x00000040U) /* PC Read/Write protection of Sector38 */
AnnaBridge 171:3a7713b1edbc 733 #define OB_PCROP2_PAGES624TO639 (0x00000080U) /* PC Read/Write protection of Sector39 */
AnnaBridge 171:3a7713b1edbc 734 #define OB_PCROP2_PAGES640TO655 (0x00000100U) /* PC Read/Write protection of Sector40 */
AnnaBridge 171:3a7713b1edbc 735 #define OB_PCROP2_PAGES656TO671 (0x00000200U) /* PC Read/Write protection of Sector41 */
AnnaBridge 171:3a7713b1edbc 736 #define OB_PCROP2_PAGES672TO687 (0x00000400U) /* PC Read/Write protection of Sector42 */
AnnaBridge 171:3a7713b1edbc 737 #define OB_PCROP2_PAGES688TO703 (0x00000800U) /* PC Read/Write protection of Sector43 */
AnnaBridge 171:3a7713b1edbc 738 #define OB_PCROP2_PAGES704TO719 (0x00001000U) /* PC Read/Write protection of Sector44 */
AnnaBridge 171:3a7713b1edbc 739 #define OB_PCROP2_PAGES720TO735 (0x00002000U) /* PC Read/Write protection of Sector45 */
AnnaBridge 171:3a7713b1edbc 740 #define OB_PCROP2_PAGES736TO751 (0x00004000U) /* PC Read/Write protection of Sector46 */
AnnaBridge 171:3a7713b1edbc 741 #define OB_PCROP2_PAGES752TO767 (0x00008000U) /* PC Read/Write protection of Sector47 */
AnnaBridge 171:3a7713b1edbc 742 #define OB_PCROP2_PAGES768TO783 (0x00010000U) /* PC Read/Write protection of Sector48 */
AnnaBridge 171:3a7713b1edbc 743 #define OB_PCROP2_PAGES784TO799 (0x00020000U) /* PC Read/Write protection of Sector49 */
AnnaBridge 171:3a7713b1edbc 744 #define OB_PCROP2_PAGES800TO815 (0x00040000U) /* PC Read/Write protection of Sector50 */
AnnaBridge 171:3a7713b1edbc 745 #define OB_PCROP2_PAGES816TO831 (0x00080000U) /* PC Read/Write protection of Sector51 */
AnnaBridge 171:3a7713b1edbc 746 #define OB_PCROP2_PAGES832TO847 (0x00100000U) /* PC Read/Write protection of Sector52 */
AnnaBridge 171:3a7713b1edbc 747 #define OB_PCROP2_PAGES848TO863 (0x00200000U) /* PC Read/Write protection of Sector53 */
AnnaBridge 171:3a7713b1edbc 748 #define OB_PCROP2_PAGES864TO879 (0x00400000U) /* PC Read/Write protection of Sector54 */
AnnaBridge 171:3a7713b1edbc 749 #define OB_PCROP2_PAGES880TO895 (0x00800000U) /* PC Read/Write protection of Sector55 */
AnnaBridge 171:3a7713b1edbc 750 #define OB_PCROP2_PAGES896TO911 (0x01000000U) /* PC Read/Write protection of Sector56 */
AnnaBridge 171:3a7713b1edbc 751 #define OB_PCROP2_PAGES912TO927 (0x02000000U) /* PC Read/Write protection of Sector57 */
AnnaBridge 171:3a7713b1edbc 752 #define OB_PCROP2_PAGES928TO943 (0x04000000U) /* PC Read/Write protection of Sector58 */
AnnaBridge 171:3a7713b1edbc 753 #define OB_PCROP2_PAGES944TO959 (0x08000000U) /* PC Read/Write protection of Sector59 */
AnnaBridge 171:3a7713b1edbc 754 #define OB_PCROP2_PAGES960TO975 (0x10000000U) /* PC Read/Write protection of Sector60 */
AnnaBridge 171:3a7713b1edbc 755 #define OB_PCROP2_PAGES976TO991 (0x20000000U) /* PC Read/Write protection of Sector61 */
AnnaBridge 171:3a7713b1edbc 756 #define OB_PCROP2_PAGES992TO1007 (0x40000000U) /* PC Read/Write protection of Sector62 */
AnnaBridge 171:3a7713b1edbc 757 #define OB_PCROP2_PAGES1008TO1023 (0x80000000U) /* PC Read/Write protection of Sector63 */
AnnaBridge 171:3a7713b1edbc 758
AnnaBridge 171:3a7713b1edbc 759 #define OB_PCROP2_ALLPAGES (0xFFFFFFFFU) /*!< PC Read/Write protection of all Sectors */
AnnaBridge 171:3a7713b1edbc 760
AnnaBridge 171:3a7713b1edbc 761 /**
AnnaBridge 171:3a7713b1edbc 762 * @}
AnnaBridge 171:3a7713b1edbc 763 */
AnnaBridge 171:3a7713b1edbc 764 #endif /* STM32L151xC || STM32L152xC || STM32L162xC */
AnnaBridge 171:3a7713b1edbc 765
AnnaBridge 171:3a7713b1edbc 766 /** @defgroup FLASHEx_Type_Erase_Data FLASHEx Type Erase Data
AnnaBridge 171:3a7713b1edbc 767 * @{
AnnaBridge 171:3a7713b1edbc 768 */
AnnaBridge 171:3a7713b1edbc 769 #define FLASH_TYPEERASEDATA_BYTE (0x00U) /*!<Erase byte (8-bit) at a specified address.*/
AnnaBridge 171:3a7713b1edbc 770 #define FLASH_TYPEERASEDATA_HALFWORD (0x01U) /*!<Erase a half-word (16-bit) at a specified address.*/
AnnaBridge 171:3a7713b1edbc 771 #define FLASH_TYPEERASEDATA_WORD (0x02U) /*!<Erase a word (32-bit) at a specified address.*/
AnnaBridge 171:3a7713b1edbc 772
AnnaBridge 171:3a7713b1edbc 773 /**
AnnaBridge 171:3a7713b1edbc 774 * @}
AnnaBridge 171:3a7713b1edbc 775 */
AnnaBridge 171:3a7713b1edbc 776
AnnaBridge 171:3a7713b1edbc 777 /** @defgroup FLASHEx_Type_Program_Data FLASHEx Type Program Data
AnnaBridge 171:3a7713b1edbc 778 * @{
AnnaBridge 171:3a7713b1edbc 779 */
AnnaBridge 171:3a7713b1edbc 780 #define FLASH_TYPEPROGRAMDATA_BYTE (0x00U) /*!<Program byte (8-bit) at a specified address.*/
AnnaBridge 171:3a7713b1edbc 781 #define FLASH_TYPEPROGRAMDATA_HALFWORD (0x01U) /*!<Program a half-word (16-bit) at a specified address.*/
AnnaBridge 171:3a7713b1edbc 782 #define FLASH_TYPEPROGRAMDATA_WORD (0x02U) /*!<Program a word (32-bit) at a specified address.*/
AnnaBridge 171:3a7713b1edbc 783 #define FLASH_TYPEPROGRAMDATA_FASTBYTE (0x04U) /*!<Fast Program byte (8-bit) at a specified address.*/
AnnaBridge 171:3a7713b1edbc 784 #define FLASH_TYPEPROGRAMDATA_FASTHALFWORD (0x08U) /*!<Fast Program a half-word (16-bit) at a specified address.*/
AnnaBridge 171:3a7713b1edbc 785 #define FLASH_TYPEPROGRAMDATA_FASTWORD (0x10U) /*!<Fast Program a word (32-bit) at a specified address.*/
AnnaBridge 171:3a7713b1edbc 786
AnnaBridge 171:3a7713b1edbc 787 /**
AnnaBridge 171:3a7713b1edbc 788 * @}
AnnaBridge 171:3a7713b1edbc 789 */
AnnaBridge 171:3a7713b1edbc 790
AnnaBridge 171:3a7713b1edbc 791 #if defined(FLASH_OBR_nRST_BFB2)
AnnaBridge 171:3a7713b1edbc 792
AnnaBridge 171:3a7713b1edbc 793 /** @defgroup FLASHEx_Option_Bytes_BOOT FLASHEx Option Bytes BOOT
AnnaBridge 171:3a7713b1edbc 794 * @{
AnnaBridge 171:3a7713b1edbc 795 */
AnnaBridge 171:3a7713b1edbc 796
AnnaBridge 171:3a7713b1edbc 797 #define OB_BOOT_BANK2 ((uint8_t)0x00U) /*!< At startup, if boot pins are set in boot from user Flash position
AnnaBridge 171:3a7713b1edbc 798 and this parameter is selected the device will boot from Bank 2
AnnaBridge 171:3a7713b1edbc 799 or Bank 1, depending on the activation of the bank */
AnnaBridge 171:3a7713b1edbc 800 #define OB_BOOT_BANK1 ((uint8_t)(FLASH_OBR_nRST_BFB2 >> 16U)) /*!< At startup, if boot pins are set in boot from user Flash position
AnnaBridge 171:3a7713b1edbc 801 and this parameter is selected the device will boot from Bank1(Default) */
AnnaBridge 171:3a7713b1edbc 802
AnnaBridge 171:3a7713b1edbc 803 /**
AnnaBridge 171:3a7713b1edbc 804 * @}
AnnaBridge 171:3a7713b1edbc 805 */
AnnaBridge 171:3a7713b1edbc 806 #endif /* FLASH_OBR_nRST_BFB2 */
AnnaBridge 171:3a7713b1edbc 807
AnnaBridge 171:3a7713b1edbc 808 /**
AnnaBridge 171:3a7713b1edbc 809 * @}
AnnaBridge 171:3a7713b1edbc 810 */
AnnaBridge 171:3a7713b1edbc 811
AnnaBridge 171:3a7713b1edbc 812 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 813
AnnaBridge 171:3a7713b1edbc 814 /** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros
AnnaBridge 171:3a7713b1edbc 815 * @{
AnnaBridge 171:3a7713b1edbc 816 */
AnnaBridge 171:3a7713b1edbc 817
AnnaBridge 171:3a7713b1edbc 818 /**
AnnaBridge 171:3a7713b1edbc 819 * @brief Set the FLASH Latency.
AnnaBridge 171:3a7713b1edbc 820 * @param __LATENCY__ FLASH Latency
AnnaBridge 171:3a7713b1edbc 821 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 822 * @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle
AnnaBridge 171:3a7713b1edbc 823 * @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle
AnnaBridge 171:3a7713b1edbc 824 * @retval none
AnnaBridge 171:3a7713b1edbc 825 */
AnnaBridge 171:3a7713b1edbc 826 #define __HAL_FLASH_SET_LATENCY(__LATENCY__) do { \
AnnaBridge 171:3a7713b1edbc 827 if ((__LATENCY__) == FLASH_LATENCY_1) {__HAL_FLASH_ACC64_ENABLE();} \
AnnaBridge 171:3a7713b1edbc 828 MODIFY_REG((FLASH->ACR), FLASH_ACR_LATENCY, (__LATENCY__)); \
AnnaBridge 171:3a7713b1edbc 829 } while(0U)
AnnaBridge 171:3a7713b1edbc 830
AnnaBridge 171:3a7713b1edbc 831 /**
AnnaBridge 171:3a7713b1edbc 832 * @brief Get the FLASH Latency.
AnnaBridge 171:3a7713b1edbc 833 * @retval FLASH Latency
AnnaBridge 171:3a7713b1edbc 834 * This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 835 * @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle
AnnaBridge 171:3a7713b1edbc 836 * @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle
AnnaBridge 171:3a7713b1edbc 837 */
AnnaBridge 171:3a7713b1edbc 838 #define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
AnnaBridge 171:3a7713b1edbc 839
AnnaBridge 171:3a7713b1edbc 840 /**
AnnaBridge 171:3a7713b1edbc 841 * @brief Enable the FLASH 64-bit access.
AnnaBridge 171:3a7713b1edbc 842 * @note Read access 64 bit is used.
AnnaBridge 171:3a7713b1edbc 843 * @note This bit cannot be written at the same time as the LATENCY and
AnnaBridge 171:3a7713b1edbc 844 * PRFTEN bits.
AnnaBridge 171:3a7713b1edbc 845 * @retval none
AnnaBridge 171:3a7713b1edbc 846 */
AnnaBridge 171:3a7713b1edbc 847 #define __HAL_FLASH_ACC64_ENABLE() (SET_BIT((FLASH->ACR), FLASH_ACR_ACC64))
AnnaBridge 171:3a7713b1edbc 848
AnnaBridge 171:3a7713b1edbc 849 /**
AnnaBridge 171:3a7713b1edbc 850 * @brief Disable the FLASH 64-bit access.
AnnaBridge 171:3a7713b1edbc 851 * @note Read access 32 bit is used
AnnaBridge 171:3a7713b1edbc 852 * @note To reset this bit, the LATENCY should be zero wait state and the
AnnaBridge 171:3a7713b1edbc 853 * prefetch off.
AnnaBridge 171:3a7713b1edbc 854 * @retval none
AnnaBridge 171:3a7713b1edbc 855 */
AnnaBridge 171:3a7713b1edbc 856 #define __HAL_FLASH_ACC64_DISABLE() (CLEAR_BIT((FLASH->ACR), FLASH_ACR_ACC64))
AnnaBridge 171:3a7713b1edbc 857
AnnaBridge 171:3a7713b1edbc 858 /**
AnnaBridge 171:3a7713b1edbc 859 * @brief Enable the FLASH prefetch buffer.
AnnaBridge 171:3a7713b1edbc 860 * @retval none
AnnaBridge 171:3a7713b1edbc 861 */
AnnaBridge 171:3a7713b1edbc 862 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() do { __HAL_FLASH_ACC64_ENABLE(); \
AnnaBridge 171:3a7713b1edbc 863 SET_BIT((FLASH->ACR), FLASH_ACR_PRFTEN); \
AnnaBridge 171:3a7713b1edbc 864 } while(0U)
AnnaBridge 171:3a7713b1edbc 865
AnnaBridge 171:3a7713b1edbc 866 /**
AnnaBridge 171:3a7713b1edbc 867 * @brief Disable the FLASH prefetch buffer.
AnnaBridge 171:3a7713b1edbc 868 * @retval none
AnnaBridge 171:3a7713b1edbc 869 */
AnnaBridge 171:3a7713b1edbc 870 #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_PRFTEN)
AnnaBridge 171:3a7713b1edbc 871
AnnaBridge 171:3a7713b1edbc 872 /**
AnnaBridge 171:3a7713b1edbc 873 * @brief Enable the FLASH power down during Sleep mode
AnnaBridge 171:3a7713b1edbc 874 * @retval none
AnnaBridge 171:3a7713b1edbc 875 */
AnnaBridge 171:3a7713b1edbc 876 #define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
AnnaBridge 171:3a7713b1edbc 877
AnnaBridge 171:3a7713b1edbc 878 /**
AnnaBridge 171:3a7713b1edbc 879 * @brief Disable the FLASH power down during Sleep mode
AnnaBridge 171:3a7713b1edbc 880 * @retval none
AnnaBridge 171:3a7713b1edbc 881 */
AnnaBridge 171:3a7713b1edbc 882 #define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
AnnaBridge 171:3a7713b1edbc 883
AnnaBridge 171:3a7713b1edbc 884 /**
AnnaBridge 171:3a7713b1edbc 885 * @brief Enable the Flash Run power down mode.
AnnaBridge 171:3a7713b1edbc 886 * @note Writing this bit to 0 this bit, automatically the keys are
AnnaBridge 171:3a7713b1edbc 887 * loss and a new unlock sequence is necessary to re-write it to 1.
AnnaBridge 171:3a7713b1edbc 888 */
AnnaBridge 171:3a7713b1edbc 889 #define __HAL_FLASH_POWER_DOWN_ENABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \
AnnaBridge 171:3a7713b1edbc 890 FLASH->PDKEYR = FLASH_PDKEY2; \
AnnaBridge 171:3a7713b1edbc 891 SET_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \
AnnaBridge 171:3a7713b1edbc 892 } while (0U)
AnnaBridge 171:3a7713b1edbc 893
AnnaBridge 171:3a7713b1edbc 894 /**
AnnaBridge 171:3a7713b1edbc 895 * @brief Disable the Flash Run power down mode.
AnnaBridge 171:3a7713b1edbc 896 * @note Writing this bit to 0 this bit, automatically the keys are
AnnaBridge 171:3a7713b1edbc 897 * loss and a new unlock sequence is necessary to re-write it to 1.
AnnaBridge 171:3a7713b1edbc 898 */
AnnaBridge 171:3a7713b1edbc 899 #define __HAL_FLASH_POWER_DOWN_DISABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \
AnnaBridge 171:3a7713b1edbc 900 FLASH->PDKEYR = FLASH_PDKEY2; \
AnnaBridge 171:3a7713b1edbc 901 CLEAR_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \
AnnaBridge 171:3a7713b1edbc 902 } while (0U)
AnnaBridge 171:3a7713b1edbc 903
AnnaBridge 171:3a7713b1edbc 904 /**
AnnaBridge 171:3a7713b1edbc 905 * @}
AnnaBridge 171:3a7713b1edbc 906 */
AnnaBridge 171:3a7713b1edbc 907
AnnaBridge 171:3a7713b1edbc 908 /* Exported functions --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 909
AnnaBridge 171:3a7713b1edbc 910 /** @addtogroup FLASHEx_Exported_Functions
AnnaBridge 171:3a7713b1edbc 911 * @{
AnnaBridge 171:3a7713b1edbc 912 */
AnnaBridge 171:3a7713b1edbc 913
AnnaBridge 171:3a7713b1edbc 914 /** @addtogroup FLASHEx_Exported_Functions_Group1
AnnaBridge 171:3a7713b1edbc 915 * @{
AnnaBridge 171:3a7713b1edbc 916 */
AnnaBridge 171:3a7713b1edbc 917
AnnaBridge 171:3a7713b1edbc 918 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
AnnaBridge 171:3a7713b1edbc 919 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
AnnaBridge 171:3a7713b1edbc 920
AnnaBridge 171:3a7713b1edbc 921 /**
AnnaBridge 171:3a7713b1edbc 922 * @}
AnnaBridge 171:3a7713b1edbc 923 */
AnnaBridge 171:3a7713b1edbc 924
AnnaBridge 171:3a7713b1edbc 925 /** @addtogroup FLASHEx_Exported_Functions_Group2
AnnaBridge 171:3a7713b1edbc 926 * @{
AnnaBridge 171:3a7713b1edbc 927 */
AnnaBridge 171:3a7713b1edbc 928
AnnaBridge 171:3a7713b1edbc 929 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
AnnaBridge 171:3a7713b1edbc 930 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
AnnaBridge 171:3a7713b1edbc 931
AnnaBridge 171:3a7713b1edbc 932 #if defined(FLASH_OBR_SPRMOD) || defined(FLASH_OBR_nRST_BFB2)
AnnaBridge 171:3a7713b1edbc 933
AnnaBridge 171:3a7713b1edbc 934 HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
AnnaBridge 171:3a7713b1edbc 935 void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
AnnaBridge 171:3a7713b1edbc 936
AnnaBridge 171:3a7713b1edbc 937 #endif /* FLASH_OBR_SPRMOD || FLASH_OBR_nRST_BFB2 */
AnnaBridge 171:3a7713b1edbc 938
AnnaBridge 171:3a7713b1edbc 939 #if defined(FLASH_OBR_SPRMOD)
AnnaBridge 171:3a7713b1edbc 940
AnnaBridge 171:3a7713b1edbc 941 HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void);
AnnaBridge 171:3a7713b1edbc 942 HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void);
AnnaBridge 171:3a7713b1edbc 943
AnnaBridge 171:3a7713b1edbc 944 #endif /* FLASH_OBR_SPRMOD */
AnnaBridge 171:3a7713b1edbc 945
AnnaBridge 171:3a7713b1edbc 946 /**
AnnaBridge 171:3a7713b1edbc 947 * @}
AnnaBridge 171:3a7713b1edbc 948 */
AnnaBridge 171:3a7713b1edbc 949
AnnaBridge 171:3a7713b1edbc 950 /** @addtogroup FLASHEx_Exported_Functions_Group3
AnnaBridge 171:3a7713b1edbc 951 * @{
AnnaBridge 171:3a7713b1edbc 952 */
AnnaBridge 171:3a7713b1edbc 953
AnnaBridge 171:3a7713b1edbc 954 HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Unlock(void);
AnnaBridge 171:3a7713b1edbc 955 HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Lock(void);
AnnaBridge 171:3a7713b1edbc 956
AnnaBridge 171:3a7713b1edbc 957 HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t TypeErase, uint32_t Address);
AnnaBridge 171:3a7713b1edbc 958 HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data);
AnnaBridge 171:3a7713b1edbc 959 void HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram(void);
AnnaBridge 171:3a7713b1edbc 960 void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void);
AnnaBridge 171:3a7713b1edbc 961
AnnaBridge 171:3a7713b1edbc 962 /**
AnnaBridge 171:3a7713b1edbc 963 * @}
AnnaBridge 171:3a7713b1edbc 964 */
AnnaBridge 171:3a7713b1edbc 965
AnnaBridge 171:3a7713b1edbc 966 /**
AnnaBridge 171:3a7713b1edbc 967 * @}
AnnaBridge 171:3a7713b1edbc 968 */
AnnaBridge 171:3a7713b1edbc 969
AnnaBridge 171:3a7713b1edbc 970 /**
AnnaBridge 171:3a7713b1edbc 971 * @}
AnnaBridge 171:3a7713b1edbc 972 */
AnnaBridge 171:3a7713b1edbc 973
AnnaBridge 171:3a7713b1edbc 974 /**
AnnaBridge 171:3a7713b1edbc 975 * @}
AnnaBridge 171:3a7713b1edbc 976 */
AnnaBridge 171:3a7713b1edbc 977
AnnaBridge 171:3a7713b1edbc 978 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 979 }
AnnaBridge 171:3a7713b1edbc 980 #endif
AnnaBridge 171:3a7713b1edbc 981
AnnaBridge 171:3a7713b1edbc 982 #endif /* __STM32L1xx_HAL_FLASH_EX_H */
AnnaBridge 171:3a7713b1edbc 983
AnnaBridge 171:3a7713b1edbc 984 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/