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TARGET_MOTE_L152RC/TOOLCHAIN_IAR/stm32l152xc.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file stm32l152xc.h
AnnaBridge 171:3a7713b1edbc 4 * @author MCD Application Team
AnnaBridge 171:3a7713b1edbc 5 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
AnnaBridge 171:3a7713b1edbc 6 * This file contains all the peripheral register's definitions, bits
AnnaBridge 171:3a7713b1edbc 7 * definitions and memory mapping for STM32L1xx devices.
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 * This file contains:
AnnaBridge 171:3a7713b1edbc 10 * - Data structures and the address mapping for all peripherals
AnnaBridge 171:3a7713b1edbc 11 * - Peripheral's registers declarations and bits definition
AnnaBridge 171:3a7713b1edbc 12 * - Macros to access peripheral’s registers hardware
AnnaBridge 171:3a7713b1edbc 13 *
AnnaBridge 171:3a7713b1edbc 14 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 15 * @attention
AnnaBridge 171:3a7713b1edbc 16 *
AnnaBridge 171:3a7713b1edbc 17 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 171:3a7713b1edbc 18 *
AnnaBridge 171:3a7713b1edbc 19 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 20 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 21 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 22 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 24 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 25 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 171:3a7713b1edbc 27 * may be used to endorse or promote products derived from this software
AnnaBridge 171:3a7713b1edbc 28 * without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 29 *
AnnaBridge 171:3a7713b1edbc 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 171:3a7713b1edbc 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 171:3a7713b1edbc 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 171:3a7713b1edbc 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 171:3a7713b1edbc 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 171:3a7713b1edbc 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 171:3a7713b1edbc 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 171:3a7713b1edbc 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 40 *
AnnaBridge 171:3a7713b1edbc 41 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 42 */
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 /** @addtogroup CMSIS
AnnaBridge 171:3a7713b1edbc 45 * @{
AnnaBridge 171:3a7713b1edbc 46 */
AnnaBridge 171:3a7713b1edbc 47
AnnaBridge 171:3a7713b1edbc 48 /** @addtogroup stm32l152xc
AnnaBridge 171:3a7713b1edbc 49 * @{
AnnaBridge 171:3a7713b1edbc 50 */
AnnaBridge 171:3a7713b1edbc 51
AnnaBridge 171:3a7713b1edbc 52 #ifndef __STM32L152xC_H
AnnaBridge 171:3a7713b1edbc 53 #define __STM32L152xC_H
AnnaBridge 171:3a7713b1edbc 54
AnnaBridge 171:3a7713b1edbc 55 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 56 extern "C" {
AnnaBridge 171:3a7713b1edbc 57 #endif
AnnaBridge 171:3a7713b1edbc 58
AnnaBridge 171:3a7713b1edbc 59
AnnaBridge 171:3a7713b1edbc 60 /** @addtogroup Configuration_section_for_CMSIS
AnnaBridge 171:3a7713b1edbc 61 * @{
AnnaBridge 171:3a7713b1edbc 62 */
AnnaBridge 171:3a7713b1edbc 63 /**
AnnaBridge 171:3a7713b1edbc 64 * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
AnnaBridge 171:3a7713b1edbc 65 */
AnnaBridge 171:3a7713b1edbc 66 #define __CM3_REV 0x200U /*!< Cortex-M3 Revision r2p0 */
AnnaBridge 171:3a7713b1edbc 67 #define __MPU_PRESENT 1U /*!< STM32L1xx provides MPU */
AnnaBridge 171:3a7713b1edbc 68 #define __NVIC_PRIO_BITS 4U /*!< STM32L1xx uses 4 Bits for the Priority Levels */
AnnaBridge 171:3a7713b1edbc 69 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
AnnaBridge 171:3a7713b1edbc 70
AnnaBridge 171:3a7713b1edbc 71 /**
AnnaBridge 171:3a7713b1edbc 72 * @}
AnnaBridge 171:3a7713b1edbc 73 */
AnnaBridge 171:3a7713b1edbc 74
AnnaBridge 171:3a7713b1edbc 75 /** @addtogroup Peripheral_interrupt_number_definition
AnnaBridge 171:3a7713b1edbc 76 * @{
AnnaBridge 171:3a7713b1edbc 77 */
AnnaBridge 171:3a7713b1edbc 78
AnnaBridge 171:3a7713b1edbc 79 /**
AnnaBridge 171:3a7713b1edbc 80 * @brief STM32L1xx Interrupt Number Definition, according to the selected device
AnnaBridge 171:3a7713b1edbc 81 * in @ref Library_configuration_section
AnnaBridge 171:3a7713b1edbc 82 */
AnnaBridge 171:3a7713b1edbc 83
AnnaBridge 171:3a7713b1edbc 84 /*!< Interrupt Number Definition */
AnnaBridge 171:3a7713b1edbc 85 typedef enum
AnnaBridge 171:3a7713b1edbc 86 {
AnnaBridge 171:3a7713b1edbc 87 /****** Cortex-M3 Processor Exceptions Numbers ******************************************************/
AnnaBridge 171:3a7713b1edbc 88 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
AnnaBridge 171:3a7713b1edbc 89 HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 90 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
AnnaBridge 171:3a7713b1edbc 91 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 92 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 93 SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
AnnaBridge 171:3a7713b1edbc 94 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
AnnaBridge 171:3a7713b1edbc 95 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
AnnaBridge 171:3a7713b1edbc 96 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
AnnaBridge 171:3a7713b1edbc 97
AnnaBridge 171:3a7713b1edbc 98 /****** STM32L specific Interrupt Numbers ***********************************************************/
AnnaBridge 171:3a7713b1edbc 99 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
AnnaBridge 171:3a7713b1edbc 100 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
AnnaBridge 171:3a7713b1edbc 101 TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
AnnaBridge 171:3a7713b1edbc 102 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */
AnnaBridge 171:3a7713b1edbc 103 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
AnnaBridge 171:3a7713b1edbc 104 RCC_IRQn = 5, /*!< RCC global Interrupt */
AnnaBridge 171:3a7713b1edbc 105 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
AnnaBridge 171:3a7713b1edbc 106 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
AnnaBridge 171:3a7713b1edbc 107 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
AnnaBridge 171:3a7713b1edbc 108 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
AnnaBridge 171:3a7713b1edbc 109 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
AnnaBridge 171:3a7713b1edbc 110 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
AnnaBridge 171:3a7713b1edbc 111 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
AnnaBridge 171:3a7713b1edbc 112 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
AnnaBridge 171:3a7713b1edbc 113 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
AnnaBridge 171:3a7713b1edbc 114 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
AnnaBridge 171:3a7713b1edbc 115 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
AnnaBridge 171:3a7713b1edbc 116 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
AnnaBridge 171:3a7713b1edbc 117 ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
AnnaBridge 171:3a7713b1edbc 118 USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */
AnnaBridge 171:3a7713b1edbc 119 USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */
AnnaBridge 171:3a7713b1edbc 120 DAC_IRQn = 21, /*!< DAC Interrupt */
AnnaBridge 171:3a7713b1edbc 121 COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */
AnnaBridge 171:3a7713b1edbc 122 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
AnnaBridge 171:3a7713b1edbc 123 LCD_IRQn = 24, /*!< LCD Interrupt */
AnnaBridge 171:3a7713b1edbc 124 TIM9_IRQn = 25, /*!< TIM9 global Interrupt */
AnnaBridge 171:3a7713b1edbc 125 TIM10_IRQn = 26, /*!< TIM10 global Interrupt */
AnnaBridge 171:3a7713b1edbc 126 TIM11_IRQn = 27, /*!< TIM11 global Interrupt */
AnnaBridge 171:3a7713b1edbc 127 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
AnnaBridge 171:3a7713b1edbc 128 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
AnnaBridge 171:3a7713b1edbc 129 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
AnnaBridge 171:3a7713b1edbc 130 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
AnnaBridge 171:3a7713b1edbc 131 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
AnnaBridge 171:3a7713b1edbc 132 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
AnnaBridge 171:3a7713b1edbc 133 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
AnnaBridge 171:3a7713b1edbc 134 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
AnnaBridge 171:3a7713b1edbc 135 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
AnnaBridge 171:3a7713b1edbc 136 USART1_IRQn = 37, /*!< USART1 global Interrupt */
AnnaBridge 171:3a7713b1edbc 137 USART2_IRQn = 38, /*!< USART2 global Interrupt */
AnnaBridge 171:3a7713b1edbc 138 USART3_IRQn = 39, /*!< USART3 global Interrupt */
AnnaBridge 171:3a7713b1edbc 139 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
AnnaBridge 171:3a7713b1edbc 140 RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
AnnaBridge 171:3a7713b1edbc 141 USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */
AnnaBridge 171:3a7713b1edbc 142 TIM6_IRQn = 43, /*!< TIM6 global Interrupt */
AnnaBridge 171:3a7713b1edbc 143 TIM7_IRQn = 44, /*!< TIM7 global Interrupt */
AnnaBridge 171:3a7713b1edbc 144 TIM5_IRQn = 46, /*!< TIM5 global Interrupt */
AnnaBridge 171:3a7713b1edbc 145 SPI3_IRQn = 47, /*!< SPI3 global Interrupt */
AnnaBridge 171:3a7713b1edbc 146 DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */
AnnaBridge 171:3a7713b1edbc 147 DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */
AnnaBridge 171:3a7713b1edbc 148 DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */
AnnaBridge 171:3a7713b1edbc 149 DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */
AnnaBridge 171:3a7713b1edbc 150 DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */
AnnaBridge 171:3a7713b1edbc 151 COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */
AnnaBridge 171:3a7713b1edbc 152 } IRQn_Type;
AnnaBridge 171:3a7713b1edbc 153
AnnaBridge 171:3a7713b1edbc 154 /**
AnnaBridge 171:3a7713b1edbc 155 * @}
AnnaBridge 171:3a7713b1edbc 156 */
AnnaBridge 171:3a7713b1edbc 157
AnnaBridge 171:3a7713b1edbc 158 #include "core_cm3.h"
AnnaBridge 171:3a7713b1edbc 159 #include "system_stm32l1xx.h"
AnnaBridge 171:3a7713b1edbc 160 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 161
AnnaBridge 171:3a7713b1edbc 162 /** @addtogroup Peripheral_registers_structures
AnnaBridge 171:3a7713b1edbc 163 * @{
AnnaBridge 171:3a7713b1edbc 164 */
AnnaBridge 171:3a7713b1edbc 165
AnnaBridge 171:3a7713b1edbc 166 /**
AnnaBridge 171:3a7713b1edbc 167 * @brief Analog to Digital Converter
AnnaBridge 171:3a7713b1edbc 168 */
AnnaBridge 171:3a7713b1edbc 169
AnnaBridge 171:3a7713b1edbc 170 typedef struct
AnnaBridge 171:3a7713b1edbc 171 {
AnnaBridge 171:3a7713b1edbc 172 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 173 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 174 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 175 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 176 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 177 __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 178 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 179 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 180 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 181 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 182 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 183 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 184 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 185 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 186 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 187 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 188 __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 189 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 190 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 191 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 192 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 193 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 194 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */
AnnaBridge 171:3a7713b1edbc 195 uint32_t RESERVED; /*!< Reserved, Address offset: 0x5C */
AnnaBridge 171:3a7713b1edbc 196 } ADC_TypeDef;
AnnaBridge 171:3a7713b1edbc 197
AnnaBridge 171:3a7713b1edbc 198 typedef struct
AnnaBridge 171:3a7713b1edbc 199 {
AnnaBridge 171:3a7713b1edbc 200 __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */
AnnaBridge 171:3a7713b1edbc 201 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
AnnaBridge 171:3a7713b1edbc 202 } ADC_Common_TypeDef;
AnnaBridge 171:3a7713b1edbc 203
AnnaBridge 171:3a7713b1edbc 204 /**
AnnaBridge 171:3a7713b1edbc 205 * @brief Comparator
AnnaBridge 171:3a7713b1edbc 206 */
AnnaBridge 171:3a7713b1edbc 207
AnnaBridge 171:3a7713b1edbc 208 typedef struct
AnnaBridge 171:3a7713b1edbc 209 {
AnnaBridge 171:3a7713b1edbc 210 __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 211 } COMP_TypeDef;
AnnaBridge 171:3a7713b1edbc 212
AnnaBridge 171:3a7713b1edbc 213 typedef struct
AnnaBridge 171:3a7713b1edbc 214 {
AnnaBridge 171:3a7713b1edbc 215 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 216 } COMP_Common_TypeDef;
AnnaBridge 171:3a7713b1edbc 217
AnnaBridge 171:3a7713b1edbc 218 /**
AnnaBridge 171:3a7713b1edbc 219 * @brief CRC calculation unit
AnnaBridge 171:3a7713b1edbc 220 */
AnnaBridge 171:3a7713b1edbc 221
AnnaBridge 171:3a7713b1edbc 222 typedef struct
AnnaBridge 171:3a7713b1edbc 223 {
AnnaBridge 171:3a7713b1edbc 224 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 225 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 226 uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */
AnnaBridge 171:3a7713b1edbc 227 uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */
AnnaBridge 171:3a7713b1edbc 228 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 229 } CRC_TypeDef;
AnnaBridge 171:3a7713b1edbc 230
AnnaBridge 171:3a7713b1edbc 231 /**
AnnaBridge 171:3a7713b1edbc 232 * @brief Digital to Analog Converter
AnnaBridge 171:3a7713b1edbc 233 */
AnnaBridge 171:3a7713b1edbc 234
AnnaBridge 171:3a7713b1edbc 235 typedef struct
AnnaBridge 171:3a7713b1edbc 236 {
AnnaBridge 171:3a7713b1edbc 237 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 238 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 239 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 240 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 241 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 242 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 243 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 244 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 245 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 246 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 247 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 248 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 249 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 250 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 251 } DAC_TypeDef;
AnnaBridge 171:3a7713b1edbc 252
AnnaBridge 171:3a7713b1edbc 253 /**
AnnaBridge 171:3a7713b1edbc 254 * @brief Debug MCU
AnnaBridge 171:3a7713b1edbc 255 */
AnnaBridge 171:3a7713b1edbc 256
AnnaBridge 171:3a7713b1edbc 257 typedef struct
AnnaBridge 171:3a7713b1edbc 258 {
AnnaBridge 171:3a7713b1edbc 259 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 260 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 261 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 262 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 263 }DBGMCU_TypeDef;
AnnaBridge 171:3a7713b1edbc 264
AnnaBridge 171:3a7713b1edbc 265 /**
AnnaBridge 171:3a7713b1edbc 266 * @brief DMA Controller
AnnaBridge 171:3a7713b1edbc 267 */
AnnaBridge 171:3a7713b1edbc 268
AnnaBridge 171:3a7713b1edbc 269 typedef struct
AnnaBridge 171:3a7713b1edbc 270 {
AnnaBridge 171:3a7713b1edbc 271 __IO uint32_t CCR; /*!< DMA channel x configuration register */
AnnaBridge 171:3a7713b1edbc 272 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
AnnaBridge 171:3a7713b1edbc 273 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
AnnaBridge 171:3a7713b1edbc 274 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
AnnaBridge 171:3a7713b1edbc 275 } DMA_Channel_TypeDef;
AnnaBridge 171:3a7713b1edbc 276
AnnaBridge 171:3a7713b1edbc 277 typedef struct
AnnaBridge 171:3a7713b1edbc 278 {
AnnaBridge 171:3a7713b1edbc 279 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 280 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 281 } DMA_TypeDef;
AnnaBridge 171:3a7713b1edbc 282
AnnaBridge 171:3a7713b1edbc 283 /**
AnnaBridge 171:3a7713b1edbc 284 * @brief External Interrupt/Event Controller
AnnaBridge 171:3a7713b1edbc 285 */
AnnaBridge 171:3a7713b1edbc 286
AnnaBridge 171:3a7713b1edbc 287 typedef struct
AnnaBridge 171:3a7713b1edbc 288 {
AnnaBridge 171:3a7713b1edbc 289 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 290 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 291 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 292 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 293 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 294 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 295 } EXTI_TypeDef;
AnnaBridge 171:3a7713b1edbc 296
AnnaBridge 171:3a7713b1edbc 297 /**
AnnaBridge 171:3a7713b1edbc 298 * @brief FLASH Registers
AnnaBridge 171:3a7713b1edbc 299 */
AnnaBridge 171:3a7713b1edbc 300 typedef struct
AnnaBridge 171:3a7713b1edbc 301 {
AnnaBridge 171:3a7713b1edbc 302 __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 303 __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 304 __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 305 __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
AnnaBridge 171:3a7713b1edbc 306 __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 307 __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 308 __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 309 __IO uint32_t OBR; /*!< Option byte register, Address offset: 0x1c */
AnnaBridge 171:3a7713b1edbc 310 __IO uint32_t WRPR1; /*!< Write protection register 1, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 311 uint32_t RESERVED[23]; /*!< Reserved, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 312 __IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 313 } FLASH_TypeDef;
AnnaBridge 171:3a7713b1edbc 314
AnnaBridge 171:3a7713b1edbc 315 /**
AnnaBridge 171:3a7713b1edbc 316 * @brief Option Bytes Registers
AnnaBridge 171:3a7713b1edbc 317 */
AnnaBridge 171:3a7713b1edbc 318 typedef struct
AnnaBridge 171:3a7713b1edbc 319 {
AnnaBridge 171:3a7713b1edbc 320 __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 321 __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 322 __IO uint32_t WRP01; /*!< write protection register 0 1, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 323 __IO uint32_t WRP23; /*!< write protection register 2 3, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 324 __IO uint32_t WRP45; /*!< write protection register 4 5, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 325 __IO uint32_t WRP67; /*!< write protection register 6 7, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 326 } OB_TypeDef;
AnnaBridge 171:3a7713b1edbc 327
AnnaBridge 171:3a7713b1edbc 328 /**
AnnaBridge 171:3a7713b1edbc 329 * @brief Operational Amplifier (OPAMP)
AnnaBridge 171:3a7713b1edbc 330 */
AnnaBridge 171:3a7713b1edbc 331 typedef struct
AnnaBridge 171:3a7713b1edbc 332 {
AnnaBridge 171:3a7713b1edbc 333 __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 334 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 335 __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 336 } OPAMP_TypeDef;
AnnaBridge 171:3a7713b1edbc 337
AnnaBridge 171:3a7713b1edbc 338 typedef struct
AnnaBridge 171:3a7713b1edbc 339 {
AnnaBridge 171:3a7713b1edbc 340 __IO uint32_t CSR; /*!< OPAMP control and status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 341 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, used for bits common to several OPAMP instances, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 342 } OPAMP_Common_TypeDef;
AnnaBridge 171:3a7713b1edbc 343
AnnaBridge 171:3a7713b1edbc 344 /**
AnnaBridge 171:3a7713b1edbc 345 * @brief General Purpose IO
AnnaBridge 171:3a7713b1edbc 346 */
AnnaBridge 171:3a7713b1edbc 347
AnnaBridge 171:3a7713b1edbc 348 typedef struct
AnnaBridge 171:3a7713b1edbc 349 {
AnnaBridge 171:3a7713b1edbc 350 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 351 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 352 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 353 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 354 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 355 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 356 __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 357 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 358 __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
AnnaBridge 171:3a7713b1edbc 359 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 360 } GPIO_TypeDef;
AnnaBridge 171:3a7713b1edbc 361
AnnaBridge 171:3a7713b1edbc 362 /**
AnnaBridge 171:3a7713b1edbc 363 * @brief SysTem Configuration
AnnaBridge 171:3a7713b1edbc 364 */
AnnaBridge 171:3a7713b1edbc 365
AnnaBridge 171:3a7713b1edbc 366 typedef struct
AnnaBridge 171:3a7713b1edbc 367 {
AnnaBridge 171:3a7713b1edbc 368 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 369 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 370 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
AnnaBridge 171:3a7713b1edbc 371 } SYSCFG_TypeDef;
AnnaBridge 171:3a7713b1edbc 372
AnnaBridge 171:3a7713b1edbc 373 /**
AnnaBridge 171:3a7713b1edbc 374 * @brief Inter-integrated Circuit Interface
AnnaBridge 171:3a7713b1edbc 375 */
AnnaBridge 171:3a7713b1edbc 376
AnnaBridge 171:3a7713b1edbc 377 typedef struct
AnnaBridge 171:3a7713b1edbc 378 {
AnnaBridge 171:3a7713b1edbc 379 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 380 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 381 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 382 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 383 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 384 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 385 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 386 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 387 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 388 } I2C_TypeDef;
AnnaBridge 171:3a7713b1edbc 389
AnnaBridge 171:3a7713b1edbc 390 /**
AnnaBridge 171:3a7713b1edbc 391 * @brief Independent WATCHDOG
AnnaBridge 171:3a7713b1edbc 392 */
AnnaBridge 171:3a7713b1edbc 393
AnnaBridge 171:3a7713b1edbc 394 typedef struct
AnnaBridge 171:3a7713b1edbc 395 {
AnnaBridge 171:3a7713b1edbc 396 __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 397 __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 398 __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 399 __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 400 } IWDG_TypeDef;
AnnaBridge 171:3a7713b1edbc 401
AnnaBridge 171:3a7713b1edbc 402 /**
AnnaBridge 171:3a7713b1edbc 403 * @brief LCD
AnnaBridge 171:3a7713b1edbc 404 */
AnnaBridge 171:3a7713b1edbc 405
AnnaBridge 171:3a7713b1edbc 406 typedef struct
AnnaBridge 171:3a7713b1edbc 407 {
AnnaBridge 171:3a7713b1edbc 408 __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 409 __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 410 __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 411 __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 412 uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 413 __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */
AnnaBridge 171:3a7713b1edbc 414 } LCD_TypeDef;
AnnaBridge 171:3a7713b1edbc 415
AnnaBridge 171:3a7713b1edbc 416 /**
AnnaBridge 171:3a7713b1edbc 417 * @brief Power Control
AnnaBridge 171:3a7713b1edbc 418 */
AnnaBridge 171:3a7713b1edbc 419
AnnaBridge 171:3a7713b1edbc 420 typedef struct
AnnaBridge 171:3a7713b1edbc 421 {
AnnaBridge 171:3a7713b1edbc 422 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 423 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 424 } PWR_TypeDef;
AnnaBridge 171:3a7713b1edbc 425
AnnaBridge 171:3a7713b1edbc 426 /**
AnnaBridge 171:3a7713b1edbc 427 * @brief Reset and Clock Control
AnnaBridge 171:3a7713b1edbc 428 */
AnnaBridge 171:3a7713b1edbc 429
AnnaBridge 171:3a7713b1edbc 430 typedef struct
AnnaBridge 171:3a7713b1edbc 431 {
AnnaBridge 171:3a7713b1edbc 432 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 433 __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 434 __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 435 __IO uint32_t CIR; /*!< RCC Clock interrupt register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 436 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 437 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 438 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 439 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 440 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 441 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 442 __IO uint32_t AHBLPENR; /*!< RCC AHB peripheral clock enable in low power mode register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 443 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 444 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 445 __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 446 } RCC_TypeDef;
AnnaBridge 171:3a7713b1edbc 447
AnnaBridge 171:3a7713b1edbc 448 /**
AnnaBridge 171:3a7713b1edbc 449 * @brief Routing Interface
AnnaBridge 171:3a7713b1edbc 450 */
AnnaBridge 171:3a7713b1edbc 451
AnnaBridge 171:3a7713b1edbc 452 typedef struct
AnnaBridge 171:3a7713b1edbc 453 {
AnnaBridge 171:3a7713b1edbc 454 __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 455 __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 456 __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 457 __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 458 __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 459 __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 460 __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 461 __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 462 __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 463 __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 464 __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 465 __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 466 __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 467 __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 468 __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 469 __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 470 __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 471 __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 472 __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 473 __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 474 __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 475 __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 476 } RI_TypeDef;
AnnaBridge 171:3a7713b1edbc 477
AnnaBridge 171:3a7713b1edbc 478 /**
AnnaBridge 171:3a7713b1edbc 479 * @brief Real-Time Clock
AnnaBridge 171:3a7713b1edbc 480 */
AnnaBridge 171:3a7713b1edbc 481 typedef struct
AnnaBridge 171:3a7713b1edbc 482 {
AnnaBridge 171:3a7713b1edbc 483 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 484 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 485 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 486 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 487 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 488 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 489 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 490 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 491 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 492 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 493 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 494 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 495 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 496 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 497 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 498 __IO uint32_t CALR; /*!< RRTC calibration register, Address offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 499 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 500 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 501 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 502 uint32_t RESERVED7; /*!< Reserved, 0x4C */
AnnaBridge 171:3a7713b1edbc 503 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 504 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 505 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
AnnaBridge 171:3a7713b1edbc 506 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
AnnaBridge 171:3a7713b1edbc 507 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 508 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
AnnaBridge 171:3a7713b1edbc 509 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
AnnaBridge 171:3a7713b1edbc 510 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
AnnaBridge 171:3a7713b1edbc 511 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
AnnaBridge 171:3a7713b1edbc 512 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
AnnaBridge 171:3a7713b1edbc 513 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
AnnaBridge 171:3a7713b1edbc 514 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
AnnaBridge 171:3a7713b1edbc 515 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 516 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 517 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
AnnaBridge 171:3a7713b1edbc 518 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
AnnaBridge 171:3a7713b1edbc 519 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
AnnaBridge 171:3a7713b1edbc 520 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
AnnaBridge 171:3a7713b1edbc 521 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
AnnaBridge 171:3a7713b1edbc 522 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
AnnaBridge 171:3a7713b1edbc 523 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
AnnaBridge 171:3a7713b1edbc 524 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
AnnaBridge 171:3a7713b1edbc 525 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
AnnaBridge 171:3a7713b1edbc 526 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
AnnaBridge 171:3a7713b1edbc 527 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
AnnaBridge 171:3a7713b1edbc 528 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
AnnaBridge 171:3a7713b1edbc 529 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
AnnaBridge 171:3a7713b1edbc 530 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
AnnaBridge 171:3a7713b1edbc 531 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
AnnaBridge 171:3a7713b1edbc 532 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
AnnaBridge 171:3a7713b1edbc 533 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
AnnaBridge 171:3a7713b1edbc 534 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
AnnaBridge 171:3a7713b1edbc 535 } RTC_TypeDef;
AnnaBridge 171:3a7713b1edbc 536
AnnaBridge 171:3a7713b1edbc 537 /**
AnnaBridge 171:3a7713b1edbc 538 * @brief Serial Peripheral Interface
AnnaBridge 171:3a7713b1edbc 539 */
AnnaBridge 171:3a7713b1edbc 540
AnnaBridge 171:3a7713b1edbc 541 typedef struct
AnnaBridge 171:3a7713b1edbc 542 {
AnnaBridge 171:3a7713b1edbc 543 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 544 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 545 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 546 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 547 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 548 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 549 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 550 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 551 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 552 } SPI_TypeDef;
AnnaBridge 171:3a7713b1edbc 553
AnnaBridge 171:3a7713b1edbc 554 /**
AnnaBridge 171:3a7713b1edbc 555 * @brief TIM
AnnaBridge 171:3a7713b1edbc 556 */
AnnaBridge 171:3a7713b1edbc 557 typedef struct
AnnaBridge 171:3a7713b1edbc 558 {
AnnaBridge 171:3a7713b1edbc 559 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 560 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 561 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 562 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 563 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 564 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 565 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 566 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 567 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 568 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 569 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 570 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 571 uint32_t RESERVED12; /*!< Reserved, 0x30 */
AnnaBridge 171:3a7713b1edbc 572 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 573 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 574 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 575 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 576 uint32_t RESERVED17; /*!< Reserved, 0x44 */
AnnaBridge 171:3a7713b1edbc 577 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 578 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 579 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 580 } TIM_TypeDef;
AnnaBridge 171:3a7713b1edbc 581 /**
AnnaBridge 171:3a7713b1edbc 582 * @brief Universal Synchronous Asynchronous Receiver Transmitter
AnnaBridge 171:3a7713b1edbc 583 */
AnnaBridge 171:3a7713b1edbc 584
AnnaBridge 171:3a7713b1edbc 585 typedef struct
AnnaBridge 171:3a7713b1edbc 586 {
AnnaBridge 171:3a7713b1edbc 587 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 588 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 589 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 590 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 591 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 592 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 593 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 594 } USART_TypeDef;
AnnaBridge 171:3a7713b1edbc 595
AnnaBridge 171:3a7713b1edbc 596 /**
AnnaBridge 171:3a7713b1edbc 597 * @brief Universal Serial Bus Full Speed Device
AnnaBridge 171:3a7713b1edbc 598 */
AnnaBridge 171:3a7713b1edbc 599
AnnaBridge 171:3a7713b1edbc 600 typedef struct
AnnaBridge 171:3a7713b1edbc 601 {
AnnaBridge 171:3a7713b1edbc 602 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 603 __IO uint16_t RESERVED0; /*!< Reserved */
AnnaBridge 171:3a7713b1edbc 604 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 605 __IO uint16_t RESERVED1; /*!< Reserved */
AnnaBridge 171:3a7713b1edbc 606 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 607 __IO uint16_t RESERVED2; /*!< Reserved */
AnnaBridge 171:3a7713b1edbc 608 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 609 __IO uint16_t RESERVED3; /*!< Reserved */
AnnaBridge 171:3a7713b1edbc 610 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 611 __IO uint16_t RESERVED4; /*!< Reserved */
AnnaBridge 171:3a7713b1edbc 612 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 613 __IO uint16_t RESERVED5; /*!< Reserved */
AnnaBridge 171:3a7713b1edbc 614 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 615 __IO uint16_t RESERVED6; /*!< Reserved */
AnnaBridge 171:3a7713b1edbc 616 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 617 __IO uint16_t RESERVED7[17]; /*!< Reserved */
AnnaBridge 171:3a7713b1edbc 618 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 619 __IO uint16_t RESERVED8; /*!< Reserved */
AnnaBridge 171:3a7713b1edbc 620 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 621 __IO uint16_t RESERVED9; /*!< Reserved */
AnnaBridge 171:3a7713b1edbc 622 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 623 __IO uint16_t RESERVEDA; /*!< Reserved */
AnnaBridge 171:3a7713b1edbc 624 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 625 __IO uint16_t RESERVEDB; /*!< Reserved */
AnnaBridge 171:3a7713b1edbc 626 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 627 __IO uint16_t RESERVEDC; /*!< Reserved */
AnnaBridge 171:3a7713b1edbc 628 } USB_TypeDef;
AnnaBridge 171:3a7713b1edbc 629
AnnaBridge 171:3a7713b1edbc 630 /**
AnnaBridge 171:3a7713b1edbc 631 * @brief Window WATCHDOG
AnnaBridge 171:3a7713b1edbc 632 */
AnnaBridge 171:3a7713b1edbc 633 typedef struct
AnnaBridge 171:3a7713b1edbc 634 {
AnnaBridge 171:3a7713b1edbc 635 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 636 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 637 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 638 } WWDG_TypeDef;
AnnaBridge 171:3a7713b1edbc 639
AnnaBridge 171:3a7713b1edbc 640 /**
AnnaBridge 171:3a7713b1edbc 641 * @brief Universal Serial Bus Full Speed Device
AnnaBridge 171:3a7713b1edbc 642 */
AnnaBridge 171:3a7713b1edbc 643 /**
AnnaBridge 171:3a7713b1edbc 644 * @}
AnnaBridge 171:3a7713b1edbc 645 */
AnnaBridge 171:3a7713b1edbc 646
AnnaBridge 171:3a7713b1edbc 647 /** @addtogroup Peripheral_memory_map
AnnaBridge 171:3a7713b1edbc 648 * @{
AnnaBridge 171:3a7713b1edbc 649 */
AnnaBridge 171:3a7713b1edbc 650
AnnaBridge 171:3a7713b1edbc 651 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */
AnnaBridge 171:3a7713b1edbc 652 #define FLASH_EEPROM_BASE ((uint32_t)(FLASH_BASE + 0x80000U)) /*!< FLASH EEPROM base address in the alias region */
AnnaBridge 171:3a7713b1edbc 653 #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */
AnnaBridge 171:3a7713b1edbc 654 #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */
AnnaBridge 171:3a7713b1edbc 655 #define SRAM_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM base address in the bit-band region */
AnnaBridge 171:3a7713b1edbc 656 #define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< Peripheral base address in the bit-band region */
AnnaBridge 171:3a7713b1edbc 657 #define FLASH_END ((uint32_t)0x0803FFFFU) /*!< Program end FLASH address for Cat3 */
AnnaBridge 171:3a7713b1edbc 658 #define FLASH_EEPROM_END ((uint32_t)0x08081FFFU) /*!< FLASH EEPROM end address (8KB) */
AnnaBridge 171:3a7713b1edbc 659
AnnaBridge 171:3a7713b1edbc 660 /*!< Peripheral memory map */
AnnaBridge 171:3a7713b1edbc 661 #define APB1PERIPH_BASE PERIPH_BASE
AnnaBridge 171:3a7713b1edbc 662 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
AnnaBridge 171:3a7713b1edbc 663 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
AnnaBridge 171:3a7713b1edbc 664
AnnaBridge 171:3a7713b1edbc 665 /*!< APB1 peripherals */
AnnaBridge 171:3a7713b1edbc 666 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U)
AnnaBridge 171:3a7713b1edbc 667 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U)
AnnaBridge 171:3a7713b1edbc 668 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U)
AnnaBridge 171:3a7713b1edbc 669 #define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00U)
AnnaBridge 171:3a7713b1edbc 670 #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000U)
AnnaBridge 171:3a7713b1edbc 671 #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400U)
AnnaBridge 171:3a7713b1edbc 672 #define LCD_BASE (APB1PERIPH_BASE + 0x00002400U)
AnnaBridge 171:3a7713b1edbc 673 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)
AnnaBridge 171:3a7713b1edbc 674 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)
AnnaBridge 171:3a7713b1edbc 675 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
AnnaBridge 171:3a7713b1edbc 676 #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U)
AnnaBridge 171:3a7713b1edbc 677 #define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00U)
AnnaBridge 171:3a7713b1edbc 678 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400U)
AnnaBridge 171:3a7713b1edbc 679 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800U)
AnnaBridge 171:3a7713b1edbc 680 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U)
AnnaBridge 171:3a7713b1edbc 681 #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800U)
AnnaBridge 171:3a7713b1edbc 682
AnnaBridge 171:3a7713b1edbc 683 /* USB device FS */
AnnaBridge 171:3a7713b1edbc 684 #define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */
AnnaBridge 171:3a7713b1edbc 685 #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */
AnnaBridge 171:3a7713b1edbc 686
AnnaBridge 171:3a7713b1edbc 687 /* USB device FS SRAM */
AnnaBridge 171:3a7713b1edbc 688 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000U)
AnnaBridge 171:3a7713b1edbc 689 #define DAC_BASE (APB1PERIPH_BASE + 0x00007400U)
AnnaBridge 171:3a7713b1edbc 690 #define COMP_BASE (APB1PERIPH_BASE + 0x00007C00U)
AnnaBridge 171:3a7713b1edbc 691 #define RI_BASE (APB1PERIPH_BASE + 0x00007C04U)
AnnaBridge 171:3a7713b1edbc 692 #define OPAMP_BASE (APB1PERIPH_BASE + 0x00007C5CU)
AnnaBridge 171:3a7713b1edbc 693
AnnaBridge 171:3a7713b1edbc 694 /*!< APB2 peripherals */
AnnaBridge 171:3a7713b1edbc 695 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000U)
AnnaBridge 171:3a7713b1edbc 696 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U)
AnnaBridge 171:3a7713b1edbc 697 #define TIM9_BASE (APB2PERIPH_BASE + 0x00000800U)
AnnaBridge 171:3a7713b1edbc 698 #define TIM10_BASE (APB2PERIPH_BASE + 0x00000C00U)
AnnaBridge 171:3a7713b1edbc 699 #define TIM11_BASE (APB2PERIPH_BASE + 0x00001000U)
AnnaBridge 171:3a7713b1edbc 700 #define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U)
AnnaBridge 171:3a7713b1edbc 701 #define ADC_BASE (APB2PERIPH_BASE + 0x00002700U)
AnnaBridge 171:3a7713b1edbc 702 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U)
AnnaBridge 171:3a7713b1edbc 703 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800U)
AnnaBridge 171:3a7713b1edbc 704
AnnaBridge 171:3a7713b1edbc 705 /*!< AHB peripherals */
AnnaBridge 171:3a7713b1edbc 706 #define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000U)
AnnaBridge 171:3a7713b1edbc 707 #define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400U)
AnnaBridge 171:3a7713b1edbc 708 #define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800U)
AnnaBridge 171:3a7713b1edbc 709 #define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00U)
AnnaBridge 171:3a7713b1edbc 710 #define GPIOE_BASE (AHBPERIPH_BASE + 0x00001000U)
AnnaBridge 171:3a7713b1edbc 711 #define GPIOH_BASE (AHBPERIPH_BASE + 0x00001400U)
AnnaBridge 171:3a7713b1edbc 712 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
AnnaBridge 171:3a7713b1edbc 713 #define RCC_BASE (AHBPERIPH_BASE + 0x00003800U)
AnnaBridge 171:3a7713b1edbc 714 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00U) /*!< FLASH registers base address */
AnnaBridge 171:3a7713b1edbc 715 #define OB_BASE ((uint32_t)0x1FF80000U) /*!< FLASH Option Bytes base address */
AnnaBridge 171:3a7713b1edbc 716 #define FLASHSIZE_BASE ((uint32_t)0x1FF800CCU) /*!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
AnnaBridge 171:3a7713b1edbc 717 #define UID_BASE ((uint32_t)0x1FF800D0U) /*!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
AnnaBridge 171:3a7713b1edbc 718 #define DMA1_BASE (AHBPERIPH_BASE + 0x00006000U)
AnnaBridge 171:3a7713b1edbc 719 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008U)
AnnaBridge 171:3a7713b1edbc 720 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU)
AnnaBridge 171:3a7713b1edbc 721 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030U)
AnnaBridge 171:3a7713b1edbc 722 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044U)
AnnaBridge 171:3a7713b1edbc 723 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058U)
AnnaBridge 171:3a7713b1edbc 724 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CU)
AnnaBridge 171:3a7713b1edbc 725 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080U)
AnnaBridge 171:3a7713b1edbc 726 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400U)
AnnaBridge 171:3a7713b1edbc 727 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008U)
AnnaBridge 171:3a7713b1edbc 728 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CU)
AnnaBridge 171:3a7713b1edbc 729 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030U)
AnnaBridge 171:3a7713b1edbc 730 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044U)
AnnaBridge 171:3a7713b1edbc 731 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058U)
AnnaBridge 171:3a7713b1edbc 732 #define DBGMCU_BASE ((uint32_t)0xE0042000U) /*!< Debug MCU registers base address */
AnnaBridge 171:3a7713b1edbc 733
AnnaBridge 171:3a7713b1edbc 734 /**
AnnaBridge 171:3a7713b1edbc 735 * @}
AnnaBridge 171:3a7713b1edbc 736 */
AnnaBridge 171:3a7713b1edbc 737
AnnaBridge 171:3a7713b1edbc 738 /** @addtogroup Peripheral_declaration
AnnaBridge 171:3a7713b1edbc 739 * @{
AnnaBridge 171:3a7713b1edbc 740 */
AnnaBridge 171:3a7713b1edbc 741
AnnaBridge 171:3a7713b1edbc 742 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
AnnaBridge 171:3a7713b1edbc 743 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
AnnaBridge 171:3a7713b1edbc 744 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
AnnaBridge 171:3a7713b1edbc 745 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
AnnaBridge 171:3a7713b1edbc 746 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
AnnaBridge 171:3a7713b1edbc 747 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
AnnaBridge 171:3a7713b1edbc 748 #define LCD ((LCD_TypeDef *) LCD_BASE)
AnnaBridge 171:3a7713b1edbc 749 #define RTC ((RTC_TypeDef *) RTC_BASE)
AnnaBridge 171:3a7713b1edbc 750 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
AnnaBridge 171:3a7713b1edbc 751 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
AnnaBridge 171:3a7713b1edbc 752 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
AnnaBridge 171:3a7713b1edbc 753 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
AnnaBridge 171:3a7713b1edbc 754 #define USART2 ((USART_TypeDef *) USART2_BASE)
AnnaBridge 171:3a7713b1edbc 755 #define USART3 ((USART_TypeDef *) USART3_BASE)
AnnaBridge 171:3a7713b1edbc 756 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
AnnaBridge 171:3a7713b1edbc 757 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
AnnaBridge 171:3a7713b1edbc 758 /* USB device FS */
AnnaBridge 171:3a7713b1edbc 759 #define USB ((USB_TypeDef *) USB_BASE)
AnnaBridge 171:3a7713b1edbc 760 /* USB device FS SRAM */
AnnaBridge 171:3a7713b1edbc 761 #define PWR ((PWR_TypeDef *) PWR_BASE)
AnnaBridge 171:3a7713b1edbc 762
AnnaBridge 171:3a7713b1edbc 763 #define DAC1 ((DAC_TypeDef *) DAC_BASE)
AnnaBridge 171:3a7713b1edbc 764 /* Legacy define */
AnnaBridge 171:3a7713b1edbc 765 #define DAC DAC1
AnnaBridge 171:3a7713b1edbc 766
AnnaBridge 171:3a7713b1edbc 767 #define COMP ((COMP_TypeDef *) COMP_BASE) /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */
AnnaBridge 171:3a7713b1edbc 768 #define COMP1 ((COMP_TypeDef *) COMP_BASE) /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
AnnaBridge 171:3a7713b1edbc 769 #define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
AnnaBridge 171:3a7713b1edbc 770 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP_BASE) /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */
AnnaBridge 171:3a7713b1edbc 771
AnnaBridge 171:3a7713b1edbc 772 #define RI ((RI_TypeDef *) RI_BASE)
AnnaBridge 171:3a7713b1edbc 773
AnnaBridge 171:3a7713b1edbc 774 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
AnnaBridge 171:3a7713b1edbc 775 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP_BASE)
AnnaBridge 171:3a7713b1edbc 776 #define OPAMP2 ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001U))
AnnaBridge 171:3a7713b1edbc 777 #define OPAMP12_COMMON ((OPAMP_Common_TypeDef *) OPAMP_BASE)
AnnaBridge 171:3a7713b1edbc 778 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
AnnaBridge 171:3a7713b1edbc 779 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
AnnaBridge 171:3a7713b1edbc 780 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
AnnaBridge 171:3a7713b1edbc 781 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
AnnaBridge 171:3a7713b1edbc 782 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
AnnaBridge 171:3a7713b1edbc 783
AnnaBridge 171:3a7713b1edbc 784 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
AnnaBridge 171:3a7713b1edbc 785 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
AnnaBridge 171:3a7713b1edbc 786 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 787 #define ADC ADC1_COMMON
AnnaBridge 171:3a7713b1edbc 788
AnnaBridge 171:3a7713b1edbc 789 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
AnnaBridge 171:3a7713b1edbc 790 #define USART1 ((USART_TypeDef *) USART1_BASE)
AnnaBridge 171:3a7713b1edbc 791 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
AnnaBridge 171:3a7713b1edbc 792 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
AnnaBridge 171:3a7713b1edbc 793 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
AnnaBridge 171:3a7713b1edbc 794 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
AnnaBridge 171:3a7713b1edbc 795 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
AnnaBridge 171:3a7713b1edbc 796 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
AnnaBridge 171:3a7713b1edbc 797 #define CRC ((CRC_TypeDef *) CRC_BASE)
AnnaBridge 171:3a7713b1edbc 798 #define RCC ((RCC_TypeDef *) RCC_BASE)
AnnaBridge 171:3a7713b1edbc 799 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
AnnaBridge 171:3a7713b1edbc 800 #define OB ((OB_TypeDef *) OB_BASE)
AnnaBridge 171:3a7713b1edbc 801 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
AnnaBridge 171:3a7713b1edbc 802 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
AnnaBridge 171:3a7713b1edbc 803 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
AnnaBridge 171:3a7713b1edbc 804 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
AnnaBridge 171:3a7713b1edbc 805 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
AnnaBridge 171:3a7713b1edbc 806 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
AnnaBridge 171:3a7713b1edbc 807 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
AnnaBridge 171:3a7713b1edbc 808 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
AnnaBridge 171:3a7713b1edbc 809 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
AnnaBridge 171:3a7713b1edbc 810 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
AnnaBridge 171:3a7713b1edbc 811 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
AnnaBridge 171:3a7713b1edbc 812 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
AnnaBridge 171:3a7713b1edbc 813 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
AnnaBridge 171:3a7713b1edbc 814 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
AnnaBridge 171:3a7713b1edbc 815 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
AnnaBridge 171:3a7713b1edbc 816
AnnaBridge 171:3a7713b1edbc 817 /**
AnnaBridge 171:3a7713b1edbc 818 * @}
AnnaBridge 171:3a7713b1edbc 819 */
AnnaBridge 171:3a7713b1edbc 820
AnnaBridge 171:3a7713b1edbc 821 /** @addtogroup Exported_constants
AnnaBridge 171:3a7713b1edbc 822 * @{
AnnaBridge 171:3a7713b1edbc 823 */
AnnaBridge 171:3a7713b1edbc 824
AnnaBridge 171:3a7713b1edbc 825 /** @addtogroup Peripheral_Registers_Bits_Definition
AnnaBridge 171:3a7713b1edbc 826 * @{
AnnaBridge 171:3a7713b1edbc 827 */
AnnaBridge 171:3a7713b1edbc 828
AnnaBridge 171:3a7713b1edbc 829 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 830 /* Peripheral Registers Bits Definition */
AnnaBridge 171:3a7713b1edbc 831 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 832 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 833 /* */
AnnaBridge 171:3a7713b1edbc 834 /* Analog to Digital Converter (ADC) */
AnnaBridge 171:3a7713b1edbc 835 /* */
AnnaBridge 171:3a7713b1edbc 836 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 837
AnnaBridge 171:3a7713b1edbc 838 /******************** Bit definition for ADC_SR register ********************/
AnnaBridge 171:3a7713b1edbc 839 #define ADC_SR_AWD_Pos (0U)
AnnaBridge 171:3a7713b1edbc 840 #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 841 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */
AnnaBridge 171:3a7713b1edbc 842 #define ADC_SR_EOCS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 843 #define ADC_SR_EOCS_Msk (0x1U << ADC_SR_EOCS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 844 #define ADC_SR_EOCS ADC_SR_EOCS_Msk /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */
AnnaBridge 171:3a7713b1edbc 845 #define ADC_SR_JEOS_Pos (2U)
AnnaBridge 171:3a7713b1edbc 846 #define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 847 #define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
AnnaBridge 171:3a7713b1edbc 848 #define ADC_SR_JSTRT_Pos (3U)
AnnaBridge 171:3a7713b1edbc 849 #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 850 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */
AnnaBridge 171:3a7713b1edbc 851 #define ADC_SR_STRT_Pos (4U)
AnnaBridge 171:3a7713b1edbc 852 #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 853 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */
AnnaBridge 171:3a7713b1edbc 854 #define ADC_SR_OVR_Pos (5U)
AnnaBridge 171:3a7713b1edbc 855 #define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 856 #define ADC_SR_OVR ADC_SR_OVR_Msk /*!< ADC group regular overrun flag */
AnnaBridge 171:3a7713b1edbc 857 #define ADC_SR_ADONS_Pos (6U)
AnnaBridge 171:3a7713b1edbc 858 #define ADC_SR_ADONS_Msk (0x1U << ADC_SR_ADONS_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 859 #define ADC_SR_ADONS ADC_SR_ADONS_Msk /*!< ADC ready flag */
AnnaBridge 171:3a7713b1edbc 860 #define ADC_SR_RCNR_Pos (8U)
AnnaBridge 171:3a7713b1edbc 861 #define ADC_SR_RCNR_Msk (0x1U << ADC_SR_RCNR_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 862 #define ADC_SR_RCNR ADC_SR_RCNR_Msk /*!< ADC group regular not ready flag */
AnnaBridge 171:3a7713b1edbc 863 #define ADC_SR_JCNR_Pos (9U)
AnnaBridge 171:3a7713b1edbc 864 #define ADC_SR_JCNR_Msk (0x1U << ADC_SR_JCNR_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 865 #define ADC_SR_JCNR ADC_SR_JCNR_Msk /*!< ADC group injected not ready flag */
AnnaBridge 171:3a7713b1edbc 866
AnnaBridge 171:3a7713b1edbc 867 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 868 #define ADC_SR_EOC (ADC_SR_EOCS)
AnnaBridge 171:3a7713b1edbc 869 #define ADC_SR_JEOC (ADC_SR_JEOS)
AnnaBridge 171:3a7713b1edbc 870
AnnaBridge 171:3a7713b1edbc 871 /******************* Bit definition for ADC_CR1 register ********************/
AnnaBridge 171:3a7713b1edbc 872 #define ADC_CR1_AWDCH_Pos (0U)
AnnaBridge 171:3a7713b1edbc 873 #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 874 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
AnnaBridge 171:3a7713b1edbc 875 #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 876 #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 877 #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 878 #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 879 #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 880
AnnaBridge 171:3a7713b1edbc 881 #define ADC_CR1_EOCSIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 882 #define ADC_CR1_EOCSIE_Msk (0x1U << ADC_CR1_EOCSIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 883 #define ADC_CR1_EOCSIE ADC_CR1_EOCSIE_Msk /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */
AnnaBridge 171:3a7713b1edbc 884 #define ADC_CR1_AWDIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 885 #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 886 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */
AnnaBridge 171:3a7713b1edbc 887 #define ADC_CR1_JEOSIE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 888 #define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 889 #define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
AnnaBridge 171:3a7713b1edbc 890 #define ADC_CR1_SCAN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 891 #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 892 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */
AnnaBridge 171:3a7713b1edbc 893 #define ADC_CR1_AWDSGL_Pos (9U)
AnnaBridge 171:3a7713b1edbc 894 #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 895 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
AnnaBridge 171:3a7713b1edbc 896 #define ADC_CR1_JAUTO_Pos (10U)
AnnaBridge 171:3a7713b1edbc 897 #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 898 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
AnnaBridge 171:3a7713b1edbc 899 #define ADC_CR1_DISCEN_Pos (11U)
AnnaBridge 171:3a7713b1edbc 900 #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 901 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
AnnaBridge 171:3a7713b1edbc 902 #define ADC_CR1_JDISCEN_Pos (12U)
AnnaBridge 171:3a7713b1edbc 903 #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 904 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
AnnaBridge 171:3a7713b1edbc 905
AnnaBridge 171:3a7713b1edbc 906 #define ADC_CR1_DISCNUM_Pos (13U)
AnnaBridge 171:3a7713b1edbc 907 #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
AnnaBridge 171:3a7713b1edbc 908 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
AnnaBridge 171:3a7713b1edbc 909 #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 910 #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 911 #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 912
AnnaBridge 171:3a7713b1edbc 913 #define ADC_CR1_PDD_Pos (16U)
AnnaBridge 171:3a7713b1edbc 914 #define ADC_CR1_PDD_Msk (0x1U << ADC_CR1_PDD_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 915 #define ADC_CR1_PDD ADC_CR1_PDD_Msk /*!< ADC power down during auto delay phase */
AnnaBridge 171:3a7713b1edbc 916 #define ADC_CR1_PDI_Pos (17U)
AnnaBridge 171:3a7713b1edbc 917 #define ADC_CR1_PDI_Msk (0x1U << ADC_CR1_PDI_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 918 #define ADC_CR1_PDI ADC_CR1_PDI_Msk /*!< ADC power down during idle phase */
AnnaBridge 171:3a7713b1edbc 919
AnnaBridge 171:3a7713b1edbc 920 #define ADC_CR1_JAWDEN_Pos (22U)
AnnaBridge 171:3a7713b1edbc 921 #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 922 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
AnnaBridge 171:3a7713b1edbc 923 #define ADC_CR1_AWDEN_Pos (23U)
AnnaBridge 171:3a7713b1edbc 924 #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 925 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
AnnaBridge 171:3a7713b1edbc 926
AnnaBridge 171:3a7713b1edbc 927 #define ADC_CR1_RES_Pos (24U)
AnnaBridge 171:3a7713b1edbc 928 #define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 929 #define ADC_CR1_RES ADC_CR1_RES_Msk /*!< ADC resolution */
AnnaBridge 171:3a7713b1edbc 930 #define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 931 #define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 932
AnnaBridge 171:3a7713b1edbc 933 #define ADC_CR1_OVRIE_Pos (26U)
AnnaBridge 171:3a7713b1edbc 934 #define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 935 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!< ADC group regular overrun interrupt */
AnnaBridge 171:3a7713b1edbc 936
AnnaBridge 171:3a7713b1edbc 937 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 938 #define ADC_CR1_EOCIE (ADC_CR1_EOCSIE)
AnnaBridge 171:3a7713b1edbc 939 #define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
AnnaBridge 171:3a7713b1edbc 940
AnnaBridge 171:3a7713b1edbc 941 /******************* Bit definition for ADC_CR2 register ********************/
AnnaBridge 171:3a7713b1edbc 942 #define ADC_CR2_ADON_Pos (0U)
AnnaBridge 171:3a7713b1edbc 943 #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 944 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */
AnnaBridge 171:3a7713b1edbc 945 #define ADC_CR2_CONT_Pos (1U)
AnnaBridge 171:3a7713b1edbc 946 #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 947 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */
AnnaBridge 171:3a7713b1edbc 948 #define ADC_CR2_CFG_Pos (2U)
AnnaBridge 171:3a7713b1edbc 949 #define ADC_CR2_CFG_Msk (0x1U << ADC_CR2_CFG_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 950 #define ADC_CR2_CFG ADC_CR2_CFG_Msk /*!< ADC channels bank selection */
AnnaBridge 171:3a7713b1edbc 951
AnnaBridge 171:3a7713b1edbc 952 #define ADC_CR2_DELS_Pos (4U)
AnnaBridge 171:3a7713b1edbc 953 #define ADC_CR2_DELS_Msk (0x7U << ADC_CR2_DELS_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 954 #define ADC_CR2_DELS ADC_CR2_DELS_Msk /*!< ADC auto delay selection */
AnnaBridge 171:3a7713b1edbc 955 #define ADC_CR2_DELS_0 (0x1U << ADC_CR2_DELS_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 956 #define ADC_CR2_DELS_1 (0x2U << ADC_CR2_DELS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 957 #define ADC_CR2_DELS_2 (0x4U << ADC_CR2_DELS_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 958
AnnaBridge 171:3a7713b1edbc 959 #define ADC_CR2_DMA_Pos (8U)
AnnaBridge 171:3a7713b1edbc 960 #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 961 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
AnnaBridge 171:3a7713b1edbc 962 #define ADC_CR2_DDS_Pos (9U)
AnnaBridge 171:3a7713b1edbc 963 #define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 964 #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!< ADC DMA transfer configuration */
AnnaBridge 171:3a7713b1edbc 965 #define ADC_CR2_EOCS_Pos (10U)
AnnaBridge 171:3a7713b1edbc 966 #define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 967 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!< ADC end of unitary or end of sequence conversions selection */
AnnaBridge 171:3a7713b1edbc 968 #define ADC_CR2_ALIGN_Pos (11U)
AnnaBridge 171:3a7713b1edbc 969 #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 970 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
AnnaBridge 171:3a7713b1edbc 971
AnnaBridge 171:3a7713b1edbc 972 #define ADC_CR2_JEXTSEL_Pos (16U)
AnnaBridge 171:3a7713b1edbc 973 #define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 974 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */
AnnaBridge 171:3a7713b1edbc 975 #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 976 #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 977 #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 978 #define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 979
AnnaBridge 171:3a7713b1edbc 980 #define ADC_CR2_JEXTEN_Pos (20U)
AnnaBridge 171:3a7713b1edbc 981 #define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 982 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
AnnaBridge 171:3a7713b1edbc 983 #define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 984 #define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 985
AnnaBridge 171:3a7713b1edbc 986 #define ADC_CR2_JSWSTART_Pos (22U)
AnnaBridge 171:3a7713b1edbc 987 #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 988 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */
AnnaBridge 171:3a7713b1edbc 989
AnnaBridge 171:3a7713b1edbc 990 #define ADC_CR2_EXTSEL_Pos (24U)
AnnaBridge 171:3a7713b1edbc 991 #define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 992 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */
AnnaBridge 171:3a7713b1edbc 993 #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 994 #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 995 #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 996 #define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 997
AnnaBridge 171:3a7713b1edbc 998 #define ADC_CR2_EXTEN_Pos (28U)
AnnaBridge 171:3a7713b1edbc 999 #define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 1000 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!< ADC group regular external trigger polarity */
AnnaBridge 171:3a7713b1edbc 1001 #define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1002 #define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1003
AnnaBridge 171:3a7713b1edbc 1004 #define ADC_CR2_SWSTART_Pos (30U)
AnnaBridge 171:3a7713b1edbc 1005 #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 1006 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */
AnnaBridge 171:3a7713b1edbc 1007
AnnaBridge 171:3a7713b1edbc 1008 /****************** Bit definition for ADC_SMPR1 register *******************/
AnnaBridge 171:3a7713b1edbc 1009 #define ADC_SMPR1_SMP20_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1010 #define ADC_SMPR1_SMP20_Msk (0x7U << ADC_SMPR1_SMP20_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 1011 #define ADC_SMPR1_SMP20 ADC_SMPR1_SMP20_Msk /*!< ADC channel 20 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1012 #define ADC_SMPR1_SMP20_0 (0x1U << ADC_SMPR1_SMP20_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1013 #define ADC_SMPR1_SMP20_1 (0x2U << ADC_SMPR1_SMP20_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1014 #define ADC_SMPR1_SMP20_2 (0x4U << ADC_SMPR1_SMP20_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1015
AnnaBridge 171:3a7713b1edbc 1016 #define ADC_SMPR1_SMP21_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1017 #define ADC_SMPR1_SMP21_Msk (0x7U << ADC_SMPR1_SMP21_Pos) /*!< 0x00000038 */
AnnaBridge 171:3a7713b1edbc 1018 #define ADC_SMPR1_SMP21 ADC_SMPR1_SMP21_Msk /*!< ADC channel 21 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1019 #define ADC_SMPR1_SMP21_0 (0x1U << ADC_SMPR1_SMP21_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1020 #define ADC_SMPR1_SMP21_1 (0x2U << ADC_SMPR1_SMP21_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1021 #define ADC_SMPR1_SMP21_2 (0x4U << ADC_SMPR1_SMP21_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1022
AnnaBridge 171:3a7713b1edbc 1023 #define ADC_SMPR1_SMP22_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1024 #define ADC_SMPR1_SMP22_Msk (0x7U << ADC_SMPR1_SMP22_Pos) /*!< 0x000001C0 */
AnnaBridge 171:3a7713b1edbc 1025 #define ADC_SMPR1_SMP22 ADC_SMPR1_SMP22_Msk /*!< ADC channel 22 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1026 #define ADC_SMPR1_SMP22_0 (0x1U << ADC_SMPR1_SMP22_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1027 #define ADC_SMPR1_SMP22_1 (0x2U << ADC_SMPR1_SMP22_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1028 #define ADC_SMPR1_SMP22_2 (0x4U << ADC_SMPR1_SMP22_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1029
AnnaBridge 171:3a7713b1edbc 1030 #define ADC_SMPR1_SMP23_Pos (9U)
AnnaBridge 171:3a7713b1edbc 1031 #define ADC_SMPR1_SMP23_Msk (0x7U << ADC_SMPR1_SMP23_Pos) /*!< 0x00000E00 */
AnnaBridge 171:3a7713b1edbc 1032 #define ADC_SMPR1_SMP23 ADC_SMPR1_SMP23_Msk /*!< ADC channel 23 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1033 #define ADC_SMPR1_SMP23_0 (0x1U << ADC_SMPR1_SMP23_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1034 #define ADC_SMPR1_SMP23_1 (0x2U << ADC_SMPR1_SMP23_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1035 #define ADC_SMPR1_SMP23_2 (0x4U << ADC_SMPR1_SMP23_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1036
AnnaBridge 171:3a7713b1edbc 1037 #define ADC_SMPR1_SMP24_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1038 #define ADC_SMPR1_SMP24_Msk (0x7U << ADC_SMPR1_SMP24_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 1039 #define ADC_SMPR1_SMP24 ADC_SMPR1_SMP24_Msk /*!< ADC channel 24 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1040 #define ADC_SMPR1_SMP24_0 (0x1U << ADC_SMPR1_SMP24_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1041 #define ADC_SMPR1_SMP24_1 (0x2U << ADC_SMPR1_SMP24_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1042 #define ADC_SMPR1_SMP24_2 (0x4U << ADC_SMPR1_SMP24_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1043
AnnaBridge 171:3a7713b1edbc 1044 #define ADC_SMPR1_SMP25_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1045 #define ADC_SMPR1_SMP25_Msk (0x7U << ADC_SMPR1_SMP25_Pos) /*!< 0x00038000 */
AnnaBridge 171:3a7713b1edbc 1046 #define ADC_SMPR1_SMP25 ADC_SMPR1_SMP25_Msk /*!< ADC channel 25 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1047 #define ADC_SMPR1_SMP25_0 (0x1U << ADC_SMPR1_SMP25_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1048 #define ADC_SMPR1_SMP25_1 (0x2U << ADC_SMPR1_SMP25_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1049 #define ADC_SMPR1_SMP25_2 (0x4U << ADC_SMPR1_SMP25_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1050
AnnaBridge 171:3a7713b1edbc 1051 #define ADC_SMPR1_SMP26_Pos (18U)
AnnaBridge 171:3a7713b1edbc 1052 #define ADC_SMPR1_SMP26_Msk (0x7U << ADC_SMPR1_SMP26_Pos) /*!< 0x001C0000 */
AnnaBridge 171:3a7713b1edbc 1053 #define ADC_SMPR1_SMP26 ADC_SMPR1_SMP26_Msk /*!< ADC channel 26 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1054 #define ADC_SMPR1_SMP26_0 (0x1U << ADC_SMPR1_SMP26_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1055 #define ADC_SMPR1_SMP26_1 (0x2U << ADC_SMPR1_SMP26_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1056 #define ADC_SMPR1_SMP26_2 (0x4U << ADC_SMPR1_SMP26_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1057
AnnaBridge 171:3a7713b1edbc 1058 /****************** Bit definition for ADC_SMPR2 register *******************/
AnnaBridge 171:3a7713b1edbc 1059 #define ADC_SMPR2_SMP10_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1060 #define ADC_SMPR2_SMP10_Msk (0x7U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 1061 #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1062 #define ADC_SMPR2_SMP10_0 (0x1U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1063 #define ADC_SMPR2_SMP10_1 (0x2U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1064 #define ADC_SMPR2_SMP10_2 (0x4U << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1065
AnnaBridge 171:3a7713b1edbc 1066 #define ADC_SMPR2_SMP11_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1067 #define ADC_SMPR2_SMP11_Msk (0x7U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
AnnaBridge 171:3a7713b1edbc 1068 #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1069 #define ADC_SMPR2_SMP11_0 (0x1U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1070 #define ADC_SMPR2_SMP11_1 (0x2U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1071 #define ADC_SMPR2_SMP11_2 (0x4U << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1072
AnnaBridge 171:3a7713b1edbc 1073 #define ADC_SMPR2_SMP12_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1074 #define ADC_SMPR2_SMP12_Msk (0x7U << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
AnnaBridge 171:3a7713b1edbc 1075 #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1076 #define ADC_SMPR2_SMP12_0 (0x1U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1077 #define ADC_SMPR2_SMP12_1 (0x2U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1078 #define ADC_SMPR2_SMP12_2 (0x4U << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1079
AnnaBridge 171:3a7713b1edbc 1080 #define ADC_SMPR2_SMP13_Pos (9U)
AnnaBridge 171:3a7713b1edbc 1081 #define ADC_SMPR2_SMP13_Msk (0x7U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
AnnaBridge 171:3a7713b1edbc 1082 #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1083 #define ADC_SMPR2_SMP13_0 (0x1U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1084 #define ADC_SMPR2_SMP13_1 (0x2U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1085 #define ADC_SMPR2_SMP13_2 (0x4U << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1086
AnnaBridge 171:3a7713b1edbc 1087 #define ADC_SMPR2_SMP14_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1088 #define ADC_SMPR2_SMP14_Msk (0x7U << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 1089 #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1090 #define ADC_SMPR2_SMP14_0 (0x1U << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1091 #define ADC_SMPR2_SMP14_1 (0x2U << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1092 #define ADC_SMPR2_SMP14_2 (0x4U << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1093
AnnaBridge 171:3a7713b1edbc 1094 #define ADC_SMPR2_SMP15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1095 #define ADC_SMPR2_SMP15_Msk (0x7U << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
AnnaBridge 171:3a7713b1edbc 1096 #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 5 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1097 #define ADC_SMPR2_SMP15_0 (0x1U << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1098 #define ADC_SMPR2_SMP15_1 (0x2U << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1099 #define ADC_SMPR2_SMP15_2 (0x4U << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1100
AnnaBridge 171:3a7713b1edbc 1101 #define ADC_SMPR2_SMP16_Pos (18U)
AnnaBridge 171:3a7713b1edbc 1102 #define ADC_SMPR2_SMP16_Msk (0x7U << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
AnnaBridge 171:3a7713b1edbc 1103 #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1104 #define ADC_SMPR2_SMP16_0 (0x1U << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1105 #define ADC_SMPR2_SMP16_1 (0x2U << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1106 #define ADC_SMPR2_SMP16_2 (0x4U << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1107
AnnaBridge 171:3a7713b1edbc 1108 #define ADC_SMPR2_SMP17_Pos (21U)
AnnaBridge 171:3a7713b1edbc 1109 #define ADC_SMPR2_SMP17_Msk (0x7U << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
AnnaBridge 171:3a7713b1edbc 1110 #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1111 #define ADC_SMPR2_SMP17_0 (0x1U << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1112 #define ADC_SMPR2_SMP17_1 (0x2U << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1113 #define ADC_SMPR2_SMP17_2 (0x4U << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1114
AnnaBridge 171:3a7713b1edbc 1115 #define ADC_SMPR2_SMP18_Pos (24U)
AnnaBridge 171:3a7713b1edbc 1116 #define ADC_SMPR2_SMP18_Msk (0x7U << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
AnnaBridge 171:3a7713b1edbc 1117 #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1118 #define ADC_SMPR2_SMP18_0 (0x1U << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1119 #define ADC_SMPR2_SMP18_1 (0x2U << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1120 #define ADC_SMPR2_SMP18_2 (0x4U << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1121
AnnaBridge 171:3a7713b1edbc 1122 #define ADC_SMPR2_SMP19_Pos (27U)
AnnaBridge 171:3a7713b1edbc 1123 #define ADC_SMPR2_SMP19_Msk (0x7U << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */
AnnaBridge 171:3a7713b1edbc 1124 #define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC channel 19 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1125 #define ADC_SMPR2_SMP19_0 (0x1U << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1126 #define ADC_SMPR2_SMP19_1 (0x2U << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1127 #define ADC_SMPR2_SMP19_2 (0x4U << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1128
AnnaBridge 171:3a7713b1edbc 1129 /****************** Bit definition for ADC_SMPR3 register *******************/
AnnaBridge 171:3a7713b1edbc 1130 #define ADC_SMPR3_SMP0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1131 #define ADC_SMPR3_SMP0_Msk (0x7U << ADC_SMPR3_SMP0_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 1132 #define ADC_SMPR3_SMP0 ADC_SMPR3_SMP0_Msk /*!< ADC channel 0 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1133 #define ADC_SMPR3_SMP0_0 (0x1U << ADC_SMPR3_SMP0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1134 #define ADC_SMPR3_SMP0_1 (0x2U << ADC_SMPR3_SMP0_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1135 #define ADC_SMPR3_SMP0_2 (0x4U << ADC_SMPR3_SMP0_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1136
AnnaBridge 171:3a7713b1edbc 1137 #define ADC_SMPR3_SMP1_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1138 #define ADC_SMPR3_SMP1_Msk (0x7U << ADC_SMPR3_SMP1_Pos) /*!< 0x00000038 */
AnnaBridge 171:3a7713b1edbc 1139 #define ADC_SMPR3_SMP1 ADC_SMPR3_SMP1_Msk /*!< ADC channel 1 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1140 #define ADC_SMPR3_SMP1_0 (0x1U << ADC_SMPR3_SMP1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1141 #define ADC_SMPR3_SMP1_1 (0x2U << ADC_SMPR3_SMP1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1142 #define ADC_SMPR3_SMP1_2 (0x4U << ADC_SMPR3_SMP1_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1143
AnnaBridge 171:3a7713b1edbc 1144 #define ADC_SMPR3_SMP2_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1145 #define ADC_SMPR3_SMP2_Msk (0x7U << ADC_SMPR3_SMP2_Pos) /*!< 0x000001C0 */
AnnaBridge 171:3a7713b1edbc 1146 #define ADC_SMPR3_SMP2 ADC_SMPR3_SMP2_Msk /*!< ADC channel 2 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1147 #define ADC_SMPR3_SMP2_0 (0x1U << ADC_SMPR3_SMP2_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1148 #define ADC_SMPR3_SMP2_1 (0x2U << ADC_SMPR3_SMP2_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1149 #define ADC_SMPR3_SMP2_2 (0x4U << ADC_SMPR3_SMP2_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1150
AnnaBridge 171:3a7713b1edbc 1151 #define ADC_SMPR3_SMP3_Pos (9U)
AnnaBridge 171:3a7713b1edbc 1152 #define ADC_SMPR3_SMP3_Msk (0x7U << ADC_SMPR3_SMP3_Pos) /*!< 0x00000E00 */
AnnaBridge 171:3a7713b1edbc 1153 #define ADC_SMPR3_SMP3 ADC_SMPR3_SMP3_Msk /*!< ADC channel 3 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1154 #define ADC_SMPR3_SMP3_0 (0x1U << ADC_SMPR3_SMP3_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1155 #define ADC_SMPR3_SMP3_1 (0x2U << ADC_SMPR3_SMP3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1156 #define ADC_SMPR3_SMP3_2 (0x4U << ADC_SMPR3_SMP3_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1157
AnnaBridge 171:3a7713b1edbc 1158 #define ADC_SMPR3_SMP4_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1159 #define ADC_SMPR3_SMP4_Msk (0x7U << ADC_SMPR3_SMP4_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 1160 #define ADC_SMPR3_SMP4 ADC_SMPR3_SMP4_Msk /*!< ADC channel 4 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1161 #define ADC_SMPR3_SMP4_0 (0x1U << ADC_SMPR3_SMP4_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1162 #define ADC_SMPR3_SMP4_1 (0x2U << ADC_SMPR3_SMP4_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1163 #define ADC_SMPR3_SMP4_2 (0x4U << ADC_SMPR3_SMP4_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1164
AnnaBridge 171:3a7713b1edbc 1165 #define ADC_SMPR3_SMP5_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1166 #define ADC_SMPR3_SMP5_Msk (0x7U << ADC_SMPR3_SMP5_Pos) /*!< 0x00038000 */
AnnaBridge 171:3a7713b1edbc 1167 #define ADC_SMPR3_SMP5 ADC_SMPR3_SMP5_Msk /*!< ADC channel 5 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1168 #define ADC_SMPR3_SMP5_0 (0x1U << ADC_SMPR3_SMP5_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1169 #define ADC_SMPR3_SMP5_1 (0x2U << ADC_SMPR3_SMP5_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1170 #define ADC_SMPR3_SMP5_2 (0x4U << ADC_SMPR3_SMP5_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1171
AnnaBridge 171:3a7713b1edbc 1172 #define ADC_SMPR3_SMP6_Pos (18U)
AnnaBridge 171:3a7713b1edbc 1173 #define ADC_SMPR3_SMP6_Msk (0x7U << ADC_SMPR3_SMP6_Pos) /*!< 0x001C0000 */
AnnaBridge 171:3a7713b1edbc 1174 #define ADC_SMPR3_SMP6 ADC_SMPR3_SMP6_Msk /*!< ADC channel 6 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1175 #define ADC_SMPR3_SMP6_0 (0x1U << ADC_SMPR3_SMP6_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1176 #define ADC_SMPR3_SMP6_1 (0x2U << ADC_SMPR3_SMP6_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1177 #define ADC_SMPR3_SMP6_2 (0x4U << ADC_SMPR3_SMP6_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1178
AnnaBridge 171:3a7713b1edbc 1179 #define ADC_SMPR3_SMP7_Pos (21U)
AnnaBridge 171:3a7713b1edbc 1180 #define ADC_SMPR3_SMP7_Msk (0x7U << ADC_SMPR3_SMP7_Pos) /*!< 0x00E00000 */
AnnaBridge 171:3a7713b1edbc 1181 #define ADC_SMPR3_SMP7 ADC_SMPR3_SMP7_Msk /*!< ADC channel 7 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1182 #define ADC_SMPR3_SMP7_0 (0x1U << ADC_SMPR3_SMP7_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1183 #define ADC_SMPR3_SMP7_1 (0x2U << ADC_SMPR3_SMP7_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1184 #define ADC_SMPR3_SMP7_2 (0x4U << ADC_SMPR3_SMP7_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1185
AnnaBridge 171:3a7713b1edbc 1186 #define ADC_SMPR3_SMP8_Pos (24U)
AnnaBridge 171:3a7713b1edbc 1187 #define ADC_SMPR3_SMP8_Msk (0x7U << ADC_SMPR3_SMP8_Pos) /*!< 0x07000000 */
AnnaBridge 171:3a7713b1edbc 1188 #define ADC_SMPR3_SMP8 ADC_SMPR3_SMP8_Msk /*!< ADC channel 8 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1189 #define ADC_SMPR3_SMP8_0 (0x1U << ADC_SMPR3_SMP8_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1190 #define ADC_SMPR3_SMP8_1 (0x2U << ADC_SMPR3_SMP8_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1191 #define ADC_SMPR3_SMP8_2 (0x4U << ADC_SMPR3_SMP8_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1192
AnnaBridge 171:3a7713b1edbc 1193 #define ADC_SMPR3_SMP9_Pos (27U)
AnnaBridge 171:3a7713b1edbc 1194 #define ADC_SMPR3_SMP9_Msk (0x7U << ADC_SMPR3_SMP9_Pos) /*!< 0x38000000 */
AnnaBridge 171:3a7713b1edbc 1195 #define ADC_SMPR3_SMP9 ADC_SMPR3_SMP9_Msk /*!< ADC channel 9 sampling time selection */
AnnaBridge 171:3a7713b1edbc 1196 #define ADC_SMPR3_SMP9_0 (0x1U << ADC_SMPR3_SMP9_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1197 #define ADC_SMPR3_SMP9_1 (0x2U << ADC_SMPR3_SMP9_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1198 #define ADC_SMPR3_SMP9_2 (0x4U << ADC_SMPR3_SMP9_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1199
AnnaBridge 171:3a7713b1edbc 1200 /****************** Bit definition for ADC_JOFR1 register *******************/
AnnaBridge 171:3a7713b1edbc 1201 #define ADC_JOFR1_JOFFSET1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1202 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1203 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */
AnnaBridge 171:3a7713b1edbc 1204
AnnaBridge 171:3a7713b1edbc 1205 /****************** Bit definition for ADC_JOFR2 register *******************/
AnnaBridge 171:3a7713b1edbc 1206 #define ADC_JOFR2_JOFFSET2_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1207 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1208 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */
AnnaBridge 171:3a7713b1edbc 1209
AnnaBridge 171:3a7713b1edbc 1210 /****************** Bit definition for ADC_JOFR3 register *******************/
AnnaBridge 171:3a7713b1edbc 1211 #define ADC_JOFR3_JOFFSET3_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1212 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1213 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */
AnnaBridge 171:3a7713b1edbc 1214
AnnaBridge 171:3a7713b1edbc 1215 /****************** Bit definition for ADC_JOFR4 register *******************/
AnnaBridge 171:3a7713b1edbc 1216 #define ADC_JOFR4_JOFFSET4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1217 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1218 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */
AnnaBridge 171:3a7713b1edbc 1219
AnnaBridge 171:3a7713b1edbc 1220 /******************* Bit definition for ADC_HTR register ********************/
AnnaBridge 171:3a7713b1edbc 1221 #define ADC_HTR_HT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1222 #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1223 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */
AnnaBridge 171:3a7713b1edbc 1224
AnnaBridge 171:3a7713b1edbc 1225 /******************* Bit definition for ADC_LTR register ********************/
AnnaBridge 171:3a7713b1edbc 1226 #define ADC_LTR_LT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1227 #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1228 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */
AnnaBridge 171:3a7713b1edbc 1229
AnnaBridge 171:3a7713b1edbc 1230 /******************* Bit definition for ADC_SQR1 register *******************/
AnnaBridge 171:3a7713b1edbc 1231 #define ADC_SQR1_L_Pos (20U)
AnnaBridge 171:3a7713b1edbc 1232 #define ADC_SQR1_L_Msk (0x1FU << ADC_SQR1_L_Pos) /*!< 0x01F00000 */
AnnaBridge 171:3a7713b1edbc 1233 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
AnnaBridge 171:3a7713b1edbc 1234 #define ADC_SQR1_L_0 (0x01U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1235 #define ADC_SQR1_L_1 (0x02U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1236 #define ADC_SQR1_L_2 (0x04U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1237 #define ADC_SQR1_L_3 (0x08U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1238 #define ADC_SQR1_L_4 (0x10U << ADC_SQR1_L_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1239
AnnaBridge 171:3a7713b1edbc 1240 #define ADC_SQR1_SQ28_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1241 #define ADC_SQR1_SQ28_Msk (0x1FU << ADC_SQR1_SQ28_Pos) /*!< 0x000F8000 */
AnnaBridge 171:3a7713b1edbc 1242 #define ADC_SQR1_SQ28 ADC_SQR1_SQ28_Msk /*!< ADC group regular sequencer rank 28 */
AnnaBridge 171:3a7713b1edbc 1243 #define ADC_SQR1_SQ28_0 (0x01U << ADC_SQR1_SQ28_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1244 #define ADC_SQR1_SQ28_1 (0x02U << ADC_SQR1_SQ28_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1245 #define ADC_SQR1_SQ28_2 (0x04U << ADC_SQR1_SQ28_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1246 #define ADC_SQR1_SQ28_3 (0x08U << ADC_SQR1_SQ28_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1247 #define ADC_SQR1_SQ28_4 (0x10U << ADC_SQR1_SQ28_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1248
AnnaBridge 171:3a7713b1edbc 1249 #define ADC_SQR1_SQ27_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1250 #define ADC_SQR1_SQ27_Msk (0x1FU << ADC_SQR1_SQ27_Pos) /*!< 0x00007C00 */
AnnaBridge 171:3a7713b1edbc 1251 #define ADC_SQR1_SQ27 ADC_SQR1_SQ27_Msk /*!< ADC group regular sequencer rank 27 */
AnnaBridge 171:3a7713b1edbc 1252 #define ADC_SQR1_SQ27_0 (0x01U << ADC_SQR1_SQ27_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1253 #define ADC_SQR1_SQ27_1 (0x02U << ADC_SQR1_SQ27_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1254 #define ADC_SQR1_SQ27_2 (0x04U << ADC_SQR1_SQ27_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1255 #define ADC_SQR1_SQ27_3 (0x08U << ADC_SQR1_SQ27_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1256 #define ADC_SQR1_SQ27_4 (0x10U << ADC_SQR1_SQ27_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1257
AnnaBridge 171:3a7713b1edbc 1258 #define ADC_SQR1_SQ26_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1259 #define ADC_SQR1_SQ26_Msk (0x1FU << ADC_SQR1_SQ26_Pos) /*!< 0x000003E0 */
AnnaBridge 171:3a7713b1edbc 1260 #define ADC_SQR1_SQ26 ADC_SQR1_SQ26_Msk /*!< ADC group regular sequencer rank 26 */
AnnaBridge 171:3a7713b1edbc 1261 #define ADC_SQR1_SQ26_0 (0x01U << ADC_SQR1_SQ26_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1262 #define ADC_SQR1_SQ26_1 (0x02U << ADC_SQR1_SQ26_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1263 #define ADC_SQR1_SQ26_2 (0x04U << ADC_SQR1_SQ26_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1264 #define ADC_SQR1_SQ26_3 (0x08U << ADC_SQR1_SQ26_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1265 #define ADC_SQR1_SQ26_4 (0x10U << ADC_SQR1_SQ26_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1266
AnnaBridge 171:3a7713b1edbc 1267 #define ADC_SQR1_SQ25_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1268 #define ADC_SQR1_SQ25_Msk (0x1FU << ADC_SQR1_SQ25_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 1269 #define ADC_SQR1_SQ25 ADC_SQR1_SQ25_Msk /*!< ADC group regular sequencer rank 25 */
AnnaBridge 171:3a7713b1edbc 1270 #define ADC_SQR1_SQ25_0 (0x01U << ADC_SQR1_SQ25_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1271 #define ADC_SQR1_SQ25_1 (0x02U << ADC_SQR1_SQ25_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1272 #define ADC_SQR1_SQ25_2 (0x04U << ADC_SQR1_SQ25_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1273 #define ADC_SQR1_SQ25_3 (0x08U << ADC_SQR1_SQ25_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1274 #define ADC_SQR1_SQ25_4 (0x10U << ADC_SQR1_SQ25_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1275
AnnaBridge 171:3a7713b1edbc 1276 /******************* Bit definition for ADC_SQR2 register *******************/
AnnaBridge 171:3a7713b1edbc 1277 #define ADC_SQR2_SQ19_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1278 #define ADC_SQR2_SQ19_Msk (0x1FU << ADC_SQR2_SQ19_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 1279 #define ADC_SQR2_SQ19 ADC_SQR2_SQ19_Msk /*!< ADC group regular sequencer rank 19 */
AnnaBridge 171:3a7713b1edbc 1280 #define ADC_SQR2_SQ19_0 (0x01U << ADC_SQR2_SQ19_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1281 #define ADC_SQR2_SQ19_1 (0x02U << ADC_SQR2_SQ19_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1282 #define ADC_SQR2_SQ19_2 (0x04U << ADC_SQR2_SQ19_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1283 #define ADC_SQR2_SQ19_3 (0x08U << ADC_SQR2_SQ19_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1284 #define ADC_SQR2_SQ19_4 (0x10U << ADC_SQR2_SQ19_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1285
AnnaBridge 171:3a7713b1edbc 1286 #define ADC_SQR2_SQ20_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1287 #define ADC_SQR2_SQ20_Msk (0x1FU << ADC_SQR2_SQ20_Pos) /*!< 0x000003E0 */
AnnaBridge 171:3a7713b1edbc 1288 #define ADC_SQR2_SQ20 ADC_SQR2_SQ20_Msk /*!< ADC group regular sequencer rank 20 */
AnnaBridge 171:3a7713b1edbc 1289 #define ADC_SQR2_SQ20_0 (0x01U << ADC_SQR2_SQ20_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1290 #define ADC_SQR2_SQ20_1 (0x02U << ADC_SQR2_SQ20_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1291 #define ADC_SQR2_SQ20_2 (0x04U << ADC_SQR2_SQ20_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1292 #define ADC_SQR2_SQ20_3 (0x08U << ADC_SQR2_SQ20_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1293 #define ADC_SQR2_SQ20_4 (0x10U << ADC_SQR2_SQ20_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1294
AnnaBridge 171:3a7713b1edbc 1295 #define ADC_SQR2_SQ21_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1296 #define ADC_SQR2_SQ21_Msk (0x1FU << ADC_SQR2_SQ21_Pos) /*!< 0x00007C00 */
AnnaBridge 171:3a7713b1edbc 1297 #define ADC_SQR2_SQ21 ADC_SQR2_SQ21_Msk /*!< ADC group regular sequencer rank 21 */
AnnaBridge 171:3a7713b1edbc 1298 #define ADC_SQR2_SQ21_0 (0x01U << ADC_SQR2_SQ21_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1299 #define ADC_SQR2_SQ21_1 (0x02U << ADC_SQR2_SQ21_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1300 #define ADC_SQR2_SQ21_2 (0x04U << ADC_SQR2_SQ21_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1301 #define ADC_SQR2_SQ21_3 (0x08U << ADC_SQR2_SQ21_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1302 #define ADC_SQR2_SQ21_4 (0x10U << ADC_SQR2_SQ21_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1303
AnnaBridge 171:3a7713b1edbc 1304 #define ADC_SQR2_SQ22_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1305 #define ADC_SQR2_SQ22_Msk (0x1FU << ADC_SQR2_SQ22_Pos) /*!< 0x000F8000 */
AnnaBridge 171:3a7713b1edbc 1306 #define ADC_SQR2_SQ22 ADC_SQR2_SQ22_Msk /*!< ADC group regular sequencer rank 22 */
AnnaBridge 171:3a7713b1edbc 1307 #define ADC_SQR2_SQ22_0 (0x01U << ADC_SQR2_SQ22_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1308 #define ADC_SQR2_SQ22_1 (0x02U << ADC_SQR2_SQ22_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1309 #define ADC_SQR2_SQ22_2 (0x04U << ADC_SQR2_SQ22_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1310 #define ADC_SQR2_SQ22_3 (0x08U << ADC_SQR2_SQ22_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1311 #define ADC_SQR2_SQ22_4 (0x10U << ADC_SQR2_SQ22_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1312
AnnaBridge 171:3a7713b1edbc 1313 #define ADC_SQR2_SQ23_Pos (20U)
AnnaBridge 171:3a7713b1edbc 1314 #define ADC_SQR2_SQ23_Msk (0x1FU << ADC_SQR2_SQ23_Pos) /*!< 0x01F00000 */
AnnaBridge 171:3a7713b1edbc 1315 #define ADC_SQR2_SQ23 ADC_SQR2_SQ23_Msk /*!< ADC group regular sequencer rank 23 */
AnnaBridge 171:3a7713b1edbc 1316 #define ADC_SQR2_SQ23_0 (0x01U << ADC_SQR2_SQ23_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1317 #define ADC_SQR2_SQ23_1 (0x02U << ADC_SQR2_SQ23_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1318 #define ADC_SQR2_SQ23_2 (0x04U << ADC_SQR2_SQ23_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1319 #define ADC_SQR2_SQ23_3 (0x08U << ADC_SQR2_SQ23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1320 #define ADC_SQR2_SQ23_4 (0x10U << ADC_SQR2_SQ23_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1321
AnnaBridge 171:3a7713b1edbc 1322 #define ADC_SQR2_SQ24_Pos (25U)
AnnaBridge 171:3a7713b1edbc 1323 #define ADC_SQR2_SQ24_Msk (0x1FU << ADC_SQR2_SQ24_Pos) /*!< 0x3E000000 */
AnnaBridge 171:3a7713b1edbc 1324 #define ADC_SQR2_SQ24 ADC_SQR2_SQ24_Msk /*!< ADC group regular sequencer rank 24 */
AnnaBridge 171:3a7713b1edbc 1325 #define ADC_SQR2_SQ24_0 (0x01U << ADC_SQR2_SQ24_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1326 #define ADC_SQR2_SQ24_1 (0x02U << ADC_SQR2_SQ24_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1327 #define ADC_SQR2_SQ24_2 (0x04U << ADC_SQR2_SQ24_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1328 #define ADC_SQR2_SQ24_3 (0x08U << ADC_SQR2_SQ24_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1329 #define ADC_SQR2_SQ24_4 (0x10U << ADC_SQR2_SQ24_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1330
AnnaBridge 171:3a7713b1edbc 1331 /******************* Bit definition for ADC_SQR3 register *******************/
AnnaBridge 171:3a7713b1edbc 1332 #define ADC_SQR3_SQ13_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1333 #define ADC_SQR3_SQ13_Msk (0x1FU << ADC_SQR3_SQ13_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 1334 #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
AnnaBridge 171:3a7713b1edbc 1335 #define ADC_SQR3_SQ13_0 (0x01U << ADC_SQR3_SQ13_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1336 #define ADC_SQR3_SQ13_1 (0x02U << ADC_SQR3_SQ13_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1337 #define ADC_SQR3_SQ13_2 (0x04U << ADC_SQR3_SQ13_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1338 #define ADC_SQR3_SQ13_3 (0x08U << ADC_SQR3_SQ13_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1339 #define ADC_SQR3_SQ13_4 (0x10U << ADC_SQR3_SQ13_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1340
AnnaBridge 171:3a7713b1edbc 1341 #define ADC_SQR3_SQ14_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1342 #define ADC_SQR3_SQ14_Msk (0x1FU << ADC_SQR3_SQ14_Pos) /*!< 0x000003E0 */
AnnaBridge 171:3a7713b1edbc 1343 #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
AnnaBridge 171:3a7713b1edbc 1344 #define ADC_SQR3_SQ14_0 (0x01U << ADC_SQR3_SQ14_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1345 #define ADC_SQR3_SQ14_1 (0x02U << ADC_SQR3_SQ14_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1346 #define ADC_SQR3_SQ14_2 (0x04U << ADC_SQR3_SQ14_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1347 #define ADC_SQR3_SQ14_3 (0x08U << ADC_SQR3_SQ14_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1348 #define ADC_SQR3_SQ14_4 (0x10U << ADC_SQR3_SQ14_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1349
AnnaBridge 171:3a7713b1edbc 1350 #define ADC_SQR3_SQ15_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1351 #define ADC_SQR3_SQ15_Msk (0x1FU << ADC_SQR3_SQ15_Pos) /*!< 0x00007C00 */
AnnaBridge 171:3a7713b1edbc 1352 #define ADC_SQR3_SQ15 ADC_SQR3_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
AnnaBridge 171:3a7713b1edbc 1353 #define ADC_SQR3_SQ15_0 (0x01U << ADC_SQR3_SQ15_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1354 #define ADC_SQR3_SQ15_1 (0x02U << ADC_SQR3_SQ15_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1355 #define ADC_SQR3_SQ15_2 (0x04U << ADC_SQR3_SQ15_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1356 #define ADC_SQR3_SQ15_3 (0x08U << ADC_SQR3_SQ15_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1357 #define ADC_SQR3_SQ15_4 (0x10U << ADC_SQR3_SQ15_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1358
AnnaBridge 171:3a7713b1edbc 1359 #define ADC_SQR3_SQ16_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1360 #define ADC_SQR3_SQ16_Msk (0x1FU << ADC_SQR3_SQ16_Pos) /*!< 0x000F8000 */
AnnaBridge 171:3a7713b1edbc 1361 #define ADC_SQR3_SQ16 ADC_SQR3_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
AnnaBridge 171:3a7713b1edbc 1362 #define ADC_SQR3_SQ16_0 (0x01U << ADC_SQR3_SQ16_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1363 #define ADC_SQR3_SQ16_1 (0x02U << ADC_SQR3_SQ16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1364 #define ADC_SQR3_SQ16_2 (0x04U << ADC_SQR3_SQ16_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1365 #define ADC_SQR3_SQ16_3 (0x08U << ADC_SQR3_SQ16_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1366 #define ADC_SQR3_SQ16_4 (0x10U << ADC_SQR3_SQ16_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1367
AnnaBridge 171:3a7713b1edbc 1368 #define ADC_SQR3_SQ17_Pos (20U)
AnnaBridge 171:3a7713b1edbc 1369 #define ADC_SQR3_SQ17_Msk (0x1FU << ADC_SQR3_SQ17_Pos) /*!< 0x01F00000 */
AnnaBridge 171:3a7713b1edbc 1370 #define ADC_SQR3_SQ17 ADC_SQR3_SQ17_Msk /*!< ADC group regular sequencer rank 17 */
AnnaBridge 171:3a7713b1edbc 1371 #define ADC_SQR3_SQ17_0 (0x01U << ADC_SQR3_SQ17_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1372 #define ADC_SQR3_SQ17_1 (0x02U << ADC_SQR3_SQ17_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1373 #define ADC_SQR3_SQ17_2 (0x04U << ADC_SQR3_SQ17_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1374 #define ADC_SQR3_SQ17_3 (0x08U << ADC_SQR3_SQ17_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1375 #define ADC_SQR3_SQ17_4 (0x10U << ADC_SQR3_SQ17_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1376
AnnaBridge 171:3a7713b1edbc 1377 #define ADC_SQR3_SQ18_Pos (25U)
AnnaBridge 171:3a7713b1edbc 1378 #define ADC_SQR3_SQ18_Msk (0x1FU << ADC_SQR3_SQ18_Pos) /*!< 0x3E000000 */
AnnaBridge 171:3a7713b1edbc 1379 #define ADC_SQR3_SQ18 ADC_SQR3_SQ18_Msk /*!< ADC group regular sequencer rank 18 */
AnnaBridge 171:3a7713b1edbc 1380 #define ADC_SQR3_SQ18_0 (0x01U << ADC_SQR3_SQ18_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1381 #define ADC_SQR3_SQ18_1 (0x02U << ADC_SQR3_SQ18_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1382 #define ADC_SQR3_SQ18_2 (0x04U << ADC_SQR3_SQ18_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1383 #define ADC_SQR3_SQ18_3 (0x08U << ADC_SQR3_SQ18_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1384 #define ADC_SQR3_SQ18_4 (0x10U << ADC_SQR3_SQ18_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1385
AnnaBridge 171:3a7713b1edbc 1386 /******************* Bit definition for ADC_SQR4 register *******************/
AnnaBridge 171:3a7713b1edbc 1387 #define ADC_SQR4_SQ7_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1388 #define ADC_SQR4_SQ7_Msk (0x1FU << ADC_SQR4_SQ7_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 1389 #define ADC_SQR4_SQ7 ADC_SQR4_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
AnnaBridge 171:3a7713b1edbc 1390 #define ADC_SQR4_SQ7_0 (0x01U << ADC_SQR4_SQ7_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1391 #define ADC_SQR4_SQ7_1 (0x02U << ADC_SQR4_SQ7_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1392 #define ADC_SQR4_SQ7_2 (0x04U << ADC_SQR4_SQ7_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1393 #define ADC_SQR4_SQ7_3 (0x08U << ADC_SQR4_SQ7_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1394 #define ADC_SQR4_SQ7_4 (0x10U << ADC_SQR4_SQ7_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1395
AnnaBridge 171:3a7713b1edbc 1396 #define ADC_SQR4_SQ8_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1397 #define ADC_SQR4_SQ8_Msk (0x1FU << ADC_SQR4_SQ8_Pos) /*!< 0x000003E0 */
AnnaBridge 171:3a7713b1edbc 1398 #define ADC_SQR4_SQ8 ADC_SQR4_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
AnnaBridge 171:3a7713b1edbc 1399 #define ADC_SQR4_SQ8_0 (0x01U << ADC_SQR4_SQ8_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1400 #define ADC_SQR4_SQ8_1 (0x02U << ADC_SQR4_SQ8_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1401 #define ADC_SQR4_SQ8_2 (0x04U << ADC_SQR4_SQ8_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1402 #define ADC_SQR4_SQ8_3 (0x08U << ADC_SQR4_SQ8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1403 #define ADC_SQR4_SQ8_4 (0x10U << ADC_SQR4_SQ8_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1404
AnnaBridge 171:3a7713b1edbc 1405 #define ADC_SQR4_SQ9_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1406 #define ADC_SQR4_SQ9_Msk (0x1FU << ADC_SQR4_SQ9_Pos) /*!< 0x00007C00 */
AnnaBridge 171:3a7713b1edbc 1407 #define ADC_SQR4_SQ9 ADC_SQR4_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
AnnaBridge 171:3a7713b1edbc 1408 #define ADC_SQR4_SQ9_0 (0x01U << ADC_SQR4_SQ9_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1409 #define ADC_SQR4_SQ9_1 (0x02U << ADC_SQR4_SQ9_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1410 #define ADC_SQR4_SQ9_2 (0x04U << ADC_SQR4_SQ9_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1411 #define ADC_SQR4_SQ9_3 (0x08U << ADC_SQR4_SQ9_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1412 #define ADC_SQR4_SQ9_4 (0x10U << ADC_SQR4_SQ9_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1413
AnnaBridge 171:3a7713b1edbc 1414 #define ADC_SQR4_SQ10_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1415 #define ADC_SQR4_SQ10_Msk (0x1FU << ADC_SQR4_SQ10_Pos) /*!< 0x000F8000 */
AnnaBridge 171:3a7713b1edbc 1416 #define ADC_SQR4_SQ10 ADC_SQR4_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
AnnaBridge 171:3a7713b1edbc 1417 #define ADC_SQR4_SQ10_0 (0x01U << ADC_SQR4_SQ10_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1418 #define ADC_SQR4_SQ10_1 (0x02U << ADC_SQR4_SQ10_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1419 #define ADC_SQR4_SQ10_2 (0x04U << ADC_SQR4_SQ10_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1420 #define ADC_SQR4_SQ10_3 (0x08U << ADC_SQR4_SQ10_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1421 #define ADC_SQR4_SQ10_4 (0x10U << ADC_SQR4_SQ10_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1422
AnnaBridge 171:3a7713b1edbc 1423 #define ADC_SQR4_SQ11_Pos (20U)
AnnaBridge 171:3a7713b1edbc 1424 #define ADC_SQR4_SQ11_Msk (0x1FU << ADC_SQR4_SQ11_Pos) /*!< 0x01F00000 */
AnnaBridge 171:3a7713b1edbc 1425 #define ADC_SQR4_SQ11 ADC_SQR4_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
AnnaBridge 171:3a7713b1edbc 1426 #define ADC_SQR4_SQ11_0 (0x01U << ADC_SQR4_SQ11_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1427 #define ADC_SQR4_SQ11_1 (0x02U << ADC_SQR4_SQ11_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1428 #define ADC_SQR4_SQ11_2 (0x04U << ADC_SQR4_SQ11_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1429 #define ADC_SQR4_SQ11_3 (0x08U << ADC_SQR4_SQ11_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1430 #define ADC_SQR4_SQ11_4 (0x10U << ADC_SQR4_SQ11_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1431
AnnaBridge 171:3a7713b1edbc 1432 #define ADC_SQR4_SQ12_Pos (25U)
AnnaBridge 171:3a7713b1edbc 1433 #define ADC_SQR4_SQ12_Msk (0x1FU << ADC_SQR4_SQ12_Pos) /*!< 0x3E000000 */
AnnaBridge 171:3a7713b1edbc 1434 #define ADC_SQR4_SQ12 ADC_SQR4_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
AnnaBridge 171:3a7713b1edbc 1435 #define ADC_SQR4_SQ12_0 (0x01U << ADC_SQR4_SQ12_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1436 #define ADC_SQR4_SQ12_1 (0x02U << ADC_SQR4_SQ12_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1437 #define ADC_SQR4_SQ12_2 (0x04U << ADC_SQR4_SQ12_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1438 #define ADC_SQR4_SQ12_3 (0x08U << ADC_SQR4_SQ12_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1439 #define ADC_SQR4_SQ12_4 (0x10U << ADC_SQR4_SQ12_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1440
AnnaBridge 171:3a7713b1edbc 1441 /******************* Bit definition for ADC_SQR5 register *******************/
AnnaBridge 171:3a7713b1edbc 1442 #define ADC_SQR5_SQ1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1443 #define ADC_SQR5_SQ1_Msk (0x1FU << ADC_SQR5_SQ1_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 1444 #define ADC_SQR5_SQ1 ADC_SQR5_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
AnnaBridge 171:3a7713b1edbc 1445 #define ADC_SQR5_SQ1_0 (0x01U << ADC_SQR5_SQ1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1446 #define ADC_SQR5_SQ1_1 (0x02U << ADC_SQR5_SQ1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1447 #define ADC_SQR5_SQ1_2 (0x04U << ADC_SQR5_SQ1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1448 #define ADC_SQR5_SQ1_3 (0x08U << ADC_SQR5_SQ1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1449 #define ADC_SQR5_SQ1_4 (0x10U << ADC_SQR5_SQ1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1450
AnnaBridge 171:3a7713b1edbc 1451 #define ADC_SQR5_SQ2_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1452 #define ADC_SQR5_SQ2_Msk (0x1FU << ADC_SQR5_SQ2_Pos) /*!< 0x000003E0 */
AnnaBridge 171:3a7713b1edbc 1453 #define ADC_SQR5_SQ2 ADC_SQR5_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
AnnaBridge 171:3a7713b1edbc 1454 #define ADC_SQR5_SQ2_0 (0x01U << ADC_SQR5_SQ2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1455 #define ADC_SQR5_SQ2_1 (0x02U << ADC_SQR5_SQ2_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1456 #define ADC_SQR5_SQ2_2 (0x04U << ADC_SQR5_SQ2_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1457 #define ADC_SQR5_SQ2_3 (0x08U << ADC_SQR5_SQ2_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1458 #define ADC_SQR5_SQ2_4 (0x10U << ADC_SQR5_SQ2_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1459
AnnaBridge 171:3a7713b1edbc 1460 #define ADC_SQR5_SQ3_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1461 #define ADC_SQR5_SQ3_Msk (0x1FU << ADC_SQR5_SQ3_Pos) /*!< 0x00007C00 */
AnnaBridge 171:3a7713b1edbc 1462 #define ADC_SQR5_SQ3 ADC_SQR5_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
AnnaBridge 171:3a7713b1edbc 1463 #define ADC_SQR5_SQ3_0 (0x01U << ADC_SQR5_SQ3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1464 #define ADC_SQR5_SQ3_1 (0x02U << ADC_SQR5_SQ3_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1465 #define ADC_SQR5_SQ3_2 (0x04U << ADC_SQR5_SQ3_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1466 #define ADC_SQR5_SQ3_3 (0x08U << ADC_SQR5_SQ3_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1467 #define ADC_SQR5_SQ3_4 (0x10U << ADC_SQR5_SQ3_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1468
AnnaBridge 171:3a7713b1edbc 1469 #define ADC_SQR5_SQ4_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1470 #define ADC_SQR5_SQ4_Msk (0x1FU << ADC_SQR5_SQ4_Pos) /*!< 0x000F8000 */
AnnaBridge 171:3a7713b1edbc 1471 #define ADC_SQR5_SQ4 ADC_SQR5_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
AnnaBridge 171:3a7713b1edbc 1472 #define ADC_SQR5_SQ4_0 (0x01U << ADC_SQR5_SQ4_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1473 #define ADC_SQR5_SQ4_1 (0x02U << ADC_SQR5_SQ4_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1474 #define ADC_SQR5_SQ4_2 (0x04U << ADC_SQR5_SQ4_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1475 #define ADC_SQR5_SQ4_3 (0x08U << ADC_SQR5_SQ4_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1476 #define ADC_SQR5_SQ4_4 (0x10U << ADC_SQR5_SQ4_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1477
AnnaBridge 171:3a7713b1edbc 1478 #define ADC_SQR5_SQ5_Pos (20U)
AnnaBridge 171:3a7713b1edbc 1479 #define ADC_SQR5_SQ5_Msk (0x1FU << ADC_SQR5_SQ5_Pos) /*!< 0x01F00000 */
AnnaBridge 171:3a7713b1edbc 1480 #define ADC_SQR5_SQ5 ADC_SQR5_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
AnnaBridge 171:3a7713b1edbc 1481 #define ADC_SQR5_SQ5_0 (0x01U << ADC_SQR5_SQ5_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1482 #define ADC_SQR5_SQ5_1 (0x02U << ADC_SQR5_SQ5_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1483 #define ADC_SQR5_SQ5_2 (0x04U << ADC_SQR5_SQ5_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1484 #define ADC_SQR5_SQ5_3 (0x08U << ADC_SQR5_SQ5_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1485 #define ADC_SQR5_SQ5_4 (0x10U << ADC_SQR5_SQ5_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1486
AnnaBridge 171:3a7713b1edbc 1487 #define ADC_SQR5_SQ6_Pos (25U)
AnnaBridge 171:3a7713b1edbc 1488 #define ADC_SQR5_SQ6_Msk (0x1FU << ADC_SQR5_SQ6_Pos) /*!< 0x3E000000 */
AnnaBridge 171:3a7713b1edbc 1489 #define ADC_SQR5_SQ6 ADC_SQR5_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
AnnaBridge 171:3a7713b1edbc 1490 #define ADC_SQR5_SQ6_0 (0x01U << ADC_SQR5_SQ6_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1491 #define ADC_SQR5_SQ6_1 (0x02U << ADC_SQR5_SQ6_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1492 #define ADC_SQR5_SQ6_2 (0x04U << ADC_SQR5_SQ6_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1493 #define ADC_SQR5_SQ6_3 (0x08U << ADC_SQR5_SQ6_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1494 #define ADC_SQR5_SQ6_4 (0x10U << ADC_SQR5_SQ6_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1495
AnnaBridge 171:3a7713b1edbc 1496
AnnaBridge 171:3a7713b1edbc 1497 /******************* Bit definition for ADC_JSQR register *******************/
AnnaBridge 171:3a7713b1edbc 1498 #define ADC_JSQR_JSQ1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1499 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 1500 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
AnnaBridge 171:3a7713b1edbc 1501 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1502 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1503 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1504 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1505 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1506
AnnaBridge 171:3a7713b1edbc 1507 #define ADC_JSQR_JSQ2_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1508 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
AnnaBridge 171:3a7713b1edbc 1509 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
AnnaBridge 171:3a7713b1edbc 1510 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1511 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1512 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1513 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1514 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1515
AnnaBridge 171:3a7713b1edbc 1516 #define ADC_JSQR_JSQ3_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1517 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
AnnaBridge 171:3a7713b1edbc 1518 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
AnnaBridge 171:3a7713b1edbc 1519 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1520 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1521 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1522 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1523 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1524
AnnaBridge 171:3a7713b1edbc 1525 #define ADC_JSQR_JSQ4_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1526 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
AnnaBridge 171:3a7713b1edbc 1527 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
AnnaBridge 171:3a7713b1edbc 1528 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1529 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1530 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1531 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1532 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1533
AnnaBridge 171:3a7713b1edbc 1534 #define ADC_JSQR_JL_Pos (20U)
AnnaBridge 171:3a7713b1edbc 1535 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 1536 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
AnnaBridge 171:3a7713b1edbc 1537 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1538 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1539
AnnaBridge 171:3a7713b1edbc 1540 /******************* Bit definition for ADC_JDR1 register *******************/
AnnaBridge 171:3a7713b1edbc 1541 #define ADC_JDR1_JDATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1542 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 1543 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
AnnaBridge 171:3a7713b1edbc 1544
AnnaBridge 171:3a7713b1edbc 1545 /******************* Bit definition for ADC_JDR2 register *******************/
AnnaBridge 171:3a7713b1edbc 1546 #define ADC_JDR2_JDATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1547 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 1548 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
AnnaBridge 171:3a7713b1edbc 1549
AnnaBridge 171:3a7713b1edbc 1550 /******************* Bit definition for ADC_JDR3 register *******************/
AnnaBridge 171:3a7713b1edbc 1551 #define ADC_JDR3_JDATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1552 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 1553 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
AnnaBridge 171:3a7713b1edbc 1554
AnnaBridge 171:3a7713b1edbc 1555 /******************* Bit definition for ADC_JDR4 register *******************/
AnnaBridge 171:3a7713b1edbc 1556 #define ADC_JDR4_JDATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1557 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 1558 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
AnnaBridge 171:3a7713b1edbc 1559
AnnaBridge 171:3a7713b1edbc 1560 /******************** Bit definition for ADC_DR register ********************/
AnnaBridge 171:3a7713b1edbc 1561 #define ADC_DR_DATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1562 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 1563 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
AnnaBridge 171:3a7713b1edbc 1564
AnnaBridge 171:3a7713b1edbc 1565 /******************* Bit definition for ADC_CSR register ********************/
AnnaBridge 171:3a7713b1edbc 1566 #define ADC_CSR_AWD1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1567 #define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1568 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!< ADC multimode master analog watchdog 1 flag */
AnnaBridge 171:3a7713b1edbc 1569 #define ADC_CSR_EOCS1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 1570 #define ADC_CSR_EOCS1_Msk (0x1U << ADC_CSR_EOCS1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1571 #define ADC_CSR_EOCS1 ADC_CSR_EOCS1_Msk /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */
AnnaBridge 171:3a7713b1edbc 1572 #define ADC_CSR_JEOS1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1573 #define ADC_CSR_JEOS1_Msk (0x1U << ADC_CSR_JEOS1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1574 #define ADC_CSR_JEOS1 ADC_CSR_JEOS1_Msk /*!< ADC multimode master group injected end of sequence conversions flag */
AnnaBridge 171:3a7713b1edbc 1575 #define ADC_CSR_JSTRT1_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1576 #define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1577 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!< ADC multimode master group injected conversion start flag */
AnnaBridge 171:3a7713b1edbc 1578 #define ADC_CSR_STRT1_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1579 #define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1580 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!< ADC multimode master group regular conversion start flag */
AnnaBridge 171:3a7713b1edbc 1581 #define ADC_CSR_OVR1_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1582 #define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1583 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!< ADC multimode master group regular overrun flag */
AnnaBridge 171:3a7713b1edbc 1584 #define ADC_CSR_ADONS1_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1585 #define ADC_CSR_ADONS1_Msk (0x1U << ADC_CSR_ADONS1_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1586 #define ADC_CSR_ADONS1 ADC_CSR_ADONS1_Msk /*!< ADC multimode master ready flag */
AnnaBridge 171:3a7713b1edbc 1587
AnnaBridge 171:3a7713b1edbc 1588 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 1589 #define ADC_CSR_EOC1 (ADC_CSR_EOCS1)
AnnaBridge 171:3a7713b1edbc 1590 #define ADC_CSR_JEOC1 (ADC_CSR_JEOS1)
AnnaBridge 171:3a7713b1edbc 1591
AnnaBridge 171:3a7713b1edbc 1592 /******************* Bit definition for ADC_CCR register ********************/
AnnaBridge 171:3a7713b1edbc 1593 #define ADC_CCR_ADCPRE_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1594 #define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 1595 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!< ADC clock source asynchronous prescaler */
AnnaBridge 171:3a7713b1edbc 1596 #define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1597 #define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1598 #define ADC_CCR_TSVREFE_Pos (23U)
AnnaBridge 171:3a7713b1edbc 1599 #define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1600 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */
AnnaBridge 171:3a7713b1edbc 1601
AnnaBridge 171:3a7713b1edbc 1602 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1603 /* */
AnnaBridge 171:3a7713b1edbc 1604 /* Analog Comparators (COMP) */
AnnaBridge 171:3a7713b1edbc 1605 /* */
AnnaBridge 171:3a7713b1edbc 1606 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1607
AnnaBridge 171:3a7713b1edbc 1608 /****************** Bit definition for COMP_CSR register ********************/
AnnaBridge 171:3a7713b1edbc 1609 #define COMP_CSR_10KPU (0x00000001U) /*!< Comparator 1 input plus 10K pull-up resistor */
AnnaBridge 171:3a7713b1edbc 1610 #define COMP_CSR_400KPU (0x00000002U) /*!< Comparator 1 input plus 400K pull-up resistor */
AnnaBridge 171:3a7713b1edbc 1611 #define COMP_CSR_10KPD (0x00000004U) /*!< Comparator 1 input plus 10K pull-down resistor */
AnnaBridge 171:3a7713b1edbc 1612 #define COMP_CSR_400KPD (0x00000008U) /*!< Comparator 1 input plus 400K pull-down resistor */
AnnaBridge 171:3a7713b1edbc 1613 #define COMP_CSR_CMP1EN_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1614 #define COMP_CSR_CMP1EN_Msk (0x1U << COMP_CSR_CMP1EN_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1615 #define COMP_CSR_CMP1EN COMP_CSR_CMP1EN_Msk /*!< Comparator 1 enable */
AnnaBridge 171:3a7713b1edbc 1616 #define COMP_CSR_CMP1OUT_Pos (7U)
AnnaBridge 171:3a7713b1edbc 1617 #define COMP_CSR_CMP1OUT_Msk (0x1U << COMP_CSR_CMP1OUT_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1618 #define COMP_CSR_CMP1OUT COMP_CSR_CMP1OUT_Msk /*!< Comparator 1 output level */
AnnaBridge 171:3a7713b1edbc 1619 #define COMP_CSR_SPEED_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1620 #define COMP_CSR_SPEED_Msk (0x1U << COMP_CSR_SPEED_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1621 #define COMP_CSR_SPEED COMP_CSR_SPEED_Msk /*!< Comparator 2 power mode */
AnnaBridge 171:3a7713b1edbc 1622 #define COMP_CSR_CMP2OUT_Pos (13U)
AnnaBridge 171:3a7713b1edbc 1623 #define COMP_CSR_CMP2OUT_Msk (0x1U << COMP_CSR_CMP2OUT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1624 #define COMP_CSR_CMP2OUT COMP_CSR_CMP2OUT_Msk /*!< Comparator 2 output level */
AnnaBridge 171:3a7713b1edbc 1625
AnnaBridge 171:3a7713b1edbc 1626 #define COMP_CSR_WNDWE_Pos (17U)
AnnaBridge 171:3a7713b1edbc 1627 #define COMP_CSR_WNDWE_Msk (0x1U << COMP_CSR_WNDWE_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1628 #define COMP_CSR_WNDWE COMP_CSR_WNDWE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
AnnaBridge 171:3a7713b1edbc 1629
AnnaBridge 171:3a7713b1edbc 1630 #define COMP_CSR_INSEL_Pos (18U)
AnnaBridge 171:3a7713b1edbc 1631 #define COMP_CSR_INSEL_Msk (0x7U << COMP_CSR_INSEL_Pos) /*!< 0x001C0000 */
AnnaBridge 171:3a7713b1edbc 1632 #define COMP_CSR_INSEL COMP_CSR_INSEL_Msk /*!< Comparator 2 input minus selection */
AnnaBridge 171:3a7713b1edbc 1633 #define COMP_CSR_INSEL_0 (0x1U << COMP_CSR_INSEL_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1634 #define COMP_CSR_INSEL_1 (0x2U << COMP_CSR_INSEL_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1635 #define COMP_CSR_INSEL_2 (0x4U << COMP_CSR_INSEL_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1636 #define COMP_CSR_OUTSEL_Pos (21U)
AnnaBridge 171:3a7713b1edbc 1637 #define COMP_CSR_OUTSEL_Msk (0x7U << COMP_CSR_OUTSEL_Pos) /*!< 0x00E00000 */
AnnaBridge 171:3a7713b1edbc 1638 #define COMP_CSR_OUTSEL COMP_CSR_OUTSEL_Msk /*!< Comparator 2 output redirection */
AnnaBridge 171:3a7713b1edbc 1639 #define COMP_CSR_OUTSEL_0 (0x1U << COMP_CSR_OUTSEL_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1640 #define COMP_CSR_OUTSEL_1 (0x2U << COMP_CSR_OUTSEL_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1641 #define COMP_CSR_OUTSEL_2 (0x4U << COMP_CSR_OUTSEL_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1642
AnnaBridge 171:3a7713b1edbc 1643 /* Bits present in COMP register but not related to comparator */
AnnaBridge 171:3a7713b1edbc 1644 /* (or partially related to comparator, in addition to other peripherals) */
AnnaBridge 171:3a7713b1edbc 1645 #define COMP_CSR_VREFOUTEN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1646 #define COMP_CSR_VREFOUTEN_Msk (0x1U << COMP_CSR_VREFOUTEN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1647 #define COMP_CSR_VREFOUTEN COMP_CSR_VREFOUTEN_Msk /*!< VrefInt output enable on GPIO group 3 */
AnnaBridge 171:3a7713b1edbc 1648
AnnaBridge 171:3a7713b1edbc 1649 #define COMP_CSR_FCH3_Pos (26U)
AnnaBridge 171:3a7713b1edbc 1650 #define COMP_CSR_FCH3_Msk (0x1U << COMP_CSR_FCH3_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1651 #define COMP_CSR_FCH3 COMP_CSR_FCH3_Msk /*!< Bit 26 */
AnnaBridge 171:3a7713b1edbc 1652 #define COMP_CSR_FCH8_Pos (27U)
AnnaBridge 171:3a7713b1edbc 1653 #define COMP_CSR_FCH8_Msk (0x1U << COMP_CSR_FCH8_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1654 #define COMP_CSR_FCH8 COMP_CSR_FCH8_Msk /*!< Bit 27 */
AnnaBridge 171:3a7713b1edbc 1655 #define COMP_CSR_RCH13_Pos (28U)
AnnaBridge 171:3a7713b1edbc 1656 #define COMP_CSR_RCH13_Msk (0x1U << COMP_CSR_RCH13_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1657 #define COMP_CSR_RCH13 COMP_CSR_RCH13_Msk /*!< Bit 28 */
AnnaBridge 171:3a7713b1edbc 1658
AnnaBridge 171:3a7713b1edbc 1659 #define COMP_CSR_CAIE_Pos (29U)
AnnaBridge 171:3a7713b1edbc 1660 #define COMP_CSR_CAIE_Msk (0x1U << COMP_CSR_CAIE_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1661 #define COMP_CSR_CAIE COMP_CSR_CAIE_Msk /*!< Bit 29 */
AnnaBridge 171:3a7713b1edbc 1662 #define COMP_CSR_CAIF_Pos (30U)
AnnaBridge 171:3a7713b1edbc 1663 #define COMP_CSR_CAIF_Msk (0x1U << COMP_CSR_CAIF_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 1664 #define COMP_CSR_CAIF COMP_CSR_CAIF_Msk /*!< Bit 30 */
AnnaBridge 171:3a7713b1edbc 1665 #define COMP_CSR_TSUSP_Pos (31U)
AnnaBridge 171:3a7713b1edbc 1666 #define COMP_CSR_TSUSP_Msk (0x1U << COMP_CSR_TSUSP_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 1667 #define COMP_CSR_TSUSP COMP_CSR_TSUSP_Msk /*!< Bit 31 */
AnnaBridge 171:3a7713b1edbc 1668
AnnaBridge 171:3a7713b1edbc 1669 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1670 /* */
AnnaBridge 171:3a7713b1edbc 1671 /* Operational Amplifier (OPAMP) */
AnnaBridge 171:3a7713b1edbc 1672 /* */
AnnaBridge 171:3a7713b1edbc 1673 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1674 /******************* Bit definition for OPAMP_CSR register ******************/
AnnaBridge 171:3a7713b1edbc 1675 #define OPAMP_CSR_OPA1PD_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1676 #define OPAMP_CSR_OPA1PD_Msk (0x1U << OPAMP_CSR_OPA1PD_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1677 #define OPAMP_CSR_OPA1PD OPAMP_CSR_OPA1PD_Msk /*!< OPAMP1 disable */
AnnaBridge 171:3a7713b1edbc 1678 #define OPAMP_CSR_S3SEL1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 1679 #define OPAMP_CSR_S3SEL1_Msk (0x1U << OPAMP_CSR_S3SEL1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1680 #define OPAMP_CSR_S3SEL1 OPAMP_CSR_S3SEL1_Msk /*!< Switch 3 for OPAMP1 Enable */
AnnaBridge 171:3a7713b1edbc 1681 #define OPAMP_CSR_S4SEL1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1682 #define OPAMP_CSR_S4SEL1_Msk (0x1U << OPAMP_CSR_S4SEL1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1683 #define OPAMP_CSR_S4SEL1 OPAMP_CSR_S4SEL1_Msk /*!< Switch 4 for OPAMP1 Enable */
AnnaBridge 171:3a7713b1edbc 1684 #define OPAMP_CSR_S5SEL1_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1685 #define OPAMP_CSR_S5SEL1_Msk (0x1U << OPAMP_CSR_S5SEL1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1686 #define OPAMP_CSR_S5SEL1 OPAMP_CSR_S5SEL1_Msk /*!< Switch 5 for OPAMP1 Enable */
AnnaBridge 171:3a7713b1edbc 1687 #define OPAMP_CSR_S6SEL1_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1688 #define OPAMP_CSR_S6SEL1_Msk (0x1U << OPAMP_CSR_S6SEL1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1689 #define OPAMP_CSR_S6SEL1 OPAMP_CSR_S6SEL1_Msk /*!< Switch 6 for OPAMP1 Enable */
AnnaBridge 171:3a7713b1edbc 1690 #define OPAMP_CSR_OPA1CAL_L_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1691 #define OPAMP_CSR_OPA1CAL_L_Msk (0x1U << OPAMP_CSR_OPA1CAL_L_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1692 #define OPAMP_CSR_OPA1CAL_L OPAMP_CSR_OPA1CAL_L_Msk /*!< OPAMP1 Offset calibration for P differential pair */
AnnaBridge 171:3a7713b1edbc 1693 #define OPAMP_CSR_OPA1CAL_H_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1694 #define OPAMP_CSR_OPA1CAL_H_Msk (0x1U << OPAMP_CSR_OPA1CAL_H_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1695 #define OPAMP_CSR_OPA1CAL_H OPAMP_CSR_OPA1CAL_H_Msk /*!< OPAMP1 Offset calibration for N differential pair */
AnnaBridge 171:3a7713b1edbc 1696 #define OPAMP_CSR_OPA1LPM_Pos (7U)
AnnaBridge 171:3a7713b1edbc 1697 #define OPAMP_CSR_OPA1LPM_Msk (0x1U << OPAMP_CSR_OPA1LPM_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1698 #define OPAMP_CSR_OPA1LPM OPAMP_CSR_OPA1LPM_Msk /*!< OPAMP1 Low power enable */
AnnaBridge 171:3a7713b1edbc 1699 #define OPAMP_CSR_OPA2PD_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1700 #define OPAMP_CSR_OPA2PD_Msk (0x1U << OPAMP_CSR_OPA2PD_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1701 #define OPAMP_CSR_OPA2PD OPAMP_CSR_OPA2PD_Msk /*!< OPAMP2 disable */
AnnaBridge 171:3a7713b1edbc 1702 #define OPAMP_CSR_S3SEL2_Pos (9U)
AnnaBridge 171:3a7713b1edbc 1703 #define OPAMP_CSR_S3SEL2_Msk (0x1U << OPAMP_CSR_S3SEL2_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1704 #define OPAMP_CSR_S3SEL2 OPAMP_CSR_S3SEL2_Msk /*!< Switch 3 for OPAMP2 Enable */
AnnaBridge 171:3a7713b1edbc 1705 #define OPAMP_CSR_S4SEL2_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1706 #define OPAMP_CSR_S4SEL2_Msk (0x1U << OPAMP_CSR_S4SEL2_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1707 #define OPAMP_CSR_S4SEL2 OPAMP_CSR_S4SEL2_Msk /*!< Switch 4 for OPAMP2 Enable */
AnnaBridge 171:3a7713b1edbc 1708 #define OPAMP_CSR_S5SEL2_Pos (11U)
AnnaBridge 171:3a7713b1edbc 1709 #define OPAMP_CSR_S5SEL2_Msk (0x1U << OPAMP_CSR_S5SEL2_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1710 #define OPAMP_CSR_S5SEL2 OPAMP_CSR_S5SEL2_Msk /*!< Switch 5 for OPAMP2 Enable */
AnnaBridge 171:3a7713b1edbc 1711 #define OPAMP_CSR_S6SEL2_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1712 #define OPAMP_CSR_S6SEL2_Msk (0x1U << OPAMP_CSR_S6SEL2_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1713 #define OPAMP_CSR_S6SEL2 OPAMP_CSR_S6SEL2_Msk /*!< Switch 6 for OPAMP2 Enable */
AnnaBridge 171:3a7713b1edbc 1714 #define OPAMP_CSR_OPA2CAL_L_Pos (13U)
AnnaBridge 171:3a7713b1edbc 1715 #define OPAMP_CSR_OPA2CAL_L_Msk (0x1U << OPAMP_CSR_OPA2CAL_L_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1716 #define OPAMP_CSR_OPA2CAL_L OPAMP_CSR_OPA2CAL_L_Msk /*!< OPAMP2 Offset calibration for P differential pair */
AnnaBridge 171:3a7713b1edbc 1717 #define OPAMP_CSR_OPA2CAL_H_Pos (14U)
AnnaBridge 171:3a7713b1edbc 1718 #define OPAMP_CSR_OPA2CAL_H_Msk (0x1U << OPAMP_CSR_OPA2CAL_H_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1719 #define OPAMP_CSR_OPA2CAL_H OPAMP_CSR_OPA2CAL_H_Msk /*!< OPAMP2 Offset calibration for N differential pair */
AnnaBridge 171:3a7713b1edbc 1720 #define OPAMP_CSR_OPA2LPM_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1721 #define OPAMP_CSR_OPA2LPM_Msk (0x1U << OPAMP_CSR_OPA2LPM_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1722 #define OPAMP_CSR_OPA2LPM OPAMP_CSR_OPA2LPM_Msk /*!< OPAMP2 Low power enable */
AnnaBridge 171:3a7713b1edbc 1723 #define OPAMP_CSR_ANAWSEL1_Pos (24U)
AnnaBridge 171:3a7713b1edbc 1724 #define OPAMP_CSR_ANAWSEL1_Msk (0x1U << OPAMP_CSR_ANAWSEL1_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1725 #define OPAMP_CSR_ANAWSEL1 OPAMP_CSR_ANAWSEL1_Msk /*!< Switch ANA Enable for OPAMP1 */
AnnaBridge 171:3a7713b1edbc 1726 #define OPAMP_CSR_ANAWSEL2_Pos (25U)
AnnaBridge 171:3a7713b1edbc 1727 #define OPAMP_CSR_ANAWSEL2_Msk (0x1U << OPAMP_CSR_ANAWSEL2_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1728 #define OPAMP_CSR_ANAWSEL2 OPAMP_CSR_ANAWSEL2_Msk /*!< Switch ANA Enable for OPAMP2 */
AnnaBridge 171:3a7713b1edbc 1729 #define OPAMP_CSR_S7SEL2_Pos (27U)
AnnaBridge 171:3a7713b1edbc 1730 #define OPAMP_CSR_S7SEL2_Msk (0x1U << OPAMP_CSR_S7SEL2_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1731 #define OPAMP_CSR_S7SEL2 OPAMP_CSR_S7SEL2_Msk /*!< Switch 7 for OPAMP2 Enable */
AnnaBridge 171:3a7713b1edbc 1732 #define OPAMP_CSR_AOP_RANGE_Pos (28U)
AnnaBridge 171:3a7713b1edbc 1733 #define OPAMP_CSR_AOP_RANGE_Msk (0x1U << OPAMP_CSR_AOP_RANGE_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1734 #define OPAMP_CSR_AOP_RANGE OPAMP_CSR_AOP_RANGE_Msk /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
AnnaBridge 171:3a7713b1edbc 1735 #define OPAMP_CSR_OPA1CALOUT_Pos (29U)
AnnaBridge 171:3a7713b1edbc 1736 #define OPAMP_CSR_OPA1CALOUT_Msk (0x1U << OPAMP_CSR_OPA1CALOUT_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1737 #define OPAMP_CSR_OPA1CALOUT OPAMP_CSR_OPA1CALOUT_Msk /*!< OPAMP1 calibration output */
AnnaBridge 171:3a7713b1edbc 1738 #define OPAMP_CSR_OPA2CALOUT_Pos (30U)
AnnaBridge 171:3a7713b1edbc 1739 #define OPAMP_CSR_OPA2CALOUT_Msk (0x1U << OPAMP_CSR_OPA2CALOUT_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 1740 #define OPAMP_CSR_OPA2CALOUT OPAMP_CSR_OPA2CALOUT_Msk /*!< OPAMP2 calibration output */
AnnaBridge 171:3a7713b1edbc 1741
AnnaBridge 171:3a7713b1edbc 1742 /******************* Bit definition for OPAMP_OTR register ******************/
AnnaBridge 171:3a7713b1edbc 1743 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1744 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 1745 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
AnnaBridge 171:3a7713b1edbc 1746 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1747 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000003E0 */
AnnaBridge 171:3a7713b1edbc 1748 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
AnnaBridge 171:3a7713b1edbc 1749 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1750 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x00007C00 */
AnnaBridge 171:3a7713b1edbc 1751 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
AnnaBridge 171:3a7713b1edbc 1752 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1753 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000F8000 */
AnnaBridge 171:3a7713b1edbc 1754 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
AnnaBridge 171:3a7713b1edbc 1755 #define OPAMP_OTR_OT_USER_Pos (31U)
AnnaBridge 171:3a7713b1edbc 1756 #define OPAMP_OTR_OT_USER_Msk (0x1U << OPAMP_OTR_OT_USER_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 1757 #define OPAMP_OTR_OT_USER OPAMP_OTR_OT_USER_Msk /*!< Switch to OPAMP offset user trimmed values */
AnnaBridge 171:3a7713b1edbc 1758
AnnaBridge 171:3a7713b1edbc 1759 /******************* Bit definition for OPAMP_LPOTR register ****************/
AnnaBridge 171:3a7713b1edbc 1760 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1761 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 1762 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
AnnaBridge 171:3a7713b1edbc 1763 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1764 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000003E0 */
AnnaBridge 171:3a7713b1edbc 1765 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
AnnaBridge 171:3a7713b1edbc 1766 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1767 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x00007C00 */
AnnaBridge 171:3a7713b1edbc 1768 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
AnnaBridge 171:3a7713b1edbc 1769 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1770 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000F8000 */
AnnaBridge 171:3a7713b1edbc 1771 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
AnnaBridge 171:3a7713b1edbc 1772
AnnaBridge 171:3a7713b1edbc 1773 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1774 /* */
AnnaBridge 171:3a7713b1edbc 1775 /* CRC calculation unit (CRC) */
AnnaBridge 171:3a7713b1edbc 1776 /* */
AnnaBridge 171:3a7713b1edbc 1777 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1778
AnnaBridge 171:3a7713b1edbc 1779 /******************* Bit definition for CRC_DR register *********************/
AnnaBridge 171:3a7713b1edbc 1780 #define CRC_DR_DR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1781 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 1782 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
AnnaBridge 171:3a7713b1edbc 1783
AnnaBridge 171:3a7713b1edbc 1784 /******************* Bit definition for CRC_IDR register ********************/
AnnaBridge 171:3a7713b1edbc 1785 #define CRC_IDR_IDR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1786 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 1787 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
AnnaBridge 171:3a7713b1edbc 1788
AnnaBridge 171:3a7713b1edbc 1789 /******************** Bit definition for CRC_CR register ********************/
AnnaBridge 171:3a7713b1edbc 1790 #define CRC_CR_RESET_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1791 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1792 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
AnnaBridge 171:3a7713b1edbc 1793
AnnaBridge 171:3a7713b1edbc 1794 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1795 /* */
AnnaBridge 171:3a7713b1edbc 1796 /* Digital to Analog Converter (DAC) */
AnnaBridge 171:3a7713b1edbc 1797 /* */
AnnaBridge 171:3a7713b1edbc 1798 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1799
AnnaBridge 171:3a7713b1edbc 1800 /******************** Bit definition for DAC_CR register ********************/
AnnaBridge 171:3a7713b1edbc 1801 #define DAC_CR_EN1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1802 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1803 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
AnnaBridge 171:3a7713b1edbc 1804 #define DAC_CR_BOFF1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 1805 #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1806 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
AnnaBridge 171:3a7713b1edbc 1807 #define DAC_CR_TEN1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1808 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1809 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
AnnaBridge 171:3a7713b1edbc 1810
AnnaBridge 171:3a7713b1edbc 1811 #define DAC_CR_TSEL1_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1812 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
AnnaBridge 171:3a7713b1edbc 1813 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
AnnaBridge 171:3a7713b1edbc 1814 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1815 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1816 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1817
AnnaBridge 171:3a7713b1edbc 1818 #define DAC_CR_WAVE1_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1819 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 1820 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
AnnaBridge 171:3a7713b1edbc 1821 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1822 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1823
AnnaBridge 171:3a7713b1edbc 1824 #define DAC_CR_MAMP1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1825 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 1826 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
AnnaBridge 171:3a7713b1edbc 1827 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1828 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1829 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1830 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1831
AnnaBridge 171:3a7713b1edbc 1832 #define DAC_CR_DMAEN1_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1833 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1834 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
AnnaBridge 171:3a7713b1edbc 1835 #define DAC_CR_DMAUDRIE1_Pos (13U)
AnnaBridge 171:3a7713b1edbc 1836 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1837 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA Interrupt enable */
AnnaBridge 171:3a7713b1edbc 1838 #define DAC_CR_EN2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1839 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1840 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
AnnaBridge 171:3a7713b1edbc 1841 #define DAC_CR_BOFF2_Pos (17U)
AnnaBridge 171:3a7713b1edbc 1842 #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1843 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
AnnaBridge 171:3a7713b1edbc 1844 #define DAC_CR_TEN2_Pos (18U)
AnnaBridge 171:3a7713b1edbc 1845 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1846 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
AnnaBridge 171:3a7713b1edbc 1847
AnnaBridge 171:3a7713b1edbc 1848 #define DAC_CR_TSEL2_Pos (19U)
AnnaBridge 171:3a7713b1edbc 1849 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
AnnaBridge 171:3a7713b1edbc 1850 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
AnnaBridge 171:3a7713b1edbc 1851 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1852 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1853 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1854
AnnaBridge 171:3a7713b1edbc 1855 #define DAC_CR_WAVE2_Pos (22U)
AnnaBridge 171:3a7713b1edbc 1856 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
AnnaBridge 171:3a7713b1edbc 1857 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
AnnaBridge 171:3a7713b1edbc 1858 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1859 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1860
AnnaBridge 171:3a7713b1edbc 1861 #define DAC_CR_MAMP2_Pos (24U)
AnnaBridge 171:3a7713b1edbc 1862 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 1863 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
AnnaBridge 171:3a7713b1edbc 1864 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1865 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1866 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1867 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1868
AnnaBridge 171:3a7713b1edbc 1869 #define DAC_CR_DMAEN2_Pos (28U)
AnnaBridge 171:3a7713b1edbc 1870 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1871 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
AnnaBridge 171:3a7713b1edbc 1872 #define DAC_CR_DMAUDRIE2_Pos (29U)
AnnaBridge 171:3a7713b1edbc 1873 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1874 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable */
AnnaBridge 171:3a7713b1edbc 1875 /***************** Bit definition for DAC_SWTRIGR register ******************/
AnnaBridge 171:3a7713b1edbc 1876 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1877 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1878 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
AnnaBridge 171:3a7713b1edbc 1879 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 1880 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1881 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
AnnaBridge 171:3a7713b1edbc 1882
AnnaBridge 171:3a7713b1edbc 1883 /***************** Bit definition for DAC_DHR12R1 register ******************/
AnnaBridge 171:3a7713b1edbc 1884 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1885 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1886 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 1887
AnnaBridge 171:3a7713b1edbc 1888 /***************** Bit definition for DAC_DHR12L1 register ******************/
AnnaBridge 171:3a7713b1edbc 1889 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1890 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
AnnaBridge 171:3a7713b1edbc 1891 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
AnnaBridge 171:3a7713b1edbc 1892
AnnaBridge 171:3a7713b1edbc 1893 /****************** Bit definition for DAC_DHR8R1 register ******************/
AnnaBridge 171:3a7713b1edbc 1894 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1895 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 1896 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 1897
AnnaBridge 171:3a7713b1edbc 1898 /***************** Bit definition for DAC_DHR12R2 register ******************/
AnnaBridge 171:3a7713b1edbc 1899 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1900 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1901 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 1902
AnnaBridge 171:3a7713b1edbc 1903 /***************** Bit definition for DAC_DHR12L2 register ******************/
AnnaBridge 171:3a7713b1edbc 1904 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1905 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
AnnaBridge 171:3a7713b1edbc 1906 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
AnnaBridge 171:3a7713b1edbc 1907
AnnaBridge 171:3a7713b1edbc 1908 /****************** Bit definition for DAC_DHR8R2 register ******************/
AnnaBridge 171:3a7713b1edbc 1909 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1910 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 1911 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 1912
AnnaBridge 171:3a7713b1edbc 1913 /***************** Bit definition for DAC_DHR12RD register ******************/
AnnaBridge 171:3a7713b1edbc 1914 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1915 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1916 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 1917 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1918 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
AnnaBridge 171:3a7713b1edbc 1919 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 1920
AnnaBridge 171:3a7713b1edbc 1921 /***************** Bit definition for DAC_DHR12LD register ******************/
AnnaBridge 171:3a7713b1edbc 1922 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1923 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
AnnaBridge 171:3a7713b1edbc 1924 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
AnnaBridge 171:3a7713b1edbc 1925 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
AnnaBridge 171:3a7713b1edbc 1926 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
AnnaBridge 171:3a7713b1edbc 1927 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
AnnaBridge 171:3a7713b1edbc 1928
AnnaBridge 171:3a7713b1edbc 1929 /****************** Bit definition for DAC_DHR8RD register ******************/
AnnaBridge 171:3a7713b1edbc 1930 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1931 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 1932 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 1933 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1934 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 1935 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
AnnaBridge 171:3a7713b1edbc 1936
AnnaBridge 171:3a7713b1edbc 1937 /******************* Bit definition for DAC_DOR1 register *******************/
AnnaBridge 171:3a7713b1edbc 1938 #define DAC_DOR1_DACC1DOR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1939 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1940 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
AnnaBridge 171:3a7713b1edbc 1941
AnnaBridge 171:3a7713b1edbc 1942 /******************* Bit definition for DAC_DOR2 register *******************/
AnnaBridge 171:3a7713b1edbc 1943 #define DAC_DOR2_DACC2DOR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1944 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1945 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
AnnaBridge 171:3a7713b1edbc 1946
AnnaBridge 171:3a7713b1edbc 1947 /******************** Bit definition for DAC_SR register ********************/
AnnaBridge 171:3a7713b1edbc 1948 #define DAC_SR_DMAUDR1_Pos (13U)
AnnaBridge 171:3a7713b1edbc 1949 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1950 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
AnnaBridge 171:3a7713b1edbc 1951 #define DAC_SR_DMAUDR2_Pos (29U)
AnnaBridge 171:3a7713b1edbc 1952 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1953 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
AnnaBridge 171:3a7713b1edbc 1954
AnnaBridge 171:3a7713b1edbc 1955 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1956 /* */
AnnaBridge 171:3a7713b1edbc 1957 /* Debug MCU (DBGMCU) */
AnnaBridge 171:3a7713b1edbc 1958 /* */
AnnaBridge 171:3a7713b1edbc 1959 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1960
AnnaBridge 171:3a7713b1edbc 1961 /**************** Bit definition for DBGMCU_IDCODE register *****************/
AnnaBridge 171:3a7713b1edbc 1962 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1963 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 1964 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
AnnaBridge 171:3a7713b1edbc 1965
AnnaBridge 171:3a7713b1edbc 1966 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1967 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 1968 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
AnnaBridge 171:3a7713b1edbc 1969 #define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1970 #define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1971 #define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1972 #define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1973 #define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1974 #define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1975 #define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1976 #define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1977 #define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1978 #define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1979 #define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1980 #define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1981 #define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1982 #define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1983 #define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 1984 #define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 1985
AnnaBridge 171:3a7713b1edbc 1986 /****************** Bit definition for DBGMCU_CR register *******************/
AnnaBridge 171:3a7713b1edbc 1987 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1988 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1989 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
AnnaBridge 171:3a7713b1edbc 1990 #define DBGMCU_CR_DBG_STOP_Pos (1U)
AnnaBridge 171:3a7713b1edbc 1991 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1992 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
AnnaBridge 171:3a7713b1edbc 1993 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1994 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1995 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
AnnaBridge 171:3a7713b1edbc 1996 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1997 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1998 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */
AnnaBridge 171:3a7713b1edbc 1999
AnnaBridge 171:3a7713b1edbc 2000 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2001 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 2002 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
AnnaBridge 171:3a7713b1edbc 2003 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2004 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2005
AnnaBridge 171:3a7713b1edbc 2006 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
AnnaBridge 171:3a7713b1edbc 2007
AnnaBridge 171:3a7713b1edbc 2008 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2009 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2010 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
AnnaBridge 171:3a7713b1edbc 2011 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2012 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2013 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
AnnaBridge 171:3a7713b1edbc 2014 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2015 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2016 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
AnnaBridge 171:3a7713b1edbc 2017 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2018 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2019 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */
AnnaBridge 171:3a7713b1edbc 2020 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2021 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2022 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
AnnaBridge 171:3a7713b1edbc 2023 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2024 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2025 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
AnnaBridge 171:3a7713b1edbc 2026 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2027 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2028 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Counter stopped when Core is halted */
AnnaBridge 171:3a7713b1edbc 2029 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2030 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2031 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
AnnaBridge 171:3a7713b1edbc 2032 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2033 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2034 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
AnnaBridge 171:3a7713b1edbc 2035 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
AnnaBridge 171:3a7713b1edbc 2036 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 2037 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
AnnaBridge 171:3a7713b1edbc 2038 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
AnnaBridge 171:3a7713b1edbc 2039 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2040 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
AnnaBridge 171:3a7713b1edbc 2041
AnnaBridge 171:3a7713b1edbc 2042 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
AnnaBridge 171:3a7713b1edbc 2043
AnnaBridge 171:3a7713b1edbc 2044 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2045 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2046 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /*!< TIM9 counter stopped when core is halted */
AnnaBridge 171:3a7713b1edbc 2047 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2048 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2049 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /*!< TIM10 counter stopped when core is halted */
AnnaBridge 171:3a7713b1edbc 2050 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2051 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2052 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /*!< TIM11 counter stopped when core is halted */
AnnaBridge 171:3a7713b1edbc 2053
AnnaBridge 171:3a7713b1edbc 2054 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 2055 /* */
AnnaBridge 171:3a7713b1edbc 2056 /* DMA Controller (DMA) */
AnnaBridge 171:3a7713b1edbc 2057 /* */
AnnaBridge 171:3a7713b1edbc 2058 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 2059
AnnaBridge 171:3a7713b1edbc 2060 /******************* Bit definition for DMA_ISR register ********************/
AnnaBridge 171:3a7713b1edbc 2061 #define DMA_ISR_GIF1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2062 #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2063 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
AnnaBridge 171:3a7713b1edbc 2064 #define DMA_ISR_TCIF1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2065 #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2066 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
AnnaBridge 171:3a7713b1edbc 2067 #define DMA_ISR_HTIF1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2068 #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2069 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
AnnaBridge 171:3a7713b1edbc 2070 #define DMA_ISR_TEIF1_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2071 #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2072 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
AnnaBridge 171:3a7713b1edbc 2073 #define DMA_ISR_GIF2_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2074 #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2075 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
AnnaBridge 171:3a7713b1edbc 2076 #define DMA_ISR_TCIF2_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2077 #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2078 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
AnnaBridge 171:3a7713b1edbc 2079 #define DMA_ISR_HTIF2_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2080 #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2081 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
AnnaBridge 171:3a7713b1edbc 2082 #define DMA_ISR_TEIF2_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2083 #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2084 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
AnnaBridge 171:3a7713b1edbc 2085 #define DMA_ISR_GIF3_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2086 #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2087 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
AnnaBridge 171:3a7713b1edbc 2088 #define DMA_ISR_TCIF3_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2089 #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2090 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
AnnaBridge 171:3a7713b1edbc 2091 #define DMA_ISR_HTIF3_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2092 #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2093 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
AnnaBridge 171:3a7713b1edbc 2094 #define DMA_ISR_TEIF3_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2095 #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2096 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
AnnaBridge 171:3a7713b1edbc 2097 #define DMA_ISR_GIF4_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2098 #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2099 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
AnnaBridge 171:3a7713b1edbc 2100 #define DMA_ISR_TCIF4_Pos (13U)
AnnaBridge 171:3a7713b1edbc 2101 #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2102 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
AnnaBridge 171:3a7713b1edbc 2103 #define DMA_ISR_HTIF4_Pos (14U)
AnnaBridge 171:3a7713b1edbc 2104 #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2105 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
AnnaBridge 171:3a7713b1edbc 2106 #define DMA_ISR_TEIF4_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2107 #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2108 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
AnnaBridge 171:3a7713b1edbc 2109 #define DMA_ISR_GIF5_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2110 #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2111 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
AnnaBridge 171:3a7713b1edbc 2112 #define DMA_ISR_TCIF5_Pos (17U)
AnnaBridge 171:3a7713b1edbc 2113 #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2114 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
AnnaBridge 171:3a7713b1edbc 2115 #define DMA_ISR_HTIF5_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2116 #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2117 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
AnnaBridge 171:3a7713b1edbc 2118 #define DMA_ISR_TEIF5_Pos (19U)
AnnaBridge 171:3a7713b1edbc 2119 #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2120 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
AnnaBridge 171:3a7713b1edbc 2121 #define DMA_ISR_GIF6_Pos (20U)
AnnaBridge 171:3a7713b1edbc 2122 #define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2123 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
AnnaBridge 171:3a7713b1edbc 2124 #define DMA_ISR_TCIF6_Pos (21U)
AnnaBridge 171:3a7713b1edbc 2125 #define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 2126 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
AnnaBridge 171:3a7713b1edbc 2127 #define DMA_ISR_HTIF6_Pos (22U)
AnnaBridge 171:3a7713b1edbc 2128 #define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2129 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
AnnaBridge 171:3a7713b1edbc 2130 #define DMA_ISR_TEIF6_Pos (23U)
AnnaBridge 171:3a7713b1edbc 2131 #define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 2132 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
AnnaBridge 171:3a7713b1edbc 2133 #define DMA_ISR_GIF7_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2134 #define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 2135 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
AnnaBridge 171:3a7713b1edbc 2136 #define DMA_ISR_TCIF7_Pos (25U)
AnnaBridge 171:3a7713b1edbc 2137 #define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 2138 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
AnnaBridge 171:3a7713b1edbc 2139 #define DMA_ISR_HTIF7_Pos (26U)
AnnaBridge 171:3a7713b1edbc 2140 #define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 2141 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
AnnaBridge 171:3a7713b1edbc 2142 #define DMA_ISR_TEIF7_Pos (27U)
AnnaBridge 171:3a7713b1edbc 2143 #define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 2144 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
AnnaBridge 171:3a7713b1edbc 2145
AnnaBridge 171:3a7713b1edbc 2146 /******************* Bit definition for DMA_IFCR register *******************/
AnnaBridge 171:3a7713b1edbc 2147 #define DMA_IFCR_CGIF1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2148 #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2149 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
AnnaBridge 171:3a7713b1edbc 2150 #define DMA_IFCR_CTCIF1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2151 #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2152 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
AnnaBridge 171:3a7713b1edbc 2153 #define DMA_IFCR_CHTIF1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2154 #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2155 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
AnnaBridge 171:3a7713b1edbc 2156 #define DMA_IFCR_CTEIF1_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2157 #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2158 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
AnnaBridge 171:3a7713b1edbc 2159 #define DMA_IFCR_CGIF2_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2160 #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2161 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
AnnaBridge 171:3a7713b1edbc 2162 #define DMA_IFCR_CTCIF2_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2163 #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2164 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
AnnaBridge 171:3a7713b1edbc 2165 #define DMA_IFCR_CHTIF2_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2166 #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2167 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
AnnaBridge 171:3a7713b1edbc 2168 #define DMA_IFCR_CTEIF2_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2169 #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2170 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
AnnaBridge 171:3a7713b1edbc 2171 #define DMA_IFCR_CGIF3_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2172 #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2173 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
AnnaBridge 171:3a7713b1edbc 2174 #define DMA_IFCR_CTCIF3_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2175 #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2176 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
AnnaBridge 171:3a7713b1edbc 2177 #define DMA_IFCR_CHTIF3_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2178 #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2179 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
AnnaBridge 171:3a7713b1edbc 2180 #define DMA_IFCR_CTEIF3_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2181 #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2182 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
AnnaBridge 171:3a7713b1edbc 2183 #define DMA_IFCR_CGIF4_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2184 #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2185 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
AnnaBridge 171:3a7713b1edbc 2186 #define DMA_IFCR_CTCIF4_Pos (13U)
AnnaBridge 171:3a7713b1edbc 2187 #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2188 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
AnnaBridge 171:3a7713b1edbc 2189 #define DMA_IFCR_CHTIF4_Pos (14U)
AnnaBridge 171:3a7713b1edbc 2190 #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2191 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
AnnaBridge 171:3a7713b1edbc 2192 #define DMA_IFCR_CTEIF4_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2193 #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2194 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
AnnaBridge 171:3a7713b1edbc 2195 #define DMA_IFCR_CGIF5_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2196 #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2197 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
AnnaBridge 171:3a7713b1edbc 2198 #define DMA_IFCR_CTCIF5_Pos (17U)
AnnaBridge 171:3a7713b1edbc 2199 #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2200 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
AnnaBridge 171:3a7713b1edbc 2201 #define DMA_IFCR_CHTIF5_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2202 #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2203 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
AnnaBridge 171:3a7713b1edbc 2204 #define DMA_IFCR_CTEIF5_Pos (19U)
AnnaBridge 171:3a7713b1edbc 2205 #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2206 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
AnnaBridge 171:3a7713b1edbc 2207 #define DMA_IFCR_CGIF6_Pos (20U)
AnnaBridge 171:3a7713b1edbc 2208 #define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2209 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
AnnaBridge 171:3a7713b1edbc 2210 #define DMA_IFCR_CTCIF6_Pos (21U)
AnnaBridge 171:3a7713b1edbc 2211 #define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 2212 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
AnnaBridge 171:3a7713b1edbc 2213 #define DMA_IFCR_CHTIF6_Pos (22U)
AnnaBridge 171:3a7713b1edbc 2214 #define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2215 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
AnnaBridge 171:3a7713b1edbc 2216 #define DMA_IFCR_CTEIF6_Pos (23U)
AnnaBridge 171:3a7713b1edbc 2217 #define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 2218 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
AnnaBridge 171:3a7713b1edbc 2219 #define DMA_IFCR_CGIF7_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2220 #define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 2221 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
AnnaBridge 171:3a7713b1edbc 2222 #define DMA_IFCR_CTCIF7_Pos (25U)
AnnaBridge 171:3a7713b1edbc 2223 #define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 2224 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
AnnaBridge 171:3a7713b1edbc 2225 #define DMA_IFCR_CHTIF7_Pos (26U)
AnnaBridge 171:3a7713b1edbc 2226 #define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 2227 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
AnnaBridge 171:3a7713b1edbc 2228 #define DMA_IFCR_CTEIF7_Pos (27U)
AnnaBridge 171:3a7713b1edbc 2229 #define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 2230 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
AnnaBridge 171:3a7713b1edbc 2231
AnnaBridge 171:3a7713b1edbc 2232 /******************* Bit definition for DMA_CCR register *******************/
AnnaBridge 171:3a7713b1edbc 2233 #define DMA_CCR_EN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2234 #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2235 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable*/
AnnaBridge 171:3a7713b1edbc 2236 #define DMA_CCR_TCIE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2237 #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2238 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
AnnaBridge 171:3a7713b1edbc 2239 #define DMA_CCR_HTIE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2240 #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2241 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
AnnaBridge 171:3a7713b1edbc 2242 #define DMA_CCR_TEIE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2243 #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2244 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
AnnaBridge 171:3a7713b1edbc 2245 #define DMA_CCR_DIR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2246 #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2247 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
AnnaBridge 171:3a7713b1edbc 2248 #define DMA_CCR_CIRC_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2249 #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2250 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
AnnaBridge 171:3a7713b1edbc 2251 #define DMA_CCR_PINC_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2252 #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2253 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
AnnaBridge 171:3a7713b1edbc 2254 #define DMA_CCR_MINC_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2255 #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2256 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
AnnaBridge 171:3a7713b1edbc 2257
AnnaBridge 171:3a7713b1edbc 2258 #define DMA_CCR_PSIZE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2259 #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 2260 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
AnnaBridge 171:3a7713b1edbc 2261 #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2262 #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2263
AnnaBridge 171:3a7713b1edbc 2264 #define DMA_CCR_MSIZE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2265 #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 2266 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
AnnaBridge 171:3a7713b1edbc 2267 #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2268 #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2269
AnnaBridge 171:3a7713b1edbc 2270 #define DMA_CCR_PL_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2271 #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 2272 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */
AnnaBridge 171:3a7713b1edbc 2273 #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2274 #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2275
AnnaBridge 171:3a7713b1edbc 2276 #define DMA_CCR_MEM2MEM_Pos (14U)
AnnaBridge 171:3a7713b1edbc 2277 #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2278 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
AnnaBridge 171:3a7713b1edbc 2279
AnnaBridge 171:3a7713b1edbc 2280 /****************** Bit definition generic for DMA_CNDTR register *******************/
AnnaBridge 171:3a7713b1edbc 2281 #define DMA_CNDTR_NDT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2282 #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 2283 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
AnnaBridge 171:3a7713b1edbc 2284
AnnaBridge 171:3a7713b1edbc 2285 /****************** Bit definition for DMA_CNDTR1 register ******************/
AnnaBridge 171:3a7713b1edbc 2286 #define DMA_CNDTR1_NDT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2287 #define DMA_CNDTR1_NDT_Msk (0xFFFFU << DMA_CNDTR1_NDT_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 2288 #define DMA_CNDTR1_NDT DMA_CNDTR1_NDT_Msk /*!< Number of data to Transfer */
AnnaBridge 171:3a7713b1edbc 2289
AnnaBridge 171:3a7713b1edbc 2290 /****************** Bit definition for DMA_CNDTR2 register ******************/
AnnaBridge 171:3a7713b1edbc 2291 #define DMA_CNDTR2_NDT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2292 #define DMA_CNDTR2_NDT_Msk (0xFFFFU << DMA_CNDTR2_NDT_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 2293 #define DMA_CNDTR2_NDT DMA_CNDTR2_NDT_Msk /*!< Number of data to Transfer */
AnnaBridge 171:3a7713b1edbc 2294
AnnaBridge 171:3a7713b1edbc 2295 /****************** Bit definition for DMA_CNDTR3 register ******************/
AnnaBridge 171:3a7713b1edbc 2296 #define DMA_CNDTR3_NDT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2297 #define DMA_CNDTR3_NDT_Msk (0xFFFFU << DMA_CNDTR3_NDT_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 2298 #define DMA_CNDTR3_NDT DMA_CNDTR3_NDT_Msk /*!< Number of data to Transfer */
AnnaBridge 171:3a7713b1edbc 2299
AnnaBridge 171:3a7713b1edbc 2300 /****************** Bit definition for DMA_CNDTR4 register ******************/
AnnaBridge 171:3a7713b1edbc 2301 #define DMA_CNDTR4_NDT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2302 #define DMA_CNDTR4_NDT_Msk (0xFFFFU << DMA_CNDTR4_NDT_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 2303 #define DMA_CNDTR4_NDT DMA_CNDTR4_NDT_Msk /*!< Number of data to Transfer */
AnnaBridge 171:3a7713b1edbc 2304
AnnaBridge 171:3a7713b1edbc 2305 /****************** Bit definition for DMA_CNDTR5 register ******************/
AnnaBridge 171:3a7713b1edbc 2306 #define DMA_CNDTR5_NDT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2307 #define DMA_CNDTR5_NDT_Msk (0xFFFFU << DMA_CNDTR5_NDT_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 2308 #define DMA_CNDTR5_NDT DMA_CNDTR5_NDT_Msk /*!< Number of data to Transfer */
AnnaBridge 171:3a7713b1edbc 2309
AnnaBridge 171:3a7713b1edbc 2310 /****************** Bit definition for DMA_CNDTR6 register ******************/
AnnaBridge 171:3a7713b1edbc 2311 #define DMA_CNDTR6_NDT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2312 #define DMA_CNDTR6_NDT_Msk (0xFFFFU << DMA_CNDTR6_NDT_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 2313 #define DMA_CNDTR6_NDT DMA_CNDTR6_NDT_Msk /*!< Number of data to Transfer */
AnnaBridge 171:3a7713b1edbc 2314
AnnaBridge 171:3a7713b1edbc 2315 /****************** Bit definition for DMA_CNDTR7 register ******************/
AnnaBridge 171:3a7713b1edbc 2316 #define DMA_CNDTR7_NDT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2317 #define DMA_CNDTR7_NDT_Msk (0xFFFFU << DMA_CNDTR7_NDT_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 2318 #define DMA_CNDTR7_NDT DMA_CNDTR7_NDT_Msk /*!< Number of data to Transfer */
AnnaBridge 171:3a7713b1edbc 2319
AnnaBridge 171:3a7713b1edbc 2320 /****************** Bit definition generic for DMA_CPAR register ********************/
AnnaBridge 171:3a7713b1edbc 2321 #define DMA_CPAR_PA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2322 #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 2323 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
AnnaBridge 171:3a7713b1edbc 2324
AnnaBridge 171:3a7713b1edbc 2325 /****************** Bit definition for DMA_CPAR1 register *******************/
AnnaBridge 171:3a7713b1edbc 2326 #define DMA_CPAR1_PA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2327 #define DMA_CPAR1_PA_Msk (0xFFFFFFFFU << DMA_CPAR1_PA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 2328 #define DMA_CPAR1_PA DMA_CPAR1_PA_Msk /*!< Peripheral Address */
AnnaBridge 171:3a7713b1edbc 2329
AnnaBridge 171:3a7713b1edbc 2330 /****************** Bit definition for DMA_CPAR2 register *******************/
AnnaBridge 171:3a7713b1edbc 2331 #define DMA_CPAR2_PA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2332 #define DMA_CPAR2_PA_Msk (0xFFFFFFFFU << DMA_CPAR2_PA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 2333 #define DMA_CPAR2_PA DMA_CPAR2_PA_Msk /*!< Peripheral Address */
AnnaBridge 171:3a7713b1edbc 2334
AnnaBridge 171:3a7713b1edbc 2335 /****************** Bit definition for DMA_CPAR3 register *******************/
AnnaBridge 171:3a7713b1edbc 2336 #define DMA_CPAR3_PA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2337 #define DMA_CPAR3_PA_Msk (0xFFFFFFFFU << DMA_CPAR3_PA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 2338 #define DMA_CPAR3_PA DMA_CPAR3_PA_Msk /*!< Peripheral Address */
AnnaBridge 171:3a7713b1edbc 2339
AnnaBridge 171:3a7713b1edbc 2340
AnnaBridge 171:3a7713b1edbc 2341 /****************** Bit definition for DMA_CPAR4 register *******************/
AnnaBridge 171:3a7713b1edbc 2342 #define DMA_CPAR4_PA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2343 #define DMA_CPAR4_PA_Msk (0xFFFFFFFFU << DMA_CPAR4_PA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 2344 #define DMA_CPAR4_PA DMA_CPAR4_PA_Msk /*!< Peripheral Address */
AnnaBridge 171:3a7713b1edbc 2345
AnnaBridge 171:3a7713b1edbc 2346 /****************** Bit definition for DMA_CPAR5 register *******************/
AnnaBridge 171:3a7713b1edbc 2347 #define DMA_CPAR5_PA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2348 #define DMA_CPAR5_PA_Msk (0xFFFFFFFFU << DMA_CPAR5_PA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 2349 #define DMA_CPAR5_PA DMA_CPAR5_PA_Msk /*!< Peripheral Address */
AnnaBridge 171:3a7713b1edbc 2350
AnnaBridge 171:3a7713b1edbc 2351 /****************** Bit definition for DMA_CPAR6 register *******************/
AnnaBridge 171:3a7713b1edbc 2352 #define DMA_CPAR6_PA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2353 #define DMA_CPAR6_PA_Msk (0xFFFFFFFFU << DMA_CPAR6_PA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 2354 #define DMA_CPAR6_PA DMA_CPAR6_PA_Msk /*!< Peripheral Address */
AnnaBridge 171:3a7713b1edbc 2355
AnnaBridge 171:3a7713b1edbc 2356
AnnaBridge 171:3a7713b1edbc 2357 /****************** Bit definition for DMA_CPAR7 register *******************/
AnnaBridge 171:3a7713b1edbc 2358 #define DMA_CPAR7_PA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2359 #define DMA_CPAR7_PA_Msk (0xFFFFFFFFU << DMA_CPAR7_PA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 2360 #define DMA_CPAR7_PA DMA_CPAR7_PA_Msk /*!< Peripheral Address */
AnnaBridge 171:3a7713b1edbc 2361
AnnaBridge 171:3a7713b1edbc 2362 /****************** Bit definition generic for DMA_CMAR register ********************/
AnnaBridge 171:3a7713b1edbc 2363 #define DMA_CMAR_MA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2364 #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 2365 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
AnnaBridge 171:3a7713b1edbc 2366
AnnaBridge 171:3a7713b1edbc 2367 /****************** Bit definition for DMA_CMAR1 register *******************/
AnnaBridge 171:3a7713b1edbc 2368 #define DMA_CMAR1_MA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2369 #define DMA_CMAR1_MA_Msk (0xFFFFFFFFU << DMA_CMAR1_MA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 2370 #define DMA_CMAR1_MA DMA_CMAR1_MA_Msk /*!< Memory Address */
AnnaBridge 171:3a7713b1edbc 2371
AnnaBridge 171:3a7713b1edbc 2372 /****************** Bit definition for DMA_CMAR2 register *******************/
AnnaBridge 171:3a7713b1edbc 2373 #define DMA_CMAR2_MA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2374 #define DMA_CMAR2_MA_Msk (0xFFFFFFFFU << DMA_CMAR2_MA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 2375 #define DMA_CMAR2_MA DMA_CMAR2_MA_Msk /*!< Memory Address */
AnnaBridge 171:3a7713b1edbc 2376
AnnaBridge 171:3a7713b1edbc 2377 /****************** Bit definition for DMA_CMAR3 register *******************/
AnnaBridge 171:3a7713b1edbc 2378 #define DMA_CMAR3_MA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2379 #define DMA_CMAR3_MA_Msk (0xFFFFFFFFU << DMA_CMAR3_MA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 2380 #define DMA_CMAR3_MA DMA_CMAR3_MA_Msk /*!< Memory Address */
AnnaBridge 171:3a7713b1edbc 2381
AnnaBridge 171:3a7713b1edbc 2382
AnnaBridge 171:3a7713b1edbc 2383 /****************** Bit definition for DMA_CMAR4 register *******************/
AnnaBridge 171:3a7713b1edbc 2384 #define DMA_CMAR4_MA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2385 #define DMA_CMAR4_MA_Msk (0xFFFFFFFFU << DMA_CMAR4_MA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 2386 #define DMA_CMAR4_MA DMA_CMAR4_MA_Msk /*!< Memory Address */
AnnaBridge 171:3a7713b1edbc 2387
AnnaBridge 171:3a7713b1edbc 2388 /****************** Bit definition for DMA_CMAR5 register *******************/
AnnaBridge 171:3a7713b1edbc 2389 #define DMA_CMAR5_MA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2390 #define DMA_CMAR5_MA_Msk (0xFFFFFFFFU << DMA_CMAR5_MA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 2391 #define DMA_CMAR5_MA DMA_CMAR5_MA_Msk /*!< Memory Address */
AnnaBridge 171:3a7713b1edbc 2392
AnnaBridge 171:3a7713b1edbc 2393 /****************** Bit definition for DMA_CMAR6 register *******************/
AnnaBridge 171:3a7713b1edbc 2394 #define DMA_CMAR6_MA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2395 #define DMA_CMAR6_MA_Msk (0xFFFFFFFFU << DMA_CMAR6_MA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 2396 #define DMA_CMAR6_MA DMA_CMAR6_MA_Msk /*!< Memory Address */
AnnaBridge 171:3a7713b1edbc 2397
AnnaBridge 171:3a7713b1edbc 2398 /****************** Bit definition for DMA_CMAR7 register *******************/
AnnaBridge 171:3a7713b1edbc 2399 #define DMA_CMAR7_MA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2400 #define DMA_CMAR7_MA_Msk (0xFFFFFFFFU << DMA_CMAR7_MA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 2401 #define DMA_CMAR7_MA DMA_CMAR7_MA_Msk /*!< Memory Address */
AnnaBridge 171:3a7713b1edbc 2402
AnnaBridge 171:3a7713b1edbc 2403 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 2404 /* */
AnnaBridge 171:3a7713b1edbc 2405 /* External Interrupt/Event Controller (EXTI) */
AnnaBridge 171:3a7713b1edbc 2406 /* */
AnnaBridge 171:3a7713b1edbc 2407 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 2408
AnnaBridge 171:3a7713b1edbc 2409 /******************* Bit definition for EXTI_IMR register *******************/
AnnaBridge 171:3a7713b1edbc 2410 #define EXTI_IMR_MR0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2411 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2412 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
AnnaBridge 171:3a7713b1edbc 2413 #define EXTI_IMR_MR1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2414 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2415 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
AnnaBridge 171:3a7713b1edbc 2416 #define EXTI_IMR_MR2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2417 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2418 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
AnnaBridge 171:3a7713b1edbc 2419 #define EXTI_IMR_MR3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2420 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2421 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
AnnaBridge 171:3a7713b1edbc 2422 #define EXTI_IMR_MR4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2423 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2424 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
AnnaBridge 171:3a7713b1edbc 2425 #define EXTI_IMR_MR5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2426 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2427 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
AnnaBridge 171:3a7713b1edbc 2428 #define EXTI_IMR_MR6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2429 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2430 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
AnnaBridge 171:3a7713b1edbc 2431 #define EXTI_IMR_MR7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2432 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2433 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
AnnaBridge 171:3a7713b1edbc 2434 #define EXTI_IMR_MR8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2435 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2436 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
AnnaBridge 171:3a7713b1edbc 2437 #define EXTI_IMR_MR9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2438 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2439 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
AnnaBridge 171:3a7713b1edbc 2440 #define EXTI_IMR_MR10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2441 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2442 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
AnnaBridge 171:3a7713b1edbc 2443 #define EXTI_IMR_MR11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2444 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2445 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
AnnaBridge 171:3a7713b1edbc 2446 #define EXTI_IMR_MR12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2447 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2448 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
AnnaBridge 171:3a7713b1edbc 2449 #define EXTI_IMR_MR13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 2450 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2451 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
AnnaBridge 171:3a7713b1edbc 2452 #define EXTI_IMR_MR14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 2453 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2454 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
AnnaBridge 171:3a7713b1edbc 2455 #define EXTI_IMR_MR15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2456 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2457 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
AnnaBridge 171:3a7713b1edbc 2458 #define EXTI_IMR_MR16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2459 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2460 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
AnnaBridge 171:3a7713b1edbc 2461 #define EXTI_IMR_MR17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 2462 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2463 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
AnnaBridge 171:3a7713b1edbc 2464 #define EXTI_IMR_MR18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2465 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2466 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
AnnaBridge 171:3a7713b1edbc 2467 #define EXTI_IMR_MR19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 2468 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2469 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
AnnaBridge 171:3a7713b1edbc 2470 #define EXTI_IMR_MR20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 2471 #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2472 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
AnnaBridge 171:3a7713b1edbc 2473 #define EXTI_IMR_MR21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 2474 #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 2475 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
AnnaBridge 171:3a7713b1edbc 2476 #define EXTI_IMR_MR22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 2477 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2478 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
AnnaBridge 171:3a7713b1edbc 2479 #define EXTI_IMR_MR23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 2480 #define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 2481 #define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */
AnnaBridge 171:3a7713b1edbc 2482
AnnaBridge 171:3a7713b1edbc 2483 /* References Defines */
AnnaBridge 171:3a7713b1edbc 2484 #define EXTI_IMR_IM0 EXTI_IMR_MR0
AnnaBridge 171:3a7713b1edbc 2485 #define EXTI_IMR_IM1 EXTI_IMR_MR1
AnnaBridge 171:3a7713b1edbc 2486 #define EXTI_IMR_IM2 EXTI_IMR_MR2
AnnaBridge 171:3a7713b1edbc 2487 #define EXTI_IMR_IM3 EXTI_IMR_MR3
AnnaBridge 171:3a7713b1edbc 2488 #define EXTI_IMR_IM4 EXTI_IMR_MR4
AnnaBridge 171:3a7713b1edbc 2489 #define EXTI_IMR_IM5 EXTI_IMR_MR5
AnnaBridge 171:3a7713b1edbc 2490 #define EXTI_IMR_IM6 EXTI_IMR_MR6
AnnaBridge 171:3a7713b1edbc 2491 #define EXTI_IMR_IM7 EXTI_IMR_MR7
AnnaBridge 171:3a7713b1edbc 2492 #define EXTI_IMR_IM8 EXTI_IMR_MR8
AnnaBridge 171:3a7713b1edbc 2493 #define EXTI_IMR_IM9 EXTI_IMR_MR9
AnnaBridge 171:3a7713b1edbc 2494 #define EXTI_IMR_IM10 EXTI_IMR_MR10
AnnaBridge 171:3a7713b1edbc 2495 #define EXTI_IMR_IM11 EXTI_IMR_MR11
AnnaBridge 171:3a7713b1edbc 2496 #define EXTI_IMR_IM12 EXTI_IMR_MR12
AnnaBridge 171:3a7713b1edbc 2497 #define EXTI_IMR_IM13 EXTI_IMR_MR13
AnnaBridge 171:3a7713b1edbc 2498 #define EXTI_IMR_IM14 EXTI_IMR_MR14
AnnaBridge 171:3a7713b1edbc 2499 #define EXTI_IMR_IM15 EXTI_IMR_MR15
AnnaBridge 171:3a7713b1edbc 2500 #define EXTI_IMR_IM16 EXTI_IMR_MR16
AnnaBridge 171:3a7713b1edbc 2501 #define EXTI_IMR_IM17 EXTI_IMR_MR17
AnnaBridge 171:3a7713b1edbc 2502 #define EXTI_IMR_IM18 EXTI_IMR_MR18
AnnaBridge 171:3a7713b1edbc 2503 #define EXTI_IMR_IM19 EXTI_IMR_MR19
AnnaBridge 171:3a7713b1edbc 2504 #define EXTI_IMR_IM20 EXTI_IMR_MR20
AnnaBridge 171:3a7713b1edbc 2505 #define EXTI_IMR_IM21 EXTI_IMR_MR21
AnnaBridge 171:3a7713b1edbc 2506 #define EXTI_IMR_IM22 EXTI_IMR_MR22
AnnaBridge 171:3a7713b1edbc 2507 /* Category 3, 4 & 5 */
AnnaBridge 171:3a7713b1edbc 2508 #define EXTI_IMR_IM23 EXTI_IMR_MR23
AnnaBridge 171:3a7713b1edbc 2509 #define EXTI_IMR_IM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2510 #define EXTI_IMR_IM_Msk (0xFFFFFFU << EXTI_IMR_IM_Pos) /*!< 0x00FFFFFF */
AnnaBridge 171:3a7713b1edbc 2511 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
AnnaBridge 171:3a7713b1edbc 2512
AnnaBridge 171:3a7713b1edbc 2513 /******************* Bit definition for EXTI_EMR register *******************/
AnnaBridge 171:3a7713b1edbc 2514 #define EXTI_EMR_MR0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2515 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2516 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
AnnaBridge 171:3a7713b1edbc 2517 #define EXTI_EMR_MR1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2518 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2519 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
AnnaBridge 171:3a7713b1edbc 2520 #define EXTI_EMR_MR2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2521 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2522 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
AnnaBridge 171:3a7713b1edbc 2523 #define EXTI_EMR_MR3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2524 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2525 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
AnnaBridge 171:3a7713b1edbc 2526 #define EXTI_EMR_MR4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2527 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2528 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
AnnaBridge 171:3a7713b1edbc 2529 #define EXTI_EMR_MR5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2530 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2531 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
AnnaBridge 171:3a7713b1edbc 2532 #define EXTI_EMR_MR6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2533 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2534 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
AnnaBridge 171:3a7713b1edbc 2535 #define EXTI_EMR_MR7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2536 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2537 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
AnnaBridge 171:3a7713b1edbc 2538 #define EXTI_EMR_MR8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2539 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2540 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
AnnaBridge 171:3a7713b1edbc 2541 #define EXTI_EMR_MR9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2542 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2543 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
AnnaBridge 171:3a7713b1edbc 2544 #define EXTI_EMR_MR10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2545 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2546 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
AnnaBridge 171:3a7713b1edbc 2547 #define EXTI_EMR_MR11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2548 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2549 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
AnnaBridge 171:3a7713b1edbc 2550 #define EXTI_EMR_MR12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2551 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2552 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
AnnaBridge 171:3a7713b1edbc 2553 #define EXTI_EMR_MR13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 2554 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2555 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
AnnaBridge 171:3a7713b1edbc 2556 #define EXTI_EMR_MR14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 2557 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2558 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
AnnaBridge 171:3a7713b1edbc 2559 #define EXTI_EMR_MR15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2560 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2561 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
AnnaBridge 171:3a7713b1edbc 2562 #define EXTI_EMR_MR16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2563 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2564 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
AnnaBridge 171:3a7713b1edbc 2565 #define EXTI_EMR_MR17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 2566 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2567 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
AnnaBridge 171:3a7713b1edbc 2568 #define EXTI_EMR_MR18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2569 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2570 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
AnnaBridge 171:3a7713b1edbc 2571 #define EXTI_EMR_MR19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 2572 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2573 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
AnnaBridge 171:3a7713b1edbc 2574 #define EXTI_EMR_MR20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 2575 #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2576 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
AnnaBridge 171:3a7713b1edbc 2577 #define EXTI_EMR_MR21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 2578 #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 2579 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
AnnaBridge 171:3a7713b1edbc 2580 #define EXTI_EMR_MR22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 2581 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2582 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
AnnaBridge 171:3a7713b1edbc 2583 #define EXTI_EMR_MR23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 2584 #define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 2585 #define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */
AnnaBridge 171:3a7713b1edbc 2586
AnnaBridge 171:3a7713b1edbc 2587 /* References Defines */
AnnaBridge 171:3a7713b1edbc 2588 #define EXTI_EMR_EM0 EXTI_EMR_MR0
AnnaBridge 171:3a7713b1edbc 2589 #define EXTI_EMR_EM1 EXTI_EMR_MR1
AnnaBridge 171:3a7713b1edbc 2590 #define EXTI_EMR_EM2 EXTI_EMR_MR2
AnnaBridge 171:3a7713b1edbc 2591 #define EXTI_EMR_EM3 EXTI_EMR_MR3
AnnaBridge 171:3a7713b1edbc 2592 #define EXTI_EMR_EM4 EXTI_EMR_MR4
AnnaBridge 171:3a7713b1edbc 2593 #define EXTI_EMR_EM5 EXTI_EMR_MR5
AnnaBridge 171:3a7713b1edbc 2594 #define EXTI_EMR_EM6 EXTI_EMR_MR6
AnnaBridge 171:3a7713b1edbc 2595 #define EXTI_EMR_EM7 EXTI_EMR_MR7
AnnaBridge 171:3a7713b1edbc 2596 #define EXTI_EMR_EM8 EXTI_EMR_MR8
AnnaBridge 171:3a7713b1edbc 2597 #define EXTI_EMR_EM9 EXTI_EMR_MR9
AnnaBridge 171:3a7713b1edbc 2598 #define EXTI_EMR_EM10 EXTI_EMR_MR10
AnnaBridge 171:3a7713b1edbc 2599 #define EXTI_EMR_EM11 EXTI_EMR_MR11
AnnaBridge 171:3a7713b1edbc 2600 #define EXTI_EMR_EM12 EXTI_EMR_MR12
AnnaBridge 171:3a7713b1edbc 2601 #define EXTI_EMR_EM13 EXTI_EMR_MR13
AnnaBridge 171:3a7713b1edbc 2602 #define EXTI_EMR_EM14 EXTI_EMR_MR14
AnnaBridge 171:3a7713b1edbc 2603 #define EXTI_EMR_EM15 EXTI_EMR_MR15
AnnaBridge 171:3a7713b1edbc 2604 #define EXTI_EMR_EM16 EXTI_EMR_MR16
AnnaBridge 171:3a7713b1edbc 2605 #define EXTI_EMR_EM17 EXTI_EMR_MR17
AnnaBridge 171:3a7713b1edbc 2606 #define EXTI_EMR_EM18 EXTI_EMR_MR18
AnnaBridge 171:3a7713b1edbc 2607 #define EXTI_EMR_EM19 EXTI_EMR_MR19
AnnaBridge 171:3a7713b1edbc 2608 #define EXTI_EMR_EM20 EXTI_EMR_MR20
AnnaBridge 171:3a7713b1edbc 2609 #define EXTI_EMR_EM21 EXTI_EMR_MR21
AnnaBridge 171:3a7713b1edbc 2610 #define EXTI_EMR_EM22 EXTI_EMR_MR22
AnnaBridge 171:3a7713b1edbc 2611 #define EXTI_EMR_EM23 EXTI_EMR_MR23
AnnaBridge 171:3a7713b1edbc 2612
AnnaBridge 171:3a7713b1edbc 2613 /****************** Bit definition for EXTI_RTSR register *******************/
AnnaBridge 171:3a7713b1edbc 2614 #define EXTI_RTSR_TR0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2615 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2616 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
AnnaBridge 171:3a7713b1edbc 2617 #define EXTI_RTSR_TR1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2618 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2619 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
AnnaBridge 171:3a7713b1edbc 2620 #define EXTI_RTSR_TR2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2621 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2622 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
AnnaBridge 171:3a7713b1edbc 2623 #define EXTI_RTSR_TR3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2624 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2625 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
AnnaBridge 171:3a7713b1edbc 2626 #define EXTI_RTSR_TR4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2627 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2628 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
AnnaBridge 171:3a7713b1edbc 2629 #define EXTI_RTSR_TR5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2630 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2631 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
AnnaBridge 171:3a7713b1edbc 2632 #define EXTI_RTSR_TR6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2633 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2634 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
AnnaBridge 171:3a7713b1edbc 2635 #define EXTI_RTSR_TR7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2636 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2637 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
AnnaBridge 171:3a7713b1edbc 2638 #define EXTI_RTSR_TR8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2639 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2640 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
AnnaBridge 171:3a7713b1edbc 2641 #define EXTI_RTSR_TR9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2642 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2643 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
AnnaBridge 171:3a7713b1edbc 2644 #define EXTI_RTSR_TR10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2645 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2646 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
AnnaBridge 171:3a7713b1edbc 2647 #define EXTI_RTSR_TR11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2648 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2649 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
AnnaBridge 171:3a7713b1edbc 2650 #define EXTI_RTSR_TR12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2651 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2652 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
AnnaBridge 171:3a7713b1edbc 2653 #define EXTI_RTSR_TR13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 2654 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2655 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
AnnaBridge 171:3a7713b1edbc 2656 #define EXTI_RTSR_TR14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 2657 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2658 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
AnnaBridge 171:3a7713b1edbc 2659 #define EXTI_RTSR_TR15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2660 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2661 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
AnnaBridge 171:3a7713b1edbc 2662 #define EXTI_RTSR_TR16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2663 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2664 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
AnnaBridge 171:3a7713b1edbc 2665 #define EXTI_RTSR_TR17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 2666 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2667 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
AnnaBridge 171:3a7713b1edbc 2668 #define EXTI_RTSR_TR18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2669 #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2670 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
AnnaBridge 171:3a7713b1edbc 2671 #define EXTI_RTSR_TR19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 2672 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2673 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
AnnaBridge 171:3a7713b1edbc 2674 #define EXTI_RTSR_TR20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 2675 #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2676 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
AnnaBridge 171:3a7713b1edbc 2677 #define EXTI_RTSR_TR21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 2678 #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 2679 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
AnnaBridge 171:3a7713b1edbc 2680 #define EXTI_RTSR_TR22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 2681 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2682 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
AnnaBridge 171:3a7713b1edbc 2683 #define EXTI_RTSR_TR23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 2684 #define EXTI_RTSR_TR23_Msk (0x1U << EXTI_RTSR_TR23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 2685 #define EXTI_RTSR_TR23 EXTI_RTSR_TR23_Msk /*!< Rising trigger event configuration bit of line 23 */
AnnaBridge 171:3a7713b1edbc 2686
AnnaBridge 171:3a7713b1edbc 2687 /* References Defines */
AnnaBridge 171:3a7713b1edbc 2688 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0
AnnaBridge 171:3a7713b1edbc 2689 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1
AnnaBridge 171:3a7713b1edbc 2690 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2
AnnaBridge 171:3a7713b1edbc 2691 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3
AnnaBridge 171:3a7713b1edbc 2692 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4
AnnaBridge 171:3a7713b1edbc 2693 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5
AnnaBridge 171:3a7713b1edbc 2694 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6
AnnaBridge 171:3a7713b1edbc 2695 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7
AnnaBridge 171:3a7713b1edbc 2696 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8
AnnaBridge 171:3a7713b1edbc 2697 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9
AnnaBridge 171:3a7713b1edbc 2698 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10
AnnaBridge 171:3a7713b1edbc 2699 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11
AnnaBridge 171:3a7713b1edbc 2700 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12
AnnaBridge 171:3a7713b1edbc 2701 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13
AnnaBridge 171:3a7713b1edbc 2702 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14
AnnaBridge 171:3a7713b1edbc 2703 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15
AnnaBridge 171:3a7713b1edbc 2704 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16
AnnaBridge 171:3a7713b1edbc 2705 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17
AnnaBridge 171:3a7713b1edbc 2706 #define EXTI_RTSR_RT18 EXTI_RTSR_TR18
AnnaBridge 171:3a7713b1edbc 2707 #define EXTI_RTSR_RT19 EXTI_RTSR_TR19
AnnaBridge 171:3a7713b1edbc 2708 #define EXTI_RTSR_RT20 EXTI_RTSR_TR20
AnnaBridge 171:3a7713b1edbc 2709 #define EXTI_RTSR_RT21 EXTI_RTSR_TR21
AnnaBridge 171:3a7713b1edbc 2710 #define EXTI_RTSR_RT22 EXTI_RTSR_TR22
AnnaBridge 171:3a7713b1edbc 2711 #define EXTI_RTSR_RT23 EXTI_RTSR_TR23
AnnaBridge 171:3a7713b1edbc 2712
AnnaBridge 171:3a7713b1edbc 2713 /****************** Bit definition for EXTI_FTSR register *******************/
AnnaBridge 171:3a7713b1edbc 2714 #define EXTI_FTSR_TR0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2715 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2716 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
AnnaBridge 171:3a7713b1edbc 2717 #define EXTI_FTSR_TR1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2718 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2719 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
AnnaBridge 171:3a7713b1edbc 2720 #define EXTI_FTSR_TR2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2721 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2722 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
AnnaBridge 171:3a7713b1edbc 2723 #define EXTI_FTSR_TR3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2724 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2725 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
AnnaBridge 171:3a7713b1edbc 2726 #define EXTI_FTSR_TR4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2727 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2728 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
AnnaBridge 171:3a7713b1edbc 2729 #define EXTI_FTSR_TR5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2730 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2731 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
AnnaBridge 171:3a7713b1edbc 2732 #define EXTI_FTSR_TR6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2733 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2734 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
AnnaBridge 171:3a7713b1edbc 2735 #define EXTI_FTSR_TR7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2736 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2737 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
AnnaBridge 171:3a7713b1edbc 2738 #define EXTI_FTSR_TR8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2739 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2740 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
AnnaBridge 171:3a7713b1edbc 2741 #define EXTI_FTSR_TR9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2742 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2743 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
AnnaBridge 171:3a7713b1edbc 2744 #define EXTI_FTSR_TR10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2745 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2746 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
AnnaBridge 171:3a7713b1edbc 2747 #define EXTI_FTSR_TR11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2748 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2749 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
AnnaBridge 171:3a7713b1edbc 2750 #define EXTI_FTSR_TR12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2751 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2752 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
AnnaBridge 171:3a7713b1edbc 2753 #define EXTI_FTSR_TR13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 2754 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2755 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
AnnaBridge 171:3a7713b1edbc 2756 #define EXTI_FTSR_TR14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 2757 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2758 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
AnnaBridge 171:3a7713b1edbc 2759 #define EXTI_FTSR_TR15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2760 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2761 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
AnnaBridge 171:3a7713b1edbc 2762 #define EXTI_FTSR_TR16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2763 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2764 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
AnnaBridge 171:3a7713b1edbc 2765 #define EXTI_FTSR_TR17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 2766 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2767 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
AnnaBridge 171:3a7713b1edbc 2768 #define EXTI_FTSR_TR18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2769 #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2770 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
AnnaBridge 171:3a7713b1edbc 2771 #define EXTI_FTSR_TR19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 2772 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2773 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
AnnaBridge 171:3a7713b1edbc 2774 #define EXTI_FTSR_TR20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 2775 #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2776 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
AnnaBridge 171:3a7713b1edbc 2777 #define EXTI_FTSR_TR21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 2778 #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 2779 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
AnnaBridge 171:3a7713b1edbc 2780 #define EXTI_FTSR_TR22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 2781 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2782 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
AnnaBridge 171:3a7713b1edbc 2783 #define EXTI_FTSR_TR23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 2784 #define EXTI_FTSR_TR23_Msk (0x1U << EXTI_FTSR_TR23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 2785 #define EXTI_FTSR_TR23 EXTI_FTSR_TR23_Msk /*!< Falling trigger event configuration bit of line 23 */
AnnaBridge 171:3a7713b1edbc 2786
AnnaBridge 171:3a7713b1edbc 2787 /* References Defines */
AnnaBridge 171:3a7713b1edbc 2788 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0
AnnaBridge 171:3a7713b1edbc 2789 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1
AnnaBridge 171:3a7713b1edbc 2790 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2
AnnaBridge 171:3a7713b1edbc 2791 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3
AnnaBridge 171:3a7713b1edbc 2792 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4
AnnaBridge 171:3a7713b1edbc 2793 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5
AnnaBridge 171:3a7713b1edbc 2794 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6
AnnaBridge 171:3a7713b1edbc 2795 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7
AnnaBridge 171:3a7713b1edbc 2796 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8
AnnaBridge 171:3a7713b1edbc 2797 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9
AnnaBridge 171:3a7713b1edbc 2798 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10
AnnaBridge 171:3a7713b1edbc 2799 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11
AnnaBridge 171:3a7713b1edbc 2800 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12
AnnaBridge 171:3a7713b1edbc 2801 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13
AnnaBridge 171:3a7713b1edbc 2802 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14
AnnaBridge 171:3a7713b1edbc 2803 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15
AnnaBridge 171:3a7713b1edbc 2804 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16
AnnaBridge 171:3a7713b1edbc 2805 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17
AnnaBridge 171:3a7713b1edbc 2806 #define EXTI_FTSR_FT18 EXTI_FTSR_TR18
AnnaBridge 171:3a7713b1edbc 2807 #define EXTI_FTSR_FT19 EXTI_FTSR_TR19
AnnaBridge 171:3a7713b1edbc 2808 #define EXTI_FTSR_FT20 EXTI_FTSR_TR20
AnnaBridge 171:3a7713b1edbc 2809 #define EXTI_FTSR_FT21 EXTI_FTSR_TR21
AnnaBridge 171:3a7713b1edbc 2810 #define EXTI_FTSR_FT22 EXTI_FTSR_TR22
AnnaBridge 171:3a7713b1edbc 2811 #define EXTI_FTSR_FT23 EXTI_FTSR_TR23
AnnaBridge 171:3a7713b1edbc 2812
AnnaBridge 171:3a7713b1edbc 2813 /****************** Bit definition for EXTI_SWIER register ******************/
AnnaBridge 171:3a7713b1edbc 2814 #define EXTI_SWIER_SWIER0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2815 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2816 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
AnnaBridge 171:3a7713b1edbc 2817 #define EXTI_SWIER_SWIER1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2818 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2819 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
AnnaBridge 171:3a7713b1edbc 2820 #define EXTI_SWIER_SWIER2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2821 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2822 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
AnnaBridge 171:3a7713b1edbc 2823 #define EXTI_SWIER_SWIER3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2824 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2825 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
AnnaBridge 171:3a7713b1edbc 2826 #define EXTI_SWIER_SWIER4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2827 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2828 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
AnnaBridge 171:3a7713b1edbc 2829 #define EXTI_SWIER_SWIER5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2830 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2831 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
AnnaBridge 171:3a7713b1edbc 2832 #define EXTI_SWIER_SWIER6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2833 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2834 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
AnnaBridge 171:3a7713b1edbc 2835 #define EXTI_SWIER_SWIER7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2836 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2837 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
AnnaBridge 171:3a7713b1edbc 2838 #define EXTI_SWIER_SWIER8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2839 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2840 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
AnnaBridge 171:3a7713b1edbc 2841 #define EXTI_SWIER_SWIER9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2842 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2843 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
AnnaBridge 171:3a7713b1edbc 2844 #define EXTI_SWIER_SWIER10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2845 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2846 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
AnnaBridge 171:3a7713b1edbc 2847 #define EXTI_SWIER_SWIER11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2848 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2849 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
AnnaBridge 171:3a7713b1edbc 2850 #define EXTI_SWIER_SWIER12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2851 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2852 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
AnnaBridge 171:3a7713b1edbc 2853 #define EXTI_SWIER_SWIER13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 2854 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2855 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
AnnaBridge 171:3a7713b1edbc 2856 #define EXTI_SWIER_SWIER14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 2857 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2858 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
AnnaBridge 171:3a7713b1edbc 2859 #define EXTI_SWIER_SWIER15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2860 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2861 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
AnnaBridge 171:3a7713b1edbc 2862 #define EXTI_SWIER_SWIER16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2863 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2864 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
AnnaBridge 171:3a7713b1edbc 2865 #define EXTI_SWIER_SWIER17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 2866 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2867 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
AnnaBridge 171:3a7713b1edbc 2868 #define EXTI_SWIER_SWIER18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2869 #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2870 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
AnnaBridge 171:3a7713b1edbc 2871 #define EXTI_SWIER_SWIER19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 2872 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2873 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
AnnaBridge 171:3a7713b1edbc 2874 #define EXTI_SWIER_SWIER20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 2875 #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2876 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
AnnaBridge 171:3a7713b1edbc 2877 #define EXTI_SWIER_SWIER21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 2878 #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 2879 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
AnnaBridge 171:3a7713b1edbc 2880 #define EXTI_SWIER_SWIER22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 2881 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2882 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
AnnaBridge 171:3a7713b1edbc 2883 #define EXTI_SWIER_SWIER23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 2884 #define EXTI_SWIER_SWIER23_Msk (0x1U << EXTI_SWIER_SWIER23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 2885 #define EXTI_SWIER_SWIER23 EXTI_SWIER_SWIER23_Msk /*!< Software Interrupt on line 23 */
AnnaBridge 171:3a7713b1edbc 2886
AnnaBridge 171:3a7713b1edbc 2887 /* References Defines */
AnnaBridge 171:3a7713b1edbc 2888 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
AnnaBridge 171:3a7713b1edbc 2889 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
AnnaBridge 171:3a7713b1edbc 2890 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
AnnaBridge 171:3a7713b1edbc 2891 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
AnnaBridge 171:3a7713b1edbc 2892 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
AnnaBridge 171:3a7713b1edbc 2893 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
AnnaBridge 171:3a7713b1edbc 2894 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
AnnaBridge 171:3a7713b1edbc 2895 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
AnnaBridge 171:3a7713b1edbc 2896 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
AnnaBridge 171:3a7713b1edbc 2897 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
AnnaBridge 171:3a7713b1edbc 2898 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
AnnaBridge 171:3a7713b1edbc 2899 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
AnnaBridge 171:3a7713b1edbc 2900 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
AnnaBridge 171:3a7713b1edbc 2901 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
AnnaBridge 171:3a7713b1edbc 2902 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
AnnaBridge 171:3a7713b1edbc 2903 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
AnnaBridge 171:3a7713b1edbc 2904 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
AnnaBridge 171:3a7713b1edbc 2905 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
AnnaBridge 171:3a7713b1edbc 2906 #define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
AnnaBridge 171:3a7713b1edbc 2907 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
AnnaBridge 171:3a7713b1edbc 2908 #define EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
AnnaBridge 171:3a7713b1edbc 2909 #define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
AnnaBridge 171:3a7713b1edbc 2910 #define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
AnnaBridge 171:3a7713b1edbc 2911 #define EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
AnnaBridge 171:3a7713b1edbc 2912
AnnaBridge 171:3a7713b1edbc 2913 /******************* Bit definition for EXTI_PR register ********************/
AnnaBridge 171:3a7713b1edbc 2914 #define EXTI_PR_PR0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2915 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2916 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
AnnaBridge 171:3a7713b1edbc 2917 #define EXTI_PR_PR1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2918 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2919 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
AnnaBridge 171:3a7713b1edbc 2920 #define EXTI_PR_PR2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2921 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2922 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
AnnaBridge 171:3a7713b1edbc 2923 #define EXTI_PR_PR3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2924 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2925 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
AnnaBridge 171:3a7713b1edbc 2926 #define EXTI_PR_PR4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2927 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2928 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
AnnaBridge 171:3a7713b1edbc 2929 #define EXTI_PR_PR5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2930 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2931 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
AnnaBridge 171:3a7713b1edbc 2932 #define EXTI_PR_PR6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2933 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2934 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
AnnaBridge 171:3a7713b1edbc 2935 #define EXTI_PR_PR7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2936 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2937 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
AnnaBridge 171:3a7713b1edbc 2938 #define EXTI_PR_PR8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2939 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2940 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
AnnaBridge 171:3a7713b1edbc 2941 #define EXTI_PR_PR9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2942 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2943 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
AnnaBridge 171:3a7713b1edbc 2944 #define EXTI_PR_PR10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2945 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2946 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
AnnaBridge 171:3a7713b1edbc 2947 #define EXTI_PR_PR11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2948 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2949 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
AnnaBridge 171:3a7713b1edbc 2950 #define EXTI_PR_PR12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2951 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2952 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
AnnaBridge 171:3a7713b1edbc 2953 #define EXTI_PR_PR13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 2954 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2955 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
AnnaBridge 171:3a7713b1edbc 2956 #define EXTI_PR_PR14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 2957 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2958 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
AnnaBridge 171:3a7713b1edbc 2959 #define EXTI_PR_PR15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2960 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2961 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
AnnaBridge 171:3a7713b1edbc 2962 #define EXTI_PR_PR16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2963 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2964 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
AnnaBridge 171:3a7713b1edbc 2965 #define EXTI_PR_PR17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 2966 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2967 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
AnnaBridge 171:3a7713b1edbc 2968 #define EXTI_PR_PR18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2969 #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2970 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
AnnaBridge 171:3a7713b1edbc 2971 #define EXTI_PR_PR19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 2972 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2973 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
AnnaBridge 171:3a7713b1edbc 2974 #define EXTI_PR_PR20_Pos (20U)
AnnaBridge 171:3a7713b1edbc 2975 #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2976 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
AnnaBridge 171:3a7713b1edbc 2977 #define EXTI_PR_PR21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 2978 #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 2979 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
AnnaBridge 171:3a7713b1edbc 2980 #define EXTI_PR_PR22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 2981 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2982 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
AnnaBridge 171:3a7713b1edbc 2983 #define EXTI_PR_PR23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 2984 #define EXTI_PR_PR23_Msk (0x1U << EXTI_PR_PR23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 2985 #define EXTI_PR_PR23 EXTI_PR_PR23_Msk /*!< Pending bit for line 23 */
AnnaBridge 171:3a7713b1edbc 2986
AnnaBridge 171:3a7713b1edbc 2987 /* References Defines */
AnnaBridge 171:3a7713b1edbc 2988 #define EXTI_PR_PIF0 EXTI_PR_PR0
AnnaBridge 171:3a7713b1edbc 2989 #define EXTI_PR_PIF1 EXTI_PR_PR1
AnnaBridge 171:3a7713b1edbc 2990 #define EXTI_PR_PIF2 EXTI_PR_PR2
AnnaBridge 171:3a7713b1edbc 2991 #define EXTI_PR_PIF3 EXTI_PR_PR3
AnnaBridge 171:3a7713b1edbc 2992 #define EXTI_PR_PIF4 EXTI_PR_PR4
AnnaBridge 171:3a7713b1edbc 2993 #define EXTI_PR_PIF5 EXTI_PR_PR5
AnnaBridge 171:3a7713b1edbc 2994 #define EXTI_PR_PIF6 EXTI_PR_PR6
AnnaBridge 171:3a7713b1edbc 2995 #define EXTI_PR_PIF7 EXTI_PR_PR7
AnnaBridge 171:3a7713b1edbc 2996 #define EXTI_PR_PIF8 EXTI_PR_PR8
AnnaBridge 171:3a7713b1edbc 2997 #define EXTI_PR_PIF9 EXTI_PR_PR9
AnnaBridge 171:3a7713b1edbc 2998 #define EXTI_PR_PIF10 EXTI_PR_PR10
AnnaBridge 171:3a7713b1edbc 2999 #define EXTI_PR_PIF11 EXTI_PR_PR11
AnnaBridge 171:3a7713b1edbc 3000 #define EXTI_PR_PIF12 EXTI_PR_PR12
AnnaBridge 171:3a7713b1edbc 3001 #define EXTI_PR_PIF13 EXTI_PR_PR13
AnnaBridge 171:3a7713b1edbc 3002 #define EXTI_PR_PIF14 EXTI_PR_PR14
AnnaBridge 171:3a7713b1edbc 3003 #define EXTI_PR_PIF15 EXTI_PR_PR15
AnnaBridge 171:3a7713b1edbc 3004 #define EXTI_PR_PIF16 EXTI_PR_PR16
AnnaBridge 171:3a7713b1edbc 3005 #define EXTI_PR_PIF17 EXTI_PR_PR17
AnnaBridge 171:3a7713b1edbc 3006 #define EXTI_PR_PIF18 EXTI_PR_PR18
AnnaBridge 171:3a7713b1edbc 3007 #define EXTI_PR_PIF19 EXTI_PR_PR19
AnnaBridge 171:3a7713b1edbc 3008 #define EXTI_PR_PIF20 EXTI_PR_PR20
AnnaBridge 171:3a7713b1edbc 3009 #define EXTI_PR_PIF21 EXTI_PR_PR21
AnnaBridge 171:3a7713b1edbc 3010 #define EXTI_PR_PIF22 EXTI_PR_PR22
AnnaBridge 171:3a7713b1edbc 3011 #define EXTI_PR_PIF23 EXTI_PR_PR23
AnnaBridge 171:3a7713b1edbc 3012
AnnaBridge 171:3a7713b1edbc 3013 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 3014 /* */
AnnaBridge 171:3a7713b1edbc 3015 /* FLASH, DATA EEPROM and Option Bytes Registers */
AnnaBridge 171:3a7713b1edbc 3016 /* (FLASH, DATA_EEPROM, OB) */
AnnaBridge 171:3a7713b1edbc 3017 /* */
AnnaBridge 171:3a7713b1edbc 3018 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 3019
AnnaBridge 171:3a7713b1edbc 3020 /******************* Bit definition for FLASH_ACR register ******************/
AnnaBridge 171:3a7713b1edbc 3021 #define FLASH_ACR_LATENCY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3022 #define FLASH_ACR_LATENCY_Msk (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3023 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */
AnnaBridge 171:3a7713b1edbc 3024 #define FLASH_ACR_PRFTEN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3025 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3026 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */
AnnaBridge 171:3a7713b1edbc 3027 #define FLASH_ACR_ACC64_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3028 #define FLASH_ACR_ACC64_Msk (0x1U << FLASH_ACR_ACC64_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3029 #define FLASH_ACR_ACC64 FLASH_ACR_ACC64_Msk /*!< Access 64 bits */
AnnaBridge 171:3a7713b1edbc 3030 #define FLASH_ACR_SLEEP_PD_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3031 #define FLASH_ACR_SLEEP_PD_Msk (0x1U << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3032 #define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */
AnnaBridge 171:3a7713b1edbc 3033 #define FLASH_ACR_RUN_PD_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3034 #define FLASH_ACR_RUN_PD_Msk (0x1U << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3035 #define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */
AnnaBridge 171:3a7713b1edbc 3036
AnnaBridge 171:3a7713b1edbc 3037 /******************* Bit definition for FLASH_PECR register ******************/
AnnaBridge 171:3a7713b1edbc 3038 #define FLASH_PECR_PELOCK_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3039 #define FLASH_PECR_PELOCK_Msk (0x1U << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3040 #define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */
AnnaBridge 171:3a7713b1edbc 3041 #define FLASH_PECR_PRGLOCK_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3042 #define FLASH_PECR_PRGLOCK_Msk (0x1U << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3043 #define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */
AnnaBridge 171:3a7713b1edbc 3044 #define FLASH_PECR_OPTLOCK_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3045 #define FLASH_PECR_OPTLOCK_Msk (0x1U << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3046 #define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */
AnnaBridge 171:3a7713b1edbc 3047 #define FLASH_PECR_PROG_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3048 #define FLASH_PECR_PROG_Msk (0x1U << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3049 #define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */
AnnaBridge 171:3a7713b1edbc 3050 #define FLASH_PECR_DATA_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3051 #define FLASH_PECR_DATA_Msk (0x1U << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3052 #define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */
AnnaBridge 171:3a7713b1edbc 3053 #define FLASH_PECR_FTDW_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3054 #define FLASH_PECR_FTDW_Msk (0x1U << FLASH_PECR_FTDW_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3055 #define FLASH_PECR_FTDW FLASH_PECR_FTDW_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */
AnnaBridge 171:3a7713b1edbc 3056 #define FLASH_PECR_ERASE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3057 #define FLASH_PECR_ERASE_Msk (0x1U << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3058 #define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */
AnnaBridge 171:3a7713b1edbc 3059 #define FLASH_PECR_FPRG_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3060 #define FLASH_PECR_FPRG_Msk (0x1U << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3061 #define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */
AnnaBridge 171:3a7713b1edbc 3062 #define FLASH_PECR_EOPIE_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3063 #define FLASH_PECR_EOPIE_Msk (0x1U << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3064 #define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */
AnnaBridge 171:3a7713b1edbc 3065 #define FLASH_PECR_ERRIE_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3066 #define FLASH_PECR_ERRIE_Msk (0x1U << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3067 #define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */
AnnaBridge 171:3a7713b1edbc 3068 #define FLASH_PECR_OBL_LAUNCH_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3069 #define FLASH_PECR_OBL_LAUNCH_Msk (0x1U << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3070 #define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */
AnnaBridge 171:3a7713b1edbc 3071
AnnaBridge 171:3a7713b1edbc 3072 /****************** Bit definition for FLASH_PDKEYR register ******************/
AnnaBridge 171:3a7713b1edbc 3073 #define FLASH_PDKEYR_PDKEYR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3074 #define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFU << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 3075 #define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */
AnnaBridge 171:3a7713b1edbc 3076
AnnaBridge 171:3a7713b1edbc 3077 /****************** Bit definition for FLASH_PEKEYR register ******************/
AnnaBridge 171:3a7713b1edbc 3078 #define FLASH_PEKEYR_PEKEYR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3079 #define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFU << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 3080 #define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */
AnnaBridge 171:3a7713b1edbc 3081
AnnaBridge 171:3a7713b1edbc 3082 /****************** Bit definition for FLASH_PRGKEYR register ******************/
AnnaBridge 171:3a7713b1edbc 3083 #define FLASH_PRGKEYR_PRGKEYR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3084 #define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFU << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 3085 #define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */
AnnaBridge 171:3a7713b1edbc 3086
AnnaBridge 171:3a7713b1edbc 3087 /****************** Bit definition for FLASH_OPTKEYR register ******************/
AnnaBridge 171:3a7713b1edbc 3088 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3089 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 3090 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */
AnnaBridge 171:3a7713b1edbc 3091
AnnaBridge 171:3a7713b1edbc 3092 /****************** Bit definition for FLASH_SR register *******************/
AnnaBridge 171:3a7713b1edbc 3093 #define FLASH_SR_BSY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3094 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3095 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
AnnaBridge 171:3a7713b1edbc 3096 #define FLASH_SR_EOP_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3097 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3098 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/
AnnaBridge 171:3a7713b1edbc 3099 #define FLASH_SR_ENDHV_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3100 #define FLASH_SR_ENDHV_Msk (0x1U << FLASH_SR_ENDHV_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3101 #define FLASH_SR_ENDHV FLASH_SR_ENDHV_Msk /*!< End of high voltage */
AnnaBridge 171:3a7713b1edbc 3102 #define FLASH_SR_READY_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3103 #define FLASH_SR_READY_Msk (0x1U << FLASH_SR_READY_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3104 #define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */
AnnaBridge 171:3a7713b1edbc 3105
AnnaBridge 171:3a7713b1edbc 3106 #define FLASH_SR_WRPERR_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3107 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3108 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protected error */
AnnaBridge 171:3a7713b1edbc 3109 #define FLASH_SR_PGAERR_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3110 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3111 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */
AnnaBridge 171:3a7713b1edbc 3112 #define FLASH_SR_SIZERR_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3113 #define FLASH_SR_SIZERR_Msk (0x1U << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3114 #define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */
AnnaBridge 171:3a7713b1edbc 3115 #define FLASH_SR_OPTVERR_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3116 #define FLASH_SR_OPTVERR_Msk (0x1U << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3117 #define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option validity error */
AnnaBridge 171:3a7713b1edbc 3118 #define FLASH_SR_OPTVERRUSR_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3119 #define FLASH_SR_OPTVERRUSR_Msk (0x1U << FLASH_SR_OPTVERRUSR_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3120 #define FLASH_SR_OPTVERRUSR FLASH_SR_OPTVERRUSR_Msk /*!< Option User validity error */
AnnaBridge 171:3a7713b1edbc 3121 #define FLASH_SR_RDERR_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3122 #define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3123 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */
AnnaBridge 171:3a7713b1edbc 3124
AnnaBridge 171:3a7713b1edbc 3125 /****************** Bit definition for FLASH_OBR register *******************/
AnnaBridge 171:3a7713b1edbc 3126 #define FLASH_OBR_RDPRT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3127 #define FLASH_OBR_RDPRT_Msk (0xFFU << FLASH_OBR_RDPRT_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 3128 #define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read Protection */
AnnaBridge 171:3a7713b1edbc 3129 #define FLASH_OBR_SPRMOD_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3130 #define FLASH_OBR_SPRMOD_Msk (0x1U << FLASH_OBR_SPRMOD_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3131 #define FLASH_OBR_SPRMOD FLASH_OBR_SPRMOD_Msk /*!< Selection of protection mode of WPRi bits */
AnnaBridge 171:3a7713b1edbc 3132 #define FLASH_OBR_BOR_LEV_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3133 #define FLASH_OBR_BOR_LEV_Msk (0xFU << FLASH_OBR_BOR_LEV_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 3134 #define FLASH_OBR_BOR_LEV FLASH_OBR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
AnnaBridge 171:3a7713b1edbc 3135 #define FLASH_OBR_USER_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3136 #define FLASH_OBR_USER_Msk (0x7U << FLASH_OBR_USER_Pos) /*!< 0x00700000 */
AnnaBridge 171:3a7713b1edbc 3137 #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
AnnaBridge 171:3a7713b1edbc 3138 #define FLASH_OBR_IWDG_SW_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3139 #define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3140 #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG_SW */
AnnaBridge 171:3a7713b1edbc 3141 #define FLASH_OBR_nRST_STOP_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3142 #define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3143 #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
AnnaBridge 171:3a7713b1edbc 3144 #define FLASH_OBR_nRST_STDBY_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3145 #define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3146 #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
AnnaBridge 171:3a7713b1edbc 3147
AnnaBridge 171:3a7713b1edbc 3148 /****************** Bit definition for FLASH_WRPR register ******************/
AnnaBridge 171:3a7713b1edbc 3149 #define FLASH_WRPR1_WRP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3150 #define FLASH_WRPR1_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR1_WRP_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 3151 #define FLASH_WRPR1_WRP FLASH_WRPR1_WRP_Msk /*!< Write Protect sectors 0 to 31 */
AnnaBridge 171:3a7713b1edbc 3152 #define FLASH_WRPR2_WRP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3153 #define FLASH_WRPR2_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR2_WRP_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 3154 #define FLASH_WRPR2_WRP FLASH_WRPR2_WRP_Msk /*!< Write Protect sectors 32 to 63 */
AnnaBridge 171:3a7713b1edbc 3155
AnnaBridge 171:3a7713b1edbc 3156 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 3157 /* */
AnnaBridge 171:3a7713b1edbc 3158 /* General Purpose I/O */
AnnaBridge 171:3a7713b1edbc 3159 /* */
AnnaBridge 171:3a7713b1edbc 3160 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 3161 /****************** Bits definition for GPIO_MODER register *****************/
AnnaBridge 171:3a7713b1edbc 3162 #define GPIO_MODER_MODER0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3163 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 3164 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
AnnaBridge 171:3a7713b1edbc 3165 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3166 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3167
AnnaBridge 171:3a7713b1edbc 3168 #define GPIO_MODER_MODER1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3169 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 3170 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
AnnaBridge 171:3a7713b1edbc 3171 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3172 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3173
AnnaBridge 171:3a7713b1edbc 3174 #define GPIO_MODER_MODER2_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3175 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 3176 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
AnnaBridge 171:3a7713b1edbc 3177 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3178 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3179
AnnaBridge 171:3a7713b1edbc 3180 #define GPIO_MODER_MODER3_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3181 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 3182 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
AnnaBridge 171:3a7713b1edbc 3183 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3184 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3185
AnnaBridge 171:3a7713b1edbc 3186 #define GPIO_MODER_MODER4_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3187 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 3188 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
AnnaBridge 171:3a7713b1edbc 3189 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3190 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3191
AnnaBridge 171:3a7713b1edbc 3192 #define GPIO_MODER_MODER5_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3193 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 3194 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
AnnaBridge 171:3a7713b1edbc 3195 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3196 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3197
AnnaBridge 171:3a7713b1edbc 3198 #define GPIO_MODER_MODER6_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3199 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 3200 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
AnnaBridge 171:3a7713b1edbc 3201 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3202 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3203
AnnaBridge 171:3a7713b1edbc 3204 #define GPIO_MODER_MODER7_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3205 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
AnnaBridge 171:3a7713b1edbc 3206 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
AnnaBridge 171:3a7713b1edbc 3207 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3208 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3209
AnnaBridge 171:3a7713b1edbc 3210 #define GPIO_MODER_MODER8_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3211 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 3212 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
AnnaBridge 171:3a7713b1edbc 3213 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3214 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3215
AnnaBridge 171:3a7713b1edbc 3216 #define GPIO_MODER_MODER9_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3217 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
AnnaBridge 171:3a7713b1edbc 3218 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
AnnaBridge 171:3a7713b1edbc 3219 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3220 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3221
AnnaBridge 171:3a7713b1edbc 3222 #define GPIO_MODER_MODER10_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3223 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 3224 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
AnnaBridge 171:3a7713b1edbc 3225 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3226 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3227
AnnaBridge 171:3a7713b1edbc 3228 #define GPIO_MODER_MODER11_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3229 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
AnnaBridge 171:3a7713b1edbc 3230 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
AnnaBridge 171:3a7713b1edbc 3231 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3232 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3233
AnnaBridge 171:3a7713b1edbc 3234 #define GPIO_MODER_MODER12_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3235 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 3236 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
AnnaBridge 171:3a7713b1edbc 3237 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3238 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3239
AnnaBridge 171:3a7713b1edbc 3240 #define GPIO_MODER_MODER13_Pos (26U)
AnnaBridge 171:3a7713b1edbc 3241 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
AnnaBridge 171:3a7713b1edbc 3242 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
AnnaBridge 171:3a7713b1edbc 3243 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3244 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3245
AnnaBridge 171:3a7713b1edbc 3246 #define GPIO_MODER_MODER14_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3247 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 3248 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
AnnaBridge 171:3a7713b1edbc 3249 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3250 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 3251
AnnaBridge 171:3a7713b1edbc 3252 #define GPIO_MODER_MODER15_Pos (30U)
AnnaBridge 171:3a7713b1edbc 3253 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
AnnaBridge 171:3a7713b1edbc 3254 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
AnnaBridge 171:3a7713b1edbc 3255 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 3256 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3257
AnnaBridge 171:3a7713b1edbc 3258 /****************** Bits definition for GPIO_OTYPER register ****************/
AnnaBridge 171:3a7713b1edbc 3259 #define GPIO_OTYPER_OT_0 (0x00000001U)
AnnaBridge 171:3a7713b1edbc 3260 #define GPIO_OTYPER_OT_1 (0x00000002U)
AnnaBridge 171:3a7713b1edbc 3261 #define GPIO_OTYPER_OT_2 (0x00000004U)
AnnaBridge 171:3a7713b1edbc 3262 #define GPIO_OTYPER_OT_3 (0x00000008U)
AnnaBridge 171:3a7713b1edbc 3263 #define GPIO_OTYPER_OT_4 (0x00000010U)
AnnaBridge 171:3a7713b1edbc 3264 #define GPIO_OTYPER_OT_5 (0x00000020U)
AnnaBridge 171:3a7713b1edbc 3265 #define GPIO_OTYPER_OT_6 (0x00000040U)
AnnaBridge 171:3a7713b1edbc 3266 #define GPIO_OTYPER_OT_7 (0x00000080U)
AnnaBridge 171:3a7713b1edbc 3267 #define GPIO_OTYPER_OT_8 (0x00000100U)
AnnaBridge 171:3a7713b1edbc 3268 #define GPIO_OTYPER_OT_9 (0x00000200U)
AnnaBridge 171:3a7713b1edbc 3269 #define GPIO_OTYPER_OT_10 (0x00000400U)
AnnaBridge 171:3a7713b1edbc 3270 #define GPIO_OTYPER_OT_11 (0x00000800U)
AnnaBridge 171:3a7713b1edbc 3271 #define GPIO_OTYPER_OT_12 (0x00001000U)
AnnaBridge 171:3a7713b1edbc 3272 #define GPIO_OTYPER_OT_13 (0x00002000U)
AnnaBridge 171:3a7713b1edbc 3273 #define GPIO_OTYPER_OT_14 (0x00004000U)
AnnaBridge 171:3a7713b1edbc 3274 #define GPIO_OTYPER_OT_15 (0x00008000U)
AnnaBridge 171:3a7713b1edbc 3275
AnnaBridge 171:3a7713b1edbc 3276 /****************** Bits definition for GPIO_OSPEEDR register ***************/
AnnaBridge 171:3a7713b1edbc 3277 #define GPIO_OSPEEDER_OSPEEDR0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3278 #define GPIO_OSPEEDER_OSPEEDR0_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 3279 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDER_OSPEEDR0_Msk
AnnaBridge 171:3a7713b1edbc 3280 #define GPIO_OSPEEDER_OSPEEDR0_0 (0x1U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3281 #define GPIO_OSPEEDER_OSPEEDR0_1 (0x2U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3282
AnnaBridge 171:3a7713b1edbc 3283 #define GPIO_OSPEEDER_OSPEEDR1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3284 #define GPIO_OSPEEDER_OSPEEDR1_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 3285 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDER_OSPEEDR1_Msk
AnnaBridge 171:3a7713b1edbc 3286 #define GPIO_OSPEEDER_OSPEEDR1_0 (0x1U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3287 #define GPIO_OSPEEDER_OSPEEDR1_1 (0x2U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3288
AnnaBridge 171:3a7713b1edbc 3289 #define GPIO_OSPEEDER_OSPEEDR2_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3290 #define GPIO_OSPEEDER_OSPEEDR2_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 3291 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDER_OSPEEDR2_Msk
AnnaBridge 171:3a7713b1edbc 3292 #define GPIO_OSPEEDER_OSPEEDR2_0 (0x1U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3293 #define GPIO_OSPEEDER_OSPEEDR2_1 (0x2U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3294
AnnaBridge 171:3a7713b1edbc 3295 #define GPIO_OSPEEDER_OSPEEDR3_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3296 #define GPIO_OSPEEDER_OSPEEDR3_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 3297 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDER_OSPEEDR3_Msk
AnnaBridge 171:3a7713b1edbc 3298 #define GPIO_OSPEEDER_OSPEEDR3_0 (0x1U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3299 #define GPIO_OSPEEDER_OSPEEDR3_1 (0x2U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3300
AnnaBridge 171:3a7713b1edbc 3301 #define GPIO_OSPEEDER_OSPEEDR4_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3302 #define GPIO_OSPEEDER_OSPEEDR4_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 3303 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDER_OSPEEDR4_Msk
AnnaBridge 171:3a7713b1edbc 3304 #define GPIO_OSPEEDER_OSPEEDR4_0 (0x1U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3305 #define GPIO_OSPEEDER_OSPEEDR4_1 (0x2U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3306
AnnaBridge 171:3a7713b1edbc 3307 #define GPIO_OSPEEDER_OSPEEDR5_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3308 #define GPIO_OSPEEDER_OSPEEDR5_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 3309 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDER_OSPEEDR5_Msk
AnnaBridge 171:3a7713b1edbc 3310 #define GPIO_OSPEEDER_OSPEEDR5_0 (0x1U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3311 #define GPIO_OSPEEDER_OSPEEDR5_1 (0x2U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3312
AnnaBridge 171:3a7713b1edbc 3313 #define GPIO_OSPEEDER_OSPEEDR6_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3314 #define GPIO_OSPEEDER_OSPEEDR6_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 3315 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDER_OSPEEDR6_Msk
AnnaBridge 171:3a7713b1edbc 3316 #define GPIO_OSPEEDER_OSPEEDR6_0 (0x1U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3317 #define GPIO_OSPEEDER_OSPEEDR6_1 (0x2U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3318
AnnaBridge 171:3a7713b1edbc 3319 #define GPIO_OSPEEDER_OSPEEDR7_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3320 #define GPIO_OSPEEDER_OSPEEDR7_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
AnnaBridge 171:3a7713b1edbc 3321 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDER_OSPEEDR7_Msk
AnnaBridge 171:3a7713b1edbc 3322 #define GPIO_OSPEEDER_OSPEEDR7_0 (0x1U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3323 #define GPIO_OSPEEDER_OSPEEDR7_1 (0x2U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3324
AnnaBridge 171:3a7713b1edbc 3325 #define GPIO_OSPEEDER_OSPEEDR8_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3326 #define GPIO_OSPEEDER_OSPEEDR8_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 3327 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDER_OSPEEDR8_Msk
AnnaBridge 171:3a7713b1edbc 3328 #define GPIO_OSPEEDER_OSPEEDR8_0 (0x1U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3329 #define GPIO_OSPEEDER_OSPEEDR8_1 (0x2U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3330
AnnaBridge 171:3a7713b1edbc 3331 #define GPIO_OSPEEDER_OSPEEDR9_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3332 #define GPIO_OSPEEDER_OSPEEDR9_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
AnnaBridge 171:3a7713b1edbc 3333 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDER_OSPEEDR9_Msk
AnnaBridge 171:3a7713b1edbc 3334 #define GPIO_OSPEEDER_OSPEEDR9_0 (0x1U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3335 #define GPIO_OSPEEDER_OSPEEDR9_1 (0x2U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3336
AnnaBridge 171:3a7713b1edbc 3337 #define GPIO_OSPEEDER_OSPEEDR10_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3338 #define GPIO_OSPEEDER_OSPEEDR10_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 3339 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDER_OSPEEDR10_Msk
AnnaBridge 171:3a7713b1edbc 3340 #define GPIO_OSPEEDER_OSPEEDR10_0 (0x1U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3341 #define GPIO_OSPEEDER_OSPEEDR10_1 (0x2U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3342
AnnaBridge 171:3a7713b1edbc 3343 #define GPIO_OSPEEDER_OSPEEDR11_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3344 #define GPIO_OSPEEDER_OSPEEDR11_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
AnnaBridge 171:3a7713b1edbc 3345 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDER_OSPEEDR11_Msk
AnnaBridge 171:3a7713b1edbc 3346 #define GPIO_OSPEEDER_OSPEEDR11_0 (0x1U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3347 #define GPIO_OSPEEDER_OSPEEDR11_1 (0x2U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3348
AnnaBridge 171:3a7713b1edbc 3349 #define GPIO_OSPEEDER_OSPEEDR12_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3350 #define GPIO_OSPEEDER_OSPEEDR12_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 3351 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDER_OSPEEDR12_Msk
AnnaBridge 171:3a7713b1edbc 3352 #define GPIO_OSPEEDER_OSPEEDR12_0 (0x1U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3353 #define GPIO_OSPEEDER_OSPEEDR12_1 (0x2U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3354
AnnaBridge 171:3a7713b1edbc 3355 #define GPIO_OSPEEDER_OSPEEDR13_Pos (26U)
AnnaBridge 171:3a7713b1edbc 3356 #define GPIO_OSPEEDER_OSPEEDR13_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
AnnaBridge 171:3a7713b1edbc 3357 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDER_OSPEEDR13_Msk
AnnaBridge 171:3a7713b1edbc 3358 #define GPIO_OSPEEDER_OSPEEDR13_0 (0x1U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3359 #define GPIO_OSPEEDER_OSPEEDR13_1 (0x2U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3360
AnnaBridge 171:3a7713b1edbc 3361 #define GPIO_OSPEEDER_OSPEEDR14_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3362 #define GPIO_OSPEEDER_OSPEEDR14_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 3363 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDER_OSPEEDR14_Msk
AnnaBridge 171:3a7713b1edbc 3364 #define GPIO_OSPEEDER_OSPEEDR14_0 (0x1U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3365 #define GPIO_OSPEEDER_OSPEEDR14_1 (0x2U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 3366
AnnaBridge 171:3a7713b1edbc 3367 #define GPIO_OSPEEDER_OSPEEDR15_Pos (30U)
AnnaBridge 171:3a7713b1edbc 3368 #define GPIO_OSPEEDER_OSPEEDR15_Msk (0x3U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
AnnaBridge 171:3a7713b1edbc 3369 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDER_OSPEEDR15_Msk
AnnaBridge 171:3a7713b1edbc 3370 #define GPIO_OSPEEDER_OSPEEDR15_0 (0x1U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 3371 #define GPIO_OSPEEDER_OSPEEDR15_1 (0x2U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3372
AnnaBridge 171:3a7713b1edbc 3373 /****************** Bits definition for GPIO_PUPDR register *****************/
AnnaBridge 171:3a7713b1edbc 3374 #define GPIO_PUPDR_PUPDR0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3375 #define GPIO_PUPDR_PUPDR0_Msk (0x3U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 3376 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk
AnnaBridge 171:3a7713b1edbc 3377 #define GPIO_PUPDR_PUPDR0_0 (0x1U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3378 #define GPIO_PUPDR_PUPDR0_1 (0x2U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3379
AnnaBridge 171:3a7713b1edbc 3380 #define GPIO_PUPDR_PUPDR1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3381 #define GPIO_PUPDR_PUPDR1_Msk (0x3U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 3382 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk
AnnaBridge 171:3a7713b1edbc 3383 #define GPIO_PUPDR_PUPDR1_0 (0x1U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3384 #define GPIO_PUPDR_PUPDR1_1 (0x2U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3385
AnnaBridge 171:3a7713b1edbc 3386 #define GPIO_PUPDR_PUPDR2_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3387 #define GPIO_PUPDR_PUPDR2_Msk (0x3U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 3388 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk
AnnaBridge 171:3a7713b1edbc 3389 #define GPIO_PUPDR_PUPDR2_0 (0x1U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3390 #define GPIO_PUPDR_PUPDR2_1 (0x2U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3391
AnnaBridge 171:3a7713b1edbc 3392 #define GPIO_PUPDR_PUPDR3_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3393 #define GPIO_PUPDR_PUPDR3_Msk (0x3U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 3394 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk
AnnaBridge 171:3a7713b1edbc 3395 #define GPIO_PUPDR_PUPDR3_0 (0x1U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3396 #define GPIO_PUPDR_PUPDR3_1 (0x2U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3397
AnnaBridge 171:3a7713b1edbc 3398 #define GPIO_PUPDR_PUPDR4_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3399 #define GPIO_PUPDR_PUPDR4_Msk (0x3U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 3400 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk
AnnaBridge 171:3a7713b1edbc 3401 #define GPIO_PUPDR_PUPDR4_0 (0x1U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3402 #define GPIO_PUPDR_PUPDR4_1 (0x2U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3403
AnnaBridge 171:3a7713b1edbc 3404 #define GPIO_PUPDR_PUPDR5_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3405 #define GPIO_PUPDR_PUPDR5_Msk (0x3U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 3406 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk
AnnaBridge 171:3a7713b1edbc 3407 #define GPIO_PUPDR_PUPDR5_0 (0x1U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3408 #define GPIO_PUPDR_PUPDR5_1 (0x2U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3409
AnnaBridge 171:3a7713b1edbc 3410 #define GPIO_PUPDR_PUPDR6_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3411 #define GPIO_PUPDR_PUPDR6_Msk (0x3U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 3412 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk
AnnaBridge 171:3a7713b1edbc 3413 #define GPIO_PUPDR_PUPDR6_0 (0x1U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3414 #define GPIO_PUPDR_PUPDR6_1 (0x2U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3415
AnnaBridge 171:3a7713b1edbc 3416 #define GPIO_PUPDR_PUPDR7_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3417 #define GPIO_PUPDR_PUPDR7_Msk (0x3U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */
AnnaBridge 171:3a7713b1edbc 3418 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk
AnnaBridge 171:3a7713b1edbc 3419 #define GPIO_PUPDR_PUPDR7_0 (0x1U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3420 #define GPIO_PUPDR_PUPDR7_1 (0x2U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3421
AnnaBridge 171:3a7713b1edbc 3422 #define GPIO_PUPDR_PUPDR8_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3423 #define GPIO_PUPDR_PUPDR8_Msk (0x3U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 3424 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk
AnnaBridge 171:3a7713b1edbc 3425 #define GPIO_PUPDR_PUPDR8_0 (0x1U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3426 #define GPIO_PUPDR_PUPDR8_1 (0x2U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3427
AnnaBridge 171:3a7713b1edbc 3428 #define GPIO_PUPDR_PUPDR9_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3429 #define GPIO_PUPDR_PUPDR9_Msk (0x3U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */
AnnaBridge 171:3a7713b1edbc 3430 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk
AnnaBridge 171:3a7713b1edbc 3431 #define GPIO_PUPDR_PUPDR9_0 (0x1U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3432 #define GPIO_PUPDR_PUPDR9_1 (0x2U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3433
AnnaBridge 171:3a7713b1edbc 3434 #define GPIO_PUPDR_PUPDR10_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3435 #define GPIO_PUPDR_PUPDR10_Msk (0x3U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 3436 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk
AnnaBridge 171:3a7713b1edbc 3437 #define GPIO_PUPDR_PUPDR10_0 (0x1U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3438 #define GPIO_PUPDR_PUPDR10_1 (0x2U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3439
AnnaBridge 171:3a7713b1edbc 3440 #define GPIO_PUPDR_PUPDR11_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3441 #define GPIO_PUPDR_PUPDR11_Msk (0x3U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */
AnnaBridge 171:3a7713b1edbc 3442 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk
AnnaBridge 171:3a7713b1edbc 3443 #define GPIO_PUPDR_PUPDR11_0 (0x1U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3444 #define GPIO_PUPDR_PUPDR11_1 (0x2U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3445
AnnaBridge 171:3a7713b1edbc 3446 #define GPIO_PUPDR_PUPDR12_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3447 #define GPIO_PUPDR_PUPDR12_Msk (0x3U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 3448 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk
AnnaBridge 171:3a7713b1edbc 3449 #define GPIO_PUPDR_PUPDR12_0 (0x1U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3450 #define GPIO_PUPDR_PUPDR12_1 (0x2U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3451
AnnaBridge 171:3a7713b1edbc 3452 #define GPIO_PUPDR_PUPDR13_Pos (26U)
AnnaBridge 171:3a7713b1edbc 3453 #define GPIO_PUPDR_PUPDR13_Msk (0x3U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */
AnnaBridge 171:3a7713b1edbc 3454 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk
AnnaBridge 171:3a7713b1edbc 3455 #define GPIO_PUPDR_PUPDR13_0 (0x1U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3456 #define GPIO_PUPDR_PUPDR13_1 (0x2U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3457
AnnaBridge 171:3a7713b1edbc 3458 #define GPIO_PUPDR_PUPDR14_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3459 #define GPIO_PUPDR_PUPDR14_Msk (0x3U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 3460 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk
AnnaBridge 171:3a7713b1edbc 3461 #define GPIO_PUPDR_PUPDR14_0 (0x1U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3462 #define GPIO_PUPDR_PUPDR14_1 (0x2U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 3463 #define GPIO_PUPDR_PUPDR15_Pos (30U)
AnnaBridge 171:3a7713b1edbc 3464 #define GPIO_PUPDR_PUPDR15_Msk (0x3U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */
AnnaBridge 171:3a7713b1edbc 3465 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk
AnnaBridge 171:3a7713b1edbc 3466 #define GPIO_PUPDR_PUPDR15_0 (0x1U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 3467 #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3468
AnnaBridge 171:3a7713b1edbc 3469 /****************** Bits definition for GPIO_IDR register *******************/
AnnaBridge 171:3a7713b1edbc 3470 #define GPIO_IDR_IDR_0 (0x00000001U)
AnnaBridge 171:3a7713b1edbc 3471 #define GPIO_IDR_IDR_1 (0x00000002U)
AnnaBridge 171:3a7713b1edbc 3472 #define GPIO_IDR_IDR_2 (0x00000004U)
AnnaBridge 171:3a7713b1edbc 3473 #define GPIO_IDR_IDR_3 (0x00000008U)
AnnaBridge 171:3a7713b1edbc 3474 #define GPIO_IDR_IDR_4 (0x00000010U)
AnnaBridge 171:3a7713b1edbc 3475 #define GPIO_IDR_IDR_5 (0x00000020U)
AnnaBridge 171:3a7713b1edbc 3476 #define GPIO_IDR_IDR_6 (0x00000040U)
AnnaBridge 171:3a7713b1edbc 3477 #define GPIO_IDR_IDR_7 (0x00000080U)
AnnaBridge 171:3a7713b1edbc 3478 #define GPIO_IDR_IDR_8 (0x00000100U)
AnnaBridge 171:3a7713b1edbc 3479 #define GPIO_IDR_IDR_9 (0x00000200U)
AnnaBridge 171:3a7713b1edbc 3480 #define GPIO_IDR_IDR_10 (0x00000400U)
AnnaBridge 171:3a7713b1edbc 3481 #define GPIO_IDR_IDR_11 (0x00000800U)
AnnaBridge 171:3a7713b1edbc 3482 #define GPIO_IDR_IDR_12 (0x00001000U)
AnnaBridge 171:3a7713b1edbc 3483 #define GPIO_IDR_IDR_13 (0x00002000U)
AnnaBridge 171:3a7713b1edbc 3484 #define GPIO_IDR_IDR_14 (0x00004000U)
AnnaBridge 171:3a7713b1edbc 3485 #define GPIO_IDR_IDR_15 (0x00008000U)
AnnaBridge 171:3a7713b1edbc 3486
AnnaBridge 171:3a7713b1edbc 3487 /****************** Bits definition for GPIO_ODR register *******************/
AnnaBridge 171:3a7713b1edbc 3488 #define GPIO_ODR_ODR_0 (0x00000001U)
AnnaBridge 171:3a7713b1edbc 3489 #define GPIO_ODR_ODR_1 (0x00000002U)
AnnaBridge 171:3a7713b1edbc 3490 #define GPIO_ODR_ODR_2 (0x00000004U)
AnnaBridge 171:3a7713b1edbc 3491 #define GPIO_ODR_ODR_3 (0x00000008U)
AnnaBridge 171:3a7713b1edbc 3492 #define GPIO_ODR_ODR_4 (0x00000010U)
AnnaBridge 171:3a7713b1edbc 3493 #define GPIO_ODR_ODR_5 (0x00000020U)
AnnaBridge 171:3a7713b1edbc 3494 #define GPIO_ODR_ODR_6 (0x00000040U)
AnnaBridge 171:3a7713b1edbc 3495 #define GPIO_ODR_ODR_7 (0x00000080U)
AnnaBridge 171:3a7713b1edbc 3496 #define GPIO_ODR_ODR_8 (0x00000100U)
AnnaBridge 171:3a7713b1edbc 3497 #define GPIO_ODR_ODR_9 (0x00000200U)
AnnaBridge 171:3a7713b1edbc 3498 #define GPIO_ODR_ODR_10 (0x00000400U)
AnnaBridge 171:3a7713b1edbc 3499 #define GPIO_ODR_ODR_11 (0x00000800U)
AnnaBridge 171:3a7713b1edbc 3500 #define GPIO_ODR_ODR_12 (0x00001000U)
AnnaBridge 171:3a7713b1edbc 3501 #define GPIO_ODR_ODR_13 (0x00002000U)
AnnaBridge 171:3a7713b1edbc 3502 #define GPIO_ODR_ODR_14 (0x00004000U)
AnnaBridge 171:3a7713b1edbc 3503 #define GPIO_ODR_ODR_15 (0x00008000U)
AnnaBridge 171:3a7713b1edbc 3504
AnnaBridge 171:3a7713b1edbc 3505 /****************** Bits definition for GPIO_BSRR register ******************/
AnnaBridge 171:3a7713b1edbc 3506 #define GPIO_BSRR_BS_0 (0x00000001U)
AnnaBridge 171:3a7713b1edbc 3507 #define GPIO_BSRR_BS_1 (0x00000002U)
AnnaBridge 171:3a7713b1edbc 3508 #define GPIO_BSRR_BS_2 (0x00000004U)
AnnaBridge 171:3a7713b1edbc 3509 #define GPIO_BSRR_BS_3 (0x00000008U)
AnnaBridge 171:3a7713b1edbc 3510 #define GPIO_BSRR_BS_4 (0x00000010U)
AnnaBridge 171:3a7713b1edbc 3511 #define GPIO_BSRR_BS_5 (0x00000020U)
AnnaBridge 171:3a7713b1edbc 3512 #define GPIO_BSRR_BS_6 (0x00000040U)
AnnaBridge 171:3a7713b1edbc 3513 #define GPIO_BSRR_BS_7 (0x00000080U)
AnnaBridge 171:3a7713b1edbc 3514 #define GPIO_BSRR_BS_8 (0x00000100U)
AnnaBridge 171:3a7713b1edbc 3515 #define GPIO_BSRR_BS_9 (0x00000200U)
AnnaBridge 171:3a7713b1edbc 3516 #define GPIO_BSRR_BS_10 (0x00000400U)
AnnaBridge 171:3a7713b1edbc 3517 #define GPIO_BSRR_BS_11 (0x00000800U)
AnnaBridge 171:3a7713b1edbc 3518 #define GPIO_BSRR_BS_12 (0x00001000U)
AnnaBridge 171:3a7713b1edbc 3519 #define GPIO_BSRR_BS_13 (0x00002000U)
AnnaBridge 171:3a7713b1edbc 3520 #define GPIO_BSRR_BS_14 (0x00004000U)
AnnaBridge 171:3a7713b1edbc 3521 #define GPIO_BSRR_BS_15 (0x00008000U)
AnnaBridge 171:3a7713b1edbc 3522 #define GPIO_BSRR_BR_0 (0x00010000U)
AnnaBridge 171:3a7713b1edbc 3523 #define GPIO_BSRR_BR_1 (0x00020000U)
AnnaBridge 171:3a7713b1edbc 3524 #define GPIO_BSRR_BR_2 (0x00040000U)
AnnaBridge 171:3a7713b1edbc 3525 #define GPIO_BSRR_BR_3 (0x00080000U)
AnnaBridge 171:3a7713b1edbc 3526 #define GPIO_BSRR_BR_4 (0x00100000U)
AnnaBridge 171:3a7713b1edbc 3527 #define GPIO_BSRR_BR_5 (0x00200000U)
AnnaBridge 171:3a7713b1edbc 3528 #define GPIO_BSRR_BR_6 (0x00400000U)
AnnaBridge 171:3a7713b1edbc 3529 #define GPIO_BSRR_BR_7 (0x00800000U)
AnnaBridge 171:3a7713b1edbc 3530 #define GPIO_BSRR_BR_8 (0x01000000U)
AnnaBridge 171:3a7713b1edbc 3531 #define GPIO_BSRR_BR_9 (0x02000000U)
AnnaBridge 171:3a7713b1edbc 3532 #define GPIO_BSRR_BR_10 (0x04000000U)
AnnaBridge 171:3a7713b1edbc 3533 #define GPIO_BSRR_BR_11 (0x08000000U)
AnnaBridge 171:3a7713b1edbc 3534 #define GPIO_BSRR_BR_12 (0x10000000U)
AnnaBridge 171:3a7713b1edbc 3535 #define GPIO_BSRR_BR_13 (0x20000000U)
AnnaBridge 171:3a7713b1edbc 3536 #define GPIO_BSRR_BR_14 (0x40000000U)
AnnaBridge 171:3a7713b1edbc 3537 #define GPIO_BSRR_BR_15 (0x80000000U)
AnnaBridge 171:3a7713b1edbc 3538
AnnaBridge 171:3a7713b1edbc 3539 /****************** Bit definition for GPIO_LCKR register ********************/
AnnaBridge 171:3a7713b1edbc 3540 #define GPIO_LCKR_LCK0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3541 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3542 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
AnnaBridge 171:3a7713b1edbc 3543 #define GPIO_LCKR_LCK1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3544 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3545 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
AnnaBridge 171:3a7713b1edbc 3546 #define GPIO_LCKR_LCK2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3547 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3548 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
AnnaBridge 171:3a7713b1edbc 3549 #define GPIO_LCKR_LCK3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3550 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3551 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
AnnaBridge 171:3a7713b1edbc 3552 #define GPIO_LCKR_LCK4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3553 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3554 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
AnnaBridge 171:3a7713b1edbc 3555 #define GPIO_LCKR_LCK5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3556 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3557 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
AnnaBridge 171:3a7713b1edbc 3558 #define GPIO_LCKR_LCK6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3559 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3560 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
AnnaBridge 171:3a7713b1edbc 3561 #define GPIO_LCKR_LCK7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3562 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3563 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
AnnaBridge 171:3a7713b1edbc 3564 #define GPIO_LCKR_LCK8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3565 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3566 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
AnnaBridge 171:3a7713b1edbc 3567 #define GPIO_LCKR_LCK9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3568 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3569 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
AnnaBridge 171:3a7713b1edbc 3570 #define GPIO_LCKR_LCK10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3571 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3572 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
AnnaBridge 171:3a7713b1edbc 3573 #define GPIO_LCKR_LCK11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3574 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3575 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
AnnaBridge 171:3a7713b1edbc 3576 #define GPIO_LCKR_LCK12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3577 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3578 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
AnnaBridge 171:3a7713b1edbc 3579 #define GPIO_LCKR_LCK13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3580 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3581 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
AnnaBridge 171:3a7713b1edbc 3582 #define GPIO_LCKR_LCK14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3583 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3584 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
AnnaBridge 171:3a7713b1edbc 3585 #define GPIO_LCKR_LCK15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3586 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3587 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
AnnaBridge 171:3a7713b1edbc 3588 #define GPIO_LCKR_LCKK_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3589 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3590 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
AnnaBridge 171:3a7713b1edbc 3591
AnnaBridge 171:3a7713b1edbc 3592 /****************** Bit definition for GPIO_AFRL register ********************/
AnnaBridge 171:3a7713b1edbc 3593 #define GPIO_AFRL_AFSEL0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3594 #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 3595 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
AnnaBridge 171:3a7713b1edbc 3596 #define GPIO_AFRL_AFSEL1_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3597 #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 3598 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
AnnaBridge 171:3a7713b1edbc 3599 #define GPIO_AFRL_AFSEL2_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3600 #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 3601 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
AnnaBridge 171:3a7713b1edbc 3602 #define GPIO_AFRL_AFSEL3_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3603 #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 3604 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
AnnaBridge 171:3a7713b1edbc 3605 #define GPIO_AFRL_AFSEL4_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3606 #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 3607 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
AnnaBridge 171:3a7713b1edbc 3608 #define GPIO_AFRL_AFSEL5_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3609 #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 3610 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
AnnaBridge 171:3a7713b1edbc 3611 #define GPIO_AFRL_AFSEL6_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3612 #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 3613 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
AnnaBridge 171:3a7713b1edbc 3614 #define GPIO_AFRL_AFSEL7_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3615 #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
AnnaBridge 171:3a7713b1edbc 3616 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
AnnaBridge 171:3a7713b1edbc 3617
AnnaBridge 171:3a7713b1edbc 3618 /****************** Bit definition for GPIO_AFRH register ********************/
AnnaBridge 171:3a7713b1edbc 3619 #define GPIO_AFRH_AFSEL8_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3620 #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 3621 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
AnnaBridge 171:3a7713b1edbc 3622 #define GPIO_AFRH_AFSEL9_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3623 #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 3624 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
AnnaBridge 171:3a7713b1edbc 3625 #define GPIO_AFRH_AFSEL10_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3626 #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 3627 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
AnnaBridge 171:3a7713b1edbc 3628 #define GPIO_AFRH_AFSEL11_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3629 #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 3630 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
AnnaBridge 171:3a7713b1edbc 3631 #define GPIO_AFRH_AFSEL12_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3632 #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 3633 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
AnnaBridge 171:3a7713b1edbc 3634 #define GPIO_AFRH_AFSEL13_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3635 #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 3636 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
AnnaBridge 171:3a7713b1edbc 3637 #define GPIO_AFRH_AFSEL14_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3638 #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 3639 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
AnnaBridge 171:3a7713b1edbc 3640 #define GPIO_AFRH_AFSEL15_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3641 #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
AnnaBridge 171:3a7713b1edbc 3642 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
AnnaBridge 171:3a7713b1edbc 3643
AnnaBridge 171:3a7713b1edbc 3644 /****************** Bit definition for GPIO_BRR register *********************/
AnnaBridge 171:3a7713b1edbc 3645 #define GPIO_BRR_BR_0 (0x00000001U)
AnnaBridge 171:3a7713b1edbc 3646 #define GPIO_BRR_BR_1 (0x00000002U)
AnnaBridge 171:3a7713b1edbc 3647 #define GPIO_BRR_BR_2 (0x00000004U)
AnnaBridge 171:3a7713b1edbc 3648 #define GPIO_BRR_BR_3 (0x00000008U)
AnnaBridge 171:3a7713b1edbc 3649 #define GPIO_BRR_BR_4 (0x00000010U)
AnnaBridge 171:3a7713b1edbc 3650 #define GPIO_BRR_BR_5 (0x00000020U)
AnnaBridge 171:3a7713b1edbc 3651 #define GPIO_BRR_BR_6 (0x00000040U)
AnnaBridge 171:3a7713b1edbc 3652 #define GPIO_BRR_BR_7 (0x00000080U)
AnnaBridge 171:3a7713b1edbc 3653 #define GPIO_BRR_BR_8 (0x00000100U)
AnnaBridge 171:3a7713b1edbc 3654 #define GPIO_BRR_BR_9 (0x00000200U)
AnnaBridge 171:3a7713b1edbc 3655 #define GPIO_BRR_BR_10 (0x00000400U)
AnnaBridge 171:3a7713b1edbc 3656 #define GPIO_BRR_BR_11 (0x00000800U)
AnnaBridge 171:3a7713b1edbc 3657 #define GPIO_BRR_BR_12 (0x00001000U)
AnnaBridge 171:3a7713b1edbc 3658 #define GPIO_BRR_BR_13 (0x00002000U)
AnnaBridge 171:3a7713b1edbc 3659 #define GPIO_BRR_BR_14 (0x00004000U)
AnnaBridge 171:3a7713b1edbc 3660 #define GPIO_BRR_BR_15 (0x00008000U)
AnnaBridge 171:3a7713b1edbc 3661
AnnaBridge 171:3a7713b1edbc 3662 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 3663 /* */
AnnaBridge 171:3a7713b1edbc 3664 /* Inter-integrated Circuit Interface (I2C) */
AnnaBridge 171:3a7713b1edbc 3665 /* */
AnnaBridge 171:3a7713b1edbc 3666 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 3667
AnnaBridge 171:3a7713b1edbc 3668 /******************* Bit definition for I2C_CR1 register ********************/
AnnaBridge 171:3a7713b1edbc 3669 #define I2C_CR1_PE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3670 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3671 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */
AnnaBridge 171:3a7713b1edbc 3672 #define I2C_CR1_SMBUS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3673 #define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3674 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */
AnnaBridge 171:3a7713b1edbc 3675 #define I2C_CR1_SMBTYPE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3676 #define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3677 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */
AnnaBridge 171:3a7713b1edbc 3678 #define I2C_CR1_ENARP_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3679 #define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3680 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */
AnnaBridge 171:3a7713b1edbc 3681 #define I2C_CR1_ENPEC_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3682 #define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3683 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */
AnnaBridge 171:3a7713b1edbc 3684 #define I2C_CR1_ENGC_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3685 #define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3686 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */
AnnaBridge 171:3a7713b1edbc 3687 #define I2C_CR1_NOSTRETCH_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3688 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3689 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */
AnnaBridge 171:3a7713b1edbc 3690 #define I2C_CR1_START_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3691 #define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3692 #define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */
AnnaBridge 171:3a7713b1edbc 3693 #define I2C_CR1_STOP_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3694 #define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3695 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */
AnnaBridge 171:3a7713b1edbc 3696 #define I2C_CR1_ACK_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3697 #define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3698 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */
AnnaBridge 171:3a7713b1edbc 3699 #define I2C_CR1_POS_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3700 #define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3701 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */
AnnaBridge 171:3a7713b1edbc 3702 #define I2C_CR1_PEC_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3703 #define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3704 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */
AnnaBridge 171:3a7713b1edbc 3705 #define I2C_CR1_ALERT_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3706 #define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3707 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */
AnnaBridge 171:3a7713b1edbc 3708 #define I2C_CR1_SWRST_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3709 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3710 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */
AnnaBridge 171:3a7713b1edbc 3711
AnnaBridge 171:3a7713b1edbc 3712 /******************* Bit definition for I2C_CR2 register ********************/
AnnaBridge 171:3a7713b1edbc 3713 #define I2C_CR2_FREQ_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3714 #define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
AnnaBridge 171:3a7713b1edbc 3715 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
AnnaBridge 171:3a7713b1edbc 3716 #define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3717 #define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3718 #define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3719 #define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3720 #define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3721 #define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3722
AnnaBridge 171:3a7713b1edbc 3723 #define I2C_CR2_ITERREN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3724 #define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3725 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 3726 #define I2C_CR2_ITEVTEN_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3727 #define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3728 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 3729 #define I2C_CR2_ITBUFEN_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3730 #define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3731 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 3732 #define I2C_CR2_DMAEN_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3733 #define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3734 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */
AnnaBridge 171:3a7713b1edbc 3735 #define I2C_CR2_LAST_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3736 #define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3737 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
AnnaBridge 171:3a7713b1edbc 3738
AnnaBridge 171:3a7713b1edbc 3739 /******************* Bit definition for I2C_OAR1 register *******************/
AnnaBridge 171:3a7713b1edbc 3740 #define I2C_OAR1_ADD1_7 (0x000000FEU) /*!< Interface Address */
AnnaBridge 171:3a7713b1edbc 3741 #define I2C_OAR1_ADD8_9 (0x00000300U) /*!< Interface Address */
AnnaBridge 171:3a7713b1edbc 3742
AnnaBridge 171:3a7713b1edbc 3743 #define I2C_OAR1_ADD0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3744 #define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3745 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 3746 #define I2C_OAR1_ADD1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3747 #define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3748 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 3749 #define I2C_OAR1_ADD2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3750 #define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3751 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 3752 #define I2C_OAR1_ADD3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3753 #define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3754 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */
AnnaBridge 171:3a7713b1edbc 3755 #define I2C_OAR1_ADD4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3756 #define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3757 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */
AnnaBridge 171:3a7713b1edbc 3758 #define I2C_OAR1_ADD5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3759 #define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3760 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */
AnnaBridge 171:3a7713b1edbc 3761 #define I2C_OAR1_ADD6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3762 #define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3763 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */
AnnaBridge 171:3a7713b1edbc 3764 #define I2C_OAR1_ADD7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3765 #define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3766 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */
AnnaBridge 171:3a7713b1edbc 3767 #define I2C_OAR1_ADD8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3768 #define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3769 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */
AnnaBridge 171:3a7713b1edbc 3770 #define I2C_OAR1_ADD9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3771 #define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3772 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */
AnnaBridge 171:3a7713b1edbc 3773
AnnaBridge 171:3a7713b1edbc 3774 #define I2C_OAR1_ADDMODE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3775 #define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3776 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */
AnnaBridge 171:3a7713b1edbc 3777
AnnaBridge 171:3a7713b1edbc 3778 /******************* Bit definition for I2C_OAR2 register *******************/
AnnaBridge 171:3a7713b1edbc 3779 #define I2C_OAR2_ENDUAL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3780 #define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3781 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */
AnnaBridge 171:3a7713b1edbc 3782 #define I2C_OAR2_ADD2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3783 #define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
AnnaBridge 171:3a7713b1edbc 3784 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
AnnaBridge 171:3a7713b1edbc 3785
AnnaBridge 171:3a7713b1edbc 3786 /******************** Bit definition for I2C_DR register ********************/
AnnaBridge 171:3a7713b1edbc 3787 #define I2C_DR_DR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3788 #define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 3789 #define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */
AnnaBridge 171:3a7713b1edbc 3790
AnnaBridge 171:3a7713b1edbc 3791 /******************* Bit definition for I2C_SR1 register ********************/
AnnaBridge 171:3a7713b1edbc 3792 #define I2C_SR1_SB_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3793 #define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3794 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */
AnnaBridge 171:3a7713b1edbc 3795 #define I2C_SR1_ADDR_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3796 #define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3797 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */
AnnaBridge 171:3a7713b1edbc 3798 #define I2C_SR1_BTF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3799 #define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3800 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */
AnnaBridge 171:3a7713b1edbc 3801 #define I2C_SR1_ADD10_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3802 #define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3803 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */
AnnaBridge 171:3a7713b1edbc 3804 #define I2C_SR1_STOPF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3805 #define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3806 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */
AnnaBridge 171:3a7713b1edbc 3807 #define I2C_SR1_RXNE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3808 #define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3809 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */
AnnaBridge 171:3a7713b1edbc 3810 #define I2C_SR1_TXE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3811 #define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3812 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */
AnnaBridge 171:3a7713b1edbc 3813 #define I2C_SR1_BERR_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3814 #define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3815 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */
AnnaBridge 171:3a7713b1edbc 3816 #define I2C_SR1_ARLO_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3817 #define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3818 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */
AnnaBridge 171:3a7713b1edbc 3819 #define I2C_SR1_AF_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3820 #define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3821 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */
AnnaBridge 171:3a7713b1edbc 3822 #define I2C_SR1_OVR_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3823 #define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3824 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */
AnnaBridge 171:3a7713b1edbc 3825 #define I2C_SR1_PECERR_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3826 #define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3827 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */
AnnaBridge 171:3a7713b1edbc 3828 #define I2C_SR1_TIMEOUT_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3829 #define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3830 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */
AnnaBridge 171:3a7713b1edbc 3831 #define I2C_SR1_SMBALERT_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3832 #define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3833 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */
AnnaBridge 171:3a7713b1edbc 3834
AnnaBridge 171:3a7713b1edbc 3835 /******************* Bit definition for I2C_SR2 register ********************/
AnnaBridge 171:3a7713b1edbc 3836 #define I2C_SR2_MSL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3837 #define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3838 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */
AnnaBridge 171:3a7713b1edbc 3839 #define I2C_SR2_BUSY_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3840 #define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3841 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */
AnnaBridge 171:3a7713b1edbc 3842 #define I2C_SR2_TRA_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3843 #define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3844 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */
AnnaBridge 171:3a7713b1edbc 3845 #define I2C_SR2_GENCALL_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3846 #define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3847 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */
AnnaBridge 171:3a7713b1edbc 3848 #define I2C_SR2_SMBDEFAULT_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3849 #define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3850 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */
AnnaBridge 171:3a7713b1edbc 3851 #define I2C_SR2_SMBHOST_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3852 #define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3853 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */
AnnaBridge 171:3a7713b1edbc 3854 #define I2C_SR2_DUALF_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3855 #define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3856 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */
AnnaBridge 171:3a7713b1edbc 3857 #define I2C_SR2_PEC_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3858 #define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 3859 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */
AnnaBridge 171:3a7713b1edbc 3860
AnnaBridge 171:3a7713b1edbc 3861 /******************* Bit definition for I2C_CCR register ********************/
AnnaBridge 171:3a7713b1edbc 3862 #define I2C_CCR_CCR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3863 #define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 3864 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */
AnnaBridge 171:3a7713b1edbc 3865 #define I2C_CCR_DUTY_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3866 #define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3867 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */
AnnaBridge 171:3a7713b1edbc 3868 #define I2C_CCR_FS_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3869 #define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3870 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */
AnnaBridge 171:3a7713b1edbc 3871
AnnaBridge 171:3a7713b1edbc 3872 /****************** Bit definition for I2C_TRISE register *******************/
AnnaBridge 171:3a7713b1edbc 3873 #define I2C_TRISE_TRISE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3874 #define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
AnnaBridge 171:3a7713b1edbc 3875 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
AnnaBridge 171:3a7713b1edbc 3876
AnnaBridge 171:3a7713b1edbc 3877 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 3878 /* */
AnnaBridge 171:3a7713b1edbc 3879 /* Independent WATCHDOG (IWDG) */
AnnaBridge 171:3a7713b1edbc 3880 /* */
AnnaBridge 171:3a7713b1edbc 3881 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 3882
AnnaBridge 171:3a7713b1edbc 3883 /******************* Bit definition for IWDG_KR register ********************/
AnnaBridge 171:3a7713b1edbc 3884 #define IWDG_KR_KEY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3885 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 3886 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
AnnaBridge 171:3a7713b1edbc 3887
AnnaBridge 171:3a7713b1edbc 3888 /******************* Bit definition for IWDG_PR register ********************/
AnnaBridge 171:3a7713b1edbc 3889 #define IWDG_PR_PR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3890 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 3891 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
AnnaBridge 171:3a7713b1edbc 3892 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3893 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3894 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3895
AnnaBridge 171:3a7713b1edbc 3896 /******************* Bit definition for IWDG_RLR register *******************/
AnnaBridge 171:3a7713b1edbc 3897 #define IWDG_RLR_RL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3898 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 3899 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
AnnaBridge 171:3a7713b1edbc 3900
AnnaBridge 171:3a7713b1edbc 3901 /******************* Bit definition for IWDG_SR register ********************/
AnnaBridge 171:3a7713b1edbc 3902 #define IWDG_SR_PVU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3903 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3904 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
AnnaBridge 171:3a7713b1edbc 3905 #define IWDG_SR_RVU_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3906 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3907 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
AnnaBridge 171:3a7713b1edbc 3908
AnnaBridge 171:3a7713b1edbc 3909 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 3910 /* */
AnnaBridge 171:3a7713b1edbc 3911 /* LCD Controller (LCD) */
AnnaBridge 171:3a7713b1edbc 3912 /* */
AnnaBridge 171:3a7713b1edbc 3913 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 3914
AnnaBridge 171:3a7713b1edbc 3915 /******************* Bit definition for LCD_CR register *********************/
AnnaBridge 171:3a7713b1edbc 3916 #define LCD_CR_LCDEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3917 #define LCD_CR_LCDEN_Msk (0x1U << LCD_CR_LCDEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3918 #define LCD_CR_LCDEN LCD_CR_LCDEN_Msk /*!< LCD Enable Bit */
AnnaBridge 171:3a7713b1edbc 3919 #define LCD_CR_VSEL_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3920 #define LCD_CR_VSEL_Msk (0x1U << LCD_CR_VSEL_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3921 #define LCD_CR_VSEL LCD_CR_VSEL_Msk /*!< Voltage source selector Bit */
AnnaBridge 171:3a7713b1edbc 3922
AnnaBridge 171:3a7713b1edbc 3923 #define LCD_CR_DUTY_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3924 #define LCD_CR_DUTY_Msk (0x7U << LCD_CR_DUTY_Pos) /*!< 0x0000001C */
AnnaBridge 171:3a7713b1edbc 3925 #define LCD_CR_DUTY LCD_CR_DUTY_Msk /*!< DUTY[2:0] bits (Duty selector) */
AnnaBridge 171:3a7713b1edbc 3926 #define LCD_CR_DUTY_0 (0x1U << LCD_CR_DUTY_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3927 #define LCD_CR_DUTY_1 (0x2U << LCD_CR_DUTY_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3928 #define LCD_CR_DUTY_2 (0x4U << LCD_CR_DUTY_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3929
AnnaBridge 171:3a7713b1edbc 3930 #define LCD_CR_BIAS_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3931 #define LCD_CR_BIAS_Msk (0x3U << LCD_CR_BIAS_Pos) /*!< 0x00000060 */
AnnaBridge 171:3a7713b1edbc 3932 #define LCD_CR_BIAS LCD_CR_BIAS_Msk /*!< BIAS[1:0] bits (Bias selector) */
AnnaBridge 171:3a7713b1edbc 3933 #define LCD_CR_BIAS_0 (0x1U << LCD_CR_BIAS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3934 #define LCD_CR_BIAS_1 (0x2U << LCD_CR_BIAS_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3935
AnnaBridge 171:3a7713b1edbc 3936 #define LCD_CR_MUX_SEG_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3937 #define LCD_CR_MUX_SEG_Msk (0x1U << LCD_CR_MUX_SEG_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3938 #define LCD_CR_MUX_SEG LCD_CR_MUX_SEG_Msk /*!< Mux Segment Enable Bit */
AnnaBridge 171:3a7713b1edbc 3939
AnnaBridge 171:3a7713b1edbc 3940 /******************* Bit definition for LCD_FCR register ********************/
AnnaBridge 171:3a7713b1edbc 3941 #define LCD_FCR_HD_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3942 #define LCD_FCR_HD_Msk (0x1U << LCD_FCR_HD_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3943 #define LCD_FCR_HD LCD_FCR_HD_Msk /*!< High Drive Enable Bit */
AnnaBridge 171:3a7713b1edbc 3944 #define LCD_FCR_SOFIE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3945 #define LCD_FCR_SOFIE_Msk (0x1U << LCD_FCR_SOFIE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3946 #define LCD_FCR_SOFIE LCD_FCR_SOFIE_Msk /*!< Start of Frame Interrupt Enable Bit */
AnnaBridge 171:3a7713b1edbc 3947 #define LCD_FCR_UDDIE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3948 #define LCD_FCR_UDDIE_Msk (0x1U << LCD_FCR_UDDIE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3949 #define LCD_FCR_UDDIE LCD_FCR_UDDIE_Msk /*!< Update Display Done Interrupt Enable Bit */
AnnaBridge 171:3a7713b1edbc 3950
AnnaBridge 171:3a7713b1edbc 3951 #define LCD_FCR_PON_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3952 #define LCD_FCR_PON_Msk (0x7U << LCD_FCR_PON_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 3953 #define LCD_FCR_PON LCD_FCR_PON_Msk /*!< PON[2:0] bits (Puls ON Duration) */
AnnaBridge 171:3a7713b1edbc 3954 #define LCD_FCR_PON_0 (0x1U << LCD_FCR_PON_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3955 #define LCD_FCR_PON_1 (0x2U << LCD_FCR_PON_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3956 #define LCD_FCR_PON_2 (0x4U << LCD_FCR_PON_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3957
AnnaBridge 171:3a7713b1edbc 3958 #define LCD_FCR_DEAD_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3959 #define LCD_FCR_DEAD_Msk (0x7U << LCD_FCR_DEAD_Pos) /*!< 0x00000380 */
AnnaBridge 171:3a7713b1edbc 3960 #define LCD_FCR_DEAD LCD_FCR_DEAD_Msk /*!< DEAD[2:0] bits (DEAD Time) */
AnnaBridge 171:3a7713b1edbc 3961 #define LCD_FCR_DEAD_0 (0x1U << LCD_FCR_DEAD_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3962 #define LCD_FCR_DEAD_1 (0x2U << LCD_FCR_DEAD_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3963 #define LCD_FCR_DEAD_2 (0x4U << LCD_FCR_DEAD_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3964
AnnaBridge 171:3a7713b1edbc 3965 #define LCD_FCR_CC_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3966 #define LCD_FCR_CC_Msk (0x7U << LCD_FCR_CC_Pos) /*!< 0x00001C00 */
AnnaBridge 171:3a7713b1edbc 3967 #define LCD_FCR_CC LCD_FCR_CC_Msk /*!< CC[2:0] bits (Contrast Control) */
AnnaBridge 171:3a7713b1edbc 3968 #define LCD_FCR_CC_0 (0x1U << LCD_FCR_CC_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3969 #define LCD_FCR_CC_1 (0x2U << LCD_FCR_CC_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3970 #define LCD_FCR_CC_2 (0x4U << LCD_FCR_CC_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3971
AnnaBridge 171:3a7713b1edbc 3972 #define LCD_FCR_BLINKF_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3973 #define LCD_FCR_BLINKF_Msk (0x7U << LCD_FCR_BLINKF_Pos) /*!< 0x0000E000 */
AnnaBridge 171:3a7713b1edbc 3974 #define LCD_FCR_BLINKF LCD_FCR_BLINKF_Msk /*!< BLINKF[2:0] bits (Blink Frequency) */
AnnaBridge 171:3a7713b1edbc 3975 #define LCD_FCR_BLINKF_0 (0x1U << LCD_FCR_BLINKF_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3976 #define LCD_FCR_BLINKF_1 (0x2U << LCD_FCR_BLINKF_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3977 #define LCD_FCR_BLINKF_2 (0x4U << LCD_FCR_BLINKF_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3978
AnnaBridge 171:3a7713b1edbc 3979 #define LCD_FCR_BLINK_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3980 #define LCD_FCR_BLINK_Msk (0x3U << LCD_FCR_BLINK_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 3981 #define LCD_FCR_BLINK LCD_FCR_BLINK_Msk /*!< BLINK[1:0] bits (Blink Enable) */
AnnaBridge 171:3a7713b1edbc 3982 #define LCD_FCR_BLINK_0 (0x1U << LCD_FCR_BLINK_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3983 #define LCD_FCR_BLINK_1 (0x2U << LCD_FCR_BLINK_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3984
AnnaBridge 171:3a7713b1edbc 3985 #define LCD_FCR_DIV_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3986 #define LCD_FCR_DIV_Msk (0xFU << LCD_FCR_DIV_Pos) /*!< 0x003C0000 */
AnnaBridge 171:3a7713b1edbc 3987 #define LCD_FCR_DIV LCD_FCR_DIV_Msk /*!< DIV[3:0] bits (Divider) */
AnnaBridge 171:3a7713b1edbc 3988 #define LCD_FCR_PS_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3989 #define LCD_FCR_PS_Msk (0xFU << LCD_FCR_PS_Pos) /*!< 0x03C00000 */
AnnaBridge 171:3a7713b1edbc 3990 #define LCD_FCR_PS LCD_FCR_PS_Msk /*!< PS[3:0] bits (Prescaler) */
AnnaBridge 171:3a7713b1edbc 3991
AnnaBridge 171:3a7713b1edbc 3992 /******************* Bit definition for LCD_SR register *********************/
AnnaBridge 171:3a7713b1edbc 3993 #define LCD_SR_ENS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3994 #define LCD_SR_ENS_Msk (0x1U << LCD_SR_ENS_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3995 #define LCD_SR_ENS LCD_SR_ENS_Msk /*!< LCD Enabled Bit */
AnnaBridge 171:3a7713b1edbc 3996 #define LCD_SR_SOF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3997 #define LCD_SR_SOF_Msk (0x1U << LCD_SR_SOF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3998 #define LCD_SR_SOF LCD_SR_SOF_Msk /*!< Start Of Frame Flag Bit */
AnnaBridge 171:3a7713b1edbc 3999 #define LCD_SR_UDR_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4000 #define LCD_SR_UDR_Msk (0x1U << LCD_SR_UDR_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4001 #define LCD_SR_UDR LCD_SR_UDR_Msk /*!< Update Display Request Bit */
AnnaBridge 171:3a7713b1edbc 4002 #define LCD_SR_UDD_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4003 #define LCD_SR_UDD_Msk (0x1U << LCD_SR_UDD_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4004 #define LCD_SR_UDD LCD_SR_UDD_Msk /*!< Update Display Done Flag Bit */
AnnaBridge 171:3a7713b1edbc 4005 #define LCD_SR_RDY_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4006 #define LCD_SR_RDY_Msk (0x1U << LCD_SR_RDY_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4007 #define LCD_SR_RDY LCD_SR_RDY_Msk /*!< Ready Flag Bit */
AnnaBridge 171:3a7713b1edbc 4008 #define LCD_SR_FCRSR_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4009 #define LCD_SR_FCRSR_Msk (0x1U << LCD_SR_FCRSR_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4010 #define LCD_SR_FCRSR LCD_SR_FCRSR_Msk /*!< LCD FCR Register Synchronization Flag Bit */
AnnaBridge 171:3a7713b1edbc 4011
AnnaBridge 171:3a7713b1edbc 4012 /******************* Bit definition for LCD_CLR register ********************/
AnnaBridge 171:3a7713b1edbc 4013 #define LCD_CLR_SOFC_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4014 #define LCD_CLR_SOFC_Msk (0x1U << LCD_CLR_SOFC_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4015 #define LCD_CLR_SOFC LCD_CLR_SOFC_Msk /*!< Start Of Frame Flag Clear Bit */
AnnaBridge 171:3a7713b1edbc 4016 #define LCD_CLR_UDDC_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4017 #define LCD_CLR_UDDC_Msk (0x1U << LCD_CLR_UDDC_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4018 #define LCD_CLR_UDDC LCD_CLR_UDDC_Msk /*!< Update Display Done Flag Clear Bit */
AnnaBridge 171:3a7713b1edbc 4019
AnnaBridge 171:3a7713b1edbc 4020 /******************* Bit definition for LCD_RAM register ********************/
AnnaBridge 171:3a7713b1edbc 4021 #define LCD_RAM_SEGMENT_DATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4022 #define LCD_RAM_SEGMENT_DATA_Msk (0xFFFFFFFFU << LCD_RAM_SEGMENT_DATA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 4023 #define LCD_RAM_SEGMENT_DATA LCD_RAM_SEGMENT_DATA_Msk /*!< Segment Data Bits */
AnnaBridge 171:3a7713b1edbc 4024
AnnaBridge 171:3a7713b1edbc 4025 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 4026 /* */
AnnaBridge 171:3a7713b1edbc 4027 /* Power Control (PWR) */
AnnaBridge 171:3a7713b1edbc 4028 /* */
AnnaBridge 171:3a7713b1edbc 4029 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 4030
AnnaBridge 171:3a7713b1edbc 4031 #define PWR_PVD_SUPPORT /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
AnnaBridge 171:3a7713b1edbc 4032
AnnaBridge 171:3a7713b1edbc 4033 /******************** Bit definition for PWR_CR register ********************/
AnnaBridge 171:3a7713b1edbc 4034 #define PWR_CR_LPSDSR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4035 #define PWR_CR_LPSDSR_Msk (0x1U << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4036 #define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */
AnnaBridge 171:3a7713b1edbc 4037 #define PWR_CR_PDDS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4038 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4039 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
AnnaBridge 171:3a7713b1edbc 4040 #define PWR_CR_CWUF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4041 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4042 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
AnnaBridge 171:3a7713b1edbc 4043 #define PWR_CR_CSBF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4044 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4045 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
AnnaBridge 171:3a7713b1edbc 4046 #define PWR_CR_PVDE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4047 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4048 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
AnnaBridge 171:3a7713b1edbc 4049
AnnaBridge 171:3a7713b1edbc 4050 #define PWR_CR_PLS_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4051 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
AnnaBridge 171:3a7713b1edbc 4052 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
AnnaBridge 171:3a7713b1edbc 4053 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4054 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4055 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4056
AnnaBridge 171:3a7713b1edbc 4057 /*!< PVD level configuration */
AnnaBridge 171:3a7713b1edbc 4058 #define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
AnnaBridge 171:3a7713b1edbc 4059 #define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */
AnnaBridge 171:3a7713b1edbc 4060 #define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */
AnnaBridge 171:3a7713b1edbc 4061 #define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */
AnnaBridge 171:3a7713b1edbc 4062 #define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */
AnnaBridge 171:3a7713b1edbc 4063 #define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */
AnnaBridge 171:3a7713b1edbc 4064 #define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */
AnnaBridge 171:3a7713b1edbc 4065 #define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */
AnnaBridge 171:3a7713b1edbc 4066
AnnaBridge 171:3a7713b1edbc 4067 #define PWR_CR_DBP_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4068 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4069 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
AnnaBridge 171:3a7713b1edbc 4070 #define PWR_CR_ULP_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4071 #define PWR_CR_ULP_Msk (0x1U << PWR_CR_ULP_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4072 #define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */
AnnaBridge 171:3a7713b1edbc 4073 #define PWR_CR_FWU_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4074 #define PWR_CR_FWU_Msk (0x1U << PWR_CR_FWU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4075 #define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */
AnnaBridge 171:3a7713b1edbc 4076
AnnaBridge 171:3a7713b1edbc 4077 #define PWR_CR_VOS_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4078 #define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x00001800 */
AnnaBridge 171:3a7713b1edbc 4079 #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */
AnnaBridge 171:3a7713b1edbc 4080 #define PWR_CR_VOS_0 (0x1U << PWR_CR_VOS_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4081 #define PWR_CR_VOS_1 (0x2U << PWR_CR_VOS_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4082 #define PWR_CR_LPRUN_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4083 #define PWR_CR_LPRUN_Msk (0x1U << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4084 #define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */
AnnaBridge 171:3a7713b1edbc 4085
AnnaBridge 171:3a7713b1edbc 4086 /******************* Bit definition for PWR_CSR register ********************/
AnnaBridge 171:3a7713b1edbc 4087 #define PWR_CSR_WUF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4088 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4089 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
AnnaBridge 171:3a7713b1edbc 4090 #define PWR_CSR_SBF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4091 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4092 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
AnnaBridge 171:3a7713b1edbc 4093 #define PWR_CSR_PVDO_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4094 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4095 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
AnnaBridge 171:3a7713b1edbc 4096 #define PWR_CSR_VREFINTRDYF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4097 #define PWR_CSR_VREFINTRDYF_Msk (0x1U << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4098 #define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */
AnnaBridge 171:3a7713b1edbc 4099 #define PWR_CSR_VOSF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4100 #define PWR_CSR_VOSF_Msk (0x1U << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4101 #define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */
AnnaBridge 171:3a7713b1edbc 4102 #define PWR_CSR_REGLPF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4103 #define PWR_CSR_REGLPF_Msk (0x1U << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4104 #define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */
AnnaBridge 171:3a7713b1edbc 4105
AnnaBridge 171:3a7713b1edbc 4106 #define PWR_CSR_EWUP1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4107 #define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4108 #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
AnnaBridge 171:3a7713b1edbc 4109 #define PWR_CSR_EWUP2_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4110 #define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4111 #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
AnnaBridge 171:3a7713b1edbc 4112 #define PWR_CSR_EWUP3_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4113 #define PWR_CSR_EWUP3_Msk (0x1U << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4114 #define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */
AnnaBridge 171:3a7713b1edbc 4115
AnnaBridge 171:3a7713b1edbc 4116 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 4117 /* */
AnnaBridge 171:3a7713b1edbc 4118 /* Reset and Clock Control (RCC) */
AnnaBridge 171:3a7713b1edbc 4119 /* */
AnnaBridge 171:3a7713b1edbc 4120 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 4121 /*
AnnaBridge 171:3a7713b1edbc 4122 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
AnnaBridge 171:3a7713b1edbc 4123 */
AnnaBridge 171:3a7713b1edbc 4124 #define RCC_LSECSS_SUPPORT /*!< LSE CSS feature support */
AnnaBridge 171:3a7713b1edbc 4125
AnnaBridge 171:3a7713b1edbc 4126 /******************** Bit definition for RCC_CR register ********************/
AnnaBridge 171:3a7713b1edbc 4127 #define RCC_CR_HSION_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4128 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4129 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
AnnaBridge 171:3a7713b1edbc 4130 #define RCC_CR_HSIRDY_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4131 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4132 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
AnnaBridge 171:3a7713b1edbc 4133
AnnaBridge 171:3a7713b1edbc 4134 #define RCC_CR_MSION_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4135 #define RCC_CR_MSION_Msk (0x1U << RCC_CR_MSION_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4136 #define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */
AnnaBridge 171:3a7713b1edbc 4137 #define RCC_CR_MSIRDY_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4138 #define RCC_CR_MSIRDY_Msk (0x1U << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4139 #define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */
AnnaBridge 171:3a7713b1edbc 4140
AnnaBridge 171:3a7713b1edbc 4141 #define RCC_CR_HSEON_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4142 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4143 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
AnnaBridge 171:3a7713b1edbc 4144 #define RCC_CR_HSERDY_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4145 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4146 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
AnnaBridge 171:3a7713b1edbc 4147 #define RCC_CR_HSEBYP_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4148 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4149 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
AnnaBridge 171:3a7713b1edbc 4150
AnnaBridge 171:3a7713b1edbc 4151 #define RCC_CR_PLLON_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4152 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4153 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
AnnaBridge 171:3a7713b1edbc 4154 #define RCC_CR_PLLRDY_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4155 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4156 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
AnnaBridge 171:3a7713b1edbc 4157 #define RCC_CR_CSSON_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4158 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4159 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */
AnnaBridge 171:3a7713b1edbc 4160
AnnaBridge 171:3a7713b1edbc 4161 #define RCC_CR_RTCPRE_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4162 #define RCC_CR_RTCPRE_Msk (0x3U << RCC_CR_RTCPRE_Pos) /*!< 0x60000000 */
AnnaBridge 171:3a7713b1edbc 4163 #define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC/LCD Prescaler */
AnnaBridge 171:3a7713b1edbc 4164 #define RCC_CR_RTCPRE_0 (0x20000000U) /*!< Bit0 */
AnnaBridge 171:3a7713b1edbc 4165 #define RCC_CR_RTCPRE_1 (0x40000000U) /*!< Bit1 */
AnnaBridge 171:3a7713b1edbc 4166
AnnaBridge 171:3a7713b1edbc 4167 /******************** Bit definition for RCC_ICSCR register *****************/
AnnaBridge 171:3a7713b1edbc 4168 #define RCC_ICSCR_HSICAL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4169 #define RCC_ICSCR_HSICAL_Msk (0xFFU << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 4170 #define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
AnnaBridge 171:3a7713b1edbc 4171 #define RCC_ICSCR_HSITRIM_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4172 #define RCC_ICSCR_HSITRIM_Msk (0x1FU << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */
AnnaBridge 171:3a7713b1edbc 4173 #define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
AnnaBridge 171:3a7713b1edbc 4174
AnnaBridge 171:3a7713b1edbc 4175 #define RCC_ICSCR_MSIRANGE_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4176 #define RCC_ICSCR_MSIRANGE_Msk (0x7U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */
AnnaBridge 171:3a7713b1edbc 4177 #define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */
AnnaBridge 171:3a7713b1edbc 4178 #define RCC_ICSCR_MSIRANGE_0 (0x0U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */
AnnaBridge 171:3a7713b1edbc 4179 #define RCC_ICSCR_MSIRANGE_1 (0x1U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4180 #define RCC_ICSCR_MSIRANGE_2 (0x2U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4181 #define RCC_ICSCR_MSIRANGE_3 (0x3U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */
AnnaBridge 171:3a7713b1edbc 4182 #define RCC_ICSCR_MSIRANGE_4 (0x4U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4183 #define RCC_ICSCR_MSIRANGE_5 (0x5U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */
AnnaBridge 171:3a7713b1edbc 4184 #define RCC_ICSCR_MSIRANGE_6 (0x6U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */
AnnaBridge 171:3a7713b1edbc 4185 #define RCC_ICSCR_MSICAL_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4186 #define RCC_ICSCR_MSICAL_Msk (0xFFU << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 4187 #define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */
AnnaBridge 171:3a7713b1edbc 4188 #define RCC_ICSCR_MSITRIM_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4189 #define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 4190 #define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */
AnnaBridge 171:3a7713b1edbc 4191
AnnaBridge 171:3a7713b1edbc 4192 /******************** Bit definition for RCC_CFGR register ******************/
AnnaBridge 171:3a7713b1edbc 4193 #define RCC_CFGR_SW_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4194 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 4195 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
AnnaBridge 171:3a7713b1edbc 4196 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4197 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4198
AnnaBridge 171:3a7713b1edbc 4199 /*!< SW configuration */
AnnaBridge 171:3a7713b1edbc 4200 #define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */
AnnaBridge 171:3a7713b1edbc 4201 #define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */
AnnaBridge 171:3a7713b1edbc 4202 #define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */
AnnaBridge 171:3a7713b1edbc 4203 #define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */
AnnaBridge 171:3a7713b1edbc 4204
AnnaBridge 171:3a7713b1edbc 4205 #define RCC_CFGR_SWS_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4206 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 4207 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
AnnaBridge 171:3a7713b1edbc 4208 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4209 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4210
AnnaBridge 171:3a7713b1edbc 4211 /*!< SWS configuration */
AnnaBridge 171:3a7713b1edbc 4212 #define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */
AnnaBridge 171:3a7713b1edbc 4213 #define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */
AnnaBridge 171:3a7713b1edbc 4214 #define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
AnnaBridge 171:3a7713b1edbc 4215 #define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
AnnaBridge 171:3a7713b1edbc 4216
AnnaBridge 171:3a7713b1edbc 4217 #define RCC_CFGR_HPRE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4218 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 4219 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
AnnaBridge 171:3a7713b1edbc 4220 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4221 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4222 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4223 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4224
AnnaBridge 171:3a7713b1edbc 4225 /*!< HPRE configuration */
AnnaBridge 171:3a7713b1edbc 4226 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
AnnaBridge 171:3a7713b1edbc 4227 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
AnnaBridge 171:3a7713b1edbc 4228 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
AnnaBridge 171:3a7713b1edbc 4229 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
AnnaBridge 171:3a7713b1edbc 4230 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
AnnaBridge 171:3a7713b1edbc 4231 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
AnnaBridge 171:3a7713b1edbc 4232 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
AnnaBridge 171:3a7713b1edbc 4233 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
AnnaBridge 171:3a7713b1edbc 4234 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
AnnaBridge 171:3a7713b1edbc 4235
AnnaBridge 171:3a7713b1edbc 4236 #define RCC_CFGR_PPRE1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4237 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
AnnaBridge 171:3a7713b1edbc 4238 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
AnnaBridge 171:3a7713b1edbc 4239 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4240 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4241 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4242
AnnaBridge 171:3a7713b1edbc 4243 /*!< PPRE1 configuration */
AnnaBridge 171:3a7713b1edbc 4244 #define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
AnnaBridge 171:3a7713b1edbc 4245 #define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
AnnaBridge 171:3a7713b1edbc 4246 #define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
AnnaBridge 171:3a7713b1edbc 4247 #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
AnnaBridge 171:3a7713b1edbc 4248 #define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
AnnaBridge 171:3a7713b1edbc 4249
AnnaBridge 171:3a7713b1edbc 4250 #define RCC_CFGR_PPRE2_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4251 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
AnnaBridge 171:3a7713b1edbc 4252 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
AnnaBridge 171:3a7713b1edbc 4253 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4254 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4255 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4256
AnnaBridge 171:3a7713b1edbc 4257 /*!< PPRE2 configuration */
AnnaBridge 171:3a7713b1edbc 4258 #define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
AnnaBridge 171:3a7713b1edbc 4259 #define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
AnnaBridge 171:3a7713b1edbc 4260 #define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
AnnaBridge 171:3a7713b1edbc 4261 #define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
AnnaBridge 171:3a7713b1edbc 4262 #define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
AnnaBridge 171:3a7713b1edbc 4263
AnnaBridge 171:3a7713b1edbc 4264 /*!< PLL entry clock source*/
AnnaBridge 171:3a7713b1edbc 4265 #define RCC_CFGR_PLLSRC_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4266 #define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4267 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
AnnaBridge 171:3a7713b1edbc 4268
AnnaBridge 171:3a7713b1edbc 4269 #define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */
AnnaBridge 171:3a7713b1edbc 4270 #define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */
AnnaBridge 171:3a7713b1edbc 4271
AnnaBridge 171:3a7713b1edbc 4272
AnnaBridge 171:3a7713b1edbc 4273 /*!< PLLMUL configuration */
AnnaBridge 171:3a7713b1edbc 4274 #define RCC_CFGR_PLLMUL_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4275 #define RCC_CFGR_PLLMUL_Msk (0xFU << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
AnnaBridge 171:3a7713b1edbc 4276 #define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
AnnaBridge 171:3a7713b1edbc 4277 #define RCC_CFGR_PLLMUL_0 (0x1U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4278 #define RCC_CFGR_PLLMUL_1 (0x2U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4279 #define RCC_CFGR_PLLMUL_2 (0x4U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4280 #define RCC_CFGR_PLLMUL_3 (0x8U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4281
AnnaBridge 171:3a7713b1edbc 4282 /*!< PLLMUL configuration */
AnnaBridge 171:3a7713b1edbc 4283 #define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */
AnnaBridge 171:3a7713b1edbc 4284 #define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */
AnnaBridge 171:3a7713b1edbc 4285 #define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */
AnnaBridge 171:3a7713b1edbc 4286 #define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */
AnnaBridge 171:3a7713b1edbc 4287 #define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */
AnnaBridge 171:3a7713b1edbc 4288 #define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */
AnnaBridge 171:3a7713b1edbc 4289 #define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */
AnnaBridge 171:3a7713b1edbc 4290 #define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */
AnnaBridge 171:3a7713b1edbc 4291 #define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */
AnnaBridge 171:3a7713b1edbc 4292
AnnaBridge 171:3a7713b1edbc 4293 /*!< PLLDIV configuration */
AnnaBridge 171:3a7713b1edbc 4294 #define RCC_CFGR_PLLDIV_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4295 #define RCC_CFGR_PLLDIV_Msk (0x3U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */
AnnaBridge 171:3a7713b1edbc 4296 #define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */
AnnaBridge 171:3a7713b1edbc 4297 #define RCC_CFGR_PLLDIV_0 (0x1U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4298 #define RCC_CFGR_PLLDIV_1 (0x2U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4299
AnnaBridge 171:3a7713b1edbc 4300
AnnaBridge 171:3a7713b1edbc 4301 /*!< PLLDIV configuration */
AnnaBridge 171:3a7713b1edbc 4302 #define RCC_CFGR_PLLDIV1 (0x00000000U) /*!< PLL clock output = CKVCO / 1 */
AnnaBridge 171:3a7713b1edbc 4303 #define RCC_CFGR_PLLDIV2_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4304 #define RCC_CFGR_PLLDIV2_Msk (0x1U << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4305 #define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */
AnnaBridge 171:3a7713b1edbc 4306 #define RCC_CFGR_PLLDIV3_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4307 #define RCC_CFGR_PLLDIV3_Msk (0x1U << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4308 #define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */
AnnaBridge 171:3a7713b1edbc 4309 #define RCC_CFGR_PLLDIV4_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4310 #define RCC_CFGR_PLLDIV4_Msk (0x3U << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */
AnnaBridge 171:3a7713b1edbc 4311 #define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */
AnnaBridge 171:3a7713b1edbc 4312
AnnaBridge 171:3a7713b1edbc 4313
AnnaBridge 171:3a7713b1edbc 4314 #define RCC_CFGR_MCOSEL_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4315 #define RCC_CFGR_MCOSEL_Msk (0x7U << RCC_CFGR_MCOSEL_Pos) /*!< 0x07000000 */
AnnaBridge 171:3a7713b1edbc 4316 #define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */
AnnaBridge 171:3a7713b1edbc 4317 #define RCC_CFGR_MCOSEL_0 (0x1U << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4318 #define RCC_CFGR_MCOSEL_1 (0x2U << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4319 #define RCC_CFGR_MCOSEL_2 (0x4U << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4320
AnnaBridge 171:3a7713b1edbc 4321 /*!< MCO configuration */
AnnaBridge 171:3a7713b1edbc 4322 #define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */
AnnaBridge 171:3a7713b1edbc 4323 #define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4324 #define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1U << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4325 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected */
AnnaBridge 171:3a7713b1edbc 4326 #define RCC_CFGR_MCOSEL_HSI_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4327 #define RCC_CFGR_MCOSEL_HSI_Msk (0x1U << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4328 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */
AnnaBridge 171:3a7713b1edbc 4329 #define RCC_CFGR_MCOSEL_MSI_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4330 #define RCC_CFGR_MCOSEL_MSI_Msk (0x3U << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 4331 #define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */
AnnaBridge 171:3a7713b1edbc 4332 #define RCC_CFGR_MCOSEL_HSE_Pos (26U)
AnnaBridge 171:3a7713b1edbc 4333 #define RCC_CFGR_MCOSEL_HSE_Msk (0x1U << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4334 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */
AnnaBridge 171:3a7713b1edbc 4335 #define RCC_CFGR_MCOSEL_PLL_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4336 #define RCC_CFGR_MCOSEL_PLL_Msk (0x5U << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */
AnnaBridge 171:3a7713b1edbc 4337 #define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */
AnnaBridge 171:3a7713b1edbc 4338 #define RCC_CFGR_MCOSEL_LSI_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4339 #define RCC_CFGR_MCOSEL_LSI_Msk (0x3U << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */
AnnaBridge 171:3a7713b1edbc 4340 #define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */
AnnaBridge 171:3a7713b1edbc 4341 #define RCC_CFGR_MCOSEL_LSE_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4342 #define RCC_CFGR_MCOSEL_LSE_Msk (0x7U << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */
AnnaBridge 171:3a7713b1edbc 4343 #define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */
AnnaBridge 171:3a7713b1edbc 4344
AnnaBridge 171:3a7713b1edbc 4345 #define RCC_CFGR_MCOPRE_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4346 #define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
AnnaBridge 171:3a7713b1edbc 4347 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
AnnaBridge 171:3a7713b1edbc 4348 #define RCC_CFGR_MCOPRE_0 (0x1U << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4349 #define RCC_CFGR_MCOPRE_1 (0x2U << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4350 #define RCC_CFGR_MCOPRE_2 (0x4U << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4351
AnnaBridge 171:3a7713b1edbc 4352 /*!< MCO Prescaler configuration */
AnnaBridge 171:3a7713b1edbc 4353 #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
AnnaBridge 171:3a7713b1edbc 4354 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
AnnaBridge 171:3a7713b1edbc 4355 #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
AnnaBridge 171:3a7713b1edbc 4356 #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
AnnaBridge 171:3a7713b1edbc 4357 #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
AnnaBridge 171:3a7713b1edbc 4358
AnnaBridge 171:3a7713b1edbc 4359 /* Legacy aliases */
AnnaBridge 171:3a7713b1edbc 4360 #define RCC_CFGR_MCO_DIV1 RCC_CFGR_MCOPRE_DIV1
AnnaBridge 171:3a7713b1edbc 4361 #define RCC_CFGR_MCO_DIV2 RCC_CFGR_MCOPRE_DIV2
AnnaBridge 171:3a7713b1edbc 4362 #define RCC_CFGR_MCO_DIV4 RCC_CFGR_MCOPRE_DIV4
AnnaBridge 171:3a7713b1edbc 4363 #define RCC_CFGR_MCO_DIV8 RCC_CFGR_MCOPRE_DIV8
AnnaBridge 171:3a7713b1edbc 4364 #define RCC_CFGR_MCO_DIV16 RCC_CFGR_MCOPRE_DIV16
AnnaBridge 171:3a7713b1edbc 4365 #define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK
AnnaBridge 171:3a7713b1edbc 4366 #define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK
AnnaBridge 171:3a7713b1edbc 4367 #define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI
AnnaBridge 171:3a7713b1edbc 4368 #define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI
AnnaBridge 171:3a7713b1edbc 4369 #define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE
AnnaBridge 171:3a7713b1edbc 4370 #define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL
AnnaBridge 171:3a7713b1edbc 4371 #define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI
AnnaBridge 171:3a7713b1edbc 4372 #define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE
AnnaBridge 171:3a7713b1edbc 4373
AnnaBridge 171:3a7713b1edbc 4374 /*!<****************** Bit definition for RCC_CIR register ********************/
AnnaBridge 171:3a7713b1edbc 4375 #define RCC_CIR_LSIRDYF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4376 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4377 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
AnnaBridge 171:3a7713b1edbc 4378 #define RCC_CIR_LSERDYF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4379 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4380 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
AnnaBridge 171:3a7713b1edbc 4381 #define RCC_CIR_HSIRDYF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4382 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4383 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
AnnaBridge 171:3a7713b1edbc 4384 #define RCC_CIR_HSERDYF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4385 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4386 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
AnnaBridge 171:3a7713b1edbc 4387 #define RCC_CIR_PLLRDYF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4388 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4389 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
AnnaBridge 171:3a7713b1edbc 4390 #define RCC_CIR_MSIRDYF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4391 #define RCC_CIR_MSIRDYF_Msk (0x1U << RCC_CIR_MSIRDYF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4392 #define RCC_CIR_MSIRDYF RCC_CIR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */
AnnaBridge 171:3a7713b1edbc 4393 #define RCC_CIR_LSECSSF_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4394 #define RCC_CIR_LSECSSF_Msk (0x1U << RCC_CIR_LSECSSF_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4395 #define RCC_CIR_LSECSSF RCC_CIR_LSECSSF_Msk /*!< LSE CSS Interrupt flag */
AnnaBridge 171:3a7713b1edbc 4396 #define RCC_CIR_CSSF_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4397 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4398 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
AnnaBridge 171:3a7713b1edbc 4399
AnnaBridge 171:3a7713b1edbc 4400 #define RCC_CIR_LSIRDYIE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4401 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4402 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 4403 #define RCC_CIR_LSERDYIE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4404 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4405 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 4406 #define RCC_CIR_HSIRDYIE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4407 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4408 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 4409 #define RCC_CIR_HSERDYIE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4410 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4411 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 4412 #define RCC_CIR_PLLRDYIE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4413 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4414 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 4415 #define RCC_CIR_MSIRDYIE_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4416 #define RCC_CIR_MSIRDYIE_Msk (0x1U << RCC_CIR_MSIRDYIE_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4417 #define RCC_CIR_MSIRDYIE RCC_CIR_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 4418 #define RCC_CIR_LSECSSIE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4419 #define RCC_CIR_LSECSSIE_Msk (0x1U << RCC_CIR_LSECSSIE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4420 #define RCC_CIR_LSECSSIE RCC_CIR_LSECSSIE_Msk /*!< LSE CSS Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 4421
AnnaBridge 171:3a7713b1edbc 4422 #define RCC_CIR_LSIRDYC_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4423 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4424 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
AnnaBridge 171:3a7713b1edbc 4425 #define RCC_CIR_LSERDYC_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4426 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4427 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
AnnaBridge 171:3a7713b1edbc 4428 #define RCC_CIR_HSIRDYC_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4429 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4430 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
AnnaBridge 171:3a7713b1edbc 4431 #define RCC_CIR_HSERDYC_Pos (19U)
AnnaBridge 171:3a7713b1edbc 4432 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4433 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
AnnaBridge 171:3a7713b1edbc 4434 #define RCC_CIR_PLLRDYC_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4435 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4436 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
AnnaBridge 171:3a7713b1edbc 4437 #define RCC_CIR_MSIRDYC_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4438 #define RCC_CIR_MSIRDYC_Msk (0x1U << RCC_CIR_MSIRDYC_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4439 #define RCC_CIR_MSIRDYC RCC_CIR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */
AnnaBridge 171:3a7713b1edbc 4440 #define RCC_CIR_LSECSSC_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4441 #define RCC_CIR_LSECSSC_Msk (0x1U << RCC_CIR_LSECSSC_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4442 #define RCC_CIR_LSECSSC RCC_CIR_LSECSSC_Msk /*!< LSE CSS Interrupt Clear */
AnnaBridge 171:3a7713b1edbc 4443 #define RCC_CIR_CSSC_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4444 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4445 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
AnnaBridge 171:3a7713b1edbc 4446
AnnaBridge 171:3a7713b1edbc 4447 /***************** Bit definition for RCC_AHBRSTR register ******************/
AnnaBridge 171:3a7713b1edbc 4448 #define RCC_AHBRSTR_GPIOARST_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4449 #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4450 #define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIO port A reset */
AnnaBridge 171:3a7713b1edbc 4451 #define RCC_AHBRSTR_GPIOBRST_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4452 #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4453 #define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIO port B reset */
AnnaBridge 171:3a7713b1edbc 4454 #define RCC_AHBRSTR_GPIOCRST_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4455 #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4456 #define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIO port C reset */
AnnaBridge 171:3a7713b1edbc 4457 #define RCC_AHBRSTR_GPIODRST_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4458 #define RCC_AHBRSTR_GPIODRST_Msk (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4459 #define RCC_AHBRSTR_GPIODRST RCC_AHBRSTR_GPIODRST_Msk /*!< GPIO port D reset */
AnnaBridge 171:3a7713b1edbc 4460 #define RCC_AHBRSTR_GPIOERST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4461 #define RCC_AHBRSTR_GPIOERST_Msk (0x1U << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4462 #define RCC_AHBRSTR_GPIOERST RCC_AHBRSTR_GPIOERST_Msk /*!< GPIO port E reset */
AnnaBridge 171:3a7713b1edbc 4463 #define RCC_AHBRSTR_GPIOHRST_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4464 #define RCC_AHBRSTR_GPIOHRST_Msk (0x1U << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4465 #define RCC_AHBRSTR_GPIOHRST RCC_AHBRSTR_GPIOHRST_Msk /*!< GPIO port H reset */
AnnaBridge 171:3a7713b1edbc 4466 #define RCC_AHBRSTR_CRCRST_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4467 #define RCC_AHBRSTR_CRCRST_Msk (0x1U << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4468 #define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */
AnnaBridge 171:3a7713b1edbc 4469 #define RCC_AHBRSTR_FLITFRST_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4470 #define RCC_AHBRSTR_FLITFRST_Msk (0x1U << RCC_AHBRSTR_FLITFRST_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4471 #define RCC_AHBRSTR_FLITFRST RCC_AHBRSTR_FLITFRST_Msk /*!< FLITF reset */
AnnaBridge 171:3a7713b1edbc 4472 #define RCC_AHBRSTR_DMA1RST_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4473 #define RCC_AHBRSTR_DMA1RST_Msk (0x1U << RCC_AHBRSTR_DMA1RST_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4474 #define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMA1RST_Msk /*!< DMA1 reset */
AnnaBridge 171:3a7713b1edbc 4475 #define RCC_AHBRSTR_DMA2RST_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4476 #define RCC_AHBRSTR_DMA2RST_Msk (0x1U << RCC_AHBRSTR_DMA2RST_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4477 #define RCC_AHBRSTR_DMA2RST RCC_AHBRSTR_DMA2RST_Msk /*!< DMA2 reset */
AnnaBridge 171:3a7713b1edbc 4478
AnnaBridge 171:3a7713b1edbc 4479 /***************** Bit definition for RCC_APB2RSTR register *****************/
AnnaBridge 171:3a7713b1edbc 4480 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4481 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4482 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< System Configuration SYSCFG reset */
AnnaBridge 171:3a7713b1edbc 4483 #define RCC_APB2RSTR_TIM9RST_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4484 #define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4485 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk /*!< TIM9 reset */
AnnaBridge 171:3a7713b1edbc 4486 #define RCC_APB2RSTR_TIM10RST_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4487 #define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4488 #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk /*!< TIM10 reset */
AnnaBridge 171:3a7713b1edbc 4489 #define RCC_APB2RSTR_TIM11RST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4490 #define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4491 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk /*!< TIM11 reset */
AnnaBridge 171:3a7713b1edbc 4492 #define RCC_APB2RSTR_ADC1RST_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4493 #define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4494 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC1 reset */
AnnaBridge 171:3a7713b1edbc 4495 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4496 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4497 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */
AnnaBridge 171:3a7713b1edbc 4498 #define RCC_APB2RSTR_USART1RST_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4499 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4500 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
AnnaBridge 171:3a7713b1edbc 4501
AnnaBridge 171:3a7713b1edbc 4502 /***************** Bit definition for RCC_APB1RSTR register *****************/
AnnaBridge 171:3a7713b1edbc 4503 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4504 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4505 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
AnnaBridge 171:3a7713b1edbc 4506 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4507 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4508 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
AnnaBridge 171:3a7713b1edbc 4509 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4510 #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4511 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */
AnnaBridge 171:3a7713b1edbc 4512 #define RCC_APB1RSTR_TIM5RST_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4513 #define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4514 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk /*!< Timer 5 reset */
AnnaBridge 171:3a7713b1edbc 4515 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4516 #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4517 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */
AnnaBridge 171:3a7713b1edbc 4518 #define RCC_APB1RSTR_TIM7RST_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4519 #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4520 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */
AnnaBridge 171:3a7713b1edbc 4521 #define RCC_APB1RSTR_LCDRST_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4522 #define RCC_APB1RSTR_LCDRST_Msk (0x1U << RCC_APB1RSTR_LCDRST_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4523 #define RCC_APB1RSTR_LCDRST RCC_APB1RSTR_LCDRST_Msk /*!< LCD reset */
AnnaBridge 171:3a7713b1edbc 4524 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4525 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4526 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
AnnaBridge 171:3a7713b1edbc 4527 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4528 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4529 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */
AnnaBridge 171:3a7713b1edbc 4530 #define RCC_APB1RSTR_SPI3RST_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4531 #define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4532 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk /*!< SPI 3 reset */
AnnaBridge 171:3a7713b1edbc 4533 #define RCC_APB1RSTR_USART2RST_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4534 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4535 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
AnnaBridge 171:3a7713b1edbc 4536 #define RCC_APB1RSTR_USART3RST_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4537 #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4538 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */
AnnaBridge 171:3a7713b1edbc 4539 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4540 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4541 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
AnnaBridge 171:3a7713b1edbc 4542 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4543 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4544 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
AnnaBridge 171:3a7713b1edbc 4545 #define RCC_APB1RSTR_USBRST_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4546 #define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4547 #define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB reset */
AnnaBridge 171:3a7713b1edbc 4548 #define RCC_APB1RSTR_PWRRST_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4549 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4550 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */
AnnaBridge 171:3a7713b1edbc 4551 #define RCC_APB1RSTR_DACRST_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4552 #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4553 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC interface reset */
AnnaBridge 171:3a7713b1edbc 4554 #define RCC_APB1RSTR_COMPRST_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4555 #define RCC_APB1RSTR_COMPRST_Msk (0x1U << RCC_APB1RSTR_COMPRST_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4556 #define RCC_APB1RSTR_COMPRST RCC_APB1RSTR_COMPRST_Msk /*!< Comparator interface reset */
AnnaBridge 171:3a7713b1edbc 4557
AnnaBridge 171:3a7713b1edbc 4558 /****************** Bit definition for RCC_AHBENR register ******************/
AnnaBridge 171:3a7713b1edbc 4559 #define RCC_AHBENR_GPIOAEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4560 #define RCC_AHBENR_GPIOAEN_Msk (0x1U << RCC_AHBENR_GPIOAEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4561 #define RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk /*!< GPIO port A clock enable */
AnnaBridge 171:3a7713b1edbc 4562 #define RCC_AHBENR_GPIOBEN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4563 #define RCC_AHBENR_GPIOBEN_Msk (0x1U << RCC_AHBENR_GPIOBEN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4564 #define RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk /*!< GPIO port B clock enable */
AnnaBridge 171:3a7713b1edbc 4565 #define RCC_AHBENR_GPIOCEN_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4566 #define RCC_AHBENR_GPIOCEN_Msk (0x1U << RCC_AHBENR_GPIOCEN_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4567 #define RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk /*!< GPIO port C clock enable */
AnnaBridge 171:3a7713b1edbc 4568 #define RCC_AHBENR_GPIODEN_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4569 #define RCC_AHBENR_GPIODEN_Msk (0x1U << RCC_AHBENR_GPIODEN_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4570 #define RCC_AHBENR_GPIODEN RCC_AHBENR_GPIODEN_Msk /*!< GPIO port D clock enable */
AnnaBridge 171:3a7713b1edbc 4571 #define RCC_AHBENR_GPIOEEN_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4572 #define RCC_AHBENR_GPIOEEN_Msk (0x1U << RCC_AHBENR_GPIOEEN_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4573 #define RCC_AHBENR_GPIOEEN RCC_AHBENR_GPIOEEN_Msk /*!< GPIO port E clock enable */
AnnaBridge 171:3a7713b1edbc 4574 #define RCC_AHBENR_GPIOHEN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4575 #define RCC_AHBENR_GPIOHEN_Msk (0x1U << RCC_AHBENR_GPIOHEN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4576 #define RCC_AHBENR_GPIOHEN RCC_AHBENR_GPIOHEN_Msk /*!< GPIO port H clock enable */
AnnaBridge 171:3a7713b1edbc 4577 #define RCC_AHBENR_CRCEN_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4578 #define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4579 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
AnnaBridge 171:3a7713b1edbc 4580 #define RCC_AHBENR_FLITFEN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4581 #define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4582 #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable (has effect only when
AnnaBridge 171:3a7713b1edbc 4583 the Flash memory is in power down mode) */
AnnaBridge 171:3a7713b1edbc 4584 #define RCC_AHBENR_DMA1EN_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4585 #define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4586 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */
AnnaBridge 171:3a7713b1edbc 4587 #define RCC_AHBENR_DMA2EN_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4588 #define RCC_AHBENR_DMA2EN_Msk (0x1U << RCC_AHBENR_DMA2EN_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4589 #define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enable */
AnnaBridge 171:3a7713b1edbc 4590
AnnaBridge 171:3a7713b1edbc 4591 /****************** Bit definition for RCC_APB2ENR register *****************/
AnnaBridge 171:3a7713b1edbc 4592 #define RCC_APB2ENR_SYSCFGEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4593 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4594 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< System Configuration SYSCFG clock enable */
AnnaBridge 171:3a7713b1edbc 4595 #define RCC_APB2ENR_TIM9EN_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4596 #define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4597 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk /*!< TIM9 interface clock enable */
AnnaBridge 171:3a7713b1edbc 4598 #define RCC_APB2ENR_TIM10EN_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4599 #define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4600 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk /*!< TIM10 interface clock enable */
AnnaBridge 171:3a7713b1edbc 4601 #define RCC_APB2ENR_TIM11EN_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4602 #define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4603 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk /*!< TIM11 Timer clock enable */
AnnaBridge 171:3a7713b1edbc 4604 #define RCC_APB2ENR_ADC1EN_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4605 #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4606 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC1 clock enable */
AnnaBridge 171:3a7713b1edbc 4607 #define RCC_APB2ENR_SPI1EN_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4608 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4609 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */
AnnaBridge 171:3a7713b1edbc 4610 #define RCC_APB2ENR_USART1EN_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4611 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4612 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
AnnaBridge 171:3a7713b1edbc 4613
AnnaBridge 171:3a7713b1edbc 4614 /***************** Bit definition for RCC_APB1ENR register ******************/
AnnaBridge 171:3a7713b1edbc 4615 #define RCC_APB1ENR_TIM2EN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4616 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4617 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/
AnnaBridge 171:3a7713b1edbc 4618 #define RCC_APB1ENR_TIM3EN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4619 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4620 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
AnnaBridge 171:3a7713b1edbc 4621 #define RCC_APB1ENR_TIM4EN_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4622 #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4623 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */
AnnaBridge 171:3a7713b1edbc 4624 #define RCC_APB1ENR_TIM5EN_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4625 #define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4626 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /*!< Timer 5 clock enable */
AnnaBridge 171:3a7713b1edbc 4627 #define RCC_APB1ENR_TIM6EN_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4628 #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4629 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */
AnnaBridge 171:3a7713b1edbc 4630 #define RCC_APB1ENR_TIM7EN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4631 #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4632 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */
AnnaBridge 171:3a7713b1edbc 4633 #define RCC_APB1ENR_LCDEN_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4634 #define RCC_APB1ENR_LCDEN_Msk (0x1U << RCC_APB1ENR_LCDEN_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4635 #define RCC_APB1ENR_LCDEN RCC_APB1ENR_LCDEN_Msk /*!< LCD clock enable */
AnnaBridge 171:3a7713b1edbc 4636 #define RCC_APB1ENR_WWDGEN_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4637 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4638 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
AnnaBridge 171:3a7713b1edbc 4639 #define RCC_APB1ENR_SPI2EN_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4640 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4641 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */
AnnaBridge 171:3a7713b1edbc 4642 #define RCC_APB1ENR_SPI3EN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4643 #define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4644 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock enable */
AnnaBridge 171:3a7713b1edbc 4645 #define RCC_APB1ENR_USART2EN_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4646 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4647 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */
AnnaBridge 171:3a7713b1edbc 4648 #define RCC_APB1ENR_USART3EN_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4649 #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4650 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */
AnnaBridge 171:3a7713b1edbc 4651 #define RCC_APB1ENR_I2C1EN_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4652 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4653 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */
AnnaBridge 171:3a7713b1edbc 4654 #define RCC_APB1ENR_I2C2EN_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4655 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4656 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */
AnnaBridge 171:3a7713b1edbc 4657 #define RCC_APB1ENR_USBEN_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4658 #define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4659 #define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB clock enable */
AnnaBridge 171:3a7713b1edbc 4660 #define RCC_APB1ENR_PWREN_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4661 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4662 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */
AnnaBridge 171:3a7713b1edbc 4663 #define RCC_APB1ENR_DACEN_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4664 #define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4665 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC interface clock enable */
AnnaBridge 171:3a7713b1edbc 4666 #define RCC_APB1ENR_COMPEN_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4667 #define RCC_APB1ENR_COMPEN_Msk (0x1U << RCC_APB1ENR_COMPEN_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4668 #define RCC_APB1ENR_COMPEN RCC_APB1ENR_COMPEN_Msk /*!< Comparator interface clock enable */
AnnaBridge 171:3a7713b1edbc 4669
AnnaBridge 171:3a7713b1edbc 4670 /****************** Bit definition for RCC_AHBLPENR register ****************/
AnnaBridge 171:3a7713b1edbc 4671 #define RCC_AHBLPENR_GPIOALPEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4672 #define RCC_AHBLPENR_GPIOALPEN_Msk (0x1U << RCC_AHBLPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4673 #define RCC_AHBLPENR_GPIOALPEN RCC_AHBLPENR_GPIOALPEN_Msk /*!< GPIO port A clock enabled in sleep mode */
AnnaBridge 171:3a7713b1edbc 4674 #define RCC_AHBLPENR_GPIOBLPEN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4675 #define RCC_AHBLPENR_GPIOBLPEN_Msk (0x1U << RCC_AHBLPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4676 #define RCC_AHBLPENR_GPIOBLPEN RCC_AHBLPENR_GPIOBLPEN_Msk /*!< GPIO port B clock enabled in sleep mode */
AnnaBridge 171:3a7713b1edbc 4677 #define RCC_AHBLPENR_GPIOCLPEN_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4678 #define RCC_AHBLPENR_GPIOCLPEN_Msk (0x1U << RCC_AHBLPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4679 #define RCC_AHBLPENR_GPIOCLPEN RCC_AHBLPENR_GPIOCLPEN_Msk /*!< GPIO port C clock enabled in sleep mode */
AnnaBridge 171:3a7713b1edbc 4680 #define RCC_AHBLPENR_GPIODLPEN_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4681 #define RCC_AHBLPENR_GPIODLPEN_Msk (0x1U << RCC_AHBLPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4682 #define RCC_AHBLPENR_GPIODLPEN RCC_AHBLPENR_GPIODLPEN_Msk /*!< GPIO port D clock enabled in sleep mode */
AnnaBridge 171:3a7713b1edbc 4683 #define RCC_AHBLPENR_GPIOELPEN_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4684 #define RCC_AHBLPENR_GPIOELPEN_Msk (0x1U << RCC_AHBLPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4685 #define RCC_AHBLPENR_GPIOELPEN RCC_AHBLPENR_GPIOELPEN_Msk /*!< GPIO port E clock enabled in sleep mode */
AnnaBridge 171:3a7713b1edbc 4686 #define RCC_AHBLPENR_GPIOHLPEN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4687 #define RCC_AHBLPENR_GPIOHLPEN_Msk (0x1U << RCC_AHBLPENR_GPIOHLPEN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4688 #define RCC_AHBLPENR_GPIOHLPEN RCC_AHBLPENR_GPIOHLPEN_Msk /*!< GPIO port H clock enabled in sleep mode */
AnnaBridge 171:3a7713b1edbc 4689 #define RCC_AHBLPENR_CRCLPEN_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4690 #define RCC_AHBLPENR_CRCLPEN_Msk (0x1U << RCC_AHBLPENR_CRCLPEN_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4691 #define RCC_AHBLPENR_CRCLPEN RCC_AHBLPENR_CRCLPEN_Msk /*!< CRC clock enabled in sleep mode */
AnnaBridge 171:3a7713b1edbc 4692 #define RCC_AHBLPENR_FLITFLPEN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4693 #define RCC_AHBLPENR_FLITFLPEN_Msk (0x1U << RCC_AHBLPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4694 #define RCC_AHBLPENR_FLITFLPEN RCC_AHBLPENR_FLITFLPEN_Msk /*!< Flash Interface clock enabled in sleep mode
AnnaBridge 171:3a7713b1edbc 4695 (has effect only when the Flash memory is
AnnaBridge 171:3a7713b1edbc 4696 in power down mode) */
AnnaBridge 171:3a7713b1edbc 4697 #define RCC_AHBLPENR_SRAMLPEN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4698 #define RCC_AHBLPENR_SRAMLPEN_Msk (0x1U << RCC_AHBLPENR_SRAMLPEN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4699 #define RCC_AHBLPENR_SRAMLPEN RCC_AHBLPENR_SRAMLPEN_Msk /*!< SRAM clock enabled in sleep mode */
AnnaBridge 171:3a7713b1edbc 4700 #define RCC_AHBLPENR_DMA1LPEN_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4701 #define RCC_AHBLPENR_DMA1LPEN_Msk (0x1U << RCC_AHBLPENR_DMA1LPEN_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4702 #define RCC_AHBLPENR_DMA1LPEN RCC_AHBLPENR_DMA1LPEN_Msk /*!< DMA1 clock enabled in sleep mode */
AnnaBridge 171:3a7713b1edbc 4703 #define RCC_AHBLPENR_DMA2LPEN_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4704 #define RCC_AHBLPENR_DMA2LPEN_Msk (0x1U << RCC_AHBLPENR_DMA2LPEN_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4705 #define RCC_AHBLPENR_DMA2LPEN RCC_AHBLPENR_DMA2LPEN_Msk /*!< DMA2 clock enabled in sleep mode */
AnnaBridge 171:3a7713b1edbc 4706
AnnaBridge 171:3a7713b1edbc 4707 /****************** Bit definition for RCC_APB2LPENR register ***************/
AnnaBridge 171:3a7713b1edbc 4708 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4709 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4710 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk /*!< System Configuration SYSCFG clock enabled in sleep mode */
AnnaBridge 171:3a7713b1edbc 4711 #define RCC_APB2LPENR_TIM9LPEN_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4712 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4713 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk /*!< TIM9 interface clock enabled in sleep mode */
AnnaBridge 171:3a7713b1edbc 4714 #define RCC_APB2LPENR_TIM10LPEN_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4715 #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4716 #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk /*!< TIM10 interface clock enabled in sleep mode */
AnnaBridge 171:3a7713b1edbc 4717 #define RCC_APB2LPENR_TIM11LPEN_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4718 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4719 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk /*!< TIM11 Timer clock enabled in sleep mode */
AnnaBridge 171:3a7713b1edbc 4720 #define RCC_APB2LPENR_ADC1LPEN_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4721 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4722 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk /*!< ADC1 clock enabled in sleep mode */
AnnaBridge 171:3a7713b1edbc 4723 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4724 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4725 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk /*!< SPI1 clock enabled in sleep mode */
AnnaBridge 171:3a7713b1edbc 4726 #define RCC_APB2LPENR_USART1LPEN_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4727 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4728 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk /*!< USART1 clock enabled in sleep mode */
AnnaBridge 171:3a7713b1edbc 4729
AnnaBridge 171:3a7713b1edbc 4730 /***************** Bit definition for RCC_APB1LPENR register ****************/
AnnaBridge 171:3a7713b1edbc 4731 #define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4732 #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4733 #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk /*!< Timer 2 clock enabled in sleep mode */
AnnaBridge 171:3a7713b1edbc 4734 #define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4735 #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4736 #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk /*!< Timer 3 clock enabled in sleep mode */
AnnaBridge 171:3a7713b1edbc 4737 #define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4738 #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4739 #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk /*!< Timer 4 clock enabled in sleep mode */
AnnaBridge 171:3a7713b1edbc 4740 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4741 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4742 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk /*!< Timer 5 clock enabled in sleep mode */
AnnaBridge 171:3a7713b1edbc 4743 #define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4744 #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4745 #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk /*!< Timer 6 clock enabled in sleep mode */
AnnaBridge 171:3a7713b1edbc 4746 #define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4747 #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4748 #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk /*!< Timer 7 clock enabled in sleep mode */
AnnaBridge 171:3a7713b1edbc 4749 #define RCC_APB1LPENR_LCDLPEN_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4750 #define RCC_APB1LPENR_LCDLPEN_Msk (0x1U << RCC_APB1LPENR_LCDLPEN_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4751 #define RCC_APB1LPENR_LCDLPEN RCC_APB1LPENR_LCDLPEN_Msk /*!< LCD clock enabled in sleep mode */
AnnaBridge 171:3a7713b1edbc 4752 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4753 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4754 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk /*!< Window Watchdog clock enabled in sleep mode */
AnnaBridge 171:3a7713b1edbc 4755 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4756 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4757 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk /*!< SPI 2 clock enabled in sleep mode */
AnnaBridge 171:3a7713b1edbc 4758 #define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4759 #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4760 #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk /*!< SPI 3 clock enabled in sleep mode */
AnnaBridge 171:3a7713b1edbc 4761 #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4762 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4763 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk /*!< USART 2 clock enabled in sleep mode */
AnnaBridge 171:3a7713b1edbc 4764 #define RCC_APB1LPENR_USART3LPEN_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4765 #define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4766 #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk /*!< USART 3 clock enabled in sleep mode */
AnnaBridge 171:3a7713b1edbc 4767 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4768 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4769 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk /*!< I2C 1 clock enabled in sleep mode */
AnnaBridge 171:3a7713b1edbc 4770 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4771 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4772 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk /*!< I2C 2 clock enabled in sleep mode */
AnnaBridge 171:3a7713b1edbc 4773 #define RCC_APB1LPENR_USBLPEN_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4774 #define RCC_APB1LPENR_USBLPEN_Msk (0x1U << RCC_APB1LPENR_USBLPEN_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4775 #define RCC_APB1LPENR_USBLPEN RCC_APB1LPENR_USBLPEN_Msk /*!< USB clock enabled in sleep mode */
AnnaBridge 171:3a7713b1edbc 4776 #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4777 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4778 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk /*!< Power interface clock enabled in sleep mode */
AnnaBridge 171:3a7713b1edbc 4779 #define RCC_APB1LPENR_DACLPEN_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4780 #define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4781 #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk /*!< DAC interface clock enabled in sleep mode */
AnnaBridge 171:3a7713b1edbc 4782 #define RCC_APB1LPENR_COMPLPEN_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4783 #define RCC_APB1LPENR_COMPLPEN_Msk (0x1U << RCC_APB1LPENR_COMPLPEN_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4784 #define RCC_APB1LPENR_COMPLPEN RCC_APB1LPENR_COMPLPEN_Msk /*!< Comparator interface clock enabled in sleep mode*/
AnnaBridge 171:3a7713b1edbc 4785
AnnaBridge 171:3a7713b1edbc 4786 /******************* Bit definition for RCC_CSR register ********************/
AnnaBridge 171:3a7713b1edbc 4787 #define RCC_CSR_LSION_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4788 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4789 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
AnnaBridge 171:3a7713b1edbc 4790 #define RCC_CSR_LSIRDY_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4791 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4792 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
AnnaBridge 171:3a7713b1edbc 4793
AnnaBridge 171:3a7713b1edbc 4794 #define RCC_CSR_LSEON_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4795 #define RCC_CSR_LSEON_Msk (0x1U << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4796 #define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */
AnnaBridge 171:3a7713b1edbc 4797 #define RCC_CSR_LSERDY_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4798 #define RCC_CSR_LSERDY_Msk (0x1U << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4799 #define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
AnnaBridge 171:3a7713b1edbc 4800 #define RCC_CSR_LSEBYP_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4801 #define RCC_CSR_LSEBYP_Msk (0x1U << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4802 #define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
AnnaBridge 171:3a7713b1edbc 4803
AnnaBridge 171:3a7713b1edbc 4804 #define RCC_CSR_LSECSSON_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4805 #define RCC_CSR_LSECSSON_Msk (0x1U << RCC_CSR_LSECSSON_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4806 #define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */
AnnaBridge 171:3a7713b1edbc 4807 #define RCC_CSR_LSECSSD_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4808 #define RCC_CSR_LSECSSD_Msk (0x1U << RCC_CSR_LSECSSD_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4809 #define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */
AnnaBridge 171:3a7713b1edbc 4810
AnnaBridge 171:3a7713b1edbc 4811 #define RCC_CSR_RTCSEL_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4812 #define RCC_CSR_RTCSEL_Msk (0x3U << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 4813 #define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
AnnaBridge 171:3a7713b1edbc 4814 #define RCC_CSR_RTCSEL_0 (0x1U << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4815 #define RCC_CSR_RTCSEL_1 (0x2U << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4816
AnnaBridge 171:3a7713b1edbc 4817 /*!< RTC congiguration */
AnnaBridge 171:3a7713b1edbc 4818 #define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
AnnaBridge 171:3a7713b1edbc 4819 #define RCC_CSR_RTCSEL_LSE_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4820 #define RCC_CSR_RTCSEL_LSE_Msk (0x1U << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4821 #define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */
AnnaBridge 171:3a7713b1edbc 4822 #define RCC_CSR_RTCSEL_LSI_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4823 #define RCC_CSR_RTCSEL_LSI_Msk (0x1U << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4824 #define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */
AnnaBridge 171:3a7713b1edbc 4825 #define RCC_CSR_RTCSEL_HSE_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4826 #define RCC_CSR_RTCSEL_HSE_Msk (0x3U << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 4827 #define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
AnnaBridge 171:3a7713b1edbc 4828
AnnaBridge 171:3a7713b1edbc 4829 #define RCC_CSR_RTCEN_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4830 #define RCC_CSR_RTCEN_Msk (0x1U << RCC_CSR_RTCEN_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4831 #define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */
AnnaBridge 171:3a7713b1edbc 4832 #define RCC_CSR_RTCRST_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4833 #define RCC_CSR_RTCRST_Msk (0x1U << RCC_CSR_RTCRST_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4834 #define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC reset */
AnnaBridge 171:3a7713b1edbc 4835
AnnaBridge 171:3a7713b1edbc 4836 #define RCC_CSR_RMVF_Pos (24U)
AnnaBridge 171:3a7713b1edbc 4837 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 4838 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
AnnaBridge 171:3a7713b1edbc 4839 #define RCC_CSR_OBLRSTF_Pos (25U)
AnnaBridge 171:3a7713b1edbc 4840 #define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 4841 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< Option Bytes Loader reset flag */
AnnaBridge 171:3a7713b1edbc 4842 #define RCC_CSR_PINRSTF_Pos (26U)
AnnaBridge 171:3a7713b1edbc 4843 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 4844 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
AnnaBridge 171:3a7713b1edbc 4845 #define RCC_CSR_PORRSTF_Pos (27U)
AnnaBridge 171:3a7713b1edbc 4846 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 4847 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
AnnaBridge 171:3a7713b1edbc 4848 #define RCC_CSR_SFTRSTF_Pos (28U)
AnnaBridge 171:3a7713b1edbc 4849 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 4850 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
AnnaBridge 171:3a7713b1edbc 4851 #define RCC_CSR_IWDGRSTF_Pos (29U)
AnnaBridge 171:3a7713b1edbc 4852 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 4853 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
AnnaBridge 171:3a7713b1edbc 4854 #define RCC_CSR_WWDGRSTF_Pos (30U)
AnnaBridge 171:3a7713b1edbc 4855 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 4856 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
AnnaBridge 171:3a7713b1edbc 4857 #define RCC_CSR_LPWRRSTF_Pos (31U)
AnnaBridge 171:3a7713b1edbc 4858 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 4859 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
AnnaBridge 171:3a7713b1edbc 4860
AnnaBridge 171:3a7713b1edbc 4861 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 4862 /* */
AnnaBridge 171:3a7713b1edbc 4863 /* Real-Time Clock (RTC) */
AnnaBridge 171:3a7713b1edbc 4864 /* */
AnnaBridge 171:3a7713b1edbc 4865 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 4866 /*
AnnaBridge 171:3a7713b1edbc 4867 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
AnnaBridge 171:3a7713b1edbc 4868 */
AnnaBridge 171:3a7713b1edbc 4869 #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
AnnaBridge 171:3a7713b1edbc 4870 #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
AnnaBridge 171:3a7713b1edbc 4871 #define RTC_TAMPER3_SUPPORT /*!< TAMPER 3 feature support */
AnnaBridge 171:3a7713b1edbc 4872 #define RTC_BACKUP_SUPPORT /*!< BACKUP register feature support */
AnnaBridge 171:3a7713b1edbc 4873 #define RTC_WAKEUP_SUPPORT /*!< WAKEUP feature support */
AnnaBridge 171:3a7713b1edbc 4874 #define RTC_SMOOTHCALIB_SUPPORT /*!< Smooth digital calibration feature support */
AnnaBridge 171:3a7713b1edbc 4875 #define RTC_SUBSECOND_SUPPORT /*!< Sub-second feature support */
AnnaBridge 171:3a7713b1edbc 4876
AnnaBridge 171:3a7713b1edbc 4877 /******************** Bits definition for RTC_TR register *******************/
AnnaBridge 171:3a7713b1edbc 4878 #define RTC_TR_PM_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4879 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4880 #define RTC_TR_PM RTC_TR_PM_Msk
AnnaBridge 171:3a7713b1edbc 4881 #define RTC_TR_HT_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4882 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 4883 #define RTC_TR_HT RTC_TR_HT_Msk
AnnaBridge 171:3a7713b1edbc 4884 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4885 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4886 #define RTC_TR_HU_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4887 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 4888 #define RTC_TR_HU RTC_TR_HU_Msk
AnnaBridge 171:3a7713b1edbc 4889 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4890 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4891 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4892 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4893 #define RTC_TR_MNT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4894 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 4895 #define RTC_TR_MNT RTC_TR_MNT_Msk
AnnaBridge 171:3a7713b1edbc 4896 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4897 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4898 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4899 #define RTC_TR_MNU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4900 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 4901 #define RTC_TR_MNU RTC_TR_MNU_Msk
AnnaBridge 171:3a7713b1edbc 4902 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4903 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4904 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4905 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4906 #define RTC_TR_ST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4907 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 4908 #define RTC_TR_ST RTC_TR_ST_Msk
AnnaBridge 171:3a7713b1edbc 4909 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4910 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4911 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4912 #define RTC_TR_SU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4913 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 4914 #define RTC_TR_SU RTC_TR_SU_Msk
AnnaBridge 171:3a7713b1edbc 4915 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4916 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4917 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4918 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4919
AnnaBridge 171:3a7713b1edbc 4920 /******************** Bits definition for RTC_DR register *******************/
AnnaBridge 171:3a7713b1edbc 4921 #define RTC_DR_YT_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4922 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 4923 #define RTC_DR_YT RTC_DR_YT_Msk
AnnaBridge 171:3a7713b1edbc 4924 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4925 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4926 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4927 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4928 #define RTC_DR_YU_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4929 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 4930 #define RTC_DR_YU RTC_DR_YU_Msk
AnnaBridge 171:3a7713b1edbc 4931 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4932 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4933 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4934 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4935 #define RTC_DR_WDU_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4936 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
AnnaBridge 171:3a7713b1edbc 4937 #define RTC_DR_WDU RTC_DR_WDU_Msk
AnnaBridge 171:3a7713b1edbc 4938 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4939 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4940 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4941 #define RTC_DR_MT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4942 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4943 #define RTC_DR_MT RTC_DR_MT_Msk
AnnaBridge 171:3a7713b1edbc 4944 #define RTC_DR_MU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4945 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 4946 #define RTC_DR_MU RTC_DR_MU_Msk
AnnaBridge 171:3a7713b1edbc 4947 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4948 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4949 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4950 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4951 #define RTC_DR_DT_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4952 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 4953 #define RTC_DR_DT RTC_DR_DT_Msk
AnnaBridge 171:3a7713b1edbc 4954 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4955 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4956 #define RTC_DR_DU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4957 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 4958 #define RTC_DR_DU RTC_DR_DU_Msk
AnnaBridge 171:3a7713b1edbc 4959 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4960 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4961 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4962 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4963
AnnaBridge 171:3a7713b1edbc 4964 /******************** Bits definition for RTC_CR register *******************/
AnnaBridge 171:3a7713b1edbc 4965 #define RTC_CR_COE_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4966 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4967 #define RTC_CR_COE RTC_CR_COE_Msk
AnnaBridge 171:3a7713b1edbc 4968 #define RTC_CR_OSEL_Pos (21U)
AnnaBridge 171:3a7713b1edbc 4969 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
AnnaBridge 171:3a7713b1edbc 4970 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
AnnaBridge 171:3a7713b1edbc 4971 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 4972 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4973 #define RTC_CR_POL_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4974 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4975 #define RTC_CR_POL RTC_CR_POL_Msk
AnnaBridge 171:3a7713b1edbc 4976 #define RTC_CR_COSEL_Pos (19U)
AnnaBridge 171:3a7713b1edbc 4977 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4978 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
AnnaBridge 171:3a7713b1edbc 4979 #define RTC_CR_BKP_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4980 #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4981 #define RTC_CR_BKP RTC_CR_BKP_Msk
AnnaBridge 171:3a7713b1edbc 4982 #define RTC_CR_SUB1H_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4983 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4984 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
AnnaBridge 171:3a7713b1edbc 4985 #define RTC_CR_ADD1H_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4986 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4987 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
AnnaBridge 171:3a7713b1edbc 4988 #define RTC_CR_TSIE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4989 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4990 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
AnnaBridge 171:3a7713b1edbc 4991 #define RTC_CR_WUTIE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4992 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4993 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
AnnaBridge 171:3a7713b1edbc 4994 #define RTC_CR_ALRBIE_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4995 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4996 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
AnnaBridge 171:3a7713b1edbc 4997 #define RTC_CR_ALRAIE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4998 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4999 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
AnnaBridge 171:3a7713b1edbc 5000 #define RTC_CR_TSE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5001 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5002 #define RTC_CR_TSE RTC_CR_TSE_Msk
AnnaBridge 171:3a7713b1edbc 5003 #define RTC_CR_WUTE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 5004 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5005 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
AnnaBridge 171:3a7713b1edbc 5006 #define RTC_CR_ALRBE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5007 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5008 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
AnnaBridge 171:3a7713b1edbc 5009 #define RTC_CR_ALRAE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5010 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5011 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
AnnaBridge 171:3a7713b1edbc 5012 #define RTC_CR_DCE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5013 #define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5014 #define RTC_CR_DCE RTC_CR_DCE_Msk
AnnaBridge 171:3a7713b1edbc 5015 #define RTC_CR_FMT_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5016 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5017 #define RTC_CR_FMT RTC_CR_FMT_Msk
AnnaBridge 171:3a7713b1edbc 5018 #define RTC_CR_BYPSHAD_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5019 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5020 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
AnnaBridge 171:3a7713b1edbc 5021 #define RTC_CR_REFCKON_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5022 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5023 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
AnnaBridge 171:3a7713b1edbc 5024 #define RTC_CR_TSEDGE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5025 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5026 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
AnnaBridge 171:3a7713b1edbc 5027 #define RTC_CR_WUCKSEL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5028 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 5029 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
AnnaBridge 171:3a7713b1edbc 5030 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5031 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5032 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5033
AnnaBridge 171:3a7713b1edbc 5034 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 5035 #define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
AnnaBridge 171:3a7713b1edbc 5036 #define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
AnnaBridge 171:3a7713b1edbc 5037 #define RTC_CR_BCK RTC_CR_BKP
AnnaBridge 171:3a7713b1edbc 5038
AnnaBridge 171:3a7713b1edbc 5039 /******************** Bits definition for RTC_ISR register ******************/
AnnaBridge 171:3a7713b1edbc 5040 #define RTC_ISR_RECALPF_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5041 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5042 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
AnnaBridge 171:3a7713b1edbc 5043 #define RTC_ISR_TAMP3F_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5044 #define RTC_ISR_TAMP3F_Msk (0x1U << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5045 #define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
AnnaBridge 171:3a7713b1edbc 5046 #define RTC_ISR_TAMP2F_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5047 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5048 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
AnnaBridge 171:3a7713b1edbc 5049 #define RTC_ISR_TAMP1F_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5050 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5051 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
AnnaBridge 171:3a7713b1edbc 5052 #define RTC_ISR_TSOVF_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5053 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5054 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
AnnaBridge 171:3a7713b1edbc 5055 #define RTC_ISR_TSF_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5056 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5057 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
AnnaBridge 171:3a7713b1edbc 5058 #define RTC_ISR_WUTF_Pos (10U)
AnnaBridge 171:3a7713b1edbc 5059 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5060 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
AnnaBridge 171:3a7713b1edbc 5061 #define RTC_ISR_ALRBF_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5062 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5063 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
AnnaBridge 171:3a7713b1edbc 5064 #define RTC_ISR_ALRAF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5065 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5066 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
AnnaBridge 171:3a7713b1edbc 5067 #define RTC_ISR_INIT_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5068 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5069 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
AnnaBridge 171:3a7713b1edbc 5070 #define RTC_ISR_INITF_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5071 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5072 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
AnnaBridge 171:3a7713b1edbc 5073 #define RTC_ISR_RSF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5074 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5075 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
AnnaBridge 171:3a7713b1edbc 5076 #define RTC_ISR_INITS_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5077 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5078 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
AnnaBridge 171:3a7713b1edbc 5079 #define RTC_ISR_SHPF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5080 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5081 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
AnnaBridge 171:3a7713b1edbc 5082 #define RTC_ISR_WUTWF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5083 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5084 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
AnnaBridge 171:3a7713b1edbc 5085 #define RTC_ISR_ALRBWF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5086 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5087 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
AnnaBridge 171:3a7713b1edbc 5088 #define RTC_ISR_ALRAWF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5089 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5090 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
AnnaBridge 171:3a7713b1edbc 5091
AnnaBridge 171:3a7713b1edbc 5092 /******************** Bits definition for RTC_PRER register *****************/
AnnaBridge 171:3a7713b1edbc 5093 #define RTC_PRER_PREDIV_A_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5094 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
AnnaBridge 171:3a7713b1edbc 5095 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
AnnaBridge 171:3a7713b1edbc 5096 #define RTC_PRER_PREDIV_S_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5097 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
AnnaBridge 171:3a7713b1edbc 5098 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
AnnaBridge 171:3a7713b1edbc 5099
AnnaBridge 171:3a7713b1edbc 5100 /******************** Bits definition for RTC_WUTR register *****************/
AnnaBridge 171:3a7713b1edbc 5101 #define RTC_WUTR_WUT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5102 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 5103 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
AnnaBridge 171:3a7713b1edbc 5104
AnnaBridge 171:3a7713b1edbc 5105 /******************** Bits definition for RTC_CALIBR register ***************/
AnnaBridge 171:3a7713b1edbc 5106 #define RTC_CALIBR_DCS_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5107 #define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5108 #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
AnnaBridge 171:3a7713b1edbc 5109 #define RTC_CALIBR_DC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5110 #define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 5111 #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
AnnaBridge 171:3a7713b1edbc 5112
AnnaBridge 171:3a7713b1edbc 5113 /******************** Bits definition for RTC_ALRMAR register ***************/
AnnaBridge 171:3a7713b1edbc 5114 #define RTC_ALRMAR_MSK4_Pos (31U)
AnnaBridge 171:3a7713b1edbc 5115 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 5116 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
AnnaBridge 171:3a7713b1edbc 5117 #define RTC_ALRMAR_WDSEL_Pos (30U)
AnnaBridge 171:3a7713b1edbc 5118 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 5119 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
AnnaBridge 171:3a7713b1edbc 5120 #define RTC_ALRMAR_DT_Pos (28U)
AnnaBridge 171:3a7713b1edbc 5121 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 5122 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
AnnaBridge 171:3a7713b1edbc 5123 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 5124 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 5125 #define RTC_ALRMAR_DU_Pos (24U)
AnnaBridge 171:3a7713b1edbc 5126 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 5127 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
AnnaBridge 171:3a7713b1edbc 5128 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 5129 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 5130 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 5131 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 5132 #define RTC_ALRMAR_MSK3_Pos (23U)
AnnaBridge 171:3a7713b1edbc 5133 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 5134 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
AnnaBridge 171:3a7713b1edbc 5135 #define RTC_ALRMAR_PM_Pos (22U)
AnnaBridge 171:3a7713b1edbc 5136 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 5137 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
AnnaBridge 171:3a7713b1edbc 5138 #define RTC_ALRMAR_HT_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5139 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 5140 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
AnnaBridge 171:3a7713b1edbc 5141 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5142 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 5143 #define RTC_ALRMAR_HU_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5144 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 5145 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
AnnaBridge 171:3a7713b1edbc 5146 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5147 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5148 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5149 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5150 #define RTC_ALRMAR_MSK2_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5151 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5152 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
AnnaBridge 171:3a7713b1edbc 5153 #define RTC_ALRMAR_MNT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5154 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 5155 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
AnnaBridge 171:3a7713b1edbc 5156 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5157 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5158 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5159 #define RTC_ALRMAR_MNU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5160 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 5161 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
AnnaBridge 171:3a7713b1edbc 5162 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5163 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5164 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5165 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5166 #define RTC_ALRMAR_MSK1_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5167 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5168 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
AnnaBridge 171:3a7713b1edbc 5169 #define RTC_ALRMAR_ST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5170 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 5171 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
AnnaBridge 171:3a7713b1edbc 5172 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5173 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5174 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5175 #define RTC_ALRMAR_SU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5176 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 5177 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
AnnaBridge 171:3a7713b1edbc 5178 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5179 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5180 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5181 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5182
AnnaBridge 171:3a7713b1edbc 5183 /******************** Bits definition for RTC_ALRMBR register ***************/
AnnaBridge 171:3a7713b1edbc 5184 #define RTC_ALRMBR_MSK4_Pos (31U)
AnnaBridge 171:3a7713b1edbc 5185 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 5186 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
AnnaBridge 171:3a7713b1edbc 5187 #define RTC_ALRMBR_WDSEL_Pos (30U)
AnnaBridge 171:3a7713b1edbc 5188 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 5189 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
AnnaBridge 171:3a7713b1edbc 5190 #define RTC_ALRMBR_DT_Pos (28U)
AnnaBridge 171:3a7713b1edbc 5191 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 5192 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
AnnaBridge 171:3a7713b1edbc 5193 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 5194 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 5195 #define RTC_ALRMBR_DU_Pos (24U)
AnnaBridge 171:3a7713b1edbc 5196 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 5197 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
AnnaBridge 171:3a7713b1edbc 5198 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 5199 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 5200 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 5201 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 5202 #define RTC_ALRMBR_MSK3_Pos (23U)
AnnaBridge 171:3a7713b1edbc 5203 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 5204 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
AnnaBridge 171:3a7713b1edbc 5205 #define RTC_ALRMBR_PM_Pos (22U)
AnnaBridge 171:3a7713b1edbc 5206 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 5207 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
AnnaBridge 171:3a7713b1edbc 5208 #define RTC_ALRMBR_HT_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5209 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 5210 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
AnnaBridge 171:3a7713b1edbc 5211 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5212 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 5213 #define RTC_ALRMBR_HU_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5214 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 5215 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
AnnaBridge 171:3a7713b1edbc 5216 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5217 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5218 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5219 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5220 #define RTC_ALRMBR_MSK2_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5221 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5222 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
AnnaBridge 171:3a7713b1edbc 5223 #define RTC_ALRMBR_MNT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5224 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 5225 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
AnnaBridge 171:3a7713b1edbc 5226 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5227 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5228 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5229 #define RTC_ALRMBR_MNU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5230 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 5231 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
AnnaBridge 171:3a7713b1edbc 5232 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5233 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5234 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5235 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5236 #define RTC_ALRMBR_MSK1_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5237 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5238 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
AnnaBridge 171:3a7713b1edbc 5239 #define RTC_ALRMBR_ST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5240 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 5241 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
AnnaBridge 171:3a7713b1edbc 5242 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5243 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5244 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5245 #define RTC_ALRMBR_SU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5246 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 5247 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
AnnaBridge 171:3a7713b1edbc 5248 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5249 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5250 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5251 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5252
AnnaBridge 171:3a7713b1edbc 5253 /******************** Bits definition for RTC_WPR register ******************/
AnnaBridge 171:3a7713b1edbc 5254 #define RTC_WPR_KEY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5255 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 5256 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
AnnaBridge 171:3a7713b1edbc 5257
AnnaBridge 171:3a7713b1edbc 5258 /******************** Bits definition for RTC_SSR register ******************/
AnnaBridge 171:3a7713b1edbc 5259 #define RTC_SSR_SS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5260 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 5261 #define RTC_SSR_SS RTC_SSR_SS_Msk
AnnaBridge 171:3a7713b1edbc 5262
AnnaBridge 171:3a7713b1edbc 5263 /******************** Bits definition for RTC_SHIFTR register ***************/
AnnaBridge 171:3a7713b1edbc 5264 #define RTC_SHIFTR_SUBFS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5265 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
AnnaBridge 171:3a7713b1edbc 5266 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
AnnaBridge 171:3a7713b1edbc 5267 #define RTC_SHIFTR_ADD1S_Pos (31U)
AnnaBridge 171:3a7713b1edbc 5268 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 5269 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
AnnaBridge 171:3a7713b1edbc 5270
AnnaBridge 171:3a7713b1edbc 5271 /******************** Bits definition for RTC_TSTR register *****************/
AnnaBridge 171:3a7713b1edbc 5272 #define RTC_TSTR_PM_Pos (22U)
AnnaBridge 171:3a7713b1edbc 5273 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 5274 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
AnnaBridge 171:3a7713b1edbc 5275 #define RTC_TSTR_HT_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5276 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 5277 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
AnnaBridge 171:3a7713b1edbc 5278 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5279 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 5280 #define RTC_TSTR_HU_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5281 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 5282 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
AnnaBridge 171:3a7713b1edbc 5283 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5284 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5285 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5286 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5287 #define RTC_TSTR_MNT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5288 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 5289 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
AnnaBridge 171:3a7713b1edbc 5290 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5291 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5292 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5293 #define RTC_TSTR_MNU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5294 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 5295 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
AnnaBridge 171:3a7713b1edbc 5296 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5297 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5298 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5299 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5300 #define RTC_TSTR_ST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5301 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 5302 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
AnnaBridge 171:3a7713b1edbc 5303 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5304 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5305 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5306 #define RTC_TSTR_SU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5307 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 5308 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
AnnaBridge 171:3a7713b1edbc 5309 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5310 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5311 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5312 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5313
AnnaBridge 171:3a7713b1edbc 5314 /******************** Bits definition for RTC_TSDR register *****************/
AnnaBridge 171:3a7713b1edbc 5315 #define RTC_TSDR_WDU_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5316 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
AnnaBridge 171:3a7713b1edbc 5317 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
AnnaBridge 171:3a7713b1edbc 5318 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5319 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5320 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5321 #define RTC_TSDR_MT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5322 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5323 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
AnnaBridge 171:3a7713b1edbc 5324 #define RTC_TSDR_MU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5325 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 5326 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
AnnaBridge 171:3a7713b1edbc 5327 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5328 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5329 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5330 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5331 #define RTC_TSDR_DT_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5332 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 5333 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
AnnaBridge 171:3a7713b1edbc 5334 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5335 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5336 #define RTC_TSDR_DU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5337 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 5338 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
AnnaBridge 171:3a7713b1edbc 5339 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5340 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5341 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5342 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5343
AnnaBridge 171:3a7713b1edbc 5344 /******************** Bits definition for RTC_TSSSR register ****************/
AnnaBridge 171:3a7713b1edbc 5345 #define RTC_TSSSR_SS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5346 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 5347 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
AnnaBridge 171:3a7713b1edbc 5348
AnnaBridge 171:3a7713b1edbc 5349 /******************** Bits definition for RTC_CAL register *****************/
AnnaBridge 171:3a7713b1edbc 5350 #define RTC_CALR_CALP_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5351 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5352 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
AnnaBridge 171:3a7713b1edbc 5353 #define RTC_CALR_CALW8_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5354 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5355 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
AnnaBridge 171:3a7713b1edbc 5356 #define RTC_CALR_CALW16_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5357 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5358 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
AnnaBridge 171:3a7713b1edbc 5359 #define RTC_CALR_CALM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5360 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
AnnaBridge 171:3a7713b1edbc 5361 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
AnnaBridge 171:3a7713b1edbc 5362 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5363 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5364 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5365 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5366 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5367 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5368 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5369 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5370 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5371
AnnaBridge 171:3a7713b1edbc 5372 /******************** Bits definition for RTC_TAFCR register ****************/
AnnaBridge 171:3a7713b1edbc 5373 #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
AnnaBridge 171:3a7713b1edbc 5374 #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5375 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
AnnaBridge 171:3a7713b1edbc 5376 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5377 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5378 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
AnnaBridge 171:3a7713b1edbc 5379 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5380 #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
AnnaBridge 171:3a7713b1edbc 5381 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
AnnaBridge 171:3a7713b1edbc 5382 #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5383 #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5384 #define RTC_TAFCR_TAMPFLT_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5385 #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
AnnaBridge 171:3a7713b1edbc 5386 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
AnnaBridge 171:3a7713b1edbc 5387 #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5388 #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5389 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5390 #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
AnnaBridge 171:3a7713b1edbc 5391 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
AnnaBridge 171:3a7713b1edbc 5392 #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5393 #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5394 #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5395 #define RTC_TAFCR_TAMPTS_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5396 #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5397 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
AnnaBridge 171:3a7713b1edbc 5398 #define RTC_TAFCR_TAMP3TRG_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5399 #define RTC_TAFCR_TAMP3TRG_Msk (0x1U << RTC_TAFCR_TAMP3TRG_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5400 #define RTC_TAFCR_TAMP3TRG RTC_TAFCR_TAMP3TRG_Msk
AnnaBridge 171:3a7713b1edbc 5401 #define RTC_TAFCR_TAMP3E_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5402 #define RTC_TAFCR_TAMP3E_Msk (0x1U << RTC_TAFCR_TAMP3E_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5403 #define RTC_TAFCR_TAMP3E RTC_TAFCR_TAMP3E_Msk
AnnaBridge 171:3a7713b1edbc 5404 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5405 #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5406 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
AnnaBridge 171:3a7713b1edbc 5407 #define RTC_TAFCR_TAMP2E_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5408 #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5409 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
AnnaBridge 171:3a7713b1edbc 5410 #define RTC_TAFCR_TAMPIE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5411 #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5412 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
AnnaBridge 171:3a7713b1edbc 5413 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5414 #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5415 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
AnnaBridge 171:3a7713b1edbc 5416 #define RTC_TAFCR_TAMP1E_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5417 #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5418 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
AnnaBridge 171:3a7713b1edbc 5419
AnnaBridge 171:3a7713b1edbc 5420 /******************** Bits definition for RTC_ALRMASSR register *************/
AnnaBridge 171:3a7713b1edbc 5421 #define RTC_ALRMASSR_MASKSS_Pos (24U)
AnnaBridge 171:3a7713b1edbc 5422 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 5423 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
AnnaBridge 171:3a7713b1edbc 5424 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 5425 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 5426 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 5427 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 5428 #define RTC_ALRMASSR_SS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5429 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
AnnaBridge 171:3a7713b1edbc 5430 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
AnnaBridge 171:3a7713b1edbc 5431
AnnaBridge 171:3a7713b1edbc 5432 /******************** Bits definition for RTC_ALRMBSSR register *************/
AnnaBridge 171:3a7713b1edbc 5433 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
AnnaBridge 171:3a7713b1edbc 5434 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 5435 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
AnnaBridge 171:3a7713b1edbc 5436 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 5437 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 5438 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 5439 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 5440 #define RTC_ALRMBSSR_SS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5441 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
AnnaBridge 171:3a7713b1edbc 5442 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
AnnaBridge 171:3a7713b1edbc 5443
AnnaBridge 171:3a7713b1edbc 5444 /******************** Bits definition for RTC_BKP0R register ****************/
AnnaBridge 171:3a7713b1edbc 5445 #define RTC_BKP0R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5446 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5447 #define RTC_BKP0R RTC_BKP0R_Msk
AnnaBridge 171:3a7713b1edbc 5448
AnnaBridge 171:3a7713b1edbc 5449 /******************** Bits definition for RTC_BKP1R register ****************/
AnnaBridge 171:3a7713b1edbc 5450 #define RTC_BKP1R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5451 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5452 #define RTC_BKP1R RTC_BKP1R_Msk
AnnaBridge 171:3a7713b1edbc 5453
AnnaBridge 171:3a7713b1edbc 5454 /******************** Bits definition for RTC_BKP2R register ****************/
AnnaBridge 171:3a7713b1edbc 5455 #define RTC_BKP2R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5456 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5457 #define RTC_BKP2R RTC_BKP2R_Msk
AnnaBridge 171:3a7713b1edbc 5458
AnnaBridge 171:3a7713b1edbc 5459 /******************** Bits definition for RTC_BKP3R register ****************/
AnnaBridge 171:3a7713b1edbc 5460 #define RTC_BKP3R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5461 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5462 #define RTC_BKP3R RTC_BKP3R_Msk
AnnaBridge 171:3a7713b1edbc 5463
AnnaBridge 171:3a7713b1edbc 5464 /******************** Bits definition for RTC_BKP4R register ****************/
AnnaBridge 171:3a7713b1edbc 5465 #define RTC_BKP4R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5466 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5467 #define RTC_BKP4R RTC_BKP4R_Msk
AnnaBridge 171:3a7713b1edbc 5468
AnnaBridge 171:3a7713b1edbc 5469 /******************** Bits definition for RTC_BKP5R register ****************/
AnnaBridge 171:3a7713b1edbc 5470 #define RTC_BKP5R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5471 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5472 #define RTC_BKP5R RTC_BKP5R_Msk
AnnaBridge 171:3a7713b1edbc 5473
AnnaBridge 171:3a7713b1edbc 5474 /******************** Bits definition for RTC_BKP6R register ****************/
AnnaBridge 171:3a7713b1edbc 5475 #define RTC_BKP6R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5476 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5477 #define RTC_BKP6R RTC_BKP6R_Msk
AnnaBridge 171:3a7713b1edbc 5478
AnnaBridge 171:3a7713b1edbc 5479 /******************** Bits definition for RTC_BKP7R register ****************/
AnnaBridge 171:3a7713b1edbc 5480 #define RTC_BKP7R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5481 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5482 #define RTC_BKP7R RTC_BKP7R_Msk
AnnaBridge 171:3a7713b1edbc 5483
AnnaBridge 171:3a7713b1edbc 5484 /******************** Bits definition for RTC_BKP8R register ****************/
AnnaBridge 171:3a7713b1edbc 5485 #define RTC_BKP8R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5486 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5487 #define RTC_BKP8R RTC_BKP8R_Msk
AnnaBridge 171:3a7713b1edbc 5488
AnnaBridge 171:3a7713b1edbc 5489 /******************** Bits definition for RTC_BKP9R register ****************/
AnnaBridge 171:3a7713b1edbc 5490 #define RTC_BKP9R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5491 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5492 #define RTC_BKP9R RTC_BKP9R_Msk
AnnaBridge 171:3a7713b1edbc 5493
AnnaBridge 171:3a7713b1edbc 5494 /******************** Bits definition for RTC_BKP10R register ***************/
AnnaBridge 171:3a7713b1edbc 5495 #define RTC_BKP10R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5496 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5497 #define RTC_BKP10R RTC_BKP10R_Msk
AnnaBridge 171:3a7713b1edbc 5498
AnnaBridge 171:3a7713b1edbc 5499 /******************** Bits definition for RTC_BKP11R register ***************/
AnnaBridge 171:3a7713b1edbc 5500 #define RTC_BKP11R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5501 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5502 #define RTC_BKP11R RTC_BKP11R_Msk
AnnaBridge 171:3a7713b1edbc 5503
AnnaBridge 171:3a7713b1edbc 5504 /******************** Bits definition for RTC_BKP12R register ***************/
AnnaBridge 171:3a7713b1edbc 5505 #define RTC_BKP12R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5506 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5507 #define RTC_BKP12R RTC_BKP12R_Msk
AnnaBridge 171:3a7713b1edbc 5508
AnnaBridge 171:3a7713b1edbc 5509 /******************** Bits definition for RTC_BKP13R register ***************/
AnnaBridge 171:3a7713b1edbc 5510 #define RTC_BKP13R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5511 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5512 #define RTC_BKP13R RTC_BKP13R_Msk
AnnaBridge 171:3a7713b1edbc 5513
AnnaBridge 171:3a7713b1edbc 5514 /******************** Bits definition for RTC_BKP14R register ***************/
AnnaBridge 171:3a7713b1edbc 5515 #define RTC_BKP14R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5516 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5517 #define RTC_BKP14R RTC_BKP14R_Msk
AnnaBridge 171:3a7713b1edbc 5518
AnnaBridge 171:3a7713b1edbc 5519 /******************** Bits definition for RTC_BKP15R register ***************/
AnnaBridge 171:3a7713b1edbc 5520 #define RTC_BKP15R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5521 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5522 #define RTC_BKP15R RTC_BKP15R_Msk
AnnaBridge 171:3a7713b1edbc 5523
AnnaBridge 171:3a7713b1edbc 5524 /******************** Bits definition for RTC_BKP16R register ***************/
AnnaBridge 171:3a7713b1edbc 5525 #define RTC_BKP16R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5526 #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5527 #define RTC_BKP16R RTC_BKP16R_Msk
AnnaBridge 171:3a7713b1edbc 5528
AnnaBridge 171:3a7713b1edbc 5529 /******************** Bits definition for RTC_BKP17R register ***************/
AnnaBridge 171:3a7713b1edbc 5530 #define RTC_BKP17R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5531 #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5532 #define RTC_BKP17R RTC_BKP17R_Msk
AnnaBridge 171:3a7713b1edbc 5533
AnnaBridge 171:3a7713b1edbc 5534 /******************** Bits definition for RTC_BKP18R register ***************/
AnnaBridge 171:3a7713b1edbc 5535 #define RTC_BKP18R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5536 #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5537 #define RTC_BKP18R RTC_BKP18R_Msk
AnnaBridge 171:3a7713b1edbc 5538
AnnaBridge 171:3a7713b1edbc 5539 /******************** Bits definition for RTC_BKP19R register ***************/
AnnaBridge 171:3a7713b1edbc 5540 #define RTC_BKP19R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5541 #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5542 #define RTC_BKP19R RTC_BKP19R_Msk
AnnaBridge 171:3a7713b1edbc 5543
AnnaBridge 171:3a7713b1edbc 5544 /******************** Bits definition for RTC_BKP20R register ***************/
AnnaBridge 171:3a7713b1edbc 5545 #define RTC_BKP20R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5546 #define RTC_BKP20R_Msk (0xFFFFFFFFU << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5547 #define RTC_BKP20R RTC_BKP20R_Msk
AnnaBridge 171:3a7713b1edbc 5548
AnnaBridge 171:3a7713b1edbc 5549 /******************** Bits definition for RTC_BKP21R register ***************/
AnnaBridge 171:3a7713b1edbc 5550 #define RTC_BKP21R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5551 #define RTC_BKP21R_Msk (0xFFFFFFFFU << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5552 #define RTC_BKP21R RTC_BKP21R_Msk
AnnaBridge 171:3a7713b1edbc 5553
AnnaBridge 171:3a7713b1edbc 5554 /******************** Bits definition for RTC_BKP22R register ***************/
AnnaBridge 171:3a7713b1edbc 5555 #define RTC_BKP22R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5556 #define RTC_BKP22R_Msk (0xFFFFFFFFU << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5557 #define RTC_BKP22R RTC_BKP22R_Msk
AnnaBridge 171:3a7713b1edbc 5558
AnnaBridge 171:3a7713b1edbc 5559 /******************** Bits definition for RTC_BKP23R register ***************/
AnnaBridge 171:3a7713b1edbc 5560 #define RTC_BKP23R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5561 #define RTC_BKP23R_Msk (0xFFFFFFFFU << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5562 #define RTC_BKP23R RTC_BKP23R_Msk
AnnaBridge 171:3a7713b1edbc 5563
AnnaBridge 171:3a7713b1edbc 5564 /******************** Bits definition for RTC_BKP24R register ***************/
AnnaBridge 171:3a7713b1edbc 5565 #define RTC_BKP24R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5566 #define RTC_BKP24R_Msk (0xFFFFFFFFU << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5567 #define RTC_BKP24R RTC_BKP24R_Msk
AnnaBridge 171:3a7713b1edbc 5568
AnnaBridge 171:3a7713b1edbc 5569 /******************** Bits definition for RTC_BKP25R register ***************/
AnnaBridge 171:3a7713b1edbc 5570 #define RTC_BKP25R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5571 #define RTC_BKP25R_Msk (0xFFFFFFFFU << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5572 #define RTC_BKP25R RTC_BKP25R_Msk
AnnaBridge 171:3a7713b1edbc 5573
AnnaBridge 171:3a7713b1edbc 5574 /******************** Bits definition for RTC_BKP26R register ***************/
AnnaBridge 171:3a7713b1edbc 5575 #define RTC_BKP26R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5576 #define RTC_BKP26R_Msk (0xFFFFFFFFU << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5577 #define RTC_BKP26R RTC_BKP26R_Msk
AnnaBridge 171:3a7713b1edbc 5578
AnnaBridge 171:3a7713b1edbc 5579 /******************** Bits definition for RTC_BKP27R register ***************/
AnnaBridge 171:3a7713b1edbc 5580 #define RTC_BKP27R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5581 #define RTC_BKP27R_Msk (0xFFFFFFFFU << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5582 #define RTC_BKP27R RTC_BKP27R_Msk
AnnaBridge 171:3a7713b1edbc 5583
AnnaBridge 171:3a7713b1edbc 5584 /******************** Bits definition for RTC_BKP28R register ***************/
AnnaBridge 171:3a7713b1edbc 5585 #define RTC_BKP28R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5586 #define RTC_BKP28R_Msk (0xFFFFFFFFU << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5587 #define RTC_BKP28R RTC_BKP28R_Msk
AnnaBridge 171:3a7713b1edbc 5588
AnnaBridge 171:3a7713b1edbc 5589 /******************** Bits definition for RTC_BKP29R register ***************/
AnnaBridge 171:3a7713b1edbc 5590 #define RTC_BKP29R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5591 #define RTC_BKP29R_Msk (0xFFFFFFFFU << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5592 #define RTC_BKP29R RTC_BKP29R_Msk
AnnaBridge 171:3a7713b1edbc 5593
AnnaBridge 171:3a7713b1edbc 5594 /******************** Bits definition for RTC_BKP30R register ***************/
AnnaBridge 171:3a7713b1edbc 5595 #define RTC_BKP30R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5596 #define RTC_BKP30R_Msk (0xFFFFFFFFU << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5597 #define RTC_BKP30R RTC_BKP30R_Msk
AnnaBridge 171:3a7713b1edbc 5598
AnnaBridge 171:3a7713b1edbc 5599 /******************** Bits definition for RTC_BKP31R register ***************/
AnnaBridge 171:3a7713b1edbc 5600 #define RTC_BKP31R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5601 #define RTC_BKP31R_Msk (0xFFFFFFFFU << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 5602 #define RTC_BKP31R RTC_BKP31R_Msk
AnnaBridge 171:3a7713b1edbc 5603
AnnaBridge 171:3a7713b1edbc 5604 /******************** Number of backup registers ******************************/
AnnaBridge 171:3a7713b1edbc 5605 #define RTC_BKP_NUMBER 32
AnnaBridge 171:3a7713b1edbc 5606
AnnaBridge 171:3a7713b1edbc 5607 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 5608 /* */
AnnaBridge 171:3a7713b1edbc 5609 /* Serial Peripheral Interface (SPI) */
AnnaBridge 171:3a7713b1edbc 5610 /* */
AnnaBridge 171:3a7713b1edbc 5611 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 5612
AnnaBridge 171:3a7713b1edbc 5613 /*
AnnaBridge 171:3a7713b1edbc 5614 * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
AnnaBridge 171:3a7713b1edbc 5615 */
AnnaBridge 171:3a7713b1edbc 5616 #define SPI_I2S_SUPPORT
AnnaBridge 171:3a7713b1edbc 5617
AnnaBridge 171:3a7713b1edbc 5618 /******************* Bit definition for SPI_CR1 register ********************/
AnnaBridge 171:3a7713b1edbc 5619 #define SPI_CR1_CPHA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5620 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5621 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
AnnaBridge 171:3a7713b1edbc 5622 #define SPI_CR1_CPOL_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5623 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5624 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
AnnaBridge 171:3a7713b1edbc 5625 #define SPI_CR1_MSTR_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5626 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5627 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
AnnaBridge 171:3a7713b1edbc 5628
AnnaBridge 171:3a7713b1edbc 5629 #define SPI_CR1_BR_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5630 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
AnnaBridge 171:3a7713b1edbc 5631 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
AnnaBridge 171:3a7713b1edbc 5632 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5633 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5634 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5635
AnnaBridge 171:3a7713b1edbc 5636 #define SPI_CR1_SPE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5637 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5638 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
AnnaBridge 171:3a7713b1edbc 5639 #define SPI_CR1_LSBFIRST_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5640 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5641 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
AnnaBridge 171:3a7713b1edbc 5642 #define SPI_CR1_SSI_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5643 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5644 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
AnnaBridge 171:3a7713b1edbc 5645 #define SPI_CR1_SSM_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5646 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5647 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
AnnaBridge 171:3a7713b1edbc 5648 #define SPI_CR1_RXONLY_Pos (10U)
AnnaBridge 171:3a7713b1edbc 5649 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5650 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
AnnaBridge 171:3a7713b1edbc 5651 #define SPI_CR1_DFF_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5652 #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5653 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
AnnaBridge 171:3a7713b1edbc 5654 #define SPI_CR1_CRCNEXT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5655 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5656 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
AnnaBridge 171:3a7713b1edbc 5657 #define SPI_CR1_CRCEN_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5658 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5659 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
AnnaBridge 171:3a7713b1edbc 5660 #define SPI_CR1_BIDIOE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5661 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5662 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
AnnaBridge 171:3a7713b1edbc 5663 #define SPI_CR1_BIDIMODE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5664 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5665 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
AnnaBridge 171:3a7713b1edbc 5666
AnnaBridge 171:3a7713b1edbc 5667 /******************* Bit definition for SPI_CR2 register ********************/
AnnaBridge 171:3a7713b1edbc 5668 #define SPI_CR2_RXDMAEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5669 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5670 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
AnnaBridge 171:3a7713b1edbc 5671 #define SPI_CR2_TXDMAEN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5672 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5673 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
AnnaBridge 171:3a7713b1edbc 5674 #define SPI_CR2_SSOE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5675 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5676 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
AnnaBridge 171:3a7713b1edbc 5677 #define SPI_CR2_FRF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5678 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5679 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame format */
AnnaBridge 171:3a7713b1edbc 5680 #define SPI_CR2_ERRIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5681 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5682 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 5683 #define SPI_CR2_RXNEIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5684 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5685 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 5686 #define SPI_CR2_TXEIE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5687 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5688 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 5689
AnnaBridge 171:3a7713b1edbc 5690 /******************** Bit definition for SPI_SR register ********************/
AnnaBridge 171:3a7713b1edbc 5691 #define SPI_SR_RXNE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5692 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5693 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
AnnaBridge 171:3a7713b1edbc 5694 #define SPI_SR_TXE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5695 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5696 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
AnnaBridge 171:3a7713b1edbc 5697 #define SPI_SR_CHSIDE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5698 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5699 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
AnnaBridge 171:3a7713b1edbc 5700 #define SPI_SR_UDR_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5701 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5702 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
AnnaBridge 171:3a7713b1edbc 5703 #define SPI_SR_CRCERR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5704 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5705 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
AnnaBridge 171:3a7713b1edbc 5706 #define SPI_SR_MODF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5707 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5708 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
AnnaBridge 171:3a7713b1edbc 5709 #define SPI_SR_OVR_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5710 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5711 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
AnnaBridge 171:3a7713b1edbc 5712 #define SPI_SR_BSY_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5713 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5714 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
AnnaBridge 171:3a7713b1edbc 5715 #define SPI_SR_FRE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5716 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5717 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
AnnaBridge 171:3a7713b1edbc 5718
AnnaBridge 171:3a7713b1edbc 5719 /******************** Bit definition for SPI_DR register ********************/
AnnaBridge 171:3a7713b1edbc 5720 #define SPI_DR_DR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5721 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 5722 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
AnnaBridge 171:3a7713b1edbc 5723
AnnaBridge 171:3a7713b1edbc 5724 /******************* Bit definition for SPI_CRCPR register ******************/
AnnaBridge 171:3a7713b1edbc 5725 #define SPI_CRCPR_CRCPOLY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5726 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 5727 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
AnnaBridge 171:3a7713b1edbc 5728
AnnaBridge 171:3a7713b1edbc 5729 /****************** Bit definition for SPI_RXCRCR register ******************/
AnnaBridge 171:3a7713b1edbc 5730 #define SPI_RXCRCR_RXCRC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5731 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 5732 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
AnnaBridge 171:3a7713b1edbc 5733
AnnaBridge 171:3a7713b1edbc 5734 /****************** Bit definition for SPI_TXCRCR register ******************/
AnnaBridge 171:3a7713b1edbc 5735 #define SPI_TXCRCR_TXCRC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5736 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 5737 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
AnnaBridge 171:3a7713b1edbc 5738
AnnaBridge 171:3a7713b1edbc 5739 /****************** Bit definition for SPI_I2SCFGR register *****************/
AnnaBridge 171:3a7713b1edbc 5740 #define SPI_I2SCFGR_CHLEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5741 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5742 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
AnnaBridge 171:3a7713b1edbc 5743
AnnaBridge 171:3a7713b1edbc 5744 #define SPI_I2SCFGR_DATLEN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5745 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
AnnaBridge 171:3a7713b1edbc 5746 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
AnnaBridge 171:3a7713b1edbc 5747 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5748 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5749
AnnaBridge 171:3a7713b1edbc 5750 #define SPI_I2SCFGR_CKPOL_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5751 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5752 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
AnnaBridge 171:3a7713b1edbc 5753
AnnaBridge 171:3a7713b1edbc 5754 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5755 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 5756 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
AnnaBridge 171:3a7713b1edbc 5757 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5758 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5759
AnnaBridge 171:3a7713b1edbc 5760 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5761 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5762 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
AnnaBridge 171:3a7713b1edbc 5763
AnnaBridge 171:3a7713b1edbc 5764 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5765 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 5766 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
AnnaBridge 171:3a7713b1edbc 5767 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5768 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5769
AnnaBridge 171:3a7713b1edbc 5770 #define SPI_I2SCFGR_I2SE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 5771 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5772 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
AnnaBridge 171:3a7713b1edbc 5773 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5774 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5775 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
AnnaBridge 171:3a7713b1edbc 5776
AnnaBridge 171:3a7713b1edbc 5777 /****************** Bit definition for SPI_I2SPR register *******************/
AnnaBridge 171:3a7713b1edbc 5778 #define SPI_I2SPR_I2SDIV_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5779 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 5780 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
AnnaBridge 171:3a7713b1edbc 5781 #define SPI_I2SPR_ODD_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5782 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5783 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
AnnaBridge 171:3a7713b1edbc 5784 #define SPI_I2SPR_MCKOE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5785 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5786 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
AnnaBridge 171:3a7713b1edbc 5787
AnnaBridge 171:3a7713b1edbc 5788 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 5789 /* */
AnnaBridge 171:3a7713b1edbc 5790 /* System Configuration (SYSCFG) */
AnnaBridge 171:3a7713b1edbc 5791 /* */
AnnaBridge 171:3a7713b1edbc 5792 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 5793 /***************** Bit definition for SYSCFG_MEMRMP register ****************/
AnnaBridge 171:3a7713b1edbc 5794 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5795 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 5796 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
AnnaBridge 171:3a7713b1edbc 5797 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5798 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5799 #define SYSCFG_MEMRMP_BOOT_MODE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5800 #define SYSCFG_MEMRMP_BOOT_MODE_Msk (0x3U << SYSCFG_MEMRMP_BOOT_MODE_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 5801 #define SYSCFG_MEMRMP_BOOT_MODE SYSCFG_MEMRMP_BOOT_MODE_Msk /*!< Boot mode Config */
AnnaBridge 171:3a7713b1edbc 5802 #define SYSCFG_MEMRMP_BOOT_MODE_0 (0x1U << SYSCFG_MEMRMP_BOOT_MODE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5803 #define SYSCFG_MEMRMP_BOOT_MODE_1 (0x2U << SYSCFG_MEMRMP_BOOT_MODE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5804
AnnaBridge 171:3a7713b1edbc 5805 /***************** Bit definition for SYSCFG_PMC register *******************/
AnnaBridge 171:3a7713b1edbc 5806 #define SYSCFG_PMC_USB_PU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5807 #define SYSCFG_PMC_USB_PU_Msk (0x1U << SYSCFG_PMC_USB_PU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5808 #define SYSCFG_PMC_USB_PU SYSCFG_PMC_USB_PU_Msk /*!< SYSCFG PMC */
AnnaBridge 171:3a7713b1edbc 5809 #define SYSCFG_PMC_LCD_CAPA_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5810 #define SYSCFG_PMC_LCD_CAPA_Msk (0x1FU << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x0000003E */
AnnaBridge 171:3a7713b1edbc 5811 #define SYSCFG_PMC_LCD_CAPA SYSCFG_PMC_LCD_CAPA_Msk /*!< LCD_CAPA decoupling capacitance connection */
AnnaBridge 171:3a7713b1edbc 5812 #define SYSCFG_PMC_LCD_CAPA_0 (0x01U << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5813 #define SYSCFG_PMC_LCD_CAPA_1 (0x02U << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5814 #define SYSCFG_PMC_LCD_CAPA_2 (0x04U << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5815 #define SYSCFG_PMC_LCD_CAPA_3 (0x08U << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5816 #define SYSCFG_PMC_LCD_CAPA_4 (0x10U << SYSCFG_PMC_LCD_CAPA_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5817
AnnaBridge 171:3a7713b1edbc 5818 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
AnnaBridge 171:3a7713b1edbc 5819 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5820 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 5821 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
AnnaBridge 171:3a7713b1edbc 5822 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5823 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 5824 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
AnnaBridge 171:3a7713b1edbc 5825 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5826 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 5827 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
AnnaBridge 171:3a7713b1edbc 5828 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5829 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 5830 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
AnnaBridge 171:3a7713b1edbc 5831
AnnaBridge 171:3a7713b1edbc 5832 /**
AnnaBridge 171:3a7713b1edbc 5833 * @brief EXTI0 configuration
AnnaBridge 171:3a7713b1edbc 5834 */
AnnaBridge 171:3a7713b1edbc 5835 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */
AnnaBridge 171:3a7713b1edbc 5836 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */
AnnaBridge 171:3a7713b1edbc 5837 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */
AnnaBridge 171:3a7713b1edbc 5838 #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */
AnnaBridge 171:3a7713b1edbc 5839 #define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!< PE[0] pin */
AnnaBridge 171:3a7713b1edbc 5840 #define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */
AnnaBridge 171:3a7713b1edbc 5841 #define SYSCFG_EXTICR1_EXTI0_PF (0x00000006U) /*!< PF[0] pin */
AnnaBridge 171:3a7713b1edbc 5842 #define SYSCFG_EXTICR1_EXTI0_PG (0x00000007U) /*!< PG[0] pin */
AnnaBridge 171:3a7713b1edbc 5843
AnnaBridge 171:3a7713b1edbc 5844 /**
AnnaBridge 171:3a7713b1edbc 5845 * @brief EXTI1 configuration
AnnaBridge 171:3a7713b1edbc 5846 */
AnnaBridge 171:3a7713b1edbc 5847 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */
AnnaBridge 171:3a7713b1edbc 5848 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */
AnnaBridge 171:3a7713b1edbc 5849 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */
AnnaBridge 171:3a7713b1edbc 5850 #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */
AnnaBridge 171:3a7713b1edbc 5851 #define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!< PE[1] pin */
AnnaBridge 171:3a7713b1edbc 5852 #define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */
AnnaBridge 171:3a7713b1edbc 5853 #define SYSCFG_EXTICR1_EXTI1_PF (0x00000060U) /*!< PF[1] pin */
AnnaBridge 171:3a7713b1edbc 5854 #define SYSCFG_EXTICR1_EXTI1_PG (0x00000070U) /*!< PG[1] pin */
AnnaBridge 171:3a7713b1edbc 5855
AnnaBridge 171:3a7713b1edbc 5856 /**
AnnaBridge 171:3a7713b1edbc 5857 * @brief EXTI2 configuration
AnnaBridge 171:3a7713b1edbc 5858 */
AnnaBridge 171:3a7713b1edbc 5859 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */
AnnaBridge 171:3a7713b1edbc 5860 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */
AnnaBridge 171:3a7713b1edbc 5861 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */
AnnaBridge 171:3a7713b1edbc 5862 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
AnnaBridge 171:3a7713b1edbc 5863 #define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!< PE[2] pin */
AnnaBridge 171:3a7713b1edbc 5864 #define SYSCFG_EXTICR1_EXTI2_PH (0x00000500U) /*!< PH[2] pin */
AnnaBridge 171:3a7713b1edbc 5865 #define SYSCFG_EXTICR1_EXTI2_PF (0x00000600U) /*!< PF[2] pin */
AnnaBridge 171:3a7713b1edbc 5866 #define SYSCFG_EXTICR1_EXTI2_PG (0x00000700U) /*!< PG[2] pin */
AnnaBridge 171:3a7713b1edbc 5867
AnnaBridge 171:3a7713b1edbc 5868 /**
AnnaBridge 171:3a7713b1edbc 5869 * @brief EXTI3 configuration
AnnaBridge 171:3a7713b1edbc 5870 */
AnnaBridge 171:3a7713b1edbc 5871 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */
AnnaBridge 171:3a7713b1edbc 5872 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */
AnnaBridge 171:3a7713b1edbc 5873 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
AnnaBridge 171:3a7713b1edbc 5874 #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
AnnaBridge 171:3a7713b1edbc 5875 #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */
AnnaBridge 171:3a7713b1edbc 5876 #define SYSCFG_EXTICR1_EXTI3_PF (0x00003000U) /*!< PF[3] pin */
AnnaBridge 171:3a7713b1edbc 5877 #define SYSCFG_EXTICR1_EXTI3_PG (0x00004000U) /*!< PG[3] pin */
AnnaBridge 171:3a7713b1edbc 5878
AnnaBridge 171:3a7713b1edbc 5879 /***************** Bit definition for SYSCFG_EXTICR2 register *****************/
AnnaBridge 171:3a7713b1edbc 5880 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5881 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 5882 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
AnnaBridge 171:3a7713b1edbc 5883 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5884 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 5885 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
AnnaBridge 171:3a7713b1edbc 5886 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5887 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 5888 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
AnnaBridge 171:3a7713b1edbc 5889 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5890 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 5891 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
AnnaBridge 171:3a7713b1edbc 5892
AnnaBridge 171:3a7713b1edbc 5893 /**
AnnaBridge 171:3a7713b1edbc 5894 * @brief EXTI4 configuration
AnnaBridge 171:3a7713b1edbc 5895 */
AnnaBridge 171:3a7713b1edbc 5896 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */
AnnaBridge 171:3a7713b1edbc 5897 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */
AnnaBridge 171:3a7713b1edbc 5898 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
AnnaBridge 171:3a7713b1edbc 5899 #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */
AnnaBridge 171:3a7713b1edbc 5900 #define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!< PE[4] pin */
AnnaBridge 171:3a7713b1edbc 5901 #define SYSCFG_EXTICR2_EXTI4_PF (0x00000006U) /*!< PF[4] pin */
AnnaBridge 171:3a7713b1edbc 5902 #define SYSCFG_EXTICR2_EXTI4_PG (0x00000007U) /*!< PG[4] pin */
AnnaBridge 171:3a7713b1edbc 5903
AnnaBridge 171:3a7713b1edbc 5904 /**
AnnaBridge 171:3a7713b1edbc 5905 * @brief EXTI5 configuration
AnnaBridge 171:3a7713b1edbc 5906 */
AnnaBridge 171:3a7713b1edbc 5907 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */
AnnaBridge 171:3a7713b1edbc 5908 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */
AnnaBridge 171:3a7713b1edbc 5909 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
AnnaBridge 171:3a7713b1edbc 5910 #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */
AnnaBridge 171:3a7713b1edbc 5911 #define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!< PE[5] pin */
AnnaBridge 171:3a7713b1edbc 5912 #define SYSCFG_EXTICR2_EXTI5_PF (0x00000060U) /*!< PF[5] pin */
AnnaBridge 171:3a7713b1edbc 5913 #define SYSCFG_EXTICR2_EXTI5_PG (0x00000070U) /*!< PG[5] pin */
AnnaBridge 171:3a7713b1edbc 5914
AnnaBridge 171:3a7713b1edbc 5915 /**
AnnaBridge 171:3a7713b1edbc 5916 * @brief EXTI6 configuration
AnnaBridge 171:3a7713b1edbc 5917 */
AnnaBridge 171:3a7713b1edbc 5918 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */
AnnaBridge 171:3a7713b1edbc 5919 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */
AnnaBridge 171:3a7713b1edbc 5920 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
AnnaBridge 171:3a7713b1edbc 5921 #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */
AnnaBridge 171:3a7713b1edbc 5922 #define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!< PE[6] pin */
AnnaBridge 171:3a7713b1edbc 5923 #define SYSCFG_EXTICR2_EXTI6_PF (0x00000600U) /*!< PF[6] pin */
AnnaBridge 171:3a7713b1edbc 5924 #define SYSCFG_EXTICR2_EXTI6_PG (0x00000700U) /*!< PG[6] pin */
AnnaBridge 171:3a7713b1edbc 5925
AnnaBridge 171:3a7713b1edbc 5926 /**
AnnaBridge 171:3a7713b1edbc 5927 * @brief EXTI7 configuration
AnnaBridge 171:3a7713b1edbc 5928 */
AnnaBridge 171:3a7713b1edbc 5929 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */
AnnaBridge 171:3a7713b1edbc 5930 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */
AnnaBridge 171:3a7713b1edbc 5931 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
AnnaBridge 171:3a7713b1edbc 5932 #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */
AnnaBridge 171:3a7713b1edbc 5933 #define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!< PE[7] pin */
AnnaBridge 171:3a7713b1edbc 5934 #define SYSCFG_EXTICR2_EXTI7_PF (0x00006000U) /*!< PF[7] pin */
AnnaBridge 171:3a7713b1edbc 5935 #define SYSCFG_EXTICR2_EXTI7_PG (0x00007000U) /*!< PG[7] pin */
AnnaBridge 171:3a7713b1edbc 5936
AnnaBridge 171:3a7713b1edbc 5937 /***************** Bit definition for SYSCFG_EXTICR3 register *****************/
AnnaBridge 171:3a7713b1edbc 5938 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5939 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 5940 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
AnnaBridge 171:3a7713b1edbc 5941 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5942 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 5943 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
AnnaBridge 171:3a7713b1edbc 5944 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5945 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 5946 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
AnnaBridge 171:3a7713b1edbc 5947 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5948 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 5949 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
AnnaBridge 171:3a7713b1edbc 5950
AnnaBridge 171:3a7713b1edbc 5951 /**
AnnaBridge 171:3a7713b1edbc 5952 * @brief EXTI8 configuration
AnnaBridge 171:3a7713b1edbc 5953 */
AnnaBridge 171:3a7713b1edbc 5954 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */
AnnaBridge 171:3a7713b1edbc 5955 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */
AnnaBridge 171:3a7713b1edbc 5956 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
AnnaBridge 171:3a7713b1edbc 5957 #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */
AnnaBridge 171:3a7713b1edbc 5958 #define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!< PE[8] pin */
AnnaBridge 171:3a7713b1edbc 5959 #define SYSCFG_EXTICR3_EXTI8_PF (0x00000006U) /*!< PF[8] pin */
AnnaBridge 171:3a7713b1edbc 5960 #define SYSCFG_EXTICR3_EXTI8_PG (0x00000007U) /*!< PG[8] pin */
AnnaBridge 171:3a7713b1edbc 5961
AnnaBridge 171:3a7713b1edbc 5962 /**
AnnaBridge 171:3a7713b1edbc 5963 * @brief EXTI9 configuration
AnnaBridge 171:3a7713b1edbc 5964 */
AnnaBridge 171:3a7713b1edbc 5965 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */
AnnaBridge 171:3a7713b1edbc 5966 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */
AnnaBridge 171:3a7713b1edbc 5967 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
AnnaBridge 171:3a7713b1edbc 5968 #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */
AnnaBridge 171:3a7713b1edbc 5969 #define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!< PE[9] pin */
AnnaBridge 171:3a7713b1edbc 5970 #define SYSCFG_EXTICR3_EXTI9_PF (0x00000060U) /*!< PF[9] pin */
AnnaBridge 171:3a7713b1edbc 5971 #define SYSCFG_EXTICR3_EXTI9_PG (0x00000070U) /*!< PG[9] pin */
AnnaBridge 171:3a7713b1edbc 5972
AnnaBridge 171:3a7713b1edbc 5973 /**
AnnaBridge 171:3a7713b1edbc 5974 * @brief EXTI10 configuration
AnnaBridge 171:3a7713b1edbc 5975 */
AnnaBridge 171:3a7713b1edbc 5976 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */
AnnaBridge 171:3a7713b1edbc 5977 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */
AnnaBridge 171:3a7713b1edbc 5978 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
AnnaBridge 171:3a7713b1edbc 5979 #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */
AnnaBridge 171:3a7713b1edbc 5980 #define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!< PE[10] pin */
AnnaBridge 171:3a7713b1edbc 5981 #define SYSCFG_EXTICR3_EXTI10_PF (0x00000600U) /*!< PF[10] pin */
AnnaBridge 171:3a7713b1edbc 5982 #define SYSCFG_EXTICR3_EXTI10_PG (0x00000700U) /*!< PG[10] pin */
AnnaBridge 171:3a7713b1edbc 5983
AnnaBridge 171:3a7713b1edbc 5984 /**
AnnaBridge 171:3a7713b1edbc 5985 * @brief EXTI11 configuration
AnnaBridge 171:3a7713b1edbc 5986 */
AnnaBridge 171:3a7713b1edbc 5987 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */
AnnaBridge 171:3a7713b1edbc 5988 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */
AnnaBridge 171:3a7713b1edbc 5989 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
AnnaBridge 171:3a7713b1edbc 5990 #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */
AnnaBridge 171:3a7713b1edbc 5991 #define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!< PE[11] pin */
AnnaBridge 171:3a7713b1edbc 5992 #define SYSCFG_EXTICR3_EXTI11_PF (0x00006000U) /*!< PF[11] pin */
AnnaBridge 171:3a7713b1edbc 5993 #define SYSCFG_EXTICR3_EXTI11_PG (0x00007000U) /*!< PG[11] pin */
AnnaBridge 171:3a7713b1edbc 5994
AnnaBridge 171:3a7713b1edbc 5995 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/
AnnaBridge 171:3a7713b1edbc 5996 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5997 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 5998 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
AnnaBridge 171:3a7713b1edbc 5999 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6000 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 6001 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
AnnaBridge 171:3a7713b1edbc 6002 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6003 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 6004 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
AnnaBridge 171:3a7713b1edbc 6005 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6006 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 6007 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
AnnaBridge 171:3a7713b1edbc 6008
AnnaBridge 171:3a7713b1edbc 6009 /**
AnnaBridge 171:3a7713b1edbc 6010 * @brief EXTI12 configuration
AnnaBridge 171:3a7713b1edbc 6011 */
AnnaBridge 171:3a7713b1edbc 6012 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */
AnnaBridge 171:3a7713b1edbc 6013 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */
AnnaBridge 171:3a7713b1edbc 6014 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
AnnaBridge 171:3a7713b1edbc 6015 #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */
AnnaBridge 171:3a7713b1edbc 6016 #define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!< PE[12] pin */
AnnaBridge 171:3a7713b1edbc 6017 #define SYSCFG_EXTICR4_EXTI12_PF (0x00000006U) /*!< PF[12] pin */
AnnaBridge 171:3a7713b1edbc 6018 #define SYSCFG_EXTICR4_EXTI12_PG (0x00000007U) /*!< PG[12] pin */
AnnaBridge 171:3a7713b1edbc 6019
AnnaBridge 171:3a7713b1edbc 6020 /**
AnnaBridge 171:3a7713b1edbc 6021 * @brief EXTI13 configuration
AnnaBridge 171:3a7713b1edbc 6022 */
AnnaBridge 171:3a7713b1edbc 6023 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */
AnnaBridge 171:3a7713b1edbc 6024 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */
AnnaBridge 171:3a7713b1edbc 6025 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
AnnaBridge 171:3a7713b1edbc 6026 #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */
AnnaBridge 171:3a7713b1edbc 6027 #define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!< PE[13] pin */
AnnaBridge 171:3a7713b1edbc 6028 #define SYSCFG_EXTICR4_EXTI13_PF (0x00000060U) /*!< PF[13] pin */
AnnaBridge 171:3a7713b1edbc 6029 #define SYSCFG_EXTICR4_EXTI13_PG (0x00000070U) /*!< PG[13] pin */
AnnaBridge 171:3a7713b1edbc 6030
AnnaBridge 171:3a7713b1edbc 6031 /**
AnnaBridge 171:3a7713b1edbc 6032 * @brief EXTI14 configuration
AnnaBridge 171:3a7713b1edbc 6033 */
AnnaBridge 171:3a7713b1edbc 6034 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */
AnnaBridge 171:3a7713b1edbc 6035 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */
AnnaBridge 171:3a7713b1edbc 6036 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
AnnaBridge 171:3a7713b1edbc 6037 #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */
AnnaBridge 171:3a7713b1edbc 6038 #define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!< PE[14] pin */
AnnaBridge 171:3a7713b1edbc 6039 #define SYSCFG_EXTICR4_EXTI14_PF (0x00000600U) /*!< PF[14] pin */
AnnaBridge 171:3a7713b1edbc 6040 #define SYSCFG_EXTICR4_EXTI14_PG (0x00000700U) /*!< PG[14] pin */
AnnaBridge 171:3a7713b1edbc 6041
AnnaBridge 171:3a7713b1edbc 6042 /**
AnnaBridge 171:3a7713b1edbc 6043 * @brief EXTI15 configuration
AnnaBridge 171:3a7713b1edbc 6044 */
AnnaBridge 171:3a7713b1edbc 6045 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */
AnnaBridge 171:3a7713b1edbc 6046 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */
AnnaBridge 171:3a7713b1edbc 6047 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
AnnaBridge 171:3a7713b1edbc 6048 #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */
AnnaBridge 171:3a7713b1edbc 6049 #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */
AnnaBridge 171:3a7713b1edbc 6050 #define SYSCFG_EXTICR4_EXTI15_PF (0x00006000U) /*!< PF[15] pin */
AnnaBridge 171:3a7713b1edbc 6051 #define SYSCFG_EXTICR4_EXTI15_PG (0x00007000U) /*!< PG[15] pin */
AnnaBridge 171:3a7713b1edbc 6052
AnnaBridge 171:3a7713b1edbc 6053 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 6054 /* */
AnnaBridge 171:3a7713b1edbc 6055 /* Routing Interface (RI) */
AnnaBridge 171:3a7713b1edbc 6056 /* */
AnnaBridge 171:3a7713b1edbc 6057 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 6058
AnnaBridge 171:3a7713b1edbc 6059 /******************** Bit definition for RI_ICR register ********************/
AnnaBridge 171:3a7713b1edbc 6060 #define RI_ICR_IC1OS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6061 #define RI_ICR_IC1OS_Msk (0xFU << RI_ICR_IC1OS_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 6062 #define RI_ICR_IC1OS RI_ICR_IC1OS_Msk /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
AnnaBridge 171:3a7713b1edbc 6063 #define RI_ICR_IC1OS_0 (0x1U << RI_ICR_IC1OS_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6064 #define RI_ICR_IC1OS_1 (0x2U << RI_ICR_IC1OS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6065 #define RI_ICR_IC1OS_2 (0x4U << RI_ICR_IC1OS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6066 #define RI_ICR_IC1OS_3 (0x8U << RI_ICR_IC1OS_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6067
AnnaBridge 171:3a7713b1edbc 6068 #define RI_ICR_IC2OS_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6069 #define RI_ICR_IC2OS_Msk (0xFU << RI_ICR_IC2OS_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 6070 #define RI_ICR_IC2OS RI_ICR_IC2OS_Msk /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
AnnaBridge 171:3a7713b1edbc 6071 #define RI_ICR_IC2OS_0 (0x1U << RI_ICR_IC2OS_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6072 #define RI_ICR_IC2OS_1 (0x2U << RI_ICR_IC2OS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6073 #define RI_ICR_IC2OS_2 (0x4U << RI_ICR_IC2OS_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6074 #define RI_ICR_IC2OS_3 (0x8U << RI_ICR_IC2OS_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6075
AnnaBridge 171:3a7713b1edbc 6076 #define RI_ICR_IC3OS_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6077 #define RI_ICR_IC3OS_Msk (0xFU << RI_ICR_IC3OS_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 6078 #define RI_ICR_IC3OS RI_ICR_IC3OS_Msk /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
AnnaBridge 171:3a7713b1edbc 6079 #define RI_ICR_IC3OS_0 (0x1U << RI_ICR_IC3OS_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6080 #define RI_ICR_IC3OS_1 (0x2U << RI_ICR_IC3OS_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6081 #define RI_ICR_IC3OS_2 (0x4U << RI_ICR_IC3OS_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6082 #define RI_ICR_IC3OS_3 (0x8U << RI_ICR_IC3OS_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6083
AnnaBridge 171:3a7713b1edbc 6084 #define RI_ICR_IC4OS_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6085 #define RI_ICR_IC4OS_Msk (0xFU << RI_ICR_IC4OS_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 6086 #define RI_ICR_IC4OS RI_ICR_IC4OS_Msk /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
AnnaBridge 171:3a7713b1edbc 6087 #define RI_ICR_IC4OS_0 (0x1U << RI_ICR_IC4OS_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6088 #define RI_ICR_IC4OS_1 (0x2U << RI_ICR_IC4OS_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6089 #define RI_ICR_IC4OS_2 (0x4U << RI_ICR_IC4OS_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6090 #define RI_ICR_IC4OS_3 (0x8U << RI_ICR_IC4OS_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6091
AnnaBridge 171:3a7713b1edbc 6092 #define RI_ICR_TIM_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6093 #define RI_ICR_TIM_Msk (0x3U << RI_ICR_TIM_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 6094 #define RI_ICR_TIM RI_ICR_TIM_Msk /*!< TIM[3:0] bits (Timers select bits) */
AnnaBridge 171:3a7713b1edbc 6095 #define RI_ICR_TIM_0 (0x1U << RI_ICR_TIM_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 6096 #define RI_ICR_TIM_1 (0x2U << RI_ICR_TIM_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 6097
AnnaBridge 171:3a7713b1edbc 6098 #define RI_ICR_IC1_Pos (18U)
AnnaBridge 171:3a7713b1edbc 6099 #define RI_ICR_IC1_Msk (0x1U << RI_ICR_IC1_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 6100 #define RI_ICR_IC1 RI_ICR_IC1_Msk /*!< Input capture 1 */
AnnaBridge 171:3a7713b1edbc 6101 #define RI_ICR_IC2_Pos (19U)
AnnaBridge 171:3a7713b1edbc 6102 #define RI_ICR_IC2_Msk (0x1U << RI_ICR_IC2_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 6103 #define RI_ICR_IC2 RI_ICR_IC2_Msk /*!< Input capture 2 */
AnnaBridge 171:3a7713b1edbc 6104 #define RI_ICR_IC3_Pos (20U)
AnnaBridge 171:3a7713b1edbc 6105 #define RI_ICR_IC3_Msk (0x1U << RI_ICR_IC3_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 6106 #define RI_ICR_IC3 RI_ICR_IC3_Msk /*!< Input capture 3 */
AnnaBridge 171:3a7713b1edbc 6107 #define RI_ICR_IC4_Pos (21U)
AnnaBridge 171:3a7713b1edbc 6108 #define RI_ICR_IC4_Msk (0x1U << RI_ICR_IC4_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 6109 #define RI_ICR_IC4 RI_ICR_IC4_Msk /*!< Input capture 4 */
AnnaBridge 171:3a7713b1edbc 6110
AnnaBridge 171:3a7713b1edbc 6111 /******************** Bit definition for RI_ASCR1 register ********************/
AnnaBridge 171:3a7713b1edbc 6112 #define RI_ASCR1_CH_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6113 #define RI_ASCR1_CH_Msk (0x7BFDFFFFU << RI_ASCR1_CH_Pos) /*!< 0x7BFDFFFF */
AnnaBridge 171:3a7713b1edbc 6114 #define RI_ASCR1_CH RI_ASCR1_CH_Msk /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
AnnaBridge 171:3a7713b1edbc 6115 #define RI_ASCR1_CH_0 (0x00000001U) /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 6116 #define RI_ASCR1_CH_1 (0x00000002U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 6117 #define RI_ASCR1_CH_2 (0x00000004U) /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 6118 #define RI_ASCR1_CH_3 (0x00000008U) /*!< Bit 3 */
AnnaBridge 171:3a7713b1edbc 6119 #define RI_ASCR1_CH_4 (0x00000010U) /*!< Bit 4 */
AnnaBridge 171:3a7713b1edbc 6120 #define RI_ASCR1_CH_5 (0x00000020U) /*!< Bit 5 */
AnnaBridge 171:3a7713b1edbc 6121 #define RI_ASCR1_CH_6 (0x00000040U) /*!< Bit 6 */
AnnaBridge 171:3a7713b1edbc 6122 #define RI_ASCR1_CH_7 (0x00000080U) /*!< Bit 7 */
AnnaBridge 171:3a7713b1edbc 6123 #define RI_ASCR1_CH_8 (0x00000100U) /*!< Bit 8 */
AnnaBridge 171:3a7713b1edbc 6124 #define RI_ASCR1_CH_9 (0x00000200U) /*!< Bit 9 */
AnnaBridge 171:3a7713b1edbc 6125 #define RI_ASCR1_CH_10 (0x00000400U) /*!< Bit 10 */
AnnaBridge 171:3a7713b1edbc 6126 #define RI_ASCR1_CH_11 (0x00000800U) /*!< Bit 11 */
AnnaBridge 171:3a7713b1edbc 6127 #define RI_ASCR1_CH_12 (0x00001000U) /*!< Bit 12 */
AnnaBridge 171:3a7713b1edbc 6128 #define RI_ASCR1_CH_13 (0x00002000U) /*!< Bit 13 */
AnnaBridge 171:3a7713b1edbc 6129 #define RI_ASCR1_CH_14 (0x00004000U) /*!< Bit 14 */
AnnaBridge 171:3a7713b1edbc 6130 #define RI_ASCR1_CH_15 (0x00008000U) /*!< Bit 15 */
AnnaBridge 171:3a7713b1edbc 6131 #define RI_ASCR1_CH_31 (0x00010000U) /*!< Bit 16 */
AnnaBridge 171:3a7713b1edbc 6132 #define RI_ASCR1_CH_18 (0x00040000U) /*!< Bit 18 */
AnnaBridge 171:3a7713b1edbc 6133 #define RI_ASCR1_CH_19 (0x00080000U) /*!< Bit 19 */
AnnaBridge 171:3a7713b1edbc 6134 #define RI_ASCR1_CH_20 (0x00100000U) /*!< Bit 20 */
AnnaBridge 171:3a7713b1edbc 6135 #define RI_ASCR1_CH_21 (0x00200000U) /*!< Bit 21 */
AnnaBridge 171:3a7713b1edbc 6136 #define RI_ASCR1_CH_22 (0x00400000U) /*!< Bit 22 */
AnnaBridge 171:3a7713b1edbc 6137 #define RI_ASCR1_CH_23 (0x00800000U) /*!< Bit 23 */
AnnaBridge 171:3a7713b1edbc 6138 #define RI_ASCR1_CH_24 (0x01000000U) /*!< Bit 24 */
AnnaBridge 171:3a7713b1edbc 6139 #define RI_ASCR1_CH_25 (0x02000000U) /*!< Bit 25 */
AnnaBridge 171:3a7713b1edbc 6140 #define RI_ASCR1_VCOMP_Pos (26U)
AnnaBridge 171:3a7713b1edbc 6141 #define RI_ASCR1_VCOMP_Msk (0x1U << RI_ASCR1_VCOMP_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 6142 #define RI_ASCR1_VCOMP RI_ASCR1_VCOMP_Msk /*!< ADC analog switch selection for internal node to COMP1 */
AnnaBridge 171:3a7713b1edbc 6143 #define RI_ASCR1_CH_27 (0x08000000U) /*!< Bit 27 */
AnnaBridge 171:3a7713b1edbc 6144 #define RI_ASCR1_CH_28 (0x10000000U) /*!< Bit 28 */
AnnaBridge 171:3a7713b1edbc 6145 #define RI_ASCR1_CH_29 (0x20000000U) /*!< Bit 29 */
AnnaBridge 171:3a7713b1edbc 6146 #define RI_ASCR1_CH_30 (0x40000000U) /*!< Bit 30 */
AnnaBridge 171:3a7713b1edbc 6147 #define RI_ASCR1_SCM_Pos (31U)
AnnaBridge 171:3a7713b1edbc 6148 #define RI_ASCR1_SCM_Msk (0x1U << RI_ASCR1_SCM_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 6149 #define RI_ASCR1_SCM RI_ASCR1_SCM_Msk /*!< I/O Switch control mode */
AnnaBridge 171:3a7713b1edbc 6150
AnnaBridge 171:3a7713b1edbc 6151 /******************** Bit definition for RI_ASCR2 register ********************/
AnnaBridge 171:3a7713b1edbc 6152 #define RI_ASCR2_GR10_1 (0x00000001U) /*!< GR10-1 selection bit */
AnnaBridge 171:3a7713b1edbc 6153 #define RI_ASCR2_GR10_2 (0x00000002U) /*!< GR10-2 selection bit */
AnnaBridge 171:3a7713b1edbc 6154 #define RI_ASCR2_GR10_3 (0x00000004U) /*!< GR10-3 selection bit */
AnnaBridge 171:3a7713b1edbc 6155 #define RI_ASCR2_GR10_4 (0x00000008U) /*!< GR10-4 selection bit */
AnnaBridge 171:3a7713b1edbc 6156 #define RI_ASCR2_GR6_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6157 #define RI_ASCR2_GR6_Msk (0x1800003U << RI_ASCR2_GR6_Pos) /*!< 0x18000030 */
AnnaBridge 171:3a7713b1edbc 6158 #define RI_ASCR2_GR6 RI_ASCR2_GR6_Msk /*!< GR6 selection bits */
AnnaBridge 171:3a7713b1edbc 6159 #define RI_ASCR2_GR6_1 (0x0000001U << RI_ASCR2_GR6_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6160 #define RI_ASCR2_GR6_2 (0x0000002U << RI_ASCR2_GR6_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6161 #define RI_ASCR2_GR6_3 (0x0800000U << RI_ASCR2_GR6_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 6162 #define RI_ASCR2_GR6_4 (0x1000000U << RI_ASCR2_GR6_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 6163 #define RI_ASCR2_GR5_1 (0x00000040U) /*!< GR5-1 selection bit */
AnnaBridge 171:3a7713b1edbc 6164 #define RI_ASCR2_GR5_2 (0x00000080U) /*!< GR5-2 selection bit */
AnnaBridge 171:3a7713b1edbc 6165 #define RI_ASCR2_GR5_3 (0x00000100U) /*!< GR5-3 selection bit */
AnnaBridge 171:3a7713b1edbc 6166 #define RI_ASCR2_GR4_1 (0x00000200U) /*!< GR4-1 selection bit */
AnnaBridge 171:3a7713b1edbc 6167 #define RI_ASCR2_GR4_2 (0x00000400U) /*!< GR4-2 selection bit */
AnnaBridge 171:3a7713b1edbc 6168 #define RI_ASCR2_GR4_3 (0x00000800U) /*!< GR4-3 selection bit */
AnnaBridge 171:3a7713b1edbc 6169 #define RI_ASCR2_GR4_4 (0x00008000U) /*!< GR4-4 selection bit */
AnnaBridge 171:3a7713b1edbc 6170 #define RI_ASCR2_CH0b_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6171 #define RI_ASCR2_CH0b_Msk (0x1U << RI_ASCR2_CH0b_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 6172 #define RI_ASCR2_CH0b RI_ASCR2_CH0b_Msk /*!< CH0b selection bit */
AnnaBridge 171:3a7713b1edbc 6173
AnnaBridge 171:3a7713b1edbc 6174 /******************** Bit definition for RI_HYSCR1 register ********************/
AnnaBridge 171:3a7713b1edbc 6175 #define RI_HYSCR1_PA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6176 #define RI_HYSCR1_PA_Msk (0xFFFFU << RI_HYSCR1_PA_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 6177 #define RI_HYSCR1_PA RI_HYSCR1_PA_Msk /*!< PA[15:0] Port A Hysteresis selection */
AnnaBridge 171:3a7713b1edbc 6178 #define RI_HYSCR1_PA_0 (0x0001U << RI_HYSCR1_PA_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6179 #define RI_HYSCR1_PA_1 (0x0002U << RI_HYSCR1_PA_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6180 #define RI_HYSCR1_PA_2 (0x0004U << RI_HYSCR1_PA_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6181 #define RI_HYSCR1_PA_3 (0x0008U << RI_HYSCR1_PA_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6182 #define RI_HYSCR1_PA_4 (0x0010U << RI_HYSCR1_PA_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6183 #define RI_HYSCR1_PA_5 (0x0020U << RI_HYSCR1_PA_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6184 #define RI_HYSCR1_PA_6 (0x0040U << RI_HYSCR1_PA_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6185 #define RI_HYSCR1_PA_7 (0x0080U << RI_HYSCR1_PA_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6186 #define RI_HYSCR1_PA_8 (0x0100U << RI_HYSCR1_PA_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6187 #define RI_HYSCR1_PA_9 (0x0200U << RI_HYSCR1_PA_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6188 #define RI_HYSCR1_PA_10 (0x0400U << RI_HYSCR1_PA_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6189 #define RI_HYSCR1_PA_11 (0x0800U << RI_HYSCR1_PA_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6190 #define RI_HYSCR1_PA_12 (0x1000U << RI_HYSCR1_PA_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6191 #define RI_HYSCR1_PA_13 (0x2000U << RI_HYSCR1_PA_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6192 #define RI_HYSCR1_PA_14 (0x4000U << RI_HYSCR1_PA_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6193 #define RI_HYSCR1_PA_15 (0x8000U << RI_HYSCR1_PA_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6194
AnnaBridge 171:3a7713b1edbc 6195 #define RI_HYSCR1_PB_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6196 #define RI_HYSCR1_PB_Msk (0xFFFFU << RI_HYSCR1_PB_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 6197 #define RI_HYSCR1_PB RI_HYSCR1_PB_Msk /*!< PB[15:0] Port B Hysteresis selection */
AnnaBridge 171:3a7713b1edbc 6198 #define RI_HYSCR1_PB_0 (0x0001U << RI_HYSCR1_PB_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 6199 #define RI_HYSCR1_PB_1 (0x0002U << RI_HYSCR1_PB_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 6200 #define RI_HYSCR1_PB_2 (0x0004U << RI_HYSCR1_PB_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 6201 #define RI_HYSCR1_PB_3 (0x0008U << RI_HYSCR1_PB_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 6202 #define RI_HYSCR1_PB_4 (0x0010U << RI_HYSCR1_PB_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 6203 #define RI_HYSCR1_PB_5 (0x0020U << RI_HYSCR1_PB_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 6204 #define RI_HYSCR1_PB_6 (0x0040U << RI_HYSCR1_PB_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 6205 #define RI_HYSCR1_PB_7 (0x0080U << RI_HYSCR1_PB_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 6206 #define RI_HYSCR1_PB_8 (0x0100U << RI_HYSCR1_PB_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 6207 #define RI_HYSCR1_PB_9 (0x0200U << RI_HYSCR1_PB_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 6208 #define RI_HYSCR1_PB_10 (0x0400U << RI_HYSCR1_PB_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 6209 #define RI_HYSCR1_PB_11 (0x0800U << RI_HYSCR1_PB_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 6210 #define RI_HYSCR1_PB_12 (0x1000U << RI_HYSCR1_PB_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 6211 #define RI_HYSCR1_PB_13 (0x2000U << RI_HYSCR1_PB_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 6212 #define RI_HYSCR1_PB_14 (0x4000U << RI_HYSCR1_PB_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 6213 #define RI_HYSCR1_PB_15 (0x8000U << RI_HYSCR1_PB_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 6214
AnnaBridge 171:3a7713b1edbc 6215 /******************** Bit definition for RI_HYSCR2 register ********************/
AnnaBridge 171:3a7713b1edbc 6216 #define RI_HYSCR2_PC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6217 #define RI_HYSCR2_PC_Msk (0xFFFFU << RI_HYSCR2_PC_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 6218 #define RI_HYSCR2_PC RI_HYSCR2_PC_Msk /*!< PC[15:0] Port C Hysteresis selection */
AnnaBridge 171:3a7713b1edbc 6219 #define RI_HYSCR2_PC_0 (0x0001U << RI_HYSCR2_PC_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6220 #define RI_HYSCR2_PC_1 (0x0002U << RI_HYSCR2_PC_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6221 #define RI_HYSCR2_PC_2 (0x0004U << RI_HYSCR2_PC_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6222 #define RI_HYSCR2_PC_3 (0x0008U << RI_HYSCR2_PC_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6223 #define RI_HYSCR2_PC_4 (0x0010U << RI_HYSCR2_PC_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6224 #define RI_HYSCR2_PC_5 (0x0020U << RI_HYSCR2_PC_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6225 #define RI_HYSCR2_PC_6 (0x0040U << RI_HYSCR2_PC_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6226 #define RI_HYSCR2_PC_7 (0x0080U << RI_HYSCR2_PC_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6227 #define RI_HYSCR2_PC_8 (0x0100U << RI_HYSCR2_PC_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6228 #define RI_HYSCR2_PC_9 (0x0200U << RI_HYSCR2_PC_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6229 #define RI_HYSCR2_PC_10 (0x0400U << RI_HYSCR2_PC_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6230 #define RI_HYSCR2_PC_11 (0x0800U << RI_HYSCR2_PC_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6231 #define RI_HYSCR2_PC_12 (0x1000U << RI_HYSCR2_PC_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6232 #define RI_HYSCR2_PC_13 (0x2000U << RI_HYSCR2_PC_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6233 #define RI_HYSCR2_PC_14 (0x4000U << RI_HYSCR2_PC_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6234 #define RI_HYSCR2_PC_15 (0x8000U << RI_HYSCR2_PC_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6235
AnnaBridge 171:3a7713b1edbc 6236 #define RI_HYSCR2_PD_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6237 #define RI_HYSCR2_PD_Msk (0xFFFFU << RI_HYSCR2_PD_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 6238 #define RI_HYSCR2_PD RI_HYSCR2_PD_Msk /*!< PD[15:0] Port D Hysteresis selection */
AnnaBridge 171:3a7713b1edbc 6239 #define RI_HYSCR2_PD_0 (0x0001U << RI_HYSCR2_PD_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 6240 #define RI_HYSCR2_PD_1 (0x0002U << RI_HYSCR2_PD_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 6241 #define RI_HYSCR2_PD_2 (0x0004U << RI_HYSCR2_PD_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 6242 #define RI_HYSCR2_PD_3 (0x0008U << RI_HYSCR2_PD_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 6243 #define RI_HYSCR2_PD_4 (0x0010U << RI_HYSCR2_PD_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 6244 #define RI_HYSCR2_PD_5 (0x0020U << RI_HYSCR2_PD_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 6245 #define RI_HYSCR2_PD_6 (0x0040U << RI_HYSCR2_PD_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 6246 #define RI_HYSCR2_PD_7 (0x0080U << RI_HYSCR2_PD_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 6247 #define RI_HYSCR2_PD_8 (0x0100U << RI_HYSCR2_PD_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 6248 #define RI_HYSCR2_PD_9 (0x0200U << RI_HYSCR2_PD_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 6249 #define RI_HYSCR2_PD_10 (0x0400U << RI_HYSCR2_PD_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 6250 #define RI_HYSCR2_PD_11 (0x0800U << RI_HYSCR2_PD_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 6251 #define RI_HYSCR2_PD_12 (0x1000U << RI_HYSCR2_PD_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 6252 #define RI_HYSCR2_PD_13 (0x2000U << RI_HYSCR2_PD_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 6253 #define RI_HYSCR2_PD_14 (0x4000U << RI_HYSCR2_PD_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 6254 #define RI_HYSCR2_PD_15 (0x8000U << RI_HYSCR2_PD_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 6255
AnnaBridge 171:3a7713b1edbc 6256 /******************** Bit definition for RI_HYSCR3 register ********************/
AnnaBridge 171:3a7713b1edbc 6257 #define RI_HYSCR3_PE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6258 #define RI_HYSCR3_PE_Msk (0xFFFFU << RI_HYSCR3_PE_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 6259 #define RI_HYSCR3_PE RI_HYSCR3_PE_Msk /*!< PE[15:0] Port E Hysteresis selection */
AnnaBridge 171:3a7713b1edbc 6260 #define RI_HYSCR3_PE_0 (0x0001U << RI_HYSCR3_PE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6261 #define RI_HYSCR3_PE_1 (0x0002U << RI_HYSCR3_PE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6262 #define RI_HYSCR3_PE_2 (0x0004U << RI_HYSCR3_PE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6263 #define RI_HYSCR3_PE_3 (0x0008U << RI_HYSCR3_PE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6264 #define RI_HYSCR3_PE_4 (0x0010U << RI_HYSCR3_PE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6265 #define RI_HYSCR3_PE_5 (0x0020U << RI_HYSCR3_PE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6266 #define RI_HYSCR3_PE_6 (0x0040U << RI_HYSCR3_PE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6267 #define RI_HYSCR3_PE_7 (0x0080U << RI_HYSCR3_PE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6268 #define RI_HYSCR3_PE_8 (0x0100U << RI_HYSCR3_PE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6269 #define RI_HYSCR3_PE_9 (0x0200U << RI_HYSCR3_PE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6270 #define RI_HYSCR3_PE_10 (0x0400U << RI_HYSCR3_PE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6271 #define RI_HYSCR3_PE_11 (0x0800U << RI_HYSCR3_PE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6272 #define RI_HYSCR3_PE_12 (0x1000U << RI_HYSCR3_PE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6273 #define RI_HYSCR3_PE_13 (0x2000U << RI_HYSCR3_PE_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6274 #define RI_HYSCR3_PE_14 (0x4000U << RI_HYSCR3_PE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6275 #define RI_HYSCR3_PE_15 (0x8000U << RI_HYSCR3_PE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6276 #define RI_HYSCR3_PF_Pos (16U)
AnnaBridge 171:3a7713b1edbc 6277 #define RI_HYSCR3_PF_Msk (0xFFFFU << RI_HYSCR3_PF_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 6278 #define RI_HYSCR3_PF RI_HYSCR3_PF_Msk /*!< PF[15:0] Port F Hysteresis selection */
AnnaBridge 171:3a7713b1edbc 6279 #define RI_HYSCR3_PF_0 (0x0001U << RI_HYSCR3_PF_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 6280 #define RI_HYSCR3_PF_1 (0x0002U << RI_HYSCR3_PF_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 6281 #define RI_HYSCR3_PF_2 (0x0004U << RI_HYSCR3_PF_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 6282 #define RI_HYSCR3_PF_3 (0x0008U << RI_HYSCR3_PF_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 6283 #define RI_HYSCR3_PF_4 (0x0010U << RI_HYSCR3_PF_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 6284 #define RI_HYSCR3_PF_5 (0x0020U << RI_HYSCR3_PF_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 6285 #define RI_HYSCR3_PF_6 (0x0040U << RI_HYSCR3_PF_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 6286 #define RI_HYSCR3_PF_7 (0x0080U << RI_HYSCR3_PF_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 6287 #define RI_HYSCR3_PF_8 (0x0100U << RI_HYSCR3_PF_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 6288 #define RI_HYSCR3_PF_9 (0x0200U << RI_HYSCR3_PF_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 6289 #define RI_HYSCR3_PF_10 (0x0400U << RI_HYSCR3_PF_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 6290 #define RI_HYSCR3_PF_11 (0x0800U << RI_HYSCR3_PF_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 6291 #define RI_HYSCR3_PF_12 (0x1000U << RI_HYSCR3_PF_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 6292 #define RI_HYSCR3_PF_13 (0x2000U << RI_HYSCR3_PF_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 6293 #define RI_HYSCR3_PF_14 (0x4000U << RI_HYSCR3_PF_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 6294 #define RI_HYSCR3_PF_15 (0x8000U << RI_HYSCR3_PF_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 6295 /******************** Bit definition for RI_HYSCR4 register ********************/
AnnaBridge 171:3a7713b1edbc 6296 #define RI_HYSCR4_PG_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6297 #define RI_HYSCR4_PG_Msk (0xFFFFU << RI_HYSCR4_PG_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 6298 #define RI_HYSCR4_PG RI_HYSCR4_PG_Msk /*!< PG[15:0] Port G Hysteresis selection */
AnnaBridge 171:3a7713b1edbc 6299 #define RI_HYSCR4_PG_0 (0x0001U << RI_HYSCR4_PG_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6300 #define RI_HYSCR4_PG_1 (0x0002U << RI_HYSCR4_PG_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6301 #define RI_HYSCR4_PG_2 (0x0004U << RI_HYSCR4_PG_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6302 #define RI_HYSCR4_PG_3 (0x0008U << RI_HYSCR4_PG_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6303 #define RI_HYSCR4_PG_4 (0x0010U << RI_HYSCR4_PG_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6304 #define RI_HYSCR4_PG_5 (0x0020U << RI_HYSCR4_PG_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6305 #define RI_HYSCR4_PG_6 (0x0040U << RI_HYSCR4_PG_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6306 #define RI_HYSCR4_PG_7 (0x0080U << RI_HYSCR4_PG_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6307 #define RI_HYSCR4_PG_8 (0x0100U << RI_HYSCR4_PG_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6308 #define RI_HYSCR4_PG_9 (0x0200U << RI_HYSCR4_PG_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6309 #define RI_HYSCR4_PG_10 (0x0400U << RI_HYSCR4_PG_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6310 #define RI_HYSCR4_PG_11 (0x0800U << RI_HYSCR4_PG_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6311 #define RI_HYSCR4_PG_12 (0x1000U << RI_HYSCR4_PG_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6312 #define RI_HYSCR4_PG_13 (0x2000U << RI_HYSCR4_PG_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6313 #define RI_HYSCR4_PG_14 (0x4000U << RI_HYSCR4_PG_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6314 #define RI_HYSCR4_PG_15 (0x8000U << RI_HYSCR4_PG_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6315
AnnaBridge 171:3a7713b1edbc 6316 /******************** Bit definition for RI_ASMR1 register ********************/
AnnaBridge 171:3a7713b1edbc 6317 #define RI_ASMR1_PA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6318 #define RI_ASMR1_PA_Msk (0xFFFFU << RI_ASMR1_PA_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 6319 #define RI_ASMR1_PA RI_ASMR1_PA_Msk /*!< PA[15:0] Port A selection*/
AnnaBridge 171:3a7713b1edbc 6320 #define RI_ASMR1_PA_0 (0x0001U << RI_ASMR1_PA_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6321 #define RI_ASMR1_PA_1 (0x0002U << RI_ASMR1_PA_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6322 #define RI_ASMR1_PA_2 (0x0004U << RI_ASMR1_PA_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6323 #define RI_ASMR1_PA_3 (0x0008U << RI_ASMR1_PA_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6324 #define RI_ASMR1_PA_4 (0x0010U << RI_ASMR1_PA_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6325 #define RI_ASMR1_PA_5 (0x0020U << RI_ASMR1_PA_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6326 #define RI_ASMR1_PA_6 (0x0040U << RI_ASMR1_PA_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6327 #define RI_ASMR1_PA_7 (0x0080U << RI_ASMR1_PA_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6328 #define RI_ASMR1_PA_8 (0x0100U << RI_ASMR1_PA_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6329 #define RI_ASMR1_PA_9 (0x0200U << RI_ASMR1_PA_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6330 #define RI_ASMR1_PA_10 (0x0400U << RI_ASMR1_PA_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6331 #define RI_ASMR1_PA_11 (0x0800U << RI_ASMR1_PA_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6332 #define RI_ASMR1_PA_12 (0x1000U << RI_ASMR1_PA_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6333 #define RI_ASMR1_PA_13 (0x2000U << RI_ASMR1_PA_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6334 #define RI_ASMR1_PA_14 (0x4000U << RI_ASMR1_PA_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6335 #define RI_ASMR1_PA_15 (0x8000U << RI_ASMR1_PA_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6336
AnnaBridge 171:3a7713b1edbc 6337 /******************** Bit definition for RI_CMR1 register ********************/
AnnaBridge 171:3a7713b1edbc 6338 #define RI_CMR1_PA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6339 #define RI_CMR1_PA_Msk (0xFFFFU << RI_CMR1_PA_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 6340 #define RI_CMR1_PA RI_CMR1_PA_Msk /*!< PA[15:0] Port A selection*/
AnnaBridge 171:3a7713b1edbc 6341 #define RI_CMR1_PA_0 (0x0001U << RI_CMR1_PA_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6342 #define RI_CMR1_PA_1 (0x0002U << RI_CMR1_PA_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6343 #define RI_CMR1_PA_2 (0x0004U << RI_CMR1_PA_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6344 #define RI_CMR1_PA_3 (0x0008U << RI_CMR1_PA_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6345 #define RI_CMR1_PA_4 (0x0010U << RI_CMR1_PA_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6346 #define RI_CMR1_PA_5 (0x0020U << RI_CMR1_PA_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6347 #define RI_CMR1_PA_6 (0x0040U << RI_CMR1_PA_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6348 #define RI_CMR1_PA_7 (0x0080U << RI_CMR1_PA_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6349 #define RI_CMR1_PA_8 (0x0100U << RI_CMR1_PA_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6350 #define RI_CMR1_PA_9 (0x0200U << RI_CMR1_PA_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6351 #define RI_CMR1_PA_10 (0x0400U << RI_CMR1_PA_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6352 #define RI_CMR1_PA_11 (0x0800U << RI_CMR1_PA_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6353 #define RI_CMR1_PA_12 (0x1000U << RI_CMR1_PA_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6354 #define RI_CMR1_PA_13 (0x2000U << RI_CMR1_PA_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6355 #define RI_CMR1_PA_14 (0x4000U << RI_CMR1_PA_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6356 #define RI_CMR1_PA_15 (0x8000U << RI_CMR1_PA_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6357
AnnaBridge 171:3a7713b1edbc 6358 /******************** Bit definition for RI_CICR1 register ********************/
AnnaBridge 171:3a7713b1edbc 6359 #define RI_CICR1_PA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6360 #define RI_CICR1_PA_Msk (0xFFFFU << RI_CICR1_PA_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 6361 #define RI_CICR1_PA RI_CICR1_PA_Msk /*!< PA[15:0] Port A selection*/
AnnaBridge 171:3a7713b1edbc 6362 #define RI_CICR1_PA_0 (0x0001U << RI_CICR1_PA_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6363 #define RI_CICR1_PA_1 (0x0002U << RI_CICR1_PA_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6364 #define RI_CICR1_PA_2 (0x0004U << RI_CICR1_PA_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6365 #define RI_CICR1_PA_3 (0x0008U << RI_CICR1_PA_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6366 #define RI_CICR1_PA_4 (0x0010U << RI_CICR1_PA_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6367 #define RI_CICR1_PA_5 (0x0020U << RI_CICR1_PA_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6368 #define RI_CICR1_PA_6 (0x0040U << RI_CICR1_PA_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6369 #define RI_CICR1_PA_7 (0x0080U << RI_CICR1_PA_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6370 #define RI_CICR1_PA_8 (0x0100U << RI_CICR1_PA_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6371 #define RI_CICR1_PA_9 (0x0200U << RI_CICR1_PA_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6372 #define RI_CICR1_PA_10 (0x0400U << RI_CICR1_PA_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6373 #define RI_CICR1_PA_11 (0x0800U << RI_CICR1_PA_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6374 #define RI_CICR1_PA_12 (0x1000U << RI_CICR1_PA_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6375 #define RI_CICR1_PA_13 (0x2000U << RI_CICR1_PA_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6376 #define RI_CICR1_PA_14 (0x4000U << RI_CICR1_PA_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6377 #define RI_CICR1_PA_15 (0x8000U << RI_CICR1_PA_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6378
AnnaBridge 171:3a7713b1edbc 6379 /******************** Bit definition for RI_ASMR2 register ********************/
AnnaBridge 171:3a7713b1edbc 6380 #define RI_ASMR2_PB_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6381 #define RI_ASMR2_PB_Msk (0xFFFFU << RI_ASMR2_PB_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 6382 #define RI_ASMR2_PB RI_ASMR2_PB_Msk /*!< PB[15:0] Port B selection */
AnnaBridge 171:3a7713b1edbc 6383 #define RI_ASMR2_PB_0 (0x0001U << RI_ASMR2_PB_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6384 #define RI_ASMR2_PB_1 (0x0002U << RI_ASMR2_PB_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6385 #define RI_ASMR2_PB_2 (0x0004U << RI_ASMR2_PB_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6386 #define RI_ASMR2_PB_3 (0x0008U << RI_ASMR2_PB_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6387 #define RI_ASMR2_PB_4 (0x0010U << RI_ASMR2_PB_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6388 #define RI_ASMR2_PB_5 (0x0020U << RI_ASMR2_PB_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6389 #define RI_ASMR2_PB_6 (0x0040U << RI_ASMR2_PB_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6390 #define RI_ASMR2_PB_7 (0x0080U << RI_ASMR2_PB_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6391 #define RI_ASMR2_PB_8 (0x0100U << RI_ASMR2_PB_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6392 #define RI_ASMR2_PB_9 (0x0200U << RI_ASMR2_PB_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6393 #define RI_ASMR2_PB_10 (0x0400U << RI_ASMR2_PB_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6394 #define RI_ASMR2_PB_11 (0x0800U << RI_ASMR2_PB_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6395 #define RI_ASMR2_PB_12 (0x1000U << RI_ASMR2_PB_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6396 #define RI_ASMR2_PB_13 (0x2000U << RI_ASMR2_PB_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6397 #define RI_ASMR2_PB_14 (0x4000U << RI_ASMR2_PB_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6398 #define RI_ASMR2_PB_15 (0x8000U << RI_ASMR2_PB_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6399
AnnaBridge 171:3a7713b1edbc 6400 /******************** Bit definition for RI_CMR2 register ********************/
AnnaBridge 171:3a7713b1edbc 6401 #define RI_CMR2_PB_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6402 #define RI_CMR2_PB_Msk (0xFFFFU << RI_CMR2_PB_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 6403 #define RI_CMR2_PB RI_CMR2_PB_Msk /*!< PB[15:0] Port B selection */
AnnaBridge 171:3a7713b1edbc 6404 #define RI_CMR2_PB_0 (0x0001U << RI_CMR2_PB_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6405 #define RI_CMR2_PB_1 (0x0002U << RI_CMR2_PB_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6406 #define RI_CMR2_PB_2 (0x0004U << RI_CMR2_PB_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6407 #define RI_CMR2_PB_3 (0x0008U << RI_CMR2_PB_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6408 #define RI_CMR2_PB_4 (0x0010U << RI_CMR2_PB_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6409 #define RI_CMR2_PB_5 (0x0020U << RI_CMR2_PB_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6410 #define RI_CMR2_PB_6 (0x0040U << RI_CMR2_PB_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6411 #define RI_CMR2_PB_7 (0x0080U << RI_CMR2_PB_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6412 #define RI_CMR2_PB_8 (0x0100U << RI_CMR2_PB_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6413 #define RI_CMR2_PB_9 (0x0200U << RI_CMR2_PB_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6414 #define RI_CMR2_PB_10 (0x0400U << RI_CMR2_PB_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6415 #define RI_CMR2_PB_11 (0x0800U << RI_CMR2_PB_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6416 #define RI_CMR2_PB_12 (0x1000U << RI_CMR2_PB_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6417 #define RI_CMR2_PB_13 (0x2000U << RI_CMR2_PB_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6418 #define RI_CMR2_PB_14 (0x4000U << RI_CMR2_PB_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6419 #define RI_CMR2_PB_15 (0x8000U << RI_CMR2_PB_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6420
AnnaBridge 171:3a7713b1edbc 6421 /******************** Bit definition for RI_CICR2 register ********************/
AnnaBridge 171:3a7713b1edbc 6422 #define RI_CICR2_PB_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6423 #define RI_CICR2_PB_Msk (0xFFFFU << RI_CICR2_PB_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 6424 #define RI_CICR2_PB RI_CICR2_PB_Msk /*!< PB[15:0] Port B selection */
AnnaBridge 171:3a7713b1edbc 6425 #define RI_CICR2_PB_0 (0x0001U << RI_CICR2_PB_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6426 #define RI_CICR2_PB_1 (0x0002U << RI_CICR2_PB_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6427 #define RI_CICR2_PB_2 (0x0004U << RI_CICR2_PB_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6428 #define RI_CICR2_PB_3 (0x0008U << RI_CICR2_PB_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6429 #define RI_CICR2_PB_4 (0x0010U << RI_CICR2_PB_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6430 #define RI_CICR2_PB_5 (0x0020U << RI_CICR2_PB_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6431 #define RI_CICR2_PB_6 (0x0040U << RI_CICR2_PB_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6432 #define RI_CICR2_PB_7 (0x0080U << RI_CICR2_PB_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6433 #define RI_CICR2_PB_8 (0x0100U << RI_CICR2_PB_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6434 #define RI_CICR2_PB_9 (0x0200U << RI_CICR2_PB_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6435 #define RI_CICR2_PB_10 (0x0400U << RI_CICR2_PB_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6436 #define RI_CICR2_PB_11 (0x0800U << RI_CICR2_PB_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6437 #define RI_CICR2_PB_12 (0x1000U << RI_CICR2_PB_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6438 #define RI_CICR2_PB_13 (0x2000U << RI_CICR2_PB_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6439 #define RI_CICR2_PB_14 (0x4000U << RI_CICR2_PB_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6440 #define RI_CICR2_PB_15 (0x8000U << RI_CICR2_PB_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6441
AnnaBridge 171:3a7713b1edbc 6442 /******************** Bit definition for RI_ASMR3 register ********************/
AnnaBridge 171:3a7713b1edbc 6443 #define RI_ASMR3_PC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6444 #define RI_ASMR3_PC_Msk (0xFFFFU << RI_ASMR3_PC_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 6445 #define RI_ASMR3_PC RI_ASMR3_PC_Msk /*!< PC[15:0] Port C selection */
AnnaBridge 171:3a7713b1edbc 6446 #define RI_ASMR3_PC_0 (0x0001U << RI_ASMR3_PC_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6447 #define RI_ASMR3_PC_1 (0x0002U << RI_ASMR3_PC_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6448 #define RI_ASMR3_PC_2 (0x0004U << RI_ASMR3_PC_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6449 #define RI_ASMR3_PC_3 (0x0008U << RI_ASMR3_PC_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6450 #define RI_ASMR3_PC_4 (0x0010U << RI_ASMR3_PC_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6451 #define RI_ASMR3_PC_5 (0x0020U << RI_ASMR3_PC_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6452 #define RI_ASMR3_PC_6 (0x0040U << RI_ASMR3_PC_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6453 #define RI_ASMR3_PC_7 (0x0080U << RI_ASMR3_PC_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6454 #define RI_ASMR3_PC_8 (0x0100U << RI_ASMR3_PC_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6455 #define RI_ASMR3_PC_9 (0x0200U << RI_ASMR3_PC_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6456 #define RI_ASMR3_PC_10 (0x0400U << RI_ASMR3_PC_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6457 #define RI_ASMR3_PC_11 (0x0800U << RI_ASMR3_PC_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6458 #define RI_ASMR3_PC_12 (0x1000U << RI_ASMR3_PC_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6459 #define RI_ASMR3_PC_13 (0x2000U << RI_ASMR3_PC_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6460 #define RI_ASMR3_PC_14 (0x4000U << RI_ASMR3_PC_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6461 #define RI_ASMR3_PC_15 (0x8000U << RI_ASMR3_PC_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6462
AnnaBridge 171:3a7713b1edbc 6463 /******************** Bit definition for RI_CMR3 register ********************/
AnnaBridge 171:3a7713b1edbc 6464 #define RI_CMR3_PC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6465 #define RI_CMR3_PC_Msk (0xFFFFU << RI_CMR3_PC_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 6466 #define RI_CMR3_PC RI_CMR3_PC_Msk /*!< PC[15:0] Port C selection */
AnnaBridge 171:3a7713b1edbc 6467 #define RI_CMR3_PC_0 (0x0001U << RI_CMR3_PC_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6468 #define RI_CMR3_PC_1 (0x0002U << RI_CMR3_PC_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6469 #define RI_CMR3_PC_2 (0x0004U << RI_CMR3_PC_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6470 #define RI_CMR3_PC_3 (0x0008U << RI_CMR3_PC_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6471 #define RI_CMR3_PC_4 (0x0010U << RI_CMR3_PC_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6472 #define RI_CMR3_PC_5 (0x0020U << RI_CMR3_PC_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6473 #define RI_CMR3_PC_6 (0x0040U << RI_CMR3_PC_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6474 #define RI_CMR3_PC_7 (0x0080U << RI_CMR3_PC_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6475 #define RI_CMR3_PC_8 (0x0100U << RI_CMR3_PC_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6476 #define RI_CMR3_PC_9 (0x0200U << RI_CMR3_PC_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6477 #define RI_CMR3_PC_10 (0x0400U << RI_CMR3_PC_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6478 #define RI_CMR3_PC_11 (0x0800U << RI_CMR3_PC_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6479 #define RI_CMR3_PC_12 (0x1000U << RI_CMR3_PC_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6480 #define RI_CMR3_PC_13 (0x2000U << RI_CMR3_PC_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6481 #define RI_CMR3_PC_14 (0x4000U << RI_CMR3_PC_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6482 #define RI_CMR3_PC_15 (0x8000U << RI_CMR3_PC_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6483
AnnaBridge 171:3a7713b1edbc 6484 /******************** Bit definition for RI_CICR3 register ********************/
AnnaBridge 171:3a7713b1edbc 6485 #define RI_CICR3_PC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6486 #define RI_CICR3_PC_Msk (0xFFFFU << RI_CICR3_PC_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 6487 #define RI_CICR3_PC RI_CICR3_PC_Msk /*!< PC[15:0] Port C selection */
AnnaBridge 171:3a7713b1edbc 6488 #define RI_CICR3_PC_0 (0x0001U << RI_CICR3_PC_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6489 #define RI_CICR3_PC_1 (0x0002U << RI_CICR3_PC_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6490 #define RI_CICR3_PC_2 (0x0004U << RI_CICR3_PC_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6491 #define RI_CICR3_PC_3 (0x0008U << RI_CICR3_PC_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6492 #define RI_CICR3_PC_4 (0x0010U << RI_CICR3_PC_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6493 #define RI_CICR3_PC_5 (0x0020U << RI_CICR3_PC_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6494 #define RI_CICR3_PC_6 (0x0040U << RI_CICR3_PC_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6495 #define RI_CICR3_PC_7 (0x0080U << RI_CICR3_PC_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6496 #define RI_CICR3_PC_8 (0x0100U << RI_CICR3_PC_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6497 #define RI_CICR3_PC_9 (0x0200U << RI_CICR3_PC_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6498 #define RI_CICR3_PC_10 (0x0400U << RI_CICR3_PC_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6499 #define RI_CICR3_PC_11 (0x0800U << RI_CICR3_PC_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6500 #define RI_CICR3_PC_12 (0x1000U << RI_CICR3_PC_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6501 #define RI_CICR3_PC_13 (0x2000U << RI_CICR3_PC_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6502 #define RI_CICR3_PC_14 (0x4000U << RI_CICR3_PC_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6503 #define RI_CICR3_PC_15 (0x8000U << RI_CICR3_PC_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6504
AnnaBridge 171:3a7713b1edbc 6505 /******************** Bit definition for RI_ASMR4 register ********************/
AnnaBridge 171:3a7713b1edbc 6506 #define RI_ASMR4_PF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6507 #define RI_ASMR4_PF_Msk (0xFFFFU << RI_ASMR4_PF_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 6508 #define RI_ASMR4_PF RI_ASMR4_PF_Msk /*!< PF[15:0] Port F selection */
AnnaBridge 171:3a7713b1edbc 6509 #define RI_ASMR4_PF_0 (0x0001U << RI_ASMR4_PF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6510 #define RI_ASMR4_PF_1 (0x0002U << RI_ASMR4_PF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6511 #define RI_ASMR4_PF_2 (0x0004U << RI_ASMR4_PF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6512 #define RI_ASMR4_PF_3 (0x0008U << RI_ASMR4_PF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6513 #define RI_ASMR4_PF_4 (0x0010U << RI_ASMR4_PF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6514 #define RI_ASMR4_PF_5 (0x0020U << RI_ASMR4_PF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6515 #define RI_ASMR4_PF_6 (0x0040U << RI_ASMR4_PF_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6516 #define RI_ASMR4_PF_7 (0x0080U << RI_ASMR4_PF_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6517 #define RI_ASMR4_PF_8 (0x0100U << RI_ASMR4_PF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6518 #define RI_ASMR4_PF_9 (0x0200U << RI_ASMR4_PF_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6519 #define RI_ASMR4_PF_10 (0x0400U << RI_ASMR4_PF_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6520 #define RI_ASMR4_PF_11 (0x0800U << RI_ASMR4_PF_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6521 #define RI_ASMR4_PF_12 (0x1000U << RI_ASMR4_PF_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6522 #define RI_ASMR4_PF_13 (0x2000U << RI_ASMR4_PF_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6523 #define RI_ASMR4_PF_14 (0x4000U << RI_ASMR4_PF_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6524 #define RI_ASMR4_PF_15 (0x8000U << RI_ASMR4_PF_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6525
AnnaBridge 171:3a7713b1edbc 6526 /******************** Bit definition for RI_CMR4 register ********************/
AnnaBridge 171:3a7713b1edbc 6527 #define RI_CMR4_PF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6528 #define RI_CMR4_PF_Msk (0xFFFFU << RI_CMR4_PF_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 6529 #define RI_CMR4_PF RI_CMR4_PF_Msk /*!< PF[15:0] Port F selection */
AnnaBridge 171:3a7713b1edbc 6530 #define RI_CMR4_PF_0 (0x0001U << RI_CMR4_PF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6531 #define RI_CMR4_PF_1 (0x0002U << RI_CMR4_PF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6532 #define RI_CMR4_PF_2 (0x0004U << RI_CMR4_PF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6533 #define RI_CMR4_PF_3 (0x0008U << RI_CMR4_PF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6534 #define RI_CMR4_PF_4 (0x0010U << RI_CMR4_PF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6535 #define RI_CMR4_PF_5 (0x0020U << RI_CMR4_PF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6536 #define RI_CMR4_PF_6 (0x0040U << RI_CMR4_PF_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6537 #define RI_CMR4_PF_7 (0x0080U << RI_CMR4_PF_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6538 #define RI_CMR4_PF_8 (0x0100U << RI_CMR4_PF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6539 #define RI_CMR4_PF_9 (0x0200U << RI_CMR4_PF_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6540 #define RI_CMR4_PF_10 (0x0400U << RI_CMR4_PF_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6541 #define RI_CMR4_PF_11 (0x0800U << RI_CMR4_PF_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6542 #define RI_CMR4_PF_12 (0x1000U << RI_CMR4_PF_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6543 #define RI_CMR4_PF_13 (0x2000U << RI_CMR4_PF_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6544 #define RI_CMR4_PF_14 (0x4000U << RI_CMR4_PF_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6545 #define RI_CMR4_PF_15 (0x8000U << RI_CMR4_PF_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6546
AnnaBridge 171:3a7713b1edbc 6547 /******************** Bit definition for RI_CICR4 register ********************/
AnnaBridge 171:3a7713b1edbc 6548 #define RI_CICR4_PF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6549 #define RI_CICR4_PF_Msk (0xFFFFU << RI_CICR4_PF_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 6550 #define RI_CICR4_PF RI_CICR4_PF_Msk /*!< PF[15:0] Port F selection */
AnnaBridge 171:3a7713b1edbc 6551 #define RI_CICR4_PF_0 (0x0001U << RI_CICR4_PF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6552 #define RI_CICR4_PF_1 (0x0002U << RI_CICR4_PF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6553 #define RI_CICR4_PF_2 (0x0004U << RI_CICR4_PF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6554 #define RI_CICR4_PF_3 (0x0008U << RI_CICR4_PF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6555 #define RI_CICR4_PF_4 (0x0010U << RI_CICR4_PF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6556 #define RI_CICR4_PF_5 (0x0020U << RI_CICR4_PF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6557 #define RI_CICR4_PF_6 (0x0040U << RI_CICR4_PF_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6558 #define RI_CICR4_PF_7 (0x0080U << RI_CICR4_PF_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6559 #define RI_CICR4_PF_8 (0x0100U << RI_CICR4_PF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6560 #define RI_CICR4_PF_9 (0x0200U << RI_CICR4_PF_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6561 #define RI_CICR4_PF_10 (0x0400U << RI_CICR4_PF_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6562 #define RI_CICR4_PF_11 (0x0800U << RI_CICR4_PF_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6563 #define RI_CICR4_PF_12 (0x1000U << RI_CICR4_PF_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6564 #define RI_CICR4_PF_13 (0x2000U << RI_CICR4_PF_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6565 #define RI_CICR4_PF_14 (0x4000U << RI_CICR4_PF_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6566 #define RI_CICR4_PF_15 (0x8000U << RI_CICR4_PF_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6567
AnnaBridge 171:3a7713b1edbc 6568 /******************** Bit definition for RI_ASMR5 register ********************/
AnnaBridge 171:3a7713b1edbc 6569 #define RI_ASMR5_PG_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6570 #define RI_ASMR5_PG_Msk (0xFFFFU << RI_ASMR5_PG_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 6571 #define RI_ASMR5_PG RI_ASMR5_PG_Msk /*!< PG[15:0] Port G selection */
AnnaBridge 171:3a7713b1edbc 6572 #define RI_ASMR5_PG_0 (0x0001U << RI_ASMR5_PG_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6573 #define RI_ASMR5_PG_1 (0x0002U << RI_ASMR5_PG_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6574 #define RI_ASMR5_PG_2 (0x0004U << RI_ASMR5_PG_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6575 #define RI_ASMR5_PG_3 (0x0008U << RI_ASMR5_PG_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6576 #define RI_ASMR5_PG_4 (0x0010U << RI_ASMR5_PG_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6577 #define RI_ASMR5_PG_5 (0x0020U << RI_ASMR5_PG_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6578 #define RI_ASMR5_PG_6 (0x0040U << RI_ASMR5_PG_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6579 #define RI_ASMR5_PG_7 (0x0080U << RI_ASMR5_PG_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6580 #define RI_ASMR5_PG_8 (0x0100U << RI_ASMR5_PG_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6581 #define RI_ASMR5_PG_9 (0x0200U << RI_ASMR5_PG_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6582 #define RI_ASMR5_PG_10 (0x0400U << RI_ASMR5_PG_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6583 #define RI_ASMR5_PG_11 (0x0800U << RI_ASMR5_PG_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6584 #define RI_ASMR5_PG_12 (0x1000U << RI_ASMR5_PG_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6585 #define RI_ASMR5_PG_13 (0x2000U << RI_ASMR5_PG_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6586 #define RI_ASMR5_PG_14 (0x4000U << RI_ASMR5_PG_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6587 #define RI_ASMR5_PG_15 (0x8000U << RI_ASMR5_PG_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6588
AnnaBridge 171:3a7713b1edbc 6589 /******************** Bit definition for RI_CMR5 register ********************/
AnnaBridge 171:3a7713b1edbc 6590 #define RI_CMR5_PG_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6591 #define RI_CMR5_PG_Msk (0xFFFFU << RI_CMR5_PG_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 6592 #define RI_CMR5_PG RI_CMR5_PG_Msk /*!< PG[15:0] Port G selection */
AnnaBridge 171:3a7713b1edbc 6593 #define RI_CMR5_PG_0 (0x0001U << RI_CMR5_PG_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6594 #define RI_CMR5_PG_1 (0x0002U << RI_CMR5_PG_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6595 #define RI_CMR5_PG_2 (0x0004U << RI_CMR5_PG_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6596 #define RI_CMR5_PG_3 (0x0008U << RI_CMR5_PG_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6597 #define RI_CMR5_PG_4 (0x0010U << RI_CMR5_PG_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6598 #define RI_CMR5_PG_5 (0x0020U << RI_CMR5_PG_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6599 #define RI_CMR5_PG_6 (0x0040U << RI_CMR5_PG_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6600 #define RI_CMR5_PG_7 (0x0080U << RI_CMR5_PG_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6601 #define RI_CMR5_PG_8 (0x0100U << RI_CMR5_PG_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6602 #define RI_CMR5_PG_9 (0x0200U << RI_CMR5_PG_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6603 #define RI_CMR5_PG_10 (0x0400U << RI_CMR5_PG_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6604 #define RI_CMR5_PG_11 (0x0800U << RI_CMR5_PG_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6605 #define RI_CMR5_PG_12 (0x1000U << RI_CMR5_PG_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6606 #define RI_CMR5_PG_13 (0x2000U << RI_CMR5_PG_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6607 #define RI_CMR5_PG_14 (0x4000U << RI_CMR5_PG_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6608 #define RI_CMR5_PG_15 (0x8000U << RI_CMR5_PG_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6609
AnnaBridge 171:3a7713b1edbc 6610 /******************** Bit definition for RI_CICR5 register ********************/
AnnaBridge 171:3a7713b1edbc 6611 #define RI_CICR5_PG_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6612 #define RI_CICR5_PG_Msk (0xFFFFU << RI_CICR5_PG_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 6613 #define RI_CICR5_PG RI_CICR5_PG_Msk /*!< PG[15:0] Port G selection */
AnnaBridge 171:3a7713b1edbc 6614 #define RI_CICR5_PG_0 (0x0001U << RI_CICR5_PG_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6615 #define RI_CICR5_PG_1 (0x0002U << RI_CICR5_PG_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6616 #define RI_CICR5_PG_2 (0x0004U << RI_CICR5_PG_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6617 #define RI_CICR5_PG_3 (0x0008U << RI_CICR5_PG_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6618 #define RI_CICR5_PG_4 (0x0010U << RI_CICR5_PG_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6619 #define RI_CICR5_PG_5 (0x0020U << RI_CICR5_PG_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6620 #define RI_CICR5_PG_6 (0x0040U << RI_CICR5_PG_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6621 #define RI_CICR5_PG_7 (0x0080U << RI_CICR5_PG_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6622 #define RI_CICR5_PG_8 (0x0100U << RI_CICR5_PG_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6623 #define RI_CICR5_PG_9 (0x0200U << RI_CICR5_PG_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6624 #define RI_CICR5_PG_10 (0x0400U << RI_CICR5_PG_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6625 #define RI_CICR5_PG_11 (0x0800U << RI_CICR5_PG_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6626 #define RI_CICR5_PG_12 (0x1000U << RI_CICR5_PG_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6627 #define RI_CICR5_PG_13 (0x2000U << RI_CICR5_PG_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6628 #define RI_CICR5_PG_14 (0x4000U << RI_CICR5_PG_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6629 #define RI_CICR5_PG_15 (0x8000U << RI_CICR5_PG_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6630
AnnaBridge 171:3a7713b1edbc 6631 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 6632 /* */
AnnaBridge 171:3a7713b1edbc 6633 /* Timers (TIM) */
AnnaBridge 171:3a7713b1edbc 6634 /* */
AnnaBridge 171:3a7713b1edbc 6635 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 6636
AnnaBridge 171:3a7713b1edbc 6637 /******************* Bit definition for TIM_CR1 register ********************/
AnnaBridge 171:3a7713b1edbc 6638 #define TIM_CR1_CEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6639 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6640 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
AnnaBridge 171:3a7713b1edbc 6641 #define TIM_CR1_UDIS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6642 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6643 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
AnnaBridge 171:3a7713b1edbc 6644 #define TIM_CR1_URS_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6645 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6646 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
AnnaBridge 171:3a7713b1edbc 6647 #define TIM_CR1_OPM_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6648 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6649 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
AnnaBridge 171:3a7713b1edbc 6650 #define TIM_CR1_DIR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6651 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6652 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
AnnaBridge 171:3a7713b1edbc 6653
AnnaBridge 171:3a7713b1edbc 6654 #define TIM_CR1_CMS_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6655 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
AnnaBridge 171:3a7713b1edbc 6656 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
AnnaBridge 171:3a7713b1edbc 6657 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6658 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6659
AnnaBridge 171:3a7713b1edbc 6660 #define TIM_CR1_ARPE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6661 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6662 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
AnnaBridge 171:3a7713b1edbc 6663
AnnaBridge 171:3a7713b1edbc 6664 #define TIM_CR1_CKD_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6665 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 6666 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
AnnaBridge 171:3a7713b1edbc 6667 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6668 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6669
AnnaBridge 171:3a7713b1edbc 6670 /******************* Bit definition for TIM_CR2 register ********************/
AnnaBridge 171:3a7713b1edbc 6671 #define TIM_CR2_CCDS_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6672 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6673 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
AnnaBridge 171:3a7713b1edbc 6674
AnnaBridge 171:3a7713b1edbc 6675 #define TIM_CR2_MMS_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6676 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 6677 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
AnnaBridge 171:3a7713b1edbc 6678 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6679 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6680 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6681
AnnaBridge 171:3a7713b1edbc 6682 #define TIM_CR2_TI1S_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6683 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6684 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
AnnaBridge 171:3a7713b1edbc 6685
AnnaBridge 171:3a7713b1edbc 6686 /******************* Bit definition for TIM_SMCR register *******************/
AnnaBridge 171:3a7713b1edbc 6687 #define TIM_SMCR_SMS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6688 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 6689 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
AnnaBridge 171:3a7713b1edbc 6690 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6691 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6692 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6693
AnnaBridge 171:3a7713b1edbc 6694 #define TIM_SMCR_OCCS_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6695 #define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6696 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
AnnaBridge 171:3a7713b1edbc 6697
AnnaBridge 171:3a7713b1edbc 6698 #define TIM_SMCR_TS_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6699 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 6700 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
AnnaBridge 171:3a7713b1edbc 6701 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6702 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6703 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6704
AnnaBridge 171:3a7713b1edbc 6705 #define TIM_SMCR_MSM_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6706 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6707 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
AnnaBridge 171:3a7713b1edbc 6708
AnnaBridge 171:3a7713b1edbc 6709 #define TIM_SMCR_ETF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6710 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 6711 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
AnnaBridge 171:3a7713b1edbc 6712 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6713 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6714 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6715 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6716
AnnaBridge 171:3a7713b1edbc 6717 #define TIM_SMCR_ETPS_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6718 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 6719 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
AnnaBridge 171:3a7713b1edbc 6720 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6721 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6722
AnnaBridge 171:3a7713b1edbc 6723 #define TIM_SMCR_ECE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 6724 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6725 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
AnnaBridge 171:3a7713b1edbc 6726 #define TIM_SMCR_ETP_Pos (15U)
AnnaBridge 171:3a7713b1edbc 6727 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6728 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
AnnaBridge 171:3a7713b1edbc 6729
AnnaBridge 171:3a7713b1edbc 6730 /******************* Bit definition for TIM_DIER register *******************/
AnnaBridge 171:3a7713b1edbc 6731 #define TIM_DIER_UIE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6732 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6733 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
AnnaBridge 171:3a7713b1edbc 6734 #define TIM_DIER_CC1IE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6735 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6736 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
AnnaBridge 171:3a7713b1edbc 6737 #define TIM_DIER_CC2IE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6738 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6739 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
AnnaBridge 171:3a7713b1edbc 6740 #define TIM_DIER_CC3IE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6741 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6742 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
AnnaBridge 171:3a7713b1edbc 6743 #define TIM_DIER_CC4IE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6744 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6745 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
AnnaBridge 171:3a7713b1edbc 6746 #define TIM_DIER_TIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6747 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6748 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
AnnaBridge 171:3a7713b1edbc 6749 #define TIM_DIER_UDE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6750 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6751 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
AnnaBridge 171:3a7713b1edbc 6752 #define TIM_DIER_CC1DE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6753 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6754 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
AnnaBridge 171:3a7713b1edbc 6755 #define TIM_DIER_CC2DE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6756 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6757 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
AnnaBridge 171:3a7713b1edbc 6758 #define TIM_DIER_CC3DE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6759 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6760 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
AnnaBridge 171:3a7713b1edbc 6761 #define TIM_DIER_CC4DE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6762 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6763 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
AnnaBridge 171:3a7713b1edbc 6764 #define TIM_DIER_COMDE ((uint16_t)0x2000U) /*!<COM DMA request enable */
AnnaBridge 171:3a7713b1edbc 6765 #define TIM_DIER_TDE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 6766 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6767 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
AnnaBridge 171:3a7713b1edbc 6768
AnnaBridge 171:3a7713b1edbc 6769 /******************** Bit definition for TIM_SR register ********************/
AnnaBridge 171:3a7713b1edbc 6770 #define TIM_SR_UIF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6771 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6772 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
AnnaBridge 171:3a7713b1edbc 6773 #define TIM_SR_CC1IF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6774 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6775 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
AnnaBridge 171:3a7713b1edbc 6776 #define TIM_SR_CC2IF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6777 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6778 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
AnnaBridge 171:3a7713b1edbc 6779 #define TIM_SR_CC3IF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6780 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6781 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
AnnaBridge 171:3a7713b1edbc 6782 #define TIM_SR_CC4IF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6783 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6784 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
AnnaBridge 171:3a7713b1edbc 6785 #define TIM_SR_TIF_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6786 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6787 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
AnnaBridge 171:3a7713b1edbc 6788 #define TIM_SR_CC1OF_Pos (9U)
AnnaBridge 171:3a7713b1edbc 6789 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6790 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
AnnaBridge 171:3a7713b1edbc 6791 #define TIM_SR_CC2OF_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6792 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6793 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
AnnaBridge 171:3a7713b1edbc 6794 #define TIM_SR_CC3OF_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6795 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6796 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
AnnaBridge 171:3a7713b1edbc 6797 #define TIM_SR_CC4OF_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6798 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6799 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
AnnaBridge 171:3a7713b1edbc 6800
AnnaBridge 171:3a7713b1edbc 6801 /******************* Bit definition for TIM_EGR register ********************/
AnnaBridge 171:3a7713b1edbc 6802 #define TIM_EGR_UG_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6803 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6804 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
AnnaBridge 171:3a7713b1edbc 6805 #define TIM_EGR_CC1G_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6806 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6807 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
AnnaBridge 171:3a7713b1edbc 6808 #define TIM_EGR_CC2G_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6809 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6810 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
AnnaBridge 171:3a7713b1edbc 6811 #define TIM_EGR_CC3G_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6812 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6813 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
AnnaBridge 171:3a7713b1edbc 6814 #define TIM_EGR_CC4G_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6815 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6816 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
AnnaBridge 171:3a7713b1edbc 6817 #define TIM_EGR_TG_Pos (6U)
AnnaBridge 171:3a7713b1edbc 6818 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6819 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
AnnaBridge 171:3a7713b1edbc 6820
AnnaBridge 171:3a7713b1edbc 6821 /****************** Bit definition for TIM_CCMR1 register *******************/
AnnaBridge 171:3a7713b1edbc 6822 #define TIM_CCMR1_CC1S_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6823 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 6824 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
AnnaBridge 171:3a7713b1edbc 6825 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6826 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6827
AnnaBridge 171:3a7713b1edbc 6828 #define TIM_CCMR1_OC1FE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6829 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6830 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
AnnaBridge 171:3a7713b1edbc 6831 #define TIM_CCMR1_OC1PE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6832 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6833 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
AnnaBridge 171:3a7713b1edbc 6834
AnnaBridge 171:3a7713b1edbc 6835 #define TIM_CCMR1_OC1M_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6836 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 6837 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
AnnaBridge 171:3a7713b1edbc 6838 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6839 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6840 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6841
AnnaBridge 171:3a7713b1edbc 6842 #define TIM_CCMR1_OC1CE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6843 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6844 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
AnnaBridge 171:3a7713b1edbc 6845
AnnaBridge 171:3a7713b1edbc 6846 #define TIM_CCMR1_CC2S_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6847 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 6848 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
AnnaBridge 171:3a7713b1edbc 6849 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6850 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6851
AnnaBridge 171:3a7713b1edbc 6852 #define TIM_CCMR1_OC2FE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6853 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6854 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
AnnaBridge 171:3a7713b1edbc 6855 #define TIM_CCMR1_OC2PE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6856 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6857 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
AnnaBridge 171:3a7713b1edbc 6858
AnnaBridge 171:3a7713b1edbc 6859 #define TIM_CCMR1_OC2M_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6860 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 6861 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
AnnaBridge 171:3a7713b1edbc 6862 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6863 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6864 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6865
AnnaBridge 171:3a7713b1edbc 6866 #define TIM_CCMR1_OC2CE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 6867 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6868 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
AnnaBridge 171:3a7713b1edbc 6869
AnnaBridge 171:3a7713b1edbc 6870 /*----------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 6871
AnnaBridge 171:3a7713b1edbc 6872 #define TIM_CCMR1_IC1PSC_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6873 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 6874 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
AnnaBridge 171:3a7713b1edbc 6875 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6876 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6877
AnnaBridge 171:3a7713b1edbc 6878 #define TIM_CCMR1_IC1F_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6879 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 6880 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
AnnaBridge 171:3a7713b1edbc 6881 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6882 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6883 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6884 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6885
AnnaBridge 171:3a7713b1edbc 6886 #define TIM_CCMR1_IC2PSC_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6887 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 6888 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
AnnaBridge 171:3a7713b1edbc 6889 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6890 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6891
AnnaBridge 171:3a7713b1edbc 6892 #define TIM_CCMR1_IC2F_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6893 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 6894 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
AnnaBridge 171:3a7713b1edbc 6895 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6896 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6897 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6898 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6899
AnnaBridge 171:3a7713b1edbc 6900 /****************** Bit definition for TIM_CCMR2 register *******************/
AnnaBridge 171:3a7713b1edbc 6901 #define TIM_CCMR2_CC3S_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6902 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 6903 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
AnnaBridge 171:3a7713b1edbc 6904 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6905 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6906
AnnaBridge 171:3a7713b1edbc 6907 #define TIM_CCMR2_OC3FE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6908 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6909 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
AnnaBridge 171:3a7713b1edbc 6910 #define TIM_CCMR2_OC3PE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6911 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6912 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
AnnaBridge 171:3a7713b1edbc 6913
AnnaBridge 171:3a7713b1edbc 6914 #define TIM_CCMR2_OC3M_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6915 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 6916 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
AnnaBridge 171:3a7713b1edbc 6917 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6918 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6919 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6920
AnnaBridge 171:3a7713b1edbc 6921 #define TIM_CCMR2_OC3CE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6922 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6923 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
AnnaBridge 171:3a7713b1edbc 6924
AnnaBridge 171:3a7713b1edbc 6925 #define TIM_CCMR2_CC4S_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6926 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 6927 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
AnnaBridge 171:3a7713b1edbc 6928 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 6929 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 6930
AnnaBridge 171:3a7713b1edbc 6931 #define TIM_CCMR2_OC4FE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6932 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6933 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
AnnaBridge 171:3a7713b1edbc 6934 #define TIM_CCMR2_OC4PE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 6935 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6936 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
AnnaBridge 171:3a7713b1edbc 6937
AnnaBridge 171:3a7713b1edbc 6938 #define TIM_CCMR2_OC4M_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6939 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 6940 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
AnnaBridge 171:3a7713b1edbc 6941 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6942 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6943 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6944
AnnaBridge 171:3a7713b1edbc 6945 #define TIM_CCMR2_OC4CE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 6946 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6947 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
AnnaBridge 171:3a7713b1edbc 6948
AnnaBridge 171:3a7713b1edbc 6949 /*----------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 6950
AnnaBridge 171:3a7713b1edbc 6951 #define TIM_CCMR2_IC3PSC_Pos (2U)
AnnaBridge 171:3a7713b1edbc 6952 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 6953 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
AnnaBridge 171:3a7713b1edbc 6954 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 6955 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6956
AnnaBridge 171:3a7713b1edbc 6957 #define TIM_CCMR2_IC3F_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6958 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 6959 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
AnnaBridge 171:3a7713b1edbc 6960 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6961 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6962 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 6963 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6964
AnnaBridge 171:3a7713b1edbc 6965 #define TIM_CCMR2_IC4PSC_Pos (10U)
AnnaBridge 171:3a7713b1edbc 6966 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 6967 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
AnnaBridge 171:3a7713b1edbc 6968 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 6969 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 6970
AnnaBridge 171:3a7713b1edbc 6971 #define TIM_CCMR2_IC4F_Pos (12U)
AnnaBridge 171:3a7713b1edbc 6972 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 6973 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
AnnaBridge 171:3a7713b1edbc 6974 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 6975 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 6976 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 6977 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 6978
AnnaBridge 171:3a7713b1edbc 6979 /******************* Bit definition for TIM_CCER register *******************/
AnnaBridge 171:3a7713b1edbc 6980 #define TIM_CCER_CC1E_Pos (0U)
AnnaBridge 171:3a7713b1edbc 6981 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 6982 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
AnnaBridge 171:3a7713b1edbc 6983 #define TIM_CCER_CC1P_Pos (1U)
AnnaBridge 171:3a7713b1edbc 6984 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 6985 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
AnnaBridge 171:3a7713b1edbc 6986 #define TIM_CCER_CC1NP_Pos (3U)
AnnaBridge 171:3a7713b1edbc 6987 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 6988 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
AnnaBridge 171:3a7713b1edbc 6989 #define TIM_CCER_CC2E_Pos (4U)
AnnaBridge 171:3a7713b1edbc 6990 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 6991 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
AnnaBridge 171:3a7713b1edbc 6992 #define TIM_CCER_CC2P_Pos (5U)
AnnaBridge 171:3a7713b1edbc 6993 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 6994 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
AnnaBridge 171:3a7713b1edbc 6995 #define TIM_CCER_CC2NP_Pos (7U)
AnnaBridge 171:3a7713b1edbc 6996 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 6997 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
AnnaBridge 171:3a7713b1edbc 6998 #define TIM_CCER_CC3E_Pos (8U)
AnnaBridge 171:3a7713b1edbc 6999 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7000 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
AnnaBridge 171:3a7713b1edbc 7001 #define TIM_CCER_CC3P_Pos (9U)
AnnaBridge 171:3a7713b1edbc 7002 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7003 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
AnnaBridge 171:3a7713b1edbc 7004 #define TIM_CCER_CC3NP_Pos (11U)
AnnaBridge 171:3a7713b1edbc 7005 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7006 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
AnnaBridge 171:3a7713b1edbc 7007 #define TIM_CCER_CC4E_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7008 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7009 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
AnnaBridge 171:3a7713b1edbc 7010 #define TIM_CCER_CC4P_Pos (13U)
AnnaBridge 171:3a7713b1edbc 7011 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7012 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
AnnaBridge 171:3a7713b1edbc 7013 #define TIM_CCER_CC4NP_Pos (15U)
AnnaBridge 171:3a7713b1edbc 7014 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7015 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
AnnaBridge 171:3a7713b1edbc 7016
AnnaBridge 171:3a7713b1edbc 7017 /******************* Bit definition for TIM_CNT register ********************/
AnnaBridge 171:3a7713b1edbc 7018 #define TIM_CNT_CNT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7019 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 7020 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
AnnaBridge 171:3a7713b1edbc 7021
AnnaBridge 171:3a7713b1edbc 7022 /******************* Bit definition for TIM_PSC register ********************/
AnnaBridge 171:3a7713b1edbc 7023 #define TIM_PSC_PSC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7024 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 7025 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
AnnaBridge 171:3a7713b1edbc 7026
AnnaBridge 171:3a7713b1edbc 7027 /******************* Bit definition for TIM_ARR register ********************/
AnnaBridge 171:3a7713b1edbc 7028 #define TIM_ARR_ARR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7029 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 7030 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
AnnaBridge 171:3a7713b1edbc 7031
AnnaBridge 171:3a7713b1edbc 7032 /******************* Bit definition for TIM_CCR1 register *******************/
AnnaBridge 171:3a7713b1edbc 7033 #define TIM_CCR1_CCR1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7034 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 7035 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
AnnaBridge 171:3a7713b1edbc 7036
AnnaBridge 171:3a7713b1edbc 7037 /******************* Bit definition for TIM_CCR2 register *******************/
AnnaBridge 171:3a7713b1edbc 7038 #define TIM_CCR2_CCR2_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7039 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 7040 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
AnnaBridge 171:3a7713b1edbc 7041
AnnaBridge 171:3a7713b1edbc 7042 /******************* Bit definition for TIM_CCR3 register *******************/
AnnaBridge 171:3a7713b1edbc 7043 #define TIM_CCR3_CCR3_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7044 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 7045 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
AnnaBridge 171:3a7713b1edbc 7046
AnnaBridge 171:3a7713b1edbc 7047 /******************* Bit definition for TIM_CCR4 register *******************/
AnnaBridge 171:3a7713b1edbc 7048 #define TIM_CCR4_CCR4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7049 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 7050 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
AnnaBridge 171:3a7713b1edbc 7051
AnnaBridge 171:3a7713b1edbc 7052 /******************* Bit definition for TIM_DCR register ********************/
AnnaBridge 171:3a7713b1edbc 7053 #define TIM_DCR_DBA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7054 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 7055 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
AnnaBridge 171:3a7713b1edbc 7056 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7057 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7058 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7059 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7060 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7061
AnnaBridge 171:3a7713b1edbc 7062 #define TIM_DCR_DBL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7063 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
AnnaBridge 171:3a7713b1edbc 7064 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
AnnaBridge 171:3a7713b1edbc 7065 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7066 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7067 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7068 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7069 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7070
AnnaBridge 171:3a7713b1edbc 7071 /******************* Bit definition for TIM_DMAR register *******************/
AnnaBridge 171:3a7713b1edbc 7072 #define TIM_DMAR_DMAB_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7073 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 7074 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
AnnaBridge 171:3a7713b1edbc 7075
AnnaBridge 171:3a7713b1edbc 7076 /******************* Bit definition for TIM_OR register *********************/
AnnaBridge 171:3a7713b1edbc 7077 #define TIM_OR_TI1RMP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7078 #define TIM_OR_TI1RMP_Msk (0x3U << TIM_OR_TI1RMP_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 7079 #define TIM_OR_TI1RMP TIM_OR_TI1RMP_Msk /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
AnnaBridge 171:3a7713b1edbc 7080 #define TIM_OR_TI1RMP_0 (0x1U << TIM_OR_TI1RMP_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7081 #define TIM_OR_TI1RMP_1 (0x2U << TIM_OR_TI1RMP_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7082
AnnaBridge 171:3a7713b1edbc 7083 #define TIM_OR_ETR_RMP_Pos (2U)
AnnaBridge 171:3a7713b1edbc 7084 #define TIM_OR_ETR_RMP_Msk (0x1U << TIM_OR_ETR_RMP_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7085 #define TIM_OR_ETR_RMP TIM_OR_ETR_RMP_Msk /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
AnnaBridge 171:3a7713b1edbc 7086 #define TIM_OR_TI1_RMP_RI_Pos (3U)
AnnaBridge 171:3a7713b1edbc 7087 #define TIM_OR_TI1_RMP_RI_Msk (0x1U << TIM_OR_TI1_RMP_RI_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7088 #define TIM_OR_TI1_RMP_RI TIM_OR_TI1_RMP_RI_Msk /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
AnnaBridge 171:3a7713b1edbc 7089
AnnaBridge 171:3a7713b1edbc 7090 /*----------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 7091 #define TIM9_OR_ITR1_RMP_Pos (2U)
AnnaBridge 171:3a7713b1edbc 7092 #define TIM9_OR_ITR1_RMP_Msk (0x1U << TIM9_OR_ITR1_RMP_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7093 #define TIM9_OR_ITR1_RMP TIM9_OR_ITR1_RMP_Msk /*!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) */
AnnaBridge 171:3a7713b1edbc 7094
AnnaBridge 171:3a7713b1edbc 7095 /*----------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 7096 #define TIM2_OR_ITR1_RMP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7097 #define TIM2_OR_ITR1_RMP_Msk (0x1U << TIM2_OR_ITR1_RMP_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7098 #define TIM2_OR_ITR1_RMP TIM2_OR_ITR1_RMP_Msk /*!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) */
AnnaBridge 171:3a7713b1edbc 7099
AnnaBridge 171:3a7713b1edbc 7100 /*----------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 7101 #define TIM3_OR_ITR2_RMP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7102 #define TIM3_OR_ITR2_RMP_Msk (0x1U << TIM3_OR_ITR2_RMP_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7103 #define TIM3_OR_ITR2_RMP TIM3_OR_ITR2_RMP_Msk /*!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) */
AnnaBridge 171:3a7713b1edbc 7104
AnnaBridge 171:3a7713b1edbc 7105 /*----------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 7106
AnnaBridge 171:3a7713b1edbc 7107 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 7108 /* */
AnnaBridge 171:3a7713b1edbc 7109 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
AnnaBridge 171:3a7713b1edbc 7110 /* */
AnnaBridge 171:3a7713b1edbc 7111 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 7112
AnnaBridge 171:3a7713b1edbc 7113 /******************* Bit definition for USART_SR register *******************/
AnnaBridge 171:3a7713b1edbc 7114 #define USART_SR_PE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7115 #define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7116 #define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */
AnnaBridge 171:3a7713b1edbc 7117 #define USART_SR_FE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 7118 #define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7119 #define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */
AnnaBridge 171:3a7713b1edbc 7120 #define USART_SR_NE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 7121 #define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7122 #define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */
AnnaBridge 171:3a7713b1edbc 7123 #define USART_SR_ORE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 7124 #define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7125 #define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */
AnnaBridge 171:3a7713b1edbc 7126 #define USART_SR_IDLE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7127 #define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7128 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */
AnnaBridge 171:3a7713b1edbc 7129 #define USART_SR_RXNE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 7130 #define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7131 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */
AnnaBridge 171:3a7713b1edbc 7132 #define USART_SR_TC_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7133 #define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7134 #define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */
AnnaBridge 171:3a7713b1edbc 7135 #define USART_SR_TXE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 7136 #define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7137 #define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */
AnnaBridge 171:3a7713b1edbc 7138 #define USART_SR_LBD_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7139 #define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7140 #define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */
AnnaBridge 171:3a7713b1edbc 7141 #define USART_SR_CTS_Pos (9U)
AnnaBridge 171:3a7713b1edbc 7142 #define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7143 #define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */
AnnaBridge 171:3a7713b1edbc 7144
AnnaBridge 171:3a7713b1edbc 7145 /******************* Bit definition for USART_DR register *******************/
AnnaBridge 171:3a7713b1edbc 7146 #define USART_DR_DR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7147 #define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
AnnaBridge 171:3a7713b1edbc 7148 #define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
AnnaBridge 171:3a7713b1edbc 7149
AnnaBridge 171:3a7713b1edbc 7150 /****************** Bit definition for USART_BRR register *******************/
AnnaBridge 171:3a7713b1edbc 7151 #define USART_BRR_DIV_FRACTION_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7152 #define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 7153 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
AnnaBridge 171:3a7713b1edbc 7154 #define USART_BRR_DIV_MANTISSA_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7155 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
AnnaBridge 171:3a7713b1edbc 7156 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
AnnaBridge 171:3a7713b1edbc 7157
AnnaBridge 171:3a7713b1edbc 7158 /****************** Bit definition for USART_CR1 register *******************/
AnnaBridge 171:3a7713b1edbc 7159 #define USART_CR1_SBK_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7160 #define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7161 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */
AnnaBridge 171:3a7713b1edbc 7162 #define USART_CR1_RWU_Pos (1U)
AnnaBridge 171:3a7713b1edbc 7163 #define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7164 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */
AnnaBridge 171:3a7713b1edbc 7165 #define USART_CR1_RE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 7166 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7167 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
AnnaBridge 171:3a7713b1edbc 7168 #define USART_CR1_TE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 7169 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7170 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
AnnaBridge 171:3a7713b1edbc 7171 #define USART_CR1_IDLEIE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7172 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7173 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 7174 #define USART_CR1_RXNEIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 7175 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7176 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 7177 #define USART_CR1_TCIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7178 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7179 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 7180 #define USART_CR1_TXEIE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 7181 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7182 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 7183 #define USART_CR1_PEIE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7184 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7185 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 7186 #define USART_CR1_PS_Pos (9U)
AnnaBridge 171:3a7713b1edbc 7187 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7188 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
AnnaBridge 171:3a7713b1edbc 7189 #define USART_CR1_PCE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 7190 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7191 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
AnnaBridge 171:3a7713b1edbc 7192 #define USART_CR1_WAKE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 7193 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7194 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */
AnnaBridge 171:3a7713b1edbc 7195 #define USART_CR1_M_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7196 #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7197 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
AnnaBridge 171:3a7713b1edbc 7198 #define USART_CR1_UE_Pos (13U)
AnnaBridge 171:3a7713b1edbc 7199 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7200 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
AnnaBridge 171:3a7713b1edbc 7201 #define USART_CR1_OVER8_Pos (15U)
AnnaBridge 171:3a7713b1edbc 7202 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7203 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit mode */
AnnaBridge 171:3a7713b1edbc 7204
AnnaBridge 171:3a7713b1edbc 7205 /****************** Bit definition for USART_CR2 register *******************/
AnnaBridge 171:3a7713b1edbc 7206 #define USART_CR2_ADD_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7207 #define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 7208 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
AnnaBridge 171:3a7713b1edbc 7209 #define USART_CR2_LBDL_Pos (5U)
AnnaBridge 171:3a7713b1edbc 7210 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7211 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
AnnaBridge 171:3a7713b1edbc 7212 #define USART_CR2_LBDIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7213 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7214 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 7215 #define USART_CR2_LBCL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7216 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7217 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
AnnaBridge 171:3a7713b1edbc 7218 #define USART_CR2_CPHA_Pos (9U)
AnnaBridge 171:3a7713b1edbc 7219 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7220 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
AnnaBridge 171:3a7713b1edbc 7221 #define USART_CR2_CPOL_Pos (10U)
AnnaBridge 171:3a7713b1edbc 7222 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7223 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
AnnaBridge 171:3a7713b1edbc 7224 #define USART_CR2_CLKEN_Pos (11U)
AnnaBridge 171:3a7713b1edbc 7225 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7226 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
AnnaBridge 171:3a7713b1edbc 7227
AnnaBridge 171:3a7713b1edbc 7228 #define USART_CR2_STOP_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7229 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 7230 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
AnnaBridge 171:3a7713b1edbc 7231 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7232 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7233
AnnaBridge 171:3a7713b1edbc 7234 #define USART_CR2_LINEN_Pos (14U)
AnnaBridge 171:3a7713b1edbc 7235 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7236 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
AnnaBridge 171:3a7713b1edbc 7237
AnnaBridge 171:3a7713b1edbc 7238 /****************** Bit definition for USART_CR3 register *******************/
AnnaBridge 171:3a7713b1edbc 7239 #define USART_CR3_EIE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7240 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7241 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 7242 #define USART_CR3_IREN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 7243 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7244 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
AnnaBridge 171:3a7713b1edbc 7245 #define USART_CR3_IRLP_Pos (2U)
AnnaBridge 171:3a7713b1edbc 7246 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7247 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
AnnaBridge 171:3a7713b1edbc 7248 #define USART_CR3_HDSEL_Pos (3U)
AnnaBridge 171:3a7713b1edbc 7249 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7250 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
AnnaBridge 171:3a7713b1edbc 7251 #define USART_CR3_NACK_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7252 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7253 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */
AnnaBridge 171:3a7713b1edbc 7254 #define USART_CR3_SCEN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 7255 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7256 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */
AnnaBridge 171:3a7713b1edbc 7257 #define USART_CR3_DMAR_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7258 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7259 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
AnnaBridge 171:3a7713b1edbc 7260 #define USART_CR3_DMAT_Pos (7U)
AnnaBridge 171:3a7713b1edbc 7261 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7262 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
AnnaBridge 171:3a7713b1edbc 7263 #define USART_CR3_RTSE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7264 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7265 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
AnnaBridge 171:3a7713b1edbc 7266 #define USART_CR3_CTSE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 7267 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7268 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
AnnaBridge 171:3a7713b1edbc 7269 #define USART_CR3_CTSIE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 7270 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7271 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 7272 #define USART_CR3_ONEBIT_Pos (11U)
AnnaBridge 171:3a7713b1edbc 7273 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7274 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
AnnaBridge 171:3a7713b1edbc 7275
AnnaBridge 171:3a7713b1edbc 7276 /****************** Bit definition for USART_GTPR register ******************/
AnnaBridge 171:3a7713b1edbc 7277 #define USART_GTPR_PSC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7278 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 7279 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
AnnaBridge 171:3a7713b1edbc 7280 #define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7281 #define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7282 #define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7283 #define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7284 #define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7285 #define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7286 #define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7287 #define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7288
AnnaBridge 171:3a7713b1edbc 7289 #define USART_GTPR_GT_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7290 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 7291 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */
AnnaBridge 171:3a7713b1edbc 7292
AnnaBridge 171:3a7713b1edbc 7293 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 7294 /* */
AnnaBridge 171:3a7713b1edbc 7295 /* Universal Serial Bus (USB) */
AnnaBridge 171:3a7713b1edbc 7296 /* */
AnnaBridge 171:3a7713b1edbc 7297 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 7298
AnnaBridge 171:3a7713b1edbc 7299 /*!<Endpoint-specific registers */
AnnaBridge 171:3a7713b1edbc 7300
AnnaBridge 171:3a7713b1edbc 7301 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
AnnaBridge 171:3a7713b1edbc 7302 #define USB_EP1R (USB_BASE + 0x00000004U) /*!< endpoint 1 register address */
AnnaBridge 171:3a7713b1edbc 7303 #define USB_EP2R (USB_BASE + 0x00000008U) /*!< endpoint 2 register address */
AnnaBridge 171:3a7713b1edbc 7304 #define USB_EP3R (USB_BASE + 0x0000000CU) /*!< endpoint 3 register address */
AnnaBridge 171:3a7713b1edbc 7305 #define USB_EP4R (USB_BASE + 0x00000010U) /*!< endpoint 4 register address */
AnnaBridge 171:3a7713b1edbc 7306 #define USB_EP5R (USB_BASE + 0x00000014U) /*!< endpoint 5 register address */
AnnaBridge 171:3a7713b1edbc 7307 #define USB_EP6R (USB_BASE + 0x00000018U) /*!< endpoint 6 register address */
AnnaBridge 171:3a7713b1edbc 7308 #define USB_EP7R (USB_BASE + 0x0000001CU) /*!< endpoint 7 register address */
AnnaBridge 171:3a7713b1edbc 7309
AnnaBridge 171:3a7713b1edbc 7310 /* bit positions */
AnnaBridge 171:3a7713b1edbc 7311 #define USB_EP_CTR_RX_Pos (15U)
AnnaBridge 171:3a7713b1edbc 7312 #define USB_EP_CTR_RX_Msk (0x1U << USB_EP_CTR_RX_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7313 #define USB_EP_CTR_RX USB_EP_CTR_RX_Msk /*!< EndPoint Correct TRansfer RX */
AnnaBridge 171:3a7713b1edbc 7314 #define USB_EP_DTOG_RX_Pos (14U)
AnnaBridge 171:3a7713b1edbc 7315 #define USB_EP_DTOG_RX_Msk (0x1U << USB_EP_DTOG_RX_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7316 #define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk /*!< EndPoint Data TOGGLE RX */
AnnaBridge 171:3a7713b1edbc 7317 #define USB_EPRX_STAT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7318 #define USB_EPRX_STAT_Msk (0x3U << USB_EPRX_STAT_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 7319 #define USB_EPRX_STAT USB_EPRX_STAT_Msk /*!< EndPoint RX STATus bit field */
AnnaBridge 171:3a7713b1edbc 7320 #define USB_EP_SETUP_Pos (11U)
AnnaBridge 171:3a7713b1edbc 7321 #define USB_EP_SETUP_Msk (0x1U << USB_EP_SETUP_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7322 #define USB_EP_SETUP USB_EP_SETUP_Msk /*!< EndPoint SETUP */
AnnaBridge 171:3a7713b1edbc 7323 #define USB_EP_T_FIELD_Pos (9U)
AnnaBridge 171:3a7713b1edbc 7324 #define USB_EP_T_FIELD_Msk (0x3U << USB_EP_T_FIELD_Pos) /*!< 0x00000600 */
AnnaBridge 171:3a7713b1edbc 7325 #define USB_EP_T_FIELD USB_EP_T_FIELD_Msk /*!< EndPoint TYPE */
AnnaBridge 171:3a7713b1edbc 7326 #define USB_EP_KIND_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7327 #define USB_EP_KIND_Msk (0x1U << USB_EP_KIND_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7328 #define USB_EP_KIND USB_EP_KIND_Msk /*!< EndPoint KIND */
AnnaBridge 171:3a7713b1edbc 7329 #define USB_EP_CTR_TX_Pos (7U)
AnnaBridge 171:3a7713b1edbc 7330 #define USB_EP_CTR_TX_Msk (0x1U << USB_EP_CTR_TX_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7331 #define USB_EP_CTR_TX USB_EP_CTR_TX_Msk /*!< EndPoint Correct TRansfer TX */
AnnaBridge 171:3a7713b1edbc 7332 #define USB_EP_DTOG_TX_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7333 #define USB_EP_DTOG_TX_Msk (0x1U << USB_EP_DTOG_TX_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7334 #define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk /*!< EndPoint Data TOGGLE TX */
AnnaBridge 171:3a7713b1edbc 7335 #define USB_EPTX_STAT_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7336 #define USB_EPTX_STAT_Msk (0x3U << USB_EPTX_STAT_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 7337 #define USB_EPTX_STAT USB_EPTX_STAT_Msk /*!< EndPoint TX STATus bit field */
AnnaBridge 171:3a7713b1edbc 7338 #define USB_EPADDR_FIELD_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7339 #define USB_EPADDR_FIELD_Msk (0xFU << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 7340 #define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /*!< EndPoint ADDRess FIELD */
AnnaBridge 171:3a7713b1edbc 7341
AnnaBridge 171:3a7713b1edbc 7342 /* EndPoint REGister MASK (no toggle fields) */
AnnaBridge 171:3a7713b1edbc 7343 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
AnnaBridge 171:3a7713b1edbc 7344 /*!< EP_TYPE[1:0] EndPoint TYPE */
AnnaBridge 171:3a7713b1edbc 7345 #define USB_EP_TYPE_MASK_Pos (9U)
AnnaBridge 171:3a7713b1edbc 7346 #define USB_EP_TYPE_MASK_Msk (0x3U << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */
AnnaBridge 171:3a7713b1edbc 7347 #define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */
AnnaBridge 171:3a7713b1edbc 7348 #define USB_EP_BULK (0x00000000U) /*!< EndPoint BULK */
AnnaBridge 171:3a7713b1edbc 7349 #define USB_EP_CONTROL (0x00000200U) /*!< EndPoint CONTROL */
AnnaBridge 171:3a7713b1edbc 7350 #define USB_EP_ISOCHRONOUS (0x00000400U) /*!< EndPoint ISOCHRONOUS */
AnnaBridge 171:3a7713b1edbc 7351 #define USB_EP_INTERRUPT (0x00000600U) /*!< EndPoint INTERRUPT */
AnnaBridge 171:3a7713b1edbc 7352 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
AnnaBridge 171:3a7713b1edbc 7353
AnnaBridge 171:3a7713b1edbc 7354 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
AnnaBridge 171:3a7713b1edbc 7355 /*!< STAT_TX[1:0] STATus for TX transfer */
AnnaBridge 171:3a7713b1edbc 7356 #define USB_EP_TX_DIS (0x00000000U) /*!< EndPoint TX DISabled */
AnnaBridge 171:3a7713b1edbc 7357 #define USB_EP_TX_STALL (0x00000010U) /*!< EndPoint TX STALLed */
AnnaBridge 171:3a7713b1edbc 7358 #define USB_EP_TX_NAK (0x00000020U) /*!< EndPoint TX NAKed */
AnnaBridge 171:3a7713b1edbc 7359 #define USB_EP_TX_VALID (0x00000030U) /*!< EndPoint TX VALID */
AnnaBridge 171:3a7713b1edbc 7360 #define USB_EPTX_DTOG1 (0x00000010U) /*!< EndPoint TX Data TOGgle bit1 */
AnnaBridge 171:3a7713b1edbc 7361 #define USB_EPTX_DTOG2 (0x00000020U) /*!< EndPoint TX Data TOGgle bit2 */
AnnaBridge 171:3a7713b1edbc 7362 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
AnnaBridge 171:3a7713b1edbc 7363 /*!< STAT_RX[1:0] STATus for RX transfer */
AnnaBridge 171:3a7713b1edbc 7364 #define USB_EP_RX_DIS (0x00000000U) /*!< EndPoint RX DISabled */
AnnaBridge 171:3a7713b1edbc 7365 #define USB_EP_RX_STALL (0x00001000U) /*!< EndPoint RX STALLed */
AnnaBridge 171:3a7713b1edbc 7366 #define USB_EP_RX_NAK (0x00002000U) /*!< EndPoint RX NAKed */
AnnaBridge 171:3a7713b1edbc 7367 #define USB_EP_RX_VALID (0x00003000U) /*!< EndPoint RX VALID */
AnnaBridge 171:3a7713b1edbc 7368 #define USB_EPRX_DTOG1 (0x00001000U) /*!< EndPoint RX Data TOGgle bit1 */
AnnaBridge 171:3a7713b1edbc 7369 #define USB_EPRX_DTOG2 (0x00002000U) /*!< EndPoint RX Data TOGgle bit1 */
AnnaBridge 171:3a7713b1edbc 7370 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
AnnaBridge 171:3a7713b1edbc 7371
AnnaBridge 171:3a7713b1edbc 7372 /******************* Bit definition for USB_EP0R register *******************/
AnnaBridge 171:3a7713b1edbc 7373 #define USB_EP0R_EA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7374 #define USB_EP0R_EA_Msk (0xFU << USB_EP0R_EA_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 7375 #define USB_EP0R_EA USB_EP0R_EA_Msk /*!<Endpoint Address */
AnnaBridge 171:3a7713b1edbc 7376
AnnaBridge 171:3a7713b1edbc 7377 #define USB_EP0R_STAT_TX_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7378 #define USB_EP0R_STAT_TX_Msk (0x3U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 7379 #define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
AnnaBridge 171:3a7713b1edbc 7380 #define USB_EP0R_STAT_TX_0 (0x1U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7381 #define USB_EP0R_STAT_TX_1 (0x2U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7382
AnnaBridge 171:3a7713b1edbc 7383 #define USB_EP0R_DTOG_TX_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7384 #define USB_EP0R_DTOG_TX_Msk (0x1U << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7385 #define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */
AnnaBridge 171:3a7713b1edbc 7386 #define USB_EP0R_CTR_TX_Pos (7U)
AnnaBridge 171:3a7713b1edbc 7387 #define USB_EP0R_CTR_TX_Msk (0x1U << USB_EP0R_CTR_TX_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7388 #define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk /*!<Correct Transfer for transmission */
AnnaBridge 171:3a7713b1edbc 7389 #define USB_EP0R_EP_KIND_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7390 #define USB_EP0R_EP_KIND_Msk (0x1U << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7391 #define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk /*!<Endpoint Kind */
AnnaBridge 171:3a7713b1edbc 7392
AnnaBridge 171:3a7713b1edbc 7393 #define USB_EP0R_EP_TYPE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 7394 #define USB_EP0R_EP_TYPE_Msk (0x3U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */
AnnaBridge 171:3a7713b1edbc 7395 #define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */
AnnaBridge 171:3a7713b1edbc 7396 #define USB_EP0R_EP_TYPE_0 (0x1U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7397 #define USB_EP0R_EP_TYPE_1 (0x2U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7398
AnnaBridge 171:3a7713b1edbc 7399 #define USB_EP0R_SETUP_Pos (11U)
AnnaBridge 171:3a7713b1edbc 7400 #define USB_EP0R_SETUP_Msk (0x1U << USB_EP0R_SETUP_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7401 #define USB_EP0R_SETUP USB_EP0R_SETUP_Msk /*!<Setup transaction completed */
AnnaBridge 171:3a7713b1edbc 7402
AnnaBridge 171:3a7713b1edbc 7403 #define USB_EP0R_STAT_RX_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7404 #define USB_EP0R_STAT_RX_Msk (0x3U << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 7405 #define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
AnnaBridge 171:3a7713b1edbc 7406 #define USB_EP0R_STAT_RX_0 (0x1U << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7407 #define USB_EP0R_STAT_RX_1 (0x2U << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7408
AnnaBridge 171:3a7713b1edbc 7409 #define USB_EP0R_DTOG_RX_Pos (14U)
AnnaBridge 171:3a7713b1edbc 7410 #define USB_EP0R_DTOG_RX_Msk (0x1U << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7411 #define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */
AnnaBridge 171:3a7713b1edbc 7412 #define USB_EP0R_CTR_RX_Pos (15U)
AnnaBridge 171:3a7713b1edbc 7413 #define USB_EP0R_CTR_RX_Msk (0x1U << USB_EP0R_CTR_RX_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7414 #define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk /*!<Correct Transfer for reception */
AnnaBridge 171:3a7713b1edbc 7415
AnnaBridge 171:3a7713b1edbc 7416 /******************* Bit definition for USB_EP1R register *******************/
AnnaBridge 171:3a7713b1edbc 7417 #define USB_EP1R_EA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7418 #define USB_EP1R_EA_Msk (0xFU << USB_EP1R_EA_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 7419 #define USB_EP1R_EA USB_EP1R_EA_Msk /*!<Endpoint Address */
AnnaBridge 171:3a7713b1edbc 7420
AnnaBridge 171:3a7713b1edbc 7421 #define USB_EP1R_STAT_TX_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7422 #define USB_EP1R_STAT_TX_Msk (0x3U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 7423 #define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
AnnaBridge 171:3a7713b1edbc 7424 #define USB_EP1R_STAT_TX_0 (0x1U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7425 #define USB_EP1R_STAT_TX_1 (0x2U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7426
AnnaBridge 171:3a7713b1edbc 7427 #define USB_EP1R_DTOG_TX_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7428 #define USB_EP1R_DTOG_TX_Msk (0x1U << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7429 #define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */
AnnaBridge 171:3a7713b1edbc 7430 #define USB_EP1R_CTR_TX_Pos (7U)
AnnaBridge 171:3a7713b1edbc 7431 #define USB_EP1R_CTR_TX_Msk (0x1U << USB_EP1R_CTR_TX_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7432 #define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk /*!<Correct Transfer for transmission */
AnnaBridge 171:3a7713b1edbc 7433 #define USB_EP1R_EP_KIND_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7434 #define USB_EP1R_EP_KIND_Msk (0x1U << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7435 #define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk /*!<Endpoint Kind */
AnnaBridge 171:3a7713b1edbc 7436
AnnaBridge 171:3a7713b1edbc 7437 #define USB_EP1R_EP_TYPE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 7438 #define USB_EP1R_EP_TYPE_Msk (0x3U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */
AnnaBridge 171:3a7713b1edbc 7439 #define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */
AnnaBridge 171:3a7713b1edbc 7440 #define USB_EP1R_EP_TYPE_0 (0x1U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7441 #define USB_EP1R_EP_TYPE_1 (0x2U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7442
AnnaBridge 171:3a7713b1edbc 7443 #define USB_EP1R_SETUP_Pos (11U)
AnnaBridge 171:3a7713b1edbc 7444 #define USB_EP1R_SETUP_Msk (0x1U << USB_EP1R_SETUP_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7445 #define USB_EP1R_SETUP USB_EP1R_SETUP_Msk /*!<Setup transaction completed */
AnnaBridge 171:3a7713b1edbc 7446
AnnaBridge 171:3a7713b1edbc 7447 #define USB_EP1R_STAT_RX_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7448 #define USB_EP1R_STAT_RX_Msk (0x3U << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 7449 #define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
AnnaBridge 171:3a7713b1edbc 7450 #define USB_EP1R_STAT_RX_0 (0x1U << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7451 #define USB_EP1R_STAT_RX_1 (0x2U << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7452
AnnaBridge 171:3a7713b1edbc 7453 #define USB_EP1R_DTOG_RX_Pos (14U)
AnnaBridge 171:3a7713b1edbc 7454 #define USB_EP1R_DTOG_RX_Msk (0x1U << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7455 #define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */
AnnaBridge 171:3a7713b1edbc 7456 #define USB_EP1R_CTR_RX_Pos (15U)
AnnaBridge 171:3a7713b1edbc 7457 #define USB_EP1R_CTR_RX_Msk (0x1U << USB_EP1R_CTR_RX_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7458 #define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk /*!<Correct Transfer for reception */
AnnaBridge 171:3a7713b1edbc 7459
AnnaBridge 171:3a7713b1edbc 7460 /******************* Bit definition for USB_EP2R register *******************/
AnnaBridge 171:3a7713b1edbc 7461 #define USB_EP2R_EA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7462 #define USB_EP2R_EA_Msk (0xFU << USB_EP2R_EA_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 7463 #define USB_EP2R_EA USB_EP2R_EA_Msk /*!<Endpoint Address */
AnnaBridge 171:3a7713b1edbc 7464
AnnaBridge 171:3a7713b1edbc 7465 #define USB_EP2R_STAT_TX_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7466 #define USB_EP2R_STAT_TX_Msk (0x3U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 7467 #define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
AnnaBridge 171:3a7713b1edbc 7468 #define USB_EP2R_STAT_TX_0 (0x1U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7469 #define USB_EP2R_STAT_TX_1 (0x2U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7470
AnnaBridge 171:3a7713b1edbc 7471 #define USB_EP2R_DTOG_TX_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7472 #define USB_EP2R_DTOG_TX_Msk (0x1U << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7473 #define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */
AnnaBridge 171:3a7713b1edbc 7474 #define USB_EP2R_CTR_TX_Pos (7U)
AnnaBridge 171:3a7713b1edbc 7475 #define USB_EP2R_CTR_TX_Msk (0x1U << USB_EP2R_CTR_TX_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7476 #define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk /*!<Correct Transfer for transmission */
AnnaBridge 171:3a7713b1edbc 7477 #define USB_EP2R_EP_KIND_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7478 #define USB_EP2R_EP_KIND_Msk (0x1U << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7479 #define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk /*!<Endpoint Kind */
AnnaBridge 171:3a7713b1edbc 7480
AnnaBridge 171:3a7713b1edbc 7481 #define USB_EP2R_EP_TYPE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 7482 #define USB_EP2R_EP_TYPE_Msk (0x3U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */
AnnaBridge 171:3a7713b1edbc 7483 #define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */
AnnaBridge 171:3a7713b1edbc 7484 #define USB_EP2R_EP_TYPE_0 (0x1U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7485 #define USB_EP2R_EP_TYPE_1 (0x2U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7486
AnnaBridge 171:3a7713b1edbc 7487 #define USB_EP2R_SETUP_Pos (11U)
AnnaBridge 171:3a7713b1edbc 7488 #define USB_EP2R_SETUP_Msk (0x1U << USB_EP2R_SETUP_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7489 #define USB_EP2R_SETUP USB_EP2R_SETUP_Msk /*!<Setup transaction completed */
AnnaBridge 171:3a7713b1edbc 7490
AnnaBridge 171:3a7713b1edbc 7491 #define USB_EP2R_STAT_RX_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7492 #define USB_EP2R_STAT_RX_Msk (0x3U << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 7493 #define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
AnnaBridge 171:3a7713b1edbc 7494 #define USB_EP2R_STAT_RX_0 (0x1U << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7495 #define USB_EP2R_STAT_RX_1 (0x2U << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7496
AnnaBridge 171:3a7713b1edbc 7497 #define USB_EP2R_DTOG_RX_Pos (14U)
AnnaBridge 171:3a7713b1edbc 7498 #define USB_EP2R_DTOG_RX_Msk (0x1U << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7499 #define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */
AnnaBridge 171:3a7713b1edbc 7500 #define USB_EP2R_CTR_RX_Pos (15U)
AnnaBridge 171:3a7713b1edbc 7501 #define USB_EP2R_CTR_RX_Msk (0x1U << USB_EP2R_CTR_RX_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7502 #define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk /*!<Correct Transfer for reception */
AnnaBridge 171:3a7713b1edbc 7503
AnnaBridge 171:3a7713b1edbc 7504 /******************* Bit definition for USB_EP3R register *******************/
AnnaBridge 171:3a7713b1edbc 7505 #define USB_EP3R_EA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7506 #define USB_EP3R_EA_Msk (0xFU << USB_EP3R_EA_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 7507 #define USB_EP3R_EA USB_EP3R_EA_Msk /*!<Endpoint Address */
AnnaBridge 171:3a7713b1edbc 7508
AnnaBridge 171:3a7713b1edbc 7509 #define USB_EP3R_STAT_TX_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7510 #define USB_EP3R_STAT_TX_Msk (0x3U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 7511 #define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
AnnaBridge 171:3a7713b1edbc 7512 #define USB_EP3R_STAT_TX_0 (0x1U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7513 #define USB_EP3R_STAT_TX_1 (0x2U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7514
AnnaBridge 171:3a7713b1edbc 7515 #define USB_EP3R_DTOG_TX_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7516 #define USB_EP3R_DTOG_TX_Msk (0x1U << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7517 #define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */
AnnaBridge 171:3a7713b1edbc 7518 #define USB_EP3R_CTR_TX_Pos (7U)
AnnaBridge 171:3a7713b1edbc 7519 #define USB_EP3R_CTR_TX_Msk (0x1U << USB_EP3R_CTR_TX_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7520 #define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk /*!<Correct Transfer for transmission */
AnnaBridge 171:3a7713b1edbc 7521 #define USB_EP3R_EP_KIND_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7522 #define USB_EP3R_EP_KIND_Msk (0x1U << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7523 #define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk /*!<Endpoint Kind */
AnnaBridge 171:3a7713b1edbc 7524
AnnaBridge 171:3a7713b1edbc 7525 #define USB_EP3R_EP_TYPE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 7526 #define USB_EP3R_EP_TYPE_Msk (0x3U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */
AnnaBridge 171:3a7713b1edbc 7527 #define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */
AnnaBridge 171:3a7713b1edbc 7528 #define USB_EP3R_EP_TYPE_0 (0x1U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7529 #define USB_EP3R_EP_TYPE_1 (0x2U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7530
AnnaBridge 171:3a7713b1edbc 7531 #define USB_EP3R_SETUP_Pos (11U)
AnnaBridge 171:3a7713b1edbc 7532 #define USB_EP3R_SETUP_Msk (0x1U << USB_EP3R_SETUP_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7533 #define USB_EP3R_SETUP USB_EP3R_SETUP_Msk /*!<Setup transaction completed */
AnnaBridge 171:3a7713b1edbc 7534
AnnaBridge 171:3a7713b1edbc 7535 #define USB_EP3R_STAT_RX_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7536 #define USB_EP3R_STAT_RX_Msk (0x3U << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 7537 #define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
AnnaBridge 171:3a7713b1edbc 7538 #define USB_EP3R_STAT_RX_0 (0x1U << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7539 #define USB_EP3R_STAT_RX_1 (0x2U << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7540
AnnaBridge 171:3a7713b1edbc 7541 #define USB_EP3R_DTOG_RX_Pos (14U)
AnnaBridge 171:3a7713b1edbc 7542 #define USB_EP3R_DTOG_RX_Msk (0x1U << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7543 #define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */
AnnaBridge 171:3a7713b1edbc 7544 #define USB_EP3R_CTR_RX_Pos (15U)
AnnaBridge 171:3a7713b1edbc 7545 #define USB_EP3R_CTR_RX_Msk (0x1U << USB_EP3R_CTR_RX_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7546 #define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk /*!<Correct Transfer for reception */
AnnaBridge 171:3a7713b1edbc 7547
AnnaBridge 171:3a7713b1edbc 7548 /******************* Bit definition for USB_EP4R register *******************/
AnnaBridge 171:3a7713b1edbc 7549 #define USB_EP4R_EA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7550 #define USB_EP4R_EA_Msk (0xFU << USB_EP4R_EA_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 7551 #define USB_EP4R_EA USB_EP4R_EA_Msk /*!<Endpoint Address */
AnnaBridge 171:3a7713b1edbc 7552
AnnaBridge 171:3a7713b1edbc 7553 #define USB_EP4R_STAT_TX_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7554 #define USB_EP4R_STAT_TX_Msk (0x3U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 7555 #define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
AnnaBridge 171:3a7713b1edbc 7556 #define USB_EP4R_STAT_TX_0 (0x1U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7557 #define USB_EP4R_STAT_TX_1 (0x2U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7558
AnnaBridge 171:3a7713b1edbc 7559 #define USB_EP4R_DTOG_TX_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7560 #define USB_EP4R_DTOG_TX_Msk (0x1U << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7561 #define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */
AnnaBridge 171:3a7713b1edbc 7562 #define USB_EP4R_CTR_TX_Pos (7U)
AnnaBridge 171:3a7713b1edbc 7563 #define USB_EP4R_CTR_TX_Msk (0x1U << USB_EP4R_CTR_TX_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7564 #define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk /*!<Correct Transfer for transmission */
AnnaBridge 171:3a7713b1edbc 7565 #define USB_EP4R_EP_KIND_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7566 #define USB_EP4R_EP_KIND_Msk (0x1U << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7567 #define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk /*!<Endpoint Kind */
AnnaBridge 171:3a7713b1edbc 7568
AnnaBridge 171:3a7713b1edbc 7569 #define USB_EP4R_EP_TYPE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 7570 #define USB_EP4R_EP_TYPE_Msk (0x3U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */
AnnaBridge 171:3a7713b1edbc 7571 #define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */
AnnaBridge 171:3a7713b1edbc 7572 #define USB_EP4R_EP_TYPE_0 (0x1U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7573 #define USB_EP4R_EP_TYPE_1 (0x2U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7574
AnnaBridge 171:3a7713b1edbc 7575 #define USB_EP4R_SETUP_Pos (11U)
AnnaBridge 171:3a7713b1edbc 7576 #define USB_EP4R_SETUP_Msk (0x1U << USB_EP4R_SETUP_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7577 #define USB_EP4R_SETUP USB_EP4R_SETUP_Msk /*!<Setup transaction completed */
AnnaBridge 171:3a7713b1edbc 7578
AnnaBridge 171:3a7713b1edbc 7579 #define USB_EP4R_STAT_RX_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7580 #define USB_EP4R_STAT_RX_Msk (0x3U << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 7581 #define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
AnnaBridge 171:3a7713b1edbc 7582 #define USB_EP4R_STAT_RX_0 (0x1U << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7583 #define USB_EP4R_STAT_RX_1 (0x2U << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7584
AnnaBridge 171:3a7713b1edbc 7585 #define USB_EP4R_DTOG_RX_Pos (14U)
AnnaBridge 171:3a7713b1edbc 7586 #define USB_EP4R_DTOG_RX_Msk (0x1U << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7587 #define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */
AnnaBridge 171:3a7713b1edbc 7588 #define USB_EP4R_CTR_RX_Pos (15U)
AnnaBridge 171:3a7713b1edbc 7589 #define USB_EP4R_CTR_RX_Msk (0x1U << USB_EP4R_CTR_RX_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7590 #define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk /*!<Correct Transfer for reception */
AnnaBridge 171:3a7713b1edbc 7591
AnnaBridge 171:3a7713b1edbc 7592 /******************* Bit definition for USB_EP5R register *******************/
AnnaBridge 171:3a7713b1edbc 7593 #define USB_EP5R_EA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7594 #define USB_EP5R_EA_Msk (0xFU << USB_EP5R_EA_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 7595 #define USB_EP5R_EA USB_EP5R_EA_Msk /*!<Endpoint Address */
AnnaBridge 171:3a7713b1edbc 7596
AnnaBridge 171:3a7713b1edbc 7597 #define USB_EP5R_STAT_TX_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7598 #define USB_EP5R_STAT_TX_Msk (0x3U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 7599 #define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
AnnaBridge 171:3a7713b1edbc 7600 #define USB_EP5R_STAT_TX_0 (0x1U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7601 #define USB_EP5R_STAT_TX_1 (0x2U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7602
AnnaBridge 171:3a7713b1edbc 7603 #define USB_EP5R_DTOG_TX_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7604 #define USB_EP5R_DTOG_TX_Msk (0x1U << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7605 #define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */
AnnaBridge 171:3a7713b1edbc 7606 #define USB_EP5R_CTR_TX_Pos (7U)
AnnaBridge 171:3a7713b1edbc 7607 #define USB_EP5R_CTR_TX_Msk (0x1U << USB_EP5R_CTR_TX_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7608 #define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk /*!<Correct Transfer for transmission */
AnnaBridge 171:3a7713b1edbc 7609 #define USB_EP5R_EP_KIND_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7610 #define USB_EP5R_EP_KIND_Msk (0x1U << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7611 #define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk /*!<Endpoint Kind */
AnnaBridge 171:3a7713b1edbc 7612
AnnaBridge 171:3a7713b1edbc 7613 #define USB_EP5R_EP_TYPE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 7614 #define USB_EP5R_EP_TYPE_Msk (0x3U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */
AnnaBridge 171:3a7713b1edbc 7615 #define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */
AnnaBridge 171:3a7713b1edbc 7616 #define USB_EP5R_EP_TYPE_0 (0x1U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7617 #define USB_EP5R_EP_TYPE_1 (0x2U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7618
AnnaBridge 171:3a7713b1edbc 7619 #define USB_EP5R_SETUP_Pos (11U)
AnnaBridge 171:3a7713b1edbc 7620 #define USB_EP5R_SETUP_Msk (0x1U << USB_EP5R_SETUP_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7621 #define USB_EP5R_SETUP USB_EP5R_SETUP_Msk /*!<Setup transaction completed */
AnnaBridge 171:3a7713b1edbc 7622
AnnaBridge 171:3a7713b1edbc 7623 #define USB_EP5R_STAT_RX_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7624 #define USB_EP5R_STAT_RX_Msk (0x3U << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 7625 #define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
AnnaBridge 171:3a7713b1edbc 7626 #define USB_EP5R_STAT_RX_0 (0x1U << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7627 #define USB_EP5R_STAT_RX_1 (0x2U << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7628
AnnaBridge 171:3a7713b1edbc 7629 #define USB_EP5R_DTOG_RX_Pos (14U)
AnnaBridge 171:3a7713b1edbc 7630 #define USB_EP5R_DTOG_RX_Msk (0x1U << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7631 #define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */
AnnaBridge 171:3a7713b1edbc 7632 #define USB_EP5R_CTR_RX_Pos (15U)
AnnaBridge 171:3a7713b1edbc 7633 #define USB_EP5R_CTR_RX_Msk (0x1U << USB_EP5R_CTR_RX_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7634 #define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk /*!<Correct Transfer for reception */
AnnaBridge 171:3a7713b1edbc 7635
AnnaBridge 171:3a7713b1edbc 7636 /******************* Bit definition for USB_EP6R register *******************/
AnnaBridge 171:3a7713b1edbc 7637 #define USB_EP6R_EA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7638 #define USB_EP6R_EA_Msk (0xFU << USB_EP6R_EA_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 7639 #define USB_EP6R_EA USB_EP6R_EA_Msk /*!<Endpoint Address */
AnnaBridge 171:3a7713b1edbc 7640
AnnaBridge 171:3a7713b1edbc 7641 #define USB_EP6R_STAT_TX_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7642 #define USB_EP6R_STAT_TX_Msk (0x3U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 7643 #define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
AnnaBridge 171:3a7713b1edbc 7644 #define USB_EP6R_STAT_TX_0 (0x1U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7645 #define USB_EP6R_STAT_TX_1 (0x2U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7646
AnnaBridge 171:3a7713b1edbc 7647 #define USB_EP6R_DTOG_TX_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7648 #define USB_EP6R_DTOG_TX_Msk (0x1U << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7649 #define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */
AnnaBridge 171:3a7713b1edbc 7650 #define USB_EP6R_CTR_TX_Pos (7U)
AnnaBridge 171:3a7713b1edbc 7651 #define USB_EP6R_CTR_TX_Msk (0x1U << USB_EP6R_CTR_TX_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7652 #define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk /*!<Correct Transfer for transmission */
AnnaBridge 171:3a7713b1edbc 7653 #define USB_EP6R_EP_KIND_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7654 #define USB_EP6R_EP_KIND_Msk (0x1U << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7655 #define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk /*!<Endpoint Kind */
AnnaBridge 171:3a7713b1edbc 7656
AnnaBridge 171:3a7713b1edbc 7657 #define USB_EP6R_EP_TYPE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 7658 #define USB_EP6R_EP_TYPE_Msk (0x3U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */
AnnaBridge 171:3a7713b1edbc 7659 #define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */
AnnaBridge 171:3a7713b1edbc 7660 #define USB_EP6R_EP_TYPE_0 (0x1U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7661 #define USB_EP6R_EP_TYPE_1 (0x2U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7662
AnnaBridge 171:3a7713b1edbc 7663 #define USB_EP6R_SETUP_Pos (11U)
AnnaBridge 171:3a7713b1edbc 7664 #define USB_EP6R_SETUP_Msk (0x1U << USB_EP6R_SETUP_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7665 #define USB_EP6R_SETUP USB_EP6R_SETUP_Msk /*!<Setup transaction completed */
AnnaBridge 171:3a7713b1edbc 7666
AnnaBridge 171:3a7713b1edbc 7667 #define USB_EP6R_STAT_RX_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7668 #define USB_EP6R_STAT_RX_Msk (0x3U << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 7669 #define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
AnnaBridge 171:3a7713b1edbc 7670 #define USB_EP6R_STAT_RX_0 (0x1U << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7671 #define USB_EP6R_STAT_RX_1 (0x2U << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7672
AnnaBridge 171:3a7713b1edbc 7673 #define USB_EP6R_DTOG_RX_Pos (14U)
AnnaBridge 171:3a7713b1edbc 7674 #define USB_EP6R_DTOG_RX_Msk (0x1U << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7675 #define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */
AnnaBridge 171:3a7713b1edbc 7676 #define USB_EP6R_CTR_RX_Pos (15U)
AnnaBridge 171:3a7713b1edbc 7677 #define USB_EP6R_CTR_RX_Msk (0x1U << USB_EP6R_CTR_RX_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7678 #define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk /*!<Correct Transfer for reception */
AnnaBridge 171:3a7713b1edbc 7679
AnnaBridge 171:3a7713b1edbc 7680 /******************* Bit definition for USB_EP7R register *******************/
AnnaBridge 171:3a7713b1edbc 7681 #define USB_EP7R_EA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7682 #define USB_EP7R_EA_Msk (0xFU << USB_EP7R_EA_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 7683 #define USB_EP7R_EA USB_EP7R_EA_Msk /*!<Endpoint Address */
AnnaBridge 171:3a7713b1edbc 7684
AnnaBridge 171:3a7713b1edbc 7685 #define USB_EP7R_STAT_TX_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7686 #define USB_EP7R_STAT_TX_Msk (0x3U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 7687 #define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
AnnaBridge 171:3a7713b1edbc 7688 #define USB_EP7R_STAT_TX_0 (0x1U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7689 #define USB_EP7R_STAT_TX_1 (0x2U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7690
AnnaBridge 171:3a7713b1edbc 7691 #define USB_EP7R_DTOG_TX_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7692 #define USB_EP7R_DTOG_TX_Msk (0x1U << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7693 #define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk /*!<Data Toggle, for transmission transfers */
AnnaBridge 171:3a7713b1edbc 7694 #define USB_EP7R_CTR_TX_Pos (7U)
AnnaBridge 171:3a7713b1edbc 7695 #define USB_EP7R_CTR_TX_Msk (0x1U << USB_EP7R_CTR_TX_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7696 #define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk /*!<Correct Transfer for transmission */
AnnaBridge 171:3a7713b1edbc 7697 #define USB_EP7R_EP_KIND_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7698 #define USB_EP7R_EP_KIND_Msk (0x1U << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7699 #define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk /*!<Endpoint Kind */
AnnaBridge 171:3a7713b1edbc 7700
AnnaBridge 171:3a7713b1edbc 7701 #define USB_EP7R_EP_TYPE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 7702 #define USB_EP7R_EP_TYPE_Msk (0x3U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */
AnnaBridge 171:3a7713b1edbc 7703 #define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk /*!<EP_TYPE[1:0] bits (Endpoint type) */
AnnaBridge 171:3a7713b1edbc 7704 #define USB_EP7R_EP_TYPE_0 (0x1U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7705 #define USB_EP7R_EP_TYPE_1 (0x2U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7706
AnnaBridge 171:3a7713b1edbc 7707 #define USB_EP7R_SETUP_Pos (11U)
AnnaBridge 171:3a7713b1edbc 7708 #define USB_EP7R_SETUP_Msk (0x1U << USB_EP7R_SETUP_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7709 #define USB_EP7R_SETUP USB_EP7R_SETUP_Msk /*!<Setup transaction completed */
AnnaBridge 171:3a7713b1edbc 7710
AnnaBridge 171:3a7713b1edbc 7711 #define USB_EP7R_STAT_RX_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7712 #define USB_EP7R_STAT_RX_Msk (0x3U << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 7713 #define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
AnnaBridge 171:3a7713b1edbc 7714 #define USB_EP7R_STAT_RX_0 (0x1U << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7715 #define USB_EP7R_STAT_RX_1 (0x2U << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7716
AnnaBridge 171:3a7713b1edbc 7717 #define USB_EP7R_DTOG_RX_Pos (14U)
AnnaBridge 171:3a7713b1edbc 7718 #define USB_EP7R_DTOG_RX_Msk (0x1U << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7719 #define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk /*!<Data Toggle, for reception transfers */
AnnaBridge 171:3a7713b1edbc 7720 #define USB_EP7R_CTR_RX_Pos (15U)
AnnaBridge 171:3a7713b1edbc 7721 #define USB_EP7R_CTR_RX_Msk (0x1U << USB_EP7R_CTR_RX_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7722 #define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk /*!<Correct Transfer for reception */
AnnaBridge 171:3a7713b1edbc 7723
AnnaBridge 171:3a7713b1edbc 7724 /*!<Common registers */
AnnaBridge 171:3a7713b1edbc 7725
AnnaBridge 171:3a7713b1edbc 7726 #define USB_CNTR (USB_BASE + 0x00000040U) /*!< Control register */
AnnaBridge 171:3a7713b1edbc 7727 #define USB_ISTR (USB_BASE + 0x00000044U) /*!< Interrupt status register */
AnnaBridge 171:3a7713b1edbc 7728 #define USB_FNR (USB_BASE + 0x00000048U) /*!< Frame number register */
AnnaBridge 171:3a7713b1edbc 7729 #define USB_DADDR (USB_BASE + 0x0000004CU) /*!< Device address register */
AnnaBridge 171:3a7713b1edbc 7730 #define USB_BTABLE (USB_BASE + 0x00000050U) /*!< Buffer Table address register */
AnnaBridge 171:3a7713b1edbc 7731
AnnaBridge 171:3a7713b1edbc 7732
AnnaBridge 171:3a7713b1edbc 7733
AnnaBridge 171:3a7713b1edbc 7734 /******************* Bit definition for USB_CNTR register *******************/
AnnaBridge 171:3a7713b1edbc 7735 #define USB_CNTR_FRES_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7736 #define USB_CNTR_FRES_Msk (0x1U << USB_CNTR_FRES_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7737 #define USB_CNTR_FRES USB_CNTR_FRES_Msk /*!<Force USB Reset */
AnnaBridge 171:3a7713b1edbc 7738 #define USB_CNTR_PDWN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 7739 #define USB_CNTR_PDWN_Msk (0x1U << USB_CNTR_PDWN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7740 #define USB_CNTR_PDWN USB_CNTR_PDWN_Msk /*!<Power down */
AnnaBridge 171:3a7713b1edbc 7741 #define USB_CNTR_LPMODE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 7742 #define USB_CNTR_LPMODE_Msk (0x1U << USB_CNTR_LPMODE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7743 #define USB_CNTR_LPMODE USB_CNTR_LPMODE_Msk /*!<Low-power mode */
AnnaBridge 171:3a7713b1edbc 7744 #define USB_CNTR_FSUSP_Pos (3U)
AnnaBridge 171:3a7713b1edbc 7745 #define USB_CNTR_FSUSP_Msk (0x1U << USB_CNTR_FSUSP_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7746 #define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk /*!<Force suspend */
AnnaBridge 171:3a7713b1edbc 7747 #define USB_CNTR_RESUME_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7748 #define USB_CNTR_RESUME_Msk (0x1U << USB_CNTR_RESUME_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7749 #define USB_CNTR_RESUME USB_CNTR_RESUME_Msk /*!<Resume request */
AnnaBridge 171:3a7713b1edbc 7750 #define USB_CNTR_ESOFM_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7751 #define USB_CNTR_ESOFM_Msk (0x1U << USB_CNTR_ESOFM_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7752 #define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk /*!<Expected Start Of Frame Interrupt Mask */
AnnaBridge 171:3a7713b1edbc 7753 #define USB_CNTR_SOFM_Pos (9U)
AnnaBridge 171:3a7713b1edbc 7754 #define USB_CNTR_SOFM_Msk (0x1U << USB_CNTR_SOFM_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7755 #define USB_CNTR_SOFM USB_CNTR_SOFM_Msk /*!<Start Of Frame Interrupt Mask */
AnnaBridge 171:3a7713b1edbc 7756 #define USB_CNTR_RESETM_Pos (10U)
AnnaBridge 171:3a7713b1edbc 7757 #define USB_CNTR_RESETM_Msk (0x1U << USB_CNTR_RESETM_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7758 #define USB_CNTR_RESETM USB_CNTR_RESETM_Msk /*!<RESET Interrupt Mask */
AnnaBridge 171:3a7713b1edbc 7759 #define USB_CNTR_SUSPM_Pos (11U)
AnnaBridge 171:3a7713b1edbc 7760 #define USB_CNTR_SUSPM_Msk (0x1U << USB_CNTR_SUSPM_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7761 #define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk /*!<Suspend mode Interrupt Mask */
AnnaBridge 171:3a7713b1edbc 7762 #define USB_CNTR_WKUPM_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7763 #define USB_CNTR_WKUPM_Msk (0x1U << USB_CNTR_WKUPM_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7764 #define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk /*!<Wakeup Interrupt Mask */
AnnaBridge 171:3a7713b1edbc 7765 #define USB_CNTR_ERRM_Pos (13U)
AnnaBridge 171:3a7713b1edbc 7766 #define USB_CNTR_ERRM_Msk (0x1U << USB_CNTR_ERRM_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7767 #define USB_CNTR_ERRM USB_CNTR_ERRM_Msk /*!<Error Interrupt Mask */
AnnaBridge 171:3a7713b1edbc 7768 #define USB_CNTR_PMAOVRM_Pos (14U)
AnnaBridge 171:3a7713b1edbc 7769 #define USB_CNTR_PMAOVRM_Msk (0x1U << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7770 #define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk /*!<Packet Memory Area Over / Underrun Interrupt Mask */
AnnaBridge 171:3a7713b1edbc 7771 #define USB_CNTR_CTRM_Pos (15U)
AnnaBridge 171:3a7713b1edbc 7772 #define USB_CNTR_CTRM_Msk (0x1U << USB_CNTR_CTRM_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7773 #define USB_CNTR_CTRM USB_CNTR_CTRM_Msk /*!<Correct Transfer Interrupt Mask */
AnnaBridge 171:3a7713b1edbc 7774
AnnaBridge 171:3a7713b1edbc 7775 /******************* Bit definition for USB_ISTR register *******************/
AnnaBridge 171:3a7713b1edbc 7776 #define USB_ISTR_EP_ID_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7777 #define USB_ISTR_EP_ID_Msk (0xFU << USB_ISTR_EP_ID_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 7778 #define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk /*!<Endpoint Identifier */
AnnaBridge 171:3a7713b1edbc 7779 #define USB_ISTR_DIR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7780 #define USB_ISTR_DIR_Msk (0x1U << USB_ISTR_DIR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7781 #define USB_ISTR_DIR USB_ISTR_DIR_Msk /*!<Direction of transaction */
AnnaBridge 171:3a7713b1edbc 7782 #define USB_ISTR_ESOF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 7783 #define USB_ISTR_ESOF_Msk (0x1U << USB_ISTR_ESOF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 7784 #define USB_ISTR_ESOF USB_ISTR_ESOF_Msk /*!<Expected Start Of Frame */
AnnaBridge 171:3a7713b1edbc 7785 #define USB_ISTR_SOF_Pos (9U)
AnnaBridge 171:3a7713b1edbc 7786 #define USB_ISTR_SOF_Msk (0x1U << USB_ISTR_SOF_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 7787 #define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!<Start Of Frame */
AnnaBridge 171:3a7713b1edbc 7788 #define USB_ISTR_RESET_Pos (10U)
AnnaBridge 171:3a7713b1edbc 7789 #define USB_ISTR_RESET_Msk (0x1U << USB_ISTR_RESET_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 7790 #define USB_ISTR_RESET USB_ISTR_RESET_Msk /*!<USB RESET request */
AnnaBridge 171:3a7713b1edbc 7791 #define USB_ISTR_SUSP_Pos (11U)
AnnaBridge 171:3a7713b1edbc 7792 #define USB_ISTR_SUSP_Msk (0x1U << USB_ISTR_SUSP_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 7793 #define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!<Suspend mode request */
AnnaBridge 171:3a7713b1edbc 7794 #define USB_ISTR_WKUP_Pos (12U)
AnnaBridge 171:3a7713b1edbc 7795 #define USB_ISTR_WKUP_Msk (0x1U << USB_ISTR_WKUP_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 7796 #define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!<Wake up */
AnnaBridge 171:3a7713b1edbc 7797 #define USB_ISTR_ERR_Pos (13U)
AnnaBridge 171:3a7713b1edbc 7798 #define USB_ISTR_ERR_Msk (0x1U << USB_ISTR_ERR_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7799 #define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!<Error */
AnnaBridge 171:3a7713b1edbc 7800 #define USB_ISTR_PMAOVR_Pos (14U)
AnnaBridge 171:3a7713b1edbc 7801 #define USB_ISTR_PMAOVR_Msk (0x1U << USB_ISTR_PMAOVR_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7802 #define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk /*!<Packet Memory Area Over / Underrun */
AnnaBridge 171:3a7713b1edbc 7803 #define USB_ISTR_CTR_Pos (15U)
AnnaBridge 171:3a7713b1edbc 7804 #define USB_ISTR_CTR_Msk (0x1U << USB_ISTR_CTR_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7805 #define USB_ISTR_CTR USB_ISTR_CTR_Msk /*!<Correct Transfer */
AnnaBridge 171:3a7713b1edbc 7806
AnnaBridge 171:3a7713b1edbc 7807 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
AnnaBridge 171:3a7713b1edbc 7808 #define USB_CLR_PMAOVRM (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
AnnaBridge 171:3a7713b1edbc 7809 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
AnnaBridge 171:3a7713b1edbc 7810 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
AnnaBridge 171:3a7713b1edbc 7811 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
AnnaBridge 171:3a7713b1edbc 7812 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
AnnaBridge 171:3a7713b1edbc 7813 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
AnnaBridge 171:3a7713b1edbc 7814 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
AnnaBridge 171:3a7713b1edbc 7815
AnnaBridge 171:3a7713b1edbc 7816
AnnaBridge 171:3a7713b1edbc 7817 /******************* Bit definition for USB_FNR register ********************/
AnnaBridge 171:3a7713b1edbc 7818 #define USB_FNR_FN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7819 #define USB_FNR_FN_Msk (0x7FFU << USB_FNR_FN_Pos) /*!< 0x000007FF */
AnnaBridge 171:3a7713b1edbc 7820 #define USB_FNR_FN USB_FNR_FN_Msk /*!<Frame Number */
AnnaBridge 171:3a7713b1edbc 7821 #define USB_FNR_LSOF_Pos (11U)
AnnaBridge 171:3a7713b1edbc 7822 #define USB_FNR_LSOF_Msk (0x3U << USB_FNR_LSOF_Pos) /*!< 0x00001800 */
AnnaBridge 171:3a7713b1edbc 7823 #define USB_FNR_LSOF USB_FNR_LSOF_Msk /*!<Lost SOF */
AnnaBridge 171:3a7713b1edbc 7824 #define USB_FNR_LCK_Pos (13U)
AnnaBridge 171:3a7713b1edbc 7825 #define USB_FNR_LCK_Msk (0x1U << USB_FNR_LCK_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 7826 #define USB_FNR_LCK USB_FNR_LCK_Msk /*!<Locked */
AnnaBridge 171:3a7713b1edbc 7827 #define USB_FNR_RXDM_Pos (14U)
AnnaBridge 171:3a7713b1edbc 7828 #define USB_FNR_RXDM_Msk (0x1U << USB_FNR_RXDM_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 7829 #define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!<Receive Data - Line Status */
AnnaBridge 171:3a7713b1edbc 7830 #define USB_FNR_RXDP_Pos (15U)
AnnaBridge 171:3a7713b1edbc 7831 #define USB_FNR_RXDP_Msk (0x1U << USB_FNR_RXDP_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 7832 #define USB_FNR_RXDP USB_FNR_RXDP_Msk /*!<Receive Data + Line Status */
AnnaBridge 171:3a7713b1edbc 7833
AnnaBridge 171:3a7713b1edbc 7834 /****************** Bit definition for USB_DADDR register *******************/
AnnaBridge 171:3a7713b1edbc 7835 #define USB_DADDR_ADD_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7836 #define USB_DADDR_ADD_Msk (0x7FU << USB_DADDR_ADD_Pos) /*!< 0x0000007F */
AnnaBridge 171:3a7713b1edbc 7837 #define USB_DADDR_ADD USB_DADDR_ADD_Msk /*!<ADD[6:0] bits (Device Address) */
AnnaBridge 171:3a7713b1edbc 7838 #define USB_DADDR_ADD0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7839 #define USB_DADDR_ADD0_Msk (0x1U << USB_DADDR_ADD0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 7840 #define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk /*!<Bit 0 */
AnnaBridge 171:3a7713b1edbc 7841 #define USB_DADDR_ADD1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 7842 #define USB_DADDR_ADD1_Msk (0x1U << USB_DADDR_ADD1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 7843 #define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk /*!<Bit 1 */
AnnaBridge 171:3a7713b1edbc 7844 #define USB_DADDR_ADD2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 7845 #define USB_DADDR_ADD2_Msk (0x1U << USB_DADDR_ADD2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 7846 #define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk /*!<Bit 2 */
AnnaBridge 171:3a7713b1edbc 7847 #define USB_DADDR_ADD3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 7848 #define USB_DADDR_ADD3_Msk (0x1U << USB_DADDR_ADD3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 7849 #define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk /*!<Bit 3 */
AnnaBridge 171:3a7713b1edbc 7850 #define USB_DADDR_ADD4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 7851 #define USB_DADDR_ADD4_Msk (0x1U << USB_DADDR_ADD4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 7852 #define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk /*!<Bit 4 */
AnnaBridge 171:3a7713b1edbc 7853 #define USB_DADDR_ADD5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 7854 #define USB_DADDR_ADD5_Msk (0x1U << USB_DADDR_ADD5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 7855 #define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk /*!<Bit 5 */
AnnaBridge 171:3a7713b1edbc 7856 #define USB_DADDR_ADD6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 7857 #define USB_DADDR_ADD6_Msk (0x1U << USB_DADDR_ADD6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 7858 #define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk /*!<Bit 6 */
AnnaBridge 171:3a7713b1edbc 7859
AnnaBridge 171:3a7713b1edbc 7860 #define USB_DADDR_EF_Pos (7U)
AnnaBridge 171:3a7713b1edbc 7861 #define USB_DADDR_EF_Msk (0x1U << USB_DADDR_EF_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 7862 #define USB_DADDR_EF USB_DADDR_EF_Msk /*!<Enable Function */
AnnaBridge 171:3a7713b1edbc 7863
AnnaBridge 171:3a7713b1edbc 7864 /****************** Bit definition for USB_BTABLE register ******************/
AnnaBridge 171:3a7713b1edbc 7865 #define USB_BTABLE_BTABLE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 7866 #define USB_BTABLE_BTABLE_Msk (0x1FFFU << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
AnnaBridge 171:3a7713b1edbc 7867 #define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk /*!<Buffer Table */
AnnaBridge 171:3a7713b1edbc 7868
AnnaBridge 171:3a7713b1edbc 7869 /*!< Buffer descriptor table */
AnnaBridge 171:3a7713b1edbc 7870 /***************** Bit definition for USB_ADDR0_TX register *****************/
AnnaBridge 171:3a7713b1edbc 7871 #define USB_ADDR0_TX_ADDR0_TX_Pos (1U)
AnnaBridge 171:3a7713b1edbc 7872 #define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFU << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
AnnaBridge 171:3a7713b1edbc 7873 #define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */
AnnaBridge 171:3a7713b1edbc 7874
AnnaBridge 171:3a7713b1edbc 7875 /***************** Bit definition for USB_ADDR1_TX register *****************/
AnnaBridge 171:3a7713b1edbc 7876 #define USB_ADDR1_TX_ADDR1_TX_Pos (1U)
AnnaBridge 171:3a7713b1edbc 7877 #define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFU << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
AnnaBridge 171:3a7713b1edbc 7878 #define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */
AnnaBridge 171:3a7713b1edbc 7879
AnnaBridge 171:3a7713b1edbc 7880 /***************** Bit definition for USB_ADDR2_TX register *****************/
AnnaBridge 171:3a7713b1edbc 7881 #define USB_ADDR2_TX_ADDR2_TX_Pos (1U)
AnnaBridge 171:3a7713b1edbc 7882 #define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFU << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
AnnaBridge 171:3a7713b1edbc 7883 #define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */
AnnaBridge 171:3a7713b1edbc 7884
AnnaBridge 171:3a7713b1edbc 7885 /***************** Bit definition for USB_ADDR3_TX register *****************/
AnnaBridge 171:3a7713b1edbc 7886 #define USB_ADDR3_TX_ADDR3_TX_Pos (1U)
AnnaBridge 171:3a7713b1edbc 7887 #define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFU << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
AnnaBridge 171:3a7713b1edbc 7888 #define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */
AnnaBridge 171:3a7713b1edbc 7889
AnnaBridge 171:3a7713b1edbc 7890 /***************** Bit definition for USB_ADDR4_TX register *****************/
AnnaBridge 171:3a7713b1edbc 7891 #define USB_ADDR4_TX_ADDR4_TX_Pos (1U)
AnnaBridge 171:3a7713b1edbc 7892 #define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFU << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
AnnaBridge 171:3a7713b1edbc 7893 #define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */
AnnaBridge 171:3a7713b1edbc 7894
AnnaBridge 171:3a7713b1edbc 7895 /***************** Bit definition for USB_ADDR5_TX register *****************/
AnnaBridge 171:3a7713b1edbc 7896 #define USB_ADDR5_TX_ADDR5_TX_Pos (1U)
AnnaBridge 171:3a7713b1edbc 7897 #define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFU << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
AnnaBridge 171:3a7713b1edbc 7898 #define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */
AnnaBridge 171:3a7713b1edbc 7899
AnnaBridge 171:3a7713b1edbc 7900 /***************** Bit definition for USB_ADDR6_TX register *****************/
AnnaBridge 171:3a7713b1edbc 7901 #define USB_ADDR6_TX_ADDR6_TX_Pos (1U)
AnnaBridge 171:3a7713b1edbc 7902 #define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFU << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
AnnaBridge 171:3a7713b1edbc 7903 #define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */
AnnaBridge 171:3a7713b1edbc 7904
AnnaBridge 171:3a7713b1edbc 7905 /***************** Bit definition for USB_ADDR7_TX register *****************/
AnnaBridge 171:3a7713b1edbc 7906 #define USB_ADDR7_TX_ADDR7_TX_Pos (1U)
AnnaBridge 171:3a7713b1edbc 7907 #define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFU << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
AnnaBridge 171:3a7713b1edbc 7908 #define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */
AnnaBridge 171:3a7713b1edbc 7909
AnnaBridge 171:3a7713b1edbc 7910 /*----------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 7911
AnnaBridge 171:3a7713b1edbc 7912 /***************** Bit definition for USB_COUNT0_TX register ****************/
AnnaBridge 171:3a7713b1edbc 7913 #define USB_COUNT0_TX_COUNT0_TX_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7914 #define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFU << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 7915 #define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */
AnnaBridge 171:3a7713b1edbc 7916
AnnaBridge 171:3a7713b1edbc 7917 /***************** Bit definition for USB_COUNT1_TX register ****************/
AnnaBridge 171:3a7713b1edbc 7918 #define USB_COUNT1_TX_COUNT1_TX_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7919 #define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFU << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 7920 #define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */
AnnaBridge 171:3a7713b1edbc 7921
AnnaBridge 171:3a7713b1edbc 7922 /***************** Bit definition for USB_COUNT2_TX register ****************/
AnnaBridge 171:3a7713b1edbc 7923 #define USB_COUNT2_TX_COUNT2_TX_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7924 #define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFU << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 7925 #define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */
AnnaBridge 171:3a7713b1edbc 7926
AnnaBridge 171:3a7713b1edbc 7927 /***************** Bit definition for USB_COUNT3_TX register ****************/
AnnaBridge 171:3a7713b1edbc 7928 #define USB_COUNT3_TX_COUNT3_TX_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7929 #define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFU << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 7930 #define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */
AnnaBridge 171:3a7713b1edbc 7931
AnnaBridge 171:3a7713b1edbc 7932 /***************** Bit definition for USB_COUNT4_TX register ****************/
AnnaBridge 171:3a7713b1edbc 7933 #define USB_COUNT4_TX_COUNT4_TX_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7934 #define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFU << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 7935 #define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */
AnnaBridge 171:3a7713b1edbc 7936
AnnaBridge 171:3a7713b1edbc 7937 /***************** Bit definition for USB_COUNT5_TX register ****************/
AnnaBridge 171:3a7713b1edbc 7938 #define USB_COUNT5_TX_COUNT5_TX_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7939 #define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFU << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 7940 #define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */
AnnaBridge 171:3a7713b1edbc 7941
AnnaBridge 171:3a7713b1edbc 7942 /***************** Bit definition for USB_COUNT6_TX register ****************/
AnnaBridge 171:3a7713b1edbc 7943 #define USB_COUNT6_TX_COUNT6_TX_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7944 #define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFU << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 7945 #define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */
AnnaBridge 171:3a7713b1edbc 7946
AnnaBridge 171:3a7713b1edbc 7947 /***************** Bit definition for USB_COUNT7_TX register ****************/
AnnaBridge 171:3a7713b1edbc 7948 #define USB_COUNT7_TX_COUNT7_TX_Pos (0U)
AnnaBridge 171:3a7713b1edbc 7949 #define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFU << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 7950 #define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */
AnnaBridge 171:3a7713b1edbc 7951
AnnaBridge 171:3a7713b1edbc 7952 /*----------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 7953
AnnaBridge 171:3a7713b1edbc 7954 /**************** Bit definition for USB_COUNT0_TX_0 register ***************/
AnnaBridge 171:3a7713b1edbc 7955 #define USB_COUNT0_TX_0_COUNT0_TX_0 (0x000003FFU) /*!< Transmission Byte Count 0 (low) */
AnnaBridge 171:3a7713b1edbc 7956
AnnaBridge 171:3a7713b1edbc 7957 /**************** Bit definition for USB_COUNT0_TX_1 register ***************/
AnnaBridge 171:3a7713b1edbc 7958 #define USB_COUNT0_TX_1_COUNT0_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 0 (high) */
AnnaBridge 171:3a7713b1edbc 7959
AnnaBridge 171:3a7713b1edbc 7960 /**************** Bit definition for USB_COUNT1_TX_0 register ***************/
AnnaBridge 171:3a7713b1edbc 7961 #define USB_COUNT1_TX_0_COUNT1_TX_0 (0x000003FFU) /*!< Transmission Byte Count 1 (low) */
AnnaBridge 171:3a7713b1edbc 7962
AnnaBridge 171:3a7713b1edbc 7963 /**************** Bit definition for USB_COUNT1_TX_1 register ***************/
AnnaBridge 171:3a7713b1edbc 7964 #define USB_COUNT1_TX_1_COUNT1_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 1 (high) */
AnnaBridge 171:3a7713b1edbc 7965
AnnaBridge 171:3a7713b1edbc 7966 /**************** Bit definition for USB_COUNT2_TX_0 register ***************/
AnnaBridge 171:3a7713b1edbc 7967 #define USB_COUNT2_TX_0_COUNT2_TX_0 (0x000003FFU) /*!< Transmission Byte Count 2 (low) */
AnnaBridge 171:3a7713b1edbc 7968
AnnaBridge 171:3a7713b1edbc 7969 /**************** Bit definition for USB_COUNT2_TX_1 register ***************/
AnnaBridge 171:3a7713b1edbc 7970 #define USB_COUNT2_TX_1_COUNT2_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 2 (high) */
AnnaBridge 171:3a7713b1edbc 7971
AnnaBridge 171:3a7713b1edbc 7972 /**************** Bit definition for USB_COUNT3_TX_0 register ***************/
AnnaBridge 171:3a7713b1edbc 7973 #define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x00000000U03FF) /*!< Transmission Byte Count 3 (low) */
AnnaBridge 171:3a7713b1edbc 7974
AnnaBridge 171:3a7713b1edbc 7975 /**************** Bit definition for USB_COUNT3_TX_1 register ***************/
AnnaBridge 171:3a7713b1edbc 7976 #define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x000003FFU0000) /*!< Transmission Byte Count 3 (high) */
AnnaBridge 171:3a7713b1edbc 7977
AnnaBridge 171:3a7713b1edbc 7978 /**************** Bit definition for USB_COUNT4_TX_0 register ***************/
AnnaBridge 171:3a7713b1edbc 7979 #define USB_COUNT4_TX_0_COUNT4_TX_0 (0x000003FFU) /*!< Transmission Byte Count 4 (low) */
AnnaBridge 171:3a7713b1edbc 7980
AnnaBridge 171:3a7713b1edbc 7981 /**************** Bit definition for USB_COUNT4_TX_1 register ***************/
AnnaBridge 171:3a7713b1edbc 7982 #define USB_COUNT4_TX_1_COUNT4_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 4 (high) */
AnnaBridge 171:3a7713b1edbc 7983
AnnaBridge 171:3a7713b1edbc 7984 /**************** Bit definition for USB_COUNT5_TX_0 register ***************/
AnnaBridge 171:3a7713b1edbc 7985 #define USB_COUNT5_TX_0_COUNT5_TX_0 (0x000003FFU) /*!< Transmission Byte Count 5 (low) */
AnnaBridge 171:3a7713b1edbc 7986
AnnaBridge 171:3a7713b1edbc 7987 /**************** Bit definition for USB_COUNT5_TX_1 register ***************/
AnnaBridge 171:3a7713b1edbc 7988 #define USB_COUNT5_TX_1_COUNT5_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 5 (high) */
AnnaBridge 171:3a7713b1edbc 7989
AnnaBridge 171:3a7713b1edbc 7990 /**************** Bit definition for USB_COUNT6_TX_0 register ***************/
AnnaBridge 171:3a7713b1edbc 7991 #define USB_COUNT6_TX_0_COUNT6_TX_0 (0x000003FFU) /*!< Transmission Byte Count 6 (low) */
AnnaBridge 171:3a7713b1edbc 7992
AnnaBridge 171:3a7713b1edbc 7993 /**************** Bit definition for USB_COUNT6_TX_1 register ***************/
AnnaBridge 171:3a7713b1edbc 7994 #define USB_COUNT6_TX_1_COUNT6_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 6 (high) */
AnnaBridge 171:3a7713b1edbc 7995
AnnaBridge 171:3a7713b1edbc 7996 /**************** Bit definition for USB_COUNT7_TX_0 register ***************/
AnnaBridge 171:3a7713b1edbc 7997 #define USB_COUNT7_TX_0_COUNT7_TX_0 (0x000003FFU) /*!< Transmission Byte Count 7 (low) */
AnnaBridge 171:3a7713b1edbc 7998
AnnaBridge 171:3a7713b1edbc 7999 /**************** Bit definition for USB_COUNT7_TX_1 register ***************/
AnnaBridge 171:3a7713b1edbc 8000 #define USB_COUNT7_TX_1_COUNT7_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 7 (high) */
AnnaBridge 171:3a7713b1edbc 8001
AnnaBridge 171:3a7713b1edbc 8002 /*----------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 8003
AnnaBridge 171:3a7713b1edbc 8004 /***************** Bit definition for USB_ADDR0_RX register *****************/
AnnaBridge 171:3a7713b1edbc 8005 #define USB_ADDR0_RX_ADDR0_RX_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8006 #define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFU << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
AnnaBridge 171:3a7713b1edbc 8007 #define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */
AnnaBridge 171:3a7713b1edbc 8008
AnnaBridge 171:3a7713b1edbc 8009 /***************** Bit definition for USB_ADDR1_RX register *****************/
AnnaBridge 171:3a7713b1edbc 8010 #define USB_ADDR1_RX_ADDR1_RX_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8011 #define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFU << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
AnnaBridge 171:3a7713b1edbc 8012 #define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */
AnnaBridge 171:3a7713b1edbc 8013
AnnaBridge 171:3a7713b1edbc 8014 /***************** Bit definition for USB_ADDR2_RX register *****************/
AnnaBridge 171:3a7713b1edbc 8015 #define USB_ADDR2_RX_ADDR2_RX_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8016 #define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFU << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
AnnaBridge 171:3a7713b1edbc 8017 #define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */
AnnaBridge 171:3a7713b1edbc 8018
AnnaBridge 171:3a7713b1edbc 8019 /***************** Bit definition for USB_ADDR3_RX register *****************/
AnnaBridge 171:3a7713b1edbc 8020 #define USB_ADDR3_RX_ADDR3_RX_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8021 #define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFU << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
AnnaBridge 171:3a7713b1edbc 8022 #define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */
AnnaBridge 171:3a7713b1edbc 8023
AnnaBridge 171:3a7713b1edbc 8024 /***************** Bit definition for USB_ADDR4_RX register *****************/
AnnaBridge 171:3a7713b1edbc 8025 #define USB_ADDR4_RX_ADDR4_RX_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8026 #define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFU << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
AnnaBridge 171:3a7713b1edbc 8027 #define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */
AnnaBridge 171:3a7713b1edbc 8028
AnnaBridge 171:3a7713b1edbc 8029 /***************** Bit definition for USB_ADDR5_RX register *****************/
AnnaBridge 171:3a7713b1edbc 8030 #define USB_ADDR5_RX_ADDR5_RX_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8031 #define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFU << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
AnnaBridge 171:3a7713b1edbc 8032 #define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */
AnnaBridge 171:3a7713b1edbc 8033
AnnaBridge 171:3a7713b1edbc 8034 /***************** Bit definition for USB_ADDR6_RX register *****************/
AnnaBridge 171:3a7713b1edbc 8035 #define USB_ADDR6_RX_ADDR6_RX_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8036 #define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFU << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
AnnaBridge 171:3a7713b1edbc 8037 #define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */
AnnaBridge 171:3a7713b1edbc 8038
AnnaBridge 171:3a7713b1edbc 8039 /***************** Bit definition for USB_ADDR7_RX register *****************/
AnnaBridge 171:3a7713b1edbc 8040 #define USB_ADDR7_RX_ADDR7_RX_Pos (1U)
AnnaBridge 171:3a7713b1edbc 8041 #define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFU << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
AnnaBridge 171:3a7713b1edbc 8042 #define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */
AnnaBridge 171:3a7713b1edbc 8043
AnnaBridge 171:3a7713b1edbc 8044 /*----------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 8045
AnnaBridge 171:3a7713b1edbc 8046 /***************** Bit definition for USB_COUNT0_RX register ****************/
AnnaBridge 171:3a7713b1edbc 8047 #define USB_COUNT0_RX_COUNT0_RX_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8048 #define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFU << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 8049 #define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */
AnnaBridge 171:3a7713b1edbc 8050
AnnaBridge 171:3a7713b1edbc 8051 #define USB_COUNT0_RX_NUM_BLOCK_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8052 #define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
AnnaBridge 171:3a7713b1edbc 8053 #define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
AnnaBridge 171:3a7713b1edbc 8054 #define USB_COUNT0_RX_NUM_BLOCK_0 (0x01U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8055 #define USB_COUNT0_RX_NUM_BLOCK_1 (0x02U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8056 #define USB_COUNT0_RX_NUM_BLOCK_2 (0x04U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8057 #define USB_COUNT0_RX_NUM_BLOCK_3 (0x08U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8058 #define USB_COUNT0_RX_NUM_BLOCK_4 (0x10U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8059
AnnaBridge 171:3a7713b1edbc 8060 #define USB_COUNT0_RX_BLSIZE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 8061 #define USB_COUNT0_RX_BLSIZE_Msk (0x1U << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8062 #define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */
AnnaBridge 171:3a7713b1edbc 8063
AnnaBridge 171:3a7713b1edbc 8064 /***************** Bit definition for USB_COUNT1_RX register ****************/
AnnaBridge 171:3a7713b1edbc 8065 #define USB_COUNT1_RX_COUNT1_RX_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8066 #define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFU << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 8067 #define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */
AnnaBridge 171:3a7713b1edbc 8068
AnnaBridge 171:3a7713b1edbc 8069 #define USB_COUNT1_RX_NUM_BLOCK_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8070 #define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
AnnaBridge 171:3a7713b1edbc 8071 #define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
AnnaBridge 171:3a7713b1edbc 8072 #define USB_COUNT1_RX_NUM_BLOCK_0 (0x01U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8073 #define USB_COUNT1_RX_NUM_BLOCK_1 (0x02U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8074 #define USB_COUNT1_RX_NUM_BLOCK_2 (0x04U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8075 #define USB_COUNT1_RX_NUM_BLOCK_3 (0x08U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8076 #define USB_COUNT1_RX_NUM_BLOCK_4 (0x10U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8077
AnnaBridge 171:3a7713b1edbc 8078 #define USB_COUNT1_RX_BLSIZE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 8079 #define USB_COUNT1_RX_BLSIZE_Msk (0x1U << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8080 #define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */
AnnaBridge 171:3a7713b1edbc 8081
AnnaBridge 171:3a7713b1edbc 8082 /***************** Bit definition for USB_COUNT2_RX register ****************/
AnnaBridge 171:3a7713b1edbc 8083 #define USB_COUNT2_RX_COUNT2_RX_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8084 #define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFU << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 8085 #define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */
AnnaBridge 171:3a7713b1edbc 8086
AnnaBridge 171:3a7713b1edbc 8087 #define USB_COUNT2_RX_NUM_BLOCK_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8088 #define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
AnnaBridge 171:3a7713b1edbc 8089 #define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
AnnaBridge 171:3a7713b1edbc 8090 #define USB_COUNT2_RX_NUM_BLOCK_0 (0x01U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8091 #define USB_COUNT2_RX_NUM_BLOCK_1 (0x02U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8092 #define USB_COUNT2_RX_NUM_BLOCK_2 (0x04U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8093 #define USB_COUNT2_RX_NUM_BLOCK_3 (0x08U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8094 #define USB_COUNT2_RX_NUM_BLOCK_4 (0x10U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8095
AnnaBridge 171:3a7713b1edbc 8096 #define USB_COUNT2_RX_BLSIZE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 8097 #define USB_COUNT2_RX_BLSIZE_Msk (0x1U << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8098 #define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */
AnnaBridge 171:3a7713b1edbc 8099
AnnaBridge 171:3a7713b1edbc 8100 /***************** Bit definition for USB_COUNT3_RX register ****************/
AnnaBridge 171:3a7713b1edbc 8101 #define USB_COUNT3_RX_COUNT3_RX_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8102 #define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFU << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 8103 #define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */
AnnaBridge 171:3a7713b1edbc 8104
AnnaBridge 171:3a7713b1edbc 8105 #define USB_COUNT3_RX_NUM_BLOCK_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8106 #define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
AnnaBridge 171:3a7713b1edbc 8107 #define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
AnnaBridge 171:3a7713b1edbc 8108 #define USB_COUNT3_RX_NUM_BLOCK_0 (0x01U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8109 #define USB_COUNT3_RX_NUM_BLOCK_1 (0x02U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8110 #define USB_COUNT3_RX_NUM_BLOCK_2 (0x04U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8111 #define USB_COUNT3_RX_NUM_BLOCK_3 (0x08U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8112 #define USB_COUNT3_RX_NUM_BLOCK_4 (0x10U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8113
AnnaBridge 171:3a7713b1edbc 8114 #define USB_COUNT3_RX_BLSIZE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 8115 #define USB_COUNT3_RX_BLSIZE_Msk (0x1U << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8116 #define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */
AnnaBridge 171:3a7713b1edbc 8117
AnnaBridge 171:3a7713b1edbc 8118 /***************** Bit definition for USB_COUNT4_RX register ****************/
AnnaBridge 171:3a7713b1edbc 8119 #define USB_COUNT4_RX_COUNT4_RX_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8120 #define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFU << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 8121 #define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */
AnnaBridge 171:3a7713b1edbc 8122
AnnaBridge 171:3a7713b1edbc 8123 #define USB_COUNT4_RX_NUM_BLOCK_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8124 #define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
AnnaBridge 171:3a7713b1edbc 8125 #define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
AnnaBridge 171:3a7713b1edbc 8126 #define USB_COUNT4_RX_NUM_BLOCK_0 (0x01U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8127 #define USB_COUNT4_RX_NUM_BLOCK_1 (0x02U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8128 #define USB_COUNT4_RX_NUM_BLOCK_2 (0x04U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8129 #define USB_COUNT4_RX_NUM_BLOCK_3 (0x08U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8130 #define USB_COUNT4_RX_NUM_BLOCK_4 (0x10U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8131
AnnaBridge 171:3a7713b1edbc 8132 #define USB_COUNT4_RX_BLSIZE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 8133 #define USB_COUNT4_RX_BLSIZE_Msk (0x1U << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8134 #define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */
AnnaBridge 171:3a7713b1edbc 8135
AnnaBridge 171:3a7713b1edbc 8136 /***************** Bit definition for USB_COUNT5_RX register ****************/
AnnaBridge 171:3a7713b1edbc 8137 #define USB_COUNT5_RX_COUNT5_RX_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8138 #define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFU << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 8139 #define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */
AnnaBridge 171:3a7713b1edbc 8140
AnnaBridge 171:3a7713b1edbc 8141 #define USB_COUNT5_RX_NUM_BLOCK_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8142 #define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
AnnaBridge 171:3a7713b1edbc 8143 #define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
AnnaBridge 171:3a7713b1edbc 8144 #define USB_COUNT5_RX_NUM_BLOCK_0 (0x01U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8145 #define USB_COUNT5_RX_NUM_BLOCK_1 (0x02U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8146 #define USB_COUNT5_RX_NUM_BLOCK_2 (0x04U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8147 #define USB_COUNT5_RX_NUM_BLOCK_3 (0x08U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8148 #define USB_COUNT5_RX_NUM_BLOCK_4 (0x10U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8149
AnnaBridge 171:3a7713b1edbc 8150 #define USB_COUNT5_RX_BLSIZE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 8151 #define USB_COUNT5_RX_BLSIZE_Msk (0x1U << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8152 #define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */
AnnaBridge 171:3a7713b1edbc 8153
AnnaBridge 171:3a7713b1edbc 8154 /***************** Bit definition for USB_COUNT6_RX register ****************/
AnnaBridge 171:3a7713b1edbc 8155 #define USB_COUNT6_RX_COUNT6_RX_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8156 #define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFU << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 8157 #define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */
AnnaBridge 171:3a7713b1edbc 8158
AnnaBridge 171:3a7713b1edbc 8159 #define USB_COUNT6_RX_NUM_BLOCK_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8160 #define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
AnnaBridge 171:3a7713b1edbc 8161 #define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
AnnaBridge 171:3a7713b1edbc 8162 #define USB_COUNT6_RX_NUM_BLOCK_0 (0x01U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8163 #define USB_COUNT6_RX_NUM_BLOCK_1 (0x02U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8164 #define USB_COUNT6_RX_NUM_BLOCK_2 (0x04U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8165 #define USB_COUNT6_RX_NUM_BLOCK_3 (0x08U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8166 #define USB_COUNT6_RX_NUM_BLOCK_4 (0x10U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8167
AnnaBridge 171:3a7713b1edbc 8168 #define USB_COUNT6_RX_BLSIZE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 8169 #define USB_COUNT6_RX_BLSIZE_Msk (0x1U << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8170 #define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */
AnnaBridge 171:3a7713b1edbc 8171
AnnaBridge 171:3a7713b1edbc 8172 /***************** Bit definition for USB_COUNT7_RX register ****************/
AnnaBridge 171:3a7713b1edbc 8173 #define USB_COUNT7_RX_COUNT7_RX_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8174 #define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFU << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 8175 #define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */
AnnaBridge 171:3a7713b1edbc 8176
AnnaBridge 171:3a7713b1edbc 8177 #define USB_COUNT7_RX_NUM_BLOCK_Pos (10U)
AnnaBridge 171:3a7713b1edbc 8178 #define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
AnnaBridge 171:3a7713b1edbc 8179 #define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
AnnaBridge 171:3a7713b1edbc 8180 #define USB_COUNT7_RX_NUM_BLOCK_0 (0x01U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8181 #define USB_COUNT7_RX_NUM_BLOCK_1 (0x02U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8182 #define USB_COUNT7_RX_NUM_BLOCK_2 (0x04U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8183 #define USB_COUNT7_RX_NUM_BLOCK_3 (0x08U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8184 #define USB_COUNT7_RX_NUM_BLOCK_4 (0x10U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8185
AnnaBridge 171:3a7713b1edbc 8186 #define USB_COUNT7_RX_BLSIZE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 8187 #define USB_COUNT7_RX_BLSIZE_Msk (0x1U << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8188 #define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */
AnnaBridge 171:3a7713b1edbc 8189
AnnaBridge 171:3a7713b1edbc 8190 /*----------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 8191
AnnaBridge 171:3a7713b1edbc 8192 /**************** Bit definition for USB_COUNT0_RX_0 register ***************/
AnnaBridge 171:3a7713b1edbc 8193 #define USB_COUNT0_RX_0_COUNT0_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
AnnaBridge 171:3a7713b1edbc 8194
AnnaBridge 171:3a7713b1edbc 8195 #define USB_COUNT0_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
AnnaBridge 171:3a7713b1edbc 8196 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 8197 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 8198 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 8199 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
AnnaBridge 171:3a7713b1edbc 8200 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
AnnaBridge 171:3a7713b1edbc 8201
AnnaBridge 171:3a7713b1edbc 8202 #define USB_COUNT0_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
AnnaBridge 171:3a7713b1edbc 8203
AnnaBridge 171:3a7713b1edbc 8204 /**************** Bit definition for USB_COUNT0_RX_1 register ***************/
AnnaBridge 171:3a7713b1edbc 8205 #define USB_COUNT0_RX_1_COUNT0_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
AnnaBridge 171:3a7713b1edbc 8206
AnnaBridge 171:3a7713b1edbc 8207 #define USB_COUNT0_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
AnnaBridge 171:3a7713b1edbc 8208 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 8209 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 8210 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 8211 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
AnnaBridge 171:3a7713b1edbc 8212 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
AnnaBridge 171:3a7713b1edbc 8213
AnnaBridge 171:3a7713b1edbc 8214 #define USB_COUNT0_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
AnnaBridge 171:3a7713b1edbc 8215
AnnaBridge 171:3a7713b1edbc 8216 /**************** Bit definition for USB_COUNT1_RX_0 register ***************/
AnnaBridge 171:3a7713b1edbc 8217 #define USB_COUNT1_RX_0_COUNT1_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
AnnaBridge 171:3a7713b1edbc 8218
AnnaBridge 171:3a7713b1edbc 8219 #define USB_COUNT1_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
AnnaBridge 171:3a7713b1edbc 8220 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 8221 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 8222 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 8223 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
AnnaBridge 171:3a7713b1edbc 8224 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
AnnaBridge 171:3a7713b1edbc 8225
AnnaBridge 171:3a7713b1edbc 8226 #define USB_COUNT1_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
AnnaBridge 171:3a7713b1edbc 8227
AnnaBridge 171:3a7713b1edbc 8228 /**************** Bit definition for USB_COUNT1_RX_1 register ***************/
AnnaBridge 171:3a7713b1edbc 8229 #define USB_COUNT1_RX_1_COUNT1_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
AnnaBridge 171:3a7713b1edbc 8230
AnnaBridge 171:3a7713b1edbc 8231 #define USB_COUNT1_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
AnnaBridge 171:3a7713b1edbc 8232 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 8233 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 8234 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 8235 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
AnnaBridge 171:3a7713b1edbc 8236 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
AnnaBridge 171:3a7713b1edbc 8237
AnnaBridge 171:3a7713b1edbc 8238 #define USB_COUNT1_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
AnnaBridge 171:3a7713b1edbc 8239
AnnaBridge 171:3a7713b1edbc 8240 /**************** Bit definition for USB_COUNT2_RX_0 register ***************/
AnnaBridge 171:3a7713b1edbc 8241 #define USB_COUNT2_RX_0_COUNT2_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
AnnaBridge 171:3a7713b1edbc 8242
AnnaBridge 171:3a7713b1edbc 8243 #define USB_COUNT2_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
AnnaBridge 171:3a7713b1edbc 8244 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 8245 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 8246 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 8247 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
AnnaBridge 171:3a7713b1edbc 8248 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
AnnaBridge 171:3a7713b1edbc 8249
AnnaBridge 171:3a7713b1edbc 8250 #define USB_COUNT2_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
AnnaBridge 171:3a7713b1edbc 8251
AnnaBridge 171:3a7713b1edbc 8252 /**************** Bit definition for USB_COUNT2_RX_1 register ***************/
AnnaBridge 171:3a7713b1edbc 8253 #define USB_COUNT2_RX_1_COUNT2_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
AnnaBridge 171:3a7713b1edbc 8254
AnnaBridge 171:3a7713b1edbc 8255 #define USB_COUNT2_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
AnnaBridge 171:3a7713b1edbc 8256 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 8257 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 8258 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 8259 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
AnnaBridge 171:3a7713b1edbc 8260 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
AnnaBridge 171:3a7713b1edbc 8261
AnnaBridge 171:3a7713b1edbc 8262 #define USB_COUNT2_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
AnnaBridge 171:3a7713b1edbc 8263
AnnaBridge 171:3a7713b1edbc 8264 /**************** Bit definition for USB_COUNT3_RX_0 register ***************/
AnnaBridge 171:3a7713b1edbc 8265 #define USB_COUNT3_RX_0_COUNT3_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
AnnaBridge 171:3a7713b1edbc 8266
AnnaBridge 171:3a7713b1edbc 8267 #define USB_COUNT3_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
AnnaBridge 171:3a7713b1edbc 8268 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 8269 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 8270 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 8271 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
AnnaBridge 171:3a7713b1edbc 8272 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
AnnaBridge 171:3a7713b1edbc 8273
AnnaBridge 171:3a7713b1edbc 8274 #define USB_COUNT3_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
AnnaBridge 171:3a7713b1edbc 8275
AnnaBridge 171:3a7713b1edbc 8276 /**************** Bit definition for USB_COUNT3_RX_1 register ***************/
AnnaBridge 171:3a7713b1edbc 8277 #define USB_COUNT3_RX_1_COUNT3_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
AnnaBridge 171:3a7713b1edbc 8278
AnnaBridge 171:3a7713b1edbc 8279 #define USB_COUNT3_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
AnnaBridge 171:3a7713b1edbc 8280 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 8281 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 8282 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 8283 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
AnnaBridge 171:3a7713b1edbc 8284 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
AnnaBridge 171:3a7713b1edbc 8285
AnnaBridge 171:3a7713b1edbc 8286 #define USB_COUNT3_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
AnnaBridge 171:3a7713b1edbc 8287
AnnaBridge 171:3a7713b1edbc 8288 /**************** Bit definition for USB_COUNT4_RX_0 register ***************/
AnnaBridge 171:3a7713b1edbc 8289 #define USB_COUNT4_RX_0_COUNT4_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
AnnaBridge 171:3a7713b1edbc 8290
AnnaBridge 171:3a7713b1edbc 8291 #define USB_COUNT4_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
AnnaBridge 171:3a7713b1edbc 8292 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 8293 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 8294 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 8295 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
AnnaBridge 171:3a7713b1edbc 8296 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
AnnaBridge 171:3a7713b1edbc 8297
AnnaBridge 171:3a7713b1edbc 8298 #define USB_COUNT4_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
AnnaBridge 171:3a7713b1edbc 8299
AnnaBridge 171:3a7713b1edbc 8300 /**************** Bit definition for USB_COUNT4_RX_1 register ***************/
AnnaBridge 171:3a7713b1edbc 8301 #define USB_COUNT4_RX_1_COUNT4_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
AnnaBridge 171:3a7713b1edbc 8302
AnnaBridge 171:3a7713b1edbc 8303 #define USB_COUNT4_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
AnnaBridge 171:3a7713b1edbc 8304 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 8305 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 8306 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 8307 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
AnnaBridge 171:3a7713b1edbc 8308 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
AnnaBridge 171:3a7713b1edbc 8309
AnnaBridge 171:3a7713b1edbc 8310 #define USB_COUNT4_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
AnnaBridge 171:3a7713b1edbc 8311
AnnaBridge 171:3a7713b1edbc 8312 /**************** Bit definition for USB_COUNT5_RX_0 register ***************/
AnnaBridge 171:3a7713b1edbc 8313 #define USB_COUNT5_RX_0_COUNT5_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
AnnaBridge 171:3a7713b1edbc 8314
AnnaBridge 171:3a7713b1edbc 8315 #define USB_COUNT5_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
AnnaBridge 171:3a7713b1edbc 8316 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 8317 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 8318 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 8319 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
AnnaBridge 171:3a7713b1edbc 8320 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
AnnaBridge 171:3a7713b1edbc 8321
AnnaBridge 171:3a7713b1edbc 8322 #define USB_COUNT5_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
AnnaBridge 171:3a7713b1edbc 8323
AnnaBridge 171:3a7713b1edbc 8324 /**************** Bit definition for USB_COUNT5_RX_1 register ***************/
AnnaBridge 171:3a7713b1edbc 8325 #define USB_COUNT5_RX_1_COUNT5_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
AnnaBridge 171:3a7713b1edbc 8326
AnnaBridge 171:3a7713b1edbc 8327 #define USB_COUNT5_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
AnnaBridge 171:3a7713b1edbc 8328 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 8329 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 8330 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 8331 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
AnnaBridge 171:3a7713b1edbc 8332 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
AnnaBridge 171:3a7713b1edbc 8333
AnnaBridge 171:3a7713b1edbc 8334 #define USB_COUNT5_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
AnnaBridge 171:3a7713b1edbc 8335
AnnaBridge 171:3a7713b1edbc 8336 /*************** Bit definition for USB_COUNT6_RX_0 register ***************/
AnnaBridge 171:3a7713b1edbc 8337 #define USB_COUNT6_RX_0_COUNT6_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
AnnaBridge 171:3a7713b1edbc 8338
AnnaBridge 171:3a7713b1edbc 8339 #define USB_COUNT6_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
AnnaBridge 171:3a7713b1edbc 8340 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 8341 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 8342 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 8343 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
AnnaBridge 171:3a7713b1edbc 8344 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
AnnaBridge 171:3a7713b1edbc 8345
AnnaBridge 171:3a7713b1edbc 8346 #define USB_COUNT6_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
AnnaBridge 171:3a7713b1edbc 8347
AnnaBridge 171:3a7713b1edbc 8348 /**************** Bit definition for USB_COUNT6_RX_1 register ***************/
AnnaBridge 171:3a7713b1edbc 8349 #define USB_COUNT6_RX_1_COUNT6_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
AnnaBridge 171:3a7713b1edbc 8350
AnnaBridge 171:3a7713b1edbc 8351 #define USB_COUNT6_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
AnnaBridge 171:3a7713b1edbc 8352 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 8353 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 8354 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 8355 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
AnnaBridge 171:3a7713b1edbc 8356 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
AnnaBridge 171:3a7713b1edbc 8357
AnnaBridge 171:3a7713b1edbc 8358 #define USB_COUNT6_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
AnnaBridge 171:3a7713b1edbc 8359
AnnaBridge 171:3a7713b1edbc 8360 /*************** Bit definition for USB_COUNT7_RX_0 register ****************/
AnnaBridge 171:3a7713b1edbc 8361 #define USB_COUNT7_RX_0_COUNT7_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
AnnaBridge 171:3a7713b1edbc 8362
AnnaBridge 171:3a7713b1edbc 8363 #define USB_COUNT7_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
AnnaBridge 171:3a7713b1edbc 8364 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 8365 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 8366 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 8367 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
AnnaBridge 171:3a7713b1edbc 8368 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
AnnaBridge 171:3a7713b1edbc 8369
AnnaBridge 171:3a7713b1edbc 8370 #define USB_COUNT7_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
AnnaBridge 171:3a7713b1edbc 8371
AnnaBridge 171:3a7713b1edbc 8372 /*************** Bit definition for USB_COUNT7_RX_1 register ****************/
AnnaBridge 171:3a7713b1edbc 8373 #define USB_COUNT7_RX_1_COUNT7_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
AnnaBridge 171:3a7713b1edbc 8374
AnnaBridge 171:3a7713b1edbc 8375 #define USB_COUNT7_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
AnnaBridge 171:3a7713b1edbc 8376 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 8377 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 8378 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 8379 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
AnnaBridge 171:3a7713b1edbc 8380 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
AnnaBridge 171:3a7713b1edbc 8381
AnnaBridge 171:3a7713b1edbc 8382 #define USB_COUNT7_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
AnnaBridge 171:3a7713b1edbc 8383
AnnaBridge 171:3a7713b1edbc 8384 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 8385 /* */
AnnaBridge 171:3a7713b1edbc 8386 /* Window WATCHDOG (WWDG) */
AnnaBridge 171:3a7713b1edbc 8387 /* */
AnnaBridge 171:3a7713b1edbc 8388 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 8389
AnnaBridge 171:3a7713b1edbc 8390 /******************* Bit definition for WWDG_CR register ********************/
AnnaBridge 171:3a7713b1edbc 8391 #define WWDG_CR_T_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8392 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
AnnaBridge 171:3a7713b1edbc 8393 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
AnnaBridge 171:3a7713b1edbc 8394 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8395 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8396 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8397 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8398 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8399 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8400 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8401
AnnaBridge 171:3a7713b1edbc 8402 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 8403 #define WWDG_CR_T0 WWDG_CR_T_0
AnnaBridge 171:3a7713b1edbc 8404 #define WWDG_CR_T1 WWDG_CR_T_1
AnnaBridge 171:3a7713b1edbc 8405 #define WWDG_CR_T2 WWDG_CR_T_2
AnnaBridge 171:3a7713b1edbc 8406 #define WWDG_CR_T3 WWDG_CR_T_3
AnnaBridge 171:3a7713b1edbc 8407 #define WWDG_CR_T4 WWDG_CR_T_4
AnnaBridge 171:3a7713b1edbc 8408 #define WWDG_CR_T5 WWDG_CR_T_5
AnnaBridge 171:3a7713b1edbc 8409 #define WWDG_CR_T6 WWDG_CR_T_6
AnnaBridge 171:3a7713b1edbc 8410
AnnaBridge 171:3a7713b1edbc 8411 #define WWDG_CR_WDGA_Pos (7U)
AnnaBridge 171:3a7713b1edbc 8412 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8413 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
AnnaBridge 171:3a7713b1edbc 8414
AnnaBridge 171:3a7713b1edbc 8415 /******************* Bit definition for WWDG_CFR register *******************/
AnnaBridge 171:3a7713b1edbc 8416 #define WWDG_CFR_W_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8417 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
AnnaBridge 171:3a7713b1edbc 8418 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
AnnaBridge 171:3a7713b1edbc 8419 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8420 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8421 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8422 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8423 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8424 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8425 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8426
AnnaBridge 171:3a7713b1edbc 8427 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 8428 #define WWDG_CFR_W0 WWDG_CFR_W_0
AnnaBridge 171:3a7713b1edbc 8429 #define WWDG_CFR_W1 WWDG_CFR_W_1
AnnaBridge 171:3a7713b1edbc 8430 #define WWDG_CFR_W2 WWDG_CFR_W_2
AnnaBridge 171:3a7713b1edbc 8431 #define WWDG_CFR_W3 WWDG_CFR_W_3
AnnaBridge 171:3a7713b1edbc 8432 #define WWDG_CFR_W4 WWDG_CFR_W_4
AnnaBridge 171:3a7713b1edbc 8433 #define WWDG_CFR_W5 WWDG_CFR_W_5
AnnaBridge 171:3a7713b1edbc 8434 #define WWDG_CFR_W6 WWDG_CFR_W_6
AnnaBridge 171:3a7713b1edbc 8435
AnnaBridge 171:3a7713b1edbc 8436 #define WWDG_CFR_WDGTB_Pos (7U)
AnnaBridge 171:3a7713b1edbc 8437 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
AnnaBridge 171:3a7713b1edbc 8438 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
AnnaBridge 171:3a7713b1edbc 8439 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8440 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8441
AnnaBridge 171:3a7713b1edbc 8442 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 8443 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
AnnaBridge 171:3a7713b1edbc 8444 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
AnnaBridge 171:3a7713b1edbc 8445
AnnaBridge 171:3a7713b1edbc 8446 #define WWDG_CFR_EWI_Pos (9U)
AnnaBridge 171:3a7713b1edbc 8447 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8448 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
AnnaBridge 171:3a7713b1edbc 8449
AnnaBridge 171:3a7713b1edbc 8450 /******************* Bit definition for WWDG_SR register ********************/
AnnaBridge 171:3a7713b1edbc 8451 #define WWDG_SR_EWIF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8452 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8453 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 8454
AnnaBridge 171:3a7713b1edbc 8455 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 8456 /* */
AnnaBridge 171:3a7713b1edbc 8457 /* SystemTick (SysTick) */
AnnaBridge 171:3a7713b1edbc 8458 /* */
AnnaBridge 171:3a7713b1edbc 8459 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 8460
AnnaBridge 171:3a7713b1edbc 8461 /***************** Bit definition for SysTick_CTRL register *****************/
AnnaBridge 171:3a7713b1edbc 8462 #define SysTick_CTRL_ENABLE (0x00000001U) /*!< Counter enable */
AnnaBridge 171:3a7713b1edbc 8463 #define SysTick_CTRL_TICKINT (0x00000002U) /*!< Counting down to 0 pends the SysTick handler */
AnnaBridge 171:3a7713b1edbc 8464 #define SysTick_CTRL_CLKSOURCE (0x00000004U) /*!< Clock source */
AnnaBridge 171:3a7713b1edbc 8465 #define SysTick_CTRL_COUNTFLAG (0x00010000U) /*!< Count Flag */
AnnaBridge 171:3a7713b1edbc 8466
AnnaBridge 171:3a7713b1edbc 8467 /***************** Bit definition for SysTick_LOAD register *****************/
AnnaBridge 171:3a7713b1edbc 8468 #define SysTick_LOAD_RELOAD (0x00FFFFFFU) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
AnnaBridge 171:3a7713b1edbc 8469
AnnaBridge 171:3a7713b1edbc 8470 /***************** Bit definition for SysTick_VAL register ******************/
AnnaBridge 171:3a7713b1edbc 8471 #define SysTick_VAL_CURRENT (0x00FFFFFFU) /*!< Current value at the time the register is accessed */
AnnaBridge 171:3a7713b1edbc 8472
AnnaBridge 171:3a7713b1edbc 8473 /***************** Bit definition for SysTick_CALIB register ****************/
AnnaBridge 171:3a7713b1edbc 8474 #define SysTick_CALIB_TENMS (0x00FFFFFFU) /*!< Reload value to use for 10ms timing */
AnnaBridge 171:3a7713b1edbc 8475 #define SysTick_CALIB_SKEW (0x40000000U) /*!< Calibration value is not exactly 10 ms */
AnnaBridge 171:3a7713b1edbc 8476 #define SysTick_CALIB_NOREF (0x80000000U) /*!< The reference clock is not provided */
AnnaBridge 171:3a7713b1edbc 8477
AnnaBridge 171:3a7713b1edbc 8478 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 8479 /* */
AnnaBridge 171:3a7713b1edbc 8480 /* Nested Vectored Interrupt Controller (NVIC) */
AnnaBridge 171:3a7713b1edbc 8481 /* */
AnnaBridge 171:3a7713b1edbc 8482 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 8483
AnnaBridge 171:3a7713b1edbc 8484 /****************** Bit definition for NVIC_ISER register *******************/
AnnaBridge 171:3a7713b1edbc 8485 #define NVIC_ISER_SETENA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8486 #define NVIC_ISER_SETENA_Msk (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 8487 #define NVIC_ISER_SETENA NVIC_ISER_SETENA_Msk /*!< Interrupt set enable bits */
AnnaBridge 171:3a7713b1edbc 8488 #define NVIC_ISER_SETENA_0 (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8489 #define NVIC_ISER_SETENA_1 (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8490 #define NVIC_ISER_SETENA_2 (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8491 #define NVIC_ISER_SETENA_3 (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8492 #define NVIC_ISER_SETENA_4 (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8493 #define NVIC_ISER_SETENA_5 (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8494 #define NVIC_ISER_SETENA_6 (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8495 #define NVIC_ISER_SETENA_7 (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8496 #define NVIC_ISER_SETENA_8 (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8497 #define NVIC_ISER_SETENA_9 (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8498 #define NVIC_ISER_SETENA_10 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8499 #define NVIC_ISER_SETENA_11 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8500 #define NVIC_ISER_SETENA_12 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8501 #define NVIC_ISER_SETENA_13 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8502 #define NVIC_ISER_SETENA_14 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8503 #define NVIC_ISER_SETENA_15 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8504 #define NVIC_ISER_SETENA_16 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 8505 #define NVIC_ISER_SETENA_17 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 8506 #define NVIC_ISER_SETENA_18 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 8507 #define NVIC_ISER_SETENA_19 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 8508 #define NVIC_ISER_SETENA_20 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 8509 #define NVIC_ISER_SETENA_21 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 8510 #define NVIC_ISER_SETENA_22 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 8511 #define NVIC_ISER_SETENA_23 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 8512 #define NVIC_ISER_SETENA_24 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 8513 #define NVIC_ISER_SETENA_25 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 8514 #define NVIC_ISER_SETENA_26 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 8515 #define NVIC_ISER_SETENA_27 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 8516 #define NVIC_ISER_SETENA_28 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 8517 #define NVIC_ISER_SETENA_29 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 8518 #define NVIC_ISER_SETENA_30 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 8519 #define NVIC_ISER_SETENA_31 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 8520
AnnaBridge 171:3a7713b1edbc 8521 /****************** Bit definition for NVIC_ICER register *******************/
AnnaBridge 171:3a7713b1edbc 8522 #define NVIC_ICER_CLRENA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8523 #define NVIC_ICER_CLRENA_Msk (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 8524 #define NVIC_ICER_CLRENA NVIC_ICER_CLRENA_Msk /*!< Interrupt clear-enable bits */
AnnaBridge 171:3a7713b1edbc 8525 #define NVIC_ICER_CLRENA_0 (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8526 #define NVIC_ICER_CLRENA_1 (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8527 #define NVIC_ICER_CLRENA_2 (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8528 #define NVIC_ICER_CLRENA_3 (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8529 #define NVIC_ICER_CLRENA_4 (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8530 #define NVIC_ICER_CLRENA_5 (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8531 #define NVIC_ICER_CLRENA_6 (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8532 #define NVIC_ICER_CLRENA_7 (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8533 #define NVIC_ICER_CLRENA_8 (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8534 #define NVIC_ICER_CLRENA_9 (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8535 #define NVIC_ICER_CLRENA_10 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8536 #define NVIC_ICER_CLRENA_11 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8537 #define NVIC_ICER_CLRENA_12 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8538 #define NVIC_ICER_CLRENA_13 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8539 #define NVIC_ICER_CLRENA_14 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8540 #define NVIC_ICER_CLRENA_15 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8541 #define NVIC_ICER_CLRENA_16 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 8542 #define NVIC_ICER_CLRENA_17 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 8543 #define NVIC_ICER_CLRENA_18 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 8544 #define NVIC_ICER_CLRENA_19 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 8545 #define NVIC_ICER_CLRENA_20 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 8546 #define NVIC_ICER_CLRENA_21 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 8547 #define NVIC_ICER_CLRENA_22 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 8548 #define NVIC_ICER_CLRENA_23 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 8549 #define NVIC_ICER_CLRENA_24 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 8550 #define NVIC_ICER_CLRENA_25 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 8551 #define NVIC_ICER_CLRENA_26 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 8552 #define NVIC_ICER_CLRENA_27 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 8553 #define NVIC_ICER_CLRENA_28 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 8554 #define NVIC_ICER_CLRENA_29 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 8555 #define NVIC_ICER_CLRENA_30 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 8556 #define NVIC_ICER_CLRENA_31 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 8557
AnnaBridge 171:3a7713b1edbc 8558 /****************** Bit definition for NVIC_ISPR register *******************/
AnnaBridge 171:3a7713b1edbc 8559 #define NVIC_ISPR_SETPEND_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8560 #define NVIC_ISPR_SETPEND_Msk (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 8561 #define NVIC_ISPR_SETPEND NVIC_ISPR_SETPEND_Msk /*!< Interrupt set-pending bits */
AnnaBridge 171:3a7713b1edbc 8562 #define NVIC_ISPR_SETPEND_0 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8563 #define NVIC_ISPR_SETPEND_1 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8564 #define NVIC_ISPR_SETPEND_2 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8565 #define NVIC_ISPR_SETPEND_3 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8566 #define NVIC_ISPR_SETPEND_4 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8567 #define NVIC_ISPR_SETPEND_5 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8568 #define NVIC_ISPR_SETPEND_6 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8569 #define NVIC_ISPR_SETPEND_7 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8570 #define NVIC_ISPR_SETPEND_8 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8571 #define NVIC_ISPR_SETPEND_9 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8572 #define NVIC_ISPR_SETPEND_10 (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8573 #define NVIC_ISPR_SETPEND_11 (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8574 #define NVIC_ISPR_SETPEND_12 (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8575 #define NVIC_ISPR_SETPEND_13 (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8576 #define NVIC_ISPR_SETPEND_14 (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8577 #define NVIC_ISPR_SETPEND_15 (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8578 #define NVIC_ISPR_SETPEND_16 (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 8579 #define NVIC_ISPR_SETPEND_17 (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 8580 #define NVIC_ISPR_SETPEND_18 (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 8581 #define NVIC_ISPR_SETPEND_19 (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 8582 #define NVIC_ISPR_SETPEND_20 (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 8583 #define NVIC_ISPR_SETPEND_21 (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 8584 #define NVIC_ISPR_SETPEND_22 (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 8585 #define NVIC_ISPR_SETPEND_23 (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 8586 #define NVIC_ISPR_SETPEND_24 (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 8587 #define NVIC_ISPR_SETPEND_25 (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 8588 #define NVIC_ISPR_SETPEND_26 (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 8589 #define NVIC_ISPR_SETPEND_27 (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 8590 #define NVIC_ISPR_SETPEND_28 (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 8591 #define NVIC_ISPR_SETPEND_29 (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 8592 #define NVIC_ISPR_SETPEND_30 (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 8593 #define NVIC_ISPR_SETPEND_31 (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 8594
AnnaBridge 171:3a7713b1edbc 8595 /****************** Bit definition for NVIC_ICPR register *******************/
AnnaBridge 171:3a7713b1edbc 8596 #define NVIC_ICPR_CLRPEND_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8597 #define NVIC_ICPR_CLRPEND_Msk (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 8598 #define NVIC_ICPR_CLRPEND NVIC_ICPR_CLRPEND_Msk /*!< Interrupt clear-pending bits */
AnnaBridge 171:3a7713b1edbc 8599 #define NVIC_ICPR_CLRPEND_0 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8600 #define NVIC_ICPR_CLRPEND_1 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8601 #define NVIC_ICPR_CLRPEND_2 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8602 #define NVIC_ICPR_CLRPEND_3 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8603 #define NVIC_ICPR_CLRPEND_4 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8604 #define NVIC_ICPR_CLRPEND_5 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8605 #define NVIC_ICPR_CLRPEND_6 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8606 #define NVIC_ICPR_CLRPEND_7 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8607 #define NVIC_ICPR_CLRPEND_8 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8608 #define NVIC_ICPR_CLRPEND_9 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8609 #define NVIC_ICPR_CLRPEND_10 (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8610 #define NVIC_ICPR_CLRPEND_11 (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8611 #define NVIC_ICPR_CLRPEND_12 (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8612 #define NVIC_ICPR_CLRPEND_13 (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8613 #define NVIC_ICPR_CLRPEND_14 (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8614 #define NVIC_ICPR_CLRPEND_15 (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8615 #define NVIC_ICPR_CLRPEND_16 (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 8616 #define NVIC_ICPR_CLRPEND_17 (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 8617 #define NVIC_ICPR_CLRPEND_18 (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 8618 #define NVIC_ICPR_CLRPEND_19 (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 8619 #define NVIC_ICPR_CLRPEND_20 (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 8620 #define NVIC_ICPR_CLRPEND_21 (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 8621 #define NVIC_ICPR_CLRPEND_22 (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 8622 #define NVIC_ICPR_CLRPEND_23 (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 8623 #define NVIC_ICPR_CLRPEND_24 (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 8624 #define NVIC_ICPR_CLRPEND_25 (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 8625 #define NVIC_ICPR_CLRPEND_26 (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 8626 #define NVIC_ICPR_CLRPEND_27 (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 8627 #define NVIC_ICPR_CLRPEND_28 (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 8628 #define NVIC_ICPR_CLRPEND_29 (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 8629 #define NVIC_ICPR_CLRPEND_30 (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 8630 #define NVIC_ICPR_CLRPEND_31 (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 8631
AnnaBridge 171:3a7713b1edbc 8632 /****************** Bit definition for NVIC_IABR register *******************/
AnnaBridge 171:3a7713b1edbc 8633 #define NVIC_IABR_ACTIVE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8634 #define NVIC_IABR_ACTIVE_Msk (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 8635 #define NVIC_IABR_ACTIVE NVIC_IABR_ACTIVE_Msk /*!< Interrupt active flags */
AnnaBridge 171:3a7713b1edbc 8636 #define NVIC_IABR_ACTIVE_0 (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 8637 #define NVIC_IABR_ACTIVE_1 (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 8638 #define NVIC_IABR_ACTIVE_2 (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 8639 #define NVIC_IABR_ACTIVE_3 (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 8640 #define NVIC_IABR_ACTIVE_4 (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 8641 #define NVIC_IABR_ACTIVE_5 (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 8642 #define NVIC_IABR_ACTIVE_6 (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 8643 #define NVIC_IABR_ACTIVE_7 (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 8644 #define NVIC_IABR_ACTIVE_8 (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 8645 #define NVIC_IABR_ACTIVE_9 (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 8646 #define NVIC_IABR_ACTIVE_10 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 8647 #define NVIC_IABR_ACTIVE_11 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 8648 #define NVIC_IABR_ACTIVE_12 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 8649 #define NVIC_IABR_ACTIVE_13 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 8650 #define NVIC_IABR_ACTIVE_14 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 8651 #define NVIC_IABR_ACTIVE_15 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 8652 #define NVIC_IABR_ACTIVE_16 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 8653 #define NVIC_IABR_ACTIVE_17 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 8654 #define NVIC_IABR_ACTIVE_18 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 8655 #define NVIC_IABR_ACTIVE_19 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 8656 #define NVIC_IABR_ACTIVE_20 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 8657 #define NVIC_IABR_ACTIVE_21 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 8658 #define NVIC_IABR_ACTIVE_22 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 8659 #define NVIC_IABR_ACTIVE_23 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 8660 #define NVIC_IABR_ACTIVE_24 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 8661 #define NVIC_IABR_ACTIVE_25 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 8662 #define NVIC_IABR_ACTIVE_26 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 8663 #define NVIC_IABR_ACTIVE_27 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 8664 #define NVIC_IABR_ACTIVE_28 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 8665 #define NVIC_IABR_ACTIVE_29 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 8666 #define NVIC_IABR_ACTIVE_30 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 8667 #define NVIC_IABR_ACTIVE_31 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 8668
AnnaBridge 171:3a7713b1edbc 8669 /****************** Bit definition for NVIC_PRI0 register *******************/
AnnaBridge 171:3a7713b1edbc 8670 #define NVIC_IPR0_PRI_0 (0x000000FFU) /*!< Priority of interrupt 0 */
AnnaBridge 171:3a7713b1edbc 8671 #define NVIC_IPR0_PRI_1 (0x0000FF00U) /*!< Priority of interrupt 1 */
AnnaBridge 171:3a7713b1edbc 8672 #define NVIC_IPR0_PRI_2 (0x00FF0000U) /*!< Priority of interrupt 2 */
AnnaBridge 171:3a7713b1edbc 8673 #define NVIC_IPR0_PRI_3 (0xFF000000U) /*!< Priority of interrupt 3 */
AnnaBridge 171:3a7713b1edbc 8674
AnnaBridge 171:3a7713b1edbc 8675 /****************** Bit definition for NVIC_PRI1 register *******************/
AnnaBridge 171:3a7713b1edbc 8676 #define NVIC_IPR1_PRI_4 (0x000000FFU) /*!< Priority of interrupt 4 */
AnnaBridge 171:3a7713b1edbc 8677 #define NVIC_IPR1_PRI_5 (0x0000FF00U) /*!< Priority of interrupt 5 */
AnnaBridge 171:3a7713b1edbc 8678 #define NVIC_IPR1_PRI_6 (0x00FF0000U) /*!< Priority of interrupt 6 */
AnnaBridge 171:3a7713b1edbc 8679 #define NVIC_IPR1_PRI_7 (0xFF000000U) /*!< Priority of interrupt 7 */
AnnaBridge 171:3a7713b1edbc 8680
AnnaBridge 171:3a7713b1edbc 8681 /****************** Bit definition for NVIC_PRI2 register *******************/
AnnaBridge 171:3a7713b1edbc 8682 #define NVIC_IPR2_PRI_8 (0x000000FFU) /*!< Priority of interrupt 8 */
AnnaBridge 171:3a7713b1edbc 8683 #define NVIC_IPR2_PRI_9 (0x0000FF00U) /*!< Priority of interrupt 9 */
AnnaBridge 171:3a7713b1edbc 8684 #define NVIC_IPR2_PRI_10 (0x00FF0000U) /*!< Priority of interrupt 10 */
AnnaBridge 171:3a7713b1edbc 8685 #define NVIC_IPR2_PRI_11 (0xFF000000U) /*!< Priority of interrupt 11 */
AnnaBridge 171:3a7713b1edbc 8686
AnnaBridge 171:3a7713b1edbc 8687 /****************** Bit definition for NVIC_PRI3 register *******************/
AnnaBridge 171:3a7713b1edbc 8688 #define NVIC_IPR3_PRI_12 (0x000000FFU) /*!< Priority of interrupt 12 */
AnnaBridge 171:3a7713b1edbc 8689 #define NVIC_IPR3_PRI_13 (0x0000FF00U) /*!< Priority of interrupt 13 */
AnnaBridge 171:3a7713b1edbc 8690 #define NVIC_IPR3_PRI_14 (0x00FF0000U) /*!< Priority of interrupt 14 */
AnnaBridge 171:3a7713b1edbc 8691 #define NVIC_IPR3_PRI_15 (0xFF000000U) /*!< Priority of interrupt 15 */
AnnaBridge 171:3a7713b1edbc 8692
AnnaBridge 171:3a7713b1edbc 8693 /****************** Bit definition for NVIC_PRI4 register *******************/
AnnaBridge 171:3a7713b1edbc 8694 #define NVIC_IPR4_PRI_16 (0x000000FFU) /*!< Priority of interrupt 16 */
AnnaBridge 171:3a7713b1edbc 8695 #define NVIC_IPR4_PRI_17 (0x0000FF00U) /*!< Priority of interrupt 17 */
AnnaBridge 171:3a7713b1edbc 8696 #define NVIC_IPR4_PRI_18 (0x00FF0000U) /*!< Priority of interrupt 18 */
AnnaBridge 171:3a7713b1edbc 8697 #define NVIC_IPR4_PRI_19 (0xFF000000U) /*!< Priority of interrupt 19 */
AnnaBridge 171:3a7713b1edbc 8698
AnnaBridge 171:3a7713b1edbc 8699 /****************** Bit definition for NVIC_PRI5 register *******************/
AnnaBridge 171:3a7713b1edbc 8700 #define NVIC_IPR5_PRI_20 (0x000000FFU) /*!< Priority of interrupt 20 */
AnnaBridge 171:3a7713b1edbc 8701 #define NVIC_IPR5_PRI_21 (0x0000FF00U) /*!< Priority of interrupt 21 */
AnnaBridge 171:3a7713b1edbc 8702 #define NVIC_IPR5_PRI_22 (0x00FF0000U) /*!< Priority of interrupt 22 */
AnnaBridge 171:3a7713b1edbc 8703 #define NVIC_IPR5_PRI_23 (0xFF000000U) /*!< Priority of interrupt 23 */
AnnaBridge 171:3a7713b1edbc 8704
AnnaBridge 171:3a7713b1edbc 8705 /****************** Bit definition for NVIC_PRI6 register *******************/
AnnaBridge 171:3a7713b1edbc 8706 #define NVIC_IPR6_PRI_24 (0x000000FFU) /*!< Priority of interrupt 24 */
AnnaBridge 171:3a7713b1edbc 8707 #define NVIC_IPR6_PRI_25 (0x0000FF00U) /*!< Priority of interrupt 25 */
AnnaBridge 171:3a7713b1edbc 8708 #define NVIC_IPR6_PRI_26 (0x00FF0000U) /*!< Priority of interrupt 26 */
AnnaBridge 171:3a7713b1edbc 8709 #define NVIC_IPR6_PRI_27 (0xFF000000U) /*!< Priority of interrupt 27 */
AnnaBridge 171:3a7713b1edbc 8710
AnnaBridge 171:3a7713b1edbc 8711 /****************** Bit definition for NVIC_PRI7 register *******************/
AnnaBridge 171:3a7713b1edbc 8712 #define NVIC_IPR7_PRI_28 (0x000000FFU) /*!< Priority of interrupt 28 */
AnnaBridge 171:3a7713b1edbc 8713 #define NVIC_IPR7_PRI_29 (0x0000FF00U) /*!< Priority of interrupt 29 */
AnnaBridge 171:3a7713b1edbc 8714 #define NVIC_IPR7_PRI_30 (0x00FF0000U) /*!< Priority of interrupt 30 */
AnnaBridge 171:3a7713b1edbc 8715 #define NVIC_IPR7_PRI_31 (0xFF000000U) /*!< Priority of interrupt 31 */
AnnaBridge 171:3a7713b1edbc 8716
AnnaBridge 171:3a7713b1edbc 8717 /****************** Bit definition for SCB_CPUID register *******************/
AnnaBridge 171:3a7713b1edbc 8718 #define SCB_CPUID_REVISION (0x0000000FU) /*!< Implementation defined revision number */
AnnaBridge 171:3a7713b1edbc 8719 #define SCB_CPUID_PARTNO (0x0000FFF0U) /*!< Number of processor within serie */
AnnaBridge 171:3a7713b1edbc 8720 #define SCB_CPUID_Constant (0x000F0000U) /*!< Reads as 0x0F */
AnnaBridge 171:3a7713b1edbc 8721 #define SCB_CPUID_VARIANT (0x00F00000U) /*!< Implementation defined variant number */
AnnaBridge 171:3a7713b1edbc 8722 #define SCB_CPUID_IMPLEMENTER (0xFF000000U) /*!< Implementer code. ARM is 0x41 */
AnnaBridge 171:3a7713b1edbc 8723
AnnaBridge 171:3a7713b1edbc 8724 /******************* Bit definition for SCB_ICSR register *******************/
AnnaBridge 171:3a7713b1edbc 8725 #define SCB_ICSR_VECTACTIVE (0x000001FFU) /*!< Active ISR number field */
AnnaBridge 171:3a7713b1edbc 8726 #define SCB_ICSR_RETTOBASE (0x00000800U) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
AnnaBridge 171:3a7713b1edbc 8727 #define SCB_ICSR_VECTPENDING (0x003FF000U) /*!< Pending ISR number field */
AnnaBridge 171:3a7713b1edbc 8728 #define SCB_ICSR_ISRPENDING (0x00400000U) /*!< Interrupt pending flag */
AnnaBridge 171:3a7713b1edbc 8729 #define SCB_ICSR_ISRPREEMPT (0x00800000U) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
AnnaBridge 171:3a7713b1edbc 8730 #define SCB_ICSR_PENDSTCLR (0x02000000U) /*!< Clear pending SysTick bit */
AnnaBridge 171:3a7713b1edbc 8731 #define SCB_ICSR_PENDSTSET (0x04000000U) /*!< Set pending SysTick bit */
AnnaBridge 171:3a7713b1edbc 8732 #define SCB_ICSR_PENDSVCLR (0x08000000U) /*!< Clear pending pendSV bit */
AnnaBridge 171:3a7713b1edbc 8733 #define SCB_ICSR_PENDSVSET (0x10000000U) /*!< Set pending pendSV bit */
AnnaBridge 171:3a7713b1edbc 8734 #define SCB_ICSR_NMIPENDSET (0x80000000U) /*!< Set pending NMI bit */
AnnaBridge 171:3a7713b1edbc 8735
AnnaBridge 171:3a7713b1edbc 8736 /******************* Bit definition for SCB_VTOR register *******************/
AnnaBridge 171:3a7713b1edbc 8737 #define SCB_VTOR_TBLOFF (0x1FFFFF80U) /*!< Vector table base offset field */
AnnaBridge 171:3a7713b1edbc 8738 #define SCB_VTOR_TBLBASE (0x20000000U) /*!< Table base in code(0) or RAM(1) */
AnnaBridge 171:3a7713b1edbc 8739
AnnaBridge 171:3a7713b1edbc 8740 /*!<***************** Bit definition for SCB_AIRCR register *******************/
AnnaBridge 171:3a7713b1edbc 8741 #define SCB_AIRCR_VECTRESET (0x00000001U) /*!< System Reset bit */
AnnaBridge 171:3a7713b1edbc 8742 #define SCB_AIRCR_VECTCLRACTIVE (0x00000002U) /*!< Clear active vector bit */
AnnaBridge 171:3a7713b1edbc 8743 #define SCB_AIRCR_SYSRESETREQ (0x00000004U) /*!< Requests chip control logic to generate a reset */
AnnaBridge 171:3a7713b1edbc 8744
AnnaBridge 171:3a7713b1edbc 8745 #define SCB_AIRCR_PRIGROUP (0x00000700U) /*!< PRIGROUP[2:0] bits (Priority group) */
AnnaBridge 171:3a7713b1edbc 8746 #define SCB_AIRCR_PRIGROUP_0 (0x00000100U) /*!< Bit 0 */
AnnaBridge 171:3a7713b1edbc 8747 #define SCB_AIRCR_PRIGROUP_1 (0x00000200U) /*!< Bit 1 */
AnnaBridge 171:3a7713b1edbc 8748 #define SCB_AIRCR_PRIGROUP_2 (0x00000400U) /*!< Bit 2 */
AnnaBridge 171:3a7713b1edbc 8749
AnnaBridge 171:3a7713b1edbc 8750 /* prority group configuration */
AnnaBridge 171:3a7713b1edbc 8751 #define SCB_AIRCR_PRIGROUP0 (0x00000000U) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
AnnaBridge 171:3a7713b1edbc 8752 #define SCB_AIRCR_PRIGROUP1 (0x00000100U) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
AnnaBridge 171:3a7713b1edbc 8753 #define SCB_AIRCR_PRIGROUP2 (0x00000200U) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
AnnaBridge 171:3a7713b1edbc 8754 #define SCB_AIRCR_PRIGROUP3 (0x00000300U) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
AnnaBridge 171:3a7713b1edbc 8755 #define SCB_AIRCR_PRIGROUP4 (0x00000400U) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
AnnaBridge 171:3a7713b1edbc 8756 #define SCB_AIRCR_PRIGROUP5 (0x00000500U) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
AnnaBridge 171:3a7713b1edbc 8757 #define SCB_AIRCR_PRIGROUP6 (0x00000600U) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
AnnaBridge 171:3a7713b1edbc 8758 #define SCB_AIRCR_PRIGROUP7 (0x00000700U) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
AnnaBridge 171:3a7713b1edbc 8759
AnnaBridge 171:3a7713b1edbc 8760 #define SCB_AIRCR_ENDIANESS (0x00008000U) /*!< Data endianness bit */
AnnaBridge 171:3a7713b1edbc 8761 #define SCB_AIRCR_VECTKEY (0xFFFF0000U) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
AnnaBridge 171:3a7713b1edbc 8762
AnnaBridge 171:3a7713b1edbc 8763 /******************* Bit definition for SCB_SCR register ********************/
AnnaBridge 171:3a7713b1edbc 8764 #define SCB_SCR_SLEEPONEXIT (0x00000002U) /*!< Sleep on exit bit */
AnnaBridge 171:3a7713b1edbc 8765 #define SCB_SCR_SLEEPDEEP (0x00000004U) /*!< Sleep deep bit */
AnnaBridge 171:3a7713b1edbc 8766 #define SCB_SCR_SEVONPEND (0x00000010U) /*!< Wake up from WFE */
AnnaBridge 171:3a7713b1edbc 8767
AnnaBridge 171:3a7713b1edbc 8768 /******************** Bit definition for SCB_CCR register *******************/
AnnaBridge 171:3a7713b1edbc 8769 #define SCB_CCR_NONBASETHRDENA (0x00000001U) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
AnnaBridge 171:3a7713b1edbc 8770 #define SCB_CCR_USERSETMPEND (0x00000002U) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
AnnaBridge 171:3a7713b1edbc 8771 #define SCB_CCR_UNALIGN_TRP (0x00000008U) /*!< Trap for unaligned access */
AnnaBridge 171:3a7713b1edbc 8772 #define SCB_CCR_DIV_0_TRP (0x00000010U) /*!< Trap on Divide by 0 */
AnnaBridge 171:3a7713b1edbc 8773 #define SCB_CCR_BFHFNMIGN (0x00000100U) /*!< Handlers running at priority -1 and -2 */
AnnaBridge 171:3a7713b1edbc 8774 #define SCB_CCR_STKALIGN (0x00000200U) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
AnnaBridge 171:3a7713b1edbc 8775
AnnaBridge 171:3a7713b1edbc 8776 /******************* Bit definition for SCB_SHPR register ********************/
AnnaBridge 171:3a7713b1edbc 8777 #define SCB_SHPR_PRI_N_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8778 #define SCB_SHPR_PRI_N_Msk (0xFFU << SCB_SHPR_PRI_N_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 8779 #define SCB_SHPR_PRI_N SCB_SHPR_PRI_N_Msk /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
AnnaBridge 171:3a7713b1edbc 8780 #define SCB_SHPR_PRI_N1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 8781 #define SCB_SHPR_PRI_N1_Msk (0xFFU << SCB_SHPR_PRI_N1_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 8782 #define SCB_SHPR_PRI_N1 SCB_SHPR_PRI_N1_Msk /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
AnnaBridge 171:3a7713b1edbc 8783 #define SCB_SHPR_PRI_N2_Pos (16U)
AnnaBridge 171:3a7713b1edbc 8784 #define SCB_SHPR_PRI_N2_Msk (0xFFU << SCB_SHPR_PRI_N2_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 8785 #define SCB_SHPR_PRI_N2 SCB_SHPR_PRI_N2_Msk /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
AnnaBridge 171:3a7713b1edbc 8786 #define SCB_SHPR_PRI_N3_Pos (24U)
AnnaBridge 171:3a7713b1edbc 8787 #define SCB_SHPR_PRI_N3_Msk (0xFFU << SCB_SHPR_PRI_N3_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 8788 #define SCB_SHPR_PRI_N3 SCB_SHPR_PRI_N3_Msk /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
AnnaBridge 171:3a7713b1edbc 8789
AnnaBridge 171:3a7713b1edbc 8790 /****************** Bit definition for SCB_SHCSR register *******************/
AnnaBridge 171:3a7713b1edbc 8791 #define SCB_SHCSR_MEMFAULTACT (0x00000001U) /*!< MemManage is active */
AnnaBridge 171:3a7713b1edbc 8792 #define SCB_SHCSR_BUSFAULTACT (0x00000002U) /*!< BusFault is active */
AnnaBridge 171:3a7713b1edbc 8793 #define SCB_SHCSR_USGFAULTACT (0x00000008U) /*!< UsageFault is active */
AnnaBridge 171:3a7713b1edbc 8794 #define SCB_SHCSR_SVCALLACT (0x00000080U) /*!< SVCall is active */
AnnaBridge 171:3a7713b1edbc 8795 #define SCB_SHCSR_MONITORACT (0x00000100U) /*!< Monitor is active */
AnnaBridge 171:3a7713b1edbc 8796 #define SCB_SHCSR_PENDSVACT (0x00000400U) /*!< PendSV is active */
AnnaBridge 171:3a7713b1edbc 8797 #define SCB_SHCSR_SYSTICKACT (0x00000800U) /*!< SysTick is active */
AnnaBridge 171:3a7713b1edbc 8798 #define SCB_SHCSR_USGFAULTPENDED (0x00001000U) /*!< Usage Fault is pended */
AnnaBridge 171:3a7713b1edbc 8799 #define SCB_SHCSR_MEMFAULTPENDED (0x00002000U) /*!< MemManage is pended */
AnnaBridge 171:3a7713b1edbc 8800 #define SCB_SHCSR_BUSFAULTPENDED (0x00004000U) /*!< Bus Fault is pended */
AnnaBridge 171:3a7713b1edbc 8801 #define SCB_SHCSR_SVCALLPENDED (0x00008000U) /*!< SVCall is pended */
AnnaBridge 171:3a7713b1edbc 8802 #define SCB_SHCSR_MEMFAULTENA (0x00010000U) /*!< MemManage enable */
AnnaBridge 171:3a7713b1edbc 8803 #define SCB_SHCSR_BUSFAULTENA (0x00020000U) /*!< Bus Fault enable */
AnnaBridge 171:3a7713b1edbc 8804 #define SCB_SHCSR_USGFAULTENA (0x00040000U) /*!< UsageFault enable */
AnnaBridge 171:3a7713b1edbc 8805
AnnaBridge 171:3a7713b1edbc 8806 /******************* Bit definition for SCB_CFSR register *******************/
AnnaBridge 171:3a7713b1edbc 8807 /*!< MFSR */
AnnaBridge 171:3a7713b1edbc 8808 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
AnnaBridge 171:3a7713b1edbc 8809 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
AnnaBridge 171:3a7713b1edbc 8810 #define SCB_CFSR_IACCVIOL SCB_CFSR_IACCVIOL_Msk /*!< Instruction access violation */
AnnaBridge 171:3a7713b1edbc 8811 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
AnnaBridge 171:3a7713b1edbc 8812 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
AnnaBridge 171:3a7713b1edbc 8813 #define SCB_CFSR_DACCVIOL SCB_CFSR_DACCVIOL_Msk /*!< Data access violation */
AnnaBridge 171:3a7713b1edbc 8814 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
AnnaBridge 171:3a7713b1edbc 8815 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
AnnaBridge 171:3a7713b1edbc 8816 #define SCB_CFSR_MUNSTKERR SCB_CFSR_MUNSTKERR_Msk /*!< Unstacking error */
AnnaBridge 171:3a7713b1edbc 8817 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
AnnaBridge 171:3a7713b1edbc 8818 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
AnnaBridge 171:3a7713b1edbc 8819 #define SCB_CFSR_MSTKERR SCB_CFSR_MSTKERR_Msk /*!< Stacking error */
AnnaBridge 171:3a7713b1edbc 8820 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
AnnaBridge 171:3a7713b1edbc 8821 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
AnnaBridge 171:3a7713b1edbc 8822 #define SCB_CFSR_MMARVALID SCB_CFSR_MMARVALID_Msk /*!< Memory Manage Address Register address valid flag */
AnnaBridge 171:3a7713b1edbc 8823 /*!< BFSR */
AnnaBridge 171:3a7713b1edbc 8824 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
AnnaBridge 171:3a7713b1edbc 8825 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
AnnaBridge 171:3a7713b1edbc 8826 #define SCB_CFSR_IBUSERR SCB_CFSR_IBUSERR_Msk /*!< Instruction bus error flag */
AnnaBridge 171:3a7713b1edbc 8827 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
AnnaBridge 171:3a7713b1edbc 8828 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
AnnaBridge 171:3a7713b1edbc 8829 #define SCB_CFSR_PRECISERR SCB_CFSR_PRECISERR_Msk /*!< Precise data bus error */
AnnaBridge 171:3a7713b1edbc 8830 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
AnnaBridge 171:3a7713b1edbc 8831 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
AnnaBridge 171:3a7713b1edbc 8832 #define SCB_CFSR_IMPRECISERR SCB_CFSR_IMPRECISERR_Msk /*!< Imprecise data bus error */
AnnaBridge 171:3a7713b1edbc 8833 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
AnnaBridge 171:3a7713b1edbc 8834 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
AnnaBridge 171:3a7713b1edbc 8835 #define SCB_CFSR_UNSTKERR SCB_CFSR_UNSTKERR_Msk /*!< Unstacking error */
AnnaBridge 171:3a7713b1edbc 8836 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
AnnaBridge 171:3a7713b1edbc 8837 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
AnnaBridge 171:3a7713b1edbc 8838 #define SCB_CFSR_STKERR SCB_CFSR_STKERR_Msk /*!< Stacking error */
AnnaBridge 171:3a7713b1edbc 8839 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
AnnaBridge 171:3a7713b1edbc 8840 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
AnnaBridge 171:3a7713b1edbc 8841 #define SCB_CFSR_BFARVALID SCB_CFSR_BFARVALID_Msk /*!< Bus Fault Address Register address valid flag */
AnnaBridge 171:3a7713b1edbc 8842 /*!< UFSR */
AnnaBridge 171:3a7713b1edbc 8843 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
AnnaBridge 171:3a7713b1edbc 8844 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
AnnaBridge 171:3a7713b1edbc 8845 #define SCB_CFSR_UNDEFINSTR SCB_CFSR_UNDEFINSTR_Msk /*!< The processor attempt to excecute an undefined instruction */
AnnaBridge 171:3a7713b1edbc 8846 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
AnnaBridge 171:3a7713b1edbc 8847 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
AnnaBridge 171:3a7713b1edbc 8848 #define SCB_CFSR_INVSTATE SCB_CFSR_INVSTATE_Msk /*!< Invalid combination of EPSR and instruction */
AnnaBridge 171:3a7713b1edbc 8849 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
AnnaBridge 171:3a7713b1edbc 8850 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
AnnaBridge 171:3a7713b1edbc 8851 #define SCB_CFSR_INVPC SCB_CFSR_INVPC_Msk /*!< Attempt to load EXC_RETURN into pc illegally */
AnnaBridge 171:3a7713b1edbc 8852 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
AnnaBridge 171:3a7713b1edbc 8853 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
AnnaBridge 171:3a7713b1edbc 8854 #define SCB_CFSR_NOCP SCB_CFSR_NOCP_Msk /*!< Attempt to use a coprocessor instruction */
AnnaBridge 171:3a7713b1edbc 8855 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
AnnaBridge 171:3a7713b1edbc 8856 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
AnnaBridge 171:3a7713b1edbc 8857 #define SCB_CFSR_UNALIGNED SCB_CFSR_UNALIGNED_Msk /*!< Fault occurs when there is an attempt to make an unaligned memory access */
AnnaBridge 171:3a7713b1edbc 8858 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
AnnaBridge 171:3a7713b1edbc 8859 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
AnnaBridge 171:3a7713b1edbc 8860 #define SCB_CFSR_DIVBYZERO SCB_CFSR_DIVBYZERO_Msk /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
AnnaBridge 171:3a7713b1edbc 8861
AnnaBridge 171:3a7713b1edbc 8862 /******************* Bit definition for SCB_HFSR register *******************/
AnnaBridge 171:3a7713b1edbc 8863 #define SCB_HFSR_VECTTBL (0x00000002U) /*!< Fault occures because of vector table read on exception processing */
AnnaBridge 171:3a7713b1edbc 8864 #define SCB_HFSR_FORCED (0x40000000U) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
AnnaBridge 171:3a7713b1edbc 8865 #define SCB_HFSR_DEBUGEVT (0x80000000U) /*!< Fault related to debug */
AnnaBridge 171:3a7713b1edbc 8866
AnnaBridge 171:3a7713b1edbc 8867 /******************* Bit definition for SCB_DFSR register *******************/
AnnaBridge 171:3a7713b1edbc 8868 #define SCB_DFSR_HALTED (0x00000001U) /*!< Halt request flag */
AnnaBridge 171:3a7713b1edbc 8869 #define SCB_DFSR_BKPT (0x00000002U) /*!< BKPT flag */
AnnaBridge 171:3a7713b1edbc 8870 #define SCB_DFSR_DWTTRAP (0x00000004U) /*!< Data Watchpoint and Trace (DWT) flag */
AnnaBridge 171:3a7713b1edbc 8871 #define SCB_DFSR_VCATCH (0x00000008U) /*!< Vector catch flag */
AnnaBridge 171:3a7713b1edbc 8872 #define SCB_DFSR_EXTERNAL (0x00000010U) /*!< External debug request flag */
AnnaBridge 171:3a7713b1edbc 8873
AnnaBridge 171:3a7713b1edbc 8874 /******************* Bit definition for SCB_MMFAR register ******************/
AnnaBridge 171:3a7713b1edbc 8875 #define SCB_MMFAR_ADDRESS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8876 #define SCB_MMFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 8877 #define SCB_MMFAR_ADDRESS SCB_MMFAR_ADDRESS_Msk /*!< Mem Manage fault address field */
AnnaBridge 171:3a7713b1edbc 8878
AnnaBridge 171:3a7713b1edbc 8879 /******************* Bit definition for SCB_BFAR register *******************/
AnnaBridge 171:3a7713b1edbc 8880 #define SCB_BFAR_ADDRESS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8881 #define SCB_BFAR_ADDRESS_Msk (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 8882 #define SCB_BFAR_ADDRESS SCB_BFAR_ADDRESS_Msk /*!< Bus fault address field */
AnnaBridge 171:3a7713b1edbc 8883
AnnaBridge 171:3a7713b1edbc 8884 /******************* Bit definition for SCB_afsr register *******************/
AnnaBridge 171:3a7713b1edbc 8885 #define SCB_AFSR_IMPDEF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 8886 #define SCB_AFSR_IMPDEF_Msk (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 8887 #define SCB_AFSR_IMPDEF SCB_AFSR_IMPDEF_Msk /*!< Implementation defined */
AnnaBridge 171:3a7713b1edbc 8888 /**
AnnaBridge 171:3a7713b1edbc 8889 * @}
AnnaBridge 171:3a7713b1edbc 8890 */
AnnaBridge 171:3a7713b1edbc 8891
AnnaBridge 171:3a7713b1edbc 8892 /**
AnnaBridge 171:3a7713b1edbc 8893 * @}
AnnaBridge 171:3a7713b1edbc 8894 */
AnnaBridge 171:3a7713b1edbc 8895 /** @addtogroup Exported_macro
AnnaBridge 171:3a7713b1edbc 8896 * @{
AnnaBridge 171:3a7713b1edbc 8897 */
AnnaBridge 171:3a7713b1edbc 8898
AnnaBridge 171:3a7713b1edbc 8899 /****************************** ADC Instances *********************************/
AnnaBridge 171:3a7713b1edbc 8900 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
AnnaBridge 171:3a7713b1edbc 8901
AnnaBridge 171:3a7713b1edbc 8902 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
AnnaBridge 171:3a7713b1edbc 8903
AnnaBridge 171:3a7713b1edbc 8904 /******************************** COMP Instances ******************************/
AnnaBridge 171:3a7713b1edbc 8905 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
AnnaBridge 171:3a7713b1edbc 8906 ((INSTANCE) == COMP2))
AnnaBridge 171:3a7713b1edbc 8907
AnnaBridge 171:3a7713b1edbc 8908 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
AnnaBridge 171:3a7713b1edbc 8909
AnnaBridge 171:3a7713b1edbc 8910 /****************************** CRC Instances *********************************/
AnnaBridge 171:3a7713b1edbc 8911 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
AnnaBridge 171:3a7713b1edbc 8912
AnnaBridge 171:3a7713b1edbc 8913 /****************************** DAC Instances *********************************/
AnnaBridge 171:3a7713b1edbc 8914 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
AnnaBridge 171:3a7713b1edbc 8915
AnnaBridge 171:3a7713b1edbc 8916 /****************************** DMA Instances *********************************/
AnnaBridge 171:3a7713b1edbc 8917 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
AnnaBridge 171:3a7713b1edbc 8918 ((INSTANCE) == DMA1_Channel2) || \
AnnaBridge 171:3a7713b1edbc 8919 ((INSTANCE) == DMA1_Channel3) || \
AnnaBridge 171:3a7713b1edbc 8920 ((INSTANCE) == DMA1_Channel4) || \
AnnaBridge 171:3a7713b1edbc 8921 ((INSTANCE) == DMA1_Channel5) || \
AnnaBridge 171:3a7713b1edbc 8922 ((INSTANCE) == DMA1_Channel6) || \
AnnaBridge 171:3a7713b1edbc 8923 ((INSTANCE) == DMA1_Channel7) || \
AnnaBridge 171:3a7713b1edbc 8924 ((INSTANCE) == DMA2_Channel1) || \
AnnaBridge 171:3a7713b1edbc 8925 ((INSTANCE) == DMA2_Channel2) || \
AnnaBridge 171:3a7713b1edbc 8926 ((INSTANCE) == DMA2_Channel3) || \
AnnaBridge 171:3a7713b1edbc 8927 ((INSTANCE) == DMA2_Channel4) || \
AnnaBridge 171:3a7713b1edbc 8928 ((INSTANCE) == DMA2_Channel5))
AnnaBridge 171:3a7713b1edbc 8929
AnnaBridge 171:3a7713b1edbc 8930 /******************************* GPIO Instances *******************************/
AnnaBridge 171:3a7713b1edbc 8931 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
AnnaBridge 171:3a7713b1edbc 8932 ((INSTANCE) == GPIOB) || \
AnnaBridge 171:3a7713b1edbc 8933 ((INSTANCE) == GPIOC) || \
AnnaBridge 171:3a7713b1edbc 8934 ((INSTANCE) == GPIOD) || \
AnnaBridge 171:3a7713b1edbc 8935 ((INSTANCE) == GPIOE) || \
AnnaBridge 171:3a7713b1edbc 8936 ((INSTANCE) == GPIOH))
AnnaBridge 171:3a7713b1edbc 8937
AnnaBridge 171:3a7713b1edbc 8938 /**************************** GPIO Alternate Function Instances ***************/
AnnaBridge 171:3a7713b1edbc 8939 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
AnnaBridge 171:3a7713b1edbc 8940
AnnaBridge 171:3a7713b1edbc 8941 /**************************** GPIO Lock Instances *****************************/
AnnaBridge 171:3a7713b1edbc 8942 /* On L1, all GPIO Bank support the Lock mechanism */
AnnaBridge 171:3a7713b1edbc 8943 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
AnnaBridge 171:3a7713b1edbc 8944
AnnaBridge 171:3a7713b1edbc 8945 /******************************** I2C Instances *******************************/
AnnaBridge 171:3a7713b1edbc 8946 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
AnnaBridge 171:3a7713b1edbc 8947 ((INSTANCE) == I2C2))
AnnaBridge 171:3a7713b1edbc 8948
AnnaBridge 171:3a7713b1edbc 8949 /****************************** SMBUS Instances *******************************/
AnnaBridge 171:3a7713b1edbc 8950 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
AnnaBridge 171:3a7713b1edbc 8951
AnnaBridge 171:3a7713b1edbc 8952 /******************************** I2S Instances *******************************/
AnnaBridge 171:3a7713b1edbc 8953 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
AnnaBridge 171:3a7713b1edbc 8954 ((INSTANCE) == SPI3))
AnnaBridge 171:3a7713b1edbc 8955 /****************************** IWDG Instances ********************************/
AnnaBridge 171:3a7713b1edbc 8956 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
AnnaBridge 171:3a7713b1edbc 8957
AnnaBridge 171:3a7713b1edbc 8958 /****************************** OPAMP Instances *******************************/
AnnaBridge 171:3a7713b1edbc 8959 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
AnnaBridge 171:3a7713b1edbc 8960 ((INSTANCE) == OPAMP2))
AnnaBridge 171:3a7713b1edbc 8961
AnnaBridge 171:3a7713b1edbc 8962 #define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
AnnaBridge 171:3a7713b1edbc 8963
AnnaBridge 171:3a7713b1edbc 8964 /****************************** RTC Instances *********************************/
AnnaBridge 171:3a7713b1edbc 8965 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
AnnaBridge 171:3a7713b1edbc 8966
AnnaBridge 171:3a7713b1edbc 8967 /******************************** SPI Instances *******************************/
AnnaBridge 171:3a7713b1edbc 8968 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
AnnaBridge 171:3a7713b1edbc 8969 ((INSTANCE) == SPI2) || \
AnnaBridge 171:3a7713b1edbc 8970 ((INSTANCE) == SPI3))
AnnaBridge 171:3a7713b1edbc 8971
AnnaBridge 171:3a7713b1edbc 8972 /****************************** TIM Instances *********************************/
AnnaBridge 171:3a7713b1edbc 8973 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 8974 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 8975 ((INSTANCE) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 8976 ((INSTANCE) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 8977 ((INSTANCE) == TIM6) || \
AnnaBridge 171:3a7713b1edbc 8978 ((INSTANCE) == TIM7) || \
AnnaBridge 171:3a7713b1edbc 8979 ((INSTANCE) == TIM9) || \
AnnaBridge 171:3a7713b1edbc 8980 ((INSTANCE) == TIM10) || \
AnnaBridge 171:3a7713b1edbc 8981 ((INSTANCE) == TIM11))
AnnaBridge 171:3a7713b1edbc 8982
AnnaBridge 171:3a7713b1edbc 8983 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 8984 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 8985 ((INSTANCE) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 8986 ((INSTANCE) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 8987 ((INSTANCE) == TIM9) || \
AnnaBridge 171:3a7713b1edbc 8988 ((INSTANCE) == TIM10) || \
AnnaBridge 171:3a7713b1edbc 8989 ((INSTANCE) == TIM11))
AnnaBridge 171:3a7713b1edbc 8990
AnnaBridge 171:3a7713b1edbc 8991 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 8992 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 8993 ((INSTANCE) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 8994 ((INSTANCE) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 8995 ((INSTANCE) == TIM9))
AnnaBridge 171:3a7713b1edbc 8996
AnnaBridge 171:3a7713b1edbc 8997 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 8998 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 8999 ((INSTANCE) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 9000 ((INSTANCE) == TIM5))
AnnaBridge 171:3a7713b1edbc 9001
AnnaBridge 171:3a7713b1edbc 9002 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 9003 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 9004 ((INSTANCE) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 9005 ((INSTANCE) == TIM5))
AnnaBridge 171:3a7713b1edbc 9006
AnnaBridge 171:3a7713b1edbc 9007 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 9008 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 9009 ((INSTANCE) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 9010 ((INSTANCE) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 9011 ((INSTANCE) == TIM9))
AnnaBridge 171:3a7713b1edbc 9012
AnnaBridge 171:3a7713b1edbc 9013 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 9014 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 9015 ((INSTANCE) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 9016 ((INSTANCE) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 9017 ((INSTANCE) == TIM9) || \
AnnaBridge 171:3a7713b1edbc 9018 ((INSTANCE) == TIM10) || \
AnnaBridge 171:3a7713b1edbc 9019 ((INSTANCE) == TIM11))
AnnaBridge 171:3a7713b1edbc 9020
AnnaBridge 171:3a7713b1edbc 9021 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 9022 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 9023 ((INSTANCE) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 9024 ((INSTANCE) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 9025 ((INSTANCE) == TIM9))
AnnaBridge 171:3a7713b1edbc 9026
AnnaBridge 171:3a7713b1edbc 9027 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 9028 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 9029 ((INSTANCE) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 9030 ((INSTANCE) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 9031 ((INSTANCE) == TIM9))
AnnaBridge 171:3a7713b1edbc 9032
AnnaBridge 171:3a7713b1edbc 9033 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 9034 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 9035 ((INSTANCE) == TIM4))
AnnaBridge 171:3a7713b1edbc 9036
AnnaBridge 171:3a7713b1edbc 9037 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 9038 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 9039 ((INSTANCE) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 9040 ((INSTANCE) == TIM5))
AnnaBridge 171:3a7713b1edbc 9041
AnnaBridge 171:3a7713b1edbc 9042 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 9043 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 9044 ((INSTANCE) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 9045 ((INSTANCE) == TIM5))
AnnaBridge 171:3a7713b1edbc 9046
AnnaBridge 171:3a7713b1edbc 9047
AnnaBridge 171:3a7713b1edbc 9048 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 9049 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 9050 ((INSTANCE) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 9051 ((INSTANCE) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 9052 ((INSTANCE) == TIM6) || \
AnnaBridge 171:3a7713b1edbc 9053 ((INSTANCE) == TIM7) || \
AnnaBridge 171:3a7713b1edbc 9054 ((INSTANCE) == TIM9))
AnnaBridge 171:3a7713b1edbc 9055
AnnaBridge 171:3a7713b1edbc 9056 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 9057 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 9058 ((INSTANCE) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 9059 ((INSTANCE) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 9060 ((INSTANCE) == TIM9))
AnnaBridge 171:3a7713b1edbc 9061
AnnaBridge 171:3a7713b1edbc 9062 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5)
AnnaBridge 171:3a7713b1edbc 9063
AnnaBridge 171:3a7713b1edbc 9064 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 9065 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 9066 ((INSTANCE) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 9067 ((INSTANCE) == TIM5))
AnnaBridge 171:3a7713b1edbc 9068
AnnaBridge 171:3a7713b1edbc 9069 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
AnnaBridge 171:3a7713b1edbc 9070 ((((INSTANCE) == TIM2) && \
AnnaBridge 171:3a7713b1edbc 9071 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 9072 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 171:3a7713b1edbc 9073 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 171:3a7713b1edbc 9074 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 171:3a7713b1edbc 9075 || \
AnnaBridge 171:3a7713b1edbc 9076 (((INSTANCE) == TIM3) && \
AnnaBridge 171:3a7713b1edbc 9077 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 9078 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 171:3a7713b1edbc 9079 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 171:3a7713b1edbc 9080 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 171:3a7713b1edbc 9081 || \
AnnaBridge 171:3a7713b1edbc 9082 (((INSTANCE) == TIM4) && \
AnnaBridge 171:3a7713b1edbc 9083 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 9084 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 171:3a7713b1edbc 9085 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 171:3a7713b1edbc 9086 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 171:3a7713b1edbc 9087 || \
AnnaBridge 171:3a7713b1edbc 9088 (((INSTANCE) == TIM5) && \
AnnaBridge 171:3a7713b1edbc 9089 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 9090 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 171:3a7713b1edbc 9091 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 171:3a7713b1edbc 9092 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 171:3a7713b1edbc 9093 || \
AnnaBridge 171:3a7713b1edbc 9094 (((INSTANCE) == TIM9) && \
AnnaBridge 171:3a7713b1edbc 9095 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 9096 ((CHANNEL) == TIM_CHANNEL_2))) \
AnnaBridge 171:3a7713b1edbc 9097 || \
AnnaBridge 171:3a7713b1edbc 9098 (((INSTANCE) == TIM10) && \
AnnaBridge 171:3a7713b1edbc 9099 (((CHANNEL) == TIM_CHANNEL_1))) \
AnnaBridge 171:3a7713b1edbc 9100 || \
AnnaBridge 171:3a7713b1edbc 9101 (((INSTANCE) == TIM11) && \
AnnaBridge 171:3a7713b1edbc 9102 (((CHANNEL) == TIM_CHANNEL_1))))
AnnaBridge 171:3a7713b1edbc 9103
AnnaBridge 171:3a7713b1edbc 9104 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 9105 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 9106 ((INSTANCE) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 9107 ((INSTANCE) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 9108 ((INSTANCE) == TIM9) || \
AnnaBridge 171:3a7713b1edbc 9109 ((INSTANCE) == TIM10) || \
AnnaBridge 171:3a7713b1edbc 9110 ((INSTANCE) == TIM11))
AnnaBridge 171:3a7713b1edbc 9111
AnnaBridge 171:3a7713b1edbc 9112 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 9113 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 9114 ((INSTANCE) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 9115 ((INSTANCE) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 9116 ((INSTANCE) == TIM6) || \
AnnaBridge 171:3a7713b1edbc 9117 ((INSTANCE) == TIM7))
AnnaBridge 171:3a7713b1edbc 9118
AnnaBridge 171:3a7713b1edbc 9119 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 9120 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 9121 ((INSTANCE) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 9122 ((INSTANCE) == TIM5))
AnnaBridge 171:3a7713b1edbc 9123
AnnaBridge 171:3a7713b1edbc 9124 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 9125 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 9126 ((INSTANCE) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 9127 ((INSTANCE) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 9128 ((INSTANCE) == TIM9))
AnnaBridge 171:3a7713b1edbc 9129
AnnaBridge 171:3a7713b1edbc 9130 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 9131 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 9132 ((INSTANCE) == TIM4) || \
AnnaBridge 171:3a7713b1edbc 9133 ((INSTANCE) == TIM5) || \
AnnaBridge 171:3a7713b1edbc 9134 ((INSTANCE) == TIM9))
AnnaBridge 171:3a7713b1edbc 9135
AnnaBridge 171:3a7713b1edbc 9136 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 9137 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 9138 ((INSTANCE) == TIM9) || \
AnnaBridge 171:3a7713b1edbc 9139 ((INSTANCE) == TIM10) || \
AnnaBridge 171:3a7713b1edbc 9140 ((INSTANCE) == TIM11))
AnnaBridge 171:3a7713b1edbc 9141
AnnaBridge 171:3a7713b1edbc 9142 /******************** USART Instances : Synchronous mode **********************/
AnnaBridge 171:3a7713b1edbc 9143 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 171:3a7713b1edbc 9144 ((INSTANCE) == USART2) || \
AnnaBridge 171:3a7713b1edbc 9145 ((INSTANCE) == USART3))
AnnaBridge 171:3a7713b1edbc 9146
AnnaBridge 171:3a7713b1edbc 9147 /******************** UART Instances : Asynchronous mode **********************/
AnnaBridge 171:3a7713b1edbc 9148 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 171:3a7713b1edbc 9149 ((INSTANCE) == USART2) || \
AnnaBridge 171:3a7713b1edbc 9150 ((INSTANCE) == USART3))
AnnaBridge 171:3a7713b1edbc 9151
AnnaBridge 171:3a7713b1edbc 9152 /******************** UART Instances : Half-Duplex mode **********************/
AnnaBridge 171:3a7713b1edbc 9153 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 171:3a7713b1edbc 9154 ((INSTANCE) == USART2) || \
AnnaBridge 171:3a7713b1edbc 9155 ((INSTANCE) == USART3))
AnnaBridge 171:3a7713b1edbc 9156
AnnaBridge 171:3a7713b1edbc 9157 /******************** UART Instances : LIN mode **********************/
AnnaBridge 171:3a7713b1edbc 9158 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 171:3a7713b1edbc 9159 ((INSTANCE) == USART2) || \
AnnaBridge 171:3a7713b1edbc 9160 ((INSTANCE) == USART3))
AnnaBridge 171:3a7713b1edbc 9161
AnnaBridge 171:3a7713b1edbc 9162 /****************** UART Instances : Hardware Flow control ********************/
AnnaBridge 171:3a7713b1edbc 9163 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 171:3a7713b1edbc 9164 ((INSTANCE) == USART2) || \
AnnaBridge 171:3a7713b1edbc 9165 ((INSTANCE) == USART3))
AnnaBridge 171:3a7713b1edbc 9166
AnnaBridge 171:3a7713b1edbc 9167 /********************* UART Instances : Smard card mode ***********************/
AnnaBridge 171:3a7713b1edbc 9168 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 171:3a7713b1edbc 9169 ((INSTANCE) == USART2) || \
AnnaBridge 171:3a7713b1edbc 9170 ((INSTANCE) == USART3))
AnnaBridge 171:3a7713b1edbc 9171
AnnaBridge 171:3a7713b1edbc 9172 /*********************** UART Instances : IRDA mode ***************************/
AnnaBridge 171:3a7713b1edbc 9173 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 171:3a7713b1edbc 9174 ((INSTANCE) == USART2) || \
AnnaBridge 171:3a7713b1edbc 9175 ((INSTANCE) == USART3))
AnnaBridge 171:3a7713b1edbc 9176
AnnaBridge 171:3a7713b1edbc 9177 /***************** UART Instances : Multi-Processor mode **********************/
AnnaBridge 171:3a7713b1edbc 9178 #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
AnnaBridge 171:3a7713b1edbc 9179 ((INSTANCE) == USART2) || \
AnnaBridge 171:3a7713b1edbc 9180 ((INSTANCE) == USART3))
AnnaBridge 171:3a7713b1edbc 9181
AnnaBridge 171:3a7713b1edbc 9182 /****************************** WWDG Instances ********************************/
AnnaBridge 171:3a7713b1edbc 9183 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
AnnaBridge 171:3a7713b1edbc 9184
AnnaBridge 171:3a7713b1edbc 9185
AnnaBridge 171:3a7713b1edbc 9186 /****************************** LCD Instances ********************************/
AnnaBridge 171:3a7713b1edbc 9187 #define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
AnnaBridge 171:3a7713b1edbc 9188
AnnaBridge 171:3a7713b1edbc 9189 /****************************** USB Instances ********************************/
AnnaBridge 171:3a7713b1edbc 9190 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
AnnaBridge 171:3a7713b1edbc 9191
AnnaBridge 171:3a7713b1edbc 9192 /**
AnnaBridge 171:3a7713b1edbc 9193 * @}
AnnaBridge 171:3a7713b1edbc 9194 */
AnnaBridge 171:3a7713b1edbc 9195
AnnaBridge 171:3a7713b1edbc 9196 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 9197 /* For a painless codes migration between the STM32L1xx device product */
AnnaBridge 171:3a7713b1edbc 9198 /* lines, the aliases defined below are put in place to overcome the */
AnnaBridge 171:3a7713b1edbc 9199 /* differences in the interrupt handlers and IRQn definitions. */
AnnaBridge 171:3a7713b1edbc 9200 /* No need to update developed interrupt code when moving across */
AnnaBridge 171:3a7713b1edbc 9201 /* product lines within the same STM32L1 Family */
AnnaBridge 171:3a7713b1edbc 9202 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 9203
AnnaBridge 171:3a7713b1edbc 9204 /* Aliases for __IRQn */
AnnaBridge 171:3a7713b1edbc 9205
AnnaBridge 171:3a7713b1edbc 9206 /* Aliases for __IRQHandler */
AnnaBridge 171:3a7713b1edbc 9207
AnnaBridge 171:3a7713b1edbc 9208 /**
AnnaBridge 171:3a7713b1edbc 9209 * @}
AnnaBridge 171:3a7713b1edbc 9210 */
AnnaBridge 171:3a7713b1edbc 9211
AnnaBridge 171:3a7713b1edbc 9212 /**
AnnaBridge 171:3a7713b1edbc 9213 * @}
AnnaBridge 171:3a7713b1edbc 9214 */
AnnaBridge 171:3a7713b1edbc 9215
AnnaBridge 171:3a7713b1edbc 9216 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 9217 }
AnnaBridge 171:3a7713b1edbc 9218 #endif /* __cplusplus */
AnnaBridge 171:3a7713b1edbc 9219
AnnaBridge 171:3a7713b1edbc 9220 #endif /* __STM32L152xC_H */
AnnaBridge 171:3a7713b1edbc 9221
AnnaBridge 171:3a7713b1edbc 9222
AnnaBridge 171:3a7713b1edbc 9223
AnnaBridge 171:3a7713b1edbc 9224 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/