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TARGET_MOTE_L152RC/TOOLCHAIN_GCC_ARM/stm32l1xx_ll_i2c.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file stm32l1xx_ll_i2c.h
AnnaBridge 171:3a7713b1edbc 4 * @author MCD Application Team
AnnaBridge 171:3a7713b1edbc 5 * @brief Header file of I2C LL module.
AnnaBridge 171:3a7713b1edbc 6 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 7 * @attention
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 12 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 14 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 17 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 171:3a7713b1edbc 19 * may be used to endorse or promote products derived from this software
AnnaBridge 171:3a7713b1edbc 20 * without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 171:3a7713b1edbc 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 171:3a7713b1edbc 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 171:3a7713b1edbc 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 171:3a7713b1edbc 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 171:3a7713b1edbc 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 171:3a7713b1edbc 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 171:3a7713b1edbc 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 32 *
AnnaBridge 171:3a7713b1edbc 33 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 34 */
AnnaBridge 171:3a7713b1edbc 35
AnnaBridge 171:3a7713b1edbc 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 171:3a7713b1edbc 37 #ifndef __STM32L1xx_LL_I2C_H
AnnaBridge 171:3a7713b1edbc 38 #define __STM32L1xx_LL_I2C_H
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 41 extern "C" {
AnnaBridge 171:3a7713b1edbc 42 #endif
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 /* Includes ------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 45 #include "stm32l1xx.h"
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /** @addtogroup STM32L1xx_LL_Driver
AnnaBridge 171:3a7713b1edbc 48 * @{
AnnaBridge 171:3a7713b1edbc 49 */
AnnaBridge 171:3a7713b1edbc 50
AnnaBridge 171:3a7713b1edbc 51 #if defined (I2C1) || defined (I2C2)
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 /** @defgroup I2C_LL I2C
AnnaBridge 171:3a7713b1edbc 54 * @{
AnnaBridge 171:3a7713b1edbc 55 */
AnnaBridge 171:3a7713b1edbc 56
AnnaBridge 171:3a7713b1edbc 57 /* Private types -------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 58 /* Private variables ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 59
AnnaBridge 171:3a7713b1edbc 60 /* Private constants ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 61 /** @defgroup I2C_LL_Private_Constants I2C Private Constants
AnnaBridge 171:3a7713b1edbc 62 * @{
AnnaBridge 171:3a7713b1edbc 63 */
AnnaBridge 171:3a7713b1edbc 64
AnnaBridge 171:3a7713b1edbc 65 /* Defines used to perform compute and check in the macros */
AnnaBridge 171:3a7713b1edbc 66 #define LL_I2C_MAX_SPEED_STANDARD 100000U
AnnaBridge 171:3a7713b1edbc 67 #define LL_I2C_MAX_SPEED_FAST 400000U
AnnaBridge 171:3a7713b1edbc 68 /**
AnnaBridge 171:3a7713b1edbc 69 * @}
AnnaBridge 171:3a7713b1edbc 70 */
AnnaBridge 171:3a7713b1edbc 71
AnnaBridge 171:3a7713b1edbc 72 /* Private macros ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 73 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 171:3a7713b1edbc 74 /** @defgroup I2C_LL_Private_Macros I2C Private Macros
AnnaBridge 171:3a7713b1edbc 75 * @{
AnnaBridge 171:3a7713b1edbc 76 */
AnnaBridge 171:3a7713b1edbc 77 /**
AnnaBridge 171:3a7713b1edbc 78 * @}
AnnaBridge 171:3a7713b1edbc 79 */
AnnaBridge 171:3a7713b1edbc 80 #endif /*USE_FULL_LL_DRIVER*/
AnnaBridge 171:3a7713b1edbc 81
AnnaBridge 171:3a7713b1edbc 82 /* Exported types ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 83 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 171:3a7713b1edbc 84 /** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
AnnaBridge 171:3a7713b1edbc 85 * @{
AnnaBridge 171:3a7713b1edbc 86 */
AnnaBridge 171:3a7713b1edbc 87 typedef struct
AnnaBridge 171:3a7713b1edbc 88 {
AnnaBridge 171:3a7713b1edbc 89 uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
AnnaBridge 171:3a7713b1edbc 90 This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
AnnaBridge 171:3a7713b1edbc 91
AnnaBridge 171:3a7713b1edbc 92 This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
AnnaBridge 171:3a7713b1edbc 93
AnnaBridge 171:3a7713b1edbc 94 uint32_t ClockSpeed; /*!< Specifies the clock frequency.
AnnaBridge 171:3a7713b1edbc 95 This parameter must be set to a value lower than 400kHz (in Hz)
AnnaBridge 171:3a7713b1edbc 96
AnnaBridge 171:3a7713b1edbc 97 This feature can be modified afterwards using unitary function @ref LL_I2C_SetClockPeriod()
AnnaBridge 171:3a7713b1edbc 98 or @ref LL_I2C_SetDutyCycle() or @ref LL_I2C_SetClockSpeedMode() or @ref LL_I2C_ConfigSpeed(). */
AnnaBridge 171:3a7713b1edbc 99
AnnaBridge 171:3a7713b1edbc 100 uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
AnnaBridge 171:3a7713b1edbc 101 This parameter can be a value of @ref I2C_LL_EC_DUTYCYCLE
AnnaBridge 171:3a7713b1edbc 102
AnnaBridge 171:3a7713b1edbc 103 This feature can be modified afterwards using unitary function @ref LL_I2C_SetDutyCycle(). */
AnnaBridge 171:3a7713b1edbc 104
AnnaBridge 171:3a7713b1edbc 105 uint32_t OwnAddress1; /*!< Specifies the device own address 1.
AnnaBridge 171:3a7713b1edbc 106 This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
AnnaBridge 171:3a7713b1edbc 107
AnnaBridge 171:3a7713b1edbc 108 This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
AnnaBridge 171:3a7713b1edbc 109
AnnaBridge 171:3a7713b1edbc 110 uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
AnnaBridge 171:3a7713b1edbc 111 This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
AnnaBridge 171:3a7713b1edbc 112
AnnaBridge 171:3a7713b1edbc 113 This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
AnnaBridge 171:3a7713b1edbc 114
AnnaBridge 171:3a7713b1edbc 115 uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
AnnaBridge 171:3a7713b1edbc 116 This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
AnnaBridge 171:3a7713b1edbc 117
AnnaBridge 171:3a7713b1edbc 118 This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
AnnaBridge 171:3a7713b1edbc 119 } LL_I2C_InitTypeDef;
AnnaBridge 171:3a7713b1edbc 120 /**
AnnaBridge 171:3a7713b1edbc 121 * @}
AnnaBridge 171:3a7713b1edbc 122 */
AnnaBridge 171:3a7713b1edbc 123 #endif /*USE_FULL_LL_DRIVER*/
AnnaBridge 171:3a7713b1edbc 124
AnnaBridge 171:3a7713b1edbc 125 /* Exported constants --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 126 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
AnnaBridge 171:3a7713b1edbc 127 * @{
AnnaBridge 171:3a7713b1edbc 128 */
AnnaBridge 171:3a7713b1edbc 129
AnnaBridge 171:3a7713b1edbc 130 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge 171:3a7713b1edbc 131 * @brief Flags defines which can be used with LL_I2C_ReadReg function
AnnaBridge 171:3a7713b1edbc 132 * @{
AnnaBridge 171:3a7713b1edbc 133 */
AnnaBridge 171:3a7713b1edbc 134 #define LL_I2C_SR1_SB I2C_SR1_SB /*!< Start Bit (master mode) */
AnnaBridge 171:3a7713b1edbc 135 #define LL_I2C_SR1_ADDR I2C_SR1_ADDR /*!< Address sent (master mode) or
AnnaBridge 171:3a7713b1edbc 136 Address matched flag (slave mode) */
AnnaBridge 171:3a7713b1edbc 137 #define LL_I2C_SR1_BTF I2C_SR1_BTF /*!< Byte Transfer Finished flag */
AnnaBridge 171:3a7713b1edbc 138 #define LL_I2C_SR1_ADD10 I2C_SR1_ADD10 /*!< 10-bit header sent (master mode) */
AnnaBridge 171:3a7713b1edbc 139 #define LL_I2C_SR1_STOPF I2C_SR1_STOPF /*!< Stop detection flag (slave mode) */
AnnaBridge 171:3a7713b1edbc 140 #define LL_I2C_SR1_RXNE I2C_SR1_RXNE /*!< Data register not empty (receivers) */
AnnaBridge 171:3a7713b1edbc 141 #define LL_I2C_SR1_TXE I2C_SR1_TXE /*!< Data register empty (transmitters) */
AnnaBridge 171:3a7713b1edbc 142 #define LL_I2C_SR1_BERR I2C_SR1_BERR /*!< Bus error */
AnnaBridge 171:3a7713b1edbc 143 #define LL_I2C_SR1_ARLO I2C_SR1_ARLO /*!< Arbitration lost */
AnnaBridge 171:3a7713b1edbc 144 #define LL_I2C_SR1_AF I2C_SR1_AF /*!< Acknowledge failure flag */
AnnaBridge 171:3a7713b1edbc 145 #define LL_I2C_SR1_OVR I2C_SR1_OVR /*!< Overrun/Underrun */
AnnaBridge 171:3a7713b1edbc 146 #define LL_I2C_SR1_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */
AnnaBridge 171:3a7713b1edbc 147 #define LL_I2C_SR1_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */
AnnaBridge 171:3a7713b1edbc 148 #define LL_I2C_SR1_SMALERT I2C_ISR_SMALERT /*!< SMBus alert (SMBus mode) */
AnnaBridge 171:3a7713b1edbc 149 #define LL_I2C_SR2_MSL I2C_SR2_MSL /*!< Master/Slave flag */
AnnaBridge 171:3a7713b1edbc 150 #define LL_I2C_SR2_BUSY I2C_SR2_BUSY /*!< Bus busy flag */
AnnaBridge 171:3a7713b1edbc 151 #define LL_I2C_SR2_TRA I2C_SR2_TRA /*!< Transmitter/receiver direction */
AnnaBridge 171:3a7713b1edbc 152 #define LL_I2C_SR2_GENCALL I2C_SR2_GENCALL /*!< General call address (Slave mode) */
AnnaBridge 171:3a7713b1edbc 153 #define LL_I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT /*!< SMBus Device default address (Slave mode) */
AnnaBridge 171:3a7713b1edbc 154 #define LL_I2C_SR2_SMBHOST I2C_SR2_SMBHOST /*!< SMBus Host address (Slave mode) */
AnnaBridge 171:3a7713b1edbc 155 #define LL_I2C_SR2_DUALF I2C_SR2_DUALF /*!< Dual flag (Slave mode) */
AnnaBridge 171:3a7713b1edbc 156 /**
AnnaBridge 171:3a7713b1edbc 157 * @}
AnnaBridge 171:3a7713b1edbc 158 */
AnnaBridge 171:3a7713b1edbc 159
AnnaBridge 171:3a7713b1edbc 160 /** @defgroup I2C_LL_EC_IT IT Defines
AnnaBridge 171:3a7713b1edbc 161 * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
AnnaBridge 171:3a7713b1edbc 162 * @{
AnnaBridge 171:3a7713b1edbc 163 */
AnnaBridge 171:3a7713b1edbc 164 #define LL_I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN /*!< Events interrupts enable */
AnnaBridge 171:3a7713b1edbc 165 #define LL_I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN /*!< Buffer interrupts enable */
AnnaBridge 171:3a7713b1edbc 166 #define LL_I2C_CR2_ITERREN I2C_CR2_ITERREN /*!< Error interrupts enable */
AnnaBridge 171:3a7713b1edbc 167 /**
AnnaBridge 171:3a7713b1edbc 168 * @}
AnnaBridge 171:3a7713b1edbc 169 */
AnnaBridge 171:3a7713b1edbc 170
AnnaBridge 171:3a7713b1edbc 171 /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
AnnaBridge 171:3a7713b1edbc 172 * @{
AnnaBridge 171:3a7713b1edbc 173 */
AnnaBridge 171:3a7713b1edbc 174 #define LL_I2C_OWNADDRESS1_7BIT 0x00004000U /*!< Own address 1 is a 7-bit address. */
AnnaBridge 171:3a7713b1edbc 175 #define LL_I2C_OWNADDRESS1_10BIT (uint32_t)(I2C_OAR1_ADDMODE | 0x00004000U) /*!< Own address 1 is a 10-bit address. */
AnnaBridge 171:3a7713b1edbc 176 /**
AnnaBridge 171:3a7713b1edbc 177 * @}
AnnaBridge 171:3a7713b1edbc 178 */
AnnaBridge 171:3a7713b1edbc 179
AnnaBridge 171:3a7713b1edbc 180 /** @defgroup I2C_LL_EC_DUTYCYCLE Fast Mode Duty Cycle
AnnaBridge 171:3a7713b1edbc 181 * @{
AnnaBridge 171:3a7713b1edbc 182 */
AnnaBridge 171:3a7713b1edbc 183 #define LL_I2C_DUTYCYCLE_2 0x00000000U /*!< I2C fast mode Tlow/Thigh = 2 */
AnnaBridge 171:3a7713b1edbc 184 #define LL_I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY /*!< I2C fast mode Tlow/Thigh = 16/9 */
AnnaBridge 171:3a7713b1edbc 185 /**
AnnaBridge 171:3a7713b1edbc 186 * @}
AnnaBridge 171:3a7713b1edbc 187 */
AnnaBridge 171:3a7713b1edbc 188
AnnaBridge 171:3a7713b1edbc 189 /** @defgroup I2C_LL_EC_CLOCK_SPEED_MODE Master Clock Speed Mode
AnnaBridge 171:3a7713b1edbc 190 * @{
AnnaBridge 171:3a7713b1edbc 191 */
AnnaBridge 171:3a7713b1edbc 192 #define LL_I2C_CLOCK_SPEED_STANDARD_MODE 0x00000000U /*!< Master clock speed range is standard mode */
AnnaBridge 171:3a7713b1edbc 193 #define LL_I2C_CLOCK_SPEED_FAST_MODE I2C_CCR_FS /*!< Master clock speed range is fast mode */
AnnaBridge 171:3a7713b1edbc 194 /**
AnnaBridge 171:3a7713b1edbc 195 * @}
AnnaBridge 171:3a7713b1edbc 196 */
AnnaBridge 171:3a7713b1edbc 197
AnnaBridge 171:3a7713b1edbc 198 /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
AnnaBridge 171:3a7713b1edbc 199 * @{
AnnaBridge 171:3a7713b1edbc 200 */
AnnaBridge 171:3a7713b1edbc 201 #define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
AnnaBridge 171:3a7713b1edbc 202 #define LL_I2C_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP) /*!< SMBus Host address acknowledge */
AnnaBridge 171:3a7713b1edbc 203 #define LL_I2C_MODE_SMBUS_DEVICE I2C_CR1_SMBUS /*!< SMBus Device default mode (Default address not acknowledge) */
AnnaBridge 171:3a7713b1edbc 204 #define LL_I2C_MODE_SMBUS_DEVICE_ARP (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_ENARP) /*!< SMBus Device Default address acknowledge */
AnnaBridge 171:3a7713b1edbc 205 /**
AnnaBridge 171:3a7713b1edbc 206 * @}
AnnaBridge 171:3a7713b1edbc 207 */
AnnaBridge 171:3a7713b1edbc 208
AnnaBridge 171:3a7713b1edbc 209 /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
AnnaBridge 171:3a7713b1edbc 210 * @{
AnnaBridge 171:3a7713b1edbc 211 */
AnnaBridge 171:3a7713b1edbc 212 #define LL_I2C_ACK I2C_CR1_ACK /*!< ACK is sent after current received byte. */
AnnaBridge 171:3a7713b1edbc 213 #define LL_I2C_NACK 0x00000000U /*!< NACK is sent after current received byte.*/
AnnaBridge 171:3a7713b1edbc 214 /**
AnnaBridge 171:3a7713b1edbc 215 * @}
AnnaBridge 171:3a7713b1edbc 216 */
AnnaBridge 171:3a7713b1edbc 217
AnnaBridge 171:3a7713b1edbc 218 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
AnnaBridge 171:3a7713b1edbc 219 * @{
AnnaBridge 171:3a7713b1edbc 220 */
AnnaBridge 171:3a7713b1edbc 221 #define LL_I2C_DIRECTION_WRITE I2C_SR2_TRA /*!< Bus is in write transfer */
AnnaBridge 171:3a7713b1edbc 222 #define LL_I2C_DIRECTION_READ 0x00000000U /*!< Bus is in read transfer */
AnnaBridge 171:3a7713b1edbc 223 /**
AnnaBridge 171:3a7713b1edbc 224 * @}
AnnaBridge 171:3a7713b1edbc 225 */
AnnaBridge 171:3a7713b1edbc 226
AnnaBridge 171:3a7713b1edbc 227 /**
AnnaBridge 171:3a7713b1edbc 228 * @}
AnnaBridge 171:3a7713b1edbc 229 */
AnnaBridge 171:3a7713b1edbc 230
AnnaBridge 171:3a7713b1edbc 231 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 232 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
AnnaBridge 171:3a7713b1edbc 233 * @{
AnnaBridge 171:3a7713b1edbc 234 */
AnnaBridge 171:3a7713b1edbc 235
AnnaBridge 171:3a7713b1edbc 236 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge 171:3a7713b1edbc 237 * @{
AnnaBridge 171:3a7713b1edbc 238 */
AnnaBridge 171:3a7713b1edbc 239
AnnaBridge 171:3a7713b1edbc 240 /**
AnnaBridge 171:3a7713b1edbc 241 * @brief Write a value in I2C register
AnnaBridge 171:3a7713b1edbc 242 * @param __INSTANCE__ I2C Instance
AnnaBridge 171:3a7713b1edbc 243 * @param __REG__ Register to be written
AnnaBridge 171:3a7713b1edbc 244 * @param __VALUE__ Value to be written in the register
AnnaBridge 171:3a7713b1edbc 245 * @retval None
AnnaBridge 171:3a7713b1edbc 246 */
AnnaBridge 171:3a7713b1edbc 247 #define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge 171:3a7713b1edbc 248
AnnaBridge 171:3a7713b1edbc 249 /**
AnnaBridge 171:3a7713b1edbc 250 * @brief Read a value in I2C register
AnnaBridge 171:3a7713b1edbc 251 * @param __INSTANCE__ I2C Instance
AnnaBridge 171:3a7713b1edbc 252 * @param __REG__ Register to be read
AnnaBridge 171:3a7713b1edbc 253 * @retval Register value
AnnaBridge 171:3a7713b1edbc 254 */
AnnaBridge 171:3a7713b1edbc 255 #define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge 171:3a7713b1edbc 256 /**
AnnaBridge 171:3a7713b1edbc 257 * @}
AnnaBridge 171:3a7713b1edbc 258 */
AnnaBridge 171:3a7713b1edbc 259
AnnaBridge 171:3a7713b1edbc 260 /** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
AnnaBridge 171:3a7713b1edbc 261 * @{
AnnaBridge 171:3a7713b1edbc 262 */
AnnaBridge 171:3a7713b1edbc 263
AnnaBridge 171:3a7713b1edbc 264 /**
AnnaBridge 171:3a7713b1edbc 265 * @brief Convert Peripheral Clock Frequency in Mhz.
AnnaBridge 171:3a7713b1edbc 266 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
AnnaBridge 171:3a7713b1edbc 267 * @retval Value of peripheral clock (in Mhz)
AnnaBridge 171:3a7713b1edbc 268 */
AnnaBridge 171:3a7713b1edbc 269 #define __LL_I2C_FREQ_HZ_TO_MHZ(__PCLK__) (uint32_t)((__PCLK__)/1000000U)
AnnaBridge 171:3a7713b1edbc 270
AnnaBridge 171:3a7713b1edbc 271 /**
AnnaBridge 171:3a7713b1edbc 272 * @brief Convert Peripheral Clock Frequency in Hz.
AnnaBridge 171:3a7713b1edbc 273 * @param __PCLK__ This parameter must be a value of peripheral clock (in Mhz).
AnnaBridge 171:3a7713b1edbc 274 * @retval Value of peripheral clock (in Hz)
AnnaBridge 171:3a7713b1edbc 275 */
AnnaBridge 171:3a7713b1edbc 276 #define __LL_I2C_FREQ_MHZ_TO_HZ(__PCLK__) (uint32_t)((__PCLK__)*1000000U)
AnnaBridge 171:3a7713b1edbc 277
AnnaBridge 171:3a7713b1edbc 278 /**
AnnaBridge 171:3a7713b1edbc 279 * @brief Compute I2C Clock rising time.
AnnaBridge 171:3a7713b1edbc 280 * @param __FREQRANGE__ This parameter must be a value of peripheral clock (in Mhz).
AnnaBridge 171:3a7713b1edbc 281 * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
AnnaBridge 171:3a7713b1edbc 282 * @retval Value between Min_Data=0x02 and Max_Data=0x3F
AnnaBridge 171:3a7713b1edbc 283 */
AnnaBridge 171:3a7713b1edbc 284 #define __LL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
AnnaBridge 171:3a7713b1edbc 285
AnnaBridge 171:3a7713b1edbc 286 /**
AnnaBridge 171:3a7713b1edbc 287 * @brief Compute Speed clock range to a Clock Control Register (I2C_CCR_CCR) value.
AnnaBridge 171:3a7713b1edbc 288 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
AnnaBridge 171:3a7713b1edbc 289 * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
AnnaBridge 171:3a7713b1edbc 290 * @param __DUTYCYCLE__ This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 291 * @arg @ref LL_I2C_DUTYCYCLE_2
AnnaBridge 171:3a7713b1edbc 292 * @arg @ref LL_I2C_DUTYCYCLE_16_9
AnnaBridge 171:3a7713b1edbc 293 * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
AnnaBridge 171:3a7713b1edbc 294 */
AnnaBridge 171:3a7713b1edbc 295 #define __LL_I2C_SPEED_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD)? \
AnnaBridge 171:3a7713b1edbc 296 (__LL_I2C_SPEED_STANDARD_TO_CCR((__PCLK__), (__SPEED__))) : \
AnnaBridge 171:3a7713b1edbc 297 (__LL_I2C_SPEED_FAST_TO_CCR((__PCLK__), (__SPEED__), (__DUTYCYCLE__))))
AnnaBridge 171:3a7713b1edbc 298
AnnaBridge 171:3a7713b1edbc 299 /**
AnnaBridge 171:3a7713b1edbc 300 * @brief Compute Speed Standard clock range to a Clock Control Register (I2C_CCR_CCR) value.
AnnaBridge 171:3a7713b1edbc 301 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
AnnaBridge 171:3a7713b1edbc 302 * @param __SPEED__ This parameter must be a value lower than 100kHz (in Hz).
AnnaBridge 171:3a7713b1edbc 303 * @retval Value between Min_Data=0x004 and Max_Data=0xFFF.
AnnaBridge 171:3a7713b1edbc 304 */
AnnaBridge 171:3a7713b1edbc 305 #define __LL_I2C_SPEED_STANDARD_TO_CCR(__PCLK__, __SPEED__) (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
AnnaBridge 171:3a7713b1edbc 306
AnnaBridge 171:3a7713b1edbc 307 /**
AnnaBridge 171:3a7713b1edbc 308 * @brief Compute Speed Fast clock range to a Clock Control Register (I2C_CCR_CCR) value.
AnnaBridge 171:3a7713b1edbc 309 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
AnnaBridge 171:3a7713b1edbc 310 * @param __SPEED__ This parameter must be a value between Min_Data=100Khz and Max_Data=400Khz (in Hz).
AnnaBridge 171:3a7713b1edbc 311 * @param __DUTYCYCLE__ This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 312 * @arg @ref LL_I2C_DUTYCYCLE_2
AnnaBridge 171:3a7713b1edbc 313 * @arg @ref LL_I2C_DUTYCYCLE_16_9
AnnaBridge 171:3a7713b1edbc 314 * @retval Value between Min_Data=0x001 and Max_Data=0xFFF
AnnaBridge 171:3a7713b1edbc 315 */
AnnaBridge 171:3a7713b1edbc 316 #define __LL_I2C_SPEED_FAST_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__DUTYCYCLE__) == LL_I2C_DUTYCYCLE_2)? \
AnnaBridge 171:3a7713b1edbc 317 (((((__PCLK__) / ((__SPEED__) * 3U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 3U))) : \
AnnaBridge 171:3a7713b1edbc 318 (((((__PCLK__) / ((__SPEED__) * 25U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 25U))))
AnnaBridge 171:3a7713b1edbc 319
AnnaBridge 171:3a7713b1edbc 320 /**
AnnaBridge 171:3a7713b1edbc 321 * @brief Get the Least significant bits of a 10-Bits address.
AnnaBridge 171:3a7713b1edbc 322 * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
AnnaBridge 171:3a7713b1edbc 323 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge 171:3a7713b1edbc 324 */
AnnaBridge 171:3a7713b1edbc 325 #define __LL_I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
AnnaBridge 171:3a7713b1edbc 326
AnnaBridge 171:3a7713b1edbc 327 /**
AnnaBridge 171:3a7713b1edbc 328 * @brief Convert a 10-Bits address to a 10-Bits header with Write direction.
AnnaBridge 171:3a7713b1edbc 329 * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
AnnaBridge 171:3a7713b1edbc 330 * @retval Value between Min_Data=0xF0 and Max_Data=0xF6
AnnaBridge 171:3a7713b1edbc 331 */
AnnaBridge 171:3a7713b1edbc 332 #define __LL_I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
AnnaBridge 171:3a7713b1edbc 333
AnnaBridge 171:3a7713b1edbc 334 /**
AnnaBridge 171:3a7713b1edbc 335 * @brief Convert a 10-Bits address to a 10-Bits header with Read direction.
AnnaBridge 171:3a7713b1edbc 336 * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
AnnaBridge 171:3a7713b1edbc 337 * @retval Value between Min_Data=0xF1 and Max_Data=0xF7
AnnaBridge 171:3a7713b1edbc 338 */
AnnaBridge 171:3a7713b1edbc 339 #define __LL_I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
AnnaBridge 171:3a7713b1edbc 340
AnnaBridge 171:3a7713b1edbc 341 /**
AnnaBridge 171:3a7713b1edbc 342 * @}
AnnaBridge 171:3a7713b1edbc 343 */
AnnaBridge 171:3a7713b1edbc 344
AnnaBridge 171:3a7713b1edbc 345 /**
AnnaBridge 171:3a7713b1edbc 346 * @}
AnnaBridge 171:3a7713b1edbc 347 */
AnnaBridge 171:3a7713b1edbc 348
AnnaBridge 171:3a7713b1edbc 349 /* Exported functions --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 350
AnnaBridge 171:3a7713b1edbc 351 /** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
AnnaBridge 171:3a7713b1edbc 352 * @{
AnnaBridge 171:3a7713b1edbc 353 */
AnnaBridge 171:3a7713b1edbc 354
AnnaBridge 171:3a7713b1edbc 355 /** @defgroup I2C_LL_EF_Configuration Configuration
AnnaBridge 171:3a7713b1edbc 356 * @{
AnnaBridge 171:3a7713b1edbc 357 */
AnnaBridge 171:3a7713b1edbc 358
AnnaBridge 171:3a7713b1edbc 359 /**
AnnaBridge 171:3a7713b1edbc 360 * @brief Enable I2C peripheral (PE = 1).
AnnaBridge 171:3a7713b1edbc 361 * @rmtoll CR1 PE LL_I2C_Enable
AnnaBridge 171:3a7713b1edbc 362 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 363 * @retval None
AnnaBridge 171:3a7713b1edbc 364 */
AnnaBridge 171:3a7713b1edbc 365 __STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 366 {
AnnaBridge 171:3a7713b1edbc 367 SET_BIT(I2Cx->CR1, I2C_CR1_PE);
AnnaBridge 171:3a7713b1edbc 368 }
AnnaBridge 171:3a7713b1edbc 369
AnnaBridge 171:3a7713b1edbc 370 /**
AnnaBridge 171:3a7713b1edbc 371 * @brief Disable I2C peripheral (PE = 0).
AnnaBridge 171:3a7713b1edbc 372 * @rmtoll CR1 PE LL_I2C_Disable
AnnaBridge 171:3a7713b1edbc 373 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 374 * @retval None
AnnaBridge 171:3a7713b1edbc 375 */
AnnaBridge 171:3a7713b1edbc 376 __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 377 {
AnnaBridge 171:3a7713b1edbc 378 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
AnnaBridge 171:3a7713b1edbc 379 }
AnnaBridge 171:3a7713b1edbc 380
AnnaBridge 171:3a7713b1edbc 381 /**
AnnaBridge 171:3a7713b1edbc 382 * @brief Check if the I2C peripheral is enabled or disabled.
AnnaBridge 171:3a7713b1edbc 383 * @rmtoll CR1 PE LL_I2C_IsEnabled
AnnaBridge 171:3a7713b1edbc 384 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 385 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 386 */
AnnaBridge 171:3a7713b1edbc 387 __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 388 {
AnnaBridge 171:3a7713b1edbc 389 return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
AnnaBridge 171:3a7713b1edbc 390 }
AnnaBridge 171:3a7713b1edbc 391
AnnaBridge 171:3a7713b1edbc 392
AnnaBridge 171:3a7713b1edbc 393 /**
AnnaBridge 171:3a7713b1edbc 394 * @brief Enable DMA transmission requests.
AnnaBridge 171:3a7713b1edbc 395 * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_TX
AnnaBridge 171:3a7713b1edbc 396 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 397 * @retval None
AnnaBridge 171:3a7713b1edbc 398 */
AnnaBridge 171:3a7713b1edbc 399 __STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 400 {
AnnaBridge 171:3a7713b1edbc 401 SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
AnnaBridge 171:3a7713b1edbc 402 }
AnnaBridge 171:3a7713b1edbc 403
AnnaBridge 171:3a7713b1edbc 404 /**
AnnaBridge 171:3a7713b1edbc 405 * @brief Disable DMA transmission requests.
AnnaBridge 171:3a7713b1edbc 406 * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_TX
AnnaBridge 171:3a7713b1edbc 407 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 408 * @retval None
AnnaBridge 171:3a7713b1edbc 409 */
AnnaBridge 171:3a7713b1edbc 410 __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 411 {
AnnaBridge 171:3a7713b1edbc 412 CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
AnnaBridge 171:3a7713b1edbc 413 }
AnnaBridge 171:3a7713b1edbc 414
AnnaBridge 171:3a7713b1edbc 415 /**
AnnaBridge 171:3a7713b1edbc 416 * @brief Check if DMA transmission requests are enabled or disabled.
AnnaBridge 171:3a7713b1edbc 417 * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_TX
AnnaBridge 171:3a7713b1edbc 418 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 419 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 420 */
AnnaBridge 171:3a7713b1edbc 421 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 422 {
AnnaBridge 171:3a7713b1edbc 423 return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
AnnaBridge 171:3a7713b1edbc 424 }
AnnaBridge 171:3a7713b1edbc 425
AnnaBridge 171:3a7713b1edbc 426 /**
AnnaBridge 171:3a7713b1edbc 427 * @brief Enable DMA reception requests.
AnnaBridge 171:3a7713b1edbc 428 * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_RX
AnnaBridge 171:3a7713b1edbc 429 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 430 * @retval None
AnnaBridge 171:3a7713b1edbc 431 */
AnnaBridge 171:3a7713b1edbc 432 __STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 433 {
AnnaBridge 171:3a7713b1edbc 434 SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
AnnaBridge 171:3a7713b1edbc 435 }
AnnaBridge 171:3a7713b1edbc 436
AnnaBridge 171:3a7713b1edbc 437 /**
AnnaBridge 171:3a7713b1edbc 438 * @brief Disable DMA reception requests.
AnnaBridge 171:3a7713b1edbc 439 * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_RX
AnnaBridge 171:3a7713b1edbc 440 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 441 * @retval None
AnnaBridge 171:3a7713b1edbc 442 */
AnnaBridge 171:3a7713b1edbc 443 __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 444 {
AnnaBridge 171:3a7713b1edbc 445 CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
AnnaBridge 171:3a7713b1edbc 446 }
AnnaBridge 171:3a7713b1edbc 447
AnnaBridge 171:3a7713b1edbc 448 /**
AnnaBridge 171:3a7713b1edbc 449 * @brief Check if DMA reception requests are enabled or disabled.
AnnaBridge 171:3a7713b1edbc 450 * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_RX
AnnaBridge 171:3a7713b1edbc 451 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 452 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 453 */
AnnaBridge 171:3a7713b1edbc 454 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 455 {
AnnaBridge 171:3a7713b1edbc 456 return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
AnnaBridge 171:3a7713b1edbc 457 }
AnnaBridge 171:3a7713b1edbc 458
AnnaBridge 171:3a7713b1edbc 459 /**
AnnaBridge 171:3a7713b1edbc 460 * @brief Get the data register address used for DMA transfer.
AnnaBridge 171:3a7713b1edbc 461 * @rmtoll DR DR LL_I2C_DMA_GetRegAddr
AnnaBridge 171:3a7713b1edbc 462 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 463 * @retval Address of data register
AnnaBridge 171:3a7713b1edbc 464 */
AnnaBridge 171:3a7713b1edbc 465 __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 466 {
AnnaBridge 171:3a7713b1edbc 467 return (uint32_t) & (I2Cx->DR);
AnnaBridge 171:3a7713b1edbc 468 }
AnnaBridge 171:3a7713b1edbc 469
AnnaBridge 171:3a7713b1edbc 470 /**
AnnaBridge 171:3a7713b1edbc 471 * @brief Enable Clock stretching.
AnnaBridge 171:3a7713b1edbc 472 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
AnnaBridge 171:3a7713b1edbc 473 * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
AnnaBridge 171:3a7713b1edbc 474 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 475 * @retval None
AnnaBridge 171:3a7713b1edbc 476 */
AnnaBridge 171:3a7713b1edbc 477 __STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 478 {
AnnaBridge 171:3a7713b1edbc 479 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
AnnaBridge 171:3a7713b1edbc 480 }
AnnaBridge 171:3a7713b1edbc 481
AnnaBridge 171:3a7713b1edbc 482 /**
AnnaBridge 171:3a7713b1edbc 483 * @brief Disable Clock stretching.
AnnaBridge 171:3a7713b1edbc 484 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
AnnaBridge 171:3a7713b1edbc 485 * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
AnnaBridge 171:3a7713b1edbc 486 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 487 * @retval None
AnnaBridge 171:3a7713b1edbc 488 */
AnnaBridge 171:3a7713b1edbc 489 __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 490 {
AnnaBridge 171:3a7713b1edbc 491 SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
AnnaBridge 171:3a7713b1edbc 492 }
AnnaBridge 171:3a7713b1edbc 493
AnnaBridge 171:3a7713b1edbc 494 /**
AnnaBridge 171:3a7713b1edbc 495 * @brief Check if Clock stretching is enabled or disabled.
AnnaBridge 171:3a7713b1edbc 496 * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
AnnaBridge 171:3a7713b1edbc 497 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 498 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 499 */
AnnaBridge 171:3a7713b1edbc 500 __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 501 {
AnnaBridge 171:3a7713b1edbc 502 return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
AnnaBridge 171:3a7713b1edbc 503 }
AnnaBridge 171:3a7713b1edbc 504
AnnaBridge 171:3a7713b1edbc 505 /**
AnnaBridge 171:3a7713b1edbc 506 * @brief Enable General Call.
AnnaBridge 171:3a7713b1edbc 507 * @note When enabled the Address 0x00 is ACKed.
AnnaBridge 171:3a7713b1edbc 508 * @rmtoll CR1 ENGC LL_I2C_EnableGeneralCall
AnnaBridge 171:3a7713b1edbc 509 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 510 * @retval None
AnnaBridge 171:3a7713b1edbc 511 */
AnnaBridge 171:3a7713b1edbc 512 __STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 513 {
AnnaBridge 171:3a7713b1edbc 514 SET_BIT(I2Cx->CR1, I2C_CR1_ENGC);
AnnaBridge 171:3a7713b1edbc 515 }
AnnaBridge 171:3a7713b1edbc 516
AnnaBridge 171:3a7713b1edbc 517 /**
AnnaBridge 171:3a7713b1edbc 518 * @brief Disable General Call.
AnnaBridge 171:3a7713b1edbc 519 * @note When disabled the Address 0x00 is NACKed.
AnnaBridge 171:3a7713b1edbc 520 * @rmtoll CR1 ENGC LL_I2C_DisableGeneralCall
AnnaBridge 171:3a7713b1edbc 521 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 522 * @retval None
AnnaBridge 171:3a7713b1edbc 523 */
AnnaBridge 171:3a7713b1edbc 524 __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 525 {
AnnaBridge 171:3a7713b1edbc 526 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENGC);
AnnaBridge 171:3a7713b1edbc 527 }
AnnaBridge 171:3a7713b1edbc 528
AnnaBridge 171:3a7713b1edbc 529 /**
AnnaBridge 171:3a7713b1edbc 530 * @brief Check if General Call is enabled or disabled.
AnnaBridge 171:3a7713b1edbc 531 * @rmtoll CR1 ENGC LL_I2C_IsEnabledGeneralCall
AnnaBridge 171:3a7713b1edbc 532 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 533 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 534 */
AnnaBridge 171:3a7713b1edbc 535 __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 536 {
AnnaBridge 171:3a7713b1edbc 537 return (READ_BIT(I2Cx->CR1, I2C_CR1_ENGC) == (I2C_CR1_ENGC));
AnnaBridge 171:3a7713b1edbc 538 }
AnnaBridge 171:3a7713b1edbc 539
AnnaBridge 171:3a7713b1edbc 540 /**
AnnaBridge 171:3a7713b1edbc 541 * @brief Set the Own Address1.
AnnaBridge 171:3a7713b1edbc 542 * @rmtoll OAR1 ADD0 LL_I2C_SetOwnAddress1\n
AnnaBridge 171:3a7713b1edbc 543 * OAR1 ADD1_7 LL_I2C_SetOwnAddress1\n
AnnaBridge 171:3a7713b1edbc 544 * OAR1 ADD8_9 LL_I2C_SetOwnAddress1\n
AnnaBridge 171:3a7713b1edbc 545 * OAR1 ADDMODE LL_I2C_SetOwnAddress1
AnnaBridge 171:3a7713b1edbc 546 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 547 * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
AnnaBridge 171:3a7713b1edbc 548 * @param OwnAddrSize This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 549 * @arg @ref LL_I2C_OWNADDRESS1_7BIT
AnnaBridge 171:3a7713b1edbc 550 * @arg @ref LL_I2C_OWNADDRESS1_10BIT
AnnaBridge 171:3a7713b1edbc 551 * @retval None
AnnaBridge 171:3a7713b1edbc 552 */
AnnaBridge 171:3a7713b1edbc 553 __STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
AnnaBridge 171:3a7713b1edbc 554 {
AnnaBridge 171:3a7713b1edbc 555 MODIFY_REG(I2Cx->OAR1, I2C_OAR1_ADD0 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD8_9 | I2C_OAR1_ADDMODE, OwnAddress1 | OwnAddrSize);
AnnaBridge 171:3a7713b1edbc 556 }
AnnaBridge 171:3a7713b1edbc 557
AnnaBridge 171:3a7713b1edbc 558 /**
AnnaBridge 171:3a7713b1edbc 559 * @brief Set the 7bits Own Address2.
AnnaBridge 171:3a7713b1edbc 560 * @note This action has no effect if own address2 is enabled.
AnnaBridge 171:3a7713b1edbc 561 * @rmtoll OAR2 ADD2 LL_I2C_SetOwnAddress2
AnnaBridge 171:3a7713b1edbc 562 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 563 * @param OwnAddress2 This parameter must be a value between Min_Data=0 and Max_Data=0x7F.
AnnaBridge 171:3a7713b1edbc 564 * @retval None
AnnaBridge 171:3a7713b1edbc 565 */
AnnaBridge 171:3a7713b1edbc 566 __STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2)
AnnaBridge 171:3a7713b1edbc 567 {
AnnaBridge 171:3a7713b1edbc 568 MODIFY_REG(I2Cx->OAR2, I2C_OAR2_ADD2, OwnAddress2);
AnnaBridge 171:3a7713b1edbc 569 }
AnnaBridge 171:3a7713b1edbc 570
AnnaBridge 171:3a7713b1edbc 571 /**
AnnaBridge 171:3a7713b1edbc 572 * @brief Enable acknowledge on Own Address2 match address.
AnnaBridge 171:3a7713b1edbc 573 * @rmtoll OAR2 ENDUAL LL_I2C_EnableOwnAddress2
AnnaBridge 171:3a7713b1edbc 574 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 575 * @retval None
AnnaBridge 171:3a7713b1edbc 576 */
AnnaBridge 171:3a7713b1edbc 577 __STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 578 {
AnnaBridge 171:3a7713b1edbc 579 SET_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
AnnaBridge 171:3a7713b1edbc 580 }
AnnaBridge 171:3a7713b1edbc 581
AnnaBridge 171:3a7713b1edbc 582 /**
AnnaBridge 171:3a7713b1edbc 583 * @brief Disable acknowledge on Own Address2 match address.
AnnaBridge 171:3a7713b1edbc 584 * @rmtoll OAR2 ENDUAL LL_I2C_DisableOwnAddress2
AnnaBridge 171:3a7713b1edbc 585 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 586 * @retval None
AnnaBridge 171:3a7713b1edbc 587 */
AnnaBridge 171:3a7713b1edbc 588 __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 589 {
AnnaBridge 171:3a7713b1edbc 590 CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
AnnaBridge 171:3a7713b1edbc 591 }
AnnaBridge 171:3a7713b1edbc 592
AnnaBridge 171:3a7713b1edbc 593 /**
AnnaBridge 171:3a7713b1edbc 594 * @brief Check if Own Address1 acknowledge is enabled or disabled.
AnnaBridge 171:3a7713b1edbc 595 * @rmtoll OAR2 ENDUAL LL_I2C_IsEnabledOwnAddress2
AnnaBridge 171:3a7713b1edbc 596 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 597 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 598 */
AnnaBridge 171:3a7713b1edbc 599 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 600 {
AnnaBridge 171:3a7713b1edbc 601 return (READ_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL) == (I2C_OAR2_ENDUAL));
AnnaBridge 171:3a7713b1edbc 602 }
AnnaBridge 171:3a7713b1edbc 603
AnnaBridge 171:3a7713b1edbc 604 /**
AnnaBridge 171:3a7713b1edbc 605 * @brief Configure the Peripheral clock frequency.
AnnaBridge 171:3a7713b1edbc 606 * @rmtoll CR2 FREQ LL_I2C_SetPeriphClock
AnnaBridge 171:3a7713b1edbc 607 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 608 * @param PeriphClock Peripheral Clock (in Hz)
AnnaBridge 171:3a7713b1edbc 609 * @retval None
AnnaBridge 171:3a7713b1edbc 610 */
AnnaBridge 171:3a7713b1edbc 611 __STATIC_INLINE void LL_I2C_SetPeriphClock(I2C_TypeDef *I2Cx, uint32_t PeriphClock)
AnnaBridge 171:3a7713b1edbc 612 {
AnnaBridge 171:3a7713b1edbc 613 MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock));
AnnaBridge 171:3a7713b1edbc 614 }
AnnaBridge 171:3a7713b1edbc 615
AnnaBridge 171:3a7713b1edbc 616 /**
AnnaBridge 171:3a7713b1edbc 617 * @brief Get the Peripheral clock frequency.
AnnaBridge 171:3a7713b1edbc 618 * @rmtoll CR2 FREQ LL_I2C_GetPeriphClock
AnnaBridge 171:3a7713b1edbc 619 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 620 * @retval Value of Peripheral Clock (in Hz)
AnnaBridge 171:3a7713b1edbc 621 */
AnnaBridge 171:3a7713b1edbc 622 __STATIC_INLINE uint32_t LL_I2C_GetPeriphClock(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 623 {
AnnaBridge 171:3a7713b1edbc 624 return (uint32_t)(__LL_I2C_FREQ_MHZ_TO_HZ(READ_BIT(I2Cx->CR2, I2C_CR2_FREQ)));
AnnaBridge 171:3a7713b1edbc 625 }
AnnaBridge 171:3a7713b1edbc 626
AnnaBridge 171:3a7713b1edbc 627 /**
AnnaBridge 171:3a7713b1edbc 628 * @brief Configure the Duty cycle (Fast mode only).
AnnaBridge 171:3a7713b1edbc 629 * @rmtoll CCR DUTY LL_I2C_SetDutyCycle
AnnaBridge 171:3a7713b1edbc 630 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 631 * @param DutyCycle This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 632 * @arg @ref LL_I2C_DUTYCYCLE_2
AnnaBridge 171:3a7713b1edbc 633 * @arg @ref LL_I2C_DUTYCYCLE_16_9
AnnaBridge 171:3a7713b1edbc 634 * @retval None
AnnaBridge 171:3a7713b1edbc 635 */
AnnaBridge 171:3a7713b1edbc 636 __STATIC_INLINE void LL_I2C_SetDutyCycle(I2C_TypeDef *I2Cx, uint32_t DutyCycle)
AnnaBridge 171:3a7713b1edbc 637 {
AnnaBridge 171:3a7713b1edbc 638 MODIFY_REG(I2Cx->CCR, I2C_CCR_DUTY, DutyCycle);
AnnaBridge 171:3a7713b1edbc 639 }
AnnaBridge 171:3a7713b1edbc 640
AnnaBridge 171:3a7713b1edbc 641 /**
AnnaBridge 171:3a7713b1edbc 642 * @brief Get the Duty cycle (Fast mode only).
AnnaBridge 171:3a7713b1edbc 643 * @rmtoll CCR DUTY LL_I2C_GetDutyCycle
AnnaBridge 171:3a7713b1edbc 644 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 645 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 646 * @arg @ref LL_I2C_DUTYCYCLE_2
AnnaBridge 171:3a7713b1edbc 647 * @arg @ref LL_I2C_DUTYCYCLE_16_9
AnnaBridge 171:3a7713b1edbc 648 */
AnnaBridge 171:3a7713b1edbc 649 __STATIC_INLINE uint32_t LL_I2C_GetDutyCycle(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 650 {
AnnaBridge 171:3a7713b1edbc 651 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_DUTY));
AnnaBridge 171:3a7713b1edbc 652 }
AnnaBridge 171:3a7713b1edbc 653
AnnaBridge 171:3a7713b1edbc 654 /**
AnnaBridge 171:3a7713b1edbc 655 * @brief Configure the I2C master clock speed mode.
AnnaBridge 171:3a7713b1edbc 656 * @rmtoll CCR FS LL_I2C_SetClockSpeedMode
AnnaBridge 171:3a7713b1edbc 657 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 658 * @param ClockSpeedMode This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 659 * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
AnnaBridge 171:3a7713b1edbc 660 * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
AnnaBridge 171:3a7713b1edbc 661 * @retval None
AnnaBridge 171:3a7713b1edbc 662 */
AnnaBridge 171:3a7713b1edbc 663 __STATIC_INLINE void LL_I2C_SetClockSpeedMode(I2C_TypeDef *I2Cx, uint32_t ClockSpeedMode)
AnnaBridge 171:3a7713b1edbc 664 {
AnnaBridge 171:3a7713b1edbc 665 MODIFY_REG(I2Cx->CCR, I2C_CCR_FS, ClockSpeedMode);
AnnaBridge 171:3a7713b1edbc 666 }
AnnaBridge 171:3a7713b1edbc 667
AnnaBridge 171:3a7713b1edbc 668 /**
AnnaBridge 171:3a7713b1edbc 669 * @brief Get the the I2C master speed mode.
AnnaBridge 171:3a7713b1edbc 670 * @rmtoll CCR FS LL_I2C_GetClockSpeedMode
AnnaBridge 171:3a7713b1edbc 671 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 672 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 673 * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
AnnaBridge 171:3a7713b1edbc 674 * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
AnnaBridge 171:3a7713b1edbc 675 */
AnnaBridge 171:3a7713b1edbc 676 __STATIC_INLINE uint32_t LL_I2C_GetClockSpeedMode(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 677 {
AnnaBridge 171:3a7713b1edbc 678 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_FS));
AnnaBridge 171:3a7713b1edbc 679 }
AnnaBridge 171:3a7713b1edbc 680
AnnaBridge 171:3a7713b1edbc 681 /**
AnnaBridge 171:3a7713b1edbc 682 * @brief Configure the SCL, SDA rising time.
AnnaBridge 171:3a7713b1edbc 683 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
AnnaBridge 171:3a7713b1edbc 684 * @rmtoll TRISE TRISE LL_I2C_SetRiseTime
AnnaBridge 171:3a7713b1edbc 685 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 686 * @param RiseTime This parameter must be a value between Min_Data=0x02 and Max_Data=0x3F.
AnnaBridge 171:3a7713b1edbc 687 * @retval None
AnnaBridge 171:3a7713b1edbc 688 */
AnnaBridge 171:3a7713b1edbc 689 __STATIC_INLINE void LL_I2C_SetRiseTime(I2C_TypeDef *I2Cx, uint32_t RiseTime)
AnnaBridge 171:3a7713b1edbc 690 {
AnnaBridge 171:3a7713b1edbc 691 MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, RiseTime);
AnnaBridge 171:3a7713b1edbc 692 }
AnnaBridge 171:3a7713b1edbc 693
AnnaBridge 171:3a7713b1edbc 694 /**
AnnaBridge 171:3a7713b1edbc 695 * @brief Get the SCL, SDA rising time.
AnnaBridge 171:3a7713b1edbc 696 * @rmtoll TRISE TRISE LL_I2C_GetRiseTime
AnnaBridge 171:3a7713b1edbc 697 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 698 * @retval Value between Min_Data=0x02 and Max_Data=0x3F
AnnaBridge 171:3a7713b1edbc 699 */
AnnaBridge 171:3a7713b1edbc 700 __STATIC_INLINE uint32_t LL_I2C_GetRiseTime(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 701 {
AnnaBridge 171:3a7713b1edbc 702 return (uint32_t)(READ_BIT(I2Cx->TRISE, I2C_TRISE_TRISE));
AnnaBridge 171:3a7713b1edbc 703 }
AnnaBridge 171:3a7713b1edbc 704
AnnaBridge 171:3a7713b1edbc 705 /**
AnnaBridge 171:3a7713b1edbc 706 * @brief Configure the SCL high and low period.
AnnaBridge 171:3a7713b1edbc 707 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
AnnaBridge 171:3a7713b1edbc 708 * @rmtoll CCR CCR LL_I2C_SetClockPeriod
AnnaBridge 171:3a7713b1edbc 709 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 710 * @param ClockPeriod This parameter must be a value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
AnnaBridge 171:3a7713b1edbc 711 * @retval None
AnnaBridge 171:3a7713b1edbc 712 */
AnnaBridge 171:3a7713b1edbc 713 __STATIC_INLINE void LL_I2C_SetClockPeriod(I2C_TypeDef *I2Cx, uint32_t ClockPeriod)
AnnaBridge 171:3a7713b1edbc 714 {
AnnaBridge 171:3a7713b1edbc 715 MODIFY_REG(I2Cx->CCR, I2C_CCR_CCR, ClockPeriod);
AnnaBridge 171:3a7713b1edbc 716 }
AnnaBridge 171:3a7713b1edbc 717
AnnaBridge 171:3a7713b1edbc 718 /**
AnnaBridge 171:3a7713b1edbc 719 * @brief Get the SCL high and low period.
AnnaBridge 171:3a7713b1edbc 720 * @rmtoll CCR CCR LL_I2C_GetClockPeriod
AnnaBridge 171:3a7713b1edbc 721 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 722 * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
AnnaBridge 171:3a7713b1edbc 723 */
AnnaBridge 171:3a7713b1edbc 724 __STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 725 {
AnnaBridge 171:3a7713b1edbc 726 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_CCR));
AnnaBridge 171:3a7713b1edbc 727 }
AnnaBridge 171:3a7713b1edbc 728
AnnaBridge 171:3a7713b1edbc 729 /**
AnnaBridge 171:3a7713b1edbc 730 * @brief Configure the SCL speed.
AnnaBridge 171:3a7713b1edbc 731 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
AnnaBridge 171:3a7713b1edbc 732 * @rmtoll CR2 FREQ LL_I2C_ConfigSpeed\n
AnnaBridge 171:3a7713b1edbc 733 * TRISE TRISE LL_I2C_ConfigSpeed\n
AnnaBridge 171:3a7713b1edbc 734 * CCR FS LL_I2C_ConfigSpeed\n
AnnaBridge 171:3a7713b1edbc 735 * CCR DUTY LL_I2C_ConfigSpeed\n
AnnaBridge 171:3a7713b1edbc 736 * CCR CCR LL_I2C_ConfigSpeed
AnnaBridge 171:3a7713b1edbc 737 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 738 * @param PeriphClock Peripheral Clock (in Hz)
AnnaBridge 171:3a7713b1edbc 739 * @param ClockSpeed This parameter must be a value lower than 400kHz (in Hz).
AnnaBridge 171:3a7713b1edbc 740 * @param DutyCycle This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 741 * @arg @ref LL_I2C_DUTYCYCLE_2
AnnaBridge 171:3a7713b1edbc 742 * @arg @ref LL_I2C_DUTYCYCLE_16_9
AnnaBridge 171:3a7713b1edbc 743 * @retval None
AnnaBridge 171:3a7713b1edbc 744 */
AnnaBridge 171:3a7713b1edbc 745 __STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed,
AnnaBridge 171:3a7713b1edbc 746 uint32_t DutyCycle)
AnnaBridge 171:3a7713b1edbc 747 {
AnnaBridge 171:3a7713b1edbc 748 register uint32_t freqrange = 0x0U;
AnnaBridge 171:3a7713b1edbc 749 register uint32_t clockconfig = 0x0U;
AnnaBridge 171:3a7713b1edbc 750
AnnaBridge 171:3a7713b1edbc 751 /* Compute frequency range */
AnnaBridge 171:3a7713b1edbc 752 freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock);
AnnaBridge 171:3a7713b1edbc 753
AnnaBridge 171:3a7713b1edbc 754 /* Configure I2Cx: Frequency range register */
AnnaBridge 171:3a7713b1edbc 755 MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, freqrange);
AnnaBridge 171:3a7713b1edbc 756
AnnaBridge 171:3a7713b1edbc 757 /* Configure I2Cx: Rise Time register */
AnnaBridge 171:3a7713b1edbc 758 MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, __LL_I2C_RISE_TIME(freqrange, ClockSpeed));
AnnaBridge 171:3a7713b1edbc 759
AnnaBridge 171:3a7713b1edbc 760 /* Configure Speed mode, Duty Cycle and Clock control register value */
AnnaBridge 171:3a7713b1edbc 761 if (ClockSpeed > LL_I2C_MAX_SPEED_STANDARD)
AnnaBridge 171:3a7713b1edbc 762 {
AnnaBridge 171:3a7713b1edbc 763 /* Set Speed mode at fast and duty cycle for Clock Speed request in fast clock range */
AnnaBridge 171:3a7713b1edbc 764 clockconfig = LL_I2C_CLOCK_SPEED_FAST_MODE | \
AnnaBridge 171:3a7713b1edbc 765 __LL_I2C_SPEED_FAST_TO_CCR(PeriphClock, ClockSpeed, DutyCycle) | \
AnnaBridge 171:3a7713b1edbc 766 DutyCycle;
AnnaBridge 171:3a7713b1edbc 767 }
AnnaBridge 171:3a7713b1edbc 768 else
AnnaBridge 171:3a7713b1edbc 769 {
AnnaBridge 171:3a7713b1edbc 770 /* Set Speed mode at standard for Clock Speed request in standard clock range */
AnnaBridge 171:3a7713b1edbc 771 clockconfig = LL_I2C_CLOCK_SPEED_STANDARD_MODE | \
AnnaBridge 171:3a7713b1edbc 772 __LL_I2C_SPEED_STANDARD_TO_CCR(PeriphClock, ClockSpeed);
AnnaBridge 171:3a7713b1edbc 773 }
AnnaBridge 171:3a7713b1edbc 774
AnnaBridge 171:3a7713b1edbc 775 /* Configure I2Cx: Clock control register */
AnnaBridge 171:3a7713b1edbc 776 MODIFY_REG(I2Cx->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), clockconfig);
AnnaBridge 171:3a7713b1edbc 777 }
AnnaBridge 171:3a7713b1edbc 778
AnnaBridge 171:3a7713b1edbc 779 /**
AnnaBridge 171:3a7713b1edbc 780 * @brief Configure peripheral mode.
AnnaBridge 171:3a7713b1edbc 781 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 171:3a7713b1edbc 782 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 171:3a7713b1edbc 783 * @rmtoll CR1 SMBUS LL_I2C_SetMode\n
AnnaBridge 171:3a7713b1edbc 784 * CR1 SMBTYPE LL_I2C_SetMode\n
AnnaBridge 171:3a7713b1edbc 785 * CR1 ENARP LL_I2C_SetMode
AnnaBridge 171:3a7713b1edbc 786 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 787 * @param PeripheralMode This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 788 * @arg @ref LL_I2C_MODE_I2C
AnnaBridge 171:3a7713b1edbc 789 * @arg @ref LL_I2C_MODE_SMBUS_HOST
AnnaBridge 171:3a7713b1edbc 790 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
AnnaBridge 171:3a7713b1edbc 791 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
AnnaBridge 171:3a7713b1edbc 792 * @retval None
AnnaBridge 171:3a7713b1edbc 793 */
AnnaBridge 171:3a7713b1edbc 794 __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
AnnaBridge 171:3a7713b1edbc 795 {
AnnaBridge 171:3a7713b1edbc 796 MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP, PeripheralMode);
AnnaBridge 171:3a7713b1edbc 797 }
AnnaBridge 171:3a7713b1edbc 798
AnnaBridge 171:3a7713b1edbc 799 /**
AnnaBridge 171:3a7713b1edbc 800 * @brief Get peripheral mode.
AnnaBridge 171:3a7713b1edbc 801 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 171:3a7713b1edbc 802 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 171:3a7713b1edbc 803 * @rmtoll CR1 SMBUS LL_I2C_GetMode\n
AnnaBridge 171:3a7713b1edbc 804 * CR1 SMBTYPE LL_I2C_GetMode\n
AnnaBridge 171:3a7713b1edbc 805 * CR1 ENARP LL_I2C_GetMode
AnnaBridge 171:3a7713b1edbc 806 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 807 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 808 * @arg @ref LL_I2C_MODE_I2C
AnnaBridge 171:3a7713b1edbc 809 * @arg @ref LL_I2C_MODE_SMBUS_HOST
AnnaBridge 171:3a7713b1edbc 810 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
AnnaBridge 171:3a7713b1edbc 811 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
AnnaBridge 171:3a7713b1edbc 812 */
AnnaBridge 171:3a7713b1edbc 813 __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 814 {
AnnaBridge 171:3a7713b1edbc 815 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP));
AnnaBridge 171:3a7713b1edbc 816 }
AnnaBridge 171:3a7713b1edbc 817
AnnaBridge 171:3a7713b1edbc 818 /**
AnnaBridge 171:3a7713b1edbc 819 * @brief Enable SMBus alert (Host or Device mode)
AnnaBridge 171:3a7713b1edbc 820 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 171:3a7713b1edbc 821 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 171:3a7713b1edbc 822 * @note SMBus Device mode:
AnnaBridge 171:3a7713b1edbc 823 * - SMBus Alert pin is drived low and
AnnaBridge 171:3a7713b1edbc 824 * Alert Response Address Header acknowledge is enabled.
AnnaBridge 171:3a7713b1edbc 825 * SMBus Host mode:
AnnaBridge 171:3a7713b1edbc 826 * - SMBus Alert pin management is supported.
AnnaBridge 171:3a7713b1edbc 827 * @rmtoll CR1 ALERT LL_I2C_EnableSMBusAlert
AnnaBridge 171:3a7713b1edbc 828 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 829 * @retval None
AnnaBridge 171:3a7713b1edbc 830 */
AnnaBridge 171:3a7713b1edbc 831 __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 832 {
AnnaBridge 171:3a7713b1edbc 833 SET_BIT(I2Cx->CR1, I2C_CR1_ALERT);
AnnaBridge 171:3a7713b1edbc 834 }
AnnaBridge 171:3a7713b1edbc 835
AnnaBridge 171:3a7713b1edbc 836 /**
AnnaBridge 171:3a7713b1edbc 837 * @brief Disable SMBus alert (Host or Device mode)
AnnaBridge 171:3a7713b1edbc 838 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 171:3a7713b1edbc 839 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 171:3a7713b1edbc 840 * @note SMBus Device mode:
AnnaBridge 171:3a7713b1edbc 841 * - SMBus Alert pin is not drived (can be used as a standard GPIO) and
AnnaBridge 171:3a7713b1edbc 842 * Alert Response Address Header acknowledge is disabled.
AnnaBridge 171:3a7713b1edbc 843 * SMBus Host mode:
AnnaBridge 171:3a7713b1edbc 844 * - SMBus Alert pin management is not supported.
AnnaBridge 171:3a7713b1edbc 845 * @rmtoll CR1 ALERT LL_I2C_DisableSMBusAlert
AnnaBridge 171:3a7713b1edbc 846 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 847 * @retval None
AnnaBridge 171:3a7713b1edbc 848 */
AnnaBridge 171:3a7713b1edbc 849 __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 850 {
AnnaBridge 171:3a7713b1edbc 851 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERT);
AnnaBridge 171:3a7713b1edbc 852 }
AnnaBridge 171:3a7713b1edbc 853
AnnaBridge 171:3a7713b1edbc 854 /**
AnnaBridge 171:3a7713b1edbc 855 * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
AnnaBridge 171:3a7713b1edbc 856 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 171:3a7713b1edbc 857 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 171:3a7713b1edbc 858 * @rmtoll CR1 ALERT LL_I2C_IsEnabledSMBusAlert
AnnaBridge 171:3a7713b1edbc 859 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 860 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 861 */
AnnaBridge 171:3a7713b1edbc 862 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 863 {
AnnaBridge 171:3a7713b1edbc 864 return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERT) == (I2C_CR1_ALERT));
AnnaBridge 171:3a7713b1edbc 865 }
AnnaBridge 171:3a7713b1edbc 866
AnnaBridge 171:3a7713b1edbc 867 /**
AnnaBridge 171:3a7713b1edbc 868 * @brief Enable SMBus Packet Error Calculation (PEC).
AnnaBridge 171:3a7713b1edbc 869 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 171:3a7713b1edbc 870 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 171:3a7713b1edbc 871 * @rmtoll CR1 ENPEC LL_I2C_EnableSMBusPEC
AnnaBridge 171:3a7713b1edbc 872 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 873 * @retval None
AnnaBridge 171:3a7713b1edbc 874 */
AnnaBridge 171:3a7713b1edbc 875 __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 876 {
AnnaBridge 171:3a7713b1edbc 877 SET_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
AnnaBridge 171:3a7713b1edbc 878 }
AnnaBridge 171:3a7713b1edbc 879
AnnaBridge 171:3a7713b1edbc 880 /**
AnnaBridge 171:3a7713b1edbc 881 * @brief Disable SMBus Packet Error Calculation (PEC).
AnnaBridge 171:3a7713b1edbc 882 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 171:3a7713b1edbc 883 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 171:3a7713b1edbc 884 * @rmtoll CR1 ENPEC LL_I2C_DisableSMBusPEC
AnnaBridge 171:3a7713b1edbc 885 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 886 * @retval None
AnnaBridge 171:3a7713b1edbc 887 */
AnnaBridge 171:3a7713b1edbc 888 __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 889 {
AnnaBridge 171:3a7713b1edbc 890 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
AnnaBridge 171:3a7713b1edbc 891 }
AnnaBridge 171:3a7713b1edbc 892
AnnaBridge 171:3a7713b1edbc 893 /**
AnnaBridge 171:3a7713b1edbc 894 * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
AnnaBridge 171:3a7713b1edbc 895 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 171:3a7713b1edbc 896 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 171:3a7713b1edbc 897 * @rmtoll CR1 ENPEC LL_I2C_IsEnabledSMBusPEC
AnnaBridge 171:3a7713b1edbc 898 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 899 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 900 */
AnnaBridge 171:3a7713b1edbc 901 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 902 {
AnnaBridge 171:3a7713b1edbc 903 return (READ_BIT(I2Cx->CR1, I2C_CR1_ENPEC) == (I2C_CR1_ENPEC));
AnnaBridge 171:3a7713b1edbc 904 }
AnnaBridge 171:3a7713b1edbc 905
AnnaBridge 171:3a7713b1edbc 906 /**
AnnaBridge 171:3a7713b1edbc 907 * @}
AnnaBridge 171:3a7713b1edbc 908 */
AnnaBridge 171:3a7713b1edbc 909
AnnaBridge 171:3a7713b1edbc 910 /** @defgroup I2C_LL_EF_IT_Management IT_Management
AnnaBridge 171:3a7713b1edbc 911 * @{
AnnaBridge 171:3a7713b1edbc 912 */
AnnaBridge 171:3a7713b1edbc 913
AnnaBridge 171:3a7713b1edbc 914 /**
AnnaBridge 171:3a7713b1edbc 915 * @brief Enable TXE interrupt.
AnnaBridge 171:3a7713b1edbc 916 * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_TX\n
AnnaBridge 171:3a7713b1edbc 917 * CR2 ITBUFEN LL_I2C_EnableIT_TX
AnnaBridge 171:3a7713b1edbc 918 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 919 * @retval None
AnnaBridge 171:3a7713b1edbc 920 */
AnnaBridge 171:3a7713b1edbc 921 __STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 922 {
AnnaBridge 171:3a7713b1edbc 923 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
AnnaBridge 171:3a7713b1edbc 924 }
AnnaBridge 171:3a7713b1edbc 925
AnnaBridge 171:3a7713b1edbc 926 /**
AnnaBridge 171:3a7713b1edbc 927 * @brief Disable TXE interrupt.
AnnaBridge 171:3a7713b1edbc 928 * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_TX\n
AnnaBridge 171:3a7713b1edbc 929 * CR2 ITBUFEN LL_I2C_DisableIT_TX
AnnaBridge 171:3a7713b1edbc 930 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 931 * @retval None
AnnaBridge 171:3a7713b1edbc 932 */
AnnaBridge 171:3a7713b1edbc 933 __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 934 {
AnnaBridge 171:3a7713b1edbc 935 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
AnnaBridge 171:3a7713b1edbc 936 }
AnnaBridge 171:3a7713b1edbc 937
AnnaBridge 171:3a7713b1edbc 938 /**
AnnaBridge 171:3a7713b1edbc 939 * @brief Check if the TXE Interrupt is enabled or disabled.
AnnaBridge 171:3a7713b1edbc 940 * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_TX\n
AnnaBridge 171:3a7713b1edbc 941 * CR2 ITBUFEN LL_I2C_IsEnabledIT_TX
AnnaBridge 171:3a7713b1edbc 942 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 943 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 944 */
AnnaBridge 171:3a7713b1edbc 945 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 946 {
AnnaBridge 171:3a7713b1edbc 947 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
AnnaBridge 171:3a7713b1edbc 948 }
AnnaBridge 171:3a7713b1edbc 949
AnnaBridge 171:3a7713b1edbc 950 /**
AnnaBridge 171:3a7713b1edbc 951 * @brief Enable RXNE interrupt.
AnnaBridge 171:3a7713b1edbc 952 * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_RX\n
AnnaBridge 171:3a7713b1edbc 953 * CR2 ITBUFEN LL_I2C_EnableIT_RX
AnnaBridge 171:3a7713b1edbc 954 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 955 * @retval None
AnnaBridge 171:3a7713b1edbc 956 */
AnnaBridge 171:3a7713b1edbc 957 __STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 958 {
AnnaBridge 171:3a7713b1edbc 959 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
AnnaBridge 171:3a7713b1edbc 960 }
AnnaBridge 171:3a7713b1edbc 961
AnnaBridge 171:3a7713b1edbc 962 /**
AnnaBridge 171:3a7713b1edbc 963 * @brief Disable RXNE interrupt.
AnnaBridge 171:3a7713b1edbc 964 * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_RX\n
AnnaBridge 171:3a7713b1edbc 965 * CR2 ITBUFEN LL_I2C_DisableIT_RX
AnnaBridge 171:3a7713b1edbc 966 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 967 * @retval None
AnnaBridge 171:3a7713b1edbc 968 */
AnnaBridge 171:3a7713b1edbc 969 __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 970 {
AnnaBridge 171:3a7713b1edbc 971 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
AnnaBridge 171:3a7713b1edbc 972 }
AnnaBridge 171:3a7713b1edbc 973
AnnaBridge 171:3a7713b1edbc 974 /**
AnnaBridge 171:3a7713b1edbc 975 * @brief Check if the RXNE Interrupt is enabled or disabled.
AnnaBridge 171:3a7713b1edbc 976 * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_RX\n
AnnaBridge 171:3a7713b1edbc 977 * CR2 ITBUFEN LL_I2C_IsEnabledIT_RX
AnnaBridge 171:3a7713b1edbc 978 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 979 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 980 */
AnnaBridge 171:3a7713b1edbc 981 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 982 {
AnnaBridge 171:3a7713b1edbc 983 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
AnnaBridge 171:3a7713b1edbc 984 }
AnnaBridge 171:3a7713b1edbc 985
AnnaBridge 171:3a7713b1edbc 986 /**
AnnaBridge 171:3a7713b1edbc 987 * @brief Enable Events interrupts.
AnnaBridge 171:3a7713b1edbc 988 * @note Any of these events will generate interrupt :
AnnaBridge 171:3a7713b1edbc 989 * Start Bit (SB)
AnnaBridge 171:3a7713b1edbc 990 * Address sent, Address matched (ADDR)
AnnaBridge 171:3a7713b1edbc 991 * 10-bit header sent (ADD10)
AnnaBridge 171:3a7713b1edbc 992 * Stop detection (STOPF)
AnnaBridge 171:3a7713b1edbc 993 * Byte transfer finished (BTF)
AnnaBridge 171:3a7713b1edbc 994 *
AnnaBridge 171:3a7713b1edbc 995 * @note Any of these events will generate interrupt if Buffer interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_BUF()) :
AnnaBridge 171:3a7713b1edbc 996 * Receive buffer not empty (RXNE)
AnnaBridge 171:3a7713b1edbc 997 * Transmit buffer empty (TXE)
AnnaBridge 171:3a7713b1edbc 998 * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_EVT
AnnaBridge 171:3a7713b1edbc 999 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1000 * @retval None
AnnaBridge 171:3a7713b1edbc 1001 */
AnnaBridge 171:3a7713b1edbc 1002 __STATIC_INLINE void LL_I2C_EnableIT_EVT(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1003 {
AnnaBridge 171:3a7713b1edbc 1004 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
AnnaBridge 171:3a7713b1edbc 1005 }
AnnaBridge 171:3a7713b1edbc 1006
AnnaBridge 171:3a7713b1edbc 1007 /**
AnnaBridge 171:3a7713b1edbc 1008 * @brief Disable Events interrupts.
AnnaBridge 171:3a7713b1edbc 1009 * @note Any of these events will generate interrupt :
AnnaBridge 171:3a7713b1edbc 1010 * Start Bit (SB)
AnnaBridge 171:3a7713b1edbc 1011 * Address sent, Address matched (ADDR)
AnnaBridge 171:3a7713b1edbc 1012 * 10-bit header sent (ADD10)
AnnaBridge 171:3a7713b1edbc 1013 * Stop detection (STOPF)
AnnaBridge 171:3a7713b1edbc 1014 * Byte transfer finished (BTF)
AnnaBridge 171:3a7713b1edbc 1015 * Receive buffer not empty (RXNE)
AnnaBridge 171:3a7713b1edbc 1016 * Transmit buffer empty (TXE)
AnnaBridge 171:3a7713b1edbc 1017 * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_EVT
AnnaBridge 171:3a7713b1edbc 1018 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1019 * @retval None
AnnaBridge 171:3a7713b1edbc 1020 */
AnnaBridge 171:3a7713b1edbc 1021 __STATIC_INLINE void LL_I2C_DisableIT_EVT(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1022 {
AnnaBridge 171:3a7713b1edbc 1023 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
AnnaBridge 171:3a7713b1edbc 1024 }
AnnaBridge 171:3a7713b1edbc 1025
AnnaBridge 171:3a7713b1edbc 1026 /**
AnnaBridge 171:3a7713b1edbc 1027 * @brief Check if Events interrupts are enabled or disabled.
AnnaBridge 171:3a7713b1edbc 1028 * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_EVT
AnnaBridge 171:3a7713b1edbc 1029 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1030 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1031 */
AnnaBridge 171:3a7713b1edbc 1032 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_EVT(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1033 {
AnnaBridge 171:3a7713b1edbc 1034 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN) == (I2C_CR2_ITEVTEN));
AnnaBridge 171:3a7713b1edbc 1035 }
AnnaBridge 171:3a7713b1edbc 1036
AnnaBridge 171:3a7713b1edbc 1037 /**
AnnaBridge 171:3a7713b1edbc 1038 * @brief Enable Buffer interrupts.
AnnaBridge 171:3a7713b1edbc 1039 * @note Any of these Buffer events will generate interrupt if Events interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_EVT()) :
AnnaBridge 171:3a7713b1edbc 1040 * Receive buffer not empty (RXNE)
AnnaBridge 171:3a7713b1edbc 1041 * Transmit buffer empty (TXE)
AnnaBridge 171:3a7713b1edbc 1042 * @rmtoll CR2 ITBUFEN LL_I2C_EnableIT_BUF
AnnaBridge 171:3a7713b1edbc 1043 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1044 * @retval None
AnnaBridge 171:3a7713b1edbc 1045 */
AnnaBridge 171:3a7713b1edbc 1046 __STATIC_INLINE void LL_I2C_EnableIT_BUF(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1047 {
AnnaBridge 171:3a7713b1edbc 1048 SET_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
AnnaBridge 171:3a7713b1edbc 1049 }
AnnaBridge 171:3a7713b1edbc 1050
AnnaBridge 171:3a7713b1edbc 1051 /**
AnnaBridge 171:3a7713b1edbc 1052 * @brief Disable Buffer interrupts.
AnnaBridge 171:3a7713b1edbc 1053 * @note Any of these Buffer events will generate interrupt :
AnnaBridge 171:3a7713b1edbc 1054 * Receive buffer not empty (RXNE)
AnnaBridge 171:3a7713b1edbc 1055 * Transmit buffer empty (TXE)
AnnaBridge 171:3a7713b1edbc 1056 * @rmtoll CR2 ITBUFEN LL_I2C_DisableIT_BUF
AnnaBridge 171:3a7713b1edbc 1057 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1058 * @retval None
AnnaBridge 171:3a7713b1edbc 1059 */
AnnaBridge 171:3a7713b1edbc 1060 __STATIC_INLINE void LL_I2C_DisableIT_BUF(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1061 {
AnnaBridge 171:3a7713b1edbc 1062 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
AnnaBridge 171:3a7713b1edbc 1063 }
AnnaBridge 171:3a7713b1edbc 1064
AnnaBridge 171:3a7713b1edbc 1065 /**
AnnaBridge 171:3a7713b1edbc 1066 * @brief Check if Buffer interrupts are enabled or disabled.
AnnaBridge 171:3a7713b1edbc 1067 * @rmtoll CR2 ITBUFEN LL_I2C_IsEnabledIT_BUF
AnnaBridge 171:3a7713b1edbc 1068 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1069 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1070 */
AnnaBridge 171:3a7713b1edbc 1071 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_BUF(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1072 {
AnnaBridge 171:3a7713b1edbc 1073 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN) == (I2C_CR2_ITBUFEN));
AnnaBridge 171:3a7713b1edbc 1074 }
AnnaBridge 171:3a7713b1edbc 1075
AnnaBridge 171:3a7713b1edbc 1076 /**
AnnaBridge 171:3a7713b1edbc 1077 * @brief Enable Error interrupts.
AnnaBridge 171:3a7713b1edbc 1078 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 171:3a7713b1edbc 1079 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 171:3a7713b1edbc 1080 * @note Any of these errors will generate interrupt :
AnnaBridge 171:3a7713b1edbc 1081 * Bus Error detection (BERR)
AnnaBridge 171:3a7713b1edbc 1082 * Arbitration Loss (ARLO)
AnnaBridge 171:3a7713b1edbc 1083 * Acknowledge Failure(AF)
AnnaBridge 171:3a7713b1edbc 1084 * Overrun/Underrun (OVR)
AnnaBridge 171:3a7713b1edbc 1085 * SMBus Timeout detection (TIMEOUT)
AnnaBridge 171:3a7713b1edbc 1086 * SMBus PEC error detection (PECERR)
AnnaBridge 171:3a7713b1edbc 1087 * SMBus Alert pin event detection (SMBALERT)
AnnaBridge 171:3a7713b1edbc 1088 * @rmtoll CR2 ITERREN LL_I2C_EnableIT_ERR
AnnaBridge 171:3a7713b1edbc 1089 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1090 * @retval None
AnnaBridge 171:3a7713b1edbc 1091 */
AnnaBridge 171:3a7713b1edbc 1092 __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1093 {
AnnaBridge 171:3a7713b1edbc 1094 SET_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
AnnaBridge 171:3a7713b1edbc 1095 }
AnnaBridge 171:3a7713b1edbc 1096
AnnaBridge 171:3a7713b1edbc 1097 /**
AnnaBridge 171:3a7713b1edbc 1098 * @brief Disable Error interrupts.
AnnaBridge 171:3a7713b1edbc 1099 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 171:3a7713b1edbc 1100 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 171:3a7713b1edbc 1101 * @note Any of these errors will generate interrupt :
AnnaBridge 171:3a7713b1edbc 1102 * Bus Error detection (BERR)
AnnaBridge 171:3a7713b1edbc 1103 * Arbitration Loss (ARLO)
AnnaBridge 171:3a7713b1edbc 1104 * Acknowledge Failure(AF)
AnnaBridge 171:3a7713b1edbc 1105 * Overrun/Underrun (OVR)
AnnaBridge 171:3a7713b1edbc 1106 * SMBus Timeout detection (TIMEOUT)
AnnaBridge 171:3a7713b1edbc 1107 * SMBus PEC error detection (PECERR)
AnnaBridge 171:3a7713b1edbc 1108 * SMBus Alert pin event detection (SMBALERT)
AnnaBridge 171:3a7713b1edbc 1109 * @rmtoll CR2 ITERREN LL_I2C_DisableIT_ERR
AnnaBridge 171:3a7713b1edbc 1110 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1111 * @retval None
AnnaBridge 171:3a7713b1edbc 1112 */
AnnaBridge 171:3a7713b1edbc 1113 __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1114 {
AnnaBridge 171:3a7713b1edbc 1115 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
AnnaBridge 171:3a7713b1edbc 1116 }
AnnaBridge 171:3a7713b1edbc 1117
AnnaBridge 171:3a7713b1edbc 1118 /**
AnnaBridge 171:3a7713b1edbc 1119 * @brief Check if Error interrupts are enabled or disabled.
AnnaBridge 171:3a7713b1edbc 1120 * @rmtoll CR2 ITERREN LL_I2C_IsEnabledIT_ERR
AnnaBridge 171:3a7713b1edbc 1121 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1122 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1123 */
AnnaBridge 171:3a7713b1edbc 1124 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1125 {
AnnaBridge 171:3a7713b1edbc 1126 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITERREN) == (I2C_CR2_ITERREN));
AnnaBridge 171:3a7713b1edbc 1127 }
AnnaBridge 171:3a7713b1edbc 1128
AnnaBridge 171:3a7713b1edbc 1129 /**
AnnaBridge 171:3a7713b1edbc 1130 * @}
AnnaBridge 171:3a7713b1edbc 1131 */
AnnaBridge 171:3a7713b1edbc 1132
AnnaBridge 171:3a7713b1edbc 1133 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management
AnnaBridge 171:3a7713b1edbc 1134 * @{
AnnaBridge 171:3a7713b1edbc 1135 */
AnnaBridge 171:3a7713b1edbc 1136
AnnaBridge 171:3a7713b1edbc 1137 /**
AnnaBridge 171:3a7713b1edbc 1138 * @brief Indicate the status of Transmit data register empty flag.
AnnaBridge 171:3a7713b1edbc 1139 * @note RESET: When next data is written in Transmit data register.
AnnaBridge 171:3a7713b1edbc 1140 * SET: When Transmit data register is empty.
AnnaBridge 171:3a7713b1edbc 1141 * @rmtoll SR1 TXE LL_I2C_IsActiveFlag_TXE
AnnaBridge 171:3a7713b1edbc 1142 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1143 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1144 */
AnnaBridge 171:3a7713b1edbc 1145 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1146 {
AnnaBridge 171:3a7713b1edbc 1147 return (READ_BIT(I2Cx->SR1, I2C_SR1_TXE) == (I2C_SR1_TXE));
AnnaBridge 171:3a7713b1edbc 1148 }
AnnaBridge 171:3a7713b1edbc 1149
AnnaBridge 171:3a7713b1edbc 1150 /**
AnnaBridge 171:3a7713b1edbc 1151 * @brief Indicate the status of Byte Transfer Finished flag.
AnnaBridge 171:3a7713b1edbc 1152 * RESET: When Data byte transfer not done.
AnnaBridge 171:3a7713b1edbc 1153 * SET: When Data byte transfer succeeded.
AnnaBridge 171:3a7713b1edbc 1154 * @rmtoll SR1 BTF LL_I2C_IsActiveFlag_BTF
AnnaBridge 171:3a7713b1edbc 1155 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1156 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1157 */
AnnaBridge 171:3a7713b1edbc 1158 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BTF(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1159 {
AnnaBridge 171:3a7713b1edbc 1160 return (READ_BIT(I2Cx->SR1, I2C_SR1_BTF) == (I2C_SR1_BTF));
AnnaBridge 171:3a7713b1edbc 1161 }
AnnaBridge 171:3a7713b1edbc 1162
AnnaBridge 171:3a7713b1edbc 1163 /**
AnnaBridge 171:3a7713b1edbc 1164 * @brief Indicate the status of Receive data register not empty flag.
AnnaBridge 171:3a7713b1edbc 1165 * @note RESET: When Receive data register is read.
AnnaBridge 171:3a7713b1edbc 1166 * SET: When the received data is copied in Receive data register.
AnnaBridge 171:3a7713b1edbc 1167 * @rmtoll SR1 RXNE LL_I2C_IsActiveFlag_RXNE
AnnaBridge 171:3a7713b1edbc 1168 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1169 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1170 */
AnnaBridge 171:3a7713b1edbc 1171 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1172 {
AnnaBridge 171:3a7713b1edbc 1173 return (READ_BIT(I2Cx->SR1, I2C_SR1_RXNE) == (I2C_SR1_RXNE));
AnnaBridge 171:3a7713b1edbc 1174 }
AnnaBridge 171:3a7713b1edbc 1175
AnnaBridge 171:3a7713b1edbc 1176 /**
AnnaBridge 171:3a7713b1edbc 1177 * @brief Indicate the status of Start Bit (master mode).
AnnaBridge 171:3a7713b1edbc 1178 * @note RESET: When No Start condition.
AnnaBridge 171:3a7713b1edbc 1179 * SET: When Start condition is generated.
AnnaBridge 171:3a7713b1edbc 1180 * @rmtoll SR1 SB LL_I2C_IsActiveFlag_SB
AnnaBridge 171:3a7713b1edbc 1181 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1182 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1183 */
AnnaBridge 171:3a7713b1edbc 1184 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_SB(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1185 {
AnnaBridge 171:3a7713b1edbc 1186 return (READ_BIT(I2Cx->SR1, I2C_SR1_SB) == (I2C_SR1_SB));
AnnaBridge 171:3a7713b1edbc 1187 }
AnnaBridge 171:3a7713b1edbc 1188
AnnaBridge 171:3a7713b1edbc 1189 /**
AnnaBridge 171:3a7713b1edbc 1190 * @brief Indicate the status of Address sent (master mode) or Address matched flag (slave mode).
AnnaBridge 171:3a7713b1edbc 1191 * @note RESET: Clear default value.
AnnaBridge 171:3a7713b1edbc 1192 * SET: When the address is fully sent (master mode) or when the received slave address matched with one of the enabled slave address (slave mode).
AnnaBridge 171:3a7713b1edbc 1193 * @rmtoll SR1 ADDR LL_I2C_IsActiveFlag_ADDR
AnnaBridge 171:3a7713b1edbc 1194 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1195 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1196 */
AnnaBridge 171:3a7713b1edbc 1197 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1198 {
AnnaBridge 171:3a7713b1edbc 1199 return (READ_BIT(I2Cx->SR1, I2C_SR1_ADDR) == (I2C_SR1_ADDR));
AnnaBridge 171:3a7713b1edbc 1200 }
AnnaBridge 171:3a7713b1edbc 1201
AnnaBridge 171:3a7713b1edbc 1202 /**
AnnaBridge 171:3a7713b1edbc 1203 * @brief Indicate the status of 10-bit header sent (master mode).
AnnaBridge 171:3a7713b1edbc 1204 * @note RESET: When no ADD10 event occured.
AnnaBridge 171:3a7713b1edbc 1205 * SET: When the master has sent the first address byte (header).
AnnaBridge 171:3a7713b1edbc 1206 * @rmtoll SR1 ADD10 LL_I2C_IsActiveFlag_ADD10
AnnaBridge 171:3a7713b1edbc 1207 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1208 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1209 */
AnnaBridge 171:3a7713b1edbc 1210 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADD10(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1211 {
AnnaBridge 171:3a7713b1edbc 1212 return (READ_BIT(I2Cx->SR1, I2C_SR1_ADD10) == (I2C_SR1_ADD10));
AnnaBridge 171:3a7713b1edbc 1213 }
AnnaBridge 171:3a7713b1edbc 1214
AnnaBridge 171:3a7713b1edbc 1215 /**
AnnaBridge 171:3a7713b1edbc 1216 * @brief Indicate the status of Acknowledge failure flag.
AnnaBridge 171:3a7713b1edbc 1217 * @note RESET: No acknowledge failure.
AnnaBridge 171:3a7713b1edbc 1218 * SET: When an acknowledge failure is received after a byte transmission.
AnnaBridge 171:3a7713b1edbc 1219 * @rmtoll SR1 AF LL_I2C_IsActiveFlag_AF
AnnaBridge 171:3a7713b1edbc 1220 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1221 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1222 */
AnnaBridge 171:3a7713b1edbc 1223 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_AF(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1224 {
AnnaBridge 171:3a7713b1edbc 1225 return (READ_BIT(I2Cx->SR1, I2C_SR1_AF) == (I2C_SR1_AF));
AnnaBridge 171:3a7713b1edbc 1226 }
AnnaBridge 171:3a7713b1edbc 1227
AnnaBridge 171:3a7713b1edbc 1228 /**
AnnaBridge 171:3a7713b1edbc 1229 * @brief Indicate the status of Stop detection flag (slave mode).
AnnaBridge 171:3a7713b1edbc 1230 * @note RESET: Clear default value.
AnnaBridge 171:3a7713b1edbc 1231 * SET: When a Stop condition is detected.
AnnaBridge 171:3a7713b1edbc 1232 * @rmtoll SR1 STOPF LL_I2C_IsActiveFlag_STOP
AnnaBridge 171:3a7713b1edbc 1233 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1234 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1235 */
AnnaBridge 171:3a7713b1edbc 1236 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1237 {
AnnaBridge 171:3a7713b1edbc 1238 return (READ_BIT(I2Cx->SR1, I2C_SR1_STOPF) == (I2C_SR1_STOPF));
AnnaBridge 171:3a7713b1edbc 1239 }
AnnaBridge 171:3a7713b1edbc 1240
AnnaBridge 171:3a7713b1edbc 1241 /**
AnnaBridge 171:3a7713b1edbc 1242 * @brief Indicate the status of Bus error flag.
AnnaBridge 171:3a7713b1edbc 1243 * @note RESET: Clear default value.
AnnaBridge 171:3a7713b1edbc 1244 * SET: When a misplaced Start or Stop condition is detected.
AnnaBridge 171:3a7713b1edbc 1245 * @rmtoll SR1 BERR LL_I2C_IsActiveFlag_BERR
AnnaBridge 171:3a7713b1edbc 1246 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1247 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1248 */
AnnaBridge 171:3a7713b1edbc 1249 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1250 {
AnnaBridge 171:3a7713b1edbc 1251 return (READ_BIT(I2Cx->SR1, I2C_SR1_BERR) == (I2C_SR1_BERR));
AnnaBridge 171:3a7713b1edbc 1252 }
AnnaBridge 171:3a7713b1edbc 1253
AnnaBridge 171:3a7713b1edbc 1254 /**
AnnaBridge 171:3a7713b1edbc 1255 * @brief Indicate the status of Arbitration lost flag.
AnnaBridge 171:3a7713b1edbc 1256 * @note RESET: Clear default value.
AnnaBridge 171:3a7713b1edbc 1257 * SET: When arbitration lost.
AnnaBridge 171:3a7713b1edbc 1258 * @rmtoll SR1 ARLO LL_I2C_IsActiveFlag_ARLO
AnnaBridge 171:3a7713b1edbc 1259 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1260 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1261 */
AnnaBridge 171:3a7713b1edbc 1262 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1263 {
AnnaBridge 171:3a7713b1edbc 1264 return (READ_BIT(I2Cx->SR1, I2C_SR1_ARLO) == (I2C_SR1_ARLO));
AnnaBridge 171:3a7713b1edbc 1265 }
AnnaBridge 171:3a7713b1edbc 1266
AnnaBridge 171:3a7713b1edbc 1267 /**
AnnaBridge 171:3a7713b1edbc 1268 * @brief Indicate the status of Overrun/Underrun flag.
AnnaBridge 171:3a7713b1edbc 1269 * @note RESET: Clear default value.
AnnaBridge 171:3a7713b1edbc 1270 * SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
AnnaBridge 171:3a7713b1edbc 1271 * @rmtoll SR1 OVR LL_I2C_IsActiveFlag_OVR
AnnaBridge 171:3a7713b1edbc 1272 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1273 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1274 */
AnnaBridge 171:3a7713b1edbc 1275 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1276 {
AnnaBridge 171:3a7713b1edbc 1277 return (READ_BIT(I2Cx->SR1, I2C_SR1_OVR) == (I2C_SR1_OVR));
AnnaBridge 171:3a7713b1edbc 1278 }
AnnaBridge 171:3a7713b1edbc 1279
AnnaBridge 171:3a7713b1edbc 1280 /**
AnnaBridge 171:3a7713b1edbc 1281 * @brief Indicate the status of SMBus PEC error flag in reception.
AnnaBridge 171:3a7713b1edbc 1282 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 171:3a7713b1edbc 1283 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 171:3a7713b1edbc 1284 * @rmtoll SR1 PECERR LL_I2C_IsActiveSMBusFlag_PECERR
AnnaBridge 171:3a7713b1edbc 1285 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1286 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1287 */
AnnaBridge 171:3a7713b1edbc 1288 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1289 {
AnnaBridge 171:3a7713b1edbc 1290 return (READ_BIT(I2Cx->SR1, I2C_SR1_PECERR) == (I2C_SR1_PECERR));
AnnaBridge 171:3a7713b1edbc 1291 }
AnnaBridge 171:3a7713b1edbc 1292
AnnaBridge 171:3a7713b1edbc 1293 /**
AnnaBridge 171:3a7713b1edbc 1294 * @brief Indicate the status of SMBus Timeout detection flag.
AnnaBridge 171:3a7713b1edbc 1295 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 171:3a7713b1edbc 1296 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 171:3a7713b1edbc 1297 * @rmtoll SR1 TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
AnnaBridge 171:3a7713b1edbc 1298 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1299 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1300 */
AnnaBridge 171:3a7713b1edbc 1301 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1302 {
AnnaBridge 171:3a7713b1edbc 1303 return (READ_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT) == (I2C_SR1_TIMEOUT));
AnnaBridge 171:3a7713b1edbc 1304 }
AnnaBridge 171:3a7713b1edbc 1305
AnnaBridge 171:3a7713b1edbc 1306 /**
AnnaBridge 171:3a7713b1edbc 1307 * @brief Indicate the status of SMBus alert flag.
AnnaBridge 171:3a7713b1edbc 1308 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 171:3a7713b1edbc 1309 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 171:3a7713b1edbc 1310 * @rmtoll SR1 SMBALERT LL_I2C_IsActiveSMBusFlag_ALERT
AnnaBridge 171:3a7713b1edbc 1311 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1312 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1313 */
AnnaBridge 171:3a7713b1edbc 1314 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1315 {
AnnaBridge 171:3a7713b1edbc 1316 return (READ_BIT(I2Cx->SR1, I2C_SR1_SMBALERT) == (I2C_SR1_SMBALERT));
AnnaBridge 171:3a7713b1edbc 1317 }
AnnaBridge 171:3a7713b1edbc 1318
AnnaBridge 171:3a7713b1edbc 1319 /**
AnnaBridge 171:3a7713b1edbc 1320 * @brief Indicate the status of Bus Busy flag.
AnnaBridge 171:3a7713b1edbc 1321 * @note RESET: Clear default value.
AnnaBridge 171:3a7713b1edbc 1322 * SET: When a Start condition is detected.
AnnaBridge 171:3a7713b1edbc 1323 * @rmtoll SR2 BUSY LL_I2C_IsActiveFlag_BUSY
AnnaBridge 171:3a7713b1edbc 1324 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1325 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1326 */
AnnaBridge 171:3a7713b1edbc 1327 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1328 {
AnnaBridge 171:3a7713b1edbc 1329 return (READ_BIT(I2Cx->SR2, I2C_SR2_BUSY) == (I2C_SR2_BUSY));
AnnaBridge 171:3a7713b1edbc 1330 }
AnnaBridge 171:3a7713b1edbc 1331
AnnaBridge 171:3a7713b1edbc 1332 /**
AnnaBridge 171:3a7713b1edbc 1333 * @brief Indicate the status of Dual flag.
AnnaBridge 171:3a7713b1edbc 1334 * @note RESET: Received address matched with OAR1.
AnnaBridge 171:3a7713b1edbc 1335 * SET: Received address matched with OAR2.
AnnaBridge 171:3a7713b1edbc 1336 * @rmtoll SR2 DUALF LL_I2C_IsActiveFlag_DUAL
AnnaBridge 171:3a7713b1edbc 1337 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1338 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1339 */
AnnaBridge 171:3a7713b1edbc 1340 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_DUAL(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1341 {
AnnaBridge 171:3a7713b1edbc 1342 return (READ_BIT(I2Cx->SR2, I2C_SR2_DUALF) == (I2C_SR2_DUALF));
AnnaBridge 171:3a7713b1edbc 1343 }
AnnaBridge 171:3a7713b1edbc 1344
AnnaBridge 171:3a7713b1edbc 1345 /**
AnnaBridge 171:3a7713b1edbc 1346 * @brief Indicate the status of SMBus Host address reception (Slave mode).
AnnaBridge 171:3a7713b1edbc 1347 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 171:3a7713b1edbc 1348 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 171:3a7713b1edbc 1349 * @note RESET: No SMBus Host address
AnnaBridge 171:3a7713b1edbc 1350 * SET: SMBus Host address received.
AnnaBridge 171:3a7713b1edbc 1351 * @note This status is cleared by hardware after a STOP condition or repeated START condition.
AnnaBridge 171:3a7713b1edbc 1352 * @rmtoll SR2 SMBHOST LL_I2C_IsActiveSMBusFlag_SMBHOST
AnnaBridge 171:3a7713b1edbc 1353 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1354 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1355 */
AnnaBridge 171:3a7713b1edbc 1356 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1357 {
AnnaBridge 171:3a7713b1edbc 1358 return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBHOST) == (I2C_SR2_SMBHOST));
AnnaBridge 171:3a7713b1edbc 1359 }
AnnaBridge 171:3a7713b1edbc 1360
AnnaBridge 171:3a7713b1edbc 1361 /**
AnnaBridge 171:3a7713b1edbc 1362 * @brief Indicate the status of SMBus Device default address reception (Slave mode).
AnnaBridge 171:3a7713b1edbc 1363 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 171:3a7713b1edbc 1364 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 171:3a7713b1edbc 1365 * @note RESET: No SMBus Device default address
AnnaBridge 171:3a7713b1edbc 1366 * SET: SMBus Device default address received.
AnnaBridge 171:3a7713b1edbc 1367 * @note This status is cleared by hardware after a STOP condition or repeated START condition.
AnnaBridge 171:3a7713b1edbc 1368 * @rmtoll SR2 SMBDEFAULT LL_I2C_IsActiveSMBusFlag_SMBDEFAULT
AnnaBridge 171:3a7713b1edbc 1369 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1370 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1371 */
AnnaBridge 171:3a7713b1edbc 1372 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1373 {
AnnaBridge 171:3a7713b1edbc 1374 return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBDEFAULT) == (I2C_SR2_SMBDEFAULT));
AnnaBridge 171:3a7713b1edbc 1375 }
AnnaBridge 171:3a7713b1edbc 1376
AnnaBridge 171:3a7713b1edbc 1377 /**
AnnaBridge 171:3a7713b1edbc 1378 * @brief Indicate the status of General call address reception (Slave mode).
AnnaBridge 171:3a7713b1edbc 1379 * @note RESET: No Generall call address
AnnaBridge 171:3a7713b1edbc 1380 * SET: General call address received.
AnnaBridge 171:3a7713b1edbc 1381 * @note This status is cleared by hardware after a STOP condition or repeated START condition.
AnnaBridge 171:3a7713b1edbc 1382 * @rmtoll SR2 GENCALL LL_I2C_IsActiveFlag_GENCALL
AnnaBridge 171:3a7713b1edbc 1383 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1384 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1385 */
AnnaBridge 171:3a7713b1edbc 1386 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1387 {
AnnaBridge 171:3a7713b1edbc 1388 return (READ_BIT(I2Cx->SR2, I2C_SR2_GENCALL) == (I2C_SR2_GENCALL));
AnnaBridge 171:3a7713b1edbc 1389 }
AnnaBridge 171:3a7713b1edbc 1390
AnnaBridge 171:3a7713b1edbc 1391 /**
AnnaBridge 171:3a7713b1edbc 1392 * @brief Indicate the status of Master/Slave flag.
AnnaBridge 171:3a7713b1edbc 1393 * @note RESET: Slave Mode.
AnnaBridge 171:3a7713b1edbc 1394 * SET: Master Mode.
AnnaBridge 171:3a7713b1edbc 1395 * @rmtoll SR2 MSL LL_I2C_IsActiveFlag_MSL
AnnaBridge 171:3a7713b1edbc 1396 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1397 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1398 */
AnnaBridge 171:3a7713b1edbc 1399 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_MSL(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1400 {
AnnaBridge 171:3a7713b1edbc 1401 return (READ_BIT(I2Cx->SR2, I2C_SR2_MSL) == (I2C_SR2_MSL));
AnnaBridge 171:3a7713b1edbc 1402 }
AnnaBridge 171:3a7713b1edbc 1403
AnnaBridge 171:3a7713b1edbc 1404 /**
AnnaBridge 171:3a7713b1edbc 1405 * @brief Clear Address Matched flag.
AnnaBridge 171:3a7713b1edbc 1406 * @note Clearing this flag is done by a read access to the I2Cx_SR1
AnnaBridge 171:3a7713b1edbc 1407 * register followed by a read access to the I2Cx_SR2 register.
AnnaBridge 171:3a7713b1edbc 1408 * @rmtoll SR1 ADDR LL_I2C_ClearFlag_ADDR
AnnaBridge 171:3a7713b1edbc 1409 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1410 * @retval None
AnnaBridge 171:3a7713b1edbc 1411 */
AnnaBridge 171:3a7713b1edbc 1412 __STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1413 {
AnnaBridge 171:3a7713b1edbc 1414 __IO uint32_t tmpreg;
AnnaBridge 171:3a7713b1edbc 1415 tmpreg = I2Cx->SR1;
AnnaBridge 171:3a7713b1edbc 1416 (void) tmpreg;
AnnaBridge 171:3a7713b1edbc 1417 tmpreg = I2Cx->SR2;
AnnaBridge 171:3a7713b1edbc 1418 (void) tmpreg;
AnnaBridge 171:3a7713b1edbc 1419 }
AnnaBridge 171:3a7713b1edbc 1420
AnnaBridge 171:3a7713b1edbc 1421 /**
AnnaBridge 171:3a7713b1edbc 1422 * @brief Clear Acknowledge failure flag.
AnnaBridge 171:3a7713b1edbc 1423 * @rmtoll SR1 AF LL_I2C_ClearFlag_AF
AnnaBridge 171:3a7713b1edbc 1424 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1425 * @retval None
AnnaBridge 171:3a7713b1edbc 1426 */
AnnaBridge 171:3a7713b1edbc 1427 __STATIC_INLINE void LL_I2C_ClearFlag_AF(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1428 {
AnnaBridge 171:3a7713b1edbc 1429 CLEAR_BIT(I2Cx->SR1, I2C_SR1_AF);
AnnaBridge 171:3a7713b1edbc 1430 }
AnnaBridge 171:3a7713b1edbc 1431
AnnaBridge 171:3a7713b1edbc 1432 /**
AnnaBridge 171:3a7713b1edbc 1433 * @brief Clear Stop detection flag.
AnnaBridge 171:3a7713b1edbc 1434 * @note Clearing this flag is done by a read access to the I2Cx_SR1
AnnaBridge 171:3a7713b1edbc 1435 * register followed by a write access to I2Cx_CR1 register.
AnnaBridge 171:3a7713b1edbc 1436 * @rmtoll SR1 STOPF LL_I2C_ClearFlag_STOP\n
AnnaBridge 171:3a7713b1edbc 1437 * CR1 PE LL_I2C_ClearFlag_STOP
AnnaBridge 171:3a7713b1edbc 1438 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1439 * @retval None
AnnaBridge 171:3a7713b1edbc 1440 */
AnnaBridge 171:3a7713b1edbc 1441 __STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1442 {
AnnaBridge 171:3a7713b1edbc 1443 __IO uint32_t tmpreg;
AnnaBridge 171:3a7713b1edbc 1444 tmpreg = I2Cx->SR1;
AnnaBridge 171:3a7713b1edbc 1445 (void) tmpreg;
AnnaBridge 171:3a7713b1edbc 1446 SET_BIT(I2Cx->CR1, I2C_CR1_PE);
AnnaBridge 171:3a7713b1edbc 1447 }
AnnaBridge 171:3a7713b1edbc 1448
AnnaBridge 171:3a7713b1edbc 1449 /**
AnnaBridge 171:3a7713b1edbc 1450 * @brief Clear Bus error flag.
AnnaBridge 171:3a7713b1edbc 1451 * @rmtoll SR1 BERR LL_I2C_ClearFlag_BERR
AnnaBridge 171:3a7713b1edbc 1452 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1453 * @retval None
AnnaBridge 171:3a7713b1edbc 1454 */
AnnaBridge 171:3a7713b1edbc 1455 __STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1456 {
AnnaBridge 171:3a7713b1edbc 1457 CLEAR_BIT(I2Cx->SR1, I2C_SR1_BERR);
AnnaBridge 171:3a7713b1edbc 1458 }
AnnaBridge 171:3a7713b1edbc 1459
AnnaBridge 171:3a7713b1edbc 1460 /**
AnnaBridge 171:3a7713b1edbc 1461 * @brief Clear Arbitration lost flag.
AnnaBridge 171:3a7713b1edbc 1462 * @rmtoll SR1 ARLO LL_I2C_ClearFlag_ARLO
AnnaBridge 171:3a7713b1edbc 1463 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1464 * @retval None
AnnaBridge 171:3a7713b1edbc 1465 */
AnnaBridge 171:3a7713b1edbc 1466 __STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1467 {
AnnaBridge 171:3a7713b1edbc 1468 CLEAR_BIT(I2Cx->SR1, I2C_SR1_ARLO);
AnnaBridge 171:3a7713b1edbc 1469 }
AnnaBridge 171:3a7713b1edbc 1470
AnnaBridge 171:3a7713b1edbc 1471 /**
AnnaBridge 171:3a7713b1edbc 1472 * @brief Clear Overrun/Underrun flag.
AnnaBridge 171:3a7713b1edbc 1473 * @rmtoll SR1 OVR LL_I2C_ClearFlag_OVR
AnnaBridge 171:3a7713b1edbc 1474 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1475 * @retval None
AnnaBridge 171:3a7713b1edbc 1476 */
AnnaBridge 171:3a7713b1edbc 1477 __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1478 {
AnnaBridge 171:3a7713b1edbc 1479 CLEAR_BIT(I2Cx->SR1, I2C_SR1_OVR);
AnnaBridge 171:3a7713b1edbc 1480 }
AnnaBridge 171:3a7713b1edbc 1481
AnnaBridge 171:3a7713b1edbc 1482 /**
AnnaBridge 171:3a7713b1edbc 1483 * @brief Clear SMBus PEC error flag.
AnnaBridge 171:3a7713b1edbc 1484 * @rmtoll SR1 PECERR LL_I2C_ClearSMBusFlag_PECERR
AnnaBridge 171:3a7713b1edbc 1485 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1486 * @retval None
AnnaBridge 171:3a7713b1edbc 1487 */
AnnaBridge 171:3a7713b1edbc 1488 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1489 {
AnnaBridge 171:3a7713b1edbc 1490 CLEAR_BIT(I2Cx->SR1, I2C_SR1_PECERR);
AnnaBridge 171:3a7713b1edbc 1491 }
AnnaBridge 171:3a7713b1edbc 1492
AnnaBridge 171:3a7713b1edbc 1493 /**
AnnaBridge 171:3a7713b1edbc 1494 * @brief Clear SMBus Timeout detection flag.
AnnaBridge 171:3a7713b1edbc 1495 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 171:3a7713b1edbc 1496 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 171:3a7713b1edbc 1497 * @rmtoll SR1 TIMEOUT LL_I2C_ClearSMBusFlag_TIMEOUT
AnnaBridge 171:3a7713b1edbc 1498 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1499 * @retval None
AnnaBridge 171:3a7713b1edbc 1500 */
AnnaBridge 171:3a7713b1edbc 1501 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1502 {
AnnaBridge 171:3a7713b1edbc 1503 CLEAR_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT);
AnnaBridge 171:3a7713b1edbc 1504 }
AnnaBridge 171:3a7713b1edbc 1505
AnnaBridge 171:3a7713b1edbc 1506 /**
AnnaBridge 171:3a7713b1edbc 1507 * @brief Clear SMBus Alert flag.
AnnaBridge 171:3a7713b1edbc 1508 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 171:3a7713b1edbc 1509 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 171:3a7713b1edbc 1510 * @rmtoll SR1 SMBALERT LL_I2C_ClearSMBusFlag_ALERT
AnnaBridge 171:3a7713b1edbc 1511 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1512 * @retval None
AnnaBridge 171:3a7713b1edbc 1513 */
AnnaBridge 171:3a7713b1edbc 1514 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1515 {
AnnaBridge 171:3a7713b1edbc 1516 CLEAR_BIT(I2Cx->SR1, I2C_SR1_SMBALERT);
AnnaBridge 171:3a7713b1edbc 1517 }
AnnaBridge 171:3a7713b1edbc 1518
AnnaBridge 171:3a7713b1edbc 1519 /**
AnnaBridge 171:3a7713b1edbc 1520 * @}
AnnaBridge 171:3a7713b1edbc 1521 */
AnnaBridge 171:3a7713b1edbc 1522
AnnaBridge 171:3a7713b1edbc 1523 /** @defgroup I2C_LL_EF_Data_Management Data_Management
AnnaBridge 171:3a7713b1edbc 1524 * @{
AnnaBridge 171:3a7713b1edbc 1525 */
AnnaBridge 171:3a7713b1edbc 1526
AnnaBridge 171:3a7713b1edbc 1527 /**
AnnaBridge 171:3a7713b1edbc 1528 * @brief Enable Reset of I2C peripheral.
AnnaBridge 171:3a7713b1edbc 1529 * @rmtoll CR1 SWRST LL_I2C_EnableReset
AnnaBridge 171:3a7713b1edbc 1530 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1531 * @retval None
AnnaBridge 171:3a7713b1edbc 1532 */
AnnaBridge 171:3a7713b1edbc 1533 __STATIC_INLINE void LL_I2C_EnableReset(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1534 {
AnnaBridge 171:3a7713b1edbc 1535 SET_BIT(I2Cx->CR1, I2C_CR1_SWRST);
AnnaBridge 171:3a7713b1edbc 1536 }
AnnaBridge 171:3a7713b1edbc 1537
AnnaBridge 171:3a7713b1edbc 1538 /**
AnnaBridge 171:3a7713b1edbc 1539 * @brief Disable Reset of I2C peripheral.
AnnaBridge 171:3a7713b1edbc 1540 * @rmtoll CR1 SWRST LL_I2C_DisableReset
AnnaBridge 171:3a7713b1edbc 1541 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1542 * @retval None
AnnaBridge 171:3a7713b1edbc 1543 */
AnnaBridge 171:3a7713b1edbc 1544 __STATIC_INLINE void LL_I2C_DisableReset(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1545 {
AnnaBridge 171:3a7713b1edbc 1546 CLEAR_BIT(I2Cx->CR1, I2C_CR1_SWRST);
AnnaBridge 171:3a7713b1edbc 1547 }
AnnaBridge 171:3a7713b1edbc 1548
AnnaBridge 171:3a7713b1edbc 1549 /**
AnnaBridge 171:3a7713b1edbc 1550 * @brief Check if the I2C peripheral is under reset state or not.
AnnaBridge 171:3a7713b1edbc 1551 * @rmtoll CR1 SWRST LL_I2C_IsResetEnabled
AnnaBridge 171:3a7713b1edbc 1552 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1553 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1554 */
AnnaBridge 171:3a7713b1edbc 1555 __STATIC_INLINE uint32_t LL_I2C_IsResetEnabled(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1556 {
AnnaBridge 171:3a7713b1edbc 1557 return (READ_BIT(I2Cx->CR1, I2C_CR1_SWRST) == (I2C_CR1_SWRST));
AnnaBridge 171:3a7713b1edbc 1558 }
AnnaBridge 171:3a7713b1edbc 1559
AnnaBridge 171:3a7713b1edbc 1560 /**
AnnaBridge 171:3a7713b1edbc 1561 * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
AnnaBridge 171:3a7713b1edbc 1562 * @note Usage in Slave or Master mode.
AnnaBridge 171:3a7713b1edbc 1563 * @rmtoll CR1 ACK LL_I2C_AcknowledgeNextData
AnnaBridge 171:3a7713b1edbc 1564 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1565 * @param TypeAcknowledge This parameter can be one of the following values:
AnnaBridge 171:3a7713b1edbc 1566 * @arg @ref LL_I2C_ACK
AnnaBridge 171:3a7713b1edbc 1567 * @arg @ref LL_I2C_NACK
AnnaBridge 171:3a7713b1edbc 1568 * @retval None
AnnaBridge 171:3a7713b1edbc 1569 */
AnnaBridge 171:3a7713b1edbc 1570 __STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
AnnaBridge 171:3a7713b1edbc 1571 {
AnnaBridge 171:3a7713b1edbc 1572 MODIFY_REG(I2Cx->CR1, I2C_CR1_ACK, TypeAcknowledge);
AnnaBridge 171:3a7713b1edbc 1573 }
AnnaBridge 171:3a7713b1edbc 1574
AnnaBridge 171:3a7713b1edbc 1575 /**
AnnaBridge 171:3a7713b1edbc 1576 * @brief Generate a START or RESTART condition
AnnaBridge 171:3a7713b1edbc 1577 * @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
AnnaBridge 171:3a7713b1edbc 1578 * This action has no effect when RELOAD is set.
AnnaBridge 171:3a7713b1edbc 1579 * @rmtoll CR1 START LL_I2C_GenerateStartCondition
AnnaBridge 171:3a7713b1edbc 1580 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1581 * @retval None
AnnaBridge 171:3a7713b1edbc 1582 */
AnnaBridge 171:3a7713b1edbc 1583 __STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1584 {
AnnaBridge 171:3a7713b1edbc 1585 SET_BIT(I2Cx->CR1, I2C_CR1_START);
AnnaBridge 171:3a7713b1edbc 1586 }
AnnaBridge 171:3a7713b1edbc 1587
AnnaBridge 171:3a7713b1edbc 1588 /**
AnnaBridge 171:3a7713b1edbc 1589 * @brief Generate a STOP condition after the current byte transfer (master mode).
AnnaBridge 171:3a7713b1edbc 1590 * @rmtoll CR1 STOP LL_I2C_GenerateStopCondition
AnnaBridge 171:3a7713b1edbc 1591 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1592 * @retval None
AnnaBridge 171:3a7713b1edbc 1593 */
AnnaBridge 171:3a7713b1edbc 1594 __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1595 {
AnnaBridge 171:3a7713b1edbc 1596 SET_BIT(I2Cx->CR1, I2C_CR1_STOP);
AnnaBridge 171:3a7713b1edbc 1597 }
AnnaBridge 171:3a7713b1edbc 1598
AnnaBridge 171:3a7713b1edbc 1599 /**
AnnaBridge 171:3a7713b1edbc 1600 * @brief Enable bit POS (master/host mode).
AnnaBridge 171:3a7713b1edbc 1601 * @note In that case, the ACK bit controls the (N)ACK of the next byte received or the PEC bit indicates that the next byte in shift register is a PEC.
AnnaBridge 171:3a7713b1edbc 1602 * @rmtoll CR1 POS LL_I2C_EnableBitPOS
AnnaBridge 171:3a7713b1edbc 1603 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1604 * @retval None
AnnaBridge 171:3a7713b1edbc 1605 */
AnnaBridge 171:3a7713b1edbc 1606 __STATIC_INLINE void LL_I2C_EnableBitPOS(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1607 {
AnnaBridge 171:3a7713b1edbc 1608 SET_BIT(I2Cx->CR1, I2C_CR1_POS);
AnnaBridge 171:3a7713b1edbc 1609 }
AnnaBridge 171:3a7713b1edbc 1610
AnnaBridge 171:3a7713b1edbc 1611 /**
AnnaBridge 171:3a7713b1edbc 1612 * @brief Disable bit POS (master/host mode).
AnnaBridge 171:3a7713b1edbc 1613 * @note In that case, the ACK bit controls the (N)ACK of the current byte received or the PEC bit indicates that the current byte in shift register is a PEC.
AnnaBridge 171:3a7713b1edbc 1614 * @rmtoll CR1 POS LL_I2C_DisableBitPOS
AnnaBridge 171:3a7713b1edbc 1615 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1616 * @retval None
AnnaBridge 171:3a7713b1edbc 1617 */
AnnaBridge 171:3a7713b1edbc 1618 __STATIC_INLINE void LL_I2C_DisableBitPOS(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1619 {
AnnaBridge 171:3a7713b1edbc 1620 CLEAR_BIT(I2Cx->CR1, I2C_CR1_POS);
AnnaBridge 171:3a7713b1edbc 1621 }
AnnaBridge 171:3a7713b1edbc 1622
AnnaBridge 171:3a7713b1edbc 1623 /**
AnnaBridge 171:3a7713b1edbc 1624 * @brief Check if bit POS is enabled or disabled.
AnnaBridge 171:3a7713b1edbc 1625 * @rmtoll CR1 POS LL_I2C_IsEnabledBitPOS
AnnaBridge 171:3a7713b1edbc 1626 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1627 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1628 */
AnnaBridge 171:3a7713b1edbc 1629 __STATIC_INLINE uint32_t LL_I2C_IsEnabledBitPOS(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1630 {
AnnaBridge 171:3a7713b1edbc 1631 return (READ_BIT(I2Cx->CR1, I2C_CR1_POS) == (I2C_CR1_POS));
AnnaBridge 171:3a7713b1edbc 1632 }
AnnaBridge 171:3a7713b1edbc 1633
AnnaBridge 171:3a7713b1edbc 1634 /**
AnnaBridge 171:3a7713b1edbc 1635 * @brief Indicate the value of transfer direction.
AnnaBridge 171:3a7713b1edbc 1636 * @note RESET: Bus is in read transfer (peripheral point of view).
AnnaBridge 171:3a7713b1edbc 1637 * SET: Bus is in write transfer (peripheral point of view).
AnnaBridge 171:3a7713b1edbc 1638 * @rmtoll SR2 TRA LL_I2C_GetTransferDirection
AnnaBridge 171:3a7713b1edbc 1639 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1640 * @retval Returned value can be one of the following values:
AnnaBridge 171:3a7713b1edbc 1641 * @arg @ref LL_I2C_DIRECTION_WRITE
AnnaBridge 171:3a7713b1edbc 1642 * @arg @ref LL_I2C_DIRECTION_READ
AnnaBridge 171:3a7713b1edbc 1643 */
AnnaBridge 171:3a7713b1edbc 1644 __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1645 {
AnnaBridge 171:3a7713b1edbc 1646 return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_TRA));
AnnaBridge 171:3a7713b1edbc 1647 }
AnnaBridge 171:3a7713b1edbc 1648
AnnaBridge 171:3a7713b1edbc 1649 /**
AnnaBridge 171:3a7713b1edbc 1650 * @brief Enable DMA last transfer.
AnnaBridge 171:3a7713b1edbc 1651 * @note This action mean that next DMA EOT is the last transfer.
AnnaBridge 171:3a7713b1edbc 1652 * @rmtoll CR2 LAST LL_I2C_EnableLastDMA
AnnaBridge 171:3a7713b1edbc 1653 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1654 * @retval None
AnnaBridge 171:3a7713b1edbc 1655 */
AnnaBridge 171:3a7713b1edbc 1656 __STATIC_INLINE void LL_I2C_EnableLastDMA(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1657 {
AnnaBridge 171:3a7713b1edbc 1658 SET_BIT(I2Cx->CR2, I2C_CR2_LAST);
AnnaBridge 171:3a7713b1edbc 1659 }
AnnaBridge 171:3a7713b1edbc 1660
AnnaBridge 171:3a7713b1edbc 1661 /**
AnnaBridge 171:3a7713b1edbc 1662 * @brief Disable DMA last transfer.
AnnaBridge 171:3a7713b1edbc 1663 * @note This action mean that next DMA EOT is not the last transfer.
AnnaBridge 171:3a7713b1edbc 1664 * @rmtoll CR2 LAST LL_I2C_DisableLastDMA
AnnaBridge 171:3a7713b1edbc 1665 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1666 * @retval None
AnnaBridge 171:3a7713b1edbc 1667 */
AnnaBridge 171:3a7713b1edbc 1668 __STATIC_INLINE void LL_I2C_DisableLastDMA(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1669 {
AnnaBridge 171:3a7713b1edbc 1670 CLEAR_BIT(I2Cx->CR2, I2C_CR2_LAST);
AnnaBridge 171:3a7713b1edbc 1671 }
AnnaBridge 171:3a7713b1edbc 1672
AnnaBridge 171:3a7713b1edbc 1673 /**
AnnaBridge 171:3a7713b1edbc 1674 * @brief Check if DMA last transfer is enabled or disabled.
AnnaBridge 171:3a7713b1edbc 1675 * @rmtoll CR2 LAST LL_I2C_IsEnabledLastDMA
AnnaBridge 171:3a7713b1edbc 1676 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1677 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1678 */
AnnaBridge 171:3a7713b1edbc 1679 __STATIC_INLINE uint32_t LL_I2C_IsEnabledLastDMA(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1680 {
AnnaBridge 171:3a7713b1edbc 1681 return (READ_BIT(I2Cx->CR2, I2C_CR2_LAST) == (I2C_CR2_LAST));
AnnaBridge 171:3a7713b1edbc 1682 }
AnnaBridge 171:3a7713b1edbc 1683
AnnaBridge 171:3a7713b1edbc 1684 /**
AnnaBridge 171:3a7713b1edbc 1685 * @brief Enable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
AnnaBridge 171:3a7713b1edbc 1686 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 171:3a7713b1edbc 1687 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 171:3a7713b1edbc 1688 * @note This feature is cleared by hardware when the PEC byte is transferred or compared,
AnnaBridge 171:3a7713b1edbc 1689 * or by a START or STOP condition, it is also cleared by software.
AnnaBridge 171:3a7713b1edbc 1690 * @rmtoll CR1 PEC LL_I2C_EnableSMBusPECCompare
AnnaBridge 171:3a7713b1edbc 1691 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1692 * @retval None
AnnaBridge 171:3a7713b1edbc 1693 */
AnnaBridge 171:3a7713b1edbc 1694 __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1695 {
AnnaBridge 171:3a7713b1edbc 1696 SET_BIT(I2Cx->CR1, I2C_CR1_PEC);
AnnaBridge 171:3a7713b1edbc 1697 }
AnnaBridge 171:3a7713b1edbc 1698
AnnaBridge 171:3a7713b1edbc 1699 /**
AnnaBridge 171:3a7713b1edbc 1700 * @brief Disable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
AnnaBridge 171:3a7713b1edbc 1701 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 171:3a7713b1edbc 1702 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 171:3a7713b1edbc 1703 * @rmtoll CR1 PEC LL_I2C_DisableSMBusPECCompare
AnnaBridge 171:3a7713b1edbc 1704 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1705 * @retval None
AnnaBridge 171:3a7713b1edbc 1706 */
AnnaBridge 171:3a7713b1edbc 1707 __STATIC_INLINE void LL_I2C_DisableSMBusPECCompare(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1708 {
AnnaBridge 171:3a7713b1edbc 1709 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PEC);
AnnaBridge 171:3a7713b1edbc 1710 }
AnnaBridge 171:3a7713b1edbc 1711
AnnaBridge 171:3a7713b1edbc 1712 /**
AnnaBridge 171:3a7713b1edbc 1713 * @brief Check if the SMBus Packet Error byte transfer or internal comparison is requested or not.
AnnaBridge 171:3a7713b1edbc 1714 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 171:3a7713b1edbc 1715 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 171:3a7713b1edbc 1716 * @rmtoll CR1 PEC LL_I2C_IsEnabledSMBusPECCompare
AnnaBridge 171:3a7713b1edbc 1717 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1718 * @retval State of bit (1 or 0).
AnnaBridge 171:3a7713b1edbc 1719 */
AnnaBridge 171:3a7713b1edbc 1720 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1721 {
AnnaBridge 171:3a7713b1edbc 1722 return (READ_BIT(I2Cx->CR1, I2C_CR1_PEC) == (I2C_CR1_PEC));
AnnaBridge 171:3a7713b1edbc 1723 }
AnnaBridge 171:3a7713b1edbc 1724
AnnaBridge 171:3a7713b1edbc 1725 /**
AnnaBridge 171:3a7713b1edbc 1726 * @brief Get the SMBus Packet Error byte calculated.
AnnaBridge 171:3a7713b1edbc 1727 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 171:3a7713b1edbc 1728 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 171:3a7713b1edbc 1729 * @rmtoll SR2 PEC LL_I2C_GetSMBusPEC
AnnaBridge 171:3a7713b1edbc 1730 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1731 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge 171:3a7713b1edbc 1732 */
AnnaBridge 171:3a7713b1edbc 1733 __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1734 {
AnnaBridge 171:3a7713b1edbc 1735 return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_PEC) >> I2C_SR2_PEC_Pos);
AnnaBridge 171:3a7713b1edbc 1736 }
AnnaBridge 171:3a7713b1edbc 1737
AnnaBridge 171:3a7713b1edbc 1738 /**
AnnaBridge 171:3a7713b1edbc 1739 * @brief Read Receive Data register.
AnnaBridge 171:3a7713b1edbc 1740 * @rmtoll DR DR LL_I2C_ReceiveData8
AnnaBridge 171:3a7713b1edbc 1741 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1742 * @retval Value between Min_Data=0x0 and Max_Data=0xFF
AnnaBridge 171:3a7713b1edbc 1743 */
AnnaBridge 171:3a7713b1edbc 1744 __STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
AnnaBridge 171:3a7713b1edbc 1745 {
AnnaBridge 171:3a7713b1edbc 1746 return (uint8_t)(READ_BIT(I2Cx->DR, I2C_DR_DR));
AnnaBridge 171:3a7713b1edbc 1747 }
AnnaBridge 171:3a7713b1edbc 1748
AnnaBridge 171:3a7713b1edbc 1749 /**
AnnaBridge 171:3a7713b1edbc 1750 * @brief Write in Transmit Data Register .
AnnaBridge 171:3a7713b1edbc 1751 * @rmtoll DR DR LL_I2C_TransmitData8
AnnaBridge 171:3a7713b1edbc 1752 * @param I2Cx I2C Instance.
AnnaBridge 171:3a7713b1edbc 1753 * @param Data Value between Min_Data=0x0 and Max_Data=0xFF
AnnaBridge 171:3a7713b1edbc 1754 * @retval None
AnnaBridge 171:3a7713b1edbc 1755 */
AnnaBridge 171:3a7713b1edbc 1756 __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
AnnaBridge 171:3a7713b1edbc 1757 {
AnnaBridge 171:3a7713b1edbc 1758 MODIFY_REG(I2Cx->DR, I2C_DR_DR, Data);
AnnaBridge 171:3a7713b1edbc 1759 }
AnnaBridge 171:3a7713b1edbc 1760
AnnaBridge 171:3a7713b1edbc 1761 /**
AnnaBridge 171:3a7713b1edbc 1762 * @}
AnnaBridge 171:3a7713b1edbc 1763 */
AnnaBridge 171:3a7713b1edbc 1764
AnnaBridge 171:3a7713b1edbc 1765 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 171:3a7713b1edbc 1766 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
AnnaBridge 171:3a7713b1edbc 1767 * @{
AnnaBridge 171:3a7713b1edbc 1768 */
AnnaBridge 171:3a7713b1edbc 1769
AnnaBridge 171:3a7713b1edbc 1770 uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
AnnaBridge 171:3a7713b1edbc 1771 uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
AnnaBridge 171:3a7713b1edbc 1772 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
AnnaBridge 171:3a7713b1edbc 1773
AnnaBridge 171:3a7713b1edbc 1774
AnnaBridge 171:3a7713b1edbc 1775 /**
AnnaBridge 171:3a7713b1edbc 1776 * @}
AnnaBridge 171:3a7713b1edbc 1777 */
AnnaBridge 171:3a7713b1edbc 1778 #endif /* USE_FULL_LL_DRIVER */
AnnaBridge 171:3a7713b1edbc 1779
AnnaBridge 171:3a7713b1edbc 1780 /**
AnnaBridge 171:3a7713b1edbc 1781 * @}
AnnaBridge 171:3a7713b1edbc 1782 */
AnnaBridge 171:3a7713b1edbc 1783
AnnaBridge 171:3a7713b1edbc 1784 /**
AnnaBridge 171:3a7713b1edbc 1785 * @}
AnnaBridge 171:3a7713b1edbc 1786 */
AnnaBridge 171:3a7713b1edbc 1787
AnnaBridge 171:3a7713b1edbc 1788 #endif /* I2C1 || I2C2 */
AnnaBridge 171:3a7713b1edbc 1789
AnnaBridge 171:3a7713b1edbc 1790 /**
AnnaBridge 171:3a7713b1edbc 1791 * @}
AnnaBridge 171:3a7713b1edbc 1792 */
AnnaBridge 171:3a7713b1edbc 1793
AnnaBridge 171:3a7713b1edbc 1794 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 1795 }
AnnaBridge 171:3a7713b1edbc 1796 #endif
AnnaBridge 171:3a7713b1edbc 1797
AnnaBridge 171:3a7713b1edbc 1798 #endif /* __STM32L1xx_LL_I2C_H */
AnnaBridge 171:3a7713b1edbc 1799
AnnaBridge 171:3a7713b1edbc 1800 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/