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TARGET_MOTE_L152RC/TOOLCHAIN_GCC_ARM/stm32l1xx_hal_adc.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

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AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file stm32l1xx_hal_adc.h
AnnaBridge 171:3a7713b1edbc 4 * @author MCD Application Team
AnnaBridge 171:3a7713b1edbc 5 * @brief Header file containing functions prototypes of ADC HAL library.
AnnaBridge 171:3a7713b1edbc 6 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 7 * @attention
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 12 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 14 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 17 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 171:3a7713b1edbc 19 * may be used to endorse or promote products derived from this software
AnnaBridge 171:3a7713b1edbc 20 * without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 171:3a7713b1edbc 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 171:3a7713b1edbc 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 171:3a7713b1edbc 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 171:3a7713b1edbc 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 171:3a7713b1edbc 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 171:3a7713b1edbc 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 171:3a7713b1edbc 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 32 *
AnnaBridge 171:3a7713b1edbc 33 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 34 */
AnnaBridge 171:3a7713b1edbc 35
AnnaBridge 171:3a7713b1edbc 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 171:3a7713b1edbc 37 #ifndef __STM32L1xx_HAL_ADC_H
AnnaBridge 171:3a7713b1edbc 38 #define __STM32L1xx_HAL_ADC_H
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 41 extern "C" {
AnnaBridge 171:3a7713b1edbc 42 #endif
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 /* Includes ------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 45 #include "stm32l1xx_hal_def.h"
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /* Include low level driver */
AnnaBridge 171:3a7713b1edbc 48 #include "stm32l1xx_ll_adc.h"
AnnaBridge 171:3a7713b1edbc 49
AnnaBridge 171:3a7713b1edbc 50 /** @addtogroup STM32L1xx_HAL_Driver
AnnaBridge 171:3a7713b1edbc 51 * @{
AnnaBridge 171:3a7713b1edbc 52 */
AnnaBridge 171:3a7713b1edbc 53
AnnaBridge 171:3a7713b1edbc 54 /** @addtogroup ADC
AnnaBridge 171:3a7713b1edbc 55 * @{
AnnaBridge 171:3a7713b1edbc 56 */
AnnaBridge 171:3a7713b1edbc 57
AnnaBridge 171:3a7713b1edbc 58 /* Exported types ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 59 /** @defgroup ADC_Exported_Types ADC Exported Types
AnnaBridge 171:3a7713b1edbc 60 * @{
AnnaBridge 171:3a7713b1edbc 61 */
AnnaBridge 171:3a7713b1edbc 62
AnnaBridge 171:3a7713b1edbc 63 /**
AnnaBridge 171:3a7713b1edbc 64 * @brief Structure definition of ADC and regular group initialization
AnnaBridge 171:3a7713b1edbc 65 * @note Parameters of this structure are shared within 2 scopes:
AnnaBridge 171:3a7713b1edbc 66 * - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.
AnnaBridge 171:3a7713b1edbc 67 * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
AnnaBridge 171:3a7713b1edbc 68 * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
AnnaBridge 171:3a7713b1edbc 69 * ADC state can be either:
AnnaBridge 171:3a7713b1edbc 70 * - For all parameters: ADC disabled
AnnaBridge 171:3a7713b1edbc 71 * - For all parameters except 'Resolution', 'ScanConvMode', 'LowPowerAutoWait', 'LowPowerAutoPowerOff', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.
AnnaBridge 171:3a7713b1edbc 72 * - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.
AnnaBridge 171:3a7713b1edbc 73 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
AnnaBridge 171:3a7713b1edbc 74 * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly).
AnnaBridge 171:3a7713b1edbc 75 */
AnnaBridge 171:3a7713b1edbc 76 typedef struct
AnnaBridge 171:3a7713b1edbc 77 {
AnnaBridge 171:3a7713b1edbc 78 uint32_t ClockPrescaler; /*!< Select ADC clock source (asynchronous clock derived from HSI RC oscillator) and clock prescaler.
AnnaBridge 171:3a7713b1edbc 79 This parameter can be a value of @ref ADC_ClockPrescaler
AnnaBridge 171:3a7713b1edbc 80 Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits,
AnnaBridge 171:3a7713b1edbc 81 AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits.
AnnaBridge 171:3a7713b1edbc 82 Note: HSI RC oscillator must be preliminarily enabled at RCC top level. */
AnnaBridge 171:3a7713b1edbc 83 uint32_t Resolution; /*!< Configures the ADC resolution.
AnnaBridge 171:3a7713b1edbc 84 This parameter can be a value of @ref ADC_Resolution */
AnnaBridge 171:3a7713b1edbc 85 uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
AnnaBridge 171:3a7713b1edbc 86 or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
AnnaBridge 171:3a7713b1edbc 87 This parameter can be a value of @ref ADC_Data_align */
AnnaBridge 171:3a7713b1edbc 88 uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
AnnaBridge 171:3a7713b1edbc 89 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
AnnaBridge 171:3a7713b1edbc 90 If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
AnnaBridge 171:3a7713b1edbc 91 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
AnnaBridge 171:3a7713b1edbc 92 If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
AnnaBridge 171:3a7713b1edbc 93 Scan direction is upward: from rank1 to rank 'n'.
AnnaBridge 171:3a7713b1edbc 94 This parameter can be a value of @ref ADC_Scan_mode */
AnnaBridge 171:3a7713b1edbc 95 uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
AnnaBridge 171:3a7713b1edbc 96 This parameter can be a value of @ref ADC_EOCSelection.
AnnaBridge 171:3a7713b1edbc 97 Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
AnnaBridge 171:3a7713b1edbc 98 Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
AnnaBridge 171:3a7713b1edbc 99 or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
AnnaBridge 171:3a7713b1edbc 100 Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).
AnnaBridge 171:3a7713b1edbc 101 If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */
AnnaBridge 171:3a7713b1edbc 102 uint32_t LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous
AnnaBridge 171:3a7713b1edbc 103 conversion (for regular group) or previous sequence (for injected group) has been treated by user software, using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue().
AnnaBridge 171:3a7713b1edbc 104 This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications.
AnnaBridge 171:3a7713b1edbc 105 This parameter can be a value of @ref ADC_LowPowerAutoWait.
AnnaBridge 171:3a7713b1edbc 106 Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer.
AnnaBridge 171:3a7713b1edbc 107 Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed
AnnaBridge 171:3a7713b1edbc 108 and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion (in case of usage of injected group, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...).
AnnaBridge 171:3a7713b1edbc 109 Note: ADC clock latency and some timing constraints depending on clock prescaler have to be taken into account: refer to reference manual (register ADC_CR2 bit DELS description). */
AnnaBridge 171:3a7713b1edbc 110 uint32_t LowPowerAutoPowerOff; /*!< Selects the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
AnnaBridge 171:3a7713b1edbc 111 This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait').
AnnaBridge 171:3a7713b1edbc 112 This parameter can be a value of @ref ADC_LowPowerAutoPowerOff. */
AnnaBridge 171:3a7713b1edbc 113 uint32_t ChannelsBank; /*!< Selects the ADC channels bank.
AnnaBridge 171:3a7713b1edbc 114 This parameter can be a value of @ref ADC_ChannelsBank.
AnnaBridge 171:3a7713b1edbc 115 Note: Banks availability depends on devices categories.
AnnaBridge 171:3a7713b1edbc 116 Note: To change bank selection on the fly, without going through execution of 'HAL_ADC_Init()', macro '__HAL_ADC_CHANNELS_BANK()' can be used directly. */
AnnaBridge 171:3a7713b1edbc 117 uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
AnnaBridge 171:3a7713b1edbc 118 after the selected trigger occurred (software start or external trigger).
AnnaBridge 171:3a7713b1edbc 119 This parameter can be set to ENABLE or DISABLE. */
AnnaBridge 171:3a7713b1edbc 120 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
AnnaBridge 171:3a7713b1edbc 121 uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
AnnaBridge 171:3a7713b1edbc 122 To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
AnnaBridge 171:3a7713b1edbc 123 This parameter must be a number between Min_Data = 1 and Max_Data = 28. */
AnnaBridge 171:3a7713b1edbc 124 #else
AnnaBridge 171:3a7713b1edbc 125 uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
AnnaBridge 171:3a7713b1edbc 126 To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
AnnaBridge 171:3a7713b1edbc 127 This parameter must be a number between Min_Data = 1 and Max_Data = 27. */
AnnaBridge 171:3a7713b1edbc 128 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
AnnaBridge 171:3a7713b1edbc 129 uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
AnnaBridge 171:3a7713b1edbc 130 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
AnnaBridge 171:3a7713b1edbc 131 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
AnnaBridge 171:3a7713b1edbc 132 This parameter can be set to ENABLE or DISABLE. */
AnnaBridge 171:3a7713b1edbc 133 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
AnnaBridge 171:3a7713b1edbc 134 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
AnnaBridge 171:3a7713b1edbc 135 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
AnnaBridge 171:3a7713b1edbc 136 uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
AnnaBridge 171:3a7713b1edbc 137 If set to ADC_SOFTWARE_START, external triggers are disabled.
AnnaBridge 171:3a7713b1edbc 138 If set to external trigger source, triggering is on event rising edge by default.
AnnaBridge 171:3a7713b1edbc 139 This parameter can be a value of @ref ADC_External_trigger_source_Regular */
AnnaBridge 171:3a7713b1edbc 140 uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
AnnaBridge 171:3a7713b1edbc 141 If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
AnnaBridge 171:3a7713b1edbc 142 This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
AnnaBridge 171:3a7713b1edbc 143 uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
AnnaBridge 171:3a7713b1edbc 144 or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
AnnaBridge 171:3a7713b1edbc 145 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
AnnaBridge 171:3a7713b1edbc 146 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
AnnaBridge 171:3a7713b1edbc 147 This parameter can be set to ENABLE or DISABLE. */
AnnaBridge 171:3a7713b1edbc 148 }ADC_InitTypeDef;
AnnaBridge 171:3a7713b1edbc 149
AnnaBridge 171:3a7713b1edbc 150 /**
AnnaBridge 171:3a7713b1edbc 151 * @brief Structure definition of ADC channel for regular group
AnnaBridge 171:3a7713b1edbc 152 * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
AnnaBridge 171:3a7713b1edbc 153 * ADC can be either disabled or enabled without conversion on going on regular group.
AnnaBridge 171:3a7713b1edbc 154 */
AnnaBridge 171:3a7713b1edbc 155 typedef struct
AnnaBridge 171:3a7713b1edbc 156 {
AnnaBridge 171:3a7713b1edbc 157 uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
AnnaBridge 171:3a7713b1edbc 158 This parameter can be a value of @ref ADC_channels
AnnaBridge 171:3a7713b1edbc 159 Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
AnnaBridge 171:3a7713b1edbc 160 Maximum number of channels by device category (without taking in account each device package constraints):
AnnaBridge 171:3a7713b1edbc 161 STM32L1 category 1, 2: 24 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 26.
AnnaBridge 171:3a7713b1edbc 162 STM32L1 category 3: 25 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 26, 1 additional channel in bank B. Note: OPAMP1 and OPAMP2 are connected internally but not increasing internal channels number: they are sharing ADC input with external channels ADC_IN3 and ADC_IN8.
AnnaBridge 171:3a7713b1edbc 163 STM32L1 category 4, 5: 40 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 31, 11 additional channels in bank B. Note: OPAMP1 and OPAMP2 are connected internally but not increasing internal channels number: they are sharing ADC input with external channels ADC_IN3 and ADC_IN8.
AnnaBridge 171:3a7713b1edbc 164 Note: In case of peripherals OPAMPx not used: 3 channels (3, 8, 13) can be configured as direct channels (fast channels). Refer to macro ' __HAL_ADC_CHANNEL_SPEED_FAST() '.
AnnaBridge 171:3a7713b1edbc 165 Note: In case of peripheral OPAMP3 and ADC channel OPAMP3 used (OPAMP3 available on STM32L1 devices Cat.4 only): the analog switch COMP1_SW1 must be closed. Refer to macro: ' __HAL_OPAMP_OPAMP3OUT_CONNECT_ADC_COMP1() '. */
AnnaBridge 171:3a7713b1edbc 166 uint32_t Rank; /*!< Specifies the rank in the regular group sequencer.
AnnaBridge 171:3a7713b1edbc 167 This parameter can be a value of @ref ADC_regular_rank
AnnaBridge 171:3a7713b1edbc 168 Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
AnnaBridge 171:3a7713b1edbc 169 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
AnnaBridge 171:3a7713b1edbc 170 Unit: ADC clock cycles
AnnaBridge 171:3a7713b1edbc 171 Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
AnnaBridge 171:3a7713b1edbc 172 This parameter can be a value of @ref ADC_sampling_times
AnnaBridge 171:3a7713b1edbc 173 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
AnnaBridge 171:3a7713b1edbc 174 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
AnnaBridge 171:3a7713b1edbc 175 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
AnnaBridge 171:3a7713b1edbc 176 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
AnnaBridge 171:3a7713b1edbc 177 Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
AnnaBridge 171:3a7713b1edbc 178 }ADC_ChannelConfTypeDef;
AnnaBridge 171:3a7713b1edbc 179
AnnaBridge 171:3a7713b1edbc 180 /**
AnnaBridge 171:3a7713b1edbc 181 * @brief ADC Configuration analog watchdog definition
AnnaBridge 171:3a7713b1edbc 182 * @note The setting of these parameters with function is conditioned to ADC state.
AnnaBridge 171:3a7713b1edbc 183 * ADC state can be either disabled or enabled without conversion on going on regular and injected groups.
AnnaBridge 171:3a7713b1edbc 184 */
AnnaBridge 171:3a7713b1edbc 185 typedef struct
AnnaBridge 171:3a7713b1edbc 186 {
AnnaBridge 171:3a7713b1edbc 187 uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group.
AnnaBridge 171:3a7713b1edbc 188 This parameter can be a value of @ref ADC_analog_watchdog_mode. */
AnnaBridge 171:3a7713b1edbc 189 uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
AnnaBridge 171:3a7713b1edbc 190 This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
AnnaBridge 171:3a7713b1edbc 191 This parameter can be a value of @ref ADC_channels. */
AnnaBridge 171:3a7713b1edbc 192 uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
AnnaBridge 171:3a7713b1edbc 193 This parameter can be set to ENABLE or DISABLE */
AnnaBridge 171:3a7713b1edbc 194 uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
AnnaBridge 171:3a7713b1edbc 195 This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
AnnaBridge 171:3a7713b1edbc 196 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
AnnaBridge 171:3a7713b1edbc 197 This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
AnnaBridge 171:3a7713b1edbc 198 uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
AnnaBridge 171:3a7713b1edbc 199 }ADC_AnalogWDGConfTypeDef;
AnnaBridge 171:3a7713b1edbc 200
AnnaBridge 171:3a7713b1edbc 201 /**
AnnaBridge 171:3a7713b1edbc 202 * @brief HAL ADC state machine: ADC states definition (bitfields)
AnnaBridge 171:3a7713b1edbc 203 */
AnnaBridge 171:3a7713b1edbc 204 /* States of ADC global scope */
AnnaBridge 171:3a7713b1edbc 205 #define HAL_ADC_STATE_RESET (0x00000000U) /*!< ADC not yet initialized or disabled */
AnnaBridge 171:3a7713b1edbc 206 #define HAL_ADC_STATE_READY (0x00000001U) /*!< ADC peripheral ready for use */
AnnaBridge 171:3a7713b1edbc 207 #define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */
AnnaBridge 171:3a7713b1edbc 208 #define HAL_ADC_STATE_TIMEOUT (0x00000004U) /*!< TimeOut occurrence */
AnnaBridge 171:3a7713b1edbc 209
AnnaBridge 171:3a7713b1edbc 210 /* States of ADC errors */
AnnaBridge 171:3a7713b1edbc 211 #define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010U) /*!< Internal error occurrence */
AnnaBridge 171:3a7713b1edbc 212 #define HAL_ADC_STATE_ERROR_CONFIG (0x00000020U) /*!< Configuration error occurrence */
AnnaBridge 171:3a7713b1edbc 213 #define HAL_ADC_STATE_ERROR_DMA (0x00000040U) /*!< DMA error occurrence */
AnnaBridge 171:3a7713b1edbc 214
AnnaBridge 171:3a7713b1edbc 215 /* States of ADC group regular */
AnnaBridge 171:3a7713b1edbc 216 #define HAL_ADC_STATE_REG_BUSY (0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
AnnaBridge 171:3a7713b1edbc 217 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
AnnaBridge 171:3a7713b1edbc 218 #define HAL_ADC_STATE_REG_EOC (0x00000200U) /*!< Conversion data available on group regular */
AnnaBridge 171:3a7713b1edbc 219 #define HAL_ADC_STATE_REG_OVR (0x00000400U) /*!< Overrun occurrence */
AnnaBridge 171:3a7713b1edbc 220 #define HAL_ADC_STATE_REG_EOSMP (0x00000800U) /*!< Not available on STM32L1 device: End Of Sampling flag raised */
AnnaBridge 171:3a7713b1edbc 221
AnnaBridge 171:3a7713b1edbc 222 /* States of ADC group injected */
AnnaBridge 171:3a7713b1edbc 223 #define HAL_ADC_STATE_INJ_BUSY (0x00001000U) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
AnnaBridge 171:3a7713b1edbc 224 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
AnnaBridge 171:3a7713b1edbc 225 #define HAL_ADC_STATE_INJ_EOC (0x00002000U) /*!< Conversion data available on group injected */
AnnaBridge 171:3a7713b1edbc 226 #define HAL_ADC_STATE_INJ_JQOVF (0x00004000U) /*!< Not available on STM32L1 device: Injected queue overflow occurrence */
AnnaBridge 171:3a7713b1edbc 227
AnnaBridge 171:3a7713b1edbc 228 /* States of ADC analog watchdogs */
AnnaBridge 171:3a7713b1edbc 229 #define HAL_ADC_STATE_AWD1 (0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */
AnnaBridge 171:3a7713b1edbc 230 #define HAL_ADC_STATE_AWD2 (0x00020000U) /*!< Not available on STM32L1 device: Out-of-window occurrence of analog watchdog 2 */
AnnaBridge 171:3a7713b1edbc 231 #define HAL_ADC_STATE_AWD3 (0x00040000U) /*!< Not available on STM32L1 device: Out-of-window occurrence of analog watchdog 3 */
AnnaBridge 171:3a7713b1edbc 232
AnnaBridge 171:3a7713b1edbc 233 /* States of ADC multi-mode */
AnnaBridge 171:3a7713b1edbc 234 #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000U) /*!< Not available on STM32L1 device: ADC in multimode slave state, controlled by another ADC master ( */
AnnaBridge 171:3a7713b1edbc 235
AnnaBridge 171:3a7713b1edbc 236
AnnaBridge 171:3a7713b1edbc 237 /**
AnnaBridge 171:3a7713b1edbc 238 * @brief ADC handle Structure definition
AnnaBridge 171:3a7713b1edbc 239 */
AnnaBridge 171:3a7713b1edbc 240 typedef struct
AnnaBridge 171:3a7713b1edbc 241 {
AnnaBridge 171:3a7713b1edbc 242 ADC_TypeDef *Instance; /*!< Register base address */
AnnaBridge 171:3a7713b1edbc 243
AnnaBridge 171:3a7713b1edbc 244 ADC_InitTypeDef Init; /*!< ADC required parameters */
AnnaBridge 171:3a7713b1edbc 245
AnnaBridge 171:3a7713b1edbc 246 __IO uint32_t NbrOfConversionRank ; /*!< ADC conversion rank counter */
AnnaBridge 171:3a7713b1edbc 247
AnnaBridge 171:3a7713b1edbc 248 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
AnnaBridge 171:3a7713b1edbc 249
AnnaBridge 171:3a7713b1edbc 250 HAL_LockTypeDef Lock; /*!< ADC locking object */
AnnaBridge 171:3a7713b1edbc 251
AnnaBridge 171:3a7713b1edbc 252 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
AnnaBridge 171:3a7713b1edbc 253
AnnaBridge 171:3a7713b1edbc 254 __IO uint32_t ErrorCode; /*!< ADC Error code */
AnnaBridge 171:3a7713b1edbc 255 }ADC_HandleTypeDef;
AnnaBridge 171:3a7713b1edbc 256 /**
AnnaBridge 171:3a7713b1edbc 257 * @}
AnnaBridge 171:3a7713b1edbc 258 */
AnnaBridge 171:3a7713b1edbc 259
AnnaBridge 171:3a7713b1edbc 260
AnnaBridge 171:3a7713b1edbc 261
AnnaBridge 171:3a7713b1edbc 262 /* Exported constants --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 263
AnnaBridge 171:3a7713b1edbc 264 /** @defgroup ADC_Exported_Constants ADC Exported Constants
AnnaBridge 171:3a7713b1edbc 265 * @{
AnnaBridge 171:3a7713b1edbc 266 */
AnnaBridge 171:3a7713b1edbc 267
AnnaBridge 171:3a7713b1edbc 268 /** @defgroup ADC_Error_Code ADC Error Code
AnnaBridge 171:3a7713b1edbc 269 * @{
AnnaBridge 171:3a7713b1edbc 270 */
AnnaBridge 171:3a7713b1edbc 271 #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */
AnnaBridge 171:3a7713b1edbc 272 #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC IP internal error: if problem of clocking,
AnnaBridge 171:3a7713b1edbc 273 enable/disable, erroneous state */
AnnaBridge 171:3a7713b1edbc 274 #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */
AnnaBridge 171:3a7713b1edbc 275 #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */
AnnaBridge 171:3a7713b1edbc 276 /**
AnnaBridge 171:3a7713b1edbc 277 * @}
AnnaBridge 171:3a7713b1edbc 278 */
AnnaBridge 171:3a7713b1edbc 279
AnnaBridge 171:3a7713b1edbc 280 /** @defgroup ADC_ClockPrescaler ADC ClockPrescaler
AnnaBridge 171:3a7713b1edbc 281 * @{
AnnaBridge 171:3a7713b1edbc 282 */
AnnaBridge 171:3a7713b1edbc 283 #define ADC_CLOCK_ASYNC_DIV1 (0x00000000U) /*!< ADC asynchronous clock derived from ADC dedicated HSI without prescaler */
AnnaBridge 171:3a7713b1edbc 284 #define ADC_CLOCK_ASYNC_DIV2 ((uint32_t)ADC_CCR_ADCPRE_0) /*!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 2 */
AnnaBridge 171:3a7713b1edbc 285 #define ADC_CLOCK_ASYNC_DIV4 ((uint32_t)ADC_CCR_ADCPRE_1) /*!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 4 */
AnnaBridge 171:3a7713b1edbc 286 /**
AnnaBridge 171:3a7713b1edbc 287 * @}
AnnaBridge 171:3a7713b1edbc 288 */
AnnaBridge 171:3a7713b1edbc 289
AnnaBridge 171:3a7713b1edbc 290 /** @defgroup ADC_Resolution ADC Resolution
AnnaBridge 171:3a7713b1edbc 291 * @{
AnnaBridge 171:3a7713b1edbc 292 */
AnnaBridge 171:3a7713b1edbc 293 #define ADC_RESOLUTION_12B (0x00000000U) /*!< ADC 12-bit resolution */
AnnaBridge 171:3a7713b1edbc 294 #define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0) /*!< ADC 10-bit resolution */
AnnaBridge 171:3a7713b1edbc 295 #define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1) /*!< ADC 8-bit resolution */
AnnaBridge 171:3a7713b1edbc 296 #define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES) /*!< ADC 6-bit resolution */
AnnaBridge 171:3a7713b1edbc 297 /**
AnnaBridge 171:3a7713b1edbc 298 * @}
AnnaBridge 171:3a7713b1edbc 299 */
AnnaBridge 171:3a7713b1edbc 300
AnnaBridge 171:3a7713b1edbc 301 /** @defgroup ADC_Data_align ADC Data_align
AnnaBridge 171:3a7713b1edbc 302 * @{
AnnaBridge 171:3a7713b1edbc 303 */
AnnaBridge 171:3a7713b1edbc 304 #define ADC_DATAALIGN_RIGHT (0x00000000U)
AnnaBridge 171:3a7713b1edbc 305 #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
AnnaBridge 171:3a7713b1edbc 306 /**
AnnaBridge 171:3a7713b1edbc 307 * @}
AnnaBridge 171:3a7713b1edbc 308 */
AnnaBridge 171:3a7713b1edbc 309
AnnaBridge 171:3a7713b1edbc 310 /** @defgroup ADC_Scan_mode ADC Scan mode
AnnaBridge 171:3a7713b1edbc 311 * @{
AnnaBridge 171:3a7713b1edbc 312 */
AnnaBridge 171:3a7713b1edbc 313 #define ADC_SCAN_DISABLE (0x00000000U)
AnnaBridge 171:3a7713b1edbc 314 #define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN)
AnnaBridge 171:3a7713b1edbc 315 /**
AnnaBridge 171:3a7713b1edbc 316 * @}
AnnaBridge 171:3a7713b1edbc 317 */
AnnaBridge 171:3a7713b1edbc 318
AnnaBridge 171:3a7713b1edbc 319 /** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group
AnnaBridge 171:3a7713b1edbc 320 * @{
AnnaBridge 171:3a7713b1edbc 321 */
AnnaBridge 171:3a7713b1edbc 322 #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000U)
AnnaBridge 171:3a7713b1edbc 323 #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
AnnaBridge 171:3a7713b1edbc 324 #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
AnnaBridge 171:3a7713b1edbc 325 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
AnnaBridge 171:3a7713b1edbc 326 /**
AnnaBridge 171:3a7713b1edbc 327 * @}
AnnaBridge 171:3a7713b1edbc 328 */
AnnaBridge 171:3a7713b1edbc 329
AnnaBridge 171:3a7713b1edbc 330 /** @defgroup ADC_External_trigger_source_Regular ADC External trigger source Regular
AnnaBridge 171:3a7713b1edbc 331 * @{
AnnaBridge 171:3a7713b1edbc 332 */
AnnaBridge 171:3a7713b1edbc 333 /* List of external triggers with generic trigger name, sorted by trigger */
AnnaBridge 171:3a7713b1edbc 334 /* name: */
AnnaBridge 171:3a7713b1edbc 335
AnnaBridge 171:3a7713b1edbc 336 /* External triggers of regular group for ADC1 */
AnnaBridge 171:3a7713b1edbc 337 #define ADC_EXTERNALTRIGCONV_T2_CC3 ADC_EXTERNALTRIG_T2_CC3
AnnaBridge 171:3a7713b1edbc 338 #define ADC_EXTERNALTRIGCONV_T2_CC2 ADC_EXTERNALTRIG_T2_CC2
AnnaBridge 171:3a7713b1edbc 339 #define ADC_EXTERNALTRIGCONV_T2_TRGO ADC_EXTERNALTRIG_T2_TRGO
AnnaBridge 171:3a7713b1edbc 340 #define ADC_EXTERNALTRIGCONV_T3_CC1 ADC_EXTERNALTRIG_T3_CC1
AnnaBridge 171:3a7713b1edbc 341 #define ADC_EXTERNALTRIGCONV_T3_CC3 ADC_EXTERNALTRIG_T3_CC3
AnnaBridge 171:3a7713b1edbc 342 #define ADC_EXTERNALTRIGCONV_T3_TRGO ADC_EXTERNALTRIG_T3_TRGO
AnnaBridge 171:3a7713b1edbc 343 #define ADC_EXTERNALTRIGCONV_T4_CC4 ADC_EXTERNALTRIG_T4_CC4
AnnaBridge 171:3a7713b1edbc 344 #define ADC_EXTERNALTRIGCONV_T4_TRGO ADC_EXTERNALTRIG_T4_TRGO
AnnaBridge 171:3a7713b1edbc 345 #define ADC_EXTERNALTRIGCONV_T6_TRGO ADC_EXTERNALTRIG_T6_TRGO
AnnaBridge 171:3a7713b1edbc 346 #define ADC_EXTERNALTRIGCONV_T9_CC2 ADC_EXTERNALTRIG_T9_CC2
AnnaBridge 171:3a7713b1edbc 347 #define ADC_EXTERNALTRIGCONV_T9_TRGO ADC_EXTERNALTRIG_T9_TRGO
AnnaBridge 171:3a7713b1edbc 348 #define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC_EXTERNALTRIG_EXT_IT11
AnnaBridge 171:3a7713b1edbc 349 #define ADC_SOFTWARE_START (0x00000010U)
AnnaBridge 171:3a7713b1edbc 350 /**
AnnaBridge 171:3a7713b1edbc 351 * @}
AnnaBridge 171:3a7713b1edbc 352 */
AnnaBridge 171:3a7713b1edbc 353
AnnaBridge 171:3a7713b1edbc 354 /** @defgroup ADC_EOCSelection ADC EOCSelection
AnnaBridge 171:3a7713b1edbc 355 * @{
AnnaBridge 171:3a7713b1edbc 356 */
AnnaBridge 171:3a7713b1edbc 357 #define ADC_EOC_SEQ_CONV (0x00000000U)
AnnaBridge 171:3a7713b1edbc 358 #define ADC_EOC_SINGLE_CONV ((uint32_t)ADC_CR2_EOCS)
AnnaBridge 171:3a7713b1edbc 359 /**
AnnaBridge 171:3a7713b1edbc 360 * @}
AnnaBridge 171:3a7713b1edbc 361 */
AnnaBridge 171:3a7713b1edbc 362
AnnaBridge 171:3a7713b1edbc 363 /** @defgroup ADC_LowPowerAutoWait ADC LowPowerAutoWait
AnnaBridge 171:3a7713b1edbc 364 * @{
AnnaBridge 171:3a7713b1edbc 365 */
AnnaBridge 171:3a7713b1edbc 366 /*!< Note : For compatibility with other STM32 devices with ADC autowait */
AnnaBridge 171:3a7713b1edbc 367 /* feature limited to enable or disable settings: */
AnnaBridge 171:3a7713b1edbc 368 /* Setting "ADC_AUTOWAIT_UNTIL_DATA_READ" is equivalent to "ENABLE". */
AnnaBridge 171:3a7713b1edbc 369
AnnaBridge 171:3a7713b1edbc 370 #define ADC_AUTOWAIT_DISABLE (0x00000000U)
AnnaBridge 171:3a7713b1edbc 371 #define ADC_AUTOWAIT_UNTIL_DATA_READ ((uint32_t)( ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: infinite delay, until the result of previous conversion is read */
AnnaBridge 171:3a7713b1edbc 372 #define ADC_AUTOWAIT_7_APBCLOCKCYCLES ((uint32_t)( ADC_CR2_DELS_1 )) /*!< Insert a delay between ADC conversions: 7 APB clock cycles */
AnnaBridge 171:3a7713b1edbc 373 #define ADC_AUTOWAIT_15_APBCLOCKCYCLES ((uint32_t)( ADC_CR2_DELS_1 | ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: 15 APB clock cycles */
AnnaBridge 171:3a7713b1edbc 374 #define ADC_AUTOWAIT_31_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 )) /*!< Insert a delay between ADC conversions: 31 APB clock cycles */
AnnaBridge 171:3a7713b1edbc 375 #define ADC_AUTOWAIT_63_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 | ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: 63 APB clock cycles */
AnnaBridge 171:3a7713b1edbc 376 #define ADC_AUTOWAIT_127_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 | ADC_CR2_DELS_1 )) /*!< Insert a delay between ADC conversions: 127 APB clock cycles */
AnnaBridge 171:3a7713b1edbc 377 #define ADC_AUTOWAIT_255_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 | ADC_CR2_DELS_1 | ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: 255 APB clock cycles */
AnnaBridge 171:3a7713b1edbc 378
AnnaBridge 171:3a7713b1edbc 379 /**
AnnaBridge 171:3a7713b1edbc 380 * @}
AnnaBridge 171:3a7713b1edbc 381 */
AnnaBridge 171:3a7713b1edbc 382
AnnaBridge 171:3a7713b1edbc 383 /** @defgroup ADC_LowPowerAutoPowerOff ADC LowPowerAutoPowerOff
AnnaBridge 171:3a7713b1edbc 384 * @{
AnnaBridge 171:3a7713b1edbc 385 */
AnnaBridge 171:3a7713b1edbc 386 #define ADC_AUTOPOWEROFF_DISABLE (0x00000000U)
AnnaBridge 171:3a7713b1edbc 387 #define ADC_AUTOPOWEROFF_IDLE_PHASE ((uint32_t)ADC_CR1_PDI) /*!< ADC power off when ADC is not converting (idle phase) */
AnnaBridge 171:3a7713b1edbc 388 #define ADC_AUTOPOWEROFF_DELAY_PHASE ((uint32_t)ADC_CR1_PDD) /*!< ADC power off when a delay is inserted between conversions (see parameter ADC_LowPowerAutoWait) */
AnnaBridge 171:3a7713b1edbc 389 #define ADC_AUTOPOWEROFF_IDLE_DELAY_PHASES ((uint32_t)(ADC_CR1_PDI | ADC_CR1_PDD)) /*!< ADC power off when ADC is not converting (idle phase) and when a delay is inserted between conversions */
AnnaBridge 171:3a7713b1edbc 390 /**
AnnaBridge 171:3a7713b1edbc 391 * @}
AnnaBridge 171:3a7713b1edbc 392 */
AnnaBridge 171:3a7713b1edbc 393
AnnaBridge 171:3a7713b1edbc 394
AnnaBridge 171:3a7713b1edbc 395 /** @defgroup ADC_ChannelsBank ADC ChannelsBank
AnnaBridge 171:3a7713b1edbc 396 * @{
AnnaBridge 171:3a7713b1edbc 397 */
AnnaBridge 171:3a7713b1edbc 398 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
AnnaBridge 171:3a7713b1edbc 399 #define ADC_CHANNELS_BANK_A (0x00000000U)
AnnaBridge 171:3a7713b1edbc 400 #define ADC_CHANNELS_BANK_B ((uint32_t)ADC_CR2_CFG)
AnnaBridge 171:3a7713b1edbc 401
AnnaBridge 171:3a7713b1edbc 402 #define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A) || \
AnnaBridge 171:3a7713b1edbc 403 ((BANK) == ADC_CHANNELS_BANK_B) )
AnnaBridge 171:3a7713b1edbc 404 #else
AnnaBridge 171:3a7713b1edbc 405 #define ADC_CHANNELS_BANK_A (0x00000000U)
AnnaBridge 171:3a7713b1edbc 406
AnnaBridge 171:3a7713b1edbc 407 #define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A))
AnnaBridge 171:3a7713b1edbc 408 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
AnnaBridge 171:3a7713b1edbc 409 /**
AnnaBridge 171:3a7713b1edbc 410 * @}
AnnaBridge 171:3a7713b1edbc 411 */
AnnaBridge 171:3a7713b1edbc 412
AnnaBridge 171:3a7713b1edbc 413 /** @defgroup ADC_channels ADC channels
AnnaBridge 171:3a7713b1edbc 414 * @{
AnnaBridge 171:3a7713b1edbc 415 */
AnnaBridge 171:3a7713b1edbc 416 /* Note: Depending on devices, some channels may not be available on package */
AnnaBridge 171:3a7713b1edbc 417 /* pins. Refer to device datasheet for channels availability. */
AnnaBridge 171:3a7713b1edbc 418 #define ADC_CHANNEL_0 (0x00000000U) /* Channel different in bank A and bank B */
AnnaBridge 171:3a7713b1edbc 419 #define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
AnnaBridge 171:3a7713b1edbc 420 #define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */
AnnaBridge 171:3a7713b1edbc 421 #define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
AnnaBridge 171:3a7713b1edbc 422 #define ADC_CHANNEL_4 ((uint32_t)( ADC_SQR5_SQ1_2 )) /* Direct (fast) channel */
AnnaBridge 171:3a7713b1edbc 423 #define ADC_CHANNEL_5 ((uint32_t)( ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_0)) /* Direct (fast) channel */
AnnaBridge 171:3a7713b1edbc 424 #define ADC_CHANNEL_6 ((uint32_t)( ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */
AnnaBridge 171:3a7713b1edbc 425 #define ADC_CHANNEL_7 ((uint32_t)( ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
AnnaBridge 171:3a7713b1edbc 426 #define ADC_CHANNEL_8 ((uint32_t)( ADC_SQR5_SQ1_3 )) /* Channel different in bank A and bank B */
AnnaBridge 171:3a7713b1edbc 427 #define ADC_CHANNEL_9 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
AnnaBridge 171:3a7713b1edbc 428 #define ADC_CHANNEL_10 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */
AnnaBridge 171:3a7713b1edbc 429 #define ADC_CHANNEL_11 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
AnnaBridge 171:3a7713b1edbc 430 #define ADC_CHANNEL_12 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 )) /* Channel different in bank A and bank B */
AnnaBridge 171:3a7713b1edbc 431 #define ADC_CHANNEL_13 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
AnnaBridge 171:3a7713b1edbc 432 #define ADC_CHANNEL_14 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */
AnnaBridge 171:3a7713b1edbc 433 #define ADC_CHANNEL_15 ((uint32_t)( ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
AnnaBridge 171:3a7713b1edbc 434 #define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR5_SQ1_4 )) /* Channel common to both bank A and bank B */
AnnaBridge 171:3a7713b1edbc 435 #define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
AnnaBridge 171:3a7713b1edbc 436 #define ADC_CHANNEL_18 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */
AnnaBridge 171:3a7713b1edbc 437 #define ADC_CHANNEL_19 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
AnnaBridge 171:3a7713b1edbc 438 #define ADC_CHANNEL_20 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_2 )) /* Channel common to both bank A and bank B */
AnnaBridge 171:3a7713b1edbc 439 #define ADC_CHANNEL_21 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
AnnaBridge 171:3a7713b1edbc 440 #define ADC_CHANNEL_22 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 )) /* Direct (fast) channel */
AnnaBridge 171:3a7713b1edbc 441 #define ADC_CHANNEL_23 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Direct (fast) channel */
AnnaBridge 171:3a7713b1edbc 442 #define ADC_CHANNEL_24 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 )) /* Direct (fast) channel */
AnnaBridge 171:3a7713b1edbc 443 #define ADC_CHANNEL_25 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_0)) /* Direct (fast) channel */
AnnaBridge 171:3a7713b1edbc 444 #define ADC_CHANNEL_26 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */
AnnaBridge 171:3a7713b1edbc 445 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
AnnaBridge 171:3a7713b1edbc 446 #define ADC_CHANNEL_27 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
AnnaBridge 171:3a7713b1edbc 447 #define ADC_CHANNEL_28 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 )) /* Channel common to both bank A and bank B */
AnnaBridge 171:3a7713b1edbc 448 #define ADC_CHANNEL_29 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
AnnaBridge 171:3a7713b1edbc 449 #define ADC_CHANNEL_30 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */
AnnaBridge 171:3a7713b1edbc 450 #define ADC_CHANNEL_31 ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
AnnaBridge 171:3a7713b1edbc 451 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
AnnaBridge 171:3a7713b1edbc 452
AnnaBridge 171:3a7713b1edbc 453 #define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */
AnnaBridge 171:3a7713b1edbc 454 #define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */
AnnaBridge 171:3a7713b1edbc 455 #define ADC_CHANNEL_VCOMP ADC_CHANNEL_26 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */
AnnaBridge 171:3a7713b1edbc 456
AnnaBridge 171:3a7713b1edbc 457 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
AnnaBridge 171:3a7713b1edbc 458 #define ADC_CHANNEL_VOPAMP1 ADC_CHANNEL_3 /* Internal connection from OPAMP1 output to ADC switch matrix */
AnnaBridge 171:3a7713b1edbc 459 #define ADC_CHANNEL_VOPAMP2 ADC_CHANNEL_8 /* Internal connection from OPAMP2 output to ADC switch matrix */
AnnaBridge 171:3a7713b1edbc 460 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD)
AnnaBridge 171:3a7713b1edbc 461 #define ADC_CHANNEL_VOPAMP3 ADC_CHANNEL_13 /* Internal connection from OPAMP3 output to ADC switch matrix */
AnnaBridge 171:3a7713b1edbc 462 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD */
AnnaBridge 171:3a7713b1edbc 463 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
AnnaBridge 171:3a7713b1edbc 464 /**
AnnaBridge 171:3a7713b1edbc 465 * @}
AnnaBridge 171:3a7713b1edbc 466 */
AnnaBridge 171:3a7713b1edbc 467
AnnaBridge 171:3a7713b1edbc 468 /** @defgroup ADC_sampling_times ADC sampling times
AnnaBridge 171:3a7713b1edbc 469 * @{
AnnaBridge 171:3a7713b1edbc 470 */
AnnaBridge 171:3a7713b1edbc 471 #define ADC_SAMPLETIME_4CYCLES (0x00000000U) /*!< Sampling time 4 ADC clock cycles */
AnnaBridge 171:3a7713b1edbc 472 #define ADC_SAMPLETIME_9CYCLES ((uint32_t) ADC_SMPR3_SMP0_0) /*!< Sampling time 9 ADC clock cycles */
AnnaBridge 171:3a7713b1edbc 473 #define ADC_SAMPLETIME_16CYCLES ((uint32_t) ADC_SMPR3_SMP0_1) /*!< Sampling time 16 ADC clock cycles */
AnnaBridge 171:3a7713b1edbc 474 #define ADC_SAMPLETIME_24CYCLES ((uint32_t)(ADC_SMPR3_SMP0_1 | ADC_SMPR3_SMP0_0)) /*!< Sampling time 24 ADC clock cycles */
AnnaBridge 171:3a7713b1edbc 475 #define ADC_SAMPLETIME_48CYCLES ((uint32_t) ADC_SMPR3_SMP0_2) /*!< Sampling time 48 ADC clock cycles */
AnnaBridge 171:3a7713b1edbc 476 #define ADC_SAMPLETIME_96CYCLES ((uint32_t)(ADC_SMPR3_SMP0_2 | ADC_SMPR3_SMP0_0)) /*!< Sampling time 96 ADC clock cycles */
AnnaBridge 171:3a7713b1edbc 477 #define ADC_SAMPLETIME_192CYCLES ((uint32_t)(ADC_SMPR3_SMP0_2 | ADC_SMPR3_SMP0_1)) /*!< Sampling time 192 ADC clock cycles */
AnnaBridge 171:3a7713b1edbc 478 #define ADC_SAMPLETIME_384CYCLES ((uint32_t) ADC_SMPR3_SMP0) /*!< Sampling time 384 ADC clock cycles */
AnnaBridge 171:3a7713b1edbc 479 /**
AnnaBridge 171:3a7713b1edbc 480 * @}
AnnaBridge 171:3a7713b1edbc 481 */
AnnaBridge 171:3a7713b1edbc 482
AnnaBridge 171:3a7713b1edbc 483 /** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels
AnnaBridge 171:3a7713b1edbc 484 * @{
AnnaBridge 171:3a7713b1edbc 485 */
AnnaBridge 171:3a7713b1edbc 486 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2 \
AnnaBridge 171:3a7713b1edbc 487 (ADC_SMPR3_SMP9_2 | ADC_SMPR3_SMP8_2 | ADC_SMPR3_SMP7_2 | ADC_SMPR3_SMP6_2 | \
AnnaBridge 171:3a7713b1edbc 488 ADC_SMPR3_SMP5_2 | ADC_SMPR3_SMP4_2 | ADC_SMPR3_SMP3_2 | ADC_SMPR3_SMP2_2 | \
AnnaBridge 171:3a7713b1edbc 489 ADC_SMPR3_SMP1_2 | ADC_SMPR3_SMP0_2)
AnnaBridge 171:3a7713b1edbc 490 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \
AnnaBridge 171:3a7713b1edbc 491 (ADC_SMPR2_SMP19_2 | ADC_SMPR2_SMP18_2 | ADC_SMPR2_SMP17_2 | ADC_SMPR2_SMP16_2 | \
AnnaBridge 171:3a7713b1edbc 492 ADC_SMPR2_SMP15_2 | ADC_SMPR2_SMP14_2 | ADC_SMPR2_SMP13_2 | ADC_SMPR2_SMP12_2 | \
AnnaBridge 171:3a7713b1edbc 493 ADC_SMPR2_SMP11_2 | ADC_SMPR2_SMP10_2)
AnnaBridge 171:3a7713b1edbc 494 #if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
AnnaBridge 171:3a7713b1edbc 495 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \
AnnaBridge 171:3a7713b1edbc 496 (ADC_SMPR1_SMP26_2 | ADC_SMPR1_SMP25_2 | ADC_SMPR1_SMP24_2 | ADC_SMPR1_SMP23_2 | \
AnnaBridge 171:3a7713b1edbc 497 ADC_SMPR1_SMP22_2 | ADC_SMPR1_SMP21_2 | ADC_SMPR1_SMP20_2)
AnnaBridge 171:3a7713b1edbc 498 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */
AnnaBridge 171:3a7713b1edbc 499 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
AnnaBridge 171:3a7713b1edbc 500 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \
AnnaBridge 171:3a7713b1edbc 501 (ADC_SMPR1_SMP29_2 | ADC_SMPR1_SMP28_2 | ADC_SMPR1_SMP27_2 | ADC_SMPR1_SMP26_2 | \
AnnaBridge 171:3a7713b1edbc 502 ADC_SMPR1_SMP25_2 | ADC_SMPR1_SMP24_2 | ADC_SMPR1_SMP23_2 | ADC_SMPR1_SMP22_2 | \
AnnaBridge 171:3a7713b1edbc 503 ADC_SMPR1_SMP21_2 | ADC_SMPR1_SMP20_2)
AnnaBridge 171:3a7713b1edbc 504 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT2 \
AnnaBridge 171:3a7713b1edbc 505 (ADC_SMPR0_SMP31_2 | ADC_SMPR0_SMP30_2 )
AnnaBridge 171:3a7713b1edbc 506 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
AnnaBridge 171:3a7713b1edbc 507
AnnaBridge 171:3a7713b1edbc 508 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT1 \
AnnaBridge 171:3a7713b1edbc 509 (ADC_SMPR3_SMP9_1 | ADC_SMPR3_SMP8_1 | ADC_SMPR3_SMP7_1 | ADC_SMPR3_SMP6_1 | \
AnnaBridge 171:3a7713b1edbc 510 ADC_SMPR3_SMP5_1 | ADC_SMPR3_SMP4_1 | ADC_SMPR3_SMP3_1 | ADC_SMPR3_SMP2_1 | \
AnnaBridge 171:3a7713b1edbc 511 ADC_SMPR3_SMP1_1 | ADC_SMPR3_SMP0_1)
AnnaBridge 171:3a7713b1edbc 512 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \
AnnaBridge 171:3a7713b1edbc 513 (ADC_SMPR2_SMP19_1 | ADC_SMPR2_SMP18_1 | ADC_SMPR2_SMP17_1 | ADC_SMPR2_SMP16_1 | \
AnnaBridge 171:3a7713b1edbc 514 ADC_SMPR2_SMP15_1 | ADC_SMPR2_SMP14_1 | ADC_SMPR2_SMP13_1 | ADC_SMPR2_SMP12_1 | \
AnnaBridge 171:3a7713b1edbc 515 ADC_SMPR2_SMP11_1 | ADC_SMPR2_SMP10_1)
AnnaBridge 171:3a7713b1edbc 516 #if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
AnnaBridge 171:3a7713b1edbc 517 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \
AnnaBridge 171:3a7713b1edbc 518 (ADC_SMPR1_SMP26_1 | ADC_SMPR1_SMP25_1 | ADC_SMPR1_SMP24_1 | ADC_SMPR1_SMP23_1 | \
AnnaBridge 171:3a7713b1edbc 519 ADC_SMPR1_SMP22_1 | ADC_SMPR1_SMP21_1 | ADC_SMPR1_SMP20_1)
AnnaBridge 171:3a7713b1edbc 520 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */
AnnaBridge 171:3a7713b1edbc 521 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
AnnaBridge 171:3a7713b1edbc 522 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \
AnnaBridge 171:3a7713b1edbc 523 (ADC_SMPR1_SMP29_1 | ADC_SMPR1_SMP28_1 | ADC_SMPR1_SMP27_1 | ADC_SMPR1_SMP26_1 | \
AnnaBridge 171:3a7713b1edbc 524 ADC_SMPR1_SMP25_1 | ADC_SMPR1_SMP24_1 | ADC_SMPR1_SMP23_1 | ADC_SMPR1_SMP22_1 | \
AnnaBridge 171:3a7713b1edbc 525 ADC_SMPR1_SMP21_1 | ADC_SMPR1_SMP20_1)
AnnaBridge 171:3a7713b1edbc 526 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT1 \
AnnaBridge 171:3a7713b1edbc 527 (ADC_SMPR0_SMP31_1 | ADC_SMPR0_SMP30_1 )
AnnaBridge 171:3a7713b1edbc 528 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
AnnaBridge 171:3a7713b1edbc 529
AnnaBridge 171:3a7713b1edbc 530 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT0 \
AnnaBridge 171:3a7713b1edbc 531 (ADC_SMPR3_SMP9_0 | ADC_SMPR3_SMP8_0 | ADC_SMPR3_SMP7_0 | ADC_SMPR3_SMP6_0 | \
AnnaBridge 171:3a7713b1edbc 532 ADC_SMPR3_SMP5_0 | ADC_SMPR3_SMP4_0 | ADC_SMPR3_SMP3_0 | ADC_SMPR3_SMP2_0 | \
AnnaBridge 171:3a7713b1edbc 533 ADC_SMPR3_SMP1_0 | ADC_SMPR3_SMP0_0)
AnnaBridge 171:3a7713b1edbc 534 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \
AnnaBridge 171:3a7713b1edbc 535 (ADC_SMPR2_SMP19_0 | ADC_SMPR2_SMP18_0 | ADC_SMPR2_SMP17_0 | ADC_SMPR2_SMP16_0 | \
AnnaBridge 171:3a7713b1edbc 536 ADC_SMPR2_SMP15_0 | ADC_SMPR2_SMP14_0 | ADC_SMPR2_SMP13_0 | ADC_SMPR2_SMP12_0 | \
AnnaBridge 171:3a7713b1edbc 537 ADC_SMPR2_SMP11_0 | ADC_SMPR2_SMP10_0)
AnnaBridge 171:3a7713b1edbc 538 #if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
AnnaBridge 171:3a7713b1edbc 539 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \
AnnaBridge 171:3a7713b1edbc 540 (ADC_SMPR1_SMP26_0 | ADC_SMPR1_SMP25_0 | ADC_SMPR1_SMP24_0 | ADC_SMPR1_SMP23_0 | \
AnnaBridge 171:3a7713b1edbc 541 ADC_SMPR1_SMP22_0 | ADC_SMPR1_SMP21_0 | ADC_SMPR1_SMP20_0)
AnnaBridge 171:3a7713b1edbc 542 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */
AnnaBridge 171:3a7713b1edbc 543 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
AnnaBridge 171:3a7713b1edbc 544 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \
AnnaBridge 171:3a7713b1edbc 545 (ADC_SMPR1_SMP29_0 | ADC_SMPR1_SMP28_0 | ADC_SMPR1_SMP27_0 | ADC_SMPR1_SMP26_0 | \
AnnaBridge 171:3a7713b1edbc 546 ADC_SMPR1_SMP25_0 | ADC_SMPR1_SMP24_0 | ADC_SMPR1_SMP23_0 | ADC_SMPR1_SMP22_0 | \
AnnaBridge 171:3a7713b1edbc 547 ADC_SMPR1_SMP21_0 | ADC_SMPR1_SMP20_0)
AnnaBridge 171:3a7713b1edbc 548 #define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT0 \
AnnaBridge 171:3a7713b1edbc 549 (ADC_SMPR0_SMP31_0 | ADC_SMPR0_SMP30_0 )
AnnaBridge 171:3a7713b1edbc 550 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
AnnaBridge 171:3a7713b1edbc 551 /**
AnnaBridge 171:3a7713b1edbc 552 * @}
AnnaBridge 171:3a7713b1edbc 553 */
AnnaBridge 171:3a7713b1edbc 554
AnnaBridge 171:3a7713b1edbc 555 /** @defgroup ADC_regular_rank ADC rank into regular group
AnnaBridge 171:3a7713b1edbc 556 * @{
AnnaBridge 171:3a7713b1edbc 557 */
AnnaBridge 171:3a7713b1edbc 558 #define ADC_REGULAR_RANK_1 (0x00000001U)
AnnaBridge 171:3a7713b1edbc 559 #define ADC_REGULAR_RANK_2 (0x00000002U)
AnnaBridge 171:3a7713b1edbc 560 #define ADC_REGULAR_RANK_3 (0x00000003U)
AnnaBridge 171:3a7713b1edbc 561 #define ADC_REGULAR_RANK_4 (0x00000004U)
AnnaBridge 171:3a7713b1edbc 562 #define ADC_REGULAR_RANK_5 (0x00000005U)
AnnaBridge 171:3a7713b1edbc 563 #define ADC_REGULAR_RANK_6 (0x00000006U)
AnnaBridge 171:3a7713b1edbc 564 #define ADC_REGULAR_RANK_7 (0x00000007U)
AnnaBridge 171:3a7713b1edbc 565 #define ADC_REGULAR_RANK_8 (0x00000008U)
AnnaBridge 171:3a7713b1edbc 566 #define ADC_REGULAR_RANK_9 (0x00000009U)
AnnaBridge 171:3a7713b1edbc 567 #define ADC_REGULAR_RANK_10 (0x0000000AU)
AnnaBridge 171:3a7713b1edbc 568 #define ADC_REGULAR_RANK_11 (0x0000000BU)
AnnaBridge 171:3a7713b1edbc 569 #define ADC_REGULAR_RANK_12 (0x0000000CU)
AnnaBridge 171:3a7713b1edbc 570 #define ADC_REGULAR_RANK_13 (0x0000000DU)
AnnaBridge 171:3a7713b1edbc 571 #define ADC_REGULAR_RANK_14 (0x0000000EU)
AnnaBridge 171:3a7713b1edbc 572 #define ADC_REGULAR_RANK_15 (0x0000000FU)
AnnaBridge 171:3a7713b1edbc 573 #define ADC_REGULAR_RANK_16 (0x00000010U)
AnnaBridge 171:3a7713b1edbc 574 #define ADC_REGULAR_RANK_17 (0x00000011U)
AnnaBridge 171:3a7713b1edbc 575 #define ADC_REGULAR_RANK_18 (0x00000012U)
AnnaBridge 171:3a7713b1edbc 576 #define ADC_REGULAR_RANK_19 (0x00000013U)
AnnaBridge 171:3a7713b1edbc 577 #define ADC_REGULAR_RANK_20 (0x00000014U)
AnnaBridge 171:3a7713b1edbc 578 #define ADC_REGULAR_RANK_21 (0x00000015U)
AnnaBridge 171:3a7713b1edbc 579 #define ADC_REGULAR_RANK_22 (0x00000016U)
AnnaBridge 171:3a7713b1edbc 580 #define ADC_REGULAR_RANK_23 (0x00000017U)
AnnaBridge 171:3a7713b1edbc 581 #define ADC_REGULAR_RANK_24 (0x00000018U)
AnnaBridge 171:3a7713b1edbc 582 #define ADC_REGULAR_RANK_25 (0x00000019U)
AnnaBridge 171:3a7713b1edbc 583 #define ADC_REGULAR_RANK_26 (0x0000001AU)
AnnaBridge 171:3a7713b1edbc 584 #define ADC_REGULAR_RANK_27 (0x0000001BU)
AnnaBridge 171:3a7713b1edbc 585 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
AnnaBridge 171:3a7713b1edbc 586 #define ADC_REGULAR_RANK_28 (0x0000001CU)
AnnaBridge 171:3a7713b1edbc 587 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
AnnaBridge 171:3a7713b1edbc 588 /**
AnnaBridge 171:3a7713b1edbc 589 * @}
AnnaBridge 171:3a7713b1edbc 590 */
AnnaBridge 171:3a7713b1edbc 591
AnnaBridge 171:3a7713b1edbc 592 /** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode
AnnaBridge 171:3a7713b1edbc 593 * @{
AnnaBridge 171:3a7713b1edbc 594 */
AnnaBridge 171:3a7713b1edbc 595 #define ADC_ANALOGWATCHDOG_NONE (0x00000000U)
AnnaBridge 171:3a7713b1edbc 596 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
AnnaBridge 171:3a7713b1edbc 597 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
AnnaBridge 171:3a7713b1edbc 598 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
AnnaBridge 171:3a7713b1edbc 599 #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CR1_AWDEN)
AnnaBridge 171:3a7713b1edbc 600 #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CR1_JAWDEN)
AnnaBridge 171:3a7713b1edbc 601 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
AnnaBridge 171:3a7713b1edbc 602 /**
AnnaBridge 171:3a7713b1edbc 603 * @}
AnnaBridge 171:3a7713b1edbc 604 */
AnnaBridge 171:3a7713b1edbc 605
AnnaBridge 171:3a7713b1edbc 606 /** @defgroup ADC_conversion_group ADC conversion group
AnnaBridge 171:3a7713b1edbc 607 * @{
AnnaBridge 171:3a7713b1edbc 608 */
AnnaBridge 171:3a7713b1edbc 609 #define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC))
AnnaBridge 171:3a7713b1edbc 610 #define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC))
AnnaBridge 171:3a7713b1edbc 611 #define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC))
AnnaBridge 171:3a7713b1edbc 612 /**
AnnaBridge 171:3a7713b1edbc 613 * @}
AnnaBridge 171:3a7713b1edbc 614 */
AnnaBridge 171:3a7713b1edbc 615
AnnaBridge 171:3a7713b1edbc 616 /** @defgroup ADC_Event_type ADC Event type
AnnaBridge 171:3a7713b1edbc 617 * @{
AnnaBridge 171:3a7713b1edbc 618 */
AnnaBridge 171:3a7713b1edbc 619 #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /*!< ADC Analog watchdog event */
AnnaBridge 171:3a7713b1edbc 620 #define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /*!< ADC overrun event */
AnnaBridge 171:3a7713b1edbc 621 /**
AnnaBridge 171:3a7713b1edbc 622 * @}
AnnaBridge 171:3a7713b1edbc 623 */
AnnaBridge 171:3a7713b1edbc 624
AnnaBridge 171:3a7713b1edbc 625 /** @defgroup ADC_interrupts_definition ADC interrupts definition
AnnaBridge 171:3a7713b1edbc 626 * @{
AnnaBridge 171:3a7713b1edbc 627 */
AnnaBridge 171:3a7713b1edbc 628 #define ADC_IT_EOC ADC_CR1_EOCIE /*!< ADC End of Regular Conversion interrupt source */
AnnaBridge 171:3a7713b1edbc 629 #define ADC_IT_JEOC ADC_CR1_JEOCIE /*!< ADC End of Injected Conversion interrupt source */
AnnaBridge 171:3a7713b1edbc 630 #define ADC_IT_AWD ADC_CR1_AWDIE /*!< ADC Analog watchdog interrupt source */
AnnaBridge 171:3a7713b1edbc 631 #define ADC_IT_OVR ADC_CR1_OVRIE /*!< ADC overrun interrupt source */
AnnaBridge 171:3a7713b1edbc 632 /**
AnnaBridge 171:3a7713b1edbc 633 * @}
AnnaBridge 171:3a7713b1edbc 634 */
AnnaBridge 171:3a7713b1edbc 635
AnnaBridge 171:3a7713b1edbc 636 /** @defgroup ADC_flags_definition ADC flags definition
AnnaBridge 171:3a7713b1edbc 637 * @{
AnnaBridge 171:3a7713b1edbc 638 */
AnnaBridge 171:3a7713b1edbc 639 #define ADC_FLAG_AWD ADC_SR_AWD /*!< ADC Analog watchdog flag */
AnnaBridge 171:3a7713b1edbc 640 #define ADC_FLAG_EOC ADC_SR_EOC /*!< ADC End of Regular conversion flag */
AnnaBridge 171:3a7713b1edbc 641 #define ADC_FLAG_JEOC ADC_SR_JEOC /*!< ADC End of Injected conversion flag */
AnnaBridge 171:3a7713b1edbc 642 #define ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC Injected group start flag */
AnnaBridge 171:3a7713b1edbc 643 #define ADC_FLAG_STRT ADC_SR_STRT /*!< ADC Regular group start flag */
AnnaBridge 171:3a7713b1edbc 644 #define ADC_FLAG_OVR ADC_SR_OVR /*!< ADC overrun flag */
AnnaBridge 171:3a7713b1edbc 645 #define ADC_FLAG_ADONS ADC_SR_ADONS /*!< ADC ready status flag */
AnnaBridge 171:3a7713b1edbc 646 #define ADC_FLAG_RCNR ADC_SR_RCNR /*!< ADC Regular group ready status flag */
AnnaBridge 171:3a7713b1edbc 647 #define ADC_FLAG_JCNR ADC_SR_JCNR /*!< ADC Injected group ready status flag */
AnnaBridge 171:3a7713b1edbc 648 /**
AnnaBridge 171:3a7713b1edbc 649 * @}
AnnaBridge 171:3a7713b1edbc 650 */
AnnaBridge 171:3a7713b1edbc 651
AnnaBridge 171:3a7713b1edbc 652 /**
AnnaBridge 171:3a7713b1edbc 653 * @}
AnnaBridge 171:3a7713b1edbc 654 */
AnnaBridge 171:3a7713b1edbc 655
AnnaBridge 171:3a7713b1edbc 656
AnnaBridge 171:3a7713b1edbc 657 /* Private constants ---------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 658
AnnaBridge 171:3a7713b1edbc 659 /** @addtogroup ADC_Private_Constants ADC Private Constants
AnnaBridge 171:3a7713b1edbc 660 * @{
AnnaBridge 171:3a7713b1edbc 661 */
AnnaBridge 171:3a7713b1edbc 662
AnnaBridge 171:3a7713b1edbc 663 /* List of external triggers of regular group for ADC1: */
AnnaBridge 171:3a7713b1edbc 664 /* (used internally by HAL driver. To not use into HAL structure parameters) */
AnnaBridge 171:3a7713b1edbc 665
AnnaBridge 171:3a7713b1edbc 666 /* External triggers of regular group for ADC1 */
AnnaBridge 171:3a7713b1edbc 667 #define ADC_EXTERNALTRIG_T9_CC2 (0x00000000U)
AnnaBridge 171:3a7713b1edbc 668 #define ADC_EXTERNALTRIG_T9_TRGO ((uint32_t)( ADC_CR2_EXTSEL_0))
AnnaBridge 171:3a7713b1edbc 669 #define ADC_EXTERNALTRIG_T2_CC3 ((uint32_t)( ADC_CR2_EXTSEL_1 ))
AnnaBridge 171:3a7713b1edbc 670 #define ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)( ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
AnnaBridge 171:3a7713b1edbc 671 #define ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)( ADC_CR2_EXTSEL_2 ))
AnnaBridge 171:3a7713b1edbc 672 #define ADC_EXTERNALTRIG_T4_CC4 ((uint32_t)( ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
AnnaBridge 171:3a7713b1edbc 673 #define ADC_EXTERNALTRIG_T2_TRGO ((uint32_t)( ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 ))
AnnaBridge 171:3a7713b1edbc 674 #define ADC_EXTERNALTRIG_T3_CC1 ((uint32_t)( ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
AnnaBridge 171:3a7713b1edbc 675 #define ADC_EXTERNALTRIG_T3_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 ))
AnnaBridge 171:3a7713b1edbc 676 #define ADC_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))
AnnaBridge 171:3a7713b1edbc 677 #define ADC_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 ))
AnnaBridge 171:3a7713b1edbc 678 #define ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
AnnaBridge 171:3a7713b1edbc 679
AnnaBridge 171:3a7713b1edbc 680 /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
AnnaBridge 171:3a7713b1edbc 681 #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD | \
AnnaBridge 171:3a7713b1edbc 682 ADC_FLAG_OVR)
AnnaBridge 171:3a7713b1edbc 683
AnnaBridge 171:3a7713b1edbc 684 /**
AnnaBridge 171:3a7713b1edbc 685 * @}
AnnaBridge 171:3a7713b1edbc 686 */
AnnaBridge 171:3a7713b1edbc 687
AnnaBridge 171:3a7713b1edbc 688
AnnaBridge 171:3a7713b1edbc 689 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 690
AnnaBridge 171:3a7713b1edbc 691 /** @defgroup ADC_Exported_Macros ADC Exported Macros
AnnaBridge 171:3a7713b1edbc 692 * @{
AnnaBridge 171:3a7713b1edbc 693 */
AnnaBridge 171:3a7713b1edbc 694 /* Macro for internal HAL driver usage, and possibly can be used into code of */
AnnaBridge 171:3a7713b1edbc 695 /* final user. */
AnnaBridge 171:3a7713b1edbc 696
AnnaBridge 171:3a7713b1edbc 697 /**
AnnaBridge 171:3a7713b1edbc 698 * @brief Enable the ADC peripheral
AnnaBridge 171:3a7713b1edbc 699 * @param __HANDLE__: ADC handle
AnnaBridge 171:3a7713b1edbc 700 * @retval None
AnnaBridge 171:3a7713b1edbc 701 */
AnnaBridge 171:3a7713b1edbc 702 #define __HAL_ADC_ENABLE(__HANDLE__) \
AnnaBridge 171:3a7713b1edbc 703 (__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON
AnnaBridge 171:3a7713b1edbc 704
AnnaBridge 171:3a7713b1edbc 705 /**
AnnaBridge 171:3a7713b1edbc 706 * @brief Disable the ADC peripheral
AnnaBridge 171:3a7713b1edbc 707 * @param __HANDLE__: ADC handle
AnnaBridge 171:3a7713b1edbc 708 * @retval None
AnnaBridge 171:3a7713b1edbc 709 */
AnnaBridge 171:3a7713b1edbc 710 #define __HAL_ADC_DISABLE(__HANDLE__) \
AnnaBridge 171:3a7713b1edbc 711 (__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON
AnnaBridge 171:3a7713b1edbc 712
AnnaBridge 171:3a7713b1edbc 713 /**
AnnaBridge 171:3a7713b1edbc 714 * @brief Enable the ADC end of conversion interrupt.
AnnaBridge 171:3a7713b1edbc 715 * @param __HANDLE__: ADC handle
AnnaBridge 171:3a7713b1edbc 716 * @param __INTERRUPT__: ADC Interrupt
AnnaBridge 171:3a7713b1edbc 717 * This parameter can be any combination of the following values:
AnnaBridge 171:3a7713b1edbc 718 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
AnnaBridge 171:3a7713b1edbc 719 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
AnnaBridge 171:3a7713b1edbc 720 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
AnnaBridge 171:3a7713b1edbc 721 * @arg ADC_IT_OVR: ADC overrun interrupt source
AnnaBridge 171:3a7713b1edbc 722 * @retval None
AnnaBridge 171:3a7713b1edbc 723 */
AnnaBridge 171:3a7713b1edbc 724 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
AnnaBridge 171:3a7713b1edbc 725 (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
AnnaBridge 171:3a7713b1edbc 726
AnnaBridge 171:3a7713b1edbc 727 /**
AnnaBridge 171:3a7713b1edbc 728 * @brief Disable the ADC end of conversion interrupt.
AnnaBridge 171:3a7713b1edbc 729 * @param __HANDLE__: ADC handle
AnnaBridge 171:3a7713b1edbc 730 * @param __INTERRUPT__: ADC Interrupt
AnnaBridge 171:3a7713b1edbc 731 * This parameter can be any combination of the following values:
AnnaBridge 171:3a7713b1edbc 732 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
AnnaBridge 171:3a7713b1edbc 733 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
AnnaBridge 171:3a7713b1edbc 734 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
AnnaBridge 171:3a7713b1edbc 735 * @arg ADC_IT_OVR: ADC overrun interrupt source
AnnaBridge 171:3a7713b1edbc 736 * @retval None
AnnaBridge 171:3a7713b1edbc 737 */
AnnaBridge 171:3a7713b1edbc 738 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
AnnaBridge 171:3a7713b1edbc 739 (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
AnnaBridge 171:3a7713b1edbc 740
AnnaBridge 171:3a7713b1edbc 741 /** @brief Checks if the specified ADC interrupt source is enabled or disabled.
AnnaBridge 171:3a7713b1edbc 742 * @param __HANDLE__: ADC handle
AnnaBridge 171:3a7713b1edbc 743 * @param __INTERRUPT__: ADC interrupt source to check
AnnaBridge 171:3a7713b1edbc 744 * This parameter can be any combination of the following values:
AnnaBridge 171:3a7713b1edbc 745 * @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
AnnaBridge 171:3a7713b1edbc 746 * @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
AnnaBridge 171:3a7713b1edbc 747 * @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
AnnaBridge 171:3a7713b1edbc 748 * @arg ADC_IT_OVR: ADC overrun interrupt source
AnnaBridge 171:3a7713b1edbc 749 * @retval State of interruption (SET or RESET)
AnnaBridge 171:3a7713b1edbc 750 */
AnnaBridge 171:3a7713b1edbc 751 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
AnnaBridge 171:3a7713b1edbc 752 (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
AnnaBridge 171:3a7713b1edbc 753
AnnaBridge 171:3a7713b1edbc 754 /**
AnnaBridge 171:3a7713b1edbc 755 * @brief Get the selected ADC's flag status.
AnnaBridge 171:3a7713b1edbc 756 * @param __HANDLE__: ADC handle
AnnaBridge 171:3a7713b1edbc 757 * @param __FLAG__: ADC flag
AnnaBridge 171:3a7713b1edbc 758 * This parameter can be any combination of the following values:
AnnaBridge 171:3a7713b1edbc 759 * @arg ADC_FLAG_STRT: ADC Regular group start flag
AnnaBridge 171:3a7713b1edbc 760 * @arg ADC_FLAG_JSTRT: ADC Injected group start flag
AnnaBridge 171:3a7713b1edbc 761 * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
AnnaBridge 171:3a7713b1edbc 762 * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
AnnaBridge 171:3a7713b1edbc 763 * @arg ADC_FLAG_AWD: ADC Analog watchdog flag
AnnaBridge 171:3a7713b1edbc 764 * @arg ADC_FLAG_OVR: ADC overrun flag
AnnaBridge 171:3a7713b1edbc 765 * @arg ADC_FLAG_ADONS: ADC ready status flag
AnnaBridge 171:3a7713b1edbc 766 * @arg ADC_FLAG_RCNR: ADC Regular group ready status flag
AnnaBridge 171:3a7713b1edbc 767 * @arg ADC_FLAG_JCNR: ADC Injected group ready status flag
AnnaBridge 171:3a7713b1edbc 768 * @retval None
AnnaBridge 171:3a7713b1edbc 769 */
AnnaBridge 171:3a7713b1edbc 770 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
AnnaBridge 171:3a7713b1edbc 771 ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
AnnaBridge 171:3a7713b1edbc 772
AnnaBridge 171:3a7713b1edbc 773 /**
AnnaBridge 171:3a7713b1edbc 774 * @brief Clear the ADC's pending flags
AnnaBridge 171:3a7713b1edbc 775 * @param __HANDLE__: ADC handle
AnnaBridge 171:3a7713b1edbc 776 * @param __FLAG__: ADC flag
AnnaBridge 171:3a7713b1edbc 777 * @arg ADC_FLAG_STRT: ADC Regular group start flag
AnnaBridge 171:3a7713b1edbc 778 * @arg ADC_FLAG_JSTRT: ADC Injected group start flag
AnnaBridge 171:3a7713b1edbc 779 * @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
AnnaBridge 171:3a7713b1edbc 780 * @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
AnnaBridge 171:3a7713b1edbc 781 * @arg ADC_FLAG_AWD: ADC Analog watchdog flag
AnnaBridge 171:3a7713b1edbc 782 * @arg ADC_FLAG_OVR: ADC overrun flag
AnnaBridge 171:3a7713b1edbc 783 * @arg ADC_FLAG_ADONS: ADC ready status flag
AnnaBridge 171:3a7713b1edbc 784 * @arg ADC_FLAG_RCNR: ADC Regular group ready status flag
AnnaBridge 171:3a7713b1edbc 785 * @arg ADC_FLAG_JCNR: ADC Injected group ready status flag
AnnaBridge 171:3a7713b1edbc 786 * @retval None
AnnaBridge 171:3a7713b1edbc 787 */
AnnaBridge 171:3a7713b1edbc 788 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
AnnaBridge 171:3a7713b1edbc 789 (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
AnnaBridge 171:3a7713b1edbc 790
AnnaBridge 171:3a7713b1edbc 791 /** @brief Reset ADC handle state
AnnaBridge 171:3a7713b1edbc 792 * @param __HANDLE__: ADC handle
AnnaBridge 171:3a7713b1edbc 793 * @retval None
AnnaBridge 171:3a7713b1edbc 794 */
AnnaBridge 171:3a7713b1edbc 795 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
AnnaBridge 171:3a7713b1edbc 796 ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
AnnaBridge 171:3a7713b1edbc 797
AnnaBridge 171:3a7713b1edbc 798 /**
AnnaBridge 171:3a7713b1edbc 799 * @}
AnnaBridge 171:3a7713b1edbc 800 */
AnnaBridge 171:3a7713b1edbc 801
AnnaBridge 171:3a7713b1edbc 802 /* Private macro ------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 803
AnnaBridge 171:3a7713b1edbc 804 /** @defgroup ADC_Private_Macros ADC Private Macros
AnnaBridge 171:3a7713b1edbc 805 * @{
AnnaBridge 171:3a7713b1edbc 806 */
AnnaBridge 171:3a7713b1edbc 807 /* Macro reserved for internal HAL driver usage, not intended to be used in */
AnnaBridge 171:3a7713b1edbc 808 /* code of final user. */
AnnaBridge 171:3a7713b1edbc 809
AnnaBridge 171:3a7713b1edbc 810 /**
AnnaBridge 171:3a7713b1edbc 811 * @brief Verification of ADC state: enabled or disabled
AnnaBridge 171:3a7713b1edbc 812 * @param __HANDLE__: ADC handle
AnnaBridge 171:3a7713b1edbc 813 * @retval SET (ADC enabled) or RESET (ADC disabled)
AnnaBridge 171:3a7713b1edbc 814 */
AnnaBridge 171:3a7713b1edbc 815 #define ADC_IS_ENABLE(__HANDLE__) \
AnnaBridge 171:3a7713b1edbc 816 ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \
AnnaBridge 171:3a7713b1edbc 817 ) ? SET : RESET)
AnnaBridge 171:3a7713b1edbc 818
AnnaBridge 171:3a7713b1edbc 819 /**
AnnaBridge 171:3a7713b1edbc 820 * @brief Test if conversion trigger of regular group is software start
AnnaBridge 171:3a7713b1edbc 821 * or external trigger.
AnnaBridge 171:3a7713b1edbc 822 * @param __HANDLE__: ADC handle
AnnaBridge 171:3a7713b1edbc 823 * @retval SET (software start) or RESET (external trigger)
AnnaBridge 171:3a7713b1edbc 824 */
AnnaBridge 171:3a7713b1edbc 825 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
AnnaBridge 171:3a7713b1edbc 826 (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
AnnaBridge 171:3a7713b1edbc 827
AnnaBridge 171:3a7713b1edbc 828 /**
AnnaBridge 171:3a7713b1edbc 829 * @brief Test if conversion trigger of injected group is software start
AnnaBridge 171:3a7713b1edbc 830 * or external trigger.
AnnaBridge 171:3a7713b1edbc 831 * @param __HANDLE__: ADC handle
AnnaBridge 171:3a7713b1edbc 832 * @retval SET (software start) or RESET (external trigger)
AnnaBridge 171:3a7713b1edbc 833 */
AnnaBridge 171:3a7713b1edbc 834 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
AnnaBridge 171:3a7713b1edbc 835 (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
AnnaBridge 171:3a7713b1edbc 836
AnnaBridge 171:3a7713b1edbc 837 /**
AnnaBridge 171:3a7713b1edbc 838 * @brief Simultaneously clears and sets specific bits of the handle State
AnnaBridge 171:3a7713b1edbc 839 * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
AnnaBridge 171:3a7713b1edbc 840 * the first parameter is the ADC handle State, the second parameter is the
AnnaBridge 171:3a7713b1edbc 841 * bit field to clear, the third and last parameter is the bit field to set.
AnnaBridge 171:3a7713b1edbc 842 * @retval None
AnnaBridge 171:3a7713b1edbc 843 */
AnnaBridge 171:3a7713b1edbc 844 #define ADC_STATE_CLR_SET MODIFY_REG
AnnaBridge 171:3a7713b1edbc 845
AnnaBridge 171:3a7713b1edbc 846 /**
AnnaBridge 171:3a7713b1edbc 847 * @brief Clear ADC error code (set it to error code: "no error")
AnnaBridge 171:3a7713b1edbc 848 * @param __HANDLE__: ADC handle
AnnaBridge 171:3a7713b1edbc 849 * @retval None
AnnaBridge 171:3a7713b1edbc 850 */
AnnaBridge 171:3a7713b1edbc 851 #define ADC_CLEAR_ERRORCODE(__HANDLE__) \
AnnaBridge 171:3a7713b1edbc 852 ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
AnnaBridge 171:3a7713b1edbc 853
AnnaBridge 171:3a7713b1edbc 854 /**
AnnaBridge 171:3a7713b1edbc 855 * @brief Set ADC number of ranks into regular channel sequence length.
AnnaBridge 171:3a7713b1edbc 856 * @param _NbrOfConversion_: Regular channel sequence length
AnnaBridge 171:3a7713b1edbc 857 * @retval None
AnnaBridge 171:3a7713b1edbc 858 */
AnnaBridge 171:3a7713b1edbc 859 #define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \
AnnaBridge 171:3a7713b1edbc 860 (((_NbrOfConversion_) - (uint8_t)1) << POSITION_VAL(ADC_SQR1_L))
AnnaBridge 171:3a7713b1edbc 861
AnnaBridge 171:3a7713b1edbc 862 /**
AnnaBridge 171:3a7713b1edbc 863 * @brief Set the ADC's sample time for channel numbers between 10 and 18.
AnnaBridge 171:3a7713b1edbc 864 * @param _SAMPLETIME_: Sample time parameter.
AnnaBridge 171:3a7713b1edbc 865 * @param _CHANNELNB_: Channel number.
AnnaBridge 171:3a7713b1edbc 866 * @retval None
AnnaBridge 171:3a7713b1edbc 867 */
AnnaBridge 171:3a7713b1edbc 868 #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \
AnnaBridge 171:3a7713b1edbc 869 ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 10)))
AnnaBridge 171:3a7713b1edbc 870
AnnaBridge 171:3a7713b1edbc 871 /**
AnnaBridge 171:3a7713b1edbc 872 * @brief Set the ADC's sample time for channel numbers between 0 and 9.
AnnaBridge 171:3a7713b1edbc 873 * @param _SAMPLETIME_: Sample time parameter.
AnnaBridge 171:3a7713b1edbc 874 * @param _CHANNELNB_: Channel number.
AnnaBridge 171:3a7713b1edbc 875 * @retval None
AnnaBridge 171:3a7713b1edbc 876 */
AnnaBridge 171:3a7713b1edbc 877 #define ADC_SMPR3(_SAMPLETIME_, _CHANNELNB_) \
AnnaBridge 171:3a7713b1edbc 878 ((_SAMPLETIME_) << (3 * (_CHANNELNB_)))
AnnaBridge 171:3a7713b1edbc 879
AnnaBridge 171:3a7713b1edbc 880 /**
AnnaBridge 171:3a7713b1edbc 881 * @brief Set the selected regular channel rank for rank between 1 and 6.
AnnaBridge 171:3a7713b1edbc 882 * @param _CHANNELNB_: Channel number.
AnnaBridge 171:3a7713b1edbc 883 * @param _RANKNB_: Rank number.
AnnaBridge 171:3a7713b1edbc 884 * @retval None
AnnaBridge 171:3a7713b1edbc 885 */
AnnaBridge 171:3a7713b1edbc 886 #define ADC_SQR5_RK(_CHANNELNB_, _RANKNB_) \
AnnaBridge 171:3a7713b1edbc 887 ((_CHANNELNB_) << (5 * ((_RANKNB_) - 1)))
AnnaBridge 171:3a7713b1edbc 888
AnnaBridge 171:3a7713b1edbc 889 /**
AnnaBridge 171:3a7713b1edbc 890 * @brief Set the selected regular channel rank for rank between 7 and 12.
AnnaBridge 171:3a7713b1edbc 891 * @param _CHANNELNB_: Channel number.
AnnaBridge 171:3a7713b1edbc 892 * @param _RANKNB_: Rank number.
AnnaBridge 171:3a7713b1edbc 893 * @retval None
AnnaBridge 171:3a7713b1edbc 894 */
AnnaBridge 171:3a7713b1edbc 895 #define ADC_SQR4_RK(_CHANNELNB_, _RANKNB_) \
AnnaBridge 171:3a7713b1edbc 896 ((_CHANNELNB_) << (5 * ((_RANKNB_) - 7)))
AnnaBridge 171:3a7713b1edbc 897
AnnaBridge 171:3a7713b1edbc 898 /**
AnnaBridge 171:3a7713b1edbc 899 * @brief Set the selected regular channel rank for rank between 13 and 18.
AnnaBridge 171:3a7713b1edbc 900 * @param _CHANNELNB_: Channel number.
AnnaBridge 171:3a7713b1edbc 901 * @param _RANKNB_: Rank number.
AnnaBridge 171:3a7713b1edbc 902 * @retval None
AnnaBridge 171:3a7713b1edbc 903 */
AnnaBridge 171:3a7713b1edbc 904 #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \
AnnaBridge 171:3a7713b1edbc 905 ((_CHANNELNB_) << (5 * ((_RANKNB_) - 13)))
AnnaBridge 171:3a7713b1edbc 906
AnnaBridge 171:3a7713b1edbc 907 /**
AnnaBridge 171:3a7713b1edbc 908 * @brief Set the selected regular channel rank for rank between 19 and 24.
AnnaBridge 171:3a7713b1edbc 909 * @param _CHANNELNB_: Channel number.
AnnaBridge 171:3a7713b1edbc 910 * @param _RANKNB_: Rank number.
AnnaBridge 171:3a7713b1edbc 911 * @retval None
AnnaBridge 171:3a7713b1edbc 912 */
AnnaBridge 171:3a7713b1edbc 913 #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \
AnnaBridge 171:3a7713b1edbc 914 ((_CHANNELNB_) << (5 * ((_RANKNB_) - 19)))
AnnaBridge 171:3a7713b1edbc 915
AnnaBridge 171:3a7713b1edbc 916 /**
AnnaBridge 171:3a7713b1edbc 917 * @brief Set the selected regular channel rank for rank between 25 and 28.
AnnaBridge 171:3a7713b1edbc 918 * @param _CHANNELNB_: Channel number.
AnnaBridge 171:3a7713b1edbc 919 * @param _RANKNB_: Rank number.
AnnaBridge 171:3a7713b1edbc 920 * @retval None
AnnaBridge 171:3a7713b1edbc 921 */
AnnaBridge 171:3a7713b1edbc 922 #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \
AnnaBridge 171:3a7713b1edbc 923 ((_CHANNELNB_) << (5 * ((_RANKNB_) - 25)))
AnnaBridge 171:3a7713b1edbc 924
AnnaBridge 171:3a7713b1edbc 925 /**
AnnaBridge 171:3a7713b1edbc 926 * @brief Set the injected sequence length.
AnnaBridge 171:3a7713b1edbc 927 * @param _JSQR_JL_: Sequence length.
AnnaBridge 171:3a7713b1edbc 928 * @retval None
AnnaBridge 171:3a7713b1edbc 929 */
AnnaBridge 171:3a7713b1edbc 930 #define ADC_JSQR_JL_SHIFT(_JSQR_JL_) (((_JSQR_JL_) -1) << 20)
AnnaBridge 171:3a7713b1edbc 931
AnnaBridge 171:3a7713b1edbc 932 /**
AnnaBridge 171:3a7713b1edbc 933 * @brief Set the selected injected channel rank
AnnaBridge 171:3a7713b1edbc 934 * Note: on STM32L1 devices, channel rank position in JSQR register
AnnaBridge 171:3a7713b1edbc 935 * is depending on total number of ranks selected into
AnnaBridge 171:3a7713b1edbc 936 * injected sequencer (ranks sequence starting from 4-JL)
AnnaBridge 171:3a7713b1edbc 937 * @param _CHANNELNB_: Channel number.
AnnaBridge 171:3a7713b1edbc 938 * @param _RANKNB_: Rank number.
AnnaBridge 171:3a7713b1edbc 939 * @param _JSQR_JL_: Sequence length.
AnnaBridge 171:3a7713b1edbc 940 * @retval None
AnnaBridge 171:3a7713b1edbc 941 */
AnnaBridge 171:3a7713b1edbc 942 #define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \
AnnaBridge 171:3a7713b1edbc 943 ((_CHANNELNB_) << (5 * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
AnnaBridge 171:3a7713b1edbc 944
AnnaBridge 171:3a7713b1edbc 945 /**
AnnaBridge 171:3a7713b1edbc 946 * @brief Enable the ADC DMA continuous request.
AnnaBridge 171:3a7713b1edbc 947 * @param _DMACONTREQ_MODE_: DMA continuous request mode.
AnnaBridge 171:3a7713b1edbc 948 * @retval None
AnnaBridge 171:3a7713b1edbc 949 */
AnnaBridge 171:3a7713b1edbc 950 #define ADC_CR2_DMACONTREQ(_DMACONTREQ_MODE_) \
AnnaBridge 171:3a7713b1edbc 951 ((_DMACONTREQ_MODE_) << POSITION_VAL(ADC_CR2_DDS))
AnnaBridge 171:3a7713b1edbc 952
AnnaBridge 171:3a7713b1edbc 953 /**
AnnaBridge 171:3a7713b1edbc 954 * @brief Enable ADC continuous conversion mode.
AnnaBridge 171:3a7713b1edbc 955 * @param _CONTINUOUS_MODE_: Continuous mode.
AnnaBridge 171:3a7713b1edbc 956 * @retval None
AnnaBridge 171:3a7713b1edbc 957 */
AnnaBridge 171:3a7713b1edbc 958 #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \
AnnaBridge 171:3a7713b1edbc 959 ((_CONTINUOUS_MODE_) << POSITION_VAL(ADC_CR2_CONT))
AnnaBridge 171:3a7713b1edbc 960
AnnaBridge 171:3a7713b1edbc 961 /**
AnnaBridge 171:3a7713b1edbc 962 * @brief Configures the number of discontinuous conversions for the regular group channels.
AnnaBridge 171:3a7713b1edbc 963 * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
AnnaBridge 171:3a7713b1edbc 964 * @retval None
AnnaBridge 171:3a7713b1edbc 965 */
AnnaBridge 171:3a7713b1edbc 966 #define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \
AnnaBridge 171:3a7713b1edbc 967 (((_NBR_DISCONTINUOUS_CONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM))
AnnaBridge 171:3a7713b1edbc 968
AnnaBridge 171:3a7713b1edbc 969 /**
AnnaBridge 171:3a7713b1edbc 970 * @brief Enable ADC scan mode to convert multiple ranks with sequencer.
AnnaBridge 171:3a7713b1edbc 971 * @param _SCAN_MODE_: Scan conversion mode.
AnnaBridge 171:3a7713b1edbc 972 * @retval None
AnnaBridge 171:3a7713b1edbc 973 */
AnnaBridge 171:3a7713b1edbc 974 /* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */
AnnaBridge 171:3a7713b1edbc 975 /* is equivalent to ADC_SCAN_ENABLE. */
AnnaBridge 171:3a7713b1edbc 976 #define ADC_CR1_SCAN_SET(_SCAN_MODE_) \
AnnaBridge 171:3a7713b1edbc 977 (( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) || ((_SCAN_MODE_) == ENABLE) \
AnnaBridge 171:3a7713b1edbc 978 )? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \
AnnaBridge 171:3a7713b1edbc 979 )
AnnaBridge 171:3a7713b1edbc 980
AnnaBridge 171:3a7713b1edbc 981
AnnaBridge 171:3a7713b1edbc 982 #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) || \
AnnaBridge 171:3a7713b1edbc 983 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2) || \
AnnaBridge 171:3a7713b1edbc 984 ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4) )
AnnaBridge 171:3a7713b1edbc 985
AnnaBridge 171:3a7713b1edbc 986 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
AnnaBridge 171:3a7713b1edbc 987 ((RESOLUTION) == ADC_RESOLUTION_10B) || \
AnnaBridge 171:3a7713b1edbc 988 ((RESOLUTION) == ADC_RESOLUTION_8B) || \
AnnaBridge 171:3a7713b1edbc 989 ((RESOLUTION) == ADC_RESOLUTION_6B) )
AnnaBridge 171:3a7713b1edbc 990
AnnaBridge 171:3a7713b1edbc 991 #define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) || \
AnnaBridge 171:3a7713b1edbc 992 ((RESOLUTION) == ADC_RESOLUTION_6B) )
AnnaBridge 171:3a7713b1edbc 993
AnnaBridge 171:3a7713b1edbc 994 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
AnnaBridge 171:3a7713b1edbc 995 ((ALIGN) == ADC_DATAALIGN_LEFT) )
AnnaBridge 171:3a7713b1edbc 996
AnnaBridge 171:3a7713b1edbc 997 #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \
AnnaBridge 171:3a7713b1edbc 998 ((SCAN_MODE) == ADC_SCAN_ENABLE) )
AnnaBridge 171:3a7713b1edbc 999
AnnaBridge 171:3a7713b1edbc 1000 #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
AnnaBridge 171:3a7713b1edbc 1001 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
AnnaBridge 171:3a7713b1edbc 1002 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
AnnaBridge 171:3a7713b1edbc 1003 ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) )
AnnaBridge 171:3a7713b1edbc 1004
AnnaBridge 171:3a7713b1edbc 1005 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \
AnnaBridge 171:3a7713b1edbc 1006 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
AnnaBridge 171:3a7713b1edbc 1007 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
AnnaBridge 171:3a7713b1edbc 1008 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \
AnnaBridge 171:3a7713b1edbc 1009 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC3) || \
AnnaBridge 171:3a7713b1edbc 1010 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
AnnaBridge 171:3a7713b1edbc 1011 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
AnnaBridge 171:3a7713b1edbc 1012 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \
AnnaBridge 171:3a7713b1edbc 1013 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
AnnaBridge 171:3a7713b1edbc 1014 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T9_CC2) || \
AnnaBridge 171:3a7713b1edbc 1015 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T9_TRGO) || \
AnnaBridge 171:3a7713b1edbc 1016 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
AnnaBridge 171:3a7713b1edbc 1017 ((REGTRIG) == ADC_SOFTWARE_START) )
AnnaBridge 171:3a7713b1edbc 1018
AnnaBridge 171:3a7713b1edbc 1019 #define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \
AnnaBridge 171:3a7713b1edbc 1020 ((EOC_SELECTION) == ADC_EOC_SEQ_CONV) )
AnnaBridge 171:3a7713b1edbc 1021
AnnaBridge 171:3a7713b1edbc 1022 #define IS_ADC_AUTOWAIT(AUTOWAIT) (((AUTOWAIT) == ADC_AUTOWAIT_DISABLE) || \
AnnaBridge 171:3a7713b1edbc 1023 ((AUTOWAIT) == ADC_AUTOWAIT_UNTIL_DATA_READ) || \
AnnaBridge 171:3a7713b1edbc 1024 ((AUTOWAIT) == ADC_AUTOWAIT_7_APBCLOCKCYCLES) || \
AnnaBridge 171:3a7713b1edbc 1025 ((AUTOWAIT) == ADC_AUTOWAIT_15_APBCLOCKCYCLES) || \
AnnaBridge 171:3a7713b1edbc 1026 ((AUTOWAIT) == ADC_AUTOWAIT_31_APBCLOCKCYCLES) || \
AnnaBridge 171:3a7713b1edbc 1027 ((AUTOWAIT) == ADC_AUTOWAIT_63_APBCLOCKCYCLES) || \
AnnaBridge 171:3a7713b1edbc 1028 ((AUTOWAIT) == ADC_AUTOWAIT_127_APBCLOCKCYCLES) || \
AnnaBridge 171:3a7713b1edbc 1029 ((AUTOWAIT) == ADC_AUTOWAIT_255_APBCLOCKCYCLES) )
AnnaBridge 171:3a7713b1edbc 1030
AnnaBridge 171:3a7713b1edbc 1031 #define IS_ADC_AUTOPOWEROFF(AUTOPOWEROFF) (((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_DISABLE) || \
AnnaBridge 171:3a7713b1edbc 1032 ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_IDLE_PHASE) || \
AnnaBridge 171:3a7713b1edbc 1033 ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_DELAY_PHASE) || \
AnnaBridge 171:3a7713b1edbc 1034 ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_IDLE_DELAY_PHASES) )
AnnaBridge 171:3a7713b1edbc 1035
AnnaBridge 171:3a7713b1edbc 1036 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
AnnaBridge 171:3a7713b1edbc 1037
AnnaBridge 171:3a7713b1edbc 1038 #define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A) || \
AnnaBridge 171:3a7713b1edbc 1039 ((BANK) == ADC_CHANNELS_BANK_B) )
AnnaBridge 171:3a7713b1edbc 1040 #else
AnnaBridge 171:3a7713b1edbc 1041
AnnaBridge 171:3a7713b1edbc 1042 #define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A))
AnnaBridge 171:3a7713b1edbc 1043 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
AnnaBridge 171:3a7713b1edbc 1044
AnnaBridge 171:3a7713b1edbc 1045 #if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
AnnaBridge 171:3a7713b1edbc 1046 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
AnnaBridge 171:3a7713b1edbc 1047 ((CHANNEL) == ADC_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 1048 ((CHANNEL) == ADC_CHANNEL_2) || \
AnnaBridge 171:3a7713b1edbc 1049 ((CHANNEL) == ADC_CHANNEL_3) || \
AnnaBridge 171:3a7713b1edbc 1050 ((CHANNEL) == ADC_CHANNEL_4) || \
AnnaBridge 171:3a7713b1edbc 1051 ((CHANNEL) == ADC_CHANNEL_5) || \
AnnaBridge 171:3a7713b1edbc 1052 ((CHANNEL) == ADC_CHANNEL_6) || \
AnnaBridge 171:3a7713b1edbc 1053 ((CHANNEL) == ADC_CHANNEL_7) || \
AnnaBridge 171:3a7713b1edbc 1054 ((CHANNEL) == ADC_CHANNEL_8) || \
AnnaBridge 171:3a7713b1edbc 1055 ((CHANNEL) == ADC_CHANNEL_9) || \
AnnaBridge 171:3a7713b1edbc 1056 ((CHANNEL) == ADC_CHANNEL_10) || \
AnnaBridge 171:3a7713b1edbc 1057 ((CHANNEL) == ADC_CHANNEL_11) || \
AnnaBridge 171:3a7713b1edbc 1058 ((CHANNEL) == ADC_CHANNEL_12) || \
AnnaBridge 171:3a7713b1edbc 1059 ((CHANNEL) == ADC_CHANNEL_13) || \
AnnaBridge 171:3a7713b1edbc 1060 ((CHANNEL) == ADC_CHANNEL_14) || \
AnnaBridge 171:3a7713b1edbc 1061 ((CHANNEL) == ADC_CHANNEL_15) || \
AnnaBridge 171:3a7713b1edbc 1062 ((CHANNEL) == ADC_CHANNEL_16) || \
AnnaBridge 171:3a7713b1edbc 1063 ((CHANNEL) == ADC_CHANNEL_17) || \
AnnaBridge 171:3a7713b1edbc 1064 ((CHANNEL) == ADC_CHANNEL_18) || \
AnnaBridge 171:3a7713b1edbc 1065 ((CHANNEL) == ADC_CHANNEL_19) || \
AnnaBridge 171:3a7713b1edbc 1066 ((CHANNEL) == ADC_CHANNEL_20) || \
AnnaBridge 171:3a7713b1edbc 1067 ((CHANNEL) == ADC_CHANNEL_21) || \
AnnaBridge 171:3a7713b1edbc 1068 ((CHANNEL) == ADC_CHANNEL_22) || \
AnnaBridge 171:3a7713b1edbc 1069 ((CHANNEL) == ADC_CHANNEL_23) || \
AnnaBridge 171:3a7713b1edbc 1070 ((CHANNEL) == ADC_CHANNEL_24) || \
AnnaBridge 171:3a7713b1edbc 1071 ((CHANNEL) == ADC_CHANNEL_25) || \
AnnaBridge 171:3a7713b1edbc 1072 ((CHANNEL) == ADC_CHANNEL_26) )
AnnaBridge 171:3a7713b1edbc 1073 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */
AnnaBridge 171:3a7713b1edbc 1074 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
AnnaBridge 171:3a7713b1edbc 1075 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \
AnnaBridge 171:3a7713b1edbc 1076 ((CHANNEL) == ADC_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 1077 ((CHANNEL) == ADC_CHANNEL_2) || \
AnnaBridge 171:3a7713b1edbc 1078 ((CHANNEL) == ADC_CHANNEL_3) || \
AnnaBridge 171:3a7713b1edbc 1079 ((CHANNEL) == ADC_CHANNEL_4) || \
AnnaBridge 171:3a7713b1edbc 1080 ((CHANNEL) == ADC_CHANNEL_5) || \
AnnaBridge 171:3a7713b1edbc 1081 ((CHANNEL) == ADC_CHANNEL_6) || \
AnnaBridge 171:3a7713b1edbc 1082 ((CHANNEL) == ADC_CHANNEL_7) || \
AnnaBridge 171:3a7713b1edbc 1083 ((CHANNEL) == ADC_CHANNEL_8) || \
AnnaBridge 171:3a7713b1edbc 1084 ((CHANNEL) == ADC_CHANNEL_9) || \
AnnaBridge 171:3a7713b1edbc 1085 ((CHANNEL) == ADC_CHANNEL_10) || \
AnnaBridge 171:3a7713b1edbc 1086 ((CHANNEL) == ADC_CHANNEL_11) || \
AnnaBridge 171:3a7713b1edbc 1087 ((CHANNEL) == ADC_CHANNEL_12) || \
AnnaBridge 171:3a7713b1edbc 1088 ((CHANNEL) == ADC_CHANNEL_13) || \
AnnaBridge 171:3a7713b1edbc 1089 ((CHANNEL) == ADC_CHANNEL_14) || \
AnnaBridge 171:3a7713b1edbc 1090 ((CHANNEL) == ADC_CHANNEL_15) || \
AnnaBridge 171:3a7713b1edbc 1091 ((CHANNEL) == ADC_CHANNEL_16) || \
AnnaBridge 171:3a7713b1edbc 1092 ((CHANNEL) == ADC_CHANNEL_17) || \
AnnaBridge 171:3a7713b1edbc 1093 ((CHANNEL) == ADC_CHANNEL_18) || \
AnnaBridge 171:3a7713b1edbc 1094 ((CHANNEL) == ADC_CHANNEL_19) || \
AnnaBridge 171:3a7713b1edbc 1095 ((CHANNEL) == ADC_CHANNEL_20) || \
AnnaBridge 171:3a7713b1edbc 1096 ((CHANNEL) == ADC_CHANNEL_21) || \
AnnaBridge 171:3a7713b1edbc 1097 ((CHANNEL) == ADC_CHANNEL_22) || \
AnnaBridge 171:3a7713b1edbc 1098 ((CHANNEL) == ADC_CHANNEL_23) || \
AnnaBridge 171:3a7713b1edbc 1099 ((CHANNEL) == ADC_CHANNEL_24) || \
AnnaBridge 171:3a7713b1edbc 1100 ((CHANNEL) == ADC_CHANNEL_25) || \
AnnaBridge 171:3a7713b1edbc 1101 ((CHANNEL) == ADC_CHANNEL_26) || \
AnnaBridge 171:3a7713b1edbc 1102 ((CHANNEL) == ADC_CHANNEL_27) || \
AnnaBridge 171:3a7713b1edbc 1103 ((CHANNEL) == ADC_CHANNEL_28) || \
AnnaBridge 171:3a7713b1edbc 1104 ((CHANNEL) == ADC_CHANNEL_29) || \
AnnaBridge 171:3a7713b1edbc 1105 ((CHANNEL) == ADC_CHANNEL_30) || \
AnnaBridge 171:3a7713b1edbc 1106 ((CHANNEL) == ADC_CHANNEL_31) )
AnnaBridge 171:3a7713b1edbc 1107 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
AnnaBridge 171:3a7713b1edbc 1108
AnnaBridge 171:3a7713b1edbc 1109 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_4CYCLES) || \
AnnaBridge 171:3a7713b1edbc 1110 ((TIME) == ADC_SAMPLETIME_9CYCLES) || \
AnnaBridge 171:3a7713b1edbc 1111 ((TIME) == ADC_SAMPLETIME_16CYCLES) || \
AnnaBridge 171:3a7713b1edbc 1112 ((TIME) == ADC_SAMPLETIME_24CYCLES) || \
AnnaBridge 171:3a7713b1edbc 1113 ((TIME) == ADC_SAMPLETIME_48CYCLES) || \
AnnaBridge 171:3a7713b1edbc 1114 ((TIME) == ADC_SAMPLETIME_96CYCLES) || \
AnnaBridge 171:3a7713b1edbc 1115 ((TIME) == ADC_SAMPLETIME_192CYCLES) || \
AnnaBridge 171:3a7713b1edbc 1116 ((TIME) == ADC_SAMPLETIME_384CYCLES) )
AnnaBridge 171:3a7713b1edbc 1117
AnnaBridge 171:3a7713b1edbc 1118 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
AnnaBridge 171:3a7713b1edbc 1119
AnnaBridge 171:3a7713b1edbc 1120 #define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \
AnnaBridge 171:3a7713b1edbc 1121 ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \
AnnaBridge 171:3a7713b1edbc 1122 ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \
AnnaBridge 171:3a7713b1edbc 1123 ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \
AnnaBridge 171:3a7713b1edbc 1124 ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \
AnnaBridge 171:3a7713b1edbc 1125 ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \
AnnaBridge 171:3a7713b1edbc 1126 ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \
AnnaBridge 171:3a7713b1edbc 1127 ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \
AnnaBridge 171:3a7713b1edbc 1128 ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \
AnnaBridge 171:3a7713b1edbc 1129 ((CHANNEL) == ADC_REGULAR_RANK_10) || \
AnnaBridge 171:3a7713b1edbc 1130 ((CHANNEL) == ADC_REGULAR_RANK_11) || \
AnnaBridge 171:3a7713b1edbc 1131 ((CHANNEL) == ADC_REGULAR_RANK_12) || \
AnnaBridge 171:3a7713b1edbc 1132 ((CHANNEL) == ADC_REGULAR_RANK_13) || \
AnnaBridge 171:3a7713b1edbc 1133 ((CHANNEL) == ADC_REGULAR_RANK_14) || \
AnnaBridge 171:3a7713b1edbc 1134 ((CHANNEL) == ADC_REGULAR_RANK_15) || \
AnnaBridge 171:3a7713b1edbc 1135 ((CHANNEL) == ADC_REGULAR_RANK_16) || \
AnnaBridge 171:3a7713b1edbc 1136 ((CHANNEL) == ADC_REGULAR_RANK_17) || \
AnnaBridge 171:3a7713b1edbc 1137 ((CHANNEL) == ADC_REGULAR_RANK_18) || \
AnnaBridge 171:3a7713b1edbc 1138 ((CHANNEL) == ADC_REGULAR_RANK_19) || \
AnnaBridge 171:3a7713b1edbc 1139 ((CHANNEL) == ADC_REGULAR_RANK_20) || \
AnnaBridge 171:3a7713b1edbc 1140 ((CHANNEL) == ADC_REGULAR_RANK_21) || \
AnnaBridge 171:3a7713b1edbc 1141 ((CHANNEL) == ADC_REGULAR_RANK_22) || \
AnnaBridge 171:3a7713b1edbc 1142 ((CHANNEL) == ADC_REGULAR_RANK_23) || \
AnnaBridge 171:3a7713b1edbc 1143 ((CHANNEL) == ADC_REGULAR_RANK_24) || \
AnnaBridge 171:3a7713b1edbc 1144 ((CHANNEL) == ADC_REGULAR_RANK_25) || \
AnnaBridge 171:3a7713b1edbc 1145 ((CHANNEL) == ADC_REGULAR_RANK_26) || \
AnnaBridge 171:3a7713b1edbc 1146 ((CHANNEL) == ADC_REGULAR_RANK_27) || \
AnnaBridge 171:3a7713b1edbc 1147 ((CHANNEL) == ADC_REGULAR_RANK_28) )
AnnaBridge 171:3a7713b1edbc 1148 #else
AnnaBridge 171:3a7713b1edbc 1149
AnnaBridge 171:3a7713b1edbc 1150 #define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \
AnnaBridge 171:3a7713b1edbc 1151 ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \
AnnaBridge 171:3a7713b1edbc 1152 ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \
AnnaBridge 171:3a7713b1edbc 1153 ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \
AnnaBridge 171:3a7713b1edbc 1154 ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \
AnnaBridge 171:3a7713b1edbc 1155 ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \
AnnaBridge 171:3a7713b1edbc 1156 ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \
AnnaBridge 171:3a7713b1edbc 1157 ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \
AnnaBridge 171:3a7713b1edbc 1158 ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \
AnnaBridge 171:3a7713b1edbc 1159 ((CHANNEL) == ADC_REGULAR_RANK_10) || \
AnnaBridge 171:3a7713b1edbc 1160 ((CHANNEL) == ADC_REGULAR_RANK_11) || \
AnnaBridge 171:3a7713b1edbc 1161 ((CHANNEL) == ADC_REGULAR_RANK_12) || \
AnnaBridge 171:3a7713b1edbc 1162 ((CHANNEL) == ADC_REGULAR_RANK_13) || \
AnnaBridge 171:3a7713b1edbc 1163 ((CHANNEL) == ADC_REGULAR_RANK_14) || \
AnnaBridge 171:3a7713b1edbc 1164 ((CHANNEL) == ADC_REGULAR_RANK_15) || \
AnnaBridge 171:3a7713b1edbc 1165 ((CHANNEL) == ADC_REGULAR_RANK_16) || \
AnnaBridge 171:3a7713b1edbc 1166 ((CHANNEL) == ADC_REGULAR_RANK_17) || \
AnnaBridge 171:3a7713b1edbc 1167 ((CHANNEL) == ADC_REGULAR_RANK_18) || \
AnnaBridge 171:3a7713b1edbc 1168 ((CHANNEL) == ADC_REGULAR_RANK_19) || \
AnnaBridge 171:3a7713b1edbc 1169 ((CHANNEL) == ADC_REGULAR_RANK_20) || \
AnnaBridge 171:3a7713b1edbc 1170 ((CHANNEL) == ADC_REGULAR_RANK_21) || \
AnnaBridge 171:3a7713b1edbc 1171 ((CHANNEL) == ADC_REGULAR_RANK_22) || \
AnnaBridge 171:3a7713b1edbc 1172 ((CHANNEL) == ADC_REGULAR_RANK_23) || \
AnnaBridge 171:3a7713b1edbc 1173 ((CHANNEL) == ADC_REGULAR_RANK_24) || \
AnnaBridge 171:3a7713b1edbc 1174 ((CHANNEL) == ADC_REGULAR_RANK_25) || \
AnnaBridge 171:3a7713b1edbc 1175 ((CHANNEL) == ADC_REGULAR_RANK_26) || \
AnnaBridge 171:3a7713b1edbc 1176 ((CHANNEL) == ADC_REGULAR_RANK_27) )
AnnaBridge 171:3a7713b1edbc 1177 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
AnnaBridge 171:3a7713b1edbc 1178
AnnaBridge 171:3a7713b1edbc 1179 #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \
AnnaBridge 171:3a7713b1edbc 1180 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
AnnaBridge 171:3a7713b1edbc 1181 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
AnnaBridge 171:3a7713b1edbc 1182 ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
AnnaBridge 171:3a7713b1edbc 1183 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \
AnnaBridge 171:3a7713b1edbc 1184 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
AnnaBridge 171:3a7713b1edbc 1185 ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
AnnaBridge 171:3a7713b1edbc 1186
AnnaBridge 171:3a7713b1edbc 1187 #define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) || \
AnnaBridge 171:3a7713b1edbc 1188 ((CONVERSION) == ADC_INJECTED_GROUP) || \
AnnaBridge 171:3a7713b1edbc 1189 ((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) )
AnnaBridge 171:3a7713b1edbc 1190
AnnaBridge 171:3a7713b1edbc 1191 #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \
AnnaBridge 171:3a7713b1edbc 1192 ((EVENT) == ADC_FLAG_OVR) )
AnnaBridge 171:3a7713b1edbc 1193
AnnaBridge 171:3a7713b1edbc 1194 /**
AnnaBridge 171:3a7713b1edbc 1195 * @brief Verify that a ADC data is within range corresponding to
AnnaBridge 171:3a7713b1edbc 1196 * ADC resolution.
AnnaBridge 171:3a7713b1edbc 1197 * @param __RESOLUTION__: ADC resolution (12, 10, 8 or 6 bits).
AnnaBridge 171:3a7713b1edbc 1198 * @param __ADC_DATA__: value checked against the resolution.
AnnaBridge 171:3a7713b1edbc 1199 * @retval SET: ADC data is within range corresponding to ADC resolution
AnnaBridge 171:3a7713b1edbc 1200 * RESET: ADC data is not within range corresponding to ADC resolution
AnnaBridge 171:3a7713b1edbc 1201 *
AnnaBridge 171:3a7713b1edbc 1202 */
AnnaBridge 171:3a7713b1edbc 1203 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_DATA__) \
AnnaBridge 171:3a7713b1edbc 1204 ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_DATA__) <= (0x0FFFU))) || \
AnnaBridge 171:3a7713b1edbc 1205 (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_DATA__) <= (0x03FFU))) || \
AnnaBridge 171:3a7713b1edbc 1206 (((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_DATA__) <= (0x00FFU))) || \
AnnaBridge 171:3a7713b1edbc 1207 (((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_DATA__) <= (0x003FU))) )
AnnaBridge 171:3a7713b1edbc 1208
AnnaBridge 171:3a7713b1edbc 1209
AnnaBridge 171:3a7713b1edbc 1210 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
AnnaBridge 171:3a7713b1edbc 1211 #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (28U)))
AnnaBridge 171:3a7713b1edbc 1212 #else
AnnaBridge 171:3a7713b1edbc 1213 #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (27U)))
AnnaBridge 171:3a7713b1edbc 1214 #endif
AnnaBridge 171:3a7713b1edbc 1215
AnnaBridge 171:3a7713b1edbc 1216 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1U)) && ((NUMBER) <= (8U)))
AnnaBridge 171:3a7713b1edbc 1217
AnnaBridge 171:3a7713b1edbc 1218 /**
AnnaBridge 171:3a7713b1edbc 1219 * @}
AnnaBridge 171:3a7713b1edbc 1220 */
AnnaBridge 171:3a7713b1edbc 1221
AnnaBridge 171:3a7713b1edbc 1222
AnnaBridge 171:3a7713b1edbc 1223 /* Include ADC HAL Extension module */
AnnaBridge 171:3a7713b1edbc 1224 #include "stm32l1xx_hal_adc_ex.h"
AnnaBridge 171:3a7713b1edbc 1225
AnnaBridge 171:3a7713b1edbc 1226 /* Exported functions --------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 1227 /** @addtogroup ADC_Exported_Functions
AnnaBridge 171:3a7713b1edbc 1228 * @{
AnnaBridge 171:3a7713b1edbc 1229 */
AnnaBridge 171:3a7713b1edbc 1230
AnnaBridge 171:3a7713b1edbc 1231 /** @addtogroup ADC_Exported_Functions_Group1
AnnaBridge 171:3a7713b1edbc 1232 * @{
AnnaBridge 171:3a7713b1edbc 1233 */
AnnaBridge 171:3a7713b1edbc 1234
AnnaBridge 171:3a7713b1edbc 1235
AnnaBridge 171:3a7713b1edbc 1236 /* Initialization and de-initialization functions **********************************/
AnnaBridge 171:3a7713b1edbc 1237 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 1238 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
AnnaBridge 171:3a7713b1edbc 1239 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 1240 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 1241 /**
AnnaBridge 171:3a7713b1edbc 1242 * @}
AnnaBridge 171:3a7713b1edbc 1243 */
AnnaBridge 171:3a7713b1edbc 1244
AnnaBridge 171:3a7713b1edbc 1245 /* IO operation functions *****************************************************/
AnnaBridge 171:3a7713b1edbc 1246
AnnaBridge 171:3a7713b1edbc 1247 /** @addtogroup ADC_Exported_Functions_Group2
AnnaBridge 171:3a7713b1edbc 1248 * @{
AnnaBridge 171:3a7713b1edbc 1249 */
AnnaBridge 171:3a7713b1edbc 1250
AnnaBridge 171:3a7713b1edbc 1251
AnnaBridge 171:3a7713b1edbc 1252 /* Blocking mode: Polling */
AnnaBridge 171:3a7713b1edbc 1253 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 1254 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 1255 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
AnnaBridge 171:3a7713b1edbc 1256 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
AnnaBridge 171:3a7713b1edbc 1257
AnnaBridge 171:3a7713b1edbc 1258 /* Non-blocking mode: Interruption */
AnnaBridge 171:3a7713b1edbc 1259 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 1260 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 1261
AnnaBridge 171:3a7713b1edbc 1262 /* Non-blocking mode: DMA */
AnnaBridge 171:3a7713b1edbc 1263 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
AnnaBridge 171:3a7713b1edbc 1264 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 1265
AnnaBridge 171:3a7713b1edbc 1266 /* ADC retrieve conversion value intended to be used with polling or interruption */
AnnaBridge 171:3a7713b1edbc 1267 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 1268
AnnaBridge 171:3a7713b1edbc 1269 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
AnnaBridge 171:3a7713b1edbc 1270 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 1271 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 1272 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 1273 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 1274 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
AnnaBridge 171:3a7713b1edbc 1275 /**
AnnaBridge 171:3a7713b1edbc 1276 * @}
AnnaBridge 171:3a7713b1edbc 1277 */
AnnaBridge 171:3a7713b1edbc 1278
AnnaBridge 171:3a7713b1edbc 1279
AnnaBridge 171:3a7713b1edbc 1280 /* Peripheral Control functions ***********************************************/
AnnaBridge 171:3a7713b1edbc 1281 /** @addtogroup ADC_Exported_Functions_Group3
AnnaBridge 171:3a7713b1edbc 1282 * @{
AnnaBridge 171:3a7713b1edbc 1283 */
AnnaBridge 171:3a7713b1edbc 1284 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
AnnaBridge 171:3a7713b1edbc 1285 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
AnnaBridge 171:3a7713b1edbc 1286 /**
AnnaBridge 171:3a7713b1edbc 1287 * @}
AnnaBridge 171:3a7713b1edbc 1288 */
AnnaBridge 171:3a7713b1edbc 1289
AnnaBridge 171:3a7713b1edbc 1290
AnnaBridge 171:3a7713b1edbc 1291 /* Peripheral State functions *************************************************/
AnnaBridge 171:3a7713b1edbc 1292 /** @addtogroup ADC_Exported_Functions_Group4
AnnaBridge 171:3a7713b1edbc 1293 * @{
AnnaBridge 171:3a7713b1edbc 1294 */
AnnaBridge 171:3a7713b1edbc 1295 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 1296 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
AnnaBridge 171:3a7713b1edbc 1297 /**
AnnaBridge 171:3a7713b1edbc 1298 * @}
AnnaBridge 171:3a7713b1edbc 1299 */
AnnaBridge 171:3a7713b1edbc 1300
AnnaBridge 171:3a7713b1edbc 1301
AnnaBridge 171:3a7713b1edbc 1302 /**
AnnaBridge 171:3a7713b1edbc 1303 * @}
AnnaBridge 171:3a7713b1edbc 1304 */
AnnaBridge 171:3a7713b1edbc 1305
AnnaBridge 171:3a7713b1edbc 1306
AnnaBridge 171:3a7713b1edbc 1307 /* Internal HAL driver functions **********************************************/
AnnaBridge 171:3a7713b1edbc 1308 /** @addtogroup ADC_Private_Functions
AnnaBridge 171:3a7713b1edbc 1309 * @{
AnnaBridge 171:3a7713b1edbc 1310 */
AnnaBridge 171:3a7713b1edbc 1311
AnnaBridge 171:3a7713b1edbc 1312 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 1313 HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc);
AnnaBridge 171:3a7713b1edbc 1314 /**
AnnaBridge 171:3a7713b1edbc 1315 * @}
AnnaBridge 171:3a7713b1edbc 1316 */
AnnaBridge 171:3a7713b1edbc 1317
AnnaBridge 171:3a7713b1edbc 1318
AnnaBridge 171:3a7713b1edbc 1319 /**
AnnaBridge 171:3a7713b1edbc 1320 * @}
AnnaBridge 171:3a7713b1edbc 1321 */
AnnaBridge 171:3a7713b1edbc 1322
AnnaBridge 171:3a7713b1edbc 1323 /**
AnnaBridge 171:3a7713b1edbc 1324 * @}
AnnaBridge 171:3a7713b1edbc 1325 */
AnnaBridge 171:3a7713b1edbc 1326
AnnaBridge 171:3a7713b1edbc 1327 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 1328 }
AnnaBridge 171:3a7713b1edbc 1329 #endif
AnnaBridge 171:3a7713b1edbc 1330
AnnaBridge 171:3a7713b1edbc 1331
AnnaBridge 171:3a7713b1edbc 1332 #endif /* __STM32L1xx_HAL_ADC_H */
AnnaBridge 171:3a7713b1edbc 1333
AnnaBridge 171:3a7713b1edbc 1334 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/