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TARGET_MOTE_L152RC/TOOLCHAIN_GCC_ARM/stm32l1xx_hal.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	171:3a7713b1edbc	1	/**
AnnaBridge	171:3a7713b1edbc	2	******************************************************************************
AnnaBridge	171:3a7713b1edbc	3	* @file stm32l1xx_hal.h
AnnaBridge	171:3a7713b1edbc	4	* @author MCD Application Team
AnnaBridge	171:3a7713b1edbc	5	* @brief This file contains all the functions prototypes for the HAL
AnnaBridge	171:3a7713b1edbc	6	* module driver.
AnnaBridge	171:3a7713b1edbc	7	******************************************************************************
AnnaBridge	171:3a7713b1edbc	8	* @attention
AnnaBridge	171:3a7713b1edbc	9	*
AnnaBridge	171:3a7713b1edbc	10	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	171:3a7713b1edbc	11	*
AnnaBridge	171:3a7713b1edbc	12	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	171:3a7713b1edbc	13	* are permitted provided that the following conditions are met:
AnnaBridge	171:3a7713b1edbc	14	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	171:3a7713b1edbc	15	* this list of conditions and the following disclaimer.
AnnaBridge	171:3a7713b1edbc	16	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	171:3a7713b1edbc	17	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	171:3a7713b1edbc	18	* and/or other materials provided with the distribution.
AnnaBridge	171:3a7713b1edbc	19	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	171:3a7713b1edbc	20	* may be used to endorse or promote products derived from this software
AnnaBridge	171:3a7713b1edbc	21	* without specific prior written permission.
AnnaBridge	171:3a7713b1edbc	22	*
AnnaBridge	171:3a7713b1edbc	23	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	171:3a7713b1edbc	24	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	171:3a7713b1edbc	25	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	171:3a7713b1edbc	26	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	171:3a7713b1edbc	27	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	171:3a7713b1edbc	28	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	171:3a7713b1edbc	29	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	171:3a7713b1edbc	30	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	171:3a7713b1edbc	31	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	171:3a7713b1edbc	32	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	171:3a7713b1edbc	33	*
AnnaBridge	171:3a7713b1edbc	34	******************************************************************************
AnnaBridge	171:3a7713b1edbc	35	*/
AnnaBridge	171:3a7713b1edbc	36
AnnaBridge	171:3a7713b1edbc	37	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	171:3a7713b1edbc	38	#ifndef __STM32L1xx_HAL_H
AnnaBridge	171:3a7713b1edbc	39	#define __STM32L1xx_HAL_H
AnnaBridge	171:3a7713b1edbc	40
AnnaBridge	171:3a7713b1edbc	41	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	42	extern "C" {
AnnaBridge	171:3a7713b1edbc	43	#endif
AnnaBridge	171:3a7713b1edbc	44
AnnaBridge	171:3a7713b1edbc	45	/* Includes ------------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	46	#include "stm32l1xx_hal_conf.h"
AnnaBridge	171:3a7713b1edbc	47
AnnaBridge	171:3a7713b1edbc	48	/** @addtogroup STM32L1xx_HAL_Driver
AnnaBridge	171:3a7713b1edbc	49	* @{
AnnaBridge	171:3a7713b1edbc	50	*/
AnnaBridge	171:3a7713b1edbc	51
AnnaBridge	171:3a7713b1edbc	52	/** @addtogroup HAL
AnnaBridge	171:3a7713b1edbc	53	* @{
AnnaBridge	171:3a7713b1edbc	54	*/
AnnaBridge	171:3a7713b1edbc	55
AnnaBridge	171:3a7713b1edbc	56	/* Exported types ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	57	/* Exported constants --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	58	/** @defgroup HAL_Exported_Constants HAL Exported Constants
AnnaBridge	171:3a7713b1edbc	59	* @{
AnnaBridge	171:3a7713b1edbc	60	*/
AnnaBridge	171:3a7713b1edbc	61
AnnaBridge	171:3a7713b1edbc	62	/** @defgroup SYSCFG_Constants SYSCFG: SYStem ConFiG
AnnaBridge	171:3a7713b1edbc	63	* @{
AnnaBridge	171:3a7713b1edbc	64	*/
AnnaBridge	171:3a7713b1edbc	65
AnnaBridge	171:3a7713b1edbc	66	/** @defgroup SYSCFG_BootMode Boot Mode
AnnaBridge	171:3a7713b1edbc	67	* @{
AnnaBridge	171:3a7713b1edbc	68	*/
AnnaBridge	171:3a7713b1edbc	69
AnnaBridge	171:3a7713b1edbc	70	#define SYSCFG_BOOT_MAINFLASH (0x00000000U)
AnnaBridge	171:3a7713b1edbc	71	#define SYSCFG_BOOT_SYSTEMFLASH ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_0)
AnnaBridge	171:3a7713b1edbc	72	#if defined(FSMC_R_BASE)
AnnaBridge	171:3a7713b1edbc	73	#define SYSCFG_BOOT_FSMC ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_1)
AnnaBridge	171:3a7713b1edbc	74	#endif /* FSMC_R_BASE */
AnnaBridge	171:3a7713b1edbc	75	#define SYSCFG_BOOT_SRAM ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE)
AnnaBridge	171:3a7713b1edbc	76
AnnaBridge	171:3a7713b1edbc	77	/**
AnnaBridge	171:3a7713b1edbc	78	* @}
AnnaBridge	171:3a7713b1edbc	79	*/
AnnaBridge	171:3a7713b1edbc	80
AnnaBridge	171:3a7713b1edbc	81	/**
AnnaBridge	171:3a7713b1edbc	82	* @}
AnnaBridge	171:3a7713b1edbc	83	*/
AnnaBridge	171:3a7713b1edbc	84
AnnaBridge	171:3a7713b1edbc	85	/** @defgroup RI_Constants RI: Routing Interface
AnnaBridge	171:3a7713b1edbc	86	* @{
AnnaBridge	171:3a7713b1edbc	87	*/
AnnaBridge	171:3a7713b1edbc	88
AnnaBridge	171:3a7713b1edbc	89	/** @defgroup RI_InputCapture Input Capture
AnnaBridge	171:3a7713b1edbc	90	* @{
AnnaBridge	171:3a7713b1edbc	91	*/
AnnaBridge	171:3a7713b1edbc	92
AnnaBridge	171:3a7713b1edbc	93	#define RI_INPUTCAPTURE_IC1 RI_ICR_IC1 /!< Input Capture 1 /
AnnaBridge	171:3a7713b1edbc	94	#define RI_INPUTCAPTURE_IC2 RI_ICR_IC2 /!< Input Capture 2 /
AnnaBridge	171:3a7713b1edbc	95	#define RI_INPUTCAPTURE_IC3 RI_ICR_IC3 /!< Input Capture 3 /
AnnaBridge	171:3a7713b1edbc	96	#define RI_INPUTCAPTURE_IC4 RI_ICR_IC4 /!< Input Capture 4 /
AnnaBridge	171:3a7713b1edbc	97
AnnaBridge	171:3a7713b1edbc	98	/**
AnnaBridge	171:3a7713b1edbc	99	* @}
AnnaBridge	171:3a7713b1edbc	100	*/
AnnaBridge	171:3a7713b1edbc	101
AnnaBridge	171:3a7713b1edbc	102	/** @defgroup TIM_Select TIM Select
AnnaBridge	171:3a7713b1edbc	103	* @{
AnnaBridge	171:3a7713b1edbc	104	*/
AnnaBridge	171:3a7713b1edbc	105
AnnaBridge	171:3a7713b1edbc	106	#define TIM_SELECT_NONE (0x00000000U) /!< None selected /
AnnaBridge	171:3a7713b1edbc	107	#define TIM_SELECT_TIM2 ((uint32_t)RI_ICR_TIM_0) /!< Timer 2 selected /
AnnaBridge	171:3a7713b1edbc	108	#define TIM_SELECT_TIM3 ((uint32_t)RI_ICR_TIM_1) /!< Timer 3 selected /
AnnaBridge	171:3a7713b1edbc	109	#define TIM_SELECT_TIM4 ((uint32_t)RI_ICR_TIM) /!< Timer 4 selected /
AnnaBridge	171:3a7713b1edbc	110
AnnaBridge	171:3a7713b1edbc	111	#define IS_RI_TIM(__TIM__) (((__TIM__) == TIM_SELECT_NONE) \|\| \
AnnaBridge	171:3a7713b1edbc	112	((__TIM__) == TIM_SELECT_TIM2) \|\| \
AnnaBridge	171:3a7713b1edbc	113	((__TIM__) == TIM_SELECT_TIM3) \|\| \
AnnaBridge	171:3a7713b1edbc	114	((__TIM__) == TIM_SELECT_TIM4))
AnnaBridge	171:3a7713b1edbc	115
AnnaBridge	171:3a7713b1edbc	116	/**
AnnaBridge	171:3a7713b1edbc	117	* @}
AnnaBridge	171:3a7713b1edbc	118	*/
AnnaBridge	171:3a7713b1edbc	119
AnnaBridge	171:3a7713b1edbc	120	/** @defgroup RI_InputCaptureRouting Input Capture Routing
AnnaBridge	171:3a7713b1edbc	121	* @{
AnnaBridge	171:3a7713b1edbc	122	*/
AnnaBridge	171:3a7713b1edbc	123	/* TIMx_IC1 TIMx_IC2 TIMx_IC3 TIMx_IC4 */
AnnaBridge	171:3a7713b1edbc	124	#define RI_INPUTCAPTUREROUTING_0 (0x00000000U) /* PA0 PA1 PA2 PA3 */
AnnaBridge	171:3a7713b1edbc	125	#define RI_INPUTCAPTUREROUTING_1 (0x00000001U) /* PA4 PA5 PA6 PA7 */
AnnaBridge	171:3a7713b1edbc	126	#define RI_INPUTCAPTUREROUTING_2 (0x00000002U) /* PA8 PA9 PA10 PA11 */
AnnaBridge	171:3a7713b1edbc	127	#define RI_INPUTCAPTUREROUTING_3 (0x00000003U) /* PA12 PA13 PA14 PA15 */
AnnaBridge	171:3a7713b1edbc	128	#define RI_INPUTCAPTUREROUTING_4 (0x00000004U) /* PC0 PC1 PC2 PC3 */
AnnaBridge	171:3a7713b1edbc	129	#define RI_INPUTCAPTUREROUTING_5 (0x00000005U) /* PC4 PC5 PC6 PC7 */
AnnaBridge	171:3a7713b1edbc	130	#define RI_INPUTCAPTUREROUTING_6 (0x00000006U) /* PC8 PC9 PC10 PC11 */
AnnaBridge	171:3a7713b1edbc	131	#define RI_INPUTCAPTUREROUTING_7 (0x00000007U) /* PC12 PC13 PC14 PC15 */
AnnaBridge	171:3a7713b1edbc	132	#define RI_INPUTCAPTUREROUTING_8 (0x00000008U) /* PD0 PD1 PD2 PD3 */
AnnaBridge	171:3a7713b1edbc	133	#define RI_INPUTCAPTUREROUTING_9 (0x00000009U) /* PD4 PD5 PD6 PD7 */
AnnaBridge	171:3a7713b1edbc	134	#define RI_INPUTCAPTUREROUTING_10 (0x0000000AU) /* PD8 PD9 PD10 PD11 */
AnnaBridge	171:3a7713b1edbc	135	#define RI_INPUTCAPTUREROUTING_11 (0x0000000BU) /* PD12 PD13 PD14 PD15 */
AnnaBridge	171:3a7713b1edbc	136	#define RI_INPUTCAPTUREROUTING_12 (0x0000000CU) /* PE0 PE1 PE2 PE3 */
AnnaBridge	171:3a7713b1edbc	137	#define RI_INPUTCAPTUREROUTING_13 (0x0000000DU) /* PE4 PE5 PE6 PE7 */
AnnaBridge	171:3a7713b1edbc	138	#define RI_INPUTCAPTUREROUTING_14 (0x0000000EU) /* PE8 PE9 PE10 PE11 */
AnnaBridge	171:3a7713b1edbc	139	#define RI_INPUTCAPTUREROUTING_15 (0x0000000FU) /* PE12 PE13 PE14 PE15 */
AnnaBridge	171:3a7713b1edbc	140
AnnaBridge	171:3a7713b1edbc	141	#define IS_RI_INPUTCAPTURE_ROUTING(__ROUTING__) (((__ROUTING__) == RI_INPUTCAPTUREROUTING_0) \|\| \
AnnaBridge	171:3a7713b1edbc	142	((__ROUTING__) == RI_INPUTCAPTUREROUTING_1) \|\| \
AnnaBridge	171:3a7713b1edbc	143	((__ROUTING__) == RI_INPUTCAPTUREROUTING_2) \|\| \
AnnaBridge	171:3a7713b1edbc	144	((__ROUTING__) == RI_INPUTCAPTUREROUTING_3) \|\| \
AnnaBridge	171:3a7713b1edbc	145	((__ROUTING__) == RI_INPUTCAPTUREROUTING_4) \|\| \
AnnaBridge	171:3a7713b1edbc	146	((__ROUTING__) == RI_INPUTCAPTUREROUTING_5) \|\| \
AnnaBridge	171:3a7713b1edbc	147	((__ROUTING__) == RI_INPUTCAPTUREROUTING_6) \|\| \
AnnaBridge	171:3a7713b1edbc	148	((__ROUTING__) == RI_INPUTCAPTUREROUTING_7) \|\| \
AnnaBridge	171:3a7713b1edbc	149	((__ROUTING__) == RI_INPUTCAPTUREROUTING_8) \|\| \
AnnaBridge	171:3a7713b1edbc	150	((__ROUTING__) == RI_INPUTCAPTUREROUTING_9) \|\| \
AnnaBridge	171:3a7713b1edbc	151	((__ROUTING__) == RI_INPUTCAPTUREROUTING_10) \|\| \
AnnaBridge	171:3a7713b1edbc	152	((__ROUTING__) == RI_INPUTCAPTUREROUTING_11) \|\| \
AnnaBridge	171:3a7713b1edbc	153	((__ROUTING__) == RI_INPUTCAPTUREROUTING_12) \|\| \
AnnaBridge	171:3a7713b1edbc	154	((__ROUTING__) == RI_INPUTCAPTUREROUTING_13) \|\| \
AnnaBridge	171:3a7713b1edbc	155	((__ROUTING__) == RI_INPUTCAPTUREROUTING_14) \|\| \
AnnaBridge	171:3a7713b1edbc	156	((__ROUTING__) == RI_INPUTCAPTUREROUTING_15))
AnnaBridge	171:3a7713b1edbc	157
AnnaBridge	171:3a7713b1edbc	158	/**
AnnaBridge	171:3a7713b1edbc	159	* @}
AnnaBridge	171:3a7713b1edbc	160	*/
AnnaBridge	171:3a7713b1edbc	161
AnnaBridge	171:3a7713b1edbc	162	/** @defgroup RI_IOSwitch IO Switch
AnnaBridge	171:3a7713b1edbc	163	* @{
AnnaBridge	171:3a7713b1edbc	164	*/
AnnaBridge	171:3a7713b1edbc	165	#define RI_ASCR1_REGISTER (0x80000000U)
AnnaBridge	171:3a7713b1edbc	166	/* ASCR1 I/O switch: bit 31 is set to '1' to indicate that the mask is in ASCR1 register */
AnnaBridge	171:3a7713b1edbc	167	#define RI_IOSWITCH_CH0 ((uint32_t)RI_ASCR1_REGISTER \| RI_ASCR1_CH_0)
AnnaBridge	171:3a7713b1edbc	168	#define RI_IOSWITCH_CH1 ((uint32_t)RI_ASCR1_REGISTER \| RI_ASCR1_CH_1)
AnnaBridge	171:3a7713b1edbc	169	#define RI_IOSWITCH_CH2 ((uint32_t)RI_ASCR1_REGISTER \| RI_ASCR1_CH_2)
AnnaBridge	171:3a7713b1edbc	170	#define RI_IOSWITCH_CH3 ((uint32_t)RI_ASCR1_REGISTER \| RI_ASCR1_CH_3)
AnnaBridge	171:3a7713b1edbc	171	#define RI_IOSWITCH_CH4 ((uint32_t)RI_ASCR1_REGISTER \| RI_ASCR1_CH_4)
AnnaBridge	171:3a7713b1edbc	172	#define RI_IOSWITCH_CH5 ((uint32_t)RI_ASCR1_REGISTER \| RI_ASCR1_CH_5)
AnnaBridge	171:3a7713b1edbc	173	#define RI_IOSWITCH_CH6 ((uint32_t)RI_ASCR1_REGISTER \| RI_ASCR1_CH_6)
AnnaBridge	171:3a7713b1edbc	174	#define RI_IOSWITCH_CH7 ((uint32_t)RI_ASCR1_REGISTER \| RI_ASCR1_CH_7)
AnnaBridge	171:3a7713b1edbc	175	#define RI_IOSWITCH_CH8 ((uint32_t)RI_ASCR1_REGISTER \| RI_ASCR1_CH_8)
AnnaBridge	171:3a7713b1edbc	176	#define RI_IOSWITCH_CH9 ((uint32_t)RI_ASCR1_REGISTER \| RI_ASCR1_CH_9)
AnnaBridge	171:3a7713b1edbc	177	#define RI_IOSWITCH_CH10 ((uint32_t)RI_ASCR1_REGISTER \| RI_ASCR1_CH_10)
AnnaBridge	171:3a7713b1edbc	178	#define RI_IOSWITCH_CH11 ((uint32_t)RI_ASCR1_REGISTER \| RI_ASCR1_CH_11)
AnnaBridge	171:3a7713b1edbc	179	#define RI_IOSWITCH_CH12 ((uint32_t)RI_ASCR1_REGISTER \| RI_ASCR1_CH_12)
AnnaBridge	171:3a7713b1edbc	180	#define RI_IOSWITCH_CH13 ((uint32_t)RI_ASCR1_REGISTER \| RI_ASCR1_CH_13)
AnnaBridge	171:3a7713b1edbc	181	#define RI_IOSWITCH_CH14 ((uint32_t)RI_ASCR1_REGISTER \| RI_ASCR1_CH_14)
AnnaBridge	171:3a7713b1edbc	182	#define RI_IOSWITCH_CH15 ((uint32_t)RI_ASCR1_REGISTER \| RI_ASCR1_CH_15)
AnnaBridge	171:3a7713b1edbc	183	#define RI_IOSWITCH_CH18 ((uint32_t)RI_ASCR1_REGISTER \| RI_ASCR1_CH_18)
AnnaBridge	171:3a7713b1edbc	184	#define RI_IOSWITCH_CH19 ((uint32_t)RI_ASCR1_REGISTER \| RI_ASCR1_CH_19)
AnnaBridge	171:3a7713b1edbc	185	#define RI_IOSWITCH_CH20 ((uint32_t)RI_ASCR1_REGISTER \| RI_ASCR1_CH_20)
AnnaBridge	171:3a7713b1edbc	186	#define RI_IOSWITCH_CH21 ((uint32_t)RI_ASCR1_REGISTER \| RI_ASCR1_CH_21)
AnnaBridge	171:3a7713b1edbc	187	#define RI_IOSWITCH_CH22 ((uint32_t)RI_ASCR1_REGISTER \| RI_ASCR1_CH_22)
AnnaBridge	171:3a7713b1edbc	188	#define RI_IOSWITCH_CH23 ((uint32_t)RI_ASCR1_REGISTER \| RI_ASCR1_CH_23)
AnnaBridge	171:3a7713b1edbc	189	#define RI_IOSWITCH_CH24 ((uint32_t)RI_ASCR1_REGISTER \| RI_ASCR1_CH_24)
AnnaBridge	171:3a7713b1edbc	190	#define RI_IOSWITCH_CH25 ((uint32_t)RI_ASCR1_REGISTER \| RI_ASCR1_CH_25)
AnnaBridge	171:3a7713b1edbc	191	#define RI_IOSWITCH_VCOMP ((uint32_t)RI_ASCR1_REGISTER \| RI_ASCR1_VCOMP) /* VCOMP (ADC channel 26) is an internal switch used to connect selected channel to COMP1 non inverting input */
AnnaBridge	171:3a7713b1edbc	192	#if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */
AnnaBridge	171:3a7713b1edbc	193	#define RI_IOSWITCH_CH27 ((uint32_t)RI_ASCR1_REGISTER \| RI_ASCR1_CH_27)
AnnaBridge	171:3a7713b1edbc	194	#define RI_IOSWITCH_CH28 ((uint32_t)RI_ASCR1_REGISTER \| RI_ASCR1_CH_28)
AnnaBridge	171:3a7713b1edbc	195	#define RI_IOSWITCH_CH29 ((uint32_t)RI_ASCR1_REGISTER \| RI_ASCR1_CH_29)
AnnaBridge	171:3a7713b1edbc	196	#define RI_IOSWITCH_CH30 ((uint32_t)RI_ASCR1_REGISTER \| RI_ASCR1_CH_30)
AnnaBridge	171:3a7713b1edbc	197	#define RI_IOSWITCH_CH31 ((uint32_t)RI_ASCR1_REGISTER \| RI_ASCR1_CH_31)
AnnaBridge	171:3a7713b1edbc	198	#endif /* RI_ASCR2_CH1b */
AnnaBridge	171:3a7713b1edbc	199
AnnaBridge	171:3a7713b1edbc	200	/* ASCR2 IO switch: bit 31 is set to '0' to indicate that the mask is in ASCR2 register */
AnnaBridge	171:3a7713b1edbc	201	#define RI_IOSWITCH_GR10_1 ((uint32_t)RI_ASCR2_GR10_1)
AnnaBridge	171:3a7713b1edbc	202	#define RI_IOSWITCH_GR10_2 ((uint32_t)RI_ASCR2_GR10_2)
AnnaBridge	171:3a7713b1edbc	203	#define RI_IOSWITCH_GR10_3 ((uint32_t)RI_ASCR2_GR10_3)
AnnaBridge	171:3a7713b1edbc	204	#define RI_IOSWITCH_GR10_4 ((uint32_t)RI_ASCR2_GR10_4)
AnnaBridge	171:3a7713b1edbc	205	#define RI_IOSWITCH_GR6_1 ((uint32_t)RI_ASCR2_GR6_1)
AnnaBridge	171:3a7713b1edbc	206	#define RI_IOSWITCH_GR6_2 ((uint32_t)RI_ASCR2_GR6_2)
AnnaBridge	171:3a7713b1edbc	207	#define RI_IOSWITCH_GR5_1 ((uint32_t)RI_ASCR2_GR5_1)
AnnaBridge	171:3a7713b1edbc	208	#define RI_IOSWITCH_GR5_2 ((uint32_t)RI_ASCR2_GR5_2)
AnnaBridge	171:3a7713b1edbc	209	#define RI_IOSWITCH_GR5_3 ((uint32_t)RI_ASCR2_GR5_3)
AnnaBridge	171:3a7713b1edbc	210	#define RI_IOSWITCH_GR4_1 ((uint32_t)RI_ASCR2_GR4_1)
AnnaBridge	171:3a7713b1edbc	211	#define RI_IOSWITCH_GR4_2 ((uint32_t)RI_ASCR2_GR4_2)
AnnaBridge	171:3a7713b1edbc	212	#define RI_IOSWITCH_GR4_3 ((uint32_t)RI_ASCR2_GR4_3)
AnnaBridge	171:3a7713b1edbc	213	#if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3, Cat.4 and Cat.5 */
AnnaBridge	171:3a7713b1edbc	214	#define RI_IOSWITCH_CH0b ((uint32_t)RI_ASCR2_CH0b)
AnnaBridge	171:3a7713b1edbc	215	#if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */
AnnaBridge	171:3a7713b1edbc	216	#define RI_IOSWITCH_CH1b ((uint32_t)RI_ASCR2_CH1b)
AnnaBridge	171:3a7713b1edbc	217	#define RI_IOSWITCH_CH2b ((uint32_t)RI_ASCR2_CH2b)
AnnaBridge	171:3a7713b1edbc	218	#define RI_IOSWITCH_CH3b ((uint32_t)RI_ASCR2_CH3b)
AnnaBridge	171:3a7713b1edbc	219	#define RI_IOSWITCH_CH6b ((uint32_t)RI_ASCR2_CH6b)
AnnaBridge	171:3a7713b1edbc	220	#define RI_IOSWITCH_CH7b ((uint32_t)RI_ASCR2_CH7b)
AnnaBridge	171:3a7713b1edbc	221	#define RI_IOSWITCH_CH8b ((uint32_t)RI_ASCR2_CH8b)
AnnaBridge	171:3a7713b1edbc	222	#define RI_IOSWITCH_CH9b ((uint32_t)RI_ASCR2_CH9b)
AnnaBridge	171:3a7713b1edbc	223	#define RI_IOSWITCH_CH10b ((uint32_t)RI_ASCR2_CH10b)
AnnaBridge	171:3a7713b1edbc	224	#define RI_IOSWITCH_CH11b ((uint32_t)RI_ASCR2_CH11b)
AnnaBridge	171:3a7713b1edbc	225	#define RI_IOSWITCH_CH12b ((uint32_t)RI_ASCR2_CH12b)
AnnaBridge	171:3a7713b1edbc	226	#endif /* RI_ASCR2_CH1b */
AnnaBridge	171:3a7713b1edbc	227	#define RI_IOSWITCH_GR6_3 ((uint32_t)RI_ASCR2_GR6_3)
AnnaBridge	171:3a7713b1edbc	228	#define RI_IOSWITCH_GR6_4 ((uint32_t)RI_ASCR2_GR6_4)
AnnaBridge	171:3a7713b1edbc	229	#endif /* RI_ASCR2_CH0b */
AnnaBridge	171:3a7713b1edbc	230
AnnaBridge	171:3a7713b1edbc	231
AnnaBridge	171:3a7713b1edbc	232	#if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */
AnnaBridge	171:3a7713b1edbc	233
AnnaBridge	171:3a7713b1edbc	234	#define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH1) \|\| \
AnnaBridge	171:3a7713b1edbc	235	((__IOSWITCH__) == RI_IOSWITCH_CH2) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH3) \|\| \
AnnaBridge	171:3a7713b1edbc	236	((__IOSWITCH__) == RI_IOSWITCH_CH4) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH5) \|\| \
AnnaBridge	171:3a7713b1edbc	237	((__IOSWITCH__) == RI_IOSWITCH_CH6) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH7) \|\| \
AnnaBridge	171:3a7713b1edbc	238	((__IOSWITCH__) == RI_IOSWITCH_CH8) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH9) \|\| \
AnnaBridge	171:3a7713b1edbc	239	((__IOSWITCH__) == RI_IOSWITCH_CH10) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH11) \|\| \
AnnaBridge	171:3a7713b1edbc	240	((__IOSWITCH__) == RI_IOSWITCH_CH12) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH13) \|\| \
AnnaBridge	171:3a7713b1edbc	241	((__IOSWITCH__) == RI_IOSWITCH_CH14) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH15) \|\| \
AnnaBridge	171:3a7713b1edbc	242	((__IOSWITCH__) == RI_IOSWITCH_CH18) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH19) \|\| \
AnnaBridge	171:3a7713b1edbc	243	((__IOSWITCH__) == RI_IOSWITCH_CH20) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH21) \|\| \
AnnaBridge	171:3a7713b1edbc	244	((__IOSWITCH__) == RI_IOSWITCH_CH22) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH23) \|\| \
AnnaBridge	171:3a7713b1edbc	245	((__IOSWITCH__) == RI_IOSWITCH_CH24) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH25) \|\| \
AnnaBridge	171:3a7713b1edbc	246	((__IOSWITCH__) == RI_IOSWITCH_VCOMP) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH27) \|\| \
AnnaBridge	171:3a7713b1edbc	247	((__IOSWITCH__) == RI_IOSWITCH_CH28) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH29) \|\| \
AnnaBridge	171:3a7713b1edbc	248	((__IOSWITCH__) == RI_IOSWITCH_CH30) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH31) \|\| \
AnnaBridge	171:3a7713b1edbc	249	((__IOSWITCH__) == RI_IOSWITCH_GR10_1) \|\| ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) \|\| \
AnnaBridge	171:3a7713b1edbc	250	((__IOSWITCH__) == RI_IOSWITCH_GR10_3) \|\| ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) \|\| \
AnnaBridge	171:3a7713b1edbc	251	((__IOSWITCH__) == RI_IOSWITCH_GR6_1) \|\| ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) \|\| \
AnnaBridge	171:3a7713b1edbc	252	((__IOSWITCH__) == RI_IOSWITCH_GR6_3) \|\| ((__IOSWITCH__) == RI_IOSWITCH_GR6_4) \|\| \
AnnaBridge	171:3a7713b1edbc	253	((__IOSWITCH__) == RI_IOSWITCH_GR5_1) \|\| ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) \|\| \
AnnaBridge	171:3a7713b1edbc	254	((__IOSWITCH__) == RI_IOSWITCH_GR5_3) \|\| ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) \|\| \
AnnaBridge	171:3a7713b1edbc	255	((__IOSWITCH__) == RI_IOSWITCH_GR4_2) \|\| ((__IOSWITCH__) == RI_IOSWITCH_GR4_3) \|\| \
AnnaBridge	171:3a7713b1edbc	256	((__IOSWITCH__) == RI_IOSWITCH_CH0b) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH1b) \|\| \
AnnaBridge	171:3a7713b1edbc	257	((__IOSWITCH__) == RI_IOSWITCH_CH2b) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH3b) \|\| \
AnnaBridge	171:3a7713b1edbc	258	((__IOSWITCH__) == RI_IOSWITCH_CH6b) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH7b) \|\| \
AnnaBridge	171:3a7713b1edbc	259	((__IOSWITCH__) == RI_IOSWITCH_CH8b) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH9b) \|\| \
AnnaBridge	171:3a7713b1edbc	260	((__IOSWITCH__) == RI_IOSWITCH_CH10b) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH11b) \|\| \
AnnaBridge	171:3a7713b1edbc	261	((__IOSWITCH__) == RI_IOSWITCH_CH12b))
AnnaBridge	171:3a7713b1edbc	262
AnnaBridge	171:3a7713b1edbc	263	#else /* !RI_ASCR2_CH1b */
AnnaBridge	171:3a7713b1edbc	264
AnnaBridge	171:3a7713b1edbc	265	#if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3 */
AnnaBridge	171:3a7713b1edbc	266
AnnaBridge	171:3a7713b1edbc	267	#define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH1) \|\| \
AnnaBridge	171:3a7713b1edbc	268	((__IOSWITCH__) == RI_IOSWITCH_CH2) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH3) \|\| \
AnnaBridge	171:3a7713b1edbc	269	((__IOSWITCH__) == RI_IOSWITCH_CH4) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH5) \|\| \
AnnaBridge	171:3a7713b1edbc	270	((__IOSWITCH__) == RI_IOSWITCH_CH6) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH7) \|\| \
AnnaBridge	171:3a7713b1edbc	271	((__IOSWITCH__) == RI_IOSWITCH_CH8) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH9) \|\| \
AnnaBridge	171:3a7713b1edbc	272	((__IOSWITCH__) == RI_IOSWITCH_CH10) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH11) \|\| \
AnnaBridge	171:3a7713b1edbc	273	((__IOSWITCH__) == RI_IOSWITCH_CH12) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH13) \|\| \
AnnaBridge	171:3a7713b1edbc	274	((__IOSWITCH__) == RI_IOSWITCH_CH14) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH15) \|\| \
AnnaBridge	171:3a7713b1edbc	275	((__IOSWITCH__) == RI_IOSWITCH_CH18) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH19) \|\| \
AnnaBridge	171:3a7713b1edbc	276	((__IOSWITCH__) == RI_IOSWITCH_CH20) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH21) \|\| \
AnnaBridge	171:3a7713b1edbc	277	((__IOSWITCH__) == RI_IOSWITCH_CH22) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH23) \|\| \
AnnaBridge	171:3a7713b1edbc	278	((__IOSWITCH__) == RI_IOSWITCH_CH24) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH25) \|\| \
AnnaBridge	171:3a7713b1edbc	279	((__IOSWITCH__) == RI_IOSWITCH_VCOMP) \|\| ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) \|\| \
AnnaBridge	171:3a7713b1edbc	280	((__IOSWITCH__) == RI_IOSWITCH_GR10_2) \|\| ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) \|\| \
AnnaBridge	171:3a7713b1edbc	281	((__IOSWITCH__) == RI_IOSWITCH_GR10_4) \|\| ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) \|\| \
AnnaBridge	171:3a7713b1edbc	282	((__IOSWITCH__) == RI_IOSWITCH_GR6_2) \|\| ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) \|\| \
AnnaBridge	171:3a7713b1edbc	283	((__IOSWITCH__) == RI_IOSWITCH_GR5_2) \|\| ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) \|\| \
AnnaBridge	171:3a7713b1edbc	284	((__IOSWITCH__) == RI_IOSWITCH_GR4_1) \|\| ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) \|\| \
AnnaBridge	171:3a7713b1edbc	285	((__IOSWITCH__) == RI_IOSWITCH_GR4_3) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH0b))
AnnaBridge	171:3a7713b1edbc	286
AnnaBridge	171:3a7713b1edbc	287	#else /* !RI_ASCR2_CH0b / / STM32L1 devices category Cat.1 and Cat.2 */
AnnaBridge	171:3a7713b1edbc	288
AnnaBridge	171:3a7713b1edbc	289	#define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH1) \|\| \
AnnaBridge	171:3a7713b1edbc	290	((__IOSWITCH__) == RI_IOSWITCH_CH2) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH3) \|\| \
AnnaBridge	171:3a7713b1edbc	291	((__IOSWITCH__) == RI_IOSWITCH_CH4) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH5) \|\| \
AnnaBridge	171:3a7713b1edbc	292	((__IOSWITCH__) == RI_IOSWITCH_CH6) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH7) \|\| \
AnnaBridge	171:3a7713b1edbc	293	((__IOSWITCH__) == RI_IOSWITCH_CH8) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH9) \|\| \
AnnaBridge	171:3a7713b1edbc	294	((__IOSWITCH__) == RI_IOSWITCH_CH10) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH11) \|\| \
AnnaBridge	171:3a7713b1edbc	295	((__IOSWITCH__) == RI_IOSWITCH_CH12) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH13) \|\| \
AnnaBridge	171:3a7713b1edbc	296	((__IOSWITCH__) == RI_IOSWITCH_CH14) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH15) \|\| \
AnnaBridge	171:3a7713b1edbc	297	((__IOSWITCH__) == RI_IOSWITCH_CH18) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH19) \|\| \
AnnaBridge	171:3a7713b1edbc	298	((__IOSWITCH__) == RI_IOSWITCH_CH20) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH21) \|\| \
AnnaBridge	171:3a7713b1edbc	299	((__IOSWITCH__) == RI_IOSWITCH_CH22) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH23) \|\| \
AnnaBridge	171:3a7713b1edbc	300	((__IOSWITCH__) == RI_IOSWITCH_CH24) \|\| ((__IOSWITCH__) == RI_IOSWITCH_CH25) \|\| \
AnnaBridge	171:3a7713b1edbc	301	((__IOSWITCH__) == RI_IOSWITCH_VCOMP) \|\| ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) \|\| \
AnnaBridge	171:3a7713b1edbc	302	((__IOSWITCH__) == RI_IOSWITCH_GR10_2) \|\| ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) \|\| \
AnnaBridge	171:3a7713b1edbc	303	((__IOSWITCH__) == RI_IOSWITCH_GR10_4) \|\| ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) \|\| \
AnnaBridge	171:3a7713b1edbc	304	((__IOSWITCH__) == RI_IOSWITCH_GR6_2) \|\| ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) \|\| \
AnnaBridge	171:3a7713b1edbc	305	((__IOSWITCH__) == RI_IOSWITCH_GR5_2) \|\| ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) \|\| \
AnnaBridge	171:3a7713b1edbc	306	((__IOSWITCH__) == RI_IOSWITCH_GR4_1) \|\| ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) \|\| \
AnnaBridge	171:3a7713b1edbc	307	((__IOSWITCH__) == RI_IOSWITCH_GR4_3))
AnnaBridge	171:3a7713b1edbc	308
AnnaBridge	171:3a7713b1edbc	309	#endif /* RI_ASCR2_CH0b */
AnnaBridge	171:3a7713b1edbc	310	#endif /* RI_ASCR2_CH1b */
AnnaBridge	171:3a7713b1edbc	311
AnnaBridge	171:3a7713b1edbc	312	/**
AnnaBridge	171:3a7713b1edbc	313	* @}
AnnaBridge	171:3a7713b1edbc	314	*/
AnnaBridge	171:3a7713b1edbc	315
AnnaBridge	171:3a7713b1edbc	316	/** @defgroup RI_Pin PIN define
AnnaBridge	171:3a7713b1edbc	317	* @{
AnnaBridge	171:3a7713b1edbc	318	*/
AnnaBridge	171:3a7713b1edbc	319	#define RI_PIN_0 ((uint16_t)0x0001) /!< Pin 0 selected /
AnnaBridge	171:3a7713b1edbc	320	#define RI_PIN_1 ((uint16_t)0x0002) /!< Pin 1 selected /
AnnaBridge	171:3a7713b1edbc	321	#define RI_PIN_2 ((uint16_t)0x0004) /!< Pin 2 selected /
AnnaBridge	171:3a7713b1edbc	322	#define RI_PIN_3 ((uint16_t)0x0008) /!< Pin 3 selected /
AnnaBridge	171:3a7713b1edbc	323	#define RI_PIN_4 ((uint16_t)0x0010) /!< Pin 4 selected /
AnnaBridge	171:3a7713b1edbc	324	#define RI_PIN_5 ((uint16_t)0x0020) /!< Pin 5 selected /
AnnaBridge	171:3a7713b1edbc	325	#define RI_PIN_6 ((uint16_t)0x0040) /!< Pin 6 selected /
AnnaBridge	171:3a7713b1edbc	326	#define RI_PIN_7 ((uint16_t)0x0080) /!< Pin 7 selected /
AnnaBridge	171:3a7713b1edbc	327	#define RI_PIN_8 ((uint16_t)0x0100) /!< Pin 8 selected /
AnnaBridge	171:3a7713b1edbc	328	#define RI_PIN_9 ((uint16_t)0x0200) /!< Pin 9 selected /
AnnaBridge	171:3a7713b1edbc	329	#define RI_PIN_10 ((uint16_t)0x0400) /!< Pin 10 selected /
AnnaBridge	171:3a7713b1edbc	330	#define RI_PIN_11 ((uint16_t)0x0800) /!< Pin 11 selected /
AnnaBridge	171:3a7713b1edbc	331	#define RI_PIN_12 ((uint16_t)0x1000) /!< Pin 12 selected /
AnnaBridge	171:3a7713b1edbc	332	#define RI_PIN_13 ((uint16_t)0x2000) /!< Pin 13 selected /
AnnaBridge	171:3a7713b1edbc	333	#define RI_PIN_14 ((uint16_t)0x4000) /!< Pin 14 selected /
AnnaBridge	171:3a7713b1edbc	334	#define RI_PIN_15 ((uint16_t)0x8000) /!< Pin 15 selected /
AnnaBridge	171:3a7713b1edbc	335	#define RI_PIN_ALL ((uint16_t)0xFFFF) /!< All pins selected /
AnnaBridge	171:3a7713b1edbc	336
AnnaBridge	171:3a7713b1edbc	337	#define IS_RI_PIN(__PIN__) ((__PIN__) != (uint16_t)0x00)
AnnaBridge	171:3a7713b1edbc	338
AnnaBridge	171:3a7713b1edbc	339	/**
AnnaBridge	171:3a7713b1edbc	340	* @}
AnnaBridge	171:3a7713b1edbc	341	*/
AnnaBridge	171:3a7713b1edbc	342
AnnaBridge	171:3a7713b1edbc	343	/**
AnnaBridge	171:3a7713b1edbc	344	* @}
AnnaBridge	171:3a7713b1edbc	345	*/
AnnaBridge	171:3a7713b1edbc	346
AnnaBridge	171:3a7713b1edbc	347	/**
AnnaBridge	171:3a7713b1edbc	348	* @}
AnnaBridge	171:3a7713b1edbc	349	*/
AnnaBridge	171:3a7713b1edbc	350
AnnaBridge	171:3a7713b1edbc	351	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	352
AnnaBridge	171:3a7713b1edbc	353	/** @defgroup HAL_Exported_Macros HAL Exported Macros
AnnaBridge	171:3a7713b1edbc	354	* @{
AnnaBridge	171:3a7713b1edbc	355	*/
AnnaBridge	171:3a7713b1edbc	356
AnnaBridge	171:3a7713b1edbc	357	/** @defgroup DBGMCU_Macros DBGMCU: Debug MCU
AnnaBridge	171:3a7713b1edbc	358	* @{
AnnaBridge	171:3a7713b1edbc	359	*/
AnnaBridge	171:3a7713b1edbc	360
AnnaBridge	171:3a7713b1edbc	361	/** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode
AnnaBridge	171:3a7713b1edbc	362	* @brief Freeze/Unfreeze Peripherals in Debug mode
AnnaBridge	171:3a7713b1edbc	363	* @{
AnnaBridge	171:3a7713b1edbc	364	*/
AnnaBridge	171:3a7713b1edbc	365
AnnaBridge	171:3a7713b1edbc	366	/**
AnnaBridge	171:3a7713b1edbc	367	* @brief TIM2 Peripherals Debug mode
AnnaBridge	171:3a7713b1edbc	368	*/
AnnaBridge	171:3a7713b1edbc	369	#if defined (DBGMCU_APB1_FZ_DBG_TIM2_STOP)
AnnaBridge	171:3a7713b1edbc	370	#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP)
AnnaBridge	171:3a7713b1edbc	371	#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP)
AnnaBridge	171:3a7713b1edbc	372	#endif
AnnaBridge	171:3a7713b1edbc	373
AnnaBridge	171:3a7713b1edbc	374	/**
AnnaBridge	171:3a7713b1edbc	375	* @brief TIM3 Peripherals Debug mode
AnnaBridge	171:3a7713b1edbc	376	*/
AnnaBridge	171:3a7713b1edbc	377	#if defined (DBGMCU_APB1_FZ_DBG_TIM3_STOP)
AnnaBridge	171:3a7713b1edbc	378	#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP)
AnnaBridge	171:3a7713b1edbc	379	#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP)
AnnaBridge	171:3a7713b1edbc	380	#endif
AnnaBridge	171:3a7713b1edbc	381
AnnaBridge	171:3a7713b1edbc	382	/**
AnnaBridge	171:3a7713b1edbc	383	* @brief TIM4 Peripherals Debug mode
AnnaBridge	171:3a7713b1edbc	384	*/
AnnaBridge	171:3a7713b1edbc	385	#if defined (DBGMCU_APB1_FZ_DBG_TIM4_STOP)
AnnaBridge	171:3a7713b1edbc	386	#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP)
AnnaBridge	171:3a7713b1edbc	387	#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP)
AnnaBridge	171:3a7713b1edbc	388	#endif
AnnaBridge	171:3a7713b1edbc	389
AnnaBridge	171:3a7713b1edbc	390	/**
AnnaBridge	171:3a7713b1edbc	391	* @brief TIM5 Peripherals Debug mode
AnnaBridge	171:3a7713b1edbc	392	*/
AnnaBridge	171:3a7713b1edbc	393	#if defined (DBGMCU_APB1_FZ_DBG_TIM5_STOP)
AnnaBridge	171:3a7713b1edbc	394	#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP)
AnnaBridge	171:3a7713b1edbc	395	#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP)
AnnaBridge	171:3a7713b1edbc	396	#endif
AnnaBridge	171:3a7713b1edbc	397
AnnaBridge	171:3a7713b1edbc	398	/**
AnnaBridge	171:3a7713b1edbc	399	* @brief TIM6 Peripherals Debug mode
AnnaBridge	171:3a7713b1edbc	400	*/
AnnaBridge	171:3a7713b1edbc	401	#if defined (DBGMCU_APB1_FZ_DBG_TIM6_STOP)
AnnaBridge	171:3a7713b1edbc	402	#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
AnnaBridge	171:3a7713b1edbc	403	#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
AnnaBridge	171:3a7713b1edbc	404	#endif
AnnaBridge	171:3a7713b1edbc	405
AnnaBridge	171:3a7713b1edbc	406	/**
AnnaBridge	171:3a7713b1edbc	407	* @brief TIM7 Peripherals Debug mode
AnnaBridge	171:3a7713b1edbc	408	*/
AnnaBridge	171:3a7713b1edbc	409	#if defined (DBGMCU_APB1_FZ_DBG_TIM7_STOP)
AnnaBridge	171:3a7713b1edbc	410	#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
AnnaBridge	171:3a7713b1edbc	411	#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
AnnaBridge	171:3a7713b1edbc	412	#endif
AnnaBridge	171:3a7713b1edbc	413
AnnaBridge	171:3a7713b1edbc	414	/**
AnnaBridge	171:3a7713b1edbc	415	* @brief RTC Peripherals Debug mode
AnnaBridge	171:3a7713b1edbc	416	*/
AnnaBridge	171:3a7713b1edbc	417	#if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP)
AnnaBridge	171:3a7713b1edbc	418	#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)
AnnaBridge	171:3a7713b1edbc	419	#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)
AnnaBridge	171:3a7713b1edbc	420	#endif
AnnaBridge	171:3a7713b1edbc	421
AnnaBridge	171:3a7713b1edbc	422	/**
AnnaBridge	171:3a7713b1edbc	423	* @brief WWDG Peripherals Debug mode
AnnaBridge	171:3a7713b1edbc	424	*/
AnnaBridge	171:3a7713b1edbc	425	#if defined (DBGMCU_APB1_FZ_DBG_WWDG_STOP)
AnnaBridge	171:3a7713b1edbc	426	#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)
AnnaBridge	171:3a7713b1edbc	427	#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)
AnnaBridge	171:3a7713b1edbc	428	#endif
AnnaBridge	171:3a7713b1edbc	429
AnnaBridge	171:3a7713b1edbc	430	/**
AnnaBridge	171:3a7713b1edbc	431	* @brief IWDG Peripherals Debug mode
AnnaBridge	171:3a7713b1edbc	432	*/
AnnaBridge	171:3a7713b1edbc	433	#if defined (DBGMCU_APB1_FZ_DBG_IWDG_STOP)
AnnaBridge	171:3a7713b1edbc	434	#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)
AnnaBridge	171:3a7713b1edbc	435	#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)
AnnaBridge	171:3a7713b1edbc	436	#endif
AnnaBridge	171:3a7713b1edbc	437
AnnaBridge	171:3a7713b1edbc	438	/**
AnnaBridge	171:3a7713b1edbc	439	* @brief I2C1 Peripherals Debug mode
AnnaBridge	171:3a7713b1edbc	440	*/
AnnaBridge	171:3a7713b1edbc	441	#if defined (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
AnnaBridge	171:3a7713b1edbc	442	#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
AnnaBridge	171:3a7713b1edbc	443	#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
AnnaBridge	171:3a7713b1edbc	444	#endif
AnnaBridge	171:3a7713b1edbc	445
AnnaBridge	171:3a7713b1edbc	446	/**
AnnaBridge	171:3a7713b1edbc	447	* @brief I2C2 Peripherals Debug mode
AnnaBridge	171:3a7713b1edbc	448	*/
AnnaBridge	171:3a7713b1edbc	449	#if defined (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
AnnaBridge	171:3a7713b1edbc	450	#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
AnnaBridge	171:3a7713b1edbc	451	#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
AnnaBridge	171:3a7713b1edbc	452	#endif
AnnaBridge	171:3a7713b1edbc	453
AnnaBridge	171:3a7713b1edbc	454	/**
AnnaBridge	171:3a7713b1edbc	455	* @brief TIM9 Peripherals Debug mode
AnnaBridge	171:3a7713b1edbc	456	*/
AnnaBridge	171:3a7713b1edbc	457	#if defined (DBGMCU_APB2_FZ_DBG_TIM9_STOP)
AnnaBridge	171:3a7713b1edbc	458	#define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP)
AnnaBridge	171:3a7713b1edbc	459	#define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP)
AnnaBridge	171:3a7713b1edbc	460	#endif
AnnaBridge	171:3a7713b1edbc	461
AnnaBridge	171:3a7713b1edbc	462	/**
AnnaBridge	171:3a7713b1edbc	463	* @brief TIM10 Peripherals Debug mode
AnnaBridge	171:3a7713b1edbc	464	*/
AnnaBridge	171:3a7713b1edbc	465	#if defined (DBGMCU_APB2_FZ_DBG_TIM10_STOP)
AnnaBridge	171:3a7713b1edbc	466	#define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP)
AnnaBridge	171:3a7713b1edbc	467	#define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP)
AnnaBridge	171:3a7713b1edbc	468	#endif
AnnaBridge	171:3a7713b1edbc	469
AnnaBridge	171:3a7713b1edbc	470	/**
AnnaBridge	171:3a7713b1edbc	471	* @brief TIM11 Peripherals Debug mode
AnnaBridge	171:3a7713b1edbc	472	*/
AnnaBridge	171:3a7713b1edbc	473	#if defined (DBGMCU_APB2_FZ_DBG_TIM11_STOP)
AnnaBridge	171:3a7713b1edbc	474	#define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP)
AnnaBridge	171:3a7713b1edbc	475	#define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP)
AnnaBridge	171:3a7713b1edbc	476	#endif
AnnaBridge	171:3a7713b1edbc	477
AnnaBridge	171:3a7713b1edbc	478
AnnaBridge	171:3a7713b1edbc	479	/**
AnnaBridge	171:3a7713b1edbc	480	* @}
AnnaBridge	171:3a7713b1edbc	481	*/
AnnaBridge	171:3a7713b1edbc	482
AnnaBridge	171:3a7713b1edbc	483	/**
AnnaBridge	171:3a7713b1edbc	484	* @}
AnnaBridge	171:3a7713b1edbc	485	*/
AnnaBridge	171:3a7713b1edbc	486
AnnaBridge	171:3a7713b1edbc	487	/** @defgroup SYSCFG_Macros SYSCFG: SYStem ConFiG
AnnaBridge	171:3a7713b1edbc	488	* @{
AnnaBridge	171:3a7713b1edbc	489	*/
AnnaBridge	171:3a7713b1edbc	490
AnnaBridge	171:3a7713b1edbc	491	/** @defgroup SYSCFG_VrefInt VREFINT configuration
AnnaBridge	171:3a7713b1edbc	492	* @{
AnnaBridge	171:3a7713b1edbc	493	*/
AnnaBridge	171:3a7713b1edbc	494
AnnaBridge	171:3a7713b1edbc	495	/**
AnnaBridge	171:3a7713b1edbc	496	* @brief Enables or disables the output of internal reference voltage
AnnaBridge	171:3a7713b1edbc	497	* (VREFINT) on I/O pin.
AnnaBridge	171:3a7713b1edbc	498	* The VREFINT output can be routed to any I/O in group 3:
AnnaBridge	171:3a7713b1edbc	499	* - For Cat.1 and Cat.2 devices: CH8 (PB0) or CH9 (PB1).
AnnaBridge	171:3a7713b1edbc	500	* - For Cat.3 devices: CH8 (PB0), CH9 (PB1) or CH0b (PB2).
AnnaBridge	171:3a7713b1edbc	501	* - For Cat.4 and Cat.5 devices: CH8 (PB0), CH9 (PB1), CH0b (PB2),
AnnaBridge	171:3a7713b1edbc	502	* CH1b (PF11) or CH2b (PF12).
AnnaBridge	171:3a7713b1edbc	503	* Note: Comparator peripheral clock must be preliminarility enabled,
AnnaBridge	171:3a7713b1edbc	504	* either in COMP user function "HAL_COMP_MspInit()" (should be
AnnaBridge	171:3a7713b1edbc	505	* done if comparators are used) or by direct clock enable:
AnnaBridge	171:3a7713b1edbc	506	* Refer to macro "__HAL_RCC_COMP_CLK_ENABLE()".
AnnaBridge	171:3a7713b1edbc	507	* Note: In addition with this macro, Vrefint output buffer must be
AnnaBridge	171:3a7713b1edbc	508	* connected to the selected I/O pin. Refer to macro
AnnaBridge	171:3a7713b1edbc	509	* "__HAL_RI_IOSWITCH_CLOSE()".
AnnaBridge	171:3a7713b1edbc	510	* @note ENABLE: Internal reference voltage connected to I/O group 3
AnnaBridge	171:3a7713b1edbc	511	* @note DISABLE: Internal reference voltage disconnected from I/O group 3
AnnaBridge	171:3a7713b1edbc	512	* @retval None
AnnaBridge	171:3a7713b1edbc	513	*/
AnnaBridge	171:3a7713b1edbc	514	#define __HAL_SYSCFG_VREFINT_OUT_ENABLE() SET_BIT(COMP->CSR, COMP_CSR_VREFOUTEN)
AnnaBridge	171:3a7713b1edbc	515	#define __HAL_SYSCFG_VREFINT_OUT_DISABLE() CLEAR_BIT(COMP->CSR, COMP_CSR_VREFOUTEN)
AnnaBridge	171:3a7713b1edbc	516
AnnaBridge	171:3a7713b1edbc	517	/**
AnnaBridge	171:3a7713b1edbc	518	* @}
AnnaBridge	171:3a7713b1edbc	519	*/
AnnaBridge	171:3a7713b1edbc	520
AnnaBridge	171:3a7713b1edbc	521	/** @defgroup SYSCFG_BootModeConfig Boot Mode Configuration
AnnaBridge	171:3a7713b1edbc	522	* @{
AnnaBridge	171:3a7713b1edbc	523	*/
AnnaBridge	171:3a7713b1edbc	524
AnnaBridge	171:3a7713b1edbc	525	/**
AnnaBridge	171:3a7713b1edbc	526	* @brief Main Flash memory mapped at 0x00000000
AnnaBridge	171:3a7713b1edbc	527	*/
AnnaBridge	171:3a7713b1edbc	528	#define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
AnnaBridge	171:3a7713b1edbc	529
AnnaBridge	171:3a7713b1edbc	530	/** @brief System Flash memory mapped at 0x00000000
AnnaBridge	171:3a7713b1edbc	531	*/
AnnaBridge	171:3a7713b1edbc	532	#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)
AnnaBridge	171:3a7713b1edbc	533
AnnaBridge	171:3a7713b1edbc	534	/** @brief Embedded SRAM mapped at 0x00000000
AnnaBridge	171:3a7713b1edbc	535	*/
AnnaBridge	171:3a7713b1edbc	536	#define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0 \| SYSCFG_MEMRMP_MEM_MODE_1)
AnnaBridge	171:3a7713b1edbc	537
AnnaBridge	171:3a7713b1edbc	538	#if defined(FSMC_R_BASE)
AnnaBridge	171:3a7713b1edbc	539	/** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
AnnaBridge	171:3a7713b1edbc	540	*/
AnnaBridge	171:3a7713b1edbc	541	#define __HAL_SYSCFG_REMAPMEMORY_FSMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)
AnnaBridge	171:3a7713b1edbc	542
AnnaBridge	171:3a7713b1edbc	543	#endif /* FSMC_R_BASE */
AnnaBridge	171:3a7713b1edbc	544
AnnaBridge	171:3a7713b1edbc	545	/**
AnnaBridge	171:3a7713b1edbc	546	* @brief Returns the boot mode as configured by user.
AnnaBridge	171:3a7713b1edbc	547	* @retval The boot mode as configured by user. The returned value can be one
AnnaBridge	171:3a7713b1edbc	548	* of the following values:
AnnaBridge	171:3a7713b1edbc	549	* @arg SYSCFG_BOOT_MAINFLASH
AnnaBridge	171:3a7713b1edbc	550	* @arg SYSCFG_BOOT_SYSTEMFLASH
AnnaBridge	171:3a7713b1edbc	551	* @arg SYSCFG_BOOT_FSMC (available only for STM32L151xD, STM32L152xD & STM32L162xD)
AnnaBridge	171:3a7713b1edbc	552	* @arg SYSCFG_BOOT_SRAM
AnnaBridge	171:3a7713b1edbc	553	*/
AnnaBridge	171:3a7713b1edbc	554	#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BOOT_MODE)
AnnaBridge	171:3a7713b1edbc	555
AnnaBridge	171:3a7713b1edbc	556	/**
AnnaBridge	171:3a7713b1edbc	557	* @}
AnnaBridge	171:3a7713b1edbc	558	*/
AnnaBridge	171:3a7713b1edbc	559
AnnaBridge	171:3a7713b1edbc	560	/** @defgroup SYSCFG_USBConfig USB DP line Configuration
AnnaBridge	171:3a7713b1edbc	561	* @{
AnnaBridge	171:3a7713b1edbc	562	*/
AnnaBridge	171:3a7713b1edbc	563
AnnaBridge	171:3a7713b1edbc	564	/**
AnnaBridge	171:3a7713b1edbc	565	* @brief Control the internal pull-up on USB DP line.
AnnaBridge	171:3a7713b1edbc	566	*/
AnnaBridge	171:3a7713b1edbc	567	#define __HAL_SYSCFG_USBPULLUP_ENABLE() SET_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU)
AnnaBridge	171:3a7713b1edbc	568
AnnaBridge	171:3a7713b1edbc	569	#define __HAL_SYSCFG_USBPULLUP_DISABLE() CLEAR_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU)
AnnaBridge	171:3a7713b1edbc	570
AnnaBridge	171:3a7713b1edbc	571	/**
AnnaBridge	171:3a7713b1edbc	572	* @}
AnnaBridge	171:3a7713b1edbc	573	*/
AnnaBridge	171:3a7713b1edbc	574
AnnaBridge	171:3a7713b1edbc	575	/**
AnnaBridge	171:3a7713b1edbc	576	* @}
AnnaBridge	171:3a7713b1edbc	577	*/
AnnaBridge	171:3a7713b1edbc	578
AnnaBridge	171:3a7713b1edbc	579	/** @defgroup RI_Macris RI: Routing Interface
AnnaBridge	171:3a7713b1edbc	580	* @{
AnnaBridge	171:3a7713b1edbc	581	*/
AnnaBridge	171:3a7713b1edbc	582
AnnaBridge	171:3a7713b1edbc	583	/** @defgroup RI_InputCaputureConfig Input Capture configuration
AnnaBridge	171:3a7713b1edbc	584	* @{
AnnaBridge	171:3a7713b1edbc	585	*/
AnnaBridge	171:3a7713b1edbc	586
AnnaBridge	171:3a7713b1edbc	587	/**
AnnaBridge	171:3a7713b1edbc	588	* @brief Configures the routing interface to map Input Capture 1 of TIMx to a selected I/O pin.
AnnaBridge	171:3a7713b1edbc	589	* @param __TIMSELECT__: Timer select.
AnnaBridge	171:3a7713b1edbc	590	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	591	* @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
AnnaBridge	171:3a7713b1edbc	592	* @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
AnnaBridge	171:3a7713b1edbc	593	* @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
AnnaBridge	171:3a7713b1edbc	594	* @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
AnnaBridge	171:3a7713b1edbc	595	* @param __INPUT__: selects which pin to be routed to Input Capture.
AnnaBridge	171:3a7713b1edbc	596	* This parameter must be a value of @ref RI_InputCaptureRouting
AnnaBridge	171:3a7713b1edbc	597	* e.g.
AnnaBridge	171:3a7713b1edbc	598	* __HAL_RI_REMAP_INPUTCAPTURE1(TIM_SELECT_TIM2, RI_INPUTCAPTUREROUTING_1)
AnnaBridge	171:3a7713b1edbc	599	* allows routing of Input capture IC1 of TIM2 to PA4.
AnnaBridge	171:3a7713b1edbc	600	* For details about correspondence between RI_INPUTCAPTUREROUTING_x
AnnaBridge	171:3a7713b1edbc	601	* and I/O pins refer to the parameters' description in the header file
AnnaBridge	171:3a7713b1edbc	602	* or refer to the product reference manual.
AnnaBridge	171:3a7713b1edbc	603	* @note Input capture selection bits are not reset by this function.
AnnaBridge	171:3a7713b1edbc	604	* To reset input capture selection bits, use SYSCFG_RIDeInit() function.
AnnaBridge	171:3a7713b1edbc	605	* @note The I/O should be configured in alternate function mode (AF14) using
AnnaBridge	171:3a7713b1edbc	606	* GPIO_PinAFConfig() function.
AnnaBridge	171:3a7713b1edbc	607	* @retval None.
AnnaBridge	171:3a7713b1edbc	608	*/
AnnaBridge	171:3a7713b1edbc	609	#define __HAL_RI_REMAP_INPUTCAPTURE1(__TIMSELECT__, __INPUT__) \
AnnaBridge	171:3a7713b1edbc	610	do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
AnnaBridge	171:3a7713b1edbc	611	assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
AnnaBridge	171:3a7713b1edbc	612	MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
AnnaBridge	171:3a7713b1edbc	613	SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC1); \
AnnaBridge	171:3a7713b1edbc	614	MODIFY_REG(RI->ICR, RI_ICR_IC1OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC1OS)); \
AnnaBridge	171:3a7713b1edbc	615	}while(0)
AnnaBridge	171:3a7713b1edbc	616
AnnaBridge	171:3a7713b1edbc	617	/**
AnnaBridge	171:3a7713b1edbc	618	* @brief Configures the routing interface to map Input Capture 2 of TIMx to a selected I/O pin.
AnnaBridge	171:3a7713b1edbc	619	* @param __TIMSELECT__: Timer select.
AnnaBridge	171:3a7713b1edbc	620	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	621	* @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
AnnaBridge	171:3a7713b1edbc	622	* @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
AnnaBridge	171:3a7713b1edbc	623	* @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
AnnaBridge	171:3a7713b1edbc	624	* @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
AnnaBridge	171:3a7713b1edbc	625	* @param __INPUT__: selects which pin to be routed to Input Capture.
AnnaBridge	171:3a7713b1edbc	626	* This parameter must be a value of @ref RI_InputCaptureRouting
AnnaBridge	171:3a7713b1edbc	627	* @retval None.
AnnaBridge	171:3a7713b1edbc	628	*/
AnnaBridge	171:3a7713b1edbc	629	#define __HAL_RI_REMAP_INPUTCAPTURE2(__TIMSELECT__, __INPUT__) \
AnnaBridge	171:3a7713b1edbc	630	do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
AnnaBridge	171:3a7713b1edbc	631	assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
AnnaBridge	171:3a7713b1edbc	632	MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
AnnaBridge	171:3a7713b1edbc	633	SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC2); \
AnnaBridge	171:3a7713b1edbc	634	MODIFY_REG(RI->ICR, RI_ICR_IC2OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC2OS)); \
AnnaBridge	171:3a7713b1edbc	635	}while(0)
AnnaBridge	171:3a7713b1edbc	636
AnnaBridge	171:3a7713b1edbc	637	/**
AnnaBridge	171:3a7713b1edbc	638	* @brief Configures the routing interface to map Input Capture 3 of TIMx to a selected I/O pin.
AnnaBridge	171:3a7713b1edbc	639	* @param __TIMSELECT__: Timer select.
AnnaBridge	171:3a7713b1edbc	640	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	641	* @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
AnnaBridge	171:3a7713b1edbc	642	* @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
AnnaBridge	171:3a7713b1edbc	643	* @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
AnnaBridge	171:3a7713b1edbc	644	* @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
AnnaBridge	171:3a7713b1edbc	645	* @param __INPUT__: selects which pin to be routed to Input Capture.
AnnaBridge	171:3a7713b1edbc	646	* This parameter must be a value of @ref RI_InputCaptureRouting
AnnaBridge	171:3a7713b1edbc	647	* @retval None.
AnnaBridge	171:3a7713b1edbc	648	*/
AnnaBridge	171:3a7713b1edbc	649	#define __HAL_RI_REMAP_INPUTCAPTURE3(__TIMSELECT__, __INPUT__) \
AnnaBridge	171:3a7713b1edbc	650	do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
AnnaBridge	171:3a7713b1edbc	651	assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
AnnaBridge	171:3a7713b1edbc	652	MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
AnnaBridge	171:3a7713b1edbc	653	SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC3); \
AnnaBridge	171:3a7713b1edbc	654	MODIFY_REG(RI->ICR, RI_ICR_IC3OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC3OS)); \
AnnaBridge	171:3a7713b1edbc	655	}while(0)
AnnaBridge	171:3a7713b1edbc	656
AnnaBridge	171:3a7713b1edbc	657	/**
AnnaBridge	171:3a7713b1edbc	658	* @brief Configures the routing interface to map Input Capture 4 of TIMx to a selected I/O pin.
AnnaBridge	171:3a7713b1edbc	659	* @param __TIMSELECT__: Timer select.
AnnaBridge	171:3a7713b1edbc	660	* This parameter can be one of the following values:
AnnaBridge	171:3a7713b1edbc	661	* @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
AnnaBridge	171:3a7713b1edbc	662	* @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
AnnaBridge	171:3a7713b1edbc	663	* @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
AnnaBridge	171:3a7713b1edbc	664	* @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
AnnaBridge	171:3a7713b1edbc	665	* @param __INPUT__: selects which pin to be routed to Input Capture.
AnnaBridge	171:3a7713b1edbc	666	* This parameter must be a value of @ref RI_InputCaptureRouting
AnnaBridge	171:3a7713b1edbc	667	* @retval None.
AnnaBridge	171:3a7713b1edbc	668	*/
AnnaBridge	171:3a7713b1edbc	669	#define __HAL_RI_REMAP_INPUTCAPTURE4(__TIMSELECT__, __INPUT__) \
AnnaBridge	171:3a7713b1edbc	670	do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
AnnaBridge	171:3a7713b1edbc	671	assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
AnnaBridge	171:3a7713b1edbc	672	MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
AnnaBridge	171:3a7713b1edbc	673	SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC4); \
AnnaBridge	171:3a7713b1edbc	674	MODIFY_REG(RI->ICR, RI_ICR_IC4OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC4OS)); \
AnnaBridge	171:3a7713b1edbc	675	}while(0)
AnnaBridge	171:3a7713b1edbc	676
AnnaBridge	171:3a7713b1edbc	677	/**
AnnaBridge	171:3a7713b1edbc	678	* @}
AnnaBridge	171:3a7713b1edbc	679	*/
AnnaBridge	171:3a7713b1edbc	680
AnnaBridge	171:3a7713b1edbc	681	/** @defgroup RI_SwitchControlConfig Switch Control configuration
AnnaBridge	171:3a7713b1edbc	682	* @{
AnnaBridge	171:3a7713b1edbc	683	*/
AnnaBridge	171:3a7713b1edbc	684
AnnaBridge	171:3a7713b1edbc	685	/**
AnnaBridge	171:3a7713b1edbc	686	* @brief Enable or disable the switch control mode.
AnnaBridge	171:3a7713b1edbc	687	* @note ENABLE: ADC analog switches closed if the corresponding
AnnaBridge	171:3a7713b1edbc	688	* I/O switch is also closed.
AnnaBridge	171:3a7713b1edbc	689	* When using COMP1, switch control mode must be enabled.
AnnaBridge	171:3a7713b1edbc	690	* @note DISABLE: ADC analog switches open or controlled by the ADC interface.
AnnaBridge	171:3a7713b1edbc	691	* When using the ADC for acquisition, switch control mode
AnnaBridge	171:3a7713b1edbc	692	* must be disabled.
AnnaBridge	171:3a7713b1edbc	693	* @note COMP1 comparator and ADC cannot be used at the same time since
AnnaBridge	171:3a7713b1edbc	694	* they share the ADC switch matrix.
AnnaBridge	171:3a7713b1edbc	695	* @retval None
AnnaBridge	171:3a7713b1edbc	696	*/
AnnaBridge	171:3a7713b1edbc	697	#define __HAL_RI_SWITCHCONTROLMODE_ENABLE() SET_BIT(RI->ASCR1, RI_ASCR1_SCM)
AnnaBridge	171:3a7713b1edbc	698
AnnaBridge	171:3a7713b1edbc	699	#define __HAL_RI_SWITCHCONTROLMODE_DISABLE() CLEAR_BIT(RI->ASCR1, RI_ASCR1_SCM)
AnnaBridge	171:3a7713b1edbc	700
AnnaBridge	171:3a7713b1edbc	701	/*
AnnaBridge	171:3a7713b1edbc	702	* @brief Close or Open the routing interface Input Output switches.
AnnaBridge	171:3a7713b1edbc	703	* @param __IOSWITCH__: selects the I/O analog switch number.
AnnaBridge	171:3a7713b1edbc	704	* This parameter must be a value of @ref RI_IOSwitch
AnnaBridge	171:3a7713b1edbc	705	* @retval None
AnnaBridge	171:3a7713b1edbc	706	*/
AnnaBridge	171:3a7713b1edbc	707	#define __HAL_RI_IOSWITCH_CLOSE(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \
AnnaBridge	171:3a7713b1edbc	708	if ((__IOSWITCH__) >> 31 != 0 ) \
AnnaBridge	171:3a7713b1edbc	709	{ \
AnnaBridge	171:3a7713b1edbc	710	SET_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \
AnnaBridge	171:3a7713b1edbc	711	} \
AnnaBridge	171:3a7713b1edbc	712	else \
AnnaBridge	171:3a7713b1edbc	713	{ \
AnnaBridge	171:3a7713b1edbc	714	SET_BIT(RI->ASCR2, (__IOSWITCH__)); \
AnnaBridge	171:3a7713b1edbc	715	} \
AnnaBridge	171:3a7713b1edbc	716	}while(0)
AnnaBridge	171:3a7713b1edbc	717
AnnaBridge	171:3a7713b1edbc	718	#define __HAL_RI_IOSWITCH_OPEN(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \
AnnaBridge	171:3a7713b1edbc	719	if ((__IOSWITCH__) >> 31 != 0 ) \
AnnaBridge	171:3a7713b1edbc	720	{ \
AnnaBridge	171:3a7713b1edbc	721	CLEAR_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \
AnnaBridge	171:3a7713b1edbc	722	} \
AnnaBridge	171:3a7713b1edbc	723	else \
AnnaBridge	171:3a7713b1edbc	724	{ \
AnnaBridge	171:3a7713b1edbc	725	CLEAR_BIT(RI->ASCR2, (__IOSWITCH__)); \
AnnaBridge	171:3a7713b1edbc	726	} \
AnnaBridge	171:3a7713b1edbc	727	}while(0)
AnnaBridge	171:3a7713b1edbc	728
AnnaBridge	171:3a7713b1edbc	729	#if defined (COMP_CSR_SW1)
AnnaBridge	171:3a7713b1edbc	730	/**
AnnaBridge	171:3a7713b1edbc	731	* @brief Close or open the internal switch COMP1_SW1.
AnnaBridge	171:3a7713b1edbc	732	* This switch connects I/O pin PC3 (can be used as ADC channel 13)
AnnaBridge	171:3a7713b1edbc	733	* and OPAMP3 ouput to ADC switch matrix (ADC channel VCOMP, channel
AnnaBridge	171:3a7713b1edbc	734	* 26) and COMP1 non-inverting input.
AnnaBridge	171:3a7713b1edbc	735	* Pin PC3 connection depends on another switch setting, refer to
AnnaBridge	171:3a7713b1edbc	736	* macro "__HAL_ADC_CHANNEL_SPEED_FAST()".
AnnaBridge	171:3a7713b1edbc	737	* @retval None.
AnnaBridge	171:3a7713b1edbc	738	*/
AnnaBridge	171:3a7713b1edbc	739	#define __HAL_RI_SWITCH_COMP1_SW1_CLOSE() SET_BIT(COMP->CSR, COMP_CSR_SW1)
AnnaBridge	171:3a7713b1edbc	740
AnnaBridge	171:3a7713b1edbc	741	#define __HAL_RI_SWITCH_COMP1_SW1_OPEN() CLEAR_BIT(COMP->CSR, COMP_CSR_SW1)
AnnaBridge	171:3a7713b1edbc	742	#endif /* COMP_CSR_SW1 */
AnnaBridge	171:3a7713b1edbc	743
AnnaBridge	171:3a7713b1edbc	744	/**
AnnaBridge	171:3a7713b1edbc	745	* @}
AnnaBridge	171:3a7713b1edbc	746	*/
AnnaBridge	171:3a7713b1edbc	747
AnnaBridge	171:3a7713b1edbc	748	/** @defgroup RI_HystConfig Hysteresis Activation and Deactivation
AnnaBridge	171:3a7713b1edbc	749	* @{
AnnaBridge	171:3a7713b1edbc	750	*/
AnnaBridge	171:3a7713b1edbc	751
AnnaBridge	171:3a7713b1edbc	752	/**
AnnaBridge	171:3a7713b1edbc	753	* @brief Enable or disable Hysteresis of the input schmitt triger of Ports A
AnnaBridge	171:3a7713b1edbc	754	* When the I/Os are programmed in input mode by standard I/O port
AnnaBridge	171:3a7713b1edbc	755	* registers, the Schmitt trigger and the hysteresis are enabled by default.
AnnaBridge	171:3a7713b1edbc	756	* When hysteresis is disabled, it is possible to read the
AnnaBridge	171:3a7713b1edbc	757	* corresponding port with a trigger level of VDDIO/2.
AnnaBridge	171:3a7713b1edbc	758	* @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
AnnaBridge	171:3a7713b1edbc	759	* This parameter must be a value of @ref RI_Pin
AnnaBridge	171:3a7713b1edbc	760	* @retval None
AnnaBridge	171:3a7713b1edbc	761	*/
AnnaBridge	171:3a7713b1edbc	762	#define __HAL_RI_HYSTERIS_PORTA_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
AnnaBridge	171:3a7713b1edbc	763	CLEAR_BIT(RI->HYSCR1, (__IOPIN__)); \
AnnaBridge	171:3a7713b1edbc	764	} while(0)
AnnaBridge	171:3a7713b1edbc	765
AnnaBridge	171:3a7713b1edbc	766	#define __HAL_RI_HYSTERIS_PORTA_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
AnnaBridge	171:3a7713b1edbc	767	SET_BIT(RI->HYSCR1, (__IOPIN__)); \
AnnaBridge	171:3a7713b1edbc	768	} while(0)
AnnaBridge	171:3a7713b1edbc	769
AnnaBridge	171:3a7713b1edbc	770	/**
AnnaBridge	171:3a7713b1edbc	771	* @brief Enable or disable Hysteresis of the input schmitt triger of Ports B
AnnaBridge	171:3a7713b1edbc	772	* When the I/Os are programmed in input mode by standard I/O port
AnnaBridge	171:3a7713b1edbc	773	* registers, the Schmitt trigger and the hysteresis are enabled by default.
AnnaBridge	171:3a7713b1edbc	774	* When hysteresis is disabled, it is possible to read the
AnnaBridge	171:3a7713b1edbc	775	* corresponding port with a trigger level of VDDIO/2.
AnnaBridge	171:3a7713b1edbc	776	* @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
AnnaBridge	171:3a7713b1edbc	777	* This parameter must be a value of @ref RI_Pin
AnnaBridge	171:3a7713b1edbc	778	* @retval None
AnnaBridge	171:3a7713b1edbc	779	*/
AnnaBridge	171:3a7713b1edbc	780	#define __HAL_RI_HYSTERIS_PORTB_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
AnnaBridge	171:3a7713b1edbc	781	CLEAR_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \
AnnaBridge	171:3a7713b1edbc	782	} while(0)
AnnaBridge	171:3a7713b1edbc	783
AnnaBridge	171:3a7713b1edbc	784	#define __HAL_RI_HYSTERIS_PORTB_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
AnnaBridge	171:3a7713b1edbc	785	SET_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \
AnnaBridge	171:3a7713b1edbc	786	} while(0)
AnnaBridge	171:3a7713b1edbc	787
AnnaBridge	171:3a7713b1edbc	788	/**
AnnaBridge	171:3a7713b1edbc	789	* @brief Enable or disable Hysteresis of the input schmitt triger of Ports C
AnnaBridge	171:3a7713b1edbc	790	* When the I/Os are programmed in input mode by standard I/O port
AnnaBridge	171:3a7713b1edbc	791	* registers, the Schmitt trigger and the hysteresis are enabled by default.
AnnaBridge	171:3a7713b1edbc	792	* When hysteresis is disabled, it is possible to read the
AnnaBridge	171:3a7713b1edbc	793	* corresponding port with a trigger level of VDDIO/2.
AnnaBridge	171:3a7713b1edbc	794	* @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
AnnaBridge	171:3a7713b1edbc	795	* This parameter must be a value of @ref RI_Pin
AnnaBridge	171:3a7713b1edbc	796	* @retval None
AnnaBridge	171:3a7713b1edbc	797	*/
AnnaBridge	171:3a7713b1edbc	798	#define __HAL_RI_HYSTERIS_PORTC_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
AnnaBridge	171:3a7713b1edbc	799	CLEAR_BIT(RI->HYSCR2, (__IOPIN__)); \
AnnaBridge	171:3a7713b1edbc	800	} while(0)
AnnaBridge	171:3a7713b1edbc	801
AnnaBridge	171:3a7713b1edbc	802	#define __HAL_RI_HYSTERIS_PORTC_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
AnnaBridge	171:3a7713b1edbc	803	SET_BIT(RI->HYSCR2, (__IOPIN__)); \
AnnaBridge	171:3a7713b1edbc	804	} while(0)
AnnaBridge	171:3a7713b1edbc	805
AnnaBridge	171:3a7713b1edbc	806	/**
AnnaBridge	171:3a7713b1edbc	807	* @brief Enable or disable Hysteresis of the input schmitt triger of Ports D
AnnaBridge	171:3a7713b1edbc	808	* When the I/Os are programmed in input mode by standard I/O port
AnnaBridge	171:3a7713b1edbc	809	* registers, the Schmitt trigger and the hysteresis are enabled by default.
AnnaBridge	171:3a7713b1edbc	810	* When hysteresis is disabled, it is possible to read the
AnnaBridge	171:3a7713b1edbc	811	* corresponding port with a trigger level of VDDIO/2.
AnnaBridge	171:3a7713b1edbc	812	* @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
AnnaBridge	171:3a7713b1edbc	813	* This parameter must be a value of @ref RI_Pin
AnnaBridge	171:3a7713b1edbc	814	* @retval None
AnnaBridge	171:3a7713b1edbc	815	*/
AnnaBridge	171:3a7713b1edbc	816	#define __HAL_RI_HYSTERIS_PORTD_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
AnnaBridge	171:3a7713b1edbc	817	CLEAR_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \
AnnaBridge	171:3a7713b1edbc	818	} while(0)
AnnaBridge	171:3a7713b1edbc	819
AnnaBridge	171:3a7713b1edbc	820	#define __HAL_RI_HYSTERIS_PORTD_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
AnnaBridge	171:3a7713b1edbc	821	SET_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \
AnnaBridge	171:3a7713b1edbc	822	} while(0)
AnnaBridge	171:3a7713b1edbc	823
AnnaBridge	171:3a7713b1edbc	824	#if defined (GPIOE_BASE)
AnnaBridge	171:3a7713b1edbc	825
AnnaBridge	171:3a7713b1edbc	826	/**
AnnaBridge	171:3a7713b1edbc	827	* @brief Enable or disable Hysteresis of the input schmitt triger of Ports E
AnnaBridge	171:3a7713b1edbc	828	* When the I/Os are programmed in input mode by standard I/O port
AnnaBridge	171:3a7713b1edbc	829	* registers, the Schmitt trigger and the hysteresis are enabled by default.
AnnaBridge	171:3a7713b1edbc	830	* When hysteresis is disabled, it is possible to read the
AnnaBridge	171:3a7713b1edbc	831	* corresponding port with a trigger level of VDDIO/2.
AnnaBridge	171:3a7713b1edbc	832	* @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
AnnaBridge	171:3a7713b1edbc	833	* This parameter must be a value of @ref RI_Pin
AnnaBridge	171:3a7713b1edbc	834	* @retval None
AnnaBridge	171:3a7713b1edbc	835	*/
AnnaBridge	171:3a7713b1edbc	836	#define __HAL_RI_HYSTERIS_PORTE_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
AnnaBridge	171:3a7713b1edbc	837	CLEAR_BIT(RI->HYSCR3, (__IOPIN__)); \
AnnaBridge	171:3a7713b1edbc	838	} while(0)
AnnaBridge	171:3a7713b1edbc	839
AnnaBridge	171:3a7713b1edbc	840	#define __HAL_RI_HYSTERIS_PORTE_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
AnnaBridge	171:3a7713b1edbc	841	SET_BIT(RI->HYSCR3, (__IOPIN__)); \
AnnaBridge	171:3a7713b1edbc	842	} while(0)
AnnaBridge	171:3a7713b1edbc	843
AnnaBridge	171:3a7713b1edbc	844	#endif /* GPIOE_BASE */
AnnaBridge	171:3a7713b1edbc	845
AnnaBridge	171:3a7713b1edbc	846	#if defined(GPIOF_BASE) \|\| defined(GPIOG_BASE)
AnnaBridge	171:3a7713b1edbc	847
AnnaBridge	171:3a7713b1edbc	848	/**
AnnaBridge	171:3a7713b1edbc	849	* @brief Enable or disable Hysteresis of the input schmitt triger of Ports F
AnnaBridge	171:3a7713b1edbc	850	* When the I/Os are programmed in input mode by standard I/O port
AnnaBridge	171:3a7713b1edbc	851	* registers, the Schmitt trigger and the hysteresis are enabled by default.
AnnaBridge	171:3a7713b1edbc	852	* When hysteresis is disabled, it is possible to read the
AnnaBridge	171:3a7713b1edbc	853	* corresponding port with a trigger level of VDDIO/2.
AnnaBridge	171:3a7713b1edbc	854	* @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
AnnaBridge	171:3a7713b1edbc	855	* This parameter must be a value of @ref RI_Pin
AnnaBridge	171:3a7713b1edbc	856	* @retval None
AnnaBridge	171:3a7713b1edbc	857	*/
AnnaBridge	171:3a7713b1edbc	858	#define __HAL_RI_HYSTERIS_PORTF_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
AnnaBridge	171:3a7713b1edbc	859	CLEAR_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \
AnnaBridge	171:3a7713b1edbc	860	} while(0)
AnnaBridge	171:3a7713b1edbc	861
AnnaBridge	171:3a7713b1edbc	862	#define __HAL_RI_HYSTERIS_PORTF_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
AnnaBridge	171:3a7713b1edbc	863	SET_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \
AnnaBridge	171:3a7713b1edbc	864	} while(0)
AnnaBridge	171:3a7713b1edbc	865
AnnaBridge	171:3a7713b1edbc	866	/**
AnnaBridge	171:3a7713b1edbc	867	* @brief Enable or disable Hysteresis of the input schmitt triger of Ports G
AnnaBridge	171:3a7713b1edbc	868	* When the I/Os are programmed in input mode by standard I/O port
AnnaBridge	171:3a7713b1edbc	869	* registers, the Schmitt trigger and the hysteresis are enabled by default.
AnnaBridge	171:3a7713b1edbc	870	* When hysteresis is disabled, it is possible to read the
AnnaBridge	171:3a7713b1edbc	871	* corresponding port with a trigger level of VDDIO/2.
AnnaBridge	171:3a7713b1edbc	872	* @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
AnnaBridge	171:3a7713b1edbc	873	* This parameter must be a value of @ref RI_Pin
AnnaBridge	171:3a7713b1edbc	874	* @retval None
AnnaBridge	171:3a7713b1edbc	875	*/
AnnaBridge	171:3a7713b1edbc	876	#define __HAL_RI_HYSTERIS_PORTG_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
AnnaBridge	171:3a7713b1edbc	877	CLEAR_BIT(RI->HYSCR4, (__IOPIN__)); \
AnnaBridge	171:3a7713b1edbc	878	} while(0)
AnnaBridge	171:3a7713b1edbc	879
AnnaBridge	171:3a7713b1edbc	880	#define __HAL_RI_HYSTERIS_PORTG_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
AnnaBridge	171:3a7713b1edbc	881	SET_BIT(RI->HYSCR4, (__IOPIN__)); \
AnnaBridge	171:3a7713b1edbc	882	} while(0)
AnnaBridge	171:3a7713b1edbc	883
AnnaBridge	171:3a7713b1edbc	884	#endif /* GPIOF_BASE \|\| GPIOG_BASE */
AnnaBridge	171:3a7713b1edbc	885
AnnaBridge	171:3a7713b1edbc	886	/**
AnnaBridge	171:3a7713b1edbc	887	* @}
AnnaBridge	171:3a7713b1edbc	888	*/
AnnaBridge	171:3a7713b1edbc	889
AnnaBridge	171:3a7713b1edbc	890	/**
AnnaBridge	171:3a7713b1edbc	891	* @}
AnnaBridge	171:3a7713b1edbc	892	*/
AnnaBridge	171:3a7713b1edbc	893
AnnaBridge	171:3a7713b1edbc	894	/**
AnnaBridge	171:3a7713b1edbc	895	* @}
AnnaBridge	171:3a7713b1edbc	896	*/
AnnaBridge	171:3a7713b1edbc	897
AnnaBridge	171:3a7713b1edbc	898	/* Exported functions --------------------------------------------------------*/
AnnaBridge	171:3a7713b1edbc	899
AnnaBridge	171:3a7713b1edbc	900	/** @addtogroup HAL_Exported_Functions
AnnaBridge	171:3a7713b1edbc	901	* @{
AnnaBridge	171:3a7713b1edbc	902	*/
AnnaBridge	171:3a7713b1edbc	903
AnnaBridge	171:3a7713b1edbc	904	/** @addtogroup HAL_Exported_Functions_Group1
AnnaBridge	171:3a7713b1edbc	905	* @{
AnnaBridge	171:3a7713b1edbc	906	*/
AnnaBridge	171:3a7713b1edbc	907
AnnaBridge	171:3a7713b1edbc	908	/* Initialization and de-initialization functions ******************************/
AnnaBridge	171:3a7713b1edbc	909	HAL_StatusTypeDef HAL_Init(void);
AnnaBridge	171:3a7713b1edbc	910	HAL_StatusTypeDef HAL_DeInit(void);
AnnaBridge	171:3a7713b1edbc	911	void HAL_MspInit(void);
AnnaBridge	171:3a7713b1edbc	912	void HAL_MspDeInit(void);
AnnaBridge	171:3a7713b1edbc	913	HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
AnnaBridge	171:3a7713b1edbc	914
AnnaBridge	171:3a7713b1edbc	915	/**
AnnaBridge	171:3a7713b1edbc	916	* @}
AnnaBridge	171:3a7713b1edbc	917	*/
AnnaBridge	171:3a7713b1edbc	918
AnnaBridge	171:3a7713b1edbc	919	/** @addtogroup HAL_Exported_Functions_Group2
AnnaBridge	171:3a7713b1edbc	920	* @{
AnnaBridge	171:3a7713b1edbc	921	*/
AnnaBridge	171:3a7713b1edbc	922
AnnaBridge	171:3a7713b1edbc	923	/* Peripheral Control functions ************************************************/
AnnaBridge	171:3a7713b1edbc	924	void HAL_IncTick(void);
AnnaBridge	171:3a7713b1edbc	925	void HAL_Delay(__IO uint32_t Delay);
AnnaBridge	171:3a7713b1edbc	926	uint32_t HAL_GetTick(void);
AnnaBridge	171:3a7713b1edbc	927	void HAL_SuspendTick(void);
AnnaBridge	171:3a7713b1edbc	928	void HAL_ResumeTick(void);
AnnaBridge	171:3a7713b1edbc	929	uint32_t HAL_GetHalVersion(void);
AnnaBridge	171:3a7713b1edbc	930	uint32_t HAL_GetREVID(void);
AnnaBridge	171:3a7713b1edbc	931	uint32_t HAL_GetDEVID(void);
AnnaBridge	171:3a7713b1edbc	932	void HAL_DBGMCU_EnableDBGSleepMode(void);
AnnaBridge	171:3a7713b1edbc	933	void HAL_DBGMCU_DisableDBGSleepMode(void);
AnnaBridge	171:3a7713b1edbc	934	void HAL_DBGMCU_EnableDBGStopMode(void);
AnnaBridge	171:3a7713b1edbc	935	void HAL_DBGMCU_DisableDBGStopMode(void);
AnnaBridge	171:3a7713b1edbc	936	void HAL_DBGMCU_EnableDBGStandbyMode(void);
AnnaBridge	171:3a7713b1edbc	937	void HAL_DBGMCU_DisableDBGStandbyMode(void);
AnnaBridge	171:3a7713b1edbc	938
AnnaBridge	171:3a7713b1edbc	939	/**
AnnaBridge	171:3a7713b1edbc	940	* @}
AnnaBridge	171:3a7713b1edbc	941	*/
AnnaBridge	171:3a7713b1edbc	942
AnnaBridge	171:3a7713b1edbc	943	/**
AnnaBridge	171:3a7713b1edbc	944	* @}
AnnaBridge	171:3a7713b1edbc	945	*/
AnnaBridge	171:3a7713b1edbc	946
AnnaBridge	171:3a7713b1edbc	947
AnnaBridge	171:3a7713b1edbc	948	/**
AnnaBridge	171:3a7713b1edbc	949	* @}
AnnaBridge	171:3a7713b1edbc	950	*/
AnnaBridge	171:3a7713b1edbc	951
AnnaBridge	171:3a7713b1edbc	952	/**
AnnaBridge	171:3a7713b1edbc	953	* @}
AnnaBridge	171:3a7713b1edbc	954	*/
AnnaBridge	171:3a7713b1edbc	955
AnnaBridge	171:3a7713b1edbc	956	#ifdef __cplusplus
AnnaBridge	171:3a7713b1edbc	957	}
AnnaBridge	171:3a7713b1edbc	958	#endif
AnnaBridge	171:3a7713b1edbc	959
AnnaBridge	171:3a7713b1edbc	960	#endif /* __STM32L1xx_HAL_H */
AnnaBridge	171:3a7713b1edbc	961
AnnaBridge	171:3a7713b1edbc	962	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/