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TARGET_MAX32630FTHR/TOOLCHAIN_IAR/wdt_regs.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 171:3a7713b1edbc | 1 | /** |
AnnaBridge | 171:3a7713b1edbc | 2 | * @file |
AnnaBridge | 171:3a7713b1edbc | 3 | * @brief Type definitions for the Watchdog Timer Peripheral |
AnnaBridge | 171:3a7713b1edbc | 4 | * |
AnnaBridge | 171:3a7713b1edbc | 5 | */ |
AnnaBridge | 171:3a7713b1edbc | 6 | /* **************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 7 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
AnnaBridge | 171:3a7713b1edbc | 8 | * |
AnnaBridge | 171:3a7713b1edbc | 9 | * Permission is hereby granted, free of charge, to any person obtaining a |
AnnaBridge | 171:3a7713b1edbc | 10 | * copy of this software and associated documentation files (the "Software"), |
AnnaBridge | 171:3a7713b1edbc | 11 | * to deal in the Software without restriction, including without limitation |
AnnaBridge | 171:3a7713b1edbc | 12 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
AnnaBridge | 171:3a7713b1edbc | 13 | * and/or sell copies of the Software, and to permit persons to whom the |
AnnaBridge | 171:3a7713b1edbc | 14 | * Software is furnished to do so, subject to the following conditions: |
AnnaBridge | 171:3a7713b1edbc | 15 | * |
AnnaBridge | 171:3a7713b1edbc | 16 | * The above copyright notice and this permission notice shall be included |
AnnaBridge | 171:3a7713b1edbc | 17 | * in all copies or substantial portions of the Software. |
AnnaBridge | 171:3a7713b1edbc | 18 | * |
AnnaBridge | 171:3a7713b1edbc | 19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
AnnaBridge | 171:3a7713b1edbc | 20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
AnnaBridge | 171:3a7713b1edbc | 21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
AnnaBridge | 171:3a7713b1edbc | 22 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
AnnaBridge | 171:3a7713b1edbc | 23 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
AnnaBridge | 171:3a7713b1edbc | 24 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
AnnaBridge | 171:3a7713b1edbc | 25 | * OTHER DEALINGS IN THE SOFTWARE. |
AnnaBridge | 171:3a7713b1edbc | 26 | * |
AnnaBridge | 171:3a7713b1edbc | 27 | * Except as contained in this notice, the name of Maxim Integrated |
AnnaBridge | 171:3a7713b1edbc | 28 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
AnnaBridge | 171:3a7713b1edbc | 29 | * Products, Inc. Branding Policy. |
AnnaBridge | 171:3a7713b1edbc | 30 | * |
AnnaBridge | 171:3a7713b1edbc | 31 | * The mere transfer of this software does not imply any licenses |
AnnaBridge | 171:3a7713b1edbc | 32 | * of trade secrets, proprietary technology, copyrights, patents, |
AnnaBridge | 171:3a7713b1edbc | 33 | * trademarks, maskwork rights, or any other form of intellectual |
AnnaBridge | 171:3a7713b1edbc | 34 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
AnnaBridge | 171:3a7713b1edbc | 35 | * ownership rights. |
AnnaBridge | 171:3a7713b1edbc | 36 | * |
AnnaBridge | 171:3a7713b1edbc | 37 | * $Date: 2016-10-10 19:53:06 -0500 (Mon, 10 Oct 2016) $ |
AnnaBridge | 171:3a7713b1edbc | 38 | * $Revision: 24677 $ |
AnnaBridge | 171:3a7713b1edbc | 39 | * |
AnnaBridge | 171:3a7713b1edbc | 40 | * |
AnnaBridge | 171:3a7713b1edbc | 41 | **************************************************************************** */ |
AnnaBridge | 171:3a7713b1edbc | 42 | |
AnnaBridge | 171:3a7713b1edbc | 43 | /* Define to prevent redundant inclusion */ |
AnnaBridge | 171:3a7713b1edbc | 44 | #ifndef _MXC_WDT_REGS_H_ |
AnnaBridge | 171:3a7713b1edbc | 45 | #define _MXC_WDT_REGS_H_ |
AnnaBridge | 171:3a7713b1edbc | 46 | |
AnnaBridge | 171:3a7713b1edbc | 47 | /* **** Includes **** */ |
AnnaBridge | 171:3a7713b1edbc | 48 | #include <stdint.h> |
AnnaBridge | 171:3a7713b1edbc | 49 | |
AnnaBridge | 171:3a7713b1edbc | 50 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 51 | extern "C" { |
AnnaBridge | 171:3a7713b1edbc | 52 | #endif |
AnnaBridge | 171:3a7713b1edbc | 53 | |
AnnaBridge | 171:3a7713b1edbc | 54 | |
AnnaBridge | 171:3a7713b1edbc | 55 | ///@cond |
AnnaBridge | 171:3a7713b1edbc | 56 | /* |
AnnaBridge | 171:3a7713b1edbc | 57 | If types are not defined elsewhere (CMSIS) define them here |
AnnaBridge | 171:3a7713b1edbc | 58 | */ |
AnnaBridge | 171:3a7713b1edbc | 59 | #ifndef __IO |
AnnaBridge | 171:3a7713b1edbc | 60 | #define __IO volatile |
AnnaBridge | 171:3a7713b1edbc | 61 | #endif |
AnnaBridge | 171:3a7713b1edbc | 62 | #ifndef __I |
AnnaBridge | 171:3a7713b1edbc | 63 | #define __I volatile const |
AnnaBridge | 171:3a7713b1edbc | 64 | #endif |
AnnaBridge | 171:3a7713b1edbc | 65 | #ifndef __O |
AnnaBridge | 171:3a7713b1edbc | 66 | #define __O volatile |
AnnaBridge | 171:3a7713b1edbc | 67 | #endif |
AnnaBridge | 171:3a7713b1edbc | 68 | #ifndef __RO |
AnnaBridge | 171:3a7713b1edbc | 69 | #define __RO volatile const |
AnnaBridge | 171:3a7713b1edbc | 70 | #endif |
AnnaBridge | 171:3a7713b1edbc | 71 | ///@endcond |
AnnaBridge | 171:3a7713b1edbc | 72 | |
AnnaBridge | 171:3a7713b1edbc | 73 | /** |
AnnaBridge | 171:3a7713b1edbc | 74 | * @ingroup wdt0 |
AnnaBridge | 171:3a7713b1edbc | 75 | * @defgroup wdt_registers Registers |
AnnaBridge | 171:3a7713b1edbc | 76 | * @brief Registers, Bit Masks and Bit Positions |
AnnaBridge | 171:3a7713b1edbc | 77 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 78 | */ |
AnnaBridge | 171:3a7713b1edbc | 79 | /* |
AnnaBridge | 171:3a7713b1edbc | 80 | Typedefed structure(s) for module registers (per instance or section) with direct 32-bit |
AnnaBridge | 171:3a7713b1edbc | 81 | access to each register in module. |
AnnaBridge | 171:3a7713b1edbc | 82 | */ |
AnnaBridge | 171:3a7713b1edbc | 83 | /** |
AnnaBridge | 171:3a7713b1edbc | 84 | * Structure type to access the WDT Registers, see #MXC_WDT_GET_WDT(i) to get a pointer to the WDT[i] register structure. |
AnnaBridge | 171:3a7713b1edbc | 85 | * @note For the Always-On Watch Dog Timer, see \ref wdt2. |
AnnaBridge | 171:3a7713b1edbc | 86 | */ |
AnnaBridge | 171:3a7713b1edbc | 87 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 88 | __IO uint32_t ctrl; /**< <tt>\b 0x0000:</tt> WDT_CTRL Register - WDT Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 89 | __IO uint32_t clear; /**< <tt>\b 0x0004:</tt> WDT_CLEAR Register - WDT Clear Register to prevent a WDT Reset (Feed Dog) */ |
AnnaBridge | 171:3a7713b1edbc | 90 | __IO uint32_t flags; /**< <tt>\b 0x0008:</tt> WDT_FLAGS Register - WDT Interrupt and Reset Flags */ |
AnnaBridge | 171:3a7713b1edbc | 91 | __IO uint32_t enable; /**< <tt>\b 0x000C:</tt> WDT_ENABLE Register - WDT Reset and Interrupt Enable/Disable Controls */ |
AnnaBridge | 171:3a7713b1edbc | 92 | __RO uint32_t rsv010; /**< <tt>\b 0x0010:</tt> RESERVED, DO NOT MODIFY. */ |
AnnaBridge | 171:3a7713b1edbc | 93 | __IO uint32_t lock_ctrl; /**< <tt>\b 0x0014:</tt> WDT_LOCK_CTRL Register - Lock for Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 94 | } mxc_wdt_regs_t; |
AnnaBridge | 171:3a7713b1edbc | 95 | /**@} end of group wdt_registers.*/ |
AnnaBridge | 171:3a7713b1edbc | 96 | |
AnnaBridge | 171:3a7713b1edbc | 97 | /* |
AnnaBridge | 171:3a7713b1edbc | 98 | Register offsets for module WDT. |
AnnaBridge | 171:3a7713b1edbc | 99 | */ |
AnnaBridge | 171:3a7713b1edbc | 100 | /** |
AnnaBridge | 171:3a7713b1edbc | 101 | * @ingroup wdt_registers |
AnnaBridge | 171:3a7713b1edbc | 102 | * @defgroup WDT_Register_Offsets Register Offsets |
AnnaBridge | 171:3a7713b1edbc | 103 | * @brief Watchdog Timer Register Offsets from the WDT[n] Base Peripheral Address, where n is between 0 and #MXC_CFG_WDT_INSTANCES for the \MXIM_Device. |
AnnaBridge | 171:3a7713b1edbc | 104 | * @details Use #MXC_WDT_GET_BASE(i) to get the base address for a specific watchdog timer instance. |
AnnaBridge | 171:3a7713b1edbc | 105 | * @note See \ref wdt2 for the Always-On Watchdog Timer Peripheral driver. |
AnnaBridge | 171:3a7713b1edbc | 106 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 107 | */ |
AnnaBridge | 171:3a7713b1edbc | 108 | #define MXC_R_WDT_OFFS_CTRL ((uint32_t)0x00000000UL) /**< Offset from the WDT[i] Base Peripheral Address : WDT_CTRL : <tt>\b 0x0000 </tt> */ |
AnnaBridge | 171:3a7713b1edbc | 109 | #define MXC_R_WDT_OFFS_CLEAR ((uint32_t)0x00000004UL) /**< Offset from the WDT[i] Base Peripheral Address : WDT_CLEAR : <tt>\b 0x0004 </tt> */ |
AnnaBridge | 171:3a7713b1edbc | 110 | #define MXC_R_WDT_OFFS_FLAGS ((uint32_t)0x00000008UL) /**< Offset from the WDT[i] Base Peripheral Address : WDT_FLAGS : <tt>\b 0x0008 </tt> */ |
AnnaBridge | 171:3a7713b1edbc | 111 | #define MXC_R_WDT_OFFS_ENABLE ((uint32_t)0x0000000CUL) /**< Offset from the WDT[i] Base Peripheral Address : WDT_ENABLE : <tt>\b 0x000C </tt> */ |
AnnaBridge | 171:3a7713b1edbc | 112 | #define MXC_R_WDT_OFFS_LOCK_CTRL ((uint32_t)0x00000014UL) /**< Offset from the WDT[i] Base Peripheral Address : WDT_LOCK_CTRL : <tt>\b 0x0014 </tt> */ |
AnnaBridge | 171:3a7713b1edbc | 113 | /**@} end of group WDT_Register_Offsets */ |
AnnaBridge | 171:3a7713b1edbc | 114 | |
AnnaBridge | 171:3a7713b1edbc | 115 | /* |
AnnaBridge | 171:3a7713b1edbc | 116 | Field positions and masks for module WDT. |
AnnaBridge | 171:3a7713b1edbc | 117 | */ |
AnnaBridge | 171:3a7713b1edbc | 118 | /** |
AnnaBridge | 171:3a7713b1edbc | 119 | * @ingroup wdt_registers |
AnnaBridge | 171:3a7713b1edbc | 120 | * @defgroup WDT_CTRL_Register WDT_CTRL Register |
AnnaBridge | 171:3a7713b1edbc | 121 | * @brief Field Positions and Bit Masks for the WDT_CTRL register |
AnnaBridge | 171:3a7713b1edbc | 122 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 123 | */ |
AnnaBridge | 171:3a7713b1edbc | 124 | #define MXC_F_WDT_CTRL_INT_PERIOD_POS 0 /**< INT_PERIOD Field Position */ |
AnnaBridge | 171:3a7713b1edbc | 125 | #define MXC_F_WDT_CTRL_INT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< INT_PERIOD Field Mask - This field is used to set the interrupt period on the WDT. */ |
AnnaBridge | 171:3a7713b1edbc | 126 | #define MXC_F_WDT_CTRL_RST_PERIOD_POS 4 /**< RST_PERIOD Field Position */ |
AnnaBridge | 171:3a7713b1edbc | 127 | #define MXC_F_WDT_CTRL_RST_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< RST_PERIOD Field Mask - This field sets the time after an |
AnnaBridge | 171:3a7713b1edbc | 128 | * interrupt period has expired before the device resets. If the |
AnnaBridge | 171:3a7713b1edbc | 129 | * INT_PERIOD Flag is cleared prior to the RST_PERIOD expiration, |
AnnaBridge | 171:3a7713b1edbc | 130 | * the device will not reset. */ |
AnnaBridge | 171:3a7713b1edbc | 131 | #define MXC_F_WDT_CTRL_EN_TIMER_POS 8 /**< EN_TIMER Field Position */ |
AnnaBridge | 171:3a7713b1edbc | 132 | #define MXC_F_WDT_CTRL_EN_TIMER ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_TIMER_POS)) /**< EN_TIMER Field Mask */ |
AnnaBridge | 171:3a7713b1edbc | 133 | #define MXC_F_WDT_CTRL_EN_CLOCK_POS 9 /**< EN_CLOCK Field Position */ |
AnnaBridge | 171:3a7713b1edbc | 134 | #define MXC_F_WDT_CTRL_EN_CLOCK ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_CLOCK_POS)) /**< EN_CLOCK Field Mask */ |
AnnaBridge | 171:3a7713b1edbc | 135 | #define MXC_F_WDT_CTRL_WAIT_PERIOD_POS 12 /**< WAIT_PERIOD Field Position */ |
AnnaBridge | 171:3a7713b1edbc | 136 | #define MXC_F_WDT_CTRL_WAIT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< WAIT_PERIOD Field Mask */ |
AnnaBridge | 171:3a7713b1edbc | 137 | /**@} end of group WDT_CTRL */ |
AnnaBridge | 171:3a7713b1edbc | 138 | /** |
AnnaBridge | 171:3a7713b1edbc | 139 | * @ingroup wdt_registers |
AnnaBridge | 171:3a7713b1edbc | 140 | * @defgroup WDT_FLAGS_Register WDT_FLAGS Register |
AnnaBridge | 171:3a7713b1edbc | 141 | * @brief Field Positions and Bit Masks for the WDT_FLAGS register. Watchdog Timer Flags for Interrupts and Reset. |
AnnaBridge | 171:3a7713b1edbc | 142 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 143 | */ |
AnnaBridge | 171:3a7713b1edbc | 144 | #define MXC_F_WDT_FLAGS_TIMEOUT_POS 0 /**< TIMEOUT Flag Position */ |
AnnaBridge | 171:3a7713b1edbc | 145 | #define MXC_F_WDT_FLAGS_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_TIMEOUT_POS)) /**< TIMEOUT Flag Mask - if this flag is set it indicates the Watchdog Timer timed out. */ |
AnnaBridge | 171:3a7713b1edbc | 146 | #define MXC_F_WDT_FLAGS_PRE_WIN_POS 1 /**< PRE_WIN Flag Position */ |
AnnaBridge | 171:3a7713b1edbc | 147 | #define MXC_F_WDT_FLAGS_PRE_WIN ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_PRE_WIN_POS)) /**< PRE_WIN Flag Mask - If the PRE_WIN flag is set it indicates the Watchdog Timer was cleared by firmware writing to the WDT_CLEAR register <b><em> during the pre-window period</em></b>. */ |
AnnaBridge | 171:3a7713b1edbc | 148 | #define MXC_F_WDT_FLAGS_RESET_OUT_POS 2 /**< RESET_OUT Flag Position */ |
AnnaBridge | 171:3a7713b1edbc | 149 | #define MXC_F_WDT_FLAGS_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_RESET_OUT_POS)) /**< RESET_FLAG Flag Mask - This flag indicates that the watchdog timer timed out and the reset period elapsed without the timer being cleared. This will result in a system restart. */ |
AnnaBridge | 171:3a7713b1edbc | 150 | /**@} end of group WDT_FLAGS */ |
AnnaBridge | 171:3a7713b1edbc | 151 | |
AnnaBridge | 171:3a7713b1edbc | 152 | /** |
AnnaBridge | 171:3a7713b1edbc | 153 | * @ingroup wdt_registers |
AnnaBridge | 171:3a7713b1edbc | 154 | * @defgroup WDT_ENABLE_Register WDT_ENABLE Register |
AnnaBridge | 171:3a7713b1edbc | 155 | * @brief Field Positions and Bit Masks for the WDT_ENABLE register. |
AnnaBridge | 171:3a7713b1edbc | 156 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 157 | */ |
AnnaBridge | 171:3a7713b1edbc | 158 | #define MXC_F_WDT_ENABLE_TIMEOUT_POS 0 /**< ENABLE_TIMEOUT Field Position */ |
AnnaBridge | 171:3a7713b1edbc | 159 | #define MXC_F_WDT_ENABLE_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_TIMEOUT_POS)) /**< ENABLE_TIMEOUT Field Mask */ |
AnnaBridge | 171:3a7713b1edbc | 160 | #define MXC_F_WDT_ENABLE_PRE_WIN_POS 1 /**< ENABLE_PRE_WIN Field Position */ |
AnnaBridge | 171:3a7713b1edbc | 161 | #define MXC_F_WDT_ENABLE_PRE_WIN ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_PRE_WIN_POS)) /**< ENABLE_PRE_WIN Field Mask */ |
AnnaBridge | 171:3a7713b1edbc | 162 | #define MXC_F_WDT_ENABLE_RESET_OUT_POS 2 /**< ENABLE_RESET_OUT Field Position */ |
AnnaBridge | 171:3a7713b1edbc | 163 | #define MXC_F_WDT_ENABLE_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_RESET_OUT_POS)) /**< ENABLE_RESET_OUT Field Mask */ |
AnnaBridge | 171:3a7713b1edbc | 164 | /**@} end of group WDT_ENABLE */ |
AnnaBridge | 171:3a7713b1edbc | 165 | |
AnnaBridge | 171:3a7713b1edbc | 166 | /** |
AnnaBridge | 171:3a7713b1edbc | 167 | * @ingroup wdt_registers |
AnnaBridge | 171:3a7713b1edbc | 168 | * @defgroup WDT_LOCK_CTRL_Register WDT_LOCK_CTRL Register |
AnnaBridge | 171:3a7713b1edbc | 169 | * @brief The WDT_LOCK_CTRL register controls read/write access to the \ref WDT_CTRL_Register. |
AnnaBridge | 171:3a7713b1edbc | 170 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 171 | */ |
AnnaBridge | 171:3a7713b1edbc | 172 | #define MXC_F_WDT_LOCK_CTRL_WDLOCK_POS 0 /**< WDLOCK Field's position in the WDT_LOCK_CTRL register. */ |
AnnaBridge | 171:3a7713b1edbc | 173 | #define MXC_F_WDT_LOCK_CTRL_WDLOCK ((uint32_t)(0x000000FFUL << MXC_F_WDT_LOCK_CTRL_WDLOCK_POS)) /**< WDLOCK Field mask for the WDT_LOCK_CTRL register. Reading a value of */ |
AnnaBridge | 171:3a7713b1edbc | 174 | /**@} end of group WDT_ENABLE */ |
AnnaBridge | 171:3a7713b1edbc | 175 | |
AnnaBridge | 171:3a7713b1edbc | 176 | |
AnnaBridge | 171:3a7713b1edbc | 177 | |
AnnaBridge | 171:3a7713b1edbc | 178 | /* |
AnnaBridge | 171:3a7713b1edbc | 179 | Field values and shifted values for module WDT. |
AnnaBridge | 171:3a7713b1edbc | 180 | */ |
AnnaBridge | 171:3a7713b1edbc | 181 | /** |
AnnaBridge | 171:3a7713b1edbc | 182 | * @ingroup WDT_CTRL_Register |
AnnaBridge | 171:3a7713b1edbc | 183 | * @defgroup WDT_CTRL_field_values WDT_CTRL Register Field and Shifted Field Values |
AnnaBridge | 171:3a7713b1edbc | 184 | * @brief Field values and Shifted Field values for the WDT_CTRL register. |
AnnaBridge | 171:3a7713b1edbc | 185 | * @details Shifted field values are field values shifted to the loacation of the field in the register. |
AnnaBridge | 171:3a7713b1edbc | 186 | */ |
AnnaBridge | 171:3a7713b1edbc | 187 | /** |
AnnaBridge | 171:3a7713b1edbc | 188 | * @ingroup WDT_CTRL_field_values |
AnnaBridge | 171:3a7713b1edbc | 189 | * @defgroup WDT_CTRL_INT_PERIOD_Value Watchdog Timer Interrupt Period |
AnnaBridge | 171:3a7713b1edbc | 190 | * @brief Sets the duration of the watchdog interrupt period. |
AnnaBridge | 171:3a7713b1edbc | 191 | * @details The INT_PERIOD field sets the duration of the watchdog interrupt |
AnnaBridge | 171:3a7713b1edbc | 192 | * period, which is the time period from the WDT being |
AnnaBridge | 171:3a7713b1edbc | 193 | * enabled/cleared until the WDT flag, #MXC_F_WDT_FLAGS_TIMEOUT, is |
AnnaBridge | 171:3a7713b1edbc | 194 | * set. |
AnnaBridge | 171:3a7713b1edbc | 195 | * The values defined are in the number of watchdog clock cycles. |
AnnaBridge | 171:3a7713b1edbc | 196 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 197 | */ |
AnnaBridge | 171:3a7713b1edbc | 198 | #define MXC_V_WDT_CTRL_INT_PERIOD_2_31_CLKS ((uint32_t)(0x00000000UL)) /**< Interupt Period of \f$ 2^{31} \f$ WDT CLK Cycles */ |
AnnaBridge | 171:3a7713b1edbc | 199 | #define MXC_V_WDT_CTRL_INT_PERIOD_2_30_CLKS ((uint32_t)(0x00000001UL)) /**< Interupt Period of \f$ 2^{30} \f$ WDT CLK Cycles */ |
AnnaBridge | 171:3a7713b1edbc | 200 | #define MXC_V_WDT_CTRL_INT_PERIOD_2_29_CLKS ((uint32_t)(0x00000002UL)) /**< Interupt Period of \f$ 2^{29} \f$ WDT CLK Cycles */ |
AnnaBridge | 171:3a7713b1edbc | 201 | #define MXC_V_WDT_CTRL_INT_PERIOD_2_28_CLKS ((uint32_t)(0x00000003UL)) /**< Interupt Period of \f$ 2^{28} \f$ WDT CLK Cycles */ |
AnnaBridge | 171:3a7713b1edbc | 202 | #define MXC_V_WDT_CTRL_INT_PERIOD_2_27_CLKS ((uint32_t)(0x00000004UL)) /**< Interupt Period of \f$ 2^{27} \f$ WDT CLK Cycles */ |
AnnaBridge | 171:3a7713b1edbc | 203 | #define MXC_V_WDT_CTRL_INT_PERIOD_2_26_CLKS ((uint32_t)(0x00000005UL)) /**< Interupt Period of \f$ 2^{26} \f$ WDT CLK Cycles */ |
AnnaBridge | 171:3a7713b1edbc | 204 | #define MXC_V_WDT_CTRL_INT_PERIOD_2_25_CLKS ((uint32_t)(0x00000006UL)) /**< Interupt Period of \f$ 2^{25} \f$ WDT CLK Cycles */ |
AnnaBridge | 171:3a7713b1edbc | 205 | #define MXC_V_WDT_CTRL_INT_PERIOD_2_24_CLKS ((uint32_t)(0x00000007UL)) /**< Interupt Period of \f$ 2^{24} \f$ WDT CLK Cycles */ |
AnnaBridge | 171:3a7713b1edbc | 206 | #define MXC_V_WDT_CTRL_INT_PERIOD_2_23_CLKS ((uint32_t)(0x00000008UL)) /**< Interupt Period of \f$ 2^{23} \f$ WDT CLK Cycles */ |
AnnaBridge | 171:3a7713b1edbc | 207 | #define MXC_V_WDT_CTRL_INT_PERIOD_2_22_CLKS ((uint32_t)(0x00000009UL)) /**< Interupt Period of \f$ 2^{22} \f$ WDT CLK Cycles */ |
AnnaBridge | 171:3a7713b1edbc | 208 | #define MXC_V_WDT_CTRL_INT_PERIOD_2_21_CLKS ((uint32_t)(0x0000000AUL)) /**< Interupt Period of \f$ 2^{21} \f$ WDT CLK Cycles */ |
AnnaBridge | 171:3a7713b1edbc | 209 | #define MXC_V_WDT_CTRL_INT_PERIOD_2_20_CLKS ((uint32_t)(0x0000000BUL)) /**< Interupt Period of \f$ 2^{20} \f$ WDT CLK Cycles */ |
AnnaBridge | 171:3a7713b1edbc | 210 | #define MXC_V_WDT_CTRL_INT_PERIOD_2_19_CLKS ((uint32_t)(0x0000000CUL)) /**< Interupt Period of \f$ 2^{19} \f$ WDT CLK Cycles */ |
AnnaBridge | 171:3a7713b1edbc | 211 | #define MXC_V_WDT_CTRL_INT_PERIOD_2_18_CLKS ((uint32_t)(0x0000000DUL)) /**< Interupt Period of \f$ 2^{18} \f$ WDT CLK Cycles */ |
AnnaBridge | 171:3a7713b1edbc | 212 | #define MXC_V_WDT_CTRL_INT_PERIOD_2_17_CLKS ((uint32_t)(0x0000000EUL)) /**< Interupt Period of \f$ 2^{17} \f$ WDT CLK Cycles */ |
AnnaBridge | 171:3a7713b1edbc | 213 | #define MXC_V_WDT_CTRL_INT_PERIOD_2_16_CLKS ((uint32_t)(0x0000000FUL)) /**< Interupt Period of \f$ 2^{16} \f$ WDT CLK Cycles */ |
AnnaBridge | 171:3a7713b1edbc | 214 | /**@} end of group WDT_CTRL_INT_PERIOD_Value */ |
AnnaBridge | 171:3a7713b1edbc | 215 | |
AnnaBridge | 171:3a7713b1edbc | 216 | /** |
AnnaBridge | 171:3a7713b1edbc | 217 | * @ingroup WDT_CTRL_field_values |
AnnaBridge | 171:3a7713b1edbc | 218 | * @defgroup WDT_CTRL_INT_PERIOD_Shifted Watchdog Timer Interrupt Period Shifted Values |
AnnaBridge | 171:3a7713b1edbc | 219 | * @brief Shifted values for the \ref WDT_CTRL_INT_PERIOD_Value |
AnnaBridge | 171:3a7713b1edbc | 220 | * @details The shifted value is |
AnnaBridge | 171:3a7713b1edbc | 221 | * shifted to align with the fields location in the WDT_CTRL register. |
AnnaBridge | 171:3a7713b1edbc | 222 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 223 | */ |
AnnaBridge | 171:3a7713b1edbc | 224 | #define MXC_S_WDT_CTRL_INT_PERIOD_2_31_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_31_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_31_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 225 | #define MXC_S_WDT_CTRL_INT_PERIOD_2_30_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_30_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_30_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 226 | #define MXC_S_WDT_CTRL_INT_PERIOD_2_29_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_29_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_29_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 227 | #define MXC_S_WDT_CTRL_INT_PERIOD_2_28_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_28_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_28_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 228 | #define MXC_S_WDT_CTRL_INT_PERIOD_2_27_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_27_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_27_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 229 | #define MXC_S_WDT_CTRL_INT_PERIOD_2_26_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_26_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_26_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 230 | #define MXC_S_WDT_CTRL_INT_PERIOD_2_25_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_25_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_25_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 231 | #define MXC_S_WDT_CTRL_INT_PERIOD_2_24_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_24_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_24_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 232 | #define MXC_S_WDT_CTRL_INT_PERIOD_2_23_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_23_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_23_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 233 | #define MXC_S_WDT_CTRL_INT_PERIOD_2_22_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_22_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_22_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 234 | #define MXC_S_WDT_CTRL_INT_PERIOD_2_21_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_21_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_21_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 235 | #define MXC_S_WDT_CTRL_INT_PERIOD_2_20_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_20_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_20_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 236 | #define MXC_S_WDT_CTRL_INT_PERIOD_2_19_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_19_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_19_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 237 | #define MXC_S_WDT_CTRL_INT_PERIOD_2_18_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_18_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_18_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 238 | #define MXC_S_WDT_CTRL_INT_PERIOD_2_17_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_17_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_17_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 239 | #define MXC_S_WDT_CTRL_INT_PERIOD_2_16_CLKS ((uint32_t)(MXC_V_WDT_CTRL_INT_PERIOD_2_16_CLKS << MXC_F_WDT_CTRL_INT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_INT_PERIOD_2_16_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 240 | /**@} end of group WDT_CTRL_INT_PERIOD_Shifted */ |
AnnaBridge | 171:3a7713b1edbc | 241 | /** |
AnnaBridge | 171:3a7713b1edbc | 242 | * @ingroup WDT_CTRL_field_values |
AnnaBridge | 171:3a7713b1edbc | 243 | * @defgroup WDT_CTRL_RST_PERIOD_Value Watchdog Timer Reset Period |
AnnaBridge | 171:3a7713b1edbc | 244 | * @brief Sets the duration of the watchdog reset period. |
AnnaBridge | 171:3a7713b1edbc | 245 | * @details The RST_PERIOD field sets the duration of the watchdog reset |
AnnaBridge | 171:3a7713b1edbc | 246 | * period, which is the time period from the WDT being |
AnnaBridge | 171:3a7713b1edbc | 247 | * enabled/cleared until the WDT flag, #MXC_F_WDT_CTRL_RST_PERIOD is |
AnnaBridge | 171:3a7713b1edbc | 248 | * set. |
AnnaBridge | 171:3a7713b1edbc | 249 | * The values defined are in the number of watchdog clock cycles. |
AnnaBridge | 171:3a7713b1edbc | 250 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 251 | */ |
AnnaBridge | 171:3a7713b1edbc | 252 | #define MXC_V_WDT_CTRL_RST_PERIOD_2_31_CLKS ((uint32_t)(0x00000000UL)) /**< Reset Period of \f$ 2^{31} \f$ WDT CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 253 | #define MXC_V_WDT_CTRL_RST_PERIOD_2_30_CLKS ((uint32_t)(0x00000001UL)) /**< Reset Period of \f$ 2^{30} \f$ WDT CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 254 | #define MXC_V_WDT_CTRL_RST_PERIOD_2_29_CLKS ((uint32_t)(0x00000002UL)) /**< Reset Period of \f$ 2^{29} \f$ WDT CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 255 | #define MXC_V_WDT_CTRL_RST_PERIOD_2_28_CLKS ((uint32_t)(0x00000003UL)) /**< Reset Period of \f$ 2^{28} \f$ WDT CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 256 | #define MXC_V_WDT_CTRL_RST_PERIOD_2_27_CLKS ((uint32_t)(0x00000004UL)) /**< Reset Period of \f$ 2^{27} \f$ WDT CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 257 | #define MXC_V_WDT_CTRL_RST_PERIOD_2_26_CLKS ((uint32_t)(0x00000005UL)) /**< Reset Period of \f$ 2^{26} \f$ WDT CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 258 | #define MXC_V_WDT_CTRL_RST_PERIOD_2_25_CLKS ((uint32_t)(0x00000006UL)) /**< Reset Period of \f$ 2^{25} \f$ WDT CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 259 | #define MXC_V_WDT_CTRL_RST_PERIOD_2_24_CLKS ((uint32_t)(0x00000007UL)) /**< Reset Period of \f$ 2^{24} \f$ WDT CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 260 | #define MXC_V_WDT_CTRL_RST_PERIOD_2_23_CLKS ((uint32_t)(0x00000008UL)) /**< Reset Period of \f$ 2^{23} \f$ WDT CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 261 | #define MXC_V_WDT_CTRL_RST_PERIOD_2_22_CLKS ((uint32_t)(0x00000009UL)) /**< Reset Period of \f$ 2^{22} \f$ WDT CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 262 | #define MXC_V_WDT_CTRL_RST_PERIOD_2_21_CLKS ((uint32_t)(0x0000000AUL)) /**< Reset Period of \f$ 2^{21} \f$ WDT CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 263 | #define MXC_V_WDT_CTRL_RST_PERIOD_2_20_CLKS ((uint32_t)(0x0000000BUL)) /**< Reset Period of \f$ 2^{20} \f$ WDT CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 264 | #define MXC_V_WDT_CTRL_RST_PERIOD_2_19_CLKS ((uint32_t)(0x0000000CUL)) /**< Reset Period of \f$ 2^{19} \f$ WDT CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 265 | #define MXC_V_WDT_CTRL_RST_PERIOD_2_18_CLKS ((uint32_t)(0x0000000DUL)) /**< Reset Period of \f$ 2^{18} \f$ WDT CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 266 | #define MXC_V_WDT_CTRL_RST_PERIOD_2_17_CLKS ((uint32_t)(0x0000000EUL)) /**< Reset Period of \f$ 2^{17} \f$ WDT CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 267 | #define MXC_V_WDT_CTRL_RST_PERIOD_2_16_CLKS ((uint32_t)(0x0000000FUL)) /**< Reset Period of \f$ 2^{16} \f$ WDT CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 268 | /**@} end of group WDT_CTRL_RST_PERIOD_Value */ |
AnnaBridge | 171:3a7713b1edbc | 269 | |
AnnaBridge | 171:3a7713b1edbc | 270 | /** |
AnnaBridge | 171:3a7713b1edbc | 271 | * @ingroup WDT_CTRL_field_values |
AnnaBridge | 171:3a7713b1edbc | 272 | * @defgroup WDT_CTRL_RST_PERIOD_Shifted Watchdog Timer Reset Period Shifted Values |
AnnaBridge | 171:3a7713b1edbc | 273 | * @brief Shifted values for the \ref WDT_CTRL_RST_PERIOD_Value |
AnnaBridge | 171:3a7713b1edbc | 274 | * @details These values are shifted to align with the field's location in the WDT_CTRL register. |
AnnaBridge | 171:3a7713b1edbc | 275 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 276 | */ |
AnnaBridge | 171:3a7713b1edbc | 277 | #define MXC_S_WDT_CTRL_RST_PERIOD_2_31_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_31_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_31_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 278 | #define MXC_S_WDT_CTRL_RST_PERIOD_2_30_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_30_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_30_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 279 | #define MXC_S_WDT_CTRL_RST_PERIOD_2_29_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_29_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_29_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 280 | #define MXC_S_WDT_CTRL_RST_PERIOD_2_28_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_28_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_28_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 281 | #define MXC_S_WDT_CTRL_RST_PERIOD_2_27_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_27_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_27_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 282 | #define MXC_S_WDT_CTRL_RST_PERIOD_2_26_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_26_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_26_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 283 | #define MXC_S_WDT_CTRL_RST_PERIOD_2_25_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_25_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_25_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 284 | #define MXC_S_WDT_CTRL_RST_PERIOD_2_24_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_24_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_24_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 285 | #define MXC_S_WDT_CTRL_RST_PERIOD_2_23_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_23_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_23_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 286 | #define MXC_S_WDT_CTRL_RST_PERIOD_2_22_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_22_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_22_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 287 | #define MXC_S_WDT_CTRL_RST_PERIOD_2_21_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_21_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_21_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 288 | #define MXC_S_WDT_CTRL_RST_PERIOD_2_20_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_20_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_20_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 289 | #define MXC_S_WDT_CTRL_RST_PERIOD_2_19_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_19_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_19_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 290 | #define MXC_S_WDT_CTRL_RST_PERIOD_2_18_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_18_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_18_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 291 | #define MXC_S_WDT_CTRL_RST_PERIOD_2_17_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_17_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_17_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 292 | #define MXC_S_WDT_CTRL_RST_PERIOD_2_16_CLKS ((uint32_t)(MXC_V_WDT_CTRL_RST_PERIOD_2_16_CLKS << MXC_F_WDT_CTRL_RST_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_RST_PERIOD_2_16_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 293 | /**@} end of group WDT_CTRL_RST_PERIOD_Shifted */ |
AnnaBridge | 171:3a7713b1edbc | 294 | /** |
AnnaBridge | 171:3a7713b1edbc | 295 | * @ingroup WDT_CTRL_field_values |
AnnaBridge | 171:3a7713b1edbc | 296 | * @defgroup WDT_CTRL_WAIT_PERIOD_Value Watchdog Timer Wait Period |
AnnaBridge | 171:3a7713b1edbc | 297 | * @brief Sets the duration of the watchdog wait window period. |
AnnaBridge | 171:3a7713b1edbc | 298 | * @details The WAIT_PERIOD field sets the duration of the watchdog pre-window |
AnnaBridge | 171:3a7713b1edbc | 299 | * period. If the watchdog is reset before the wait period has finished, an out-of-window interrupt will occur. |
AnnaBridge | 171:3a7713b1edbc | 300 | * This sets the minimum amount of time between watchdog enable/clear to resetting the WDT count and assists in detecting |
AnnaBridge | 171:3a7713b1edbc | 301 | * overclocking or an invalid clock. |
AnnaBridge | 171:3a7713b1edbc | 302 | * The values defined are in the number of watchdog clock cycles. |
AnnaBridge | 171:3a7713b1edbc | 303 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 304 | */ |
AnnaBridge | 171:3a7713b1edbc | 305 | #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_31_CLKS ((uint32_t)(0x00000000UL)) /**< Wait Period of \f$ 2^{31} \f$ WDT CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 306 | #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_30_CLKS ((uint32_t)(0x00000001UL)) /**< Wait Period of \f$ 2^{30} \f$ WDT CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 307 | #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_29_CLKS ((uint32_t)(0x00000002UL)) /**< Wait Period of \f$ 2^{29} \f$ WDT CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 308 | #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_28_CLKS ((uint32_t)(0x00000003UL)) /**< Wait Period of \f$ 2^{28} \f$ WDT CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 309 | #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_27_CLKS ((uint32_t)(0x00000004UL)) /**< Wait Period of \f$ 2^{27} \f$ WDT CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 310 | #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_26_CLKS ((uint32_t)(0x00000005UL)) /**< Wait Period of \f$ 2^{26} \f$ WDT CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 311 | #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_25_CLKS ((uint32_t)(0x00000006UL)) /**< Wait Period of \f$ 2^{25} \f$ WDT CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 312 | #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_24_CLKS ((uint32_t)(0x00000007UL)) /**< Wait Period of \f$ 2^{24} \f$ WDT CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 313 | #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_23_CLKS ((uint32_t)(0x00000008UL)) /**< Wait Period of \f$ 2^{23} \f$ WDT CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 314 | #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_22_CLKS ((uint32_t)(0x00000009UL)) /**< Wait Period of \f$ 2^{22} \f$ WDT CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 315 | #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_21_CLKS ((uint32_t)(0x0000000AUL)) /**< Wait Period of \f$ 2^{21} \f$ WDT CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 316 | #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_20_CLKS ((uint32_t)(0x0000000BUL)) /**< Wait Period of \f$ 2^{20} \f$ WDT CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 317 | #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_19_CLKS ((uint32_t)(0x0000000CUL)) /**< Wait Period of \f$ 2^{19} \f$ WDT CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 318 | #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_18_CLKS ((uint32_t)(0x0000000DUL)) /**< Wait Period of \f$ 2^{18} \f$ WDT CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 319 | #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_17_CLKS ((uint32_t)(0x0000000EUL)) /**< Wait Period of \f$ 2^{17} \f$ WDT CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 320 | #define MXC_V_WDT_CTRL_WAIT_PERIOD_2_16_CLKS ((uint32_t)(0x0000000FUL)) /**< Wait Period of \f$ 2^{16} \f$ WDT CLK CYCLES */ |
AnnaBridge | 171:3a7713b1edbc | 321 | /**@} end of group WDT_CTRL_WAIT_PERIOD_Value */ |
AnnaBridge | 171:3a7713b1edbc | 322 | |
AnnaBridge | 171:3a7713b1edbc | 323 | /** |
AnnaBridge | 171:3a7713b1edbc | 324 | * @ingroup WDT_CTRL_field_values |
AnnaBridge | 171:3a7713b1edbc | 325 | * @defgroup WDT_CTRL_WAIT_PERIOD_Shifted Watchdog Timer Wait Period Shifted Values |
AnnaBridge | 171:3a7713b1edbc | 326 | * @brief Shifted values for the \ref WDT_CTRL_WAIT_PERIOD_Value |
AnnaBridge | 171:3a7713b1edbc | 327 | * @details These values are shifted to align with the WAIT_PERIOD field's location in the WDT_CTRL register. |
AnnaBridge | 171:3a7713b1edbc | 328 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 329 | */ |
AnnaBridge | 171:3a7713b1edbc | 330 | #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_31_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_31_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_31_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 331 | #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_30_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_30_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_30_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 332 | #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_29_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_29_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_29_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 333 | #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_28_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_28_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_28_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 334 | #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_27_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_27_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_27_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 335 | #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_26_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_26_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_26_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 336 | #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_25_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_25_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_25_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 337 | #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_24_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_24_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_24_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 338 | #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_23_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_23_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_23_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 339 | #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_22_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_22_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_22_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 340 | #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_21_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_21_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_21_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 341 | #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_20_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_20_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_20_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 342 | #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_19_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_19_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_19_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 343 | #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_18_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_18_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_18_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 344 | #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_17_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_17_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_17_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 345 | #define MXC_S_WDT_CTRL_WAIT_PERIOD_2_16_CLKS ((uint32_t)(MXC_V_WDT_CTRL_WAIT_PERIOD_2_16_CLKS << MXC_F_WDT_CTRL_WAIT_PERIOD_POS)) /**< Shifted Field Value for #MXC_V_WDT_CTRL_WAIT_PERIOD_2_16_CLKS */ |
AnnaBridge | 171:3a7713b1edbc | 346 | /**@} end of group WDT_CTRL_WAIT_PERIOD_Shifted */ |
AnnaBridge | 171:3a7713b1edbc | 347 | |
AnnaBridge | 171:3a7713b1edbc | 348 | /** |
AnnaBridge | 171:3a7713b1edbc | 349 | * @ingroup WDT_LOCK_CTRL_Register |
AnnaBridge | 171:3a7713b1edbc | 350 | * @defgroup WDT_LOCK_field_values Watchdog Timer WDT_LOCK field values |
AnnaBridge | 171:3a7713b1edbc | 351 | * @brief Lock/Unlock values for the watchdog timer \ref WDT_CTRL_Register. |
AnnaBridge | 171:3a7713b1edbc | 352 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 353 | */ |
AnnaBridge | 171:3a7713b1edbc | 354 | #define MXC_V_WDT_LOCK_KEY 0x24 /**< Writing this value to the WDT_LOCK field of the \ref WDT_LOCK_CTRL_Register \b locks the \ref WDT_CTRL_Register making it read only. */ |
AnnaBridge | 171:3a7713b1edbc | 355 | #define MXC_V_WDT_UNLOCK_KEY 0x42 /**< Writing this value to the WDT_LOCK field of the \ref WDT_LOCK_CTRL_Register \b unlocks the \ref WDT_CTRL_Register making it read/write. */ |
AnnaBridge | 171:3a7713b1edbc | 356 | /**@} end of group WDT_LOCK_field_values */ |
AnnaBridge | 171:3a7713b1edbc | 357 | ///@cond |
AnnaBridge | 171:3a7713b1edbc | 358 | /* |
AnnaBridge | 171:3a7713b1edbc | 359 | * @internal |
AnnaBridge | 171:3a7713b1edbc | 360 | * @ingroup WDT_CLEAR_Register |
AnnaBridge | 171:3a7713b1edbc | 361 | * @defgroup WDT_CLEAR_field_values Watchdog Timer Clear Sequence Values |
AnnaBridge | 171:3a7713b1edbc | 362 | * @brief Writing the sequence of #MXC_V_WDT_RESET_KEY_0, #MXC_V_WDT_RESET_KEY_1 to the \ref WDT_CLEAR_Register will clear/reset the watchdog timer count. |
AnnaBridge | 171:3a7713b1edbc | 363 | * @note The values #MXC_V_WDT_RESET_KEY_0, #MXC_V_WDT_RESET_KEY_1 must be written sequentially to the \ref WDT_CLEAR_Register to clear the watchdog counter. |
AnnaBridge | 171:3a7713b1edbc | 364 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 365 | */ |
AnnaBridge | 171:3a7713b1edbc | 366 | #define MXC_V_WDT_RESET_KEY_0 0xA5 /**< First value to write to the \ref WDT_CLEAR_Register to perform a WDT clear. */ |
AnnaBridge | 171:3a7713b1edbc | 367 | #define MXC_V_WDT_RESET_KEY_1 0x5A /**< Second value to write to the \ref WDT_CLEAR_Register to perform a WDT clear. */ |
AnnaBridge | 171:3a7713b1edbc | 368 | /** |
AnnaBridge | 171:3a7713b1edbc | 369 | * @} end of group WDT_CLEAR_field_values |
AnnaBridge | 171:3a7713b1edbc | 370 | * @endinternal |
AnnaBridge | 171:3a7713b1edbc | 371 | */ |
AnnaBridge | 171:3a7713b1edbc | 372 | ///@endcond |
AnnaBridge | 171:3a7713b1edbc | 373 | /**@} wdt_registers*/ |
AnnaBridge | 171:3a7713b1edbc | 374 | |
AnnaBridge | 171:3a7713b1edbc | 375 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 376 | } |
AnnaBridge | 171:3a7713b1edbc | 377 | #endif |
AnnaBridge | 171:3a7713b1edbc | 378 | |
AnnaBridge | 171:3a7713b1edbc | 379 | #endif /* _MXC_WDT_REGS_H_ */ |
AnnaBridge | 171:3a7713b1edbc | 380 |