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TARGET_MAX32630FTHR/TOOLCHAIN_IAR/max3263x.h@172:65be27845400, 2019-02-20 (annotated)

Committer:: AnnaBridge
Date:: Wed Feb 20 20:53:29 2019 +0000
Revision:: 172:65be27845400
Parent:: 171:3a7713b1edbc

mbed library release version 165

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	171:3a7713b1edbc	1	/**
AnnaBridge	171:3a7713b1edbc	2	* @file
AnnaBridge	171:3a7713b1edbc	3	* @brief MAX3263X device specific definitions for the core, peripherals,
AnnaBridge	171:3a7713b1edbc	4	* features, memory, and IRQs.
AnnaBridge	171:3a7713b1edbc	5	*/
AnnaBridge	171:3a7713b1edbc	6	/* *****************************************************************************
AnnaBridge	171:3a7713b1edbc	7	* Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge	171:3a7713b1edbc	8	*
AnnaBridge	171:3a7713b1edbc	9	* Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge	171:3a7713b1edbc	10	* copy of this software and associated documentation files (the "Software"),
AnnaBridge	171:3a7713b1edbc	11	* to deal in the Software without restriction, including without limitation
AnnaBridge	171:3a7713b1edbc	12	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge	171:3a7713b1edbc	13	* and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge	171:3a7713b1edbc	14	* Software is furnished to do so, subject to the following conditions:
AnnaBridge	171:3a7713b1edbc	15	*
AnnaBridge	171:3a7713b1edbc	16	* The above copyright notice and this permission notice shall be included
AnnaBridge	171:3a7713b1edbc	17	* in all copies or substantial portions of the Software.
AnnaBridge	171:3a7713b1edbc	18	*
AnnaBridge	171:3a7713b1edbc	19	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge	171:3a7713b1edbc	20	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge	171:3a7713b1edbc	21	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge	171:3a7713b1edbc	22	* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge	171:3a7713b1edbc	23	* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge	171:3a7713b1edbc	24	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge	171:3a7713b1edbc	25	* OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge	171:3a7713b1edbc	26	*
AnnaBridge	171:3a7713b1edbc	27	* Except as contained in this notice, the name of Maxim Integrated
AnnaBridge	171:3a7713b1edbc	28	* Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge	171:3a7713b1edbc	29	* Products, Inc. Branding Policy.
AnnaBridge	171:3a7713b1edbc	30	*
AnnaBridge	171:3a7713b1edbc	31	* The mere transfer of this software does not imply any licenses
AnnaBridge	171:3a7713b1edbc	32	* of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge	171:3a7713b1edbc	33	* trademarks, maskwork rights, or any other form of intellectual
AnnaBridge	171:3a7713b1edbc	34	* property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge	171:3a7713b1edbc	35	* ownership rights.
AnnaBridge	171:3a7713b1edbc	36	*
AnnaBridge	171:3a7713b1edbc	37	*
AnnaBridge	171:3a7713b1edbc	38	* $Date: 2016-10-31 17:08:23 -0500 (Mon, 31 Oct 2016) $
AnnaBridge	171:3a7713b1edbc	39	* $Revision: 24858 $
AnnaBridge	171:3a7713b1edbc	40	*
AnnaBridge	171:3a7713b1edbc	41	*************************************************************************** */
AnnaBridge	171:3a7713b1edbc	42
AnnaBridge	171:3a7713b1edbc	43	/* ** Includes ** */
AnnaBridge	171:3a7713b1edbc	44	#include <stdint.h>
AnnaBridge	171:3a7713b1edbc	45
AnnaBridge	171:3a7713b1edbc	46	/* Define to prevent redundant inclusion */
AnnaBridge	171:3a7713b1edbc	47	#ifndef _MAX3263X_H_
AnnaBridge	171:3a7713b1edbc	48	#define _MAX3263X_H_
AnnaBridge	171:3a7713b1edbc	49
AnnaBridge	171:3a7713b1edbc	50
AnnaBridge	171:3a7713b1edbc	51	/**
AnnaBridge	171:3a7713b1edbc	52	* @ingroup cmsis_product
AnnaBridge	171:3a7713b1edbc	53	* @defgroup product_name MAX3263X
AnnaBridge	171:3a7713b1edbc	54	* @brief MAX3263X device specific definitions for the core, peripherals,
AnnaBridge	171:3a7713b1edbc	55	* features, memory, and IRQs.
AnnaBridge	171:3a7713b1edbc	56	* @details The <b><em>MAX32630/MAX32631</em></b> is an ARM®
AnnaBridge	171:3a7713b1edbc	57	* Cortex®-M4F 32-bit microcontroller with a floating point
AnnaBridge	171:3a7713b1edbc	58	* unit, ideal for the emerging category of wearable medical and
AnnaBridge	171:3a7713b1edbc	59	* fitness applications. The architecture combines ultra-low power
AnnaBridge	171:3a7713b1edbc	60	* high-efficiency signal processing functionality with
AnnaBridge	171:3a7713b1edbc	61	* significantly reduced power consumption and ease of use. The
AnnaBridge	171:3a7713b1edbc	62	* device features four powerful and flexible power modes. A
AnnaBridge	171:3a7713b1edbc	63	* peripheral management unit (PMU) enables intelligent peripheral
AnnaBridge	171:3a7713b1edbc	64	* control with up to six channels to significantly reduce power
AnnaBridge	171:3a7713b1edbc	65	* consumption. Built-in dynamic clock gating and
AnnaBridge	171:3a7713b1edbc	66	* firmware-controlled power gating allows the user to optimize
AnnaBridge	171:3a7713b1edbc	67	* power for the specific application. Multiple SPI, UART and
AnnaBridge	171:3a7713b1edbc	68	* I²C serial interfaces, as well as 1-Wire® master and
AnnaBridge	171:3a7713b1edbc	69	* USB, allow for interconnection to a wide variety of external
AnnaBridge	171:3a7713b1edbc	70	* sensors. A four-input, 10-bit ADC with selectable references is
AnnaBridge	171:3a7713b1edbc	71	* available to monitor analog input from external sensors and
AnnaBridge	171:3a7713b1edbc	72	* meters. The small 100-ball WLP package provides a tiny, 4.37mm x
AnnaBridge	171:3a7713b1edbc	73	* 4.37mm footprint. The <b><em>MAX32630/MAX32631</em></b> include
AnnaBridge	171:3a7713b1edbc	74	* a hardware AES engine. The <b>@em MAX32631</b> is a secure
AnnaBridge	171:3a7713b1edbc	75	* version of the <b>@em MAX32630</b>. It incorporates a trust
AnnaBridge	171:3a7713b1edbc	76	* protection unit (TPU) with encryption and advanced security
AnnaBridge	171:3a7713b1edbc	77	* features. These features include a modular arithmetic
AnnaBridge	171:3a7713b1edbc	78	* accelerator (MAA) for fast ECDSA, a hardware PRNG entropy
AnnaBridge	171:3a7713b1edbc	79	* generator, and a secure boot loader.
AnnaBridge	171:3a7713b1edbc	80	* @{
AnnaBridge	171:3a7713b1edbc	81	*/
AnnaBridge	171:3a7713b1edbc	82	#ifndef FALSE
AnnaBridge	171:3a7713b1edbc	83	/**
AnnaBridge	171:3a7713b1edbc	84	* @internal False
AnnaBridge	171:3a7713b1edbc	85	*/
AnnaBridge	171:3a7713b1edbc	86	#define FALSE (0)
AnnaBridge	171:3a7713b1edbc	87	#endif
AnnaBridge	171:3a7713b1edbc	88
AnnaBridge	171:3a7713b1edbc	89	#ifndef TRUE
AnnaBridge	171:3a7713b1edbc	90	/**
AnnaBridge	171:3a7713b1edbc	91	* @internal True
AnnaBridge	171:3a7713b1edbc	92	*/
AnnaBridge	171:3a7713b1edbc	93	#define TRUE (1)
AnnaBridge	171:3a7713b1edbc	94	#endif
AnnaBridge	171:3a7713b1edbc	95
AnnaBridge	171:3a7713b1edbc	96	/* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */
AnnaBridge	171:3a7713b1edbc	97	#if defined ( __GNUC__ )
AnnaBridge	171:3a7713b1edbc	98	#define __weak __attribute__((weak)) /*< GNUC weak function keyword. /
AnnaBridge	171:3a7713b1edbc	99	#elif defined ( __CC_ARM)
AnnaBridge	171:3a7713b1edbc	100	#define inline __inline /*< inline keyword for Keil compiler. /
AnnaBridge	171:3a7713b1edbc	101	#pragma anon_unions
AnnaBridge	171:3a7713b1edbc	102	#endif
AnnaBridge	171:3a7713b1edbc	103	/*@}/
AnnaBridge	171:3a7713b1edbc	104	/**
AnnaBridge	171:3a7713b1edbc	105	* @ingroup product_name
AnnaBridge	171:3a7713b1edbc	106	* @defgroup nvic_table Nested Interrupt Vector Table (NVIC)
AnnaBridge	171:3a7713b1edbc	107	* Device specific interrupt request NVIC entries.
AnnaBridge	171:3a7713b1edbc	108	* @{
AnnaBridge	171:3a7713b1edbc	109	*/
AnnaBridge	171:3a7713b1edbc	110	/**
AnnaBridge	171:3a7713b1edbc	111	* \MXIM_Device Nested Interrupt Vector Table (NVIC).
AnnaBridge	171:3a7713b1edbc	112	* @details
AnnaBridge	171:3a7713b1edbc	113	* NVIC Peripheral Entry numbers and Offsets are shown in the table below.
AnnaBridge	171:3a7713b1edbc	114	*
AnnaBridge	171:3a7713b1edbc	115	* \| Entry \| Offset \| Peripheral \|
AnnaBridge	171:3a7713b1edbc	116	* \|-------: \| ------: \| :------------------------------------ \|
AnnaBridge	171:3a7713b1edbc	117	* \| 0x10 \| 0x0040 \| CLKMAN \|
AnnaBridge	171:3a7713b1edbc	118	* \| 0x11 \| 0x0044 \| PWRMAN \|
AnnaBridge	171:3a7713b1edbc	119	* \| 0x12 \| 0x0048 \| Flash Controller \|
AnnaBridge	171:3a7713b1edbc	120	* \| 0x13 \| 0x004C \| RTC Counter match with Compare 0 \|
AnnaBridge	171:3a7713b1edbc	121	* \| 0x14 \| 0x0050 \| RTC Counter match with Compare 1 \|
AnnaBridge	171:3a7713b1edbc	122	* \| 0x15 \| 0x0054 \| RTC Prescaler interval compare match \|
AnnaBridge	171:3a7713b1edbc	123	* \| 0x16 \| 0x0058 \| RTC Overflow \|
AnnaBridge	171:3a7713b1edbc	124	* \| 0x17 \| 0x005C \| Peripheral Management Unit (PMU/DMA) \|
AnnaBridge	171:3a7713b1edbc	125	* \| 0x18 \| 0x0060 \| USB \|
AnnaBridge	171:3a7713b1edbc	126	* \| 0x19 \| 0x0064 \| AES \|
AnnaBridge	171:3a7713b1edbc	127	* \| 0x1A \| 0x0068 \| MAA \|
AnnaBridge	171:3a7713b1edbc	128	* \| 0x1B \| 0x006C \| Watchdog 0 timeout \|
AnnaBridge	171:3a7713b1edbc	129	* \| 0x1C \| 0x0070 \| Watchdog 0 pre-window (fed too early)\|
AnnaBridge	171:3a7713b1edbc	130	* \| 0x1D \| 0x0074 \| Watchdog 1 timeout \|
AnnaBridge	171:3a7713b1edbc	131	* \| 0x1E \| 0x0078 \| Watchdog 1 pre-window (fed too early)\|
AnnaBridge	171:3a7713b1edbc	132	* \| 0x1F \| 0x007C \| GPIO Port 0 \|
AnnaBridge	171:3a7713b1edbc	133	* \| 0x20 \| 0x0080 \| GPIO Port 1 \|
AnnaBridge	171:3a7713b1edbc	134	* \| 0x21 \| 0x0084 \| GPIO Port 2 \|
AnnaBridge	171:3a7713b1edbc	135	* \| 0x22 \| 0x0088 \| GPIO Port 3 \|
AnnaBridge	171:3a7713b1edbc	136	* \| 0x23 \| 0x008C \| GPIO Port 4 \|
AnnaBridge	171:3a7713b1edbc	137	* \| 0x24 \| 0x0090 \| GPIO Port 5 \|
AnnaBridge	171:3a7713b1edbc	138	* \| 0x25 \| 0x0094 \| GPIO Port 6 \|
AnnaBridge	171:3a7713b1edbc	139	* \| 0x26 \| 0x0098 \| Timer 0 (32-bit, 16-bit #0) \|
AnnaBridge	171:3a7713b1edbc	140	* \| 0x27 \| 0x009C \| Timer 0 (16-bit #1) \|
AnnaBridge	171:3a7713b1edbc	141	* \| 0x28 \| 0x00A0 \| Timer 1 (32-bit, 16-bit #0) \|
AnnaBridge	171:3a7713b1edbc	142	* \| 0x29 \| 0x00A4 \| Timer 1 (16-bit #1) \|
AnnaBridge	171:3a7713b1edbc	143	* \| 0x2A \| 0x00A8 \| Timer 2 (32-bit, 16-bit #0) \|
AnnaBridge	171:3a7713b1edbc	144	* \| 0x2B \| 0x00AC \| Timer 2 (16-bit #1) \|
AnnaBridge	171:3a7713b1edbc	145	* \| 0x2C \| 0x00B0 \| Timer 3 (32-bit, 16-bit #0) \|
AnnaBridge	171:3a7713b1edbc	146	* \| 0x2D \| 0x00B4 \| Timer 3 (16-bit #1) \|
AnnaBridge	171:3a7713b1edbc	147	* \| 0x2E \| 0x00B8 \| Timer 4 (32-bit, 16-bit #0) \|
AnnaBridge	171:3a7713b1edbc	148	* \| 0x2F \| 0x00BC \| Timer 4 (16-bit #1) \|
AnnaBridge	171:3a7713b1edbc	149	* \| 0x30 \| 0x00C0 \| Timer 5 (32-bit, 16-bit #0) \|
AnnaBridge	171:3a7713b1edbc	150	* \| 0x31 \| 0x00C4 \| Timer 5 (16-bit #1) \|
AnnaBridge	171:3a7713b1edbc	151	* \| 0x32 \| 0x00C8 \| UART 0 \|
AnnaBridge	171:3a7713b1edbc	152	* \| 0x33 \| 0x00CC \| UART 1 \|
AnnaBridge	171:3a7713b1edbc	153	* \| 0x34 \| 0x00D0 \| UART 2 \|
AnnaBridge	171:3a7713b1edbc	154	* \| 0x35 \| 0x00D4 \| UART 3 \|
AnnaBridge	171:3a7713b1edbc	155	* \| 0x36 \| 0x00D8 \| Pulse Trains \|
AnnaBridge	171:3a7713b1edbc	156	* \| 0x37 \| 0x00DC \| I2C Master 0 \|
AnnaBridge	171:3a7713b1edbc	157	* \| 0x38 \| 0x00E0 \| I2C Master 1 \|
AnnaBridge	171:3a7713b1edbc	158	* \| 0x39 \| 0x00E4 \| I2C Master 2 \|
AnnaBridge	171:3a7713b1edbc	159	* \| 0x3A \| 0x00E8 \| I2C Slave \|
AnnaBridge	171:3a7713b1edbc	160	* \| 0x3B \| 0x00EC \| SPI Master 0 \|
AnnaBridge	171:3a7713b1edbc	161	* \| 0x3C \| 0x00F0 \| SPI Master 1 \|
AnnaBridge	171:3a7713b1edbc	162	* \| 0x3D \| 0x00F4 \| SPI Master 2 \|
AnnaBridge	171:3a7713b1edbc	163	* \| 0x3E \| 0x00F8 \| SPI Bridge \|
AnnaBridge	171:3a7713b1edbc	164	* \| 0x3F \| 0x00FC \| 1-Wire Master \|
AnnaBridge	171:3a7713b1edbc	165	* \| 0x40 \| 0x0100 \| ADC \|
AnnaBridge	171:3a7713b1edbc	166	* \| 0x41 \| 0x0104 \| SPI Slave \|
AnnaBridge	171:3a7713b1edbc	167	* \| 0x42 \| 0x0108 \| GPIO Port 7 \|
AnnaBridge	171:3a7713b1edbc	168	* \| 0x43 \| 0x010C \| GPIO Port 8 \|
AnnaBridge	171:3a7713b1edbc	169	*/
AnnaBridge	171:3a7713b1edbc	170
AnnaBridge	171:3a7713b1edbc	171	/**
AnnaBridge	171:3a7713b1edbc	172	* Enumeration type of all \MXIM_Device NVIC entries.
AnnaBridge	171:3a7713b1edbc	173	*/
AnnaBridge	171:3a7713b1edbc	174	typedef enum {
AnnaBridge	171:3a7713b1edbc	175	NonMaskableInt_IRQn = -14, /*< ARM Core : Non-maskable IRQ /
AnnaBridge	171:3a7713b1edbc	176	HardFault_IRQn = -13, /*< ARM Core : Hard Fault IRQ /
AnnaBridge	171:3a7713b1edbc	177	MemoryManagement_IRQn = -12, /*< ARM Core : Memory Management IRQ /
AnnaBridge	171:3a7713b1edbc	178	BusFault_IRQn = -11, /*< ARM Core : Bus Fault IRQ /
AnnaBridge	171:3a7713b1edbc	179	UsageFault_IRQn = -10, /*< ARM Core : Usage Fault IRQ /
AnnaBridge	171:3a7713b1edbc	180	SVCall_IRQn = -5, /*< ARM Core : SVCall IRQ /
AnnaBridge	171:3a7713b1edbc	181	DebugMonitor_IRQn = -4, /*< ARM Core : Debug Monitor IRQ /
AnnaBridge	171:3a7713b1edbc	182	PendSV_IRQn = -2, /*< ARM Core : PendSV IRQ /
AnnaBridge	171:3a7713b1edbc	183	SysTick_IRQn = -1, /*< ARM Core : SysTick IRQ /
AnnaBridge	171:3a7713b1edbc	184	CLKMAN_IRQn = 0, /*< CLKMAN /
AnnaBridge	171:3a7713b1edbc	185	PWRMAN_IRQn, /*< PWRMAN /
AnnaBridge	171:3a7713b1edbc	186	FLC_IRQn, /*< Flash Controller /
AnnaBridge	171:3a7713b1edbc	187	RTC0_IRQn, /*< RTC Counter match with Compare 0 /
AnnaBridge	171:3a7713b1edbc	188	RTC1_IRQn, /*< RTC Counter match with Compare 1 /
AnnaBridge	171:3a7713b1edbc	189	RTC2_IRQn, /*< RTC Prescaler interval compare match /
AnnaBridge	171:3a7713b1edbc	190	RTC3_IRQn, /*< RTC Overflow /
AnnaBridge	171:3a7713b1edbc	191	PMU_IRQn, /*< Peripheral Management Unit (PMU/DMA) /
AnnaBridge	171:3a7713b1edbc	192	USB_IRQn, /*< USB /
AnnaBridge	171:3a7713b1edbc	193	AES_IRQn, /*< AES /
AnnaBridge	171:3a7713b1edbc	194	MAA_IRQn, /*< MAA /
AnnaBridge	171:3a7713b1edbc	195	WDT0_IRQn, /*< Watchdog 0 timeout /
AnnaBridge	171:3a7713b1edbc	196	WDT0_P_IRQn, /*< Watchdog 0 pre-window (fed too early) /
AnnaBridge	171:3a7713b1edbc	197	WDT1_IRQn, /*< Watchdog 1 timeout /
AnnaBridge	171:3a7713b1edbc	198	WDT1_P_IRQn, /*< Watchdog 1 pre-window (fed too early) /
AnnaBridge	171:3a7713b1edbc	199	GPIO_P0_IRQn, /*< GPIO Port 0 /
AnnaBridge	171:3a7713b1edbc	200	GPIO_P1_IRQn, /*< GPIO Port 1 /
AnnaBridge	171:3a7713b1edbc	201	GPIO_P2_IRQn, /*< GPIO Port 2 /
AnnaBridge	171:3a7713b1edbc	202	GPIO_P3_IRQn, /*< GPIO Port 3 /
AnnaBridge	171:3a7713b1edbc	203	GPIO_P4_IRQn, /*< GPIO Port 4 /
AnnaBridge	171:3a7713b1edbc	204	GPIO_P5_IRQn, /*< GPIO Port 5 /
AnnaBridge	171:3a7713b1edbc	205	GPIO_P6_IRQn, /*< GPIO Port 6 /
AnnaBridge	171:3a7713b1edbc	206	TMR0_0_IRQn, /*< Timer 0 (32-bit, 16-bit #0) /
AnnaBridge	171:3a7713b1edbc	207	TMR0_1_IRQn, /*< Timer 0 (16-bit #1) /
AnnaBridge	171:3a7713b1edbc	208	TMR1_0_IRQn, /*< Timer 1 (32-bit, 16-bit #0) /
AnnaBridge	171:3a7713b1edbc	209	TMR1_1_IRQn, /*< Timer 1 (16-bit #1) /
AnnaBridge	171:3a7713b1edbc	210	TMR2_0_IRQn, /*< Timer 2 (32-bit, 16-bit #0) /
AnnaBridge	171:3a7713b1edbc	211	TMR2_1_IRQn, /*< Timer 2 (16-bit #1) /
AnnaBridge	171:3a7713b1edbc	212	TMR3_0_IRQn, /*< Timer 3 (32-bit, 16-bit #0) /
AnnaBridge	171:3a7713b1edbc	213	TMR3_1_IRQn, /*< Timer 3 (16-bit #1) /
AnnaBridge	171:3a7713b1edbc	214	TMR4_0_IRQn, /*< Timer 4 (32-bit, 16-bit #0) /
AnnaBridge	171:3a7713b1edbc	215	TMR4_1_IRQn, /*< Timer 4 (16-bit #1) /
AnnaBridge	171:3a7713b1edbc	216	TMR5_0_IRQn, /*< Timer 5 (32-bit, 16-bit #0) /
AnnaBridge	171:3a7713b1edbc	217	TMR5_1_IRQn, /*< Timer 5 (16-bit #1) /
AnnaBridge	171:3a7713b1edbc	218	UART0_IRQn, /*< UART 0 /
AnnaBridge	171:3a7713b1edbc	219	UART1_IRQn, /*< UART 1 /
AnnaBridge	171:3a7713b1edbc	220	UART2_IRQn, /*< UART 2 /
AnnaBridge	171:3a7713b1edbc	221	UART3_IRQn, /*< UART 3 /
AnnaBridge	171:3a7713b1edbc	222	PT_IRQn, /*< Pulse Trains /
AnnaBridge	171:3a7713b1edbc	223	I2CM0_IRQn, /*< I2C Master 0 /
AnnaBridge	171:3a7713b1edbc	224	I2CM1_IRQn, /*< I2C Master 1 /
AnnaBridge	171:3a7713b1edbc	225	I2CM2_IRQn, /*< I2C Master 2 /
AnnaBridge	171:3a7713b1edbc	226	I2CS_IRQn, /*< I2C Slave /
AnnaBridge	171:3a7713b1edbc	227	SPIM0_IRQn, /*< SPI Master 0 /
AnnaBridge	171:3a7713b1edbc	228	SPIM1_IRQn, /*< SPI Master 1 /
AnnaBridge	171:3a7713b1edbc	229	SPIM2_IRQn, /*< SPI Master 2 /
AnnaBridge	171:3a7713b1edbc	230	SPIB_IRQn, /*< SPI Bridge /
AnnaBridge	171:3a7713b1edbc	231	OWM_IRQn, /*< 1-Wire Master /
AnnaBridge	171:3a7713b1edbc	232	AFE_IRQn, /*< ADC /
AnnaBridge	171:3a7713b1edbc	233	SPIS_IRQn, /*< SPI Slave /
AnnaBridge	171:3a7713b1edbc	234	GPIO_P7_IRQn, /*< GPIO Port 7 /
AnnaBridge	171:3a7713b1edbc	235	GPIO_P8_IRQn, /*< GPIO Port 8 /
AnnaBridge	171:3a7713b1edbc	236	MXC_IRQ_EXT_COUNT /*< Total number of non-core IRQ vectors. /
AnnaBridge	171:3a7713b1edbc	237	} IRQn_Type;
AnnaBridge	171:3a7713b1edbc	238
AnnaBridge	171:3a7713b1edbc	239	#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16) /*< Total number of device IRQs inclusive of core and non-core IRQ vectors. /
AnnaBridge	171:3a7713b1edbc	240	/*@}end of group nvic_table/
AnnaBridge	171:3a7713b1edbc	241
AnnaBridge	171:3a7713b1edbc	242	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	243	/* ================ Processor and Core Peripheral Section ================ */
AnnaBridge	171:3a7713b1edbc	244	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	245	/**
AnnaBridge	171:3a7713b1edbc	246	* @ingroup product_name
AnnaBridge	171:3a7713b1edbc	247	* @defgroup Cortex_M4 Cortex-M Configuration
AnnaBridge	171:3a7713b1edbc	248	* @{
AnnaBridge	171:3a7713b1edbc	249	*/
AnnaBridge	171:3a7713b1edbc	250	/* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */
AnnaBridge	171:3a7713b1edbc	251	#define __CM4_REV 0x0100 /*< Cortex-M4 Core Revision /
AnnaBridge	171:3a7713b1edbc	252	#define __MPU_PRESENT 1 /*< MPU is present /
AnnaBridge	171:3a7713b1edbc	253	#define __NVIC_PRIO_BITS 3 /*< Number of Bits used for IRQ Priority Levels /
AnnaBridge	171:3a7713b1edbc	254	#define __Vendor_SysTickConfig 0 /*< Using standard CMSIS SysTickConfig /
AnnaBridge	171:3a7713b1edbc	255	#define __FPU_PRESENT 1 /*< FPU is Present /
AnnaBridge	171:3a7713b1edbc	256	/*@} end of ingroup Cortex_M4/
AnnaBridge	171:3a7713b1edbc	257	#include <core_cm4.h> /!< Cortex-M4 processor and core peripherals /
AnnaBridge	171:3a7713b1edbc	258	#include "system_max3263x.h" /!< System Header /
AnnaBridge	171:3a7713b1edbc	259
AnnaBridge	171:3a7713b1edbc	260
AnnaBridge	171:3a7713b1edbc	261	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	262	/* ================== Device Specific Memory Section ================== */
AnnaBridge	171:3a7713b1edbc	263	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	264	/**
AnnaBridge	171:3a7713b1edbc	265	* @ingroup product_name
AnnaBridge	171:3a7713b1edbc	266	* @{
AnnaBridge	171:3a7713b1edbc	267	*/
AnnaBridge	171:3a7713b1edbc	268	#define MXC_FLASH_MEM_BASE 0x00000000UL /*< Internal Flash Memory Start Address. /
AnnaBridge	171:3a7713b1edbc	269	#define MXC_FLASH_PAGE_SIZE 0x00002000UL /*< Internal Flash Memory Page Size. /
AnnaBridge	171:3a7713b1edbc	270	#define MXC_FLASH_FULL_MEM_SIZE 0x00200000UL /*< Internal Flash Memory Size. /
AnnaBridge	171:3a7713b1edbc	271	#define MXC_SYS_MEM_BASE 0x20000000UL /*< System Memory Start Address. /
AnnaBridge	171:3a7713b1edbc	272	#define MXC_SRAM_FULL_MEM_SIZE 0x00080000UL /*< Internal SRAM Size. /
AnnaBridge	171:3a7713b1edbc	273	#define MXC_EXT_FLASH_MEM_BASE 0x10000000UL /*< External Flash Memory Start Address, SPIX interface. /
AnnaBridge	171:3a7713b1edbc	274
AnnaBridge	171:3a7713b1edbc	275	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	276	/* ================ Device Specific Peripheral Section ================ */
AnnaBridge	171:3a7713b1edbc	277	/* ================================================================================ */
AnnaBridge	171:3a7713b1edbc	278
AnnaBridge	171:3a7713b1edbc	279
AnnaBridge	171:3a7713b1edbc	280	/*
AnnaBridge	171:3a7713b1edbc	281	Base addresses and configuration settings for all MAX3263X peripheral modules.
AnnaBridge	171:3a7713b1edbc	282	*/
AnnaBridge	171:3a7713b1edbc	283
AnnaBridge	171:3a7713b1edbc	284
AnnaBridge	171:3a7713b1edbc	285	/* *************************************************************************** */
AnnaBridge	171:3a7713b1edbc	286	/* System Manager Settings */
AnnaBridge	171:3a7713b1edbc	287
AnnaBridge	171:3a7713b1edbc	288	#define MXC_BASE_SYSMAN ((uint32_t)0x40000000UL)
AnnaBridge	171:3a7713b1edbc	289	#define MXC_SYSMAN ((mxc_sysman_regs_t *)MXC_BASE_SYSMAN)
AnnaBridge	171:3a7713b1edbc	290
AnnaBridge	171:3a7713b1edbc	291
AnnaBridge	171:3a7713b1edbc	292
AnnaBridge	171:3a7713b1edbc	293	/* *************************************************************************** */
AnnaBridge	171:3a7713b1edbc	294	/* System Clock Manager */
AnnaBridge	171:3a7713b1edbc	295
AnnaBridge	171:3a7713b1edbc	296	#define MXC_BASE_CLKMAN ((uint32_t)0x40000400UL)
AnnaBridge	171:3a7713b1edbc	297	#define MXC_CLKMAN ((mxc_clkman_regs_t *)MXC_BASE_CLKMAN)
AnnaBridge	171:3a7713b1edbc	298
AnnaBridge	171:3a7713b1edbc	299
AnnaBridge	171:3a7713b1edbc	300
AnnaBridge	171:3a7713b1edbc	301	/* *************************************************************************** */
AnnaBridge	171:3a7713b1edbc	302	/* System Power Manager */
AnnaBridge	171:3a7713b1edbc	303
AnnaBridge	171:3a7713b1edbc	304	#define MXC_BASE_PWRMAN ((uint32_t)0x40000800UL)
AnnaBridge	171:3a7713b1edbc	305	#define MXC_PWRMAN ((mxc_pwrman_regs_t *)MXC_BASE_PWRMAN)
AnnaBridge	171:3a7713b1edbc	306
AnnaBridge	171:3a7713b1edbc	307
AnnaBridge	171:3a7713b1edbc	308
AnnaBridge	171:3a7713b1edbc	309	/* *************************************************************************** */
AnnaBridge	171:3a7713b1edbc	310	/* Real Time Clock */
AnnaBridge	171:3a7713b1edbc	311
AnnaBridge	171:3a7713b1edbc	312	#define MXC_BASE_RTCTMR ((uint32_t)0x40000A00UL)
AnnaBridge	171:3a7713b1edbc	313	#define MXC_RTCTMR ((mxc_rtctmr_regs_t *)MXC_BASE_RTCTMR)
AnnaBridge	171:3a7713b1edbc	314	#define MXC_BASE_RTCCFG ((uint32_t)0x40000A70UL)
AnnaBridge	171:3a7713b1edbc	315	#define MXC_RTCCFG ((mxc_rtccfg_regs_t *)MXC_BASE_RTCCFG)
AnnaBridge	171:3a7713b1edbc	316
AnnaBridge	171:3a7713b1edbc	317	#define MXC_RTCTMR_GET_IRQ(i) (IRQn_Type)(i == 0 ? RTC0_IRQn : \
AnnaBridge	171:3a7713b1edbc	318	i == 1 ? RTC1_IRQn : \
AnnaBridge	171:3a7713b1edbc	319	i == 2 ? RTC2_IRQn : \
AnnaBridge	171:3a7713b1edbc	320	i == 3 ? RTC3_IRQn : 0)
AnnaBridge	171:3a7713b1edbc	321
AnnaBridge	171:3a7713b1edbc	322
AnnaBridge	171:3a7713b1edbc	323
AnnaBridge	171:3a7713b1edbc	324	/* *************************************************************************** */
AnnaBridge	171:3a7713b1edbc	325	/* Power Sequencer */
AnnaBridge	171:3a7713b1edbc	326
AnnaBridge	171:3a7713b1edbc	327	#define MXC_BASE_PWRSEQ ((uint32_t)0x40000A30UL)
AnnaBridge	171:3a7713b1edbc	328	#define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ)
AnnaBridge	171:3a7713b1edbc	329
AnnaBridge	171:3a7713b1edbc	330
AnnaBridge	171:3a7713b1edbc	331
AnnaBridge	171:3a7713b1edbc	332	/* *************************************************************************** */
AnnaBridge	171:3a7713b1edbc	333	/* System I/O Manager */
AnnaBridge	171:3a7713b1edbc	334	/*@} end of ingroup product_name/
AnnaBridge	171:3a7713b1edbc	335	/**
AnnaBridge	171:3a7713b1edbc	336	* @ingroup ioman_registers
AnnaBridge	171:3a7713b1edbc	337	* @{
AnnaBridge	171:3a7713b1edbc	338	*/
AnnaBridge	171:3a7713b1edbc	339	#define MXC_BASE_IOMAN ((uint32_t)0x40000C00UL) /*< Base Peripheral Address for IOMAN /
AnnaBridge	171:3a7713b1edbc	340	#define MXC_IOMAN ((mxc_ioman_regs_t )MXC_BASE_IOMAN) /< Pointer to the #mxc_ioman_regs_t structure representing the IOMAN Registers. /
AnnaBridge	171:3a7713b1edbc	341	/*@}/
AnnaBridge	171:3a7713b1edbc	342
AnnaBridge	171:3a7713b1edbc	343	/**
AnnaBridge	171:3a7713b1edbc	344	* @ingroup product_name
AnnaBridge	171:3a7713b1edbc	345	* @{
AnnaBridge	171:3a7713b1edbc	346	*/
AnnaBridge	171:3a7713b1edbc	347	/* *************************************************************************** */
AnnaBridge	171:3a7713b1edbc	348	/* Shadow Trim Registers */
AnnaBridge	171:3a7713b1edbc	349
AnnaBridge	171:3a7713b1edbc	350	#define MXC_BASE_TRIM ((uint32_t)0x40001000UL)
AnnaBridge	171:3a7713b1edbc	351	#define MXC_TRIM ((mxc_trim_regs_t *)MXC_BASE_TRIM)
AnnaBridge	171:3a7713b1edbc	352
AnnaBridge	171:3a7713b1edbc	353
AnnaBridge	171:3a7713b1edbc	354
AnnaBridge	171:3a7713b1edbc	355	/* *************************************************************************** */
AnnaBridge	171:3a7713b1edbc	356	/* Flash Controller */
AnnaBridge	171:3a7713b1edbc	357
AnnaBridge	171:3a7713b1edbc	358	#define MXC_BASE_FLC ((uint32_t)0x40002000UL)
AnnaBridge	171:3a7713b1edbc	359	#define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC)
AnnaBridge	171:3a7713b1edbc	360
AnnaBridge	171:3a7713b1edbc	361	#define MXC_FLC_PAGE_SIZE_SHIFT (13)
AnnaBridge	171:3a7713b1edbc	362	#define MXC_FLC_PAGE_SIZE (1 << MXC_FLC_PAGE_SIZE_SHIFT)
AnnaBridge	171:3a7713b1edbc	363	#define MXC_FLC_PAGE_ERASE_MSK ((~(1 << (MXC_FLC_PAGE_SIZE_SHIFT - 1))) >> MXC_FLC_PAGE_SIZE_SHIFT) << MXC_FLC_PAGE_SIZE_SHIFT
AnnaBridge	171:3a7713b1edbc	364
AnnaBridge	171:3a7713b1edbc	365
AnnaBridge	171:3a7713b1edbc	366
AnnaBridge	171:3a7713b1edbc	367	/* *************************************************************************** */
AnnaBridge	171:3a7713b1edbc	368	/* Instruction Cache */
AnnaBridge	171:3a7713b1edbc	369
AnnaBridge	171:3a7713b1edbc	370	#define MXC_BASE_ICC ((uint32_t)0x40003000UL)
AnnaBridge	171:3a7713b1edbc	371	#define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC)
AnnaBridge	171:3a7713b1edbc	372
AnnaBridge	171:3a7713b1edbc	373
AnnaBridge	171:3a7713b1edbc	374	/*@} end of ingroup product_name/
AnnaBridge	171:3a7713b1edbc	375	/* *************************************************************************** */
AnnaBridge	171:3a7713b1edbc	376	/* SPI XIP Interface */
AnnaBridge	171:3a7713b1edbc	377	/**
AnnaBridge	171:3a7713b1edbc	378	* @ingroup spix_registers
AnnaBridge	171:3a7713b1edbc	379	* @{
AnnaBridge	171:3a7713b1edbc	380	*/
AnnaBridge	171:3a7713b1edbc	381	#define MXC_BASE_SPIX ((uint32_t)0x40004000UL) /*< SPIX Base Peripheral Address. /
AnnaBridge	171:3a7713b1edbc	382	#define MXC_SPIX ((mxc_spix_regs_t )MXC_BASE_SPIX) /< SPIX pointer to the #mxc_spix_regs_t register structure type. /
AnnaBridge	171:3a7713b1edbc	383	/*@} end of ingroup spix_registers/
AnnaBridge	171:3a7713b1edbc	384
AnnaBridge	171:3a7713b1edbc	385	/**
AnnaBridge	171:3a7713b1edbc	386	* @ingroup product_name
AnnaBridge	171:3a7713b1edbc	387	* @{
AnnaBridge	171:3a7713b1edbc	388	*/
AnnaBridge	171:3a7713b1edbc	389	/* *************************************************************************** */
AnnaBridge	171:3a7713b1edbc	390	/* Peripheral Management Unit */
AnnaBridge	171:3a7713b1edbc	391
AnnaBridge	171:3a7713b1edbc	392	#define MXC_CFG_PMU_CHANNELS (6)
AnnaBridge	171:3a7713b1edbc	393
AnnaBridge	171:3a7713b1edbc	394	#define MXC_BASE_PMU0 ((uint32_t)0x40005000UL)
AnnaBridge	171:3a7713b1edbc	395	#define MXC_PMU0 ((mxc_pmu_regs_t *)MXC_BASE_PMU0)
AnnaBridge	171:3a7713b1edbc	396	#define MXC_BASE_PMU1 ((uint32_t)0x40005020UL)
AnnaBridge	171:3a7713b1edbc	397	#define MXC_PMU1 ((mxc_pmu_regs_t *)MXC_BASE_PMU1)
AnnaBridge	171:3a7713b1edbc	398	#define MXC_BASE_PMU2 ((uint32_t)0x40005040UL)
AnnaBridge	171:3a7713b1edbc	399	#define MXC_PMU2 ((mxc_pmu_regs_t *)MXC_BASE_PMU2)
AnnaBridge	171:3a7713b1edbc	400	#define MXC_BASE_PMU3 ((uint32_t)0x40005060UL)
AnnaBridge	171:3a7713b1edbc	401	#define MXC_PMU3 ((mxc_pmu_regs_t *)MXC_BASE_PMU3)
AnnaBridge	171:3a7713b1edbc	402	#define MXC_BASE_PMU4 ((uint32_t)0x40005080UL)
AnnaBridge	171:3a7713b1edbc	403	#define MXC_PMU4 ((mxc_pmu_regs_t *)MXC_BASE_PMU4)
AnnaBridge	171:3a7713b1edbc	404	#define MXC_BASE_PMU5 ((uint32_t)0x400050A0UL)
AnnaBridge	171:3a7713b1edbc	405	#define MXC_PMU5 ((mxc_pmu_regs_t *)MXC_BASE_PMU5)
AnnaBridge	171:3a7713b1edbc	406
AnnaBridge	171:3a7713b1edbc	407	#define MXC_PMU_GET_BASE(i) ((i) == 0 ? MXC_BASE_PMU0 : \
AnnaBridge	171:3a7713b1edbc	408	(i) == 1 ? MXC_BASE_PMU1 : \
AnnaBridge	171:3a7713b1edbc	409	(i) == 2 ? MXC_BASE_PMU2 : \
AnnaBridge	171:3a7713b1edbc	410	(i) == 3 ? MXC_BASE_PMU3 : \
AnnaBridge	171:3a7713b1edbc	411	(i) == 4 ? MXC_BASE_PMU4 : \
AnnaBridge	171:3a7713b1edbc	412	(i) == 5 ? MXC_BASE_PMU5 : 0)
AnnaBridge	171:3a7713b1edbc	413
AnnaBridge	171:3a7713b1edbc	414	#define MXC_PMU_GET_PMU(i) ((i) == 0 ? MXC_PMU0 : \
AnnaBridge	171:3a7713b1edbc	415	(i) == 1 ? MXC_PMU1 : \
AnnaBridge	171:3a7713b1edbc	416	(i) == 2 ? MXC_PMU2 : \
AnnaBridge	171:3a7713b1edbc	417	(i) == 3 ? MXC_PMU3 : \
AnnaBridge	171:3a7713b1edbc	418	(i) == 4 ? MXC_PMU4 : \
AnnaBridge	171:3a7713b1edbc	419	(i) == 5 ? MXC_PMU5 : 0)
AnnaBridge	171:3a7713b1edbc	420
AnnaBridge	171:3a7713b1edbc	421	#define MXC_PMU_GET_IDX(p) ((p) == MXC_PMU0 ? 0 : \
AnnaBridge	171:3a7713b1edbc	422	(p) == MXC_PMU1 ? 1 : \
AnnaBridge	171:3a7713b1edbc	423	(p) == MXC_PMU2 ? 2 : \
AnnaBridge	171:3a7713b1edbc	424	(p) == MXC_PMU3 ? 3 : \
AnnaBridge	171:3a7713b1edbc	425	(p) == MXC_PMU4 ? 4 : \
AnnaBridge	171:3a7713b1edbc	426	(p) == MXC_PMU5 ? 5 : -1)
AnnaBridge	171:3a7713b1edbc	427
AnnaBridge	171:3a7713b1edbc	428	/* *************************************************************************** */
AnnaBridge	171:3a7713b1edbc	429	/* USB Device Controller */
AnnaBridge	171:3a7713b1edbc	430
AnnaBridge	171:3a7713b1edbc	431	#define MXC_BASE_USB ((uint32_t)0x40100000UL)
AnnaBridge	171:3a7713b1edbc	432	#define MXC_USB ((mxc_usb_regs_t *)MXC_BASE_USB)
AnnaBridge	171:3a7713b1edbc	433
AnnaBridge	171:3a7713b1edbc	434	#define MXC_USB_MAX_PACKET (64)
AnnaBridge	171:3a7713b1edbc	435	#define MXC_USB_NUM_EP (8)
AnnaBridge	171:3a7713b1edbc	436
AnnaBridge	171:3a7713b1edbc	437
AnnaBridge	171:3a7713b1edbc	438
AnnaBridge	171:3a7713b1edbc	439	/* *************************************************************************** */
AnnaBridge	171:3a7713b1edbc	440	/* CRC-16/CRC-32 Engine */
AnnaBridge	171:3a7713b1edbc	441
AnnaBridge	171:3a7713b1edbc	442	#define MXC_BASE_CRC ((uint32_t)0x40006000UL)
AnnaBridge	171:3a7713b1edbc	443	#define MXC_CRC ((mxc_crc_regs_t *)MXC_BASE_CRC)
AnnaBridge	171:3a7713b1edbc	444	#define MXC_BASE_CRC_DATA ((uint32_t)0x40101000UL)
AnnaBridge	171:3a7713b1edbc	445	#define MXC_CRC_DATA ((mxc_crc_data_regs_t *)MXC_BASE_CRC_DATA)
AnnaBridge	171:3a7713b1edbc	446
AnnaBridge	171:3a7713b1edbc	447	/* *************************************************************************** */
AnnaBridge	171:3a7713b1edbc	448	/* Pseudo-random number generator (PRNG) */
AnnaBridge	171:3a7713b1edbc	449
AnnaBridge	171:3a7713b1edbc	450	#define MXC_BASE_PRNG ((uint32_t)0x40007000UL)
AnnaBridge	171:3a7713b1edbc	451	#define MXC_PRNG ((mxc_prng_regs_t *)MXC_BASE_PRNG)
AnnaBridge	171:3a7713b1edbc	452
AnnaBridge	171:3a7713b1edbc	453	/* *************************************************************************** */
AnnaBridge	171:3a7713b1edbc	454	/* AES Cryptographic Engine */
AnnaBridge	171:3a7713b1edbc	455
AnnaBridge	171:3a7713b1edbc	456	#define MXC_BASE_AES ((uint32_t)0x40007400UL)
AnnaBridge	171:3a7713b1edbc	457	#define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES)
AnnaBridge	171:3a7713b1edbc	458	#define MXC_BASE_AES_MEM ((uint32_t)0x40102000UL)
AnnaBridge	171:3a7713b1edbc	459	#define MXC_AES_MEM ((mxc_aes_mem_regs_t *)MXC_BASE_AES_MEM)
AnnaBridge	171:3a7713b1edbc	460
AnnaBridge	171:3a7713b1edbc	461	/* *************************************************************************** */
AnnaBridge	171:3a7713b1edbc	462	/* MAA Cryptographic Engine */
AnnaBridge	171:3a7713b1edbc	463
AnnaBridge	171:3a7713b1edbc	464	#define MXC_BASE_MAA ((uint32_t)0x40007800UL)
AnnaBridge	171:3a7713b1edbc	465	#define MXC_MAA ((mxc_maa_regs_t *)MXC_BASE_MAA)
AnnaBridge	171:3a7713b1edbc	466	#define MXC_BASE_MAA_MEM ((uint32_t)0x40102800UL)
AnnaBridge	171:3a7713b1edbc	467	#define MXC_MAA_MEM ((mxc_maa_mem_regs_t *)MXC_BASE_MAA_MEM)
AnnaBridge	171:3a7713b1edbc	468
AnnaBridge	171:3a7713b1edbc	469	/* *************************************************************************** */
AnnaBridge	171:3a7713b1edbc	470	/* Trust Protection Unit (TPU) */
AnnaBridge	171:3a7713b1edbc	471
AnnaBridge	171:3a7713b1edbc	472	#define MXC_BASE_TPU ((uint32_t)0x40007000UL)
AnnaBridge	171:3a7713b1edbc	473	#define MXC_TPU ((mxc_tpu_regs_t *)MXC_BASE_TPU)
AnnaBridge	171:3a7713b1edbc	474	#define MXC_BASE_TPU_TSR ((uint32_t)0x40007C00UL)
AnnaBridge	171:3a7713b1edbc	475	#define MXC_TPU_TSR ((mxc_tpu_tsr_regs_t *)MXC_BASE_TPU_TSR)
AnnaBridge	171:3a7713b1edbc	476	/*@} end of ingroup product_name/
AnnaBridge	171:3a7713b1edbc	477	/* *************************************************************************** */
AnnaBridge	171:3a7713b1edbc	478	/* Watchdog Timers */
AnnaBridge	171:3a7713b1edbc	479	/**
AnnaBridge	171:3a7713b1edbc	480	* @ingroup wdt_registers
AnnaBridge	171:3a7713b1edbc	481	* @{
AnnaBridge	171:3a7713b1edbc	482	*/
AnnaBridge	171:3a7713b1edbc	483	#define MXC_CFG_WDT_INSTANCES (2) /*< Define for the number of timers on the \MXIM_Device /
AnnaBridge	171:3a7713b1edbc	484
AnnaBridge	171:3a7713b1edbc	485	#define MXC_BASE_WDT0 ((uint32_t)0x40008000UL) /*< Base Peripheral Address for WDT 0 /
AnnaBridge	171:3a7713b1edbc	486	#define MXC_WDT0 ((mxc_wdt_regs_t )MXC_BASE_WDT0) /< Pointer to the #mxc_wdt_regs_t structure representing WDT0 Registers. /
AnnaBridge	171:3a7713b1edbc	487	#define MXC_BASE_WDT1 ((uint32_t)0x40009000UL) /*< Base Peripheral Address for WDT 1 /
AnnaBridge	171:3a7713b1edbc	488	#define MXC_WDT1 ((mxc_wdt_regs_t )MXC_BASE_WDT1) /< Pointer to the #mxc_wdt_regs_t structure representing WDT1 Registers. /
AnnaBridge	171:3a7713b1edbc	489	/**
AnnaBridge	171:3a7713b1edbc	490	* Macro that returns the WDT[i] IRQ, where i=0 to i < #MXC_CFG_WDT_INSTANCES.
AnnaBridge	171:3a7713b1edbc	491	*/
AnnaBridge	171:3a7713b1edbc	492	#define MXC_WDT_GET_IRQ(i) (IRQn_Type)((i) == 0 ? WDT0_IRQn : \
AnnaBridge	171:3a7713b1edbc	493	(i) == 1 ? WDT1_IRQn : 0)
AnnaBridge	171:3a7713b1edbc	494
AnnaBridge	171:3a7713b1edbc	495	#define MXC_WDT_GET_IRQ_P(i) (IRQn_Type)((i) == 0 ? WDT0_P_IRQn : \
AnnaBridge	171:3a7713b1edbc	496	(i) == 1 ? WDT1_P_IRQn : 0)
AnnaBridge	171:3a7713b1edbc	497	/**
AnnaBridge	171:3a7713b1edbc	498	* Macro to return the base address for a requested Watchdog Timer index number.
AnnaBridge	171:3a7713b1edbc	499	* @p i WDT instance number.
AnnaBridge	171:3a7713b1edbc	500	* @p returns the base peripheral address for the requested Watchdog Timer instance.
AnnaBridge	171:3a7713b1edbc	501	*/
AnnaBridge	171:3a7713b1edbc	502	#define MXC_WDT_GET_BASE(i) ((i) == 0 ? MXC_BASE_WDT0 : \
AnnaBridge	171:3a7713b1edbc	503	(i) == 1 ? MXC_BASE_WDT1 : 0)
AnnaBridge	171:3a7713b1edbc	504	/**
AnnaBridge	171:3a7713b1edbc	505	* Macro to return a pointer to the #mxc_tmr_regs_t object for the requested Watchdog Timer.
AnnaBridge	171:3a7713b1edbc	506	* @p i Watchdog Timer instance number.
AnnaBridge	171:3a7713b1edbc	507	* @p returns a pointer to a #mxc_wdt_regs_t for the requested WDT number.
AnnaBridge	171:3a7713b1edbc	508	*/
AnnaBridge	171:3a7713b1edbc	509	#define MXC_WDT_GET_WDT(i) ((i) == 0 ? MXC_WDT0 : \
AnnaBridge	171:3a7713b1edbc	510	(i) == 1 ? MXC_WDT1 : 0)
AnnaBridge	171:3a7713b1edbc	511	/**
AnnaBridge	171:3a7713b1edbc	512	* Macro to return the index number for a given #mxc_wdt_regs_t structure.
AnnaBridge	171:3a7713b1edbc	513	* @p p pointer to a #mxc_wdt_regs_t structure.
AnnaBridge	171:3a7713b1edbc	514	* @p returns a watchdog timer instance number.
AnnaBridge	171:3a7713b1edbc	515	*/
AnnaBridge	171:3a7713b1edbc	516	#define MXC_WDT_GET_IDX(i) ((i) == MXC_WDT0 ? 0: \
AnnaBridge	171:3a7713b1edbc	517	(i) == MXC_WDT1 ? 1: -1)
AnnaBridge	171:3a7713b1edbc	518
AnnaBridge	171:3a7713b1edbc	519	/*@} end of ingroup wdt_registers /
AnnaBridge	171:3a7713b1edbc	520	/* *************************************************************************** */
AnnaBridge	171:3a7713b1edbc	521	/* Always-On Watchdog Timer */
AnnaBridge	171:3a7713b1edbc	522	/**
AnnaBridge	171:3a7713b1edbc	523	* @ingroup wdt2_registers
AnnaBridge	171:3a7713b1edbc	524	* @{
AnnaBridge	171:3a7713b1edbc	525	*/
AnnaBridge	171:3a7713b1edbc	526	#define MXC_BASE_WDT2 ((uint32_t)0x40007C60UL) /*< Base Peripheral Address for WDT 2 /
AnnaBridge	171:3a7713b1edbc	527	#define MXC_WDT2 ((mxc_wdt2_regs_t )MXC_BASE_WDT2) /< Pointer to the #mxc_wdt2_regs_t structure representing the WDT2 hardware registers. /
AnnaBridge	171:3a7713b1edbc	528	/*@} end of ingroup wdt2_registers /
AnnaBridge	171:3a7713b1edbc	529
AnnaBridge	171:3a7713b1edbc	530
AnnaBridge	171:3a7713b1edbc	531	/* *************************************************************************** */
AnnaBridge	171:3a7713b1edbc	532	/* General Purpose I/O Ports (GPIO) */
AnnaBridge	171:3a7713b1edbc	533	/**
AnnaBridge	171:3a7713b1edbc	534	* @ingroup gpio_registers
AnnaBridge	171:3a7713b1edbc	535	* @{
AnnaBridge	171:3a7713b1edbc	536	*/
AnnaBridge	171:3a7713b1edbc	537	#define MXC_GPIO_NUM_PORTS (9) /*< Number of GPIO Ports for the \MXIM_Device. /
AnnaBridge	171:3a7713b1edbc	538	#define MXC_GPIO_MAX_PINS_PER_PORT (8) /*< Number of port pins per port for the \MXIM_Device /
AnnaBridge	171:3a7713b1edbc	539
AnnaBridge	171:3a7713b1edbc	540	#define MXC_BASE_GPIO ((uint32_t)0x4000A000UL) /*< GPIO Base Peripheral Offset /
AnnaBridge	171:3a7713b1edbc	541	#define MXC_GPIO ((mxc_gpio_regs_t )MXC_BASE_GPIO) /< Pointer to the #mxc_gpio_regs_t object representing GPIO Registers. /
AnnaBridge	171:3a7713b1edbc	542	/**
AnnaBridge	171:3a7713b1edbc	543	* Macro that returns the GPIO[i] IRQ, where i=0 to i < #MXC_GPIO_NUM_PORTS.
AnnaBridge	171:3a7713b1edbc	544	*/
AnnaBridge	171:3a7713b1edbc	545	#define MXC_GPIO_GET_IRQ(i) (IRQn_Type)((i) == 0 ? GPIO_P0_IRQn : \
AnnaBridge	171:3a7713b1edbc	546	(i) == 1 ? GPIO_P1_IRQn : \
AnnaBridge	171:3a7713b1edbc	547	(i) == 2 ? GPIO_P2_IRQn : \
AnnaBridge	171:3a7713b1edbc	548	(i) == 3 ? GPIO_P3_IRQn : \
AnnaBridge	171:3a7713b1edbc	549	(i) == 4 ? GPIO_P4_IRQn : \
AnnaBridge	171:3a7713b1edbc	550	(i) == 5 ? GPIO_P5_IRQn : \
AnnaBridge	171:3a7713b1edbc	551	(i) == 6 ? GPIO_P6_IRQn : \
AnnaBridge	171:3a7713b1edbc	552	(i) == 7 ? GPIO_P7_IRQn : \
AnnaBridge	171:3a7713b1edbc	553	(i) == 8 ? GPIO_P8_IRQn : 0)
AnnaBridge	171:3a7713b1edbc	554
AnnaBridge	171:3a7713b1edbc	555	/*@} end of ingroup gpio_registers /
AnnaBridge	171:3a7713b1edbc	556
AnnaBridge	171:3a7713b1edbc	557	/* *************************************************************************** */
AnnaBridge	171:3a7713b1edbc	558	/* 16/32 bit Timer/Counters */
AnnaBridge	171:3a7713b1edbc	559	/**
AnnaBridge	171:3a7713b1edbc	560	* @ingroup tmr_registers
AnnaBridge	171:3a7713b1edbc	561	* @{
AnnaBridge	171:3a7713b1edbc	562	*/
AnnaBridge	171:3a7713b1edbc	563	#define MXC_CFG_TMR_INSTANCES (6) /*< Define for the number of timers on the \MXIM_Device /
AnnaBridge	171:3a7713b1edbc	564	#define MXC_BASE_TMR0 ((uint32_t)0x4000B000UL) /*< Base Address for Timer 0 /
AnnaBridge	171:3a7713b1edbc	565	#define MXC_TMR0 ((mxc_tmr_regs_t )MXC_BASE_TMR0) /< Pointer to a #mxc_tmr_regs_t structure representing Timer 0 /
AnnaBridge	171:3a7713b1edbc	566	#define MXC_BASE_TMR1 ((uint32_t)0x4000C000UL) /*< Base Address for Timer 1 /
AnnaBridge	171:3a7713b1edbc	567	#define MXC_TMR1 ((mxc_tmr_regs_t )MXC_BASE_TMR1) /< Pointer to a #mxc_tmr_regs_t structure representing Timer 1 /
AnnaBridge	171:3a7713b1edbc	568	#define MXC_BASE_TMR2 ((uint32_t)0x4000D000UL) /*< Base Address for Timer 2 /
AnnaBridge	171:3a7713b1edbc	569	#define MXC_TMR2 ((mxc_tmr_regs_t )MXC_BASE_TMR2) /< Pointer to a #mxc_tmr_regs_t structure representing Timer 2 /
AnnaBridge	171:3a7713b1edbc	570	#define MXC_BASE_TMR3 ((uint32_t)0x4000E000UL) /*< Base Address for Timer 3 /
AnnaBridge	171:3a7713b1edbc	571	#define MXC_TMR3 ((mxc_tmr_regs_t )MXC_BASE_TMR3) /< Pointer to a #mxc_tmr_regs_t structure representing Timer 3 /
AnnaBridge	171:3a7713b1edbc	572	#define MXC_BASE_TMR4 ((uint32_t)0x4000F000UL) /*< Base Address for Timer 4 /
AnnaBridge	171:3a7713b1edbc	573	#define MXC_TMR4 ((mxc_tmr_regs_t )MXC_BASE_TMR4) /< Pointer to a #mxc_tmr_regs_t structure representing Timer 4 /
AnnaBridge	171:3a7713b1edbc	574	#define MXC_BASE_TMR5 ((uint32_t)0x40010000UL) /*< Base Address for Timer 5 /
AnnaBridge	171:3a7713b1edbc	575	#define MXC_TMR5 ((mxc_tmr_regs_t )MXC_BASE_TMR5) /< Pointer to a #mxc_tmr_regs_t structure representing Timer 5 /
AnnaBridge	171:3a7713b1edbc	576
AnnaBridge	171:3a7713b1edbc	577	/**
AnnaBridge	171:3a7713b1edbc	578	* Macro that returns an #IRQn_Type for the requested 32-bit timer interrupt.
AnnaBridge	171:3a7713b1edbc	579	*/
AnnaBridge	171:3a7713b1edbc	580	#define MXC_TMR_GET_IRQ_32(i) (IRQn_Type)((i) == 0 ? TMR0_0_IRQn : \
AnnaBridge	171:3a7713b1edbc	581	(i) == 1 ? TMR1_0_IRQn : \
AnnaBridge	171:3a7713b1edbc	582	(i) == 2 ? TMR2_0_IRQn : \
AnnaBridge	171:3a7713b1edbc	583	(i) == 3 ? TMR3_0_IRQn : \
AnnaBridge	171:3a7713b1edbc	584	(i) == 4 ? TMR4_0_IRQn : \
AnnaBridge	171:3a7713b1edbc	585	(i) == 5 ? TMR5_0_IRQn : 0)
AnnaBridge	171:3a7713b1edbc	586	/**
AnnaBridge	171:3a7713b1edbc	587	* Macro that returns an IRQn_Type for the requested 16-bit timer interrupt number.
AnnaBridge	171:3a7713b1edbc	588	*/
AnnaBridge	171:3a7713b1edbc	589	#define MXC_TMR_GET_IRQ_16(i) (IRQn_Type)((i) == 0 ? TMR0_0_IRQn : \
AnnaBridge	171:3a7713b1edbc	590	(i) == 1 ? TMR1_0_IRQn : \
AnnaBridge	171:3a7713b1edbc	591	(i) == 2 ? TMR2_0_IRQn : \
AnnaBridge	171:3a7713b1edbc	592	(i) == 3 ? TMR3_0_IRQn : \
AnnaBridge	171:3a7713b1edbc	593	(i) == 4 ? TMR4_0_IRQn : \
AnnaBridge	171:3a7713b1edbc	594	(i) == 5 ? TMR5_0_IRQn : \
AnnaBridge	171:3a7713b1edbc	595	(i) == 6 ? TMR0_1_IRQn : \
AnnaBridge	171:3a7713b1edbc	596	(i) == 7 ? TMR1_1_IRQn : \
AnnaBridge	171:3a7713b1edbc	597	(i) == 8 ? TMR2_1_IRQn : \
AnnaBridge	171:3a7713b1edbc	598	(i) == 9 ? TMR3_1_IRQn : \
AnnaBridge	171:3a7713b1edbc	599	(i) == 10 ? TMR4_1_IRQn : \
AnnaBridge	171:3a7713b1edbc	600	(i) == 11 ? TMR5_1_IRQn : 0)
AnnaBridge	171:3a7713b1edbc	601	/**
AnnaBridge	171:3a7713b1edbc	602	* Macro to return the base address for a given Timer index number.
AnnaBridge	171:3a7713b1edbc	603	* @p i Timer instance number.
AnnaBridge	171:3a7713b1edbc	604	* @p returns the base peripheral address for the requested timer instance.
AnnaBridge	171:3a7713b1edbc	605	*/
AnnaBridge	171:3a7713b1edbc	606	#define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \
AnnaBridge	171:3a7713b1edbc	607	(i) == 1 ? MXC_BASE_TMR1 : \
AnnaBridge	171:3a7713b1edbc	608	(i) == 2 ? MXC_BASE_TMR2 : \
AnnaBridge	171:3a7713b1edbc	609	(i) == 3 ? MXC_BASE_TMR3 : \
AnnaBridge	171:3a7713b1edbc	610	(i) == 4 ? MXC_BASE_TMR4 : \
AnnaBridge	171:3a7713b1edbc	611	(i) == 5 ? MXC_BASE_TMR5 : 0)
AnnaBridge	171:3a7713b1edbc	612	/**
AnnaBridge	171:3a7713b1edbc	613	* Macro to return a pointer to the #mxc_tmr_regs_t structure for a given Timer Instance.
AnnaBridge	171:3a7713b1edbc	614	* @p i Timer instance number.
AnnaBridge	171:3a7713b1edbc	615	* @p returns a pointer to a #mxc_tmr_regs_t for the requested timer number.
AnnaBridge	171:3a7713b1edbc	616	*/
AnnaBridge	171:3a7713b1edbc	617	#define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \
AnnaBridge	171:3a7713b1edbc	618	(i) == 1 ? MXC_TMR1 : \
AnnaBridge	171:3a7713b1edbc	619	(i) == 2 ? MXC_TMR2 : \
AnnaBridge	171:3a7713b1edbc	620	(i) == 3 ? MXC_TMR3 : \
AnnaBridge	171:3a7713b1edbc	621	(i) == 4 ? MXC_TMR4 : \
AnnaBridge	171:3a7713b1edbc	622	(i) == 5 ? MXC_TMR5 : 0)
AnnaBridge	171:3a7713b1edbc	623	/**
AnnaBridge	171:3a7713b1edbc	624	* Macro to return the index number for a given pointer to a #mxc_tmr_regs_t structure.
AnnaBridge	171:3a7713b1edbc	625	* @p p pointer to a #mxc_tmr_regs_t structure.
AnnaBridge	171:3a7713b1edbc	626	* @p returns a timer instance number.
AnnaBridge	171:3a7713b1edbc	627	*/
AnnaBridge	171:3a7713b1edbc	628	#define MXC_TMR_GET_IDX(p) ((p) == MXC_TMR0 ? 0 : \
AnnaBridge	171:3a7713b1edbc	629	(p) == MXC_TMR1 ? 1 : \
AnnaBridge	171:3a7713b1edbc	630	(p) == MXC_TMR2 ? 2 : \
AnnaBridge	171:3a7713b1edbc	631	(p) == MXC_TMR3 ? 3 : \
AnnaBridge	171:3a7713b1edbc	632	(p) == MXC_TMR4 ? 4 : \
AnnaBridge	171:3a7713b1edbc	633	(p) == MXC_TMR5 ? 5 : -1)
AnnaBridge	171:3a7713b1edbc	634
AnnaBridge	171:3a7713b1edbc	635	/*@} end of ingroup tmr_registers /
AnnaBridge	171:3a7713b1edbc	636
AnnaBridge	171:3a7713b1edbc	637	/**
AnnaBridge	171:3a7713b1edbc	638	* @ingroup product_name
AnnaBridge	171:3a7713b1edbc	639	* @{
AnnaBridge	171:3a7713b1edbc	640	*/
AnnaBridge	171:3a7713b1edbc	641	/* *************************************************************************** */
AnnaBridge	171:3a7713b1edbc	642	/* Pulse Train Generation */
AnnaBridge	171:3a7713b1edbc	643	#define MXC_CFG_PT_INSTANCES (16)
AnnaBridge	171:3a7713b1edbc	644
AnnaBridge	171:3a7713b1edbc	645	#define MXC_BASE_PTG ((uint32_t)0x40011000UL)
AnnaBridge	171:3a7713b1edbc	646	#define MXC_PTG ((mxc_ptg_regs_t *)MXC_BASE_PTG)
AnnaBridge	171:3a7713b1edbc	647	#define MXC_BASE_PT0 ((uint32_t)0x40011020UL)
AnnaBridge	171:3a7713b1edbc	648	#define MXC_PT0 ((mxc_pt_regs_t *)MXC_BASE_PT0)
AnnaBridge	171:3a7713b1edbc	649	#define MXC_BASE_PT1 ((uint32_t)0x40011040UL)
AnnaBridge	171:3a7713b1edbc	650	#define MXC_PT1 ((mxc_pt_regs_t *)MXC_BASE_PT1)
AnnaBridge	171:3a7713b1edbc	651	#define MXC_BASE_PT2 ((uint32_t)0x40011060UL)
AnnaBridge	171:3a7713b1edbc	652	#define MXC_PT2 ((mxc_pt_regs_t *)MXC_BASE_PT2)
AnnaBridge	171:3a7713b1edbc	653	#define MXC_BASE_PT3 ((uint32_t)0x40011080UL)
AnnaBridge	171:3a7713b1edbc	654	#define MXC_PT3 ((mxc_pt_regs_t *)MXC_BASE_PT3)
AnnaBridge	171:3a7713b1edbc	655	#define MXC_BASE_PT4 ((uint32_t)0x400110A0UL)
AnnaBridge	171:3a7713b1edbc	656	#define MXC_PT4 ((mxc_pt_regs_t *)MXC_BASE_PT4)
AnnaBridge	171:3a7713b1edbc	657	#define MXC_BASE_PT5 ((uint32_t)0x400110C0UL)
AnnaBridge	171:3a7713b1edbc	658	#define MXC_PT5 ((mxc_pt_regs_t *)MXC_BASE_PT5)
AnnaBridge	171:3a7713b1edbc	659	#define MXC_BASE_PT6 ((uint32_t)0x400110E0UL)
AnnaBridge	171:3a7713b1edbc	660	#define MXC_PT6 ((mxc_pt_regs_t *)MXC_BASE_PT6)
AnnaBridge	171:3a7713b1edbc	661	#define MXC_BASE_PT7 ((uint32_t)0x40011100UL)
AnnaBridge	171:3a7713b1edbc	662	#define MXC_PT7 ((mxc_pt_regs_t *)MXC_BASE_PT7)
AnnaBridge	171:3a7713b1edbc	663	#define MXC_BASE_PT8 ((uint32_t)0x40011120UL)
AnnaBridge	171:3a7713b1edbc	664	#define MXC_PT8 ((mxc_pt_regs_t *)MXC_BASE_PT8)
AnnaBridge	171:3a7713b1edbc	665	#define MXC_BASE_PT9 ((uint32_t)0x40011140UL)
AnnaBridge	171:3a7713b1edbc	666	#define MXC_PT9 ((mxc_pt_regs_t *)MXC_BASE_PT9)
AnnaBridge	171:3a7713b1edbc	667	#define MXC_BASE_PT10 ((uint32_t)0x40011160UL)
AnnaBridge	171:3a7713b1edbc	668	#define MXC_PT10 ((mxc_pt_regs_t *)MXC_BASE_PT10)
AnnaBridge	171:3a7713b1edbc	669	#define MXC_BASE_PT11 ((uint32_t)0x40011180UL)
AnnaBridge	171:3a7713b1edbc	670	#define MXC_PT11 ((mxc_pt_regs_t *)MXC_BASE_PT11)
AnnaBridge	171:3a7713b1edbc	671	#define MXC_BASE_PT12 ((uint32_t)0x400111A0UL)
AnnaBridge	171:3a7713b1edbc	672	#define MXC_PT12 ((mxc_pt_regs_t *)MXC_BASE_PT12)
AnnaBridge	171:3a7713b1edbc	673	#define MXC_BASE_PT13 ((uint32_t)0x400111C0UL)
AnnaBridge	171:3a7713b1edbc	674	#define MXC_PT13 ((mxc_pt_regs_t *)MXC_BASE_PT13)
AnnaBridge	171:3a7713b1edbc	675	#define MXC_BASE_PT14 ((uint32_t)0x400111E0UL)
AnnaBridge	171:3a7713b1edbc	676	#define MXC_PT14 ((mxc_pt_regs_t *)MXC_BASE_PT14)
AnnaBridge	171:3a7713b1edbc	677	#define MXC_BASE_PT15 ((uint32_t)0x40011200UL)
AnnaBridge	171:3a7713b1edbc	678	#define MXC_PT15 ((mxc_pt_regs_t *)MXC_BASE_PT15)
AnnaBridge	171:3a7713b1edbc	679
AnnaBridge	171:3a7713b1edbc	680	#define MXC_PT_GET_BASE(i) ((i) == 0 ? MXC_BASE_PT0 : \
AnnaBridge	171:3a7713b1edbc	681	(i) == 1 ? MXC_BASE_PT1 : \
AnnaBridge	171:3a7713b1edbc	682	(i) == 2 ? MXC_BASE_PT2 : \
AnnaBridge	171:3a7713b1edbc	683	(i) == 3 ? MXC_BASE_PT3 : \
AnnaBridge	171:3a7713b1edbc	684	(i) == 4 ? MXC_BASE_PT4 : \
AnnaBridge	171:3a7713b1edbc	685	(i) == 5 ? MXC_BASE_PT5 : \
AnnaBridge	171:3a7713b1edbc	686	(i) == 6 ? MXC_BASE_PT6 : \
AnnaBridge	171:3a7713b1edbc	687	(i) == 7 ? MXC_BASE_PT7 : \
AnnaBridge	171:3a7713b1edbc	688	(i) == 8 ? MXC_BASE_PT8 : \
AnnaBridge	171:3a7713b1edbc	689	(i) == 9 ? MXC_BASE_PT9 : \
AnnaBridge	171:3a7713b1edbc	690	(i) == 10 ? MXC_BASE_PT10 : \
AnnaBridge	171:3a7713b1edbc	691	(i) == 11 ? MXC_BASE_PT11 : \
AnnaBridge	171:3a7713b1edbc	692	(i) == 12 ? MXC_BASE_PT12 : \
AnnaBridge	171:3a7713b1edbc	693	(i) == 13 ? MXC_BASE_PT13 : \
AnnaBridge	171:3a7713b1edbc	694	(i) == 14 ? MXC_BASE_PT14 : \
AnnaBridge	171:3a7713b1edbc	695	(i) == 15 ? MXC_BASE_PT15 : 0)
AnnaBridge	171:3a7713b1edbc	696
AnnaBridge	171:3a7713b1edbc	697	#define MXC_PT_GET_PT(i) ((i) == 0 ? MXC_PT0 : \
AnnaBridge	171:3a7713b1edbc	698	(i) == 1 ? MXC_PT1 : \
AnnaBridge	171:3a7713b1edbc	699	(i) == 2 ? MXC_PT2 : \
AnnaBridge	171:3a7713b1edbc	700	(i) == 3 ? MXC_PT3 : \
AnnaBridge	171:3a7713b1edbc	701	(i) == 4 ? MXC_PT4 : \
AnnaBridge	171:3a7713b1edbc	702	(i) == 5 ? MXC_PT5 : \
AnnaBridge	171:3a7713b1edbc	703	(i) == 6 ? MXC_PT6 : \
AnnaBridge	171:3a7713b1edbc	704	(i) == 7 ? MXC_PT7 : \
AnnaBridge	171:3a7713b1edbc	705	(i) == 8 ? MXC_PT8 : \
AnnaBridge	171:3a7713b1edbc	706	(i) == 9 ? MXC_PT9 : \
AnnaBridge	171:3a7713b1edbc	707	(i) == 10 ? MXC_PT10 : \
AnnaBridge	171:3a7713b1edbc	708	(i) == 11 ? MXC_PT11 : \
AnnaBridge	171:3a7713b1edbc	709	(i) == 12 ? MXC_PT12 : \
AnnaBridge	171:3a7713b1edbc	710	(i) == 13 ? MXC_PT13 : \
AnnaBridge	171:3a7713b1edbc	711	(i) == 14 ? MXC_PT14 : \
AnnaBridge	171:3a7713b1edbc	712	(i) == 15 ? MXC_PT15 : 0)
AnnaBridge	171:3a7713b1edbc	713
AnnaBridge	171:3a7713b1edbc	714	#define MXC_PT_GET_IDX(p) ((p) == MXC_PT0 ? 0 : \
AnnaBridge	171:3a7713b1edbc	715	(p) == MXC_PT1 ? 1 : \
AnnaBridge	171:3a7713b1edbc	716	(p) == MXC_PT2 ? 2 : \
AnnaBridge	171:3a7713b1edbc	717	(p) == MXC_PT3 ? 3 : \
AnnaBridge	171:3a7713b1edbc	718	(p) == MXC_PT4 ? 4 : \
AnnaBridge	171:3a7713b1edbc	719	(p) == MXC_PT5 ? 5 : \
AnnaBridge	171:3a7713b1edbc	720	(p) == MXC_PT6 ? 6 : \
AnnaBridge	171:3a7713b1edbc	721	(p) == MXC_PT7 ? 7 : \
AnnaBridge	171:3a7713b1edbc	722	(p) == MXC_PT8 ? 8 : \
AnnaBridge	171:3a7713b1edbc	723	(p) == MXC_PT9 ? 9 : \
AnnaBridge	171:3a7713b1edbc	724	(p) == MXC_PT10 ? 10 : \
AnnaBridge	171:3a7713b1edbc	725	(p) == MXC_PT11 ? 11 : \
AnnaBridge	171:3a7713b1edbc	726	(p) == MXC_PT12 ? 12 : \
AnnaBridge	171:3a7713b1edbc	727	(p) == MXC_PT13 ? 13 : \
AnnaBridge	171:3a7713b1edbc	728	(p) == MXC_PT14 ? 14 : \
AnnaBridge	171:3a7713b1edbc	729	(p) == MXC_PT15 ? 15 : -1)
AnnaBridge	171:3a7713b1edbc	730
AnnaBridge	171:3a7713b1edbc	731
AnnaBridge	171:3a7713b1edbc	732
AnnaBridge	171:3a7713b1edbc	733	/* *************************************************************************** */
AnnaBridge	171:3a7713b1edbc	734	/* UART / Serial Port Interface */
AnnaBridge	171:3a7713b1edbc	735
AnnaBridge	171:3a7713b1edbc	736	#define MXC_CFG_UART_INSTANCES (4)
AnnaBridge	171:3a7713b1edbc	737	#define MXC_UART_FIFO_DEPTH (32)
AnnaBridge	171:3a7713b1edbc	738
AnnaBridge	171:3a7713b1edbc	739	#define MXC_BASE_UART0 ((uint32_t)0x40012000UL)
AnnaBridge	171:3a7713b1edbc	740	#define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0)
AnnaBridge	171:3a7713b1edbc	741	#define MXC_BASE_UART1 ((uint32_t)0x40013000UL)
AnnaBridge	171:3a7713b1edbc	742	#define MXC_UART1 ((mxc_uart_regs_t )MXC_BASE_UART1) /< UART Port 1 Base Address /
AnnaBridge	171:3a7713b1edbc	743	#define MXC_BASE_UART2 ((uint32_t)0x40014000UL)
AnnaBridge	171:3a7713b1edbc	744	#define MXC_UART2 ((mxc_uart_regs_t *)MXC_BASE_UART2)
AnnaBridge	171:3a7713b1edbc	745	#define MXC_BASE_UART3 ((uint32_t)0x40015000UL)
AnnaBridge	171:3a7713b1edbc	746	#define MXC_UART3 ((mxc_uart_regs_t *)MXC_BASE_UART3)
AnnaBridge	171:3a7713b1edbc	747	#define MXC_BASE_UART0_FIFO ((uint32_t)0x40103000UL)
AnnaBridge	171:3a7713b1edbc	748	#define MXC_UART0_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART0_FIFO)
AnnaBridge	171:3a7713b1edbc	749	#define MXC_BASE_UART1_FIFO ((uint32_t)0x40104000UL)
AnnaBridge	171:3a7713b1edbc	750	#define MXC_UART1_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART1_FIFO)
AnnaBridge	171:3a7713b1edbc	751	#define MXC_BASE_UART2_FIFO ((uint32_t)0x40105000UL)
AnnaBridge	171:3a7713b1edbc	752	#define MXC_UART2_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART2_FIFO)
AnnaBridge	171:3a7713b1edbc	753	#define MXC_BASE_UART3_FIFO ((uint32_t)0x40106000UL)
AnnaBridge	171:3a7713b1edbc	754	#define MXC_UART3_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART3_FIFO)
AnnaBridge	171:3a7713b1edbc	755
AnnaBridge	171:3a7713b1edbc	756	#define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : \
AnnaBridge	171:3a7713b1edbc	757	(i) == 1 ? UART1_IRQn : \
AnnaBridge	171:3a7713b1edbc	758	(i) == 2 ? UART2_IRQn : \
AnnaBridge	171:3a7713b1edbc	759	(i) == 3 ? UART3_IRQn : 0)
AnnaBridge	171:3a7713b1edbc	760
AnnaBridge	171:3a7713b1edbc	761	#define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \
AnnaBridge	171:3a7713b1edbc	762	(i) == 1 ? MXC_BASE_UART1 : \
AnnaBridge	171:3a7713b1edbc	763	(i) == 2 ? MXC_BASE_UART2 : \
AnnaBridge	171:3a7713b1edbc	764	(i) == 3 ? MXC_BASE_UART3 : 0)
AnnaBridge	171:3a7713b1edbc	765
AnnaBridge	171:3a7713b1edbc	766	#define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \
AnnaBridge	171:3a7713b1edbc	767	(i) == 1 ? MXC_UART1 : \
AnnaBridge	171:3a7713b1edbc	768	(i) == 2 ? MXC_UART2 : \
AnnaBridge	171:3a7713b1edbc	769	(i) == 3 ? MXC_UART3 : 0)
AnnaBridge	171:3a7713b1edbc	770
AnnaBridge	171:3a7713b1edbc	771	#define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : \
AnnaBridge	171:3a7713b1edbc	772	(p) == MXC_UART1 ? 1 : \
AnnaBridge	171:3a7713b1edbc	773	(p) == MXC_UART2 ? 2 : \
AnnaBridge	171:3a7713b1edbc	774	(p) == MXC_UART3 ? 3 : -1)
AnnaBridge	171:3a7713b1edbc	775
AnnaBridge	171:3a7713b1edbc	776	#define MXC_UART_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_UART0_FIFO : \
AnnaBridge	171:3a7713b1edbc	777	(i) == 1 ? MXC_BASE_UART1_FIFO : \
AnnaBridge	171:3a7713b1edbc	778	(i) == 2 ? MXC_BASE_UART2_FIFO : \
AnnaBridge	171:3a7713b1edbc	779	(i) == 3 ? MXC_BASE_UART3_FIFO : 0)
AnnaBridge	171:3a7713b1edbc	780
AnnaBridge	171:3a7713b1edbc	781	#define MXC_UART_GET_FIFO(i) ((i) == 0 ? MXC_UART0_FIFO : \
AnnaBridge	171:3a7713b1edbc	782	(i) == 1 ? MXC_UART1_FIFO : \
AnnaBridge	171:3a7713b1edbc	783	(i) == 2 ? MXC_UART2_FIFO : \
AnnaBridge	171:3a7713b1edbc	784	(i) == 3 ? MXC_UART3_FIFO : 0)
AnnaBridge	171:3a7713b1edbc	785
AnnaBridge	171:3a7713b1edbc	786
AnnaBridge	171:3a7713b1edbc	787
AnnaBridge	171:3a7713b1edbc	788	/* *************************************************************************** */
AnnaBridge	171:3a7713b1edbc	789	/* I2C Master Interface */
AnnaBridge	171:3a7713b1edbc	790
AnnaBridge	171:3a7713b1edbc	791	#define MXC_CFG_I2CM_INSTANCES (3)
AnnaBridge	171:3a7713b1edbc	792	#define MXC_I2CM_FIFO_DEPTH (8)
AnnaBridge	171:3a7713b1edbc	793
AnnaBridge	171:3a7713b1edbc	794	#define MXC_BASE_I2CM0 ((uint32_t)0x40016000UL)
AnnaBridge	171:3a7713b1edbc	795	#define MXC_I2CM0 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM0)
AnnaBridge	171:3a7713b1edbc	796	#define MXC_BASE_I2CM1 ((uint32_t)0x40017000UL)
AnnaBridge	171:3a7713b1edbc	797	#define MXC_I2CM1 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM1)
AnnaBridge	171:3a7713b1edbc	798	#define MXC_BASE_I2CM2 ((uint32_t)0x40018000UL)
AnnaBridge	171:3a7713b1edbc	799	#define MXC_I2CM2 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM2)
AnnaBridge	171:3a7713b1edbc	800	#define MXC_BASE_I2CM0_FIFO ((uint32_t)0x40107000UL)
AnnaBridge	171:3a7713b1edbc	801	#define MXC_I2CM0_FIFO ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM0_FIFO)
AnnaBridge	171:3a7713b1edbc	802	#define MXC_BASE_I2CM1_FIFO ((uint32_t)0x40108000UL)
AnnaBridge	171:3a7713b1edbc	803	#define MXC_I2CM1_FIFO ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM1_FIFO)
AnnaBridge	171:3a7713b1edbc	804	#define MXC_BASE_I2CM2_FIFO ((uint32_t)0x40109000UL)
AnnaBridge	171:3a7713b1edbc	805	#define MXC_I2CM2_FIFO ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM2_FIFO)
AnnaBridge	171:3a7713b1edbc	806
AnnaBridge	171:3a7713b1edbc	807	#define MXC_I2CM_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2CM0_IRQn : \
AnnaBridge	171:3a7713b1edbc	808	(i) == 1 ? I2CM1_IRQn : \
AnnaBridge	171:3a7713b1edbc	809	(i) == 2 ? I2CM2_IRQn : 0)
AnnaBridge	171:3a7713b1edbc	810
AnnaBridge	171:3a7713b1edbc	811	#define MXC_I2CM_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2CM0 : \
AnnaBridge	171:3a7713b1edbc	812	(i) == 1 ? MXC_BASE_I2CM1 : \
AnnaBridge	171:3a7713b1edbc	813	(i) == 2 ? MXC_BASE_I2CM2 : 0)
AnnaBridge	171:3a7713b1edbc	814
AnnaBridge	171:3a7713b1edbc	815	#define MXC_I2CM_GET_I2CM(i) ((i) == 0 ? MXC_I2CM0 : \
AnnaBridge	171:3a7713b1edbc	816	(i) == 1 ? MXC_I2CM1 : \
AnnaBridge	171:3a7713b1edbc	817	(i) == 2 ? MXC_I2CM2 : 0)
AnnaBridge	171:3a7713b1edbc	818
AnnaBridge	171:3a7713b1edbc	819	#define MXC_I2CM_GET_IDX(p) ((p) == MXC_I2CM0 ? 0 : \
AnnaBridge	171:3a7713b1edbc	820	(p) == MXC_I2CM1 ? 1 : \
AnnaBridge	171:3a7713b1edbc	821	(p) == MXC_I2CM2 ? 2 : -1)
AnnaBridge	171:3a7713b1edbc	822
AnnaBridge	171:3a7713b1edbc	823	#define MXC_I2CM_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_I2CM0_FIFO : \
AnnaBridge	171:3a7713b1edbc	824	(i) == 1 ? MXC_BASE_I2CM1_FIFO : \
AnnaBridge	171:3a7713b1edbc	825	(i) == 2 ? MXC_BASE_I2CM2_FIFO : 0)
AnnaBridge	171:3a7713b1edbc	826
AnnaBridge	171:3a7713b1edbc	827	#define MXC_I2CM_GET_FIFO(i) ((i) == 0 ? MXC_I2CM0_FIFO : \
AnnaBridge	171:3a7713b1edbc	828	(i) == 1 ? MXC_I2CM1_FIFO : \
AnnaBridge	171:3a7713b1edbc	829	(i) == 2 ? MXC_I2CM2_FIFO : 0)
AnnaBridge	171:3a7713b1edbc	830
AnnaBridge	171:3a7713b1edbc	831
AnnaBridge	171:3a7713b1edbc	832
AnnaBridge	171:3a7713b1edbc	833	/* *************************************************************************** */
AnnaBridge	171:3a7713b1edbc	834	/* I2C Slave Interface (Mailbox type) */
AnnaBridge	171:3a7713b1edbc	835
AnnaBridge	171:3a7713b1edbc	836	#define MXC_CFG_I2CS_INSTANCES (1)
AnnaBridge	171:3a7713b1edbc	837	#define MXC_CFG_I2CS_BUFFER_SIZE (32)
AnnaBridge	171:3a7713b1edbc	838
AnnaBridge	171:3a7713b1edbc	839	#define MXC_BASE_I2CS ((uint32_t)0x40019000UL)
AnnaBridge	171:3a7713b1edbc	840	#define MXC_I2CS ((mxc_i2cs_regs_t *)MXC_BASE_I2CS)
AnnaBridge	171:3a7713b1edbc	841
AnnaBridge	171:3a7713b1edbc	842	#define MXC_I2CS_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2CS_IRQn : 0)
AnnaBridge	171:3a7713b1edbc	843
AnnaBridge	171:3a7713b1edbc	844	#define MXC_I2CS_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2CS : 0)
AnnaBridge	171:3a7713b1edbc	845
AnnaBridge	171:3a7713b1edbc	846	#define MXC_I2CS_GET_I2CS(i) ((i) == 0 ? MXC_I2CS : 0)
AnnaBridge	171:3a7713b1edbc	847
AnnaBridge	171:3a7713b1edbc	848	#define MXC_I2CS_GET_IDX(p) ((p) == MXC_I2CS ? 0 : -1)
AnnaBridge	171:3a7713b1edbc	849
AnnaBridge	171:3a7713b1edbc	850	/* *************************************************************************** */
AnnaBridge	171:3a7713b1edbc	851	/* SPI Master Interface */
AnnaBridge	171:3a7713b1edbc	852
AnnaBridge	171:3a7713b1edbc	853	#define MXC_CFG_SPIM_INSTANCES (3)
AnnaBridge	171:3a7713b1edbc	854	#define MXC_CFG_SPIM_FIFO_DEPTH (16)
AnnaBridge	171:3a7713b1edbc	855
AnnaBridge	171:3a7713b1edbc	856	#define MXC_BASE_SPIM0 ((uint32_t)0x4001A000UL)
AnnaBridge	171:3a7713b1edbc	857	#define MXC_SPIM0 ((mxc_spim_regs_t *)MXC_BASE_SPIM0)
AnnaBridge	171:3a7713b1edbc	858	#define MXC_BASE_SPIM1 ((uint32_t)0x4001B000UL)
AnnaBridge	171:3a7713b1edbc	859	#define MXC_SPIM1 ((mxc_spim_regs_t *)MXC_BASE_SPIM1)
AnnaBridge	171:3a7713b1edbc	860	#define MXC_BASE_SPIM2 ((uint32_t)0x4001C000UL)
AnnaBridge	171:3a7713b1edbc	861	#define MXC_SPIM2 ((mxc_spim_regs_t *)MXC_BASE_SPIM2)
AnnaBridge	171:3a7713b1edbc	862	#define MXC_BASE_SPIM0_FIFO ((uint32_t)0x4010A000UL)
AnnaBridge	171:3a7713b1edbc	863	#define MXC_SPIM0_FIFO ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM0_FIFO)
AnnaBridge	171:3a7713b1edbc	864	#define MXC_BASE_SPIM1_FIFO ((uint32_t)0x4010B000UL)
AnnaBridge	171:3a7713b1edbc	865	#define MXC_SPIM1_FIFO ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM1_FIFO)
AnnaBridge	171:3a7713b1edbc	866	#define MXC_BASE_SPIM2_FIFO ((uint32_t)0x4010C000UL)
AnnaBridge	171:3a7713b1edbc	867	#define MXC_SPIM2_FIFO ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM2_FIFO)
AnnaBridge	171:3a7713b1edbc	868
AnnaBridge	171:3a7713b1edbc	869	#define MXC_SPIM_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPIM0_IRQn : \
AnnaBridge	171:3a7713b1edbc	870	(i) == 1 ? SPIM1_IRQn : \
AnnaBridge	171:3a7713b1edbc	871	(i) == 2 ? SPIM2_IRQn : 0)
AnnaBridge	171:3a7713b1edbc	872
AnnaBridge	171:3a7713b1edbc	873	#define MXC_SPIM_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPIM0 : \
AnnaBridge	171:3a7713b1edbc	874	(i) == 1 ? MXC_BASE_SPIM1 : \
AnnaBridge	171:3a7713b1edbc	875	(i) == 2 ? MXC_BASE_SPIM2 : 0)
AnnaBridge	171:3a7713b1edbc	876
AnnaBridge	171:3a7713b1edbc	877	#define MXC_SPIM_GET_SPIM(i) ((i) == 0 ? MXC_SPIM0 : \
AnnaBridge	171:3a7713b1edbc	878	(i) == 1 ? MXC_SPIM1 : \
AnnaBridge	171:3a7713b1edbc	879	(i) == 2 ? MXC_SPIM2 : 0)
AnnaBridge	171:3a7713b1edbc	880
AnnaBridge	171:3a7713b1edbc	881	#define MXC_SPIM_GET_IDX(p) ((p) == MXC_SPIM0 ? 0 : \
AnnaBridge	171:3a7713b1edbc	882	(p) == MXC_SPIM1 ? 1 : \
AnnaBridge	171:3a7713b1edbc	883	(p) == MXC_SPIM2 ? 2 : -1)
AnnaBridge	171:3a7713b1edbc	884
AnnaBridge	171:3a7713b1edbc	885	#define MXC_SPIM_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_SPIM0_FIFO : \
AnnaBridge	171:3a7713b1edbc	886	(i) == 1 ? MXC_BASE_SPIM1_FIFO : \
AnnaBridge	171:3a7713b1edbc	887	(i) == 2 ? MXC_BASE_SPIM2_FIFO : 0)
AnnaBridge	171:3a7713b1edbc	888
AnnaBridge	171:3a7713b1edbc	889	#define MXC_SPIM_GET_SPIM_FIFO(i) ((i) == 0 ? MXC_SPIM0_FIFO : \
AnnaBridge	171:3a7713b1edbc	890	(i) == 1 ? MXC_SPIM1_FIFO : \
AnnaBridge	171:3a7713b1edbc	891	(i) == 2 ? MXC_SPIM2_FIFO : 0)
AnnaBridge	171:3a7713b1edbc	892
AnnaBridge	171:3a7713b1edbc	893
AnnaBridge	171:3a7713b1edbc	894
AnnaBridge	171:3a7713b1edbc	895	/* *************************************************************************** */
AnnaBridge	171:3a7713b1edbc	896	/* 1-Wire Master Interface */
AnnaBridge	171:3a7713b1edbc	897
AnnaBridge	171:3a7713b1edbc	898	#define MXC_CFG_OWM_INSTANCES (1)
AnnaBridge	171:3a7713b1edbc	899
AnnaBridge	171:3a7713b1edbc	900	#define MXC_BASE_OWM ((uint32_t)0x4001E000UL)
AnnaBridge	171:3a7713b1edbc	901	#define MXC_OWM ((mxc_owm_regs_t *)MXC_BASE_OWM)
AnnaBridge	171:3a7713b1edbc	902
AnnaBridge	171:3a7713b1edbc	903	#define MXC_OWM_GET_IRQ(i) (IRQn_Type)((i) == 0 ? OWM_IRQn : 0)
AnnaBridge	171:3a7713b1edbc	904
AnnaBridge	171:3a7713b1edbc	905	#define MXC_OWM_GET_BASE(i) ((i) == 0 ? MXC_BASE_OWM : 0)
AnnaBridge	171:3a7713b1edbc	906
AnnaBridge	171:3a7713b1edbc	907	#define MXC_OWM_GET_OWM(i) ((i) == 0 ? MXC_OWM : 0)
AnnaBridge	171:3a7713b1edbc	908
AnnaBridge	171:3a7713b1edbc	909	#define MXC_OWM_GET_IDX(p) ((p) == MXC_OWM ? 0 : -1)
AnnaBridge	171:3a7713b1edbc	910
AnnaBridge	171:3a7713b1edbc	911
AnnaBridge	171:3a7713b1edbc	912	/* *************************************************************************** */
AnnaBridge	171:3a7713b1edbc	913	/* ADC / AFE */
AnnaBridge	171:3a7713b1edbc	914
AnnaBridge	171:3a7713b1edbc	915	#define MXC_CFG_ADC_FIFO_DEPTH (32)
AnnaBridge	171:3a7713b1edbc	916
AnnaBridge	171:3a7713b1edbc	917	#define MXC_BASE_ADC ((uint32_t)0x4001F000UL)
AnnaBridge	171:3a7713b1edbc	918	#define MXC_ADC ((mxc_adc_regs_t *)MXC_BASE_ADC)
AnnaBridge	171:3a7713b1edbc	919
AnnaBridge	171:3a7713b1edbc	920
AnnaBridge	171:3a7713b1edbc	921
AnnaBridge	171:3a7713b1edbc	922	/* *************************************************************************** */
AnnaBridge	171:3a7713b1edbc	923	/* SPIB AHB-to-SPI Bridge */
AnnaBridge	171:3a7713b1edbc	924
AnnaBridge	171:3a7713b1edbc	925	#define MXC_BASE_SPIB ((uint32_t)0x4000D000UL)
AnnaBridge	171:3a7713b1edbc	926	#define MXC_SPIB ((mxc_spib_regs_t *)MXC_BASE_SPIB)
AnnaBridge	171:3a7713b1edbc	927
AnnaBridge	171:3a7713b1edbc	928
AnnaBridge	171:3a7713b1edbc	929
AnnaBridge	171:3a7713b1edbc	930	/* *************************************************************************** */
AnnaBridge	171:3a7713b1edbc	931	/* SPI Slave Interface */
AnnaBridge	171:3a7713b1edbc	932
AnnaBridge	171:3a7713b1edbc	933	#define MXC_BASE_SPIS ((uint32_t)0x40020000UL)
AnnaBridge	171:3a7713b1edbc	934	#define MXC_SPIS ((mxc_spis_regs_t *)MXC_BASE_SPIS)
AnnaBridge	171:3a7713b1edbc	935	#define MXC_BASE_SPIS_FIFO ((uint32_t)0x4010E000UL)
AnnaBridge	171:3a7713b1edbc	936	#define MXC_SPIS_FIFO ((mxc_spis_fifo_regs_t *)MXC_BASE_SPIS_FIFO)
AnnaBridge	171:3a7713b1edbc	937
AnnaBridge	171:3a7713b1edbc	938
AnnaBridge	171:3a7713b1edbc	939
AnnaBridge	171:3a7713b1edbc	940	/* *************************************************************************** */
AnnaBridge	171:3a7713b1edbc	941	/* Bit Shifting */
AnnaBridge	171:3a7713b1edbc	942
AnnaBridge	171:3a7713b1edbc	943	#define MXC_F_BIT_0 (1 << 0)
AnnaBridge	171:3a7713b1edbc	944	#define MXC_F_BIT_1 (1 << 1)
AnnaBridge	171:3a7713b1edbc	945	#define MXC_F_BIT_2 (1 << 2)
AnnaBridge	171:3a7713b1edbc	946	#define MXC_F_BIT_3 (1 << 3)
AnnaBridge	171:3a7713b1edbc	947	#define MXC_F_BIT_4 (1 << 4)
AnnaBridge	171:3a7713b1edbc	948	#define MXC_F_BIT_5 (1 << 5)
AnnaBridge	171:3a7713b1edbc	949	#define MXC_F_BIT_6 (1 << 6)
AnnaBridge	171:3a7713b1edbc	950	#define MXC_F_BIT_7 (1 << 7)
AnnaBridge	171:3a7713b1edbc	951	#define MXC_F_BIT_8 (1 << 8)
AnnaBridge	171:3a7713b1edbc	952	#define MXC_F_BIT_9 (1 << 9)
AnnaBridge	171:3a7713b1edbc	953	#define MXC_F_BIT_10 (1 << 10)
AnnaBridge	171:3a7713b1edbc	954	#define MXC_F_BIT_11 (1 << 11)
AnnaBridge	171:3a7713b1edbc	955	#define MXC_F_BIT_12 (1 << 12)
AnnaBridge	171:3a7713b1edbc	956	#define MXC_F_BIT_13 (1 << 13)
AnnaBridge	171:3a7713b1edbc	957	#define MXC_F_BIT_14 (1 << 14)
AnnaBridge	171:3a7713b1edbc	958	#define MXC_F_BIT_15 (1 << 15)
AnnaBridge	171:3a7713b1edbc	959	#define MXC_F_BIT_16 (1 << 16)
AnnaBridge	171:3a7713b1edbc	960	#define MXC_F_BIT_17 (1 << 17)
AnnaBridge	171:3a7713b1edbc	961	#define MXC_F_BIT_18 (1 << 18)
AnnaBridge	171:3a7713b1edbc	962	#define MXC_F_BIT_19 (1 << 19)
AnnaBridge	171:3a7713b1edbc	963	#define MXC_F_BIT_20 (1 << 20)
AnnaBridge	171:3a7713b1edbc	964	#define MXC_F_BIT_21 (1 << 21)
AnnaBridge	171:3a7713b1edbc	965	#define MXC_F_BIT_22 (1 << 22)
AnnaBridge	171:3a7713b1edbc	966	#define MXC_F_BIT_23 (1 << 23)
AnnaBridge	171:3a7713b1edbc	967	#define MXC_F_BIT_24 (1 << 24)
AnnaBridge	171:3a7713b1edbc	968	#define MXC_F_BIT_25 (1 << 25)
AnnaBridge	171:3a7713b1edbc	969	#define MXC_F_BIT_26 (1 << 26)
AnnaBridge	171:3a7713b1edbc	970	#define MXC_F_BIT_27 (1 << 27)
AnnaBridge	171:3a7713b1edbc	971	#define MXC_F_BIT_28 (1 << 28)
AnnaBridge	171:3a7713b1edbc	972	#define MXC_F_BIT_29 (1 << 29)
AnnaBridge	171:3a7713b1edbc	973	#define MXC_F_BIT_30 (1 << 30)
AnnaBridge	171:3a7713b1edbc	974	#define MXC_F_BIT_31 (1 << 31)
AnnaBridge	171:3a7713b1edbc	975
AnnaBridge	171:3a7713b1edbc	976	/* *************************************************************************** */
AnnaBridge	171:3a7713b1edbc	977
AnnaBridge	171:3a7713b1edbc	978	#define MXC_SET_FIELD(reg, clr, set) ((volatile uint32_t )reg = (((volatile uint32_t )reg & ~clr) \| set))
AnnaBridge	171:3a7713b1edbc	979
AnnaBridge	171:3a7713b1edbc	980	/* *************************************************************************** */
AnnaBridge	171:3a7713b1edbc	981
AnnaBridge	171:3a7713b1edbc	982	#define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2))
AnnaBridge	171:3a7713b1edbc	983	#define MXC_CLRBIT(reg, bit) ((volatile uint32_t )BITBAND(reg, bit) = 0)
AnnaBridge	171:3a7713b1edbc	984	#define MXC_SETBIT(reg, bit) ((volatile uint32_t )BITBAND(reg, bit) = 1)
AnnaBridge	171:3a7713b1edbc	985	#define MXC_GETBIT(reg, bit) ((volatile uint32_t )BITBAND(reg, bit))
AnnaBridge	171:3a7713b1edbc	986
AnnaBridge	171:3a7713b1edbc	987
AnnaBridge	171:3a7713b1edbc	988	/* *************************************************************************** */
AnnaBridge	171:3a7713b1edbc	989
AnnaBridge	171:3a7713b1edbc	990	/* SCB CPACR Register Definitions */
AnnaBridge	171:3a7713b1edbc	991	/* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */
AnnaBridge	171:3a7713b1edbc	992	#define SCB_CPACR_CP10_Pos 20 /!< SCB CPACR: Coprocessor 10 Position /
AnnaBridge	171:3a7713b1edbc	993	#define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /!< SCB CPACR: Coprocessor 10 Mask /
AnnaBridge	171:3a7713b1edbc	994	#define SCB_CPACR_CP11_Pos 22 /!< SCB CPACR: Coprocessor 11 Position /
AnnaBridge	171:3a7713b1edbc	995	#define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /!< SCB CPACR: Coprocessor 11 Mask /
AnnaBridge	171:3a7713b1edbc	996	/*@} end of ingroup product_name /
AnnaBridge	171:3a7713b1edbc	997	#endif /* _MAX3263X_H_ */
AnnaBridge	171:3a7713b1edbc	998