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TARGET_MAX32630FTHR/TOOLCHAIN_IAR/clkman_regs.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 171:3a7713b1edbc | 1 | /** |
AnnaBridge | 171:3a7713b1edbc | 2 | * @file |
AnnaBridge | 171:3a7713b1edbc | 3 | * @brief Type definitions for the Clock Management Interface |
AnnaBridge | 171:3a7713b1edbc | 4 | * |
AnnaBridge | 171:3a7713b1edbc | 5 | */ |
AnnaBridge | 171:3a7713b1edbc | 6 | /* **************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 7 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
AnnaBridge | 171:3a7713b1edbc | 8 | * |
AnnaBridge | 171:3a7713b1edbc | 9 | * Permission is hereby granted, free of charge, to any person obtaining a |
AnnaBridge | 171:3a7713b1edbc | 10 | * copy of this software and associated documentation files (the "Software"), |
AnnaBridge | 171:3a7713b1edbc | 11 | * to deal in the Software without restriction, including without limitation |
AnnaBridge | 171:3a7713b1edbc | 12 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
AnnaBridge | 171:3a7713b1edbc | 13 | * and/or sell copies of the Software, and to permit persons to whom the |
AnnaBridge | 171:3a7713b1edbc | 14 | * Software is furnished to do so, subject to the following conditions: |
AnnaBridge | 171:3a7713b1edbc | 15 | * |
AnnaBridge | 171:3a7713b1edbc | 16 | * The above copyright notice and this permission notice shall be included |
AnnaBridge | 171:3a7713b1edbc | 17 | * in all copies or substantial portions of the Software. |
AnnaBridge | 171:3a7713b1edbc | 18 | * |
AnnaBridge | 171:3a7713b1edbc | 19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
AnnaBridge | 171:3a7713b1edbc | 20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
AnnaBridge | 171:3a7713b1edbc | 21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
AnnaBridge | 171:3a7713b1edbc | 22 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
AnnaBridge | 171:3a7713b1edbc | 23 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
AnnaBridge | 171:3a7713b1edbc | 24 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
AnnaBridge | 171:3a7713b1edbc | 25 | * OTHER DEALINGS IN THE SOFTWARE. |
AnnaBridge | 171:3a7713b1edbc | 26 | * |
AnnaBridge | 171:3a7713b1edbc | 27 | * Except as contained in this notice, the name of Maxim Integrated |
AnnaBridge | 171:3a7713b1edbc | 28 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
AnnaBridge | 171:3a7713b1edbc | 29 | * Products, Inc. Branding Policy. |
AnnaBridge | 171:3a7713b1edbc | 30 | * |
AnnaBridge | 171:3a7713b1edbc | 31 | * The mere transfer of this software does not imply any licenses |
AnnaBridge | 171:3a7713b1edbc | 32 | * of trade secrets, proprietary technology, copyrights, patents, |
AnnaBridge | 171:3a7713b1edbc | 33 | * trademarks, maskwork rights, or any other form of intellectual |
AnnaBridge | 171:3a7713b1edbc | 34 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
AnnaBridge | 171:3a7713b1edbc | 35 | * ownership rights. |
AnnaBridge | 171:3a7713b1edbc | 36 | * |
AnnaBridge | 171:3a7713b1edbc | 37 | * $Date: 2016-08-15 11:08:12 -0500 (Mon, 15 Aug 2016) $ |
AnnaBridge | 171:3a7713b1edbc | 38 | * $Revision: 24058 $ |
AnnaBridge | 171:3a7713b1edbc | 39 | * |
AnnaBridge | 171:3a7713b1edbc | 40 | **************************************************************************** */ |
AnnaBridge | 171:3a7713b1edbc | 41 | |
AnnaBridge | 171:3a7713b1edbc | 42 | /* Define to prevent redundant inclusion */ |
AnnaBridge | 171:3a7713b1edbc | 43 | #ifndef _MXC_CLKMAN_REGS_H_ |
AnnaBridge | 171:3a7713b1edbc | 44 | #define _MXC_CLKMAN_REGS_H_ |
AnnaBridge | 171:3a7713b1edbc | 45 | |
AnnaBridge | 171:3a7713b1edbc | 46 | /* **** Includes **** */ |
AnnaBridge | 171:3a7713b1edbc | 47 | #include <stdint.h> |
AnnaBridge | 171:3a7713b1edbc | 48 | |
AnnaBridge | 171:3a7713b1edbc | 49 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 50 | extern "C" { |
AnnaBridge | 171:3a7713b1edbc | 51 | #endif |
AnnaBridge | 171:3a7713b1edbc | 52 | |
AnnaBridge | 171:3a7713b1edbc | 53 | /// @cond |
AnnaBridge | 171:3a7713b1edbc | 54 | /* |
AnnaBridge | 171:3a7713b1edbc | 55 | If types are not defined elsewhere (CMSIS) define them here |
AnnaBridge | 171:3a7713b1edbc | 56 | */ |
AnnaBridge | 171:3a7713b1edbc | 57 | #ifndef __IO |
AnnaBridge | 171:3a7713b1edbc | 58 | #define __IO volatile |
AnnaBridge | 171:3a7713b1edbc | 59 | #endif |
AnnaBridge | 171:3a7713b1edbc | 60 | #ifndef __I |
AnnaBridge | 171:3a7713b1edbc | 61 | #define __I volatile const |
AnnaBridge | 171:3a7713b1edbc | 62 | #endif |
AnnaBridge | 171:3a7713b1edbc | 63 | #ifndef __O |
AnnaBridge | 171:3a7713b1edbc | 64 | #define __O volatile |
AnnaBridge | 171:3a7713b1edbc | 65 | #endif |
AnnaBridge | 171:3a7713b1edbc | 66 | #ifndef __RO |
AnnaBridge | 171:3a7713b1edbc | 67 | #define __RO volatile const |
AnnaBridge | 171:3a7713b1edbc | 68 | #endif |
AnnaBridge | 171:3a7713b1edbc | 69 | /// @endcond |
AnnaBridge | 171:3a7713b1edbc | 70 | |
AnnaBridge | 171:3a7713b1edbc | 71 | /** |
AnnaBridge | 171:3a7713b1edbc | 72 | * @ingroup clkman |
AnnaBridge | 171:3a7713b1edbc | 73 | * @defgroup clkman_registers Registers |
AnnaBridge | 171:3a7713b1edbc | 74 | * @brief Registers, Bit Masks and Bit Positions |
AnnaBridge | 171:3a7713b1edbc | 75 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 76 | */ |
AnnaBridge | 171:3a7713b1edbc | 77 | |
AnnaBridge | 171:3a7713b1edbc | 78 | /** |
AnnaBridge | 171:3a7713b1edbc | 79 | * Structure type for the Clock Management module registers allowing direct 32-bit access to each register. |
AnnaBridge | 171:3a7713b1edbc | 80 | */ |
AnnaBridge | 171:3a7713b1edbc | 81 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 82 | __IO uint32_t clk_config; /**< <tt>\b 0x0000: </tt> CLKMAN_CLK_CONFIG Register - System Clock Configuration */ |
AnnaBridge | 171:3a7713b1edbc | 83 | __IO uint32_t clk_ctrl; /**< <tt>\b 0x0004: </tt> CLKMAN_CLK_CTRL Register - System Clock Controls */ |
AnnaBridge | 171:3a7713b1edbc | 84 | __IO uint32_t intfl; /**< <tt>\b 0x0008: </tt> CLKMAN_INTFL Register - Interrupt Flags */ |
AnnaBridge | 171:3a7713b1edbc | 85 | __IO uint32_t inten; /**< <tt>\b 0x000C: </tt> CLKMAN_INTEN Register - Interrupt Enable/Disable Controls */ |
AnnaBridge | 171:3a7713b1edbc | 86 | __IO uint32_t trim_calc; /**< <tt>\b 0x0010: </tt> CLKMAN_TRIM_CALC Register - Trim Calculation Controls */ |
AnnaBridge | 171:3a7713b1edbc | 87 | __IO uint32_t i2c_timer_ctrl; /**< <tt>\b 0x0014: </tt> CLKMAN_I2C_TIMER_CTRL Register - I2C Timer Control */ |
AnnaBridge | 171:3a7713b1edbc | 88 | __IO uint32_t cm4_start_clk_en0; /**< <tt>\b 0x0018: </tt> CLKMAN_CM4_START_CLK_EN0 Register - CM4 Start Clock on Interrupt Enable 0 */ |
AnnaBridge | 171:3a7713b1edbc | 89 | __IO uint32_t cm4_start_clk_en1; /**< <tt>\b 0x001C: </tt> CLKMAN_CM4_START_CLK_EN1 Register - CM4 Start Clock on Interrupt Enable 1 */ |
AnnaBridge | 171:3a7713b1edbc | 90 | __IO uint32_t cm4_start_clk_en2; /**< <tt>\b 0x0020: </tt> CLKMAN_CM4_START_CLK_EN2 Register - CM4 Start Clock on Interrupt Enable 2 */ |
AnnaBridge | 171:3a7713b1edbc | 91 | __RO uint32_t rsv024[7]; /**< <tt>\b 0x0024-0x003C:</tt> RESERVED */ |
AnnaBridge | 171:3a7713b1edbc | 92 | __IO uint32_t sys_clk_ctrl_0_cm4; /**< <tt>\b 0x0040: </tt> CLKMAN_SYS_CLK_CTRL_0_CM4 Register - Cortex M4 Clock */ |
AnnaBridge | 171:3a7713b1edbc | 93 | __IO uint32_t sys_clk_ctrl_1_sync; /**< <tt>\b 0x0044: </tt> CLKMAN_SYS_CLK_CTRL_1_SYNC Register - Synchronizer Clock */ |
AnnaBridge | 171:3a7713b1edbc | 94 | __IO uint32_t sys_clk_ctrl_2_spix; /**< <tt>\b 0x0048: </tt> CLKMAN_SYS_CLK_CTRL_2_SPIX Register - SPI XIP Clock */ |
AnnaBridge | 171:3a7713b1edbc | 95 | __IO uint32_t sys_clk_ctrl_3_prng; /**< <tt>\b 0x004C: </tt> CLKMAN_SYS_CLK_CTRL_3_PRNG Register - PRNG Clock */ |
AnnaBridge | 171:3a7713b1edbc | 96 | __IO uint32_t sys_clk_ctrl_4_wdt0; /**< <tt>\b 0x0050: </tt> CLKMAN_SYS_CLK_CTRL_4_WDT0 Register - Watchdog Timer 0 */ |
AnnaBridge | 171:3a7713b1edbc | 97 | __IO uint32_t sys_clk_ctrl_5_wdt1; /**< <tt>\b 0x0054: </tt> CLKMAN_SYS_CLK_CTRL_5_WDT1 Register - Watchdog Timer 1 */ |
AnnaBridge | 171:3a7713b1edbc | 98 | __IO uint32_t sys_clk_ctrl_6_gpio; /**< <tt>\b 0x0058: </tt> CLKMAN_SYS_CLK_CTRL_6_GPIO Register - Clock for GPIO Ports */ |
AnnaBridge | 171:3a7713b1edbc | 99 | __IO uint32_t sys_clk_ctrl_7_pt; /**< <tt>\b 0x005C: </tt> CLKMAN_SYS_CLK_CTRL_7_PT Register - Source Clock for All Pulse Trains */ |
AnnaBridge | 171:3a7713b1edbc | 100 | __IO uint32_t sys_clk_ctrl_8_uart; /**< <tt>\b 0x0060: </tt> CLKMAN_SYS_CLK_CTRL_8_UART Register - Source Clock for All UARTs */ |
AnnaBridge | 171:3a7713b1edbc | 101 | __IO uint32_t sys_clk_ctrl_9_i2cm; /**< <tt>\b 0x0064: </tt> CLKMAN_SYS_CLK_CTRL_9_I2CM Register - Source Clock for All I2C Masters */ |
AnnaBridge | 171:3a7713b1edbc | 102 | __IO uint32_t sys_clk_ctrl_10_i2cs; /**< <tt>\b 0x0068: </tt> CLKMAN_SYS_CLK_CTRL_10_I2CS Register - Source Clock for I2C Slave */ |
AnnaBridge | 171:3a7713b1edbc | 103 | __IO uint32_t sys_clk_ctrl_11_spi0; /**< <tt>\b 0x006C: </tt> CLKMAN_SYS_CLK_CTRL_11_SPI0 Register - SPI Master 0 */ |
AnnaBridge | 171:3a7713b1edbc | 104 | __IO uint32_t sys_clk_ctrl_12_spi1; /**< <tt>\b 0x0070: </tt> CLKMAN_SYS_CLK_CTRL_12_SPI1 Register - SPI Master 1 */ |
AnnaBridge | 171:3a7713b1edbc | 105 | __IO uint32_t sys_clk_ctrl_13_spi2; /**< <tt>\b 0x0074: </tt> CLKMAN_SYS_CLK_CTRL_13_SPI2 Register - SPI Master 2 */ |
AnnaBridge | 171:3a7713b1edbc | 106 | __IO uint32_t sys_clk_ctrl_14_spib; /**< <tt>\b 0x0078: </tt> CLKMAN_SYS_CLK_CTRL_14_SPIB Register - SPI Bridge Clock */ |
AnnaBridge | 171:3a7713b1edbc | 107 | __IO uint32_t sys_clk_ctrl_15_owm; /**< <tt>\b 0x007C: </tt> CLKMAN_SYS_CLK_CTRL_15_OWM Register - 1-Wire Master Clock */ |
AnnaBridge | 171:3a7713b1edbc | 108 | __IO uint32_t sys_clk_ctrl_16_spis; /**< <tt>\b 0x0080: </tt> CLKMAN_SYS_CLK_CTRL_16_SPIS Register - SPI Slave Clock */ |
AnnaBridge | 171:3a7713b1edbc | 109 | __RO uint32_t rsv084[31]; /**< <tt>\b 0x0084-0x00FC:</tt> RESERVED: */ |
AnnaBridge | 171:3a7713b1edbc | 110 | __IO uint32_t crypt_clk_ctrl_0_aes; /**< <tt>\b 0x0100: </tt> CLKMAN_CRYPT_CLK_CTRL_0_AES Register - AES */ |
AnnaBridge | 171:3a7713b1edbc | 111 | __IO uint32_t crypt_clk_ctrl_1_maa; /**< <tt>\b 0x0104: </tt> CLKMAN_CRYPT_CLK_CTRL_1_MAA Register - MAA */ |
AnnaBridge | 171:3a7713b1edbc | 112 | __IO uint32_t crypt_clk_ctrl_2_prng; /**< <tt>\b 0x0108: </tt> CLKMAN_CRYPT_CLK_CTRL_2_PRNG Register - PRNG */ |
AnnaBridge | 171:3a7713b1edbc | 113 | __RO uint32_t rsv10C[13]; /**< <tt>\b 0x010C-0x013C:</tt> RESERVED */ |
AnnaBridge | 171:3a7713b1edbc | 114 | __IO uint32_t clk_gate_ctrl0; /**< <tt>\b 0x0140: </tt> CLKMAN_CLK_GATE_CTRL0 Register - Dynamic Clock Gating Control Register 0 */ |
AnnaBridge | 171:3a7713b1edbc | 115 | __IO uint32_t clk_gate_ctrl1; /**< <tt>\b 0x0144: </tt> CLKMAN_CLK_GATE_CTRL1 Register - Dynamic Clock Gating Control Register 1 */ |
AnnaBridge | 171:3a7713b1edbc | 116 | __IO uint32_t clk_gate_ctrl2; /**< <tt>\b 0x0148: </tt> CLKMAN_CLK_GATE_CTRL2 Register - Dynamic Clock Gating Control Register 2 */ |
AnnaBridge | 171:3a7713b1edbc | 117 | } mxc_clkman_regs_t; |
AnnaBridge | 171:3a7713b1edbc | 118 | /**@} end of clkman_registers */ |
AnnaBridge | 171:3a7713b1edbc | 119 | |
AnnaBridge | 171:3a7713b1edbc | 120 | /* |
AnnaBridge | 171:3a7713b1edbc | 121 | Register offsets for module CLKMAN. |
AnnaBridge | 171:3a7713b1edbc | 122 | */ |
AnnaBridge | 171:3a7713b1edbc | 123 | /** |
AnnaBridge | 171:3a7713b1edbc | 124 | * @ingroup clkman_registers |
AnnaBridge | 171:3a7713b1edbc | 125 | * @defgroup CLKMAN_Register_Offsets Register Offsets |
AnnaBridge | 171:3a7713b1edbc | 126 | * @brief Clock Management Controller Register Offsets from the CLKMAN Base Peripheral Address. |
AnnaBridge | 171:3a7713b1edbc | 127 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 128 | */ |
AnnaBridge | 171:3a7713b1edbc | 129 | #define MXC_R_CLKMAN_OFFS_CLK_CONFIG ((uint32_t)0x00000000UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0000</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 130 | #define MXC_R_CLKMAN_OFFS_CLK_CTRL ((uint32_t)0x00000004UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0004</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 131 | #define MXC_R_CLKMAN_OFFS_INTFL ((uint32_t)0x00000008UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0008</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 132 | #define MXC_R_CLKMAN_OFFS_INTEN ((uint32_t)0x0000000CUL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x000C</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 133 | #define MXC_R_CLKMAN_OFFS_TRIM_CALC ((uint32_t)0x00000010UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0010</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 134 | #define MXC_R_CLKMAN_OFFS_I2C_TIMER_CTRL ((uint32_t)0x00000014UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0014</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 135 | #define MXC_R_CLKMAN_OFFS_CM4_START_CLK_EN0 ((uint32_t)0x00000018UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0018</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 136 | #define MXC_R_CLKMAN_OFFS_CM4_START_CLK_EN1 ((uint32_t)0x0000001CUL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x001C</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 137 | #define MXC_R_CLKMAN_OFFS_CM4_START_CLK_EN2 ((uint32_t)0x00000020UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0020</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 138 | #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_0_CM4 ((uint32_t)0x00000040UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0040</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 139 | #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_1_SYNC ((uint32_t)0x00000044UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0044</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 140 | #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_2_SPIX ((uint32_t)0x00000048UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0048</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 141 | #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_3_PRNG ((uint32_t)0x0000004CUL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x004C</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 142 | #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_4_WDT0 ((uint32_t)0x00000050UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0050</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 143 | #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_5_WDT1 ((uint32_t)0x00000054UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0054</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 144 | #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_6_GPIO ((uint32_t)0x00000058UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0058</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 145 | #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_7_PT ((uint32_t)0x0000005CUL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x005C</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 146 | #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_8_UART ((uint32_t)0x00000060UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0060</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 147 | #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_9_I2CM ((uint32_t)0x00000064UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0064</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 148 | #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_10_I2CS ((uint32_t)0x00000068UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0068</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 149 | #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_11_SPI0 ((uint32_t)0x0000006CUL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x006C</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 150 | #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_12_SPI1 ((uint32_t)0x00000070UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0070</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 151 | #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_13_SPI2 ((uint32_t)0x00000074UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0074</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 152 | #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_14_SPIB ((uint32_t)0x00000078UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0078</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 153 | #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_15_OWM ((uint32_t)0x0000007CUL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x007C</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 154 | #define MXC_R_CLKMAN_OFFS_SYS_CLK_CTRL_16_SPIS ((uint32_t)0x00000080UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0080</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 155 | #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_0_AES ((uint32_t)0x00000100UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0100</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 156 | #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_1_MAA ((uint32_t)0x00000104UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0104</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 157 | #define MXC_R_CLKMAN_OFFS_CRYPT_CLK_CTRL_2_PRNG ((uint32_t)0x00000108UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0108</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 158 | #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL0 ((uint32_t)0x00000140UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0140</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 159 | #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL1 ((uint32_t)0x00000144UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0144</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 160 | #define MXC_R_CLKMAN_OFFS_CLK_GATE_CTRL2 ((uint32_t)0x00000148UL) /**< Offset from the CLKMAN Base Peripheral Address:<tt>\b 0x0148</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 161 | /**@} end of CLKMAN_Register_Offsets */ |
AnnaBridge | 171:3a7713b1edbc | 162 | /** |
AnnaBridge | 171:3a7713b1edbc | 163 | * @ingroup clkman_registers |
AnnaBridge | 171:3a7713b1edbc | 164 | * @defgroup clkman_clk_config CLKMAN_CLK_CONFIG Register |
AnnaBridge | 171:3a7713b1edbc | 165 | * @brief Field Positions and Masks |
AnnaBridge | 171:3a7713b1edbc | 166 | */ |
AnnaBridge | 171:3a7713b1edbc | 167 | #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS 0 /**< CRYPTO_ENABLE Position */ |
AnnaBridge | 171:3a7713b1edbc | 168 | #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_ENABLE_POS)) /**< CRYPTO_ENABLE Mask */ |
AnnaBridge | 171:3a7713b1edbc | 169 | #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS 4 /**< CRYPTO_STABILITY_COUNT Position */ |
AnnaBridge | 171:3a7713b1edbc | 170 | #define MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Mask */ |
AnnaBridge | 171:3a7713b1edbc | 171 | /**@}*/ |
AnnaBridge | 171:3a7713b1edbc | 172 | /** |
AnnaBridge | 171:3a7713b1edbc | 173 | * @ingroup clkman_registers |
AnnaBridge | 171:3a7713b1edbc | 174 | * @defgroup clkman_clk_ctrl CLKMAN_CLK_CTRL Register |
AnnaBridge | 171:3a7713b1edbc | 175 | * @brief Field Positions and Masks |
AnnaBridge | 171:3a7713b1edbc | 176 | */ |
AnnaBridge | 171:3a7713b1edbc | 177 | #define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS 0 /**< SYSTEM_SOURCE_SELECT Position */ |
AnnaBridge | 171:3a7713b1edbc | 178 | #define MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS)) /**< SYSTEM_SOURCE_SELECT Mask */ |
AnnaBridge | 171:3a7713b1edbc | 179 | #define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE_POS 4 /**< USB_CLOCK_ENABLE Position */ |
AnnaBridge | 171:3a7713b1edbc | 180 | #define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_ENABLE_POS)) /**< USB_CLOCK_ENABLE Mask */ |
AnnaBridge | 171:3a7713b1edbc | 181 | #define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT_POS 5 /**< USB_CLOCK_SELECT Position */ |
AnnaBridge | 171:3a7713b1edbc | 182 | #define MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_USB_CLOCK_SELECT_POS)) /**< USB_CLOCK_SELECT Mask */ |
AnnaBridge | 171:3a7713b1edbc | 183 | #define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE_POS 8 /**< CRYPTO_CLOCK_ENABLE Position */ |
AnnaBridge | 171:3a7713b1edbc | 184 | #define MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_CRYPTO_CLOCK_ENABLE_POS)) /**< CRYPTO_CLOCK_ENABLE Mask */ |
AnnaBridge | 171:3a7713b1edbc | 185 | #define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS 12 /**< RTOS_MODE Field Position */ |
AnnaBridge | 171:3a7713b1edbc | 186 | #define MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE_POS)) /**< RTOS_MODE Field Mask */ |
AnnaBridge | 171:3a7713b1edbc | 187 | #define MXC_F_CLKMAN_CLK_CTRL_CPU_DYNAMIC_CLOCK_POS 13 /**< CPU_DYNAMIC_CLOCK Field Position */ |
AnnaBridge | 171:3a7713b1edbc | 188 | #define MXC_F_CLKMAN_CLK_CTRL_CPU_DYNAMIC_CLOCK ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_CPU_DYNAMIC_CLOCK_POS)) /**< CPU_DYNAMIC_CLOCK Field Mask */ |
AnnaBridge | 171:3a7713b1edbc | 189 | #define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE_POS 16 /**< WDT0_CLOCK_ENABLE Field Position */ |
AnnaBridge | 171:3a7713b1edbc | 190 | #define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_ENABLE_POS)) /**< WDT0_CLOCK_ENABLE Field Mask */ |
AnnaBridge | 171:3a7713b1edbc | 191 | #define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS 17 /**< WDT0_CLOCK_SELECT Field Position */ |
AnnaBridge | 171:3a7713b1edbc | 192 | #define MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS)) /**< WDT0_CLOCK_SELECT Field Mask */ |
AnnaBridge | 171:3a7713b1edbc | 193 | #define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE_POS 20 /**< WDT1_CLOCK_ENABLE Field Position */ |
AnnaBridge | 171:3a7713b1edbc | 194 | #define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_ENABLE_POS)) /**< WDT1_CLOCK_ENABLE Field Mask */ |
AnnaBridge | 171:3a7713b1edbc | 195 | #define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS 21 /**< WDT1_CLOCK_SELECT Field Position */ |
AnnaBridge | 171:3a7713b1edbc | 196 | #define MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS)) /**< WDT1_CLOCK_SELECT Field Mask */ |
AnnaBridge | 171:3a7713b1edbc | 197 | #define MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE_POS 24 /**< ADC_CLOCK_ENABLE Field Position */ |
AnnaBridge | 171:3a7713b1edbc | 198 | #define MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_CLK_CTRL_ADC_CLOCK_ENABLE_POS)) /**< ADC_CLOCK_ENABLE Field Mask */ |
AnnaBridge | 171:3a7713b1edbc | 199 | /**@}*/ |
AnnaBridge | 171:3a7713b1edbc | 200 | /** |
AnnaBridge | 171:3a7713b1edbc | 201 | * @ingroup clkman_registers |
AnnaBridge | 171:3a7713b1edbc | 202 | * @defgroup clkman_int_flags CLKMAN_INTFL Register |
AnnaBridge | 171:3a7713b1edbc | 203 | * @brief Interrupt Flag Positions and Masks |
AnnaBridge | 171:3a7713b1edbc | 204 | */ |
AnnaBridge | 171:3a7713b1edbc | 205 | #define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS 0 /**< CRYPTO_STABLE Interrupt Flag Position */ |
AnnaBridge | 171:3a7713b1edbc | 206 | #define MXC_F_CLKMAN_INTFL_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_CRYPTO_STABLE_POS)) /**< CRYPTO_STABLE Interrupt Flag Mask */ |
AnnaBridge | 171:3a7713b1edbc | 207 | #define MXC_F_CLKMAN_INTFL_SYS_RO_STABLE_POS 1 /**< SYS_RO_STABLE Interrupt Flag Position */ |
AnnaBridge | 171:3a7713b1edbc | 208 | #define MXC_F_CLKMAN_INTFL_SYS_RO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTFL_SYS_RO_STABLE_POS)) /**< SYS_RO_STABLE Interrupt Flag Mask */ |
AnnaBridge | 171:3a7713b1edbc | 209 | /**@}*/ |
AnnaBridge | 171:3a7713b1edbc | 210 | /** |
AnnaBridge | 171:3a7713b1edbc | 211 | * @ingroup clkman_registers |
AnnaBridge | 171:3a7713b1edbc | 212 | * @defgroup clkman_int_enable CLKMAN_INTEN Register |
AnnaBridge | 171:3a7713b1edbc | 213 | * @brief Interrupt Enable Positions and Masks |
AnnaBridge | 171:3a7713b1edbc | 214 | */ |
AnnaBridge | 171:3a7713b1edbc | 215 | #define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS 0 /**< CRYPTO_STABLE Field Position */ |
AnnaBridge | 171:3a7713b1edbc | 216 | #define MXC_F_CLKMAN_INTEN_CRYPTO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_CRYPTO_STABLE_POS)) /**< CRYPTO_STABLE Field Mask */ |
AnnaBridge | 171:3a7713b1edbc | 217 | #define MXC_F_CLKMAN_INTEN_SYS_RO_STABLE_POS 1 /**< SYS_RO_STABLE Field Position */ |
AnnaBridge | 171:3a7713b1edbc | 218 | #define MXC_F_CLKMAN_INTEN_SYS_RO_STABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_INTEN_SYS_RO_STABLE_POS)) /**< SYS_RO_STABLE Field Mask */ |
AnnaBridge | 171:3a7713b1edbc | 219 | /**@}*/ |
AnnaBridge | 171:3a7713b1edbc | 220 | /** |
AnnaBridge | 171:3a7713b1edbc | 221 | * @ingroup clkman_registers |
AnnaBridge | 171:3a7713b1edbc | 222 | * @defgroup clkman_trim_calc CLKMAN_TRIM_CALC Register |
AnnaBridge | 171:3a7713b1edbc | 223 | * @brief Field Positions and Masks |
AnnaBridge | 171:3a7713b1edbc | 224 | */ |
AnnaBridge | 171:3a7713b1edbc | 225 | #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS 0 /**< TRIM_CLK_SEL Field Position */ |
AnnaBridge | 171:3a7713b1edbc | 226 | #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CLK_SEL_POS)) /**< TRIM_CLK_SEL Field Mask */ |
AnnaBridge | 171:3a7713b1edbc | 227 | #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS 1 /**< TRIM_CALC_START Field Position */ |
AnnaBridge | 171:3a7713b1edbc | 228 | #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_START_POS)) /**< TRIM_CALC_START Field Mask */ |
AnnaBridge | 171:3a7713b1edbc | 229 | #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS 2 /**< TRIM_CALC_COMPLETED Field Position */ |
AnnaBridge | 171:3a7713b1edbc | 230 | #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_COMPLETED_POS)) /**< TRIM_CALC_COMPLETED Field Mask */ |
AnnaBridge | 171:3a7713b1edbc | 231 | #define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS 3 /**< TRIM_ENABLE Field Position */ |
AnnaBridge | 171:3a7713b1edbc | 232 | #define MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_TRIM_CALC_TRIM_ENABLE_POS)) /**< TRIM_ENABLE Field Mask */ |
AnnaBridge | 171:3a7713b1edbc | 233 | #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS 16 /**< TRIM_CALC_RESULTS Field Position */ |
AnnaBridge | 171:3a7713b1edbc | 234 | #define MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS ((uint32_t)(0x000003FFUL << MXC_F_CLKMAN_TRIM_CALC_TRIM_CALC_RESULTS_POS)) /**< TRIM_CALC_RESULTS Field Mask */ |
AnnaBridge | 171:3a7713b1edbc | 235 | /**@}*/ |
AnnaBridge | 171:3a7713b1edbc | 236 | /** |
AnnaBridge | 171:3a7713b1edbc | 237 | * @ingroup clkman_registers |
AnnaBridge | 171:3a7713b1edbc | 238 | * @defgroup clkman_i2c_1ms CLKMAN_I2C_TIMER_CTRL Register |
AnnaBridge | 171:3a7713b1edbc | 239 | * @brief Field Positions and Masks |
AnnaBridge | 171:3a7713b1edbc | 240 | */ |
AnnaBridge | 171:3a7713b1edbc | 241 | #define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS 0 /**< I2C_1MS_TIMER_EN Position */ |
AnnaBridge | 171:3a7713b1edbc | 242 | #define MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN ((uint32_t)(0x00000001UL << MXC_F_CLKMAN_I2C_TIMER_CTRL_I2C_1MS_TIMER_EN_POS)) /**< I2C_1MS_TIMER_EN Mask */ |
AnnaBridge | 171:3a7713b1edbc | 243 | /**@}*/ |
AnnaBridge | 171:3a7713b1edbc | 244 | /** |
AnnaBridge | 171:3a7713b1edbc | 245 | * @ingroup clkman_registers |
AnnaBridge | 171:3a7713b1edbc | 246 | * @defgroup clkman_cm4 CLKMAN_CM4 Register |
AnnaBridge | 171:3a7713b1edbc | 247 | * @brief Field Positions and Masks |
AnnaBridge | 171:3a7713b1edbc | 248 | */ |
AnnaBridge | 171:3a7713b1edbc | 249 | #define MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS_POS 0 /**< CLK_EN0_INTS Position */ |
AnnaBridge | 171:3a7713b1edbc | 250 | #define MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLKMAN_CM4_START_CLK_EN0_INTS_POS)) /**< CLK_EN0_INTS Mask */ |
AnnaBridge | 171:3a7713b1edbc | 251 | |
AnnaBridge | 171:3a7713b1edbc | 252 | #define MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS_POS 0 /**< CLK_EN1_INTS Position */ |
AnnaBridge | 171:3a7713b1edbc | 253 | #define MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLKMAN_CM4_START_CLK_EN1_INTS_POS)) /**< CLK_EN1_INTS Mask */ |
AnnaBridge | 171:3a7713b1edbc | 254 | |
AnnaBridge | 171:3a7713b1edbc | 255 | #define MXC_F_CLKMAN_CM4_START_CLK_EN2_INTS_POS 0 /**< CLK_EN2_INTS Position */ |
AnnaBridge | 171:3a7713b1edbc | 256 | #define MXC_F_CLKMAN_CM4_START_CLK_EN2_INTS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CLKMAN_CM4_START_CLK_EN2_INTS_POS)) /**< CLK_EN2_INTS Mask */ |
AnnaBridge | 171:3a7713b1edbc | 257 | /**@}*/ |
AnnaBridge | 171:3a7713b1edbc | 258 | /** |
AnnaBridge | 171:3a7713b1edbc | 259 | * @ingroup clkman_registers |
AnnaBridge | 171:3a7713b1edbc | 260 | * @defgroup clkman_sysclk_ctrl CLKMAN_SYS_CLK_CTRL Register |
AnnaBridge | 171:3a7713b1edbc | 261 | * @brief Field Positions and Masks |
AnnaBridge | 171:3a7713b1edbc | 262 | */ |
AnnaBridge | 171:3a7713b1edbc | 263 | #define MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS 0 /**< CM4_CM4_CLK_SCALE Position */ |
AnnaBridge | 171:3a7713b1edbc | 264 | #define MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) /**< CM4_CM4_CLK_SCALE Mask */ |
AnnaBridge | 171:3a7713b1edbc | 265 | #define MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE_POS 0 /**< SYNC_SYNC_CLK_SCALE Position */ |
AnnaBridge | 171:3a7713b1edbc | 266 | #define MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_1_SYNC_SYNC_CLK_SCALE_POS)) /**< SYNC_SYNC_CLK_SCALE Mask */ |
AnnaBridge | 171:3a7713b1edbc | 267 | #define MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE_POS 0 /**< SPIX_SPIX_CLK_SCALE Position */ |
AnnaBridge | 171:3a7713b1edbc | 268 | #define MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_2_SPIX_SPIX_CLK_SCALE_POS)) /**< SPIX_SPIX_CLK_SCALE Mask */ |
AnnaBridge | 171:3a7713b1edbc | 269 | #define MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE_POS 0 /**< PRNG_PRNG_CLK_SCALE Position */ |
AnnaBridge | 171:3a7713b1edbc | 270 | #define MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_3_PRNG_PRNG_CLK_SCALE_POS)) /**< PRNG_PRNG_CLK_SCALE Mask */ |
AnnaBridge | 171:3a7713b1edbc | 271 | #define MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE_POS 0 /**< WDT0_WATCHDOG0_CLK_ Position */ |
AnnaBridge | 171:3a7713b1edbc | 272 | #define MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_4_WDT0_WATCHDOG0_CLK_SCALE_POS)) /**< WDT0_WATCHDOG0_CLK_ Mask */ |
AnnaBridge | 171:3a7713b1edbc | 273 | #define MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE_POS 0 /**< WDT1_WATCHDOG1_CLK_ Position */ |
AnnaBridge | 171:3a7713b1edbc | 274 | #define MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_5_WDT1_WATCHDOG1_CLK_SCALE_POS)) /**< WDT1_WATCHDOG1_CLK_ Mask */ |
AnnaBridge | 171:3a7713b1edbc | 275 | #define MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE_POS 0 /**< GPIO_GPIO_CLK_SCALE Position */ |
AnnaBridge | 171:3a7713b1edbc | 276 | #define MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_6_GPIO_GPIO_CLK_SCALE_POS)) /**< GPIO_GPIO_CLK_SCALE Mask */ |
AnnaBridge | 171:3a7713b1edbc | 277 | #define MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE_POS 0 /**< PT_PULSE_TRAIN_CLK_ Position */ |
AnnaBridge | 171:3a7713b1edbc | 278 | #define MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_7_PT_PULSE_TRAIN_CLK_SCALE_POS)) /**< PT_PULSE_TRAIN_CLK_ Mask */ |
AnnaBridge | 171:3a7713b1edbc | 279 | #define MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE_POS 0 /**< UART_UART_CLK_SCALE Position */ |
AnnaBridge | 171:3a7713b1edbc | 280 | #define MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_8_UART_UART_CLK_SCALE_POS)) /**< UART_UART_CLK_SCALE Mask */ |
AnnaBridge | 171:3a7713b1edbc | 281 | #define MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE_POS 0 /**< I2CM_I2CM_CLK_SCALE Position */ |
AnnaBridge | 171:3a7713b1edbc | 282 | #define MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_9_I2CM_I2CM_CLK_SCALE_POS)) /**< I2CM_I2CM_CLK_SCALE Mask */ |
AnnaBridge | 171:3a7713b1edbc | 283 | #define MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE_POS 0 /**< I2CS_I2CS_CLK_SCALE Position */ |
AnnaBridge | 171:3a7713b1edbc | 284 | #define MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_10_I2CS_I2CS_CLK_SCALE_POS)) /**< I2CS_I2CS_CLK_SCALE Mask */ |
AnnaBridge | 171:3a7713b1edbc | 285 | #define MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE_POS 0 /**< PI0_SPI0_CLK_SCALE Position */ |
AnnaBridge | 171:3a7713b1edbc | 286 | #define MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_11_SPI0_SPI0_CLK_SCALE_POS)) /**< SPI0_SPI0_CLK_SCALE Mask */ |
AnnaBridge | 171:3a7713b1edbc | 287 | #define MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE_POS 0 /**< SPI1_SPI1_CLK_SCALE Position */ |
AnnaBridge | 171:3a7713b1edbc | 288 | #define MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_12_SPI1_SPI1_CLK_SCALE_POS)) /**< SPI1_SPI1_CLK_SCALE Mask */ |
AnnaBridge | 171:3a7713b1edbc | 289 | #define MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE_POS 0 /**< SPI2_SPI2_CLK_SCALE Position */ |
AnnaBridge | 171:3a7713b1edbc | 290 | #define MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_13_SPI2_SPI2_CLK_SCALE_POS)) /**< SPI2_SPI2_CLK_SCALE Mask */ |
AnnaBridge | 171:3a7713b1edbc | 291 | #define MXC_F_CLKMAN_SYS_CLK_CTRL_14_SPIB_SPIB_CLK_SCALE_POS 0 /**< SPIB_SPIB_CLK_SCALE Position */ |
AnnaBridge | 171:3a7713b1edbc | 292 | #define MXC_F_CLKMAN_SYS_CLK_CTRL_14_SPIB_SPIB_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_14_SPIB_SPIB_CLK_SCALE_POS)) /**< SPIB_SPIB_CLK_SCALE Mask */ |
AnnaBridge | 171:3a7713b1edbc | 293 | #define MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE_POS 0 /**< OWM_OWM_CLK_SCALE Position */ |
AnnaBridge | 171:3a7713b1edbc | 294 | #define MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_15_OWM_OWM_CLK_SCALE_POS)) /**< OWM_OWM_CLK_SCALE Mask */ |
AnnaBridge | 171:3a7713b1edbc | 295 | #define MXC_F_CLKMAN_SYS_CLK_CTRL_16_SPIS_SPIS_CLK_SCALE_POS 0 /**< PIS_SPIS_CLK_SCALE Position */ |
AnnaBridge | 171:3a7713b1edbc | 296 | #define MXC_F_CLKMAN_SYS_CLK_CTRL_16_SPIS_SPIS_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_SYS_CLK_CTRL_16_SPIS_SPIS_CLK_SCALE_POS)) /**< SPIS_SPIS_CLK_SCALE Mask */ |
AnnaBridge | 171:3a7713b1edbc | 297 | /**@}*/ |
AnnaBridge | 171:3a7713b1edbc | 298 | /** |
AnnaBridge | 171:3a7713b1edbc | 299 | * @ingroup clkman_registers |
AnnaBridge | 171:3a7713b1edbc | 300 | * @defgroup clkman_crypt_clk_ctrl CLKMAN_CRYPT_CLK_CTRL Register |
AnnaBridge | 171:3a7713b1edbc | 301 | * @brief Field Positions and Masks |
AnnaBridge | 171:3a7713b1edbc | 302 | */ |
AnnaBridge | 171:3a7713b1edbc | 303 | #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS 0 /**< AES_AES_CLK_SCALE Position */ |
AnnaBridge | 171:3a7713b1edbc | 304 | #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_0_AES_AES_CLK_SCALE_POS)) /**< AES_AES_CLK_SCALE Mask */ |
AnnaBridge | 171:3a7713b1edbc | 305 | #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE_POS 0 /**< MAA_MAA_CLK_SCALE Position */ |
AnnaBridge | 171:3a7713b1edbc | 306 | #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_1_MAA_MAA_CLK_SCALE_POS)) /**< MAA_MAA_CLK_SCALE Mask */ |
AnnaBridge | 171:3a7713b1edbc | 307 | #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS 0 /**< PRNG_PRNG_CLK_SCALE Position */ |
AnnaBridge | 171:3a7713b1edbc | 308 | #define MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE ((uint32_t)(0x0000000FUL << MXC_F_CLKMAN_CRYPT_CLK_CTRL_2_PRNG_PRNG_CLK_SCALE_POS)) /**< PRNG_PRNG_CLK_SCALE Mask */ |
AnnaBridge | 171:3a7713b1edbc | 309 | /**@}*/ |
AnnaBridge | 171:3a7713b1edbc | 310 | /** |
AnnaBridge | 171:3a7713b1edbc | 311 | * @ingroup clkman_registers |
AnnaBridge | 171:3a7713b1edbc | 312 | * @defgroup clkman_clk_gate_ctrl CLKMAN_CLK_GATE_CTRL Register |
AnnaBridge | 171:3a7713b1edbc | 313 | * @brief Peripheral Clock Gating Field Positions and Masks |
AnnaBridge | 171:3a7713b1edbc | 314 | */ |
AnnaBridge | 171:3a7713b1edbc | 315 | #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER_POS 0 /**< CM4_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 316 | #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CM4_CLK_GATER_POS)) /**< CM4_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 317 | #define MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER_POS 2 /**< AHB32_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 318 | #define MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_AHB32_CLK_GATER_POS)) /**< AHB32_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 319 | #define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS 4 /**< ICACHE_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 320 | #define MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_ICACHE_CLK_GATER_POS)) /**< ICACHE_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 321 | #define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS 6 /**< FLASH_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 322 | #define MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_FLASH_CLK_GATER_POS)) /**< FLASH_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 323 | #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS 8 /**< SRAM_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 324 | #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SRAM_CLK_GATER_POS)) /**< SRAM_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 325 | #define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS 10 /**< APB_BRIDGE_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 326 | #define MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_APB_BRIDGE_CLK_GATER_POS)) /**< APB_BRIDGE_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 327 | #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS 12 /**< SYSMAN_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 328 | #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SYSMAN_CLK_GATER_POS)) /**< SYSMAN_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 329 | #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER_POS 14 /**< PTP_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 330 | #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PTP_CLK_GATER_POS)) /**< PTP_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 331 | #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER_POS 16 /**< SSB_MUX_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 332 | #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SSB_MUX_CLK_GATER_POS)) /**< SSB_MUX_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 333 | #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER_POS 18 /**< PAD_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 334 | #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PAD_CLK_GATER_POS)) /**< PAD_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 335 | #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER_POS 20 /**< SPIX_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 336 | #define MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_SPIX_CLK_GATER_POS)) /**< SPIX_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 337 | #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER_POS 22 /**< PMU_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 338 | #define MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER_POS)) /**< PMU_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 339 | #define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS 24 /**< USB_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 340 | #define MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_USB_CLK_GATER_POS)) /**< USB_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 341 | #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER_POS 26 /**< CRC_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 342 | #define MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_CRC_CLK_GATER_POS)) /**< CRC_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 343 | #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER_POS 28 /**< TPU_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 344 | #define MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_TPU_CLK_GATER_POS)) /**< TPU_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 345 | #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS 30 /**< WATCHDOG0_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 346 | #define MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL0_WATCHDOG0_CLK_GATER_POS)) /**< WATCHDOG0_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 347 | #define MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER_POS 0 /**< WATCHDOG1_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 348 | #define MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_WATCHDOG1_CLK_GATER_POS)) /**< WATCHDOG1_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 349 | #define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS 2 /**< GPIO_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 350 | #define MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_GPIO_CLK_GATER_POS)) /**< GPIO_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 351 | #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER_POS 4 /**< TIMER0_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 352 | #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER0_CLK_GATER_POS)) /**< TIMER0_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 353 | #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER_POS 6 /**< TIMER1_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 354 | #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER1_CLK_GATER_POS)) /**< TIMER1_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 355 | #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER_POS 8 /**< TIMER2_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 356 | #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER2_CLK_GATER_POS)) /**< TIMER2_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 357 | #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER_POS 10 /**< TIMER3_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 358 | #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER3_CLK_GATER_POS)) /**< TIMER3_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 359 | #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER_POS 12 /**< TIMER4_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 360 | #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER4_CLK_GATER_POS)) /**< TIMER4_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 361 | #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER_POS 14 /**< TIMER5_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 362 | #define MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_TIMER5_CLK_GATER_POS)) /**< TIMER5_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 363 | #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS 16 /**< PULSETRAIN_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 364 | #define MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_PULSETRAIN_CLK_GATER_POS)) /**< PULSETRAIN_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 365 | #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER_POS 18 /**< UART0_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 366 | #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART0_CLK_GATER_POS)) /**< UART0_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 367 | #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER_POS 20 /**< UART1_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 368 | #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART1_CLK_GATER_POS)) /**< UART1_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 369 | #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER_POS 22 /**< UART2_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 370 | #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART2_CLK_GATER_POS)) /**< UART2_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 371 | #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART3_CLK_GATER_POS 24 /**< UART3_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 372 | #define MXC_F_CLKMAN_CLK_GATE_CTRL1_UART3_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_UART3_CLK_GATER_POS)) /**< UART3_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 373 | #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS 26 /**< I2CM0_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 374 | #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM0_CLK_GATER_POS)) /**< I2CM0_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 375 | #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS 28 /**< I2CM1_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 376 | #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM1_CLK_GATER_POS)) /**< I2CM1_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 377 | #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM2_CLK_GATER_POS 30 /**< I2CM2_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 378 | #define MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL1_I2CM2_CLK_GATER_POS)) /**< I2CM2_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 379 | #define MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER_POS 0 /**< I2CS_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 380 | #define MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_I2CS_CLK_GATER_POS)) /**< I2CS_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 381 | #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER_POS 2 /**< SPI0_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 382 | #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI0_CLK_GATER_POS)) /**< SPI0_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 383 | #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER_POS 4 /**< SPI1_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 384 | #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI1_CLK_GATER_POS)) /**< SPI1_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 385 | #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER_POS 6 /**< SPI2_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 386 | #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI2_CLK_GATER_POS)) /**< SPI2_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 387 | #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI_BRIDGE_CLK_GATER_POS 8 /**< SPI_BRIDGE_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 388 | #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI_BRIDGE_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPI_BRIDGE_CLK_GATER_POS)) /**< SPI_BRIDGE_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 389 | #define MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER_POS 10 /**< OWM_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 390 | #define MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_OWM_CLK_GATER_POS)) /**< OWM_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 391 | #define MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER_POS 12 /**< ADC_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 392 | #define MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_ADC_CLK_GATER_POS)) /**< ADC_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 393 | #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPIS_CLK_GATER_POS 14 /**< SPIS_CLK_GATER Position */ |
AnnaBridge | 171:3a7713b1edbc | 394 | #define MXC_F_CLKMAN_CLK_GATE_CTRL2_SPIS_CLK_GATER ((uint32_t)(0x00000003UL << MXC_F_CLKMAN_CLK_GATE_CTRL2_SPIS_CLK_GATER_POS)) /**< SPIS_CLK_GATER Mask */ |
AnnaBridge | 171:3a7713b1edbc | 395 | /**@}*/ |
AnnaBridge | 171:3a7713b1edbc | 396 | /** |
AnnaBridge | 171:3a7713b1edbc | 397 | * @ingroup clkman_clk_config |
AnnaBridge | 171:3a7713b1edbc | 398 | * @defgroup clkman_crypto_stability_count CRYPTO_STABILITY_COUNT Value Settings and Shifted Value Settings |
AnnaBridge | 171:3a7713b1edbc | 399 | * @brief Crypto Clock Stability Count Setting Values and Shifted Values |
AnnaBridge | 171:3a7713b1edbc | 400 | */ |
AnnaBridge | 171:3a7713b1edbc | 401 | #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS ((uint32_t)(0x00000000UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>8</SUP> */ |
AnnaBridge | 171:3a7713b1edbc | 402 | #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS ((uint32_t)(0x00000001UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>9</SUP> */ |
AnnaBridge | 171:3a7713b1edbc | 403 | #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS ((uint32_t)(0x00000002UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>10</SUP> */ |
AnnaBridge | 171:3a7713b1edbc | 404 | #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS ((uint32_t)(0x00000003UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>11</SUP> */ |
AnnaBridge | 171:3a7713b1edbc | 405 | #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS ((uint32_t)(0x00000004UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>12</SUP> */ |
AnnaBridge | 171:3a7713b1edbc | 406 | #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS ((uint32_t)(0x00000005UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>13</SUP> */ |
AnnaBridge | 171:3a7713b1edbc | 407 | #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS ((uint32_t)(0x00000006UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>14</SUP> */ |
AnnaBridge | 171:3a7713b1edbc | 408 | #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS ((uint32_t)(0x00000007UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>15</SUP> */ |
AnnaBridge | 171:3a7713b1edbc | 409 | #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS ((uint32_t)(0x00000008UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>16</SUP> */ |
AnnaBridge | 171:3a7713b1edbc | 410 | #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS ((uint32_t)(0x00000009UL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>17</SUP> */ |
AnnaBridge | 171:3a7713b1edbc | 411 | #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS ((uint32_t)(0x0000000AUL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>18</SUP> */ |
AnnaBridge | 171:3a7713b1edbc | 412 | #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS ((uint32_t)(0x0000000BUL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>19</SUP> */ |
AnnaBridge | 171:3a7713b1edbc | 413 | #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS ((uint32_t)(0x0000000CUL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>20</SUP> */ |
AnnaBridge | 171:3a7713b1edbc | 414 | #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS ((uint32_t)(0x0000000DUL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>21</SUP> */ |
AnnaBridge | 171:3a7713b1edbc | 415 | #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS ((uint32_t)(0x0000000EUL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>22</SUP> */ |
AnnaBridge | 171:3a7713b1edbc | 416 | #define MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS ((uint32_t)(0x0000000FUL)) /**< CRYPTO_STABILITY_COUNT Value = 2<SUP>23</SUP> */ |
AnnaBridge | 171:3a7713b1edbc | 417 | |
AnnaBridge | 171:3a7713b1edbc | 418 | #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_8_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>8</SUP> */ |
AnnaBridge | 171:3a7713b1edbc | 419 | #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_9_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>9</SUP> */ |
AnnaBridge | 171:3a7713b1edbc | 420 | #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_10_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>10</SUP> */ |
AnnaBridge | 171:3a7713b1edbc | 421 | #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_11_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>11</SUP> */ |
AnnaBridge | 171:3a7713b1edbc | 422 | #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_12_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>12</SUP> */ |
AnnaBridge | 171:3a7713b1edbc | 423 | #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_13_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>13</SUP> */ |
AnnaBridge | 171:3a7713b1edbc | 424 | #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_14_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>14</SUP> */ |
AnnaBridge | 171:3a7713b1edbc | 425 | #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_15_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>15</SUP> */ |
AnnaBridge | 171:3a7713b1edbc | 426 | #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_16_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>16</SUP> */ |
AnnaBridge | 171:3a7713b1edbc | 427 | #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_17_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>17</SUP> */ |
AnnaBridge | 171:3a7713b1edbc | 428 | #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_18_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>18</SUP> */ |
AnnaBridge | 171:3a7713b1edbc | 429 | #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_19_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>19</SUP> */ |
AnnaBridge | 171:3a7713b1edbc | 430 | #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_20_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>20</SUP> */ |
AnnaBridge | 171:3a7713b1edbc | 431 | #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_21_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>21</SUP> */ |
AnnaBridge | 171:3a7713b1edbc | 432 | #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_22_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>22</SUP> */ |
AnnaBridge | 171:3a7713b1edbc | 433 | #define MXC_S_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS ((uint32_t)(MXC_V_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_2_EXP_23_CLOCKS << MXC_F_CLKMAN_CLK_CONFIG_CRYPTO_STABILITY_COUNT_POS)) /**< CRYPTO_STABILITY_COUNT Shifted Value for 2<SUP>23</SUP> */ |
AnnaBridge | 171:3a7713b1edbc | 434 | |
AnnaBridge | 171:3a7713b1edbc | 435 | /**@} clkman_crypto_stability_count */ |
AnnaBridge | 171:3a7713b1edbc | 436 | |
AnnaBridge | 171:3a7713b1edbc | 437 | /** |
AnnaBridge | 171:3a7713b1edbc | 438 | * @ingroup clkman_clk_ctrl |
AnnaBridge | 171:3a7713b1edbc | 439 | * @defgroup clkman_sysclock_select System Clock Select Values |
AnnaBridge | 171:3a7713b1edbc | 440 | * @brief System Clock Selection Values and Shifted Values for selecting the system clock source |
AnnaBridge | 171:3a7713b1edbc | 441 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 442 | */ |
AnnaBridge | 171:3a7713b1edbc | 443 | #define MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 ((uint32_t)(0x00000000UL)) /**< Value Mask: SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 */ |
AnnaBridge | 171:3a7713b1edbc | 444 | #define MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO ((uint32_t)(0x00000001UL)) /**< Value Mask: SYSTEM_SOURCE_SELECT_96MHZ_RO */ |
AnnaBridge | 171:3a7713b1edbc | 445 | #define MXC_S_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 ((uint32_t)(MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS)) /**< Value Shifted: SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2 */ |
AnnaBridge | 171:3a7713b1edbc | 446 | #define MXC_S_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO ((uint32_t)(MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS)) /**< Value Shifted: SYSTEM_SOURCE_SELECT_96MHZ_RO */ |
AnnaBridge | 171:3a7713b1edbc | 447 | /**@} end of clkman_sysclock_select group */ |
AnnaBridge | 171:3a7713b1edbc | 448 | ///@cond |
AnnaBridge | 171:3a7713b1edbc | 449 | |
AnnaBridge | 171:3a7713b1edbc | 450 | #define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 ((uint32_t)(0x00000000UL)) |
AnnaBridge | 171:3a7713b1edbc | 451 | #define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(0x00000001UL)) |
AnnaBridge | 171:3a7713b1edbc | 452 | #define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(0x00000002UL)) |
AnnaBridge | 171:3a7713b1edbc | 453 | #define MXC_V_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(0x00000003UL)) |
AnnaBridge | 171:3a7713b1edbc | 454 | #define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT0 << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS)) |
AnnaBridge | 171:3a7713b1edbc | 455 | #define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS)) |
AnnaBridge | 171:3a7713b1edbc | 456 | #define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_96MHZ_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS)) |
AnnaBridge | 171:3a7713b1edbc | 457 | #define MXC_S_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT0_CLOCK_SELECT_NANO_RING_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT0_CLOCK_SELECT_POS)) |
AnnaBridge | 171:3a7713b1edbc | 458 | #define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 ((uint32_t)(0x00000000UL)) |
AnnaBridge | 171:3a7713b1edbc | 459 | #define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(0x00000001UL)) |
AnnaBridge | 171:3a7713b1edbc | 460 | #define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(0x00000002UL)) |
AnnaBridge | 171:3a7713b1edbc | 461 | #define MXC_V_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(0x00000003UL)) |
AnnaBridge | 171:3a7713b1edbc | 462 | #define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_SCALED_SYS_CLK_CTRL_4_WDT1 << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS)) |
AnnaBridge | 171:3a7713b1edbc | 463 | #define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_32KHZ_RTC_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS)) |
AnnaBridge | 171:3a7713b1edbc | 464 | #define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_96MHZ_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS)) |
AnnaBridge | 171:3a7713b1edbc | 465 | #define MXC_S_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR ((uint32_t)(MXC_V_CLKMAN_WDT1_CLOCK_SELECT_NANO_RING_OSCILLATOR << MXC_F_CLKMAN_CLK_CTRL_WDT1_CLOCK_SELECT_POS)) |
AnnaBridge | 171:3a7713b1edbc | 466 | #define MXC_V_CLKMAN_CLK_SCALE_DISABLED ((uint32_t)(0x00000000UL)) |
AnnaBridge | 171:3a7713b1edbc | 467 | #define MXC_V_CLKMAN_CLK_SCALE_DIV_1 ((uint32_t)(0x00000001UL)) |
AnnaBridge | 171:3a7713b1edbc | 468 | #define MXC_V_CLKMAN_CLK_SCALE_DIV_2 ((uint32_t)(0x00000002UL)) |
AnnaBridge | 171:3a7713b1edbc | 469 | #define MXC_V_CLKMAN_CLK_SCALE_DIV_4 ((uint32_t)(0x00000003UL)) |
AnnaBridge | 171:3a7713b1edbc | 470 | #define MXC_V_CLKMAN_CLK_SCALE_DIV_8 ((uint32_t)(0x00000004UL)) |
AnnaBridge | 171:3a7713b1edbc | 471 | #define MXC_V_CLKMAN_CLK_SCALE_DIV_16 ((uint32_t)(0x00000005UL)) |
AnnaBridge | 171:3a7713b1edbc | 472 | #define MXC_V_CLKMAN_CLK_SCALE_DIV_32 ((uint32_t)(0x00000006UL)) |
AnnaBridge | 171:3a7713b1edbc | 473 | #define MXC_V_CLKMAN_CLK_SCALE_DIV_64 ((uint32_t)(0x00000007UL)) |
AnnaBridge | 171:3a7713b1edbc | 474 | #define MXC_V_CLKMAN_CLK_SCALE_DIV_128 ((uint32_t)(0x00000008UL)) |
AnnaBridge | 171:3a7713b1edbc | 475 | #define MXC_V_CLKMAN_CLK_SCALE_DIV_256 ((uint32_t)(0x00000009UL)) |
AnnaBridge | 171:3a7713b1edbc | 476 | #define MXC_S_CLKMAN_CLK_SCALE_DISABLED ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DISABLED << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) |
AnnaBridge | 171:3a7713b1edbc | 477 | #define MXC_S_CLKMAN_CLK_SCALE_DIV_1 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_1 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) |
AnnaBridge | 171:3a7713b1edbc | 478 | #define MXC_S_CLKMAN_CLK_SCALE_DIV_2 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_2 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) |
AnnaBridge | 171:3a7713b1edbc | 479 | #define MXC_S_CLKMAN_CLK_SCALE_DIV_4 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_4 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) |
AnnaBridge | 171:3a7713b1edbc | 480 | #define MXC_S_CLKMAN_CLK_SCALE_DIV_8 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_8 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) |
AnnaBridge | 171:3a7713b1edbc | 481 | #define MXC_S_CLKMAN_CLK_SCALE_DIV_16 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_16 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) |
AnnaBridge | 171:3a7713b1edbc | 482 | #define MXC_S_CLKMAN_CLK_SCALE_DIV_32 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_32 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) |
AnnaBridge | 171:3a7713b1edbc | 483 | #define MXC_S_CLKMAN_CLK_SCALE_DIV_64 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_64 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) |
AnnaBridge | 171:3a7713b1edbc | 484 | #define MXC_S_CLKMAN_CLK_SCALE_DIV_128 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_128 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) |
AnnaBridge | 171:3a7713b1edbc | 485 | #define MXC_S_CLKMAN_CLK_SCALE_DIV_256 ((uint32_t)(MXC_V_CLKMAN_CLK_SCALE_DIV_256 << MXC_F_CLKMAN_SYS_CLK_CTRL_0_CM4_CM4_CLK_SCALE_POS)) |
AnnaBridge | 171:3a7713b1edbc | 486 | ///@endcond |
AnnaBridge | 171:3a7713b1edbc | 487 | |
AnnaBridge | 171:3a7713b1edbc | 488 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 489 | } |
AnnaBridge | 171:3a7713b1edbc | 490 | #endif |
AnnaBridge | 171:3a7713b1edbc | 491 | |
AnnaBridge | 171:3a7713b1edbc | 492 | #endif /* _MXC_CLKMAN_REGS_H_ */ |
AnnaBridge | 171:3a7713b1edbc | 493 |